2 * Copyright (c) 2016, Freescale Semiconductor, Inc.
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3 * Copyright 2016, NXP
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4 * All rights reserved.
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7 * SPDX-License-Identifier: BSD-3-Clause
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9 #ifndef _FSL_POWER_H_
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10 #define _FSL_POWER_H_
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12 #include "fsl_common.h"
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14 /*! @addtogroup power */
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19 /*******************************************************************************
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21 ******************************************************************************/
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23 /*! @name Driver version */
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25 /*! @brief power driver version 2.0.0. */
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26 #define FSL_POWER_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
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29 #define MAKE_PD_BITS(reg, slot) ((reg << 8) | slot)
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30 #define PDRCFG0 0x0U
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31 #define PDRCFG1 0x1U
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33 typedef enum pd_bits
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35 kPDRUNCFG_PD_FRO_EN = MAKE_PD_BITS(PDRCFG0, 4U),
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36 kPDRUNCFG_PD_FLASH = MAKE_PD_BITS(PDRCFG0, 5U),
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37 kPDRUNCFG_PD_TEMPS = MAKE_PD_BITS(PDRCFG0, 6U),
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38 kPDRUNCFG_PD_BOD_RESET = MAKE_PD_BITS(PDRCFG0, 7U),
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39 kPDRUNCFG_PD_BOD_INTR = MAKE_PD_BITS(PDRCFG0, 8U),
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40 kPDRUNCFG_PD_ADC0 = MAKE_PD_BITS(PDRCFG0, 10U),
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41 kPDRUNCFG_PD_VDDFLASH = MAKE_PD_BITS(PDRCFG0, 11U),
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42 kPDRUNCFG_LP_VDDFLASH = MAKE_PD_BITS(PDRCFG0, 12U),
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43 kPDRUNCFG_PD_RAM0 = MAKE_PD_BITS(PDRCFG0, 13U),
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44 kPDRUNCFG_PD_RAM1 = MAKE_PD_BITS(PDRCFG0, 14U),
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45 kPDRUNCFG_PD_RAM2 = MAKE_PD_BITS(PDRCFG0, 15U),
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46 kPDRUNCFG_PD_RAMX = MAKE_PD_BITS(PDRCFG0, 16U),
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47 kPDRUNCFG_PD_ROM = MAKE_PD_BITS(PDRCFG0, 17U),
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48 kPDRUNCFG_PD_VDDHV_ENA = MAKE_PD_BITS(PDRCFG0, 18U),
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49 kPDRUNCFG_PD_VD7_ENA = MAKE_PD_BITS(PDRCFG0, 19U),
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50 kPDRUNCFG_PD_WDT_OSC = MAKE_PD_BITS(PDRCFG0, 20U),
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51 kPDRUNCFG_PD_USB0_PHY = MAKE_PD_BITS(PDRCFG0, 21U),
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52 kPDRUNCFG_PD_SYS_PLL0 = MAKE_PD_BITS(PDRCFG0, 22U),
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53 kPDRUNCFG_PD_VREFP_SW = MAKE_PD_BITS(PDRCFG0, 23U),
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54 kPDRUNCFG_PD_FLASH_BG = MAKE_PD_BITS(PDRCFG0, 25U),
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56 kPDRUNCFG_PD_ALT_FLASH_IBG = MAKE_PD_BITS(PDRCFG1, 28U),
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57 kPDRUNCFG_SEL_ALT_FLASH_IBG = MAKE_PD_BITS(PDRCFG1, 29U),
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59 kPDRUNCFG_ForceUnsigned = (int)0x80000000U
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62 /* Power mode configuration API parameter */
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63 typedef enum _power_mode_config
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66 kPmu_Deep_Sleep = 1U,
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67 kPmu_Deep_PowerDown = 2U,
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70 /*******************************************************************************
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72 ******************************************************************************/
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79 * @name Power Configuration
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84 * @brief API to enable PDRUNCFG bit in the Syscon. Note that enabling the bit powers down the peripheral
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86 * @param en peripheral for which to enable the PDRUNCFG bit
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89 static inline void POWER_EnablePD(pd_bit_t en)
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92 SYSCON->PDRUNCFGSET[(en >> 8UL)] = (1UL << (en & 0xffU));
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96 * @brief API to disable PDRUNCFG bit in the Syscon. Note that disabling the bit powers up the peripheral
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98 * @param en peripheral for which to disable the PDRUNCFG bit
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101 static inline void POWER_DisablePD(pd_bit_t en)
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104 SYSCON->PDRUNCFGCLR[(en >> 8UL)] = (1UL << (en & 0xffU));
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108 * @brief API to enable deep sleep bit in the ARM Core.
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112 static inline void POWER_EnableDeepSleep(void)
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114 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
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118 * @brief API to disable deep sleep bit in the ARM Core.
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122 static inline void POWER_DisableDeepSleep(void)
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124 SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
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128 * @brief API to power down flash controller.
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132 static inline void POWER_PowerDownFlash(void)
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134 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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135 /* TURN OFF clock for Flash Controller (only needed for FLASH programming, will be turned on by ROM API) */
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136 CLOCK_DisableClock(kCLOCK_Flash);
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138 /* TURN OFF clock for Flash Accelerator */
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139 CLOCK_DisableClock(kCLOCK_Fmc);
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140 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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144 * @brief API to power up flash controller.
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148 static inline void POWER_PowerUpFlash(void)
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150 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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151 /* TURN ON clock for flash Accelerator */
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152 CLOCK_EnableClock(kCLOCK_Fmc);
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154 /* TURN ON clock for flash Controller */
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155 CLOCK_EnableClock(kCLOCK_Flash);
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156 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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160 * @brief Power Library API to enter different power mode.
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162 * @param exclude_from_pd Bit mask of the PDRUNCFG bits that needs to be powered on during deep sleep
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165 void POWER_EnterPowerMode(power_mode_cfg_t mode, uint64_t exclude_from_pd);
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168 * @brief Power Library API to enter sleep mode.
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172 void POWER_EnterSleep(void);
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175 * @brief Power Library API to enter deep sleep mode.
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177 * @param exclude_from_pd Bit mask of the PDRUNCFG bits that needs to be powered on during deep sleep
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180 void POWER_EnterDeepSleep(uint64_t exclude_from_pd);
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183 * @brief Power Library API to enter deep power down mode.
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185 * @param exclude_from_pd Bit mask of the PDRUNCFG bits that needs to be powered on during deep power down mode,
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186 * but this is has no effect as the voltages are cut off.
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189 void POWER_EnterDeepPowerDown(uint64_t exclude_from_pd);
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192 * @brief Power Library API to choose normal regulation and set the voltage for the desired operating frequency.
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194 * @param freq - The desired frequency at which the part would like to operate,
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195 * note that the voltage and flash wait states should be set before changing frequency
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198 void POWER_SetVoltageForFreq(uint32_t freq);
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201 * @brief Power Library API to choose low power regulation and set the voltage for the desired operating frequency.
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203 * @param freq - The desired frequency at which the part would like to operate,
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204 * note only 12MHz and 48Mhz are supported
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207 void POWER_SetLowPowerVoltageForFreq(uint32_t freq);
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210 * @brief Power Library API to return the library version.
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212 * @return version number of the power library
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214 uint32_t POWER_GetLibVersion(void);
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224 #endif /* _FSL_POWER_H_ */
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