2 * Copyright (c) 2016, Freescale Semiconductor, Inc.
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3 * Copyright 2016, NXP
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4 * All rights reserved.
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7 * SPDX-License-Identifier: BSD-3-Clause
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10 #include "fsl_common.h"
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11 #include "fsl_reset.h"
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13 /*******************************************************************************
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15 ******************************************************************************/
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16 /* Component ID definition, used by tools. */
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17 #ifndef FSL_COMPONENT_ID
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18 #define FSL_COMPONENT_ID "platform.drivers.reset"
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21 /*******************************************************************************
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23 ******************************************************************************/
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25 /*******************************************************************************
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27 ******************************************************************************/
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29 /*******************************************************************************
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31 ******************************************************************************/
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33 #if ((defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) || \
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34 (defined(FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT) && (FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT > 0)))
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37 * brief Assert reset to peripheral.
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39 * Asserts reset signal to specified peripheral module.
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41 * param peripheral Assert reset to this peripheral. The enum argument contains encoding of reset register
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42 * and reset bit position in the reset register.
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44 void RESET_SetPeripheralReset(reset_ip_name_t peripheral)
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46 const uint32_t regIndex = ((uint32_t)peripheral & 0xFFFF0000u) >> 16;
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47 const uint32_t bitPos = ((uint32_t)peripheral & 0x0000FFFFu);
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48 const uint32_t bitMask = 1u << bitPos;
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50 assert(bitPos < 32u);
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52 /* ASYNC_SYSCON registers have offset 1024 */
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53 if (regIndex >= SYSCON_PRESETCTRL_COUNT)
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55 /* reset register is in ASYNC_SYSCON */
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58 ASYNC_SYSCON->ASYNCPRESETCTRLSET = bitMask;
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59 /* wait until it reads 0b1 */
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60 while (0u == (ASYNC_SYSCON->ASYNCPRESETCTRL & bitMask))
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66 /* reset register is in SYSCON */
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69 SYSCON->PRESETCTRLSET[regIndex] = bitMask;
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70 /* wait until it reads 0b1 */
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71 while (0u == (SYSCON->PRESETCTRL[regIndex] & bitMask))
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78 * brief Clear reset to peripheral.
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80 * Clears reset signal to specified peripheral module, allows it to operate.
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82 * param peripheral Clear reset to this peripheral. The enum argument contains encoding of reset register
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83 * and reset bit position in the reset register.
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85 void RESET_ClearPeripheralReset(reset_ip_name_t peripheral)
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87 const uint32_t regIndex = ((uint32_t)peripheral & 0xFFFF0000u) >> 16;
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88 const uint32_t bitPos = ((uint32_t)peripheral & 0x0000FFFFu);
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89 const uint32_t bitMask = 1u << bitPos;
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91 assert(bitPos < 32u);
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93 /* ASYNC_SYSCON registers have offset 1024 */
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94 if (regIndex >= SYSCON_PRESETCTRL_COUNT)
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96 /* reset register is in ASYNC_SYSCON */
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99 ASYNC_SYSCON->ASYNCPRESETCTRLCLR = bitMask;
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100 /* wait until it reads 0b0 */
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101 while (bitMask == (ASYNC_SYSCON->ASYNCPRESETCTRL & bitMask))
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107 /* reset register is in SYSCON */
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110 SYSCON->PRESETCTRLCLR[regIndex] = bitMask;
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111 /* wait until it reads 0b0 */
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112 while (bitMask == (SYSCON->PRESETCTRL[regIndex] & bitMask))
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119 * brief Reset peripheral module.
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121 * Reset peripheral module.
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123 * param peripheral Peripheral to reset. The enum argument contains encoding of reset register
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124 * and reset bit position in the reset register.
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126 void RESET_PeripheralReset(reset_ip_name_t peripheral)
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128 RESET_SetPeripheralReset(peripheral);
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129 RESET_ClearPeripheralReset(peripheral);
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132 #endif /* FSL_FEATURE_SOC_SYSCON_COUNT || FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT */
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