2 ** ###################################################################
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3 ** Processors: LPC51U68JBD48
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6 ** Compilers: Keil ARM C/C++ Compiler
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8 ** IAR ANSI C/C++ Compiler for ARM
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9 ** MCUXpresso Compiler
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11 ** Reference manual: LPC51U68 User manual User manual Rev. 1.0 13 Dec 2017
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12 ** Version: rev. 1.0, 2017-12-15
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16 ** Provides a system configuration function and a global variable that
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17 ** contains the system frequency. It configures the device and initializes
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18 ** the oscillator (PLL) that is part of the microcontroller device.
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20 ** Copyright 2016 Freescale Semiconductor, Inc.
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21 ** Copyright 2016-2018 NXP
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23 ** SPDX-License-Identifier: BSD-3-Clause
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25 ** http: www.nxp.com
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26 ** mail: support@nxp.com
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29 ** - rev. 1.0 (2017-12-15)
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32 ** ###################################################################
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39 * @brief Device specific configuration file for LPC51U68 (implementation file)
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41 * Provides a system configuration function and a global variable that contains
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42 * the system frequency. It configures the device and initializes the oscillator
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43 * (PLL) that is part of the microcontroller device.
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47 #include "fsl_device_registers.h"
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49 #define NVALMAX (0x100)
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50 #define PVALMAX (0x20)
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51 #define MVALMAX (0x8000)
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52 #define PLL_SSCG0_MDEC_VAL_P (0) /* MDEC is in bits 16 downto 0 */
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53 #define PLL_SSCG0_MDEC_VAL_M (0x1FFFFUL << PLL_SSCG0_MDEC_VAL_P) /* NDEC is in bits 9 downto 0 */
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54 #define PLL_NDEC_VAL_P (0) /* NDEC is in bits 9:0 */
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55 #define PLL_NDEC_VAL_M (0x3FFUL << PLL_NDEC_VAL_P)
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56 #define PLL_PDEC_VAL_P (0) /* PDEC is in bits 6:0 */
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57 #define PLL_PDEC_VAL_M (0x3FFUL << PLL_PDEC_VAL_P)
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59 extern void *__Vectors;
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61 /* ----------------------------------------------------------------------------
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63 ---------------------------------------------------------------------------- */
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66 static const uint8_t wdtFreqLookup[32] = {0, 8, 12, 15, 18, 20, 24, 26, 28, 30, 32, 34, 36, 38, 40, 41, 42, 44, 45, 46,
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67 48, 49, 50, 52, 53, 54, 56, 57, 58, 59, 60, 61};
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69 static uint32_t GetWdtOscFreq(void)
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71 uint8_t freq_sel, div_sel;
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72 div_sel = ((SYSCON->WDTOSCCTRL & SYSCON_WDTOSCCTRL_DIVSEL_MASK) + 1) << 1;
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73 freq_sel = wdtFreqLookup[((SYSCON->WDTOSCCTRL & SYSCON_WDTOSCCTRL_FREQSEL_MASK) >> SYSCON_WDTOSCCTRL_FREQSEL_SHIFT)];
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74 return ((uint32_t) freq_sel * 50000U)/((uint32_t)div_sel);
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77 /* Find decoded N value for raw NDEC value */
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78 static uint32_t pllDecodeN(uint32_t NDEC)
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97 for (i = NVALMAX; ((i >= 3) && (n == 0xFFFFFFFF)); i--)
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99 x = (((x ^ (x >> 2) ^ (x >> 3) ^ (x >> 4)) & 1) << 7) | ((x >> 1) & 0x7F);
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100 if ((x & (PLL_NDEC_VAL_M >> PLL_NDEC_VAL_P)) == NDEC)
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102 /* Decoded value of NDEC */
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111 /* Find decoded P value for raw PDEC value */
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112 static uint32_t pllDecodeP(uint32_t PDEC)
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130 for (i = PVALMAX; ((i >= 3) && (p == 0xFFFFFFFF)); i--)
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132 x = (((x ^ (x >> 2)) & 1) << 4) | ((x >> 1) & 0xF);
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133 if ((x & (PLL_PDEC_VAL_M >> PLL_PDEC_VAL_P)) == PDEC)
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135 /* Decoded value of PDEC */
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144 /* Find decoded M value for raw MDEC value */
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145 static uint32_t pllDecodeM(uint32_t MDEC)
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164 for (i = MVALMAX; ((i >= 3) && (m == 0xFFFFFFFF)); i--)
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166 x = (((x ^ (x >> 1)) & 1) << 14) | ((x >> 1) & 0x3FFF);
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167 if ((x & (PLL_SSCG0_MDEC_VAL_M >> PLL_SSCG0_MDEC_VAL_P)) == MDEC)
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169 /* Decoded value of MDEC */
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178 /* Get predivider (N) from PLL NDEC setting */
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179 static uint32_t findPllPreDiv(uint32_t ctrlReg, uint32_t nDecReg)
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181 uint32_t preDiv = 1;
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183 /* Direct input is not used? */
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184 if ((ctrlReg & SYSCON_SYSPLLCTRL_DIRECTI_MASK) == 0)
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186 /* Decode NDEC value to get (N) pre divider */
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187 preDiv = pllDecodeN(nDecReg & 0x3FF);
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193 /* Adjusted by 1, directi is used to bypass */
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197 /* Get postdivider (P) from PLL PDEC setting */
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198 static uint32_t findPllPostDiv(uint32_t ctrlReg, uint32_t pDecReg)
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200 uint32_t postDiv = 1;
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202 /* Direct input is not used? */
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203 if ((ctrlReg & SYSCON_SYSPLLCTRL_DIRECTO_MASK) == 0)
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205 /* Decode PDEC value to get (P) post divider */
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206 postDiv = 2 * pllDecodeP(pDecReg & 0x7F);
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212 /* Adjusted by 1, directo is used to bypass */
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216 /* Get multiplier (M) from PLL MDEC and BYPASS_FBDIV2 settings */
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217 static uint32_t findPllMMult(uint32_t ctrlReg, uint32_t mDecReg)
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219 uint32_t mMult = 1;
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221 /* Decode MDEC value to get (M) multiplier */
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222 mMult = pllDecodeM(mDecReg & 0x1FFFF);
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223 /* Extra multiply by 2 needed? */
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224 if ((ctrlReg & SYSCON_SYSPLLCTRL_BYPASSCCODIV2_MASK) == 0)
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226 mMult = mMult << 1;
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237 /* ----------------------------------------------------------------------------
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239 ---------------------------------------------------------------------------- */
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241 uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
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243 /* ----------------------------------------------------------------------------
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245 ---------------------------------------------------------------------------- */
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247 void SystemInit (void) {
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249 #if defined(__CODE_RED)
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250 extern void(*const g_pfnVectors[]) (void);
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251 SCB->VTOR = (uint32_t) &g_pfnVectors;
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253 extern void *__Vectors;
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254 SCB->VTOR = (uint32_t) &__Vectors;
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259 /* ----------------------------------------------------------------------------
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260 -- SystemCoreClockUpdate()
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261 ---------------------------------------------------------------------------- */
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263 void SystemCoreClockUpdate (void) {
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264 uint32_t clkRate = 0;
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265 uint32_t prediv, postdiv;
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268 switch (SYSCON->MAINCLKSELB & SYSCON_MAINCLKSELB_SEL_MASK)
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270 case 0x00: /* MAINCLKSELA clock (main_clk_a)*/
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271 switch (SYSCON->MAINCLKSELA & SYSCON_MAINCLKSELA_SEL_MASK)
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273 case 0x00: /* FRO 12 MHz (fro_12m) */
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274 clkRate = CLK_FRO_12MHZ;
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276 case 0x01: /* CLKIN (clk_in) */
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277 clkRate = CLK_CLK_IN;
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279 case 0x02: /* Watchdog oscillator (wdt_clk) */
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280 clkRate = GetWdtOscFreq();
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282 default: /* = 0x03 = FRO 96 or 48 MHz (fro_hf) */
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283 if (SYSCON->FROCTRL & SYSCON_FROCTRL_SEL_MASK)
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285 clkRate = CLK_FRO_96MHZ;
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289 clkRate = CLK_FRO_48MHZ;
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294 case 0x02: /* System PLL clock (pll_clk)*/
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295 switch (SYSCON->SYSPLLCLKSEL & SYSCON_SYSPLLCLKSEL_SEL_MASK)
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297 case 0x00: /* FRO 12 MHz (fro_12m) */
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298 clkRate = CLK_FRO_12MHZ;
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300 case 0x01: /* CLKIN (clk_in) */
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301 clkRate = CLK_CLK_IN;
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303 case 0x02: /* Watchdog oscillator (wdt_clk) */
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304 clkRate = GetWdtOscFreq();
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306 case 0x03: /* RTC oscillator 32 kHz output (32k_clk) */
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307 clkRate = CLK_RTC_32K_CLK;
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312 if ((SYSCON->SYSPLLCTRL & SYSCON_SYSPLLCTRL_BYPASS_MASK) == 0)
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314 /* PLL is not in bypass mode, get pre-divider, post-divider, and M divider */
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315 prediv = findPllPreDiv(SYSCON->SYSPLLCTRL, SYSCON->SYSPLLNDEC);
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316 postdiv = findPllPostDiv(SYSCON->SYSPLLCTRL, SYSCON->SYSPLLPDEC);
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317 /* Adjust input clock */
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318 clkRate = clkRate / prediv;
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319 /* If using the SS, use the multiplier */
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320 if (SYSCON->SYSPLLSSCTRL1 & SYSCON_SYSPLLSSCTRL1_PD_MASK)
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322 /* MDEC used for rate */
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323 workRate = (uint64_t)clkRate * (uint64_t)findPllMMult(SYSCON->SYSPLLCTRL, SYSCON->SYSPLLSSCTRL0);
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327 /* SS multipler used for rate */
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329 /* Adjust by fractional */
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330 workRate = workRate + ((clkRate * (uint64_t)((SYSCON->SYSPLLSSCTRL1 & 0x7FF) >> 0)) / 0x800);
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332 clkRate = workRate / ((uint64_t)postdiv);
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335 case 0x03: /* RTC oscillator 32 kHz output (32k_clk) */
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336 clkRate = CLK_RTC_32K_CLK;
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341 SystemCoreClock = clkRate / ((SYSCON->AHBCLKDIV & 0xFF) + 1);
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