2 * Copyright (c) 2016, Freescale Semiconductor, Inc.
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3 * Copyright 2016-2017 NXP
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4 * All rights reserved.
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6 * SPDX-License-Identifier: BSD-3-Clause
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9 #include "fsl_pint.h"
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11 /* Component ID definition, used by tools. */
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12 #ifndef FSL_COMPONENT_ID
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13 #define FSL_COMPONENT_ID "platform.drivers.pint"
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16 /*******************************************************************************
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18 ******************************************************************************/
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20 #if defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS)
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21 /*! @brief Irq number array */
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22 static const IRQn_Type s_pintIRQ[FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS +
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23 FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS] = PINT_IRQS;
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25 /*! @brief Callback function array for PINT(s). */
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27 s_pintCallback[FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS + FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS];
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29 /*! @brief Irq number array */
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30 static const IRQn_Type s_pintIRQ[FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS] = PINT_IRQS;
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32 /*! @brief Callback function array for PINT(s). */
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33 static pint_cb_t s_pintCallback[FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS];
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34 #endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */
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36 /*******************************************************************************
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38 ******************************************************************************/
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41 * brief Initialize PINT peripheral.
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43 * This function initializes the PINT peripheral and enables the clock.
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45 * param base Base address of the PINT peripheral.
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49 void PINT_Init(PINT_Type *base)
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57 #if defined(SECPINT)
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58 pintcount = SEC_PINT_PIN_INT_COUNT;
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60 pintcount = PINT_PIN_INT_COUNT;
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61 #endif /* SECPINT */
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63 for (i = 0; i < FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; i++)
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65 s_pintCallback[i] = NULL;
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68 /* Disable all bit slices for pint*/
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69 for (i = 0; i < pintcount; i++)
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71 pmcfg = pmcfg | (kPINT_PatternMatchNever << (PININT_BITSLICE_CFG_START + (i * 3U)));
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74 #if defined(FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE) && (FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE == 1)
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75 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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76 /* Enable the clock. */
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77 CLOCK_EnableClock(kCLOCK_GpioInt);
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78 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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80 #if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL)
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81 /* Reset the module. */
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82 RESET_PeripheralReset(kGPIOINT_RST_N_SHIFT_RSTn);
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83 #endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */
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85 #elif defined(FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE) && (FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE == 0)
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86 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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87 /* Enable the clock. */
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88 CLOCK_EnableClock(kCLOCK_Gpio0);
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89 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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91 #if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL)
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92 /* Reset the module. */
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93 RESET_PeripheralReset(kGPIO0_RST_N_SHIFT_RSTn);
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94 #endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */
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96 #if defined(SECPINT)
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97 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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98 /* Enable the clock. */
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99 CLOCK_EnableClock(kCLOCK_Gpio_Sec);
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100 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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102 #if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL)
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103 /* Reset the module. */
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104 RESET_PeripheralReset(kGPIOSEC_RST_SHIFT_RSTn);
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105 #endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */
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106 #endif /* SECPINT */
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108 /* if need config SECURE PINT device,then enable secure pint interrupt clock */
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111 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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112 /* Enable the clock. */
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113 CLOCK_EnableClock(kCLOCK_Pint);
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114 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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116 #if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL)
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117 /* Reset the module. */
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118 RESET_PeripheralReset(kPINT_RST_SHIFT_RSTn);
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119 #endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */
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121 #if defined(SECPINT)
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122 else if (base == SECPINT)
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124 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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125 /* Enable the clock. */
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126 CLOCK_EnableClock(kCLOCK_Gpio_sec_Int);
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127 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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129 #if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL)
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130 /* Reset the module. */
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131 RESET_PeripheralReset(kGPIOSECINT_RST_SHIFT_RSTn);
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132 #endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */
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134 #endif /* SECPINT */
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135 #endif /* FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE */
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137 /* Disable all pattern match bit slices */
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138 base->PMCFG = pmcfg;
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142 * brief Configure PINT peripheral pin interrupt.
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144 * This function configures a given pin interrupt.
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146 * param base Base address of the PINT peripheral.
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147 * param intr Pin interrupt.
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148 * param enable Selects detection logic.
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149 * param callback Callback.
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153 void PINT_PinInterruptConfig(PINT_Type *base, pint_pin_int_t intr, pint_pin_enable_t enable, pint_cb_t callback)
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157 /* Clear Rise and Fall flags first */
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158 PINT_PinInterruptClrRiseFlag(base, intr);
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159 PINT_PinInterruptClrFallFlag(base, intr);
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161 /* select level or edge sensitive */
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163 (base->ISEL & ~(1UL << (uint32_t)intr)) | ((enable & PINT_PIN_INT_LEVEL) ? (1UL << (uint32_t)intr) : 0U);
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165 /* enable rising or level interrupt */
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166 if (enable & (PINT_PIN_INT_LEVEL | PINT_PIN_INT_RISE))
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168 base->SIENR = 1UL << (uint32_t)intr;
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172 base->CIENR = 1UL << (uint32_t)intr;
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175 /* Enable falling or select high level */
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176 if (enable & PINT_PIN_INT_FALL_OR_HIGH_LEVEL)
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178 base->SIENF = 1UL << (uint32_t)intr;
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182 base->CIENF = 1UL << (uint32_t)intr;
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185 s_pintCallback[intr] = callback;
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189 * brief Get PINT peripheral pin interrupt configuration.
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191 * This function returns the configuration of a given pin interrupt.
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193 * param base Base address of the PINT peripheral.
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194 * param pintr Pin interrupt.
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195 * param enable Pointer to store the detection logic.
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196 * param callback Callback.
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200 void PINT_PinInterruptGetConfig(PINT_Type *base, pint_pin_int_t pintr, pint_pin_enable_t *enable, pint_cb_t *callback)
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207 *enable = kPINT_PinIntEnableNone;
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210 mask = 1UL << (uint32_t)pintr;
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211 if ((base->ISEL & mask) != 0U)
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213 /* Pin interrupt is level sensitive */
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217 if ((base->IENR & mask) != 0U)
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221 /* Level interrupt is enabled */
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222 *enable = kPINT_PinIntEnableLowLevel;
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226 /* Rising edge interrupt */
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227 *enable = kPINT_PinIntEnableRiseEdge;
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231 if ((base->IENF & mask) != 0U)
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235 /* Level interrupt is active high */
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236 *enable = kPINT_PinIntEnableHighLevel;
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240 /* Either falling or both edge */
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241 if (*enable == kPINT_PinIntEnableRiseEdge)
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243 /* Rising and faling edge */
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244 *enable = kPINT_PinIntEnableBothEdges;
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249 *enable = kPINT_PinIntEnableFallEdge;
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254 *callback = s_pintCallback[pintr];
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258 * brief Configure PINT pattern match.
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260 * This function configures a given pattern match bit slice.
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262 * param base Base address of the PINT peripheral.
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263 * param bslice Pattern match bit slice number.
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264 * param cfg Pointer to bit slice configuration.
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268 void PINT_PatternMatchConfig(PINT_Type *base, pint_pmatch_bslice_t bslice, pint_pmatch_cfg_t *cfg)
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270 uint32_t src_shift;
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271 uint32_t cfg_shift;
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273 uint32_t tmp_src_shift = PININT_BITSLICE_SRC_MASK;
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274 uint32_t tmp_cfg_shift = PININT_BITSLICE_CFG_MASK;
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278 src_shift = PININT_BITSLICE_SRC_START + ((uint32_t)bslice * 3UL);
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279 cfg_shift = PININT_BITSLICE_CFG_START + ((uint32_t)bslice * 3UL);
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281 /* Input source selection for selected bit slice */
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282 base->PMSRC = (base->PMSRC & ~(tmp_src_shift << src_shift)) | (cfg->bs_src << src_shift);
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284 /* Bit slice configuration */
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285 pmcfg = base->PMCFG;
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286 pmcfg = (pmcfg & ~(tmp_cfg_shift << cfg_shift)) | (cfg->bs_cfg << cfg_shift);
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288 /* If end point is true, enable the bits */
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289 if ((uint32_t)bslice != 7UL)
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291 if (cfg->end_point)
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293 pmcfg |= (1UL << (uint32_t)bslice);
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297 pmcfg &= ~(1UL << (uint32_t)bslice);
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301 base->PMCFG = pmcfg;
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303 /* Save callback pointer */
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304 s_pintCallback[bslice] = cfg->callback;
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308 * brief Get PINT pattern match configuration.
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310 * This function returns the configuration of a given pattern match bit slice.
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312 * param base Base address of the PINT peripheral.
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313 * param bslice Pattern match bit slice number.
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314 * param cfg Pointer to bit slice configuration.
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318 void PINT_PatternMatchGetConfig(PINT_Type *base, pint_pmatch_bslice_t bslice, pint_pmatch_cfg_t *cfg)
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320 uint32_t src_shift;
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321 uint32_t cfg_shift;
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322 uint32_t tmp_src_shift = PININT_BITSLICE_SRC_MASK;
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323 uint32_t tmp_cfg_shift = PININT_BITSLICE_CFG_MASK;
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327 src_shift = PININT_BITSLICE_SRC_START + ((uint32_t)bslice * 3UL);
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328 cfg_shift = PININT_BITSLICE_CFG_START + ((uint32_t)bslice * 3UL);
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330 cfg->bs_src = (pint_pmatch_input_src_t)((base->PMSRC & (tmp_src_shift << src_shift)) >> src_shift);
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331 cfg->bs_cfg = (pint_pmatch_bslice_cfg_t)((base->PMCFG & (tmp_cfg_shift << cfg_shift)) >> cfg_shift);
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333 if ((uint32_t)bslice == 7U)
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335 cfg->end_point = true;
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339 cfg->end_point = ((base->PMCFG & (1UL << (uint32_t)bslice)) >> (uint32_t)bslice);
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341 cfg->callback = s_pintCallback[bslice];
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345 * brief Reset pattern match detection logic.
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347 * This function resets the pattern match detection logic if any of the product term is matching.
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349 * param base Base address of the PINT peripheral.
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351 * retval pmstatus Each bit position indicates the match status of corresponding bit slice.
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352 * = 0 Match was detected. = 1 Match was not detected.
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354 uint32_t PINT_PatternMatchResetDetectLogic(PINT_Type *base)
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360 pmctrl = base->PMCTRL;
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361 pmstatus = pmctrl >> PINT_PMCTRL_PMAT_SHIFT;
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362 if (pmstatus != 0UL)
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364 /* Reset Pattern match engine detection logic */
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365 pmsrc = base->PMSRC;
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366 base->PMSRC = pmsrc;
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372 * @brief Clear Selected pin interrupt status only when the pin was triggered by edge-sensitive.
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374 * This function clears the selected pin interrupt status.
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376 * @param base Base address of the PINT peripheral.
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377 * @param pintr Pin interrupt.
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381 void PINT_PinInterruptClrStatus(PINT_Type *base, pint_pin_int_t pintr)
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383 uint32_t pinIntMode = base->ISEL & (1UL << (uint32_t)pintr);
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384 uint32_t pinIntStatus = base->IST & (1UL << (uint32_t)pintr);
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386 /* Edge sensitive and pin interrupt that is currently requesting an interrupt. */
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387 if ((pinIntMode == 0x0UL) && (pinIntStatus != 0x0UL))
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389 base->IST = (1UL << (uint32_t)pintr);
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394 * @brief Clear all pin interrupts status only when pins were triggered by edge-sensitive.
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396 * This function clears the status of all pin interrupts.
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398 * @param base Base address of the PINT peripheral.
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402 void PINT_PinInterruptClrStatusAll(PINT_Type *base)
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404 uint32_t pinIntMode = 0;
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405 uint32_t pinIntStatus = 0;
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409 for (i = 0; i < FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; i++)
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411 pinIntMode = base->ISEL & (1UL << i);
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412 pinIntStatus = base->IST & (1UL << i);
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414 /* Edge sensitive and pin interrupt that is currently requesting an interrupt. */
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415 if ((pinIntMode == 0x0UL) && (pinIntStatus != 0x0UL))
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425 * brief Enable callback.
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427 * This function enables the interrupt for the selected PINT peripheral. Although the pin(s) are monitored
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428 * as soon as they are enabled, the callback function is not enabled until this function is called.
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430 * param base Base address of the PINT peripheral.
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434 void PINT_EnableCallback(PINT_Type *base)
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440 for (i = 0; i < FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; i++)
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442 NVIC_ClearPendingIRQ(s_pintIRQ[i]);
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443 PINT_PinInterruptClrStatus(base, (pint_pin_int_t)i);
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444 (void)EnableIRQ(s_pintIRQ[i]);
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449 * brief enable callback by pin index.
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451 * This function enables callback by pin index instead of enabling all pins.
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453 * param base Base address of the peripheral.
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454 * param pinIdx pin index.
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458 void PINT_EnableCallbackByIndex(PINT_Type *base, pint_pin_int_t pintIdx)
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462 NVIC_ClearPendingIRQ(s_pintIRQ[pintIdx]);
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463 PINT_PinInterruptClrStatus(base, (pint_pin_int_t)pintIdx);
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464 (void)EnableIRQ(s_pintIRQ[pintIdx]);
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468 * brief Disable callback.
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470 * This function disables the interrupt for the selected PINT peripheral. Although the pins are still
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471 * being monitored but the callback function is not called.
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473 * param base Base address of the peripheral.
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477 void PINT_DisableCallback(PINT_Type *base)
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483 for (i = 0; i < FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; i++)
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485 (void)DisableIRQ(s_pintIRQ[i]);
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486 PINT_PinInterruptClrStatus(base, (pint_pin_int_t)i);
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487 NVIC_ClearPendingIRQ(s_pintIRQ[i]);
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492 * brief disable callback by pin index.
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494 * This function disables callback by pin index instead of disabling all pins.
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496 * param base Base address of the peripheral.
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497 * param pinIdx pin index.
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501 void PINT_DisableCallbackByIndex(PINT_Type *base, pint_pin_int_t pintIdx)
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505 (void)DisableIRQ(s_pintIRQ[pintIdx]);
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506 PINT_PinInterruptClrStatus(base, (pint_pin_int_t)pintIdx);
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507 NVIC_ClearPendingIRQ(s_pintIRQ[pintIdx]);
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511 * brief Deinitialize PINT peripheral.
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513 * This function disables the PINT clock.
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515 * param base Base address of the PINT peripheral.
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519 void PINT_Deinit(PINT_Type *base)
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526 PINT_DisableCallback(base);
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527 for (i = 0; i < FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; i++)
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529 s_pintCallback[i] = NULL;
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532 #if defined(FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE) && (FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE == 1)
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533 #if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL)
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534 /* Reset the module. */
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535 RESET_PeripheralReset(kGPIOINT_RST_N_SHIFT_RSTn);
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536 #endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */
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538 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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539 /* Disable the clock. */
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540 CLOCK_DisableClock(kCLOCK_GpioInt);
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541 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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543 #elif defined(FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE) && (FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE == 0)
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544 #if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL)
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545 /* Reset the module. */
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546 RESET_PeripheralReset(kGPIO0_RST_N_SHIFT_RSTn);
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547 #endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */
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549 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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550 /* Disable the clock. */
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551 CLOCK_DisableClock(kCLOCK_Gpio0);
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552 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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554 #if defined(SECPINT)
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555 #if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL)
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556 /* Reset the module. */
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557 RESET_PeripheralReset(kGPIOSEC_RST_SHIFT_RSTn);
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558 #endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */
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560 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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561 /* Enable the clock. */
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562 CLOCK_DisableClock(kCLOCK_Gpio_Sec);
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563 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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564 #endif /* SECPINT */
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568 #if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL)
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569 /* Reset the module. */
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570 RESET_PeripheralReset(kPINT_RST_SHIFT_RSTn);
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571 #endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */
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573 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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574 /* Disable the clock. */
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575 CLOCK_DisableClock(kCLOCK_Pint);
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576 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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578 #if defined(SECPINT)
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579 else if (base == SECPINT)
\r
581 #if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL)
\r
582 /* Reset the module. */
\r
583 RESET_PeripheralReset(kGPIOSECINT_RST_SHIFT_RSTn);
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584 #endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */
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586 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
\r
587 /* Disable the clock. */
\r
588 CLOCK_DisableClock(kCLOCK_Gpio_sec_Int);
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589 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
\r
591 #endif /* SECPINT */
\r
592 #endif /* FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE */
\r
594 #if defined(SECPINT)
\r
595 /* IRQ handler functions overloading weak symbols in the startup */
\r
596 void SEC_GPIO_INT0_IRQ0_DriverIRQHandler(void)
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598 uint32_t pmstatus = 0;
\r
600 /* Reset pattern match detection */
\r
601 pmstatus = PINT_PatternMatchResetDetectLogic(SECPINT);
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602 /* Call user function */
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603 if (s_pintCallback[kPINT_SecPinInt0] != NULL)
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605 s_pintCallback[kPINT_SecPinInt0](kPINT_SecPinInt0, pmstatus);
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607 if ((SECPINT->ISEL & 0x1U) == 0x0U)
\r
609 /* Edge sensitive: clear Pin interrupt after callback */
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610 PINT_PinInterruptClrStatus(SECPINT, kPINT_PinInt0);
\r
612 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
\r
613 exception return operation might vector to incorrect interrupt */
\r
614 #if defined __CORTEX_M && (__CORTEX_M == 4U)
\r
619 #if (FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS > 1U)
\r
620 /* IRQ handler functions overloading weak symbols in the startup */
\r
621 void SEC_GPIO_INT0_IRQ1_DriverIRQHandler(void)
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625 /* Reset pattern match detection */
\r
626 pmstatus = PINT_PatternMatchResetDetectLogic(SECPINT);
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627 /* Call user function */
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628 if (s_pintCallback[kPINT_SecPinInt1] != NULL)
\r
630 s_pintCallback[kPINT_SecPinInt1](kPINT_SecPinInt1, pmstatus);
\r
632 if ((SECPINT->ISEL & 0x1U) == 0x0U)
\r
634 /* Edge sensitive: clear Pin interrupt after callback */
\r
635 PINT_PinInterruptClrStatus(SECPINT, kPINT_PinInt1);
\r
637 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
\r
638 exception return operation might vector to incorrect interrupt */
\r
639 #if defined __CORTEX_M && (__CORTEX_M == 4U)
\r
643 #endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */
\r
644 #endif /* SECPINT */
\r
646 /* IRQ handler functions overloading weak symbols in the startup */
\r
647 void PIN_INT0_DriverIRQHandler(void)
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651 /* Reset pattern match detection */
\r
652 pmstatus = PINT_PatternMatchResetDetectLogic(PINT);
\r
653 /* Call user function */
\r
654 if (s_pintCallback[kPINT_PinInt0] != NULL)
\r
656 s_pintCallback[kPINT_PinInt0](kPINT_PinInt0, pmstatus);
\r
658 if ((PINT->ISEL & 0x1U) == 0x0U)
\r
660 /* Edge sensitive: clear Pin interrupt after callback */
\r
661 PINT_PinInterruptClrStatus(PINT, kPINT_PinInt0);
\r
663 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
\r
664 exception return operation might vector to incorrect interrupt */
\r
665 #if defined __CORTEX_M && (__CORTEX_M == 4U)
\r
670 #if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 1U)
\r
671 void PIN_INT1_DriverIRQHandler(void)
\r
675 /* Reset pattern match detection */
\r
676 pmstatus = PINT_PatternMatchResetDetectLogic(PINT);
\r
677 /* Call user function */
\r
678 if (s_pintCallback[kPINT_PinInt1] != NULL)
\r
680 s_pintCallback[kPINT_PinInt1](kPINT_PinInt1, pmstatus);
\r
682 if ((PINT->ISEL & 0x2U) == 0x0U)
\r
684 /* Edge sensitive: clear Pin interrupt after callback */
\r
685 PINT_PinInterruptClrStatus(PINT, kPINT_PinInt1);
\r
687 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
\r
688 exception return operation might vector to incorrect interrupt */
\r
689 #if defined __CORTEX_M && (__CORTEX_M == 4U)
\r
695 #if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 2U)
\r
696 void PIN_INT2_DriverIRQHandler(void)
\r
700 /* Reset pattern match detection */
\r
701 pmstatus = PINT_PatternMatchResetDetectLogic(PINT);
\r
702 /* Call user function */
\r
703 if (s_pintCallback[kPINT_PinInt2] != NULL)
\r
705 s_pintCallback[kPINT_PinInt2](kPINT_PinInt2, pmstatus);
\r
707 if ((PINT->ISEL & 0x4U) == 0x0U)
\r
709 /* Edge sensitive: clear Pin interrupt after callback */
\r
710 PINT_PinInterruptClrStatus(PINT, kPINT_PinInt2);
\r
712 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
\r
713 exception return operation might vector to incorrect interrupt */
\r
714 #if defined __CORTEX_M && (__CORTEX_M == 4U)
\r
720 #if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 3U)
\r
721 void PIN_INT3_DriverIRQHandler(void)
\r
725 /* Reset pattern match detection */
\r
726 pmstatus = PINT_PatternMatchResetDetectLogic(PINT);
\r
727 /* Call user function */
\r
728 if (s_pintCallback[kPINT_PinInt3] != NULL)
\r
730 s_pintCallback[kPINT_PinInt3](kPINT_PinInt3, pmstatus);
\r
732 if ((PINT->ISEL & 0x8U) == 0x0U)
\r
734 /* Edge sensitive: clear Pin interrupt after callback */
\r
735 PINT_PinInterruptClrStatus(PINT, kPINT_PinInt3);
\r
737 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
\r
738 exception return operation might vector to incorrect interrupt */
\r
739 #if defined __CORTEX_M && (__CORTEX_M == 4U)
\r
745 #if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 4U)
\r
746 void PIN_INT4_DriverIRQHandler(void)
\r
750 /* Reset pattern match detection */
\r
751 pmstatus = PINT_PatternMatchResetDetectLogic(PINT);
\r
752 /* Call user function */
\r
753 if (s_pintCallback[kPINT_PinInt4] != NULL)
\r
755 s_pintCallback[kPINT_PinInt4](kPINT_PinInt4, pmstatus);
\r
757 if ((PINT->ISEL & 0x10U) == 0x0U)
\r
759 /* Edge sensitive: clear Pin interrupt after callback */
\r
760 PINT_PinInterruptClrStatus(PINT, kPINT_PinInt4);
\r
762 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
\r
763 exception return operation might vector to incorrect interrupt */
\r
764 #if defined __CORTEX_M && (__CORTEX_M == 4U)
\r
770 #if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 5U)
\r
771 #if defined(FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER) && FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER
\r
772 void PIN_INT5_DAC1_IRQHandler(void)
\r
774 void PIN_INT5_DriverIRQHandler(void)
\r
775 #endif /* FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER */
\r
779 /* Reset pattern match detection */
\r
780 pmstatus = PINT_PatternMatchResetDetectLogic(PINT);
\r
781 /* Call user function */
\r
782 if (s_pintCallback[kPINT_PinInt5] != NULL)
\r
784 s_pintCallback[kPINT_PinInt5](kPINT_PinInt5, pmstatus);
\r
786 if ((PINT->ISEL & 0x20U) == 0x0U)
\r
788 /* Edge sensitive: clear Pin interrupt after callback */
\r
789 PINT_PinInterruptClrStatus(PINT, kPINT_PinInt5);
\r
791 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
\r
792 exception return operation might vector to incorrect interrupt */
\r
793 #if defined __CORTEX_M && (__CORTEX_M == 4U)
\r
799 #if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 6U)
\r
800 #if defined(FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER) && FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER
\r
801 void PIN_INT6_USART3_IRQHandler(void)
\r
803 void PIN_INT6_DriverIRQHandler(void)
\r
804 #endif /* FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER */
\r
808 /* Reset pattern match detection */
\r
809 pmstatus = PINT_PatternMatchResetDetectLogic(PINT);
\r
810 /* Call user function */
\r
811 if (s_pintCallback[kPINT_PinInt6] != NULL)
\r
813 s_pintCallback[kPINT_PinInt6](kPINT_PinInt6, pmstatus);
\r
815 if ((PINT->ISEL & 0x40U) == 0x0U)
\r
817 /* Edge sensitive: clear Pin interrupt after callback */
\r
818 PINT_PinInterruptClrStatus(PINT, kPINT_PinInt6);
\r
820 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
\r
821 exception return operation might vector to incorrect interrupt */
\r
822 #if defined __CORTEX_M && (__CORTEX_M == 4U)
\r
828 #if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 7U)
\r
829 #if defined(FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER) && FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER
\r
830 void PIN_INT7_USART4_IRQHandler(void)
\r
832 void PIN_INT7_DriverIRQHandler(void)
\r
833 #endif /* FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER */
\r
837 /* Reset pattern match detection */
\r
838 pmstatus = PINT_PatternMatchResetDetectLogic(PINT);
\r
839 /* Call user function */
\r
840 if (s_pintCallback[kPINT_PinInt7] != NULL)
\r
842 s_pintCallback[kPINT_PinInt7](kPINT_PinInt7, pmstatus);
\r
844 if ((PINT->ISEL & 0x80U) == 0x0U)
\r
846 /* Edge sensitive: clear Pin interrupt after callback */
\r
847 PINT_PinInterruptClrStatus(PINT, kPINT_PinInt7);
\r
849 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
\r
850 exception return operation might vector to incorrect interrupt */
\r
851 #if defined __CORTEX_M && (__CORTEX_M == 4U)
\r