2 * Copyright (c) 2016, Freescale Semiconductor, Inc.
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3 * Copyright 2016, NXP
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4 * All rights reserved.
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7 * SPDX-License-Identifier: BSD-3-Clause
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10 #ifndef _FSL_RESET_H_
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11 #define _FSL_RESET_H_
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14 #include <stdbool.h>
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17 #include "fsl_device_registers.h"
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20 * @addtogroup ksdk_common
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24 /*******************************************************************************
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26 ******************************************************************************/
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28 /*! @name Driver version */
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30 /*! @brief reset driver version 2.0.1. */
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31 #define FSL_RESET_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
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35 * @brief Enumeration for peripheral reset control bits
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37 * Defines the enumeration for peripheral reset control bits in PRESETCTRL/ASYNCPRESETCTRL registers
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39 typedef enum _SYSCON_RSTn
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41 kFLASH_RST_SHIFT_RSTn = 0 | 7U, /**< Flash controller reset control */
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42 kFMC_RST_SHIFT_RSTn = 0 | 8U, /**< Flash accelerator reset control */
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43 kMUX_RST_SHIFT_RSTn = 0 | 11U, /**< Input mux reset control */
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44 kIOCON_RST_SHIFT_RSTn = 0 | 13U, /**< IOCON reset control */
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45 kGPIO0_RST_SHIFT_RSTn = 0 | 14U, /**< GPIO0 reset control */
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46 kGPIO1_RST_SHIFT_RSTn = 0 | 15U, /**< GPIO1 reset control */
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47 kPINT_RST_SHIFT_RSTn = 0 | 18U, /**< Pin interrupt (PINT) reset control */
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48 kGINT_RST_SHIFT_RSTn = 0 | 19U, /**< Grouped interrupt (PINT) reset control. */
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49 kDMA_RST_SHIFT_RSTn = 0 | 20U, /**< DMA reset control */
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50 kCRC_RST_SHIFT_RSTn = 0 | 21U, /**< CRC reset control */
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51 kWWDT_RST_SHIFT_RSTn = 0 | 22U, /**< Watchdog timer reset control */
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52 kADC0_RST_SHIFT_RSTn = 0 | 27U, /**< ADC0 reset control */
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53 kMRT_RST_SHIFT_RSTn = 65536 | 0U, /**< Multi-rate timer (MRT) reset control */
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54 kSCT0_RST_SHIFT_RSTn = 65536 | 2U, /**< SCTimer/PWM 0 (SCT0) reset control */
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55 kUTICK_RST_SHIFT_RSTn = 65536 | 10U, /**< Micro-tick timer reset control */
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56 kFC0_RST_SHIFT_RSTn = 65536 | 11U, /**< Flexcomm Interface 0 reset control */
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57 kFC1_RST_SHIFT_RSTn = 65536 | 12U, /**< Flexcomm Interface 1 reset control */
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58 kFC2_RST_SHIFT_RSTn = 65536 | 13U, /**< Flexcomm Interface 2 reset control */
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59 kFC3_RST_SHIFT_RSTn = 65536 | 14U, /**< Flexcomm Interface 3 reset control */
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60 kFC4_RST_SHIFT_RSTn = 65536 | 15U, /**< Flexcomm Interface 4 reset control */
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61 kFC5_RST_SHIFT_RSTn = 65536 | 16U, /**< Flexcomm Interface 5 reset control */
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62 kFC6_RST_SHIFT_RSTn = 65536 | 17U, /**< Flexcomm Interface 6 reset control */
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63 kFC7_RST_SHIFT_RSTn = 65536 | 18U, /**< Flexcomm Interface 7 reset control */
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64 kUSB_RST_SHIFT_RSTn = 65536 | 25U, /**< USB reset control */
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65 kCTIMER0_RST_SHIFT_RSTn = 65536 | 26U, /**< CTimer0 reset control */
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66 kCTIMER1_RST_SHIFT_RSTn = 65536 | 27U, /**< CTimer1 reset control */
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67 kCTIMER3_RST_SHIFT_RSTn = 67108864 | 13U, /**< CTimer3 reset control */
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70 /** Array initializers with peripheral reset bits **/
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73 kADC0_RST_SHIFT_RSTn \
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74 } /* Reset bits for ADC peripheral */
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77 kCRC_RST_SHIFT_RSTn \
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78 } /* Reset bits for CRC peripheral */
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79 #define DMA_RSTS_N \
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81 kDMA_RST_SHIFT_RSTn \
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82 } /* Reset bits for DMA peripheral */
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83 #define FLEXCOMM_RSTS \
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85 kFC0_RST_SHIFT_RSTn, kFC1_RST_SHIFT_RSTn, kFC2_RST_SHIFT_RSTn, kFC3_RST_SHIFT_RSTn, kFC4_RST_SHIFT_RSTn, \
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86 kFC5_RST_SHIFT_RSTn, kFC6_RST_SHIFT_RSTn, kFC7_RST_SHIFT_RSTn \
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87 } /* Reset bits for FLEXCOMM peripheral */
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90 kGINT_RST_SHIFT_RSTn, kGINT_RST_SHIFT_RSTn \
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91 } /* Reset bits for GINT peripheral. GINT0 & GINT1 share same slot */
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92 #define GPIO_RSTS_N \
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94 kGPIO0_RST_SHIFT_RSTn, kGPIO1_RST_SHIFT_RSTn \
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95 } /* Reset bits for GPIO peripheral */
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96 #define INPUTMUX_RSTS \
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98 kMUX_RST_SHIFT_RSTn \
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99 } /* Reset bits for INPUTMUX peripheral */
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100 #define IOCON_RSTS \
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102 kIOCON_RST_SHIFT_RSTn \
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103 } /* Reset bits for IOCON peripheral */
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104 #define FLASH_RSTS \
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106 kFLASH_RST_SHIFT_RSTn, kFMC_RST_SHIFT_RSTn \
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107 } /* Reset bits for Flash peripheral */
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110 kMRT_RST_SHIFT_RSTn \
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111 } /* Reset bits for MRT peripheral */
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112 #define PINT_RSTS \
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114 kPINT_RST_SHIFT_RSTn \
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115 } /* Reset bits for PINT peripheral */
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118 kSCT0_RST_SHIFT_RSTn \
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119 } /* Reset bits for SCT peripheral */
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120 #define CTIMER_RSTS \
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122 kCTIMER0_RST_SHIFT_RSTn, kCTIMER1_RST_SHIFT_RSTn, kCTIMER3_RST_SHIFT_RSTn \
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123 } /* Reset bits for TIMER peripheral */
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126 kUSB_RST_SHIFT_RSTn \
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127 } /* Reset bits for USB peripheral */
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128 #define UTICK_RSTS \
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130 kUTICK_RST_SHIFT_RSTn \
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131 } /* Reset bits for UTICK peripheral */
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132 #define WWDT_RSTS \
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134 kWWDT_RST_SHIFT_RSTn \
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135 } /* Reset bits for WWDT peripheral */
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137 typedef SYSCON_RSTn_t reset_ip_name_t;
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139 /*******************************************************************************
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141 ******************************************************************************/
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142 #if defined(__cplusplus)
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147 * @brief Assert reset to peripheral.
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149 * Asserts reset signal to specified peripheral module.
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151 * @param peripheral Assert reset to this peripheral. The enum argument contains encoding of reset register
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152 * and reset bit position in the reset register.
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154 void RESET_SetPeripheralReset(reset_ip_name_t peripheral);
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157 * @brief Clear reset to peripheral.
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159 * Clears reset signal to specified peripheral module, allows it to operate.
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161 * @param peripheral Clear reset to this peripheral. The enum argument contains encoding of reset register
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162 * and reset bit position in the reset register.
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164 void RESET_ClearPeripheralReset(reset_ip_name_t peripheral);
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167 * @brief Reset peripheral module.
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169 * Reset peripheral module.
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171 * @param peripheral Peripheral to reset. The enum argument contains encoding of reset register
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172 * and reset bit position in the reset register.
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174 void RESET_PeripheralReset(reset_ip_name_t peripheral);
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176 #if defined(__cplusplus)
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182 #endif /* _FSL_RESET_H_ */
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