2 /****************************************************************************************************//**
\r
5 * @brief CMSIS Cortex-M0 Peripheral Access Layer Header File for
\r
6 * XMC1300 from Infineon.
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8 * @version V1.0.6 (Reference Manual v1.0)
\r
9 * @date 26. March 2013
\r
11 * @note Generated with SVDConv V2.78b
\r
12 * from CMSIS SVD File 'XMC1300_Processed_SVD.xml' Version 1.0.6 (Reference Manual v1.0),
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13 *******************************************************************************************************/
\r
17 /** @addtogroup Infineon
\r
21 /** @addtogroup XMC1300
\r
33 /* ------------------------- Interrupt Number Definition ------------------------ */
\r
36 /* ------------------- Cortex-M0 Processor Exceptions Numbers ------------------- */
\r
37 Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */
\r
38 NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */
\r
39 HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */
\r
40 SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */
\r
41 DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */
\r
42 PendSV_IRQn = -2, /*!< 14 Pendable request for system service */
\r
43 SysTick_IRQn = -1, /*!< 15 System Tick Timer */
\r
44 /* --------------------- XMC1300 Specific Interrupt Numbers --------------------- */
\r
45 SCU_0_IRQn = 0, /*!< SCU SR0 Interrupt */
\r
46 SCU_1_IRQn = 1, /*!< SCU SR1 Interrupt */
\r
47 SCU_2_IRQn = 2, /*!< SCU SR2 Interrupt */
\r
48 ERU0_0_IRQn = 3, /*!< ERU0 SR0 Interrupt */
\r
49 ERU0_1_IRQn = 4, /*!< ERU0 SR1 Interrupt */
\r
50 ERU0_2_IRQn = 5, /*!< ERU0 SR2 Interrupt */
\r
51 ERU0_3_IRQn = 6, /*!< ERU0 SR3 Interrupt */
\r
52 MATH0_0_IRQn = 7, /*!< MATH0 SR0 Interrupt */
\r
54 USIC0_0_IRQn = 9, /*!< USIC SR0 Interrupt */
\r
55 USIC0_1_IRQn = 10, /*!< USIC SR1 Interrupt */
\r
56 USIC0_2_IRQn = 11, /*!< USIC SR2 Interrupt */
\r
57 USIC0_3_IRQn = 12, /*!< USIC SR3 Interrupt */
\r
58 USIC0_4_IRQn = 13, /*!< USIC SR4 Interrupt */
\r
59 USIC0_5_IRQn = 14, /*!< USIC SR5 Interrupt */
\r
61 VADC0_C0_0_IRQn = 15, /*!< VADC SR0 Interrupt */
\r
62 VADC0_C0_1_IRQn = 16, /*!< VADC SR1 Interrupt */
\r
63 VADC0_G0_0_IRQn = 17, /*!< VADC SR2 Interrupt */
\r
64 VADC0_G0_1_IRQn = 18, /*!< VADC SR3 Interrupt */
\r
65 VADC0_G1_0_IRQn = 19, /*!< VADC SR4 Interrupt */
\r
66 VADC0_G1_1_IRQn = 20, /*!< VADC SR5 Interrupt */
\r
68 CCU40_0_IRQn = 21, /*!< CCU40 SR0 Interrupt */
\r
69 CCU40_1_IRQn = 22, /*!< CCU40 SR1 Interrupt */
\r
70 CCU40_2_IRQn = 23, /*!< CCU40 SR2 Interrupt */
\r
71 CCU40_3_IRQn = 24, /*!< CCU40 SR3 Interrupt */
\r
73 CCU80_0_IRQn = 25, /*!< CCU80 SR0 Interrupt */
\r
74 CCU80_1_IRQn = 26, /*!< CCU80 SR1 Interrupt */
\r
76 POSIF0_0_IRQn = 27, /*!< POSIF0 SR0 Interrupt */
\r
77 POSIF0_1_IRQn = 28, /*!< POSIF1 SR1 Interrupt */
\r
79 BCCU0_0_IRQn = 31, /*!< BCCU0 SR0 Interrupt */
\r
83 /** @addtogroup Configuration_of_CMSIS
\r
88 /* ================================================================================ */
\r
89 /* ================ Processor and Core Peripheral Section ================ */
\r
90 /* ================================================================================ */
\r
92 /* ----------------Configuration of the Cortex-M0 Processor and Core Peripherals---------------- */
\r
93 #define __CM0_REV 0x0000 /*!< Cortex-M0 Core Revision */
\r
94 #define __MPU_PRESENT 0 /*!< MPU present or not */
\r
95 #define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */
\r
96 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
\r
97 /** @} */ /* End of group Configuration_of_CMSIS */
\r
99 #include <core_cm0.h> /*!< Cortex-M0 processor and core peripherals */
\r
100 #include "system_XMC1300.h" /*!< XMC1300 System */
\r
103 /* ================================================================================ */
\r
104 /* ================ Device Specific Peripheral Section ================ */
\r
105 /* ================================================================================ */
\r
106 /* Macro to modify desired bitfields of a register */
\r
107 #define WR_REG(reg, mask, pos, val) reg = (((uint32_t)val << pos) & \
\r
108 ((uint32_t)mask)) | \
\r
109 (reg & ((uint32_t)~((uint32_t)mask)))
\r
111 /* Macro to modify desired bitfields of a register */
\r
112 #define WR_REG_SIZE(reg, mask, pos, val, size) { \
\r
113 uint##size##_t VAL1 = (uint##size##_t)((uint##size##_t)val << pos); \
\r
114 uint##size##_t VAL2 = (uint##size##_t) (VAL1 & (uint##size##_t)mask); \
\r
115 uint##size##_t VAL3 = (uint##size##_t)~((uint##size##_t)mask); \
\r
116 uint##size##_t VAL4 = (uint##size##_t) ((uint##size##_t)reg & VAL3); \
\r
117 reg = (uint##size##_t) (VAL2 | VAL4);\
\r
120 /** Macro to read bitfields from a register */
\r
121 #define RD_REG(reg, mask, pos) (((uint32_t)reg & (uint32_t)mask) >> pos)
\r
123 /** Macro to read bitfields from a register */
\r
124 #define RD_REG_SIZE(reg, mask, pos,size) ((uint##size##_t)(((uint32_t)reg & \
\r
125 (uint32_t)mask) >> pos) )
\r
127 /** Macro to set a bit in register */
\r
128 #define SET_BIT(reg, pos) (reg |= ((uint32_t)1<<pos))
\r
130 /** Macro to clear a bit in register */
\r
131 #define CLR_BIT(reg, pos) (reg = reg & (uint32_t)(~((uint32_t)1<<pos)) )
\r
133 * ==========================================================================
\r
134 * ---------- Interrupt Handler Definition ----------------------------------
\r
135 * ==========================================================================
\r
137 #define IRQ_Hdlr_0 SCU_0_IRQHandler
\r
138 #define IRQ_Hdlr_1 SCU_1_IRQHandler
\r
139 #define IRQ_Hdlr_2 SCU_2_IRQHandler
\r
140 #define IRQ_Hdlr_3 ERU0_0_IRQHandler
\r
141 #define IRQ_Hdlr_4 ERU0_1_IRQHandler
\r
142 #define IRQ_Hdlr_5 ERU0_2_IRQHandler
\r
143 #define IRQ_Hdlr_6 ERU0_3_IRQHandler
\r
144 #define IRQ_Hdlr_7 MATH0_0_IRQHandler
\r
146 #define IRQ_Hdlr_9 USIC0_0_IRQHandler
\r
147 #define IRQ_Hdlr_10 USIC0_1_IRQHandler
\r
148 #define IRQ_Hdlr_11 USIC0_2_IRQHandler
\r
149 #define IRQ_Hdlr_12 USIC0_3_IRQHandler
\r
150 #define IRQ_Hdlr_13 USIC0_4_IRQHandler
\r
151 #define IRQ_Hdlr_14 USIC0_5_IRQHandler
\r
152 #define IRQ_Hdlr_15 VADC0_C0_0_IRQHandler
\r
153 #define IRQ_Hdlr_16 VADC0_C0_1_IRQHandler
\r
154 #define IRQ_Hdlr_17 VADC0_G0_0_IRQHandler
\r
155 #define IRQ_Hdlr_18 VADC0_G0_1_IRQHandler
\r
156 #define IRQ_Hdlr_19 VADC0_G1_0_IRQHandler
\r
157 #define IRQ_Hdlr_20 VADC0_G1_1_IRQHandler
\r
158 #define IRQ_Hdlr_21 CCU40_0_IRQHandler
\r
159 #define IRQ_Hdlr_22 CCU40_1_IRQHandler
\r
160 #define IRQ_Hdlr_23 CCU40_2_IRQHandler
\r
161 #define IRQ_Hdlr_24 CCU40_3_IRQHandler
\r
162 #define IRQ_Hdlr_25 CCU80_0_IRQHandler
\r
163 #define IRQ_Hdlr_26 CCU80_1_IRQHandler
\r
164 #define IRQ_Hdlr_27 POSIF0_0_IRQHandler
\r
165 #define IRQ_Hdlr_28 POSIF0_1_IRQHandler
\r
166 #define IRQ_Hdlr_31 BCCU0_0_IRQHandler
\r
169 * ==========================================================================
\r
170 * ---------- Interrupt Handler retrieval macro -----------------------------
\r
171 * ==========================================================================
\r
173 #define GET_IRQ_HANDLER(N) IRQ_Hdlr_##N
\r
176 /** @addtogroup Device_Peripheral_Registers
\r
181 /* ------------------- Start of section using anonymous unions ------------------ */
\r
182 #if defined(__CC_ARM)
\r
184 #pragma anon_unions
\r
185 #elif defined(__ICCARM__)
\r
186 #pragma language=extended
\r
187 #elif defined(__GNUC__)
\r
188 /* anonymous unions are enabled by default */
\r
189 #elif defined(__TMS470__)
\r
190 /* anonymous unions are enabled by default */
\r
191 #elif defined(__TASKING__)
\r
192 #pragma warning 586
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194 #warning Not supported compiler type
\r
199 /* ================================================================================ */
\r
200 /* ================ PPB ================ */
\r
201 /* ================================================================================ */
\r
205 * @brief Cortex-M0 Private Peripheral Block (PPB)
\r
208 typedef struct { /*!< (@ 0xE000E000) PPB Structure */
\r
209 __I uint32_t RESERVED0[4];
\r
210 __IO uint32_t SYST_CSR; /*!< (@ 0xE000E010) SysTick Control and Status Register */
\r
211 __IO uint32_t SYST_RVR; /*!< (@ 0xE000E014) SysTick Reload Value Register */
\r
212 __IO uint32_t SYST_CVR; /*!< (@ 0xE000E018) SysTick Current Value Register */
\r
213 __I uint32_t SYST_CALIB; /*!< (@ 0xE000E01C) SysTick Calibration Value Register */
\r
214 __I uint32_t RESERVED1[56];
\r
215 __IO uint32_t NVIC_ISER; /*!< (@ 0xE000E100) Interrupt Set-enable Register */
\r
216 __I uint32_t RESERVED2[31];
\r
217 __IO uint32_t NVIC_ICER; /*!< (@ 0xE000E180) IInterrupt Clear-enable Register */
\r
218 __I uint32_t RESERVED3[31];
\r
219 __IO uint32_t NVIC_ISPR; /*!< (@ 0xE000E200) Interrupt Set-pending Register */
\r
220 __I uint32_t RESERVED4[31];
\r
221 __IO uint32_t NVIC_ICPR; /*!< (@ 0xE000E280) Interrupt Clear-pending Register */
\r
222 __I uint32_t RESERVED5[95];
\r
223 __IO uint32_t NVIC_IPR0; /*!< (@ 0xE000E400) Interrupt Priority Register 0 */
\r
224 __IO uint32_t NVIC_IPR1; /*!< (@ 0xE000E404) Interrupt Priority Register 1 */
\r
225 __IO uint32_t NVIC_IPR2; /*!< (@ 0xE000E408) Interrupt Priority Register 2 */
\r
226 __IO uint32_t NVIC_IPR3; /*!< (@ 0xE000E40C) Interrupt Priority Register 3 */
\r
227 __IO uint32_t NVIC_IPR4; /*!< (@ 0xE000E410) Interrupt Priority Register 4 */
\r
228 __IO uint32_t NVIC_IPR5; /*!< (@ 0xE000E414) Interrupt Priority Register 5 */
\r
229 __IO uint32_t NVIC_IPR6; /*!< (@ 0xE000E418) Interrupt Priority Register 6 */
\r
230 __IO uint32_t NVIC_IPR7; /*!< (@ 0xE000E41C) Interrupt Priority Register 7 */
\r
231 __I uint32_t RESERVED6[568];
\r
232 __I uint32_t CPUID; /*!< (@ 0xE000ED00) CPUID Base Register */
\r
233 __IO uint32_t ICSR; /*!< (@ 0xE000ED04) Interrupt Control and State Register */
\r
234 __I uint32_t RESERVED7;
\r
235 __IO uint32_t AIRCR; /*!< (@ 0xE000ED0C) Application Interrupt and Reset Control Register */
\r
236 __IO uint32_t SCR; /*!< (@ 0xE000ED10) System Control Register */
\r
237 __I uint32_t CCR; /*!< (@ 0xE000ED14) Configuration and Control Register */
\r
238 __I uint32_t RESERVED8;
\r
239 __IO uint32_t SHPR2; /*!< (@ 0xE000ED1C) System Handler Priority Register 2 */
\r
240 __IO uint32_t SHPR3; /*!< (@ 0xE000ED20) System Handler Priority Register 3 */
\r
241 __IO uint32_t SHCSR; /*!< (@ 0xE000ED24) System Handler Control and State Register */
\r
245 /* ================================================================================ */
\r
246 /* ================ ERU [ERU0] ================ */
\r
247 /* ================================================================================ */
\r
251 * @brief Event Request Unit 0 (ERU)
\r
254 typedef struct { /*!< (@ 0x40010600) ERU Structure */
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255 __IO uint32_t EXISEL; /*!< (@ 0x40010600) Event Input Select */
\r
256 __I uint32_t RESERVED0[3];
\r
257 __IO uint32_t EXICON[4]; /*!< (@ 0x40010610) Event Input Control */
\r
258 __IO uint32_t EXOCON[4]; /*!< (@ 0x40010620) Event Output Trigger Control */
\r
259 } ERU_GLOBAL_TypeDef;
\r
262 /* ================================================================================ */
\r
263 /* ================ MATH ================ */
\r
264 /* ================================================================================ */
\r
268 * @brief MATH Unit (MATH)
\r
271 typedef struct { /*!< (@ 0x40030000) MATH Structure */
\r
272 __I uint32_t RESERVED0;
\r
273 __IO uint32_t GLBCON; /*!< (@ 0x40030004) Global Control Register */
\r
274 __I uint32_t ID; /*!< (@ 0x40030008) Module Identification Register */
\r
275 __IO uint32_t EVIER; /*!< (@ 0x4003000C) Event Interrupt Enable Register */
\r
276 __I uint32_t EVFR; /*!< (@ 0x40030010) Event Flag Register */
\r
277 __O uint32_t EVFSR; /*!< (@ 0x40030014) Event Flag Set Register */
\r
278 __O uint32_t EVFCR; /*!< (@ 0x40030018) Event Flag Clear Register */
\r
279 __I uint32_t RESERVED1;
\r
280 __IO uint32_t DVD; /*!< (@ 0x40030020) Dividend Register */
\r
281 __IO uint32_t DVS; /*!< (@ 0x40030024) Divisor Register */
\r
282 __I uint32_t QUOT; /*!< (@ 0x40030028) Quotient Register */
\r
283 __I uint32_t RMD; /*!< (@ 0x4003002C) Remainder Register */
\r
284 __I uint32_t DIVST; /*!< (@ 0x40030030) Divider Status Register */
\r
285 __IO uint32_t DIVCON; /*!< (@ 0x40030034) Divider Control Register */
\r
286 __I uint32_t RESERVED2[2];
\r
287 __IO uint32_t STATC; /*!< (@ 0x40030040) CORDIC Status and Data Control Register */
\r
288 __IO uint32_t CON; /*!< (@ 0x40030044) CORDIC Control Register */
\r
289 __IO uint32_t CORDX; /*!< (@ 0x40030048) CORDIC X Data Register */
\r
290 __IO uint32_t CORDY; /*!< (@ 0x4003004C) CORDIC Y Data Register */
\r
291 __IO uint32_t CORDZ; /*!< (@ 0x40030050) CORDIC Z Data Register */
\r
292 __I uint32_t CORRX; /*!< (@ 0x40030054) CORDIC X Result Register */
\r
293 __I uint32_t CORRY; /*!< (@ 0x40030058) CORDIC Y Result Register */
\r
294 __I uint32_t CORRZ; /*!< (@ 0x4003005C) CORDIC Z Result Register */
\r
298 /* ================================================================================ */
\r
299 /* ================ PAU ================ */
\r
300 /* ================================================================================ */
\r
304 * @brief PAU Unit (PAU)
\r
307 typedef struct { /*!< (@ 0x40000000) PAU Structure */
\r
308 __I uint32_t RESERVED0[16];
\r
309 __I uint32_t AVAIL0; /*!< (@ 0x40000040) Peripheral Availability Register 0 */
\r
310 __I uint32_t AVAIL1; /*!< (@ 0x40000044) Peripheral Availability Register 1 */
\r
311 __I uint32_t AVAIL2; /*!< (@ 0x40000048) Peripheral Availability Register 2 */
\r
312 __I uint32_t RESERVED1[13];
\r
313 __IO uint32_t PRIVDIS0; /*!< (@ 0x40000080) Peripheral Privilege Access Register 0 */
\r
314 __IO uint32_t PRIVDIS1; /*!< (@ 0x40000084) Peripheral Privilege Access Register 1 */
\r
315 __IO uint32_t PRIVDIS2; /*!< (@ 0x40000088) Peripheral Privilege Access Register 2 */
\r
316 __I uint32_t RESERVED2[221];
\r
317 __I uint32_t ROMSIZE; /*!< (@ 0x40000400) ROM Size Register */
\r
318 __I uint32_t FLSIZE; /*!< (@ 0x40000404) Flash Size Register */
\r
319 __I uint32_t RESERVED3[2];
\r
320 __I uint32_t RAM0SIZE; /*!< (@ 0x40000410) RAM0 Size Register */
\r
324 /* ================================================================================ */
\r
325 /* ================ NVM ================ */
\r
326 /* ================================================================================ */
\r
330 * @brief NVM Unit (NVM)
\r
333 typedef struct { /*!< (@ 0x40050000) NVM Structure */
\r
334 __I uint16_t NVMSTATUS; /*!< (@ 0x40050000) NVM Status Register */
\r
335 __I uint16_t RESERVED0;
\r
336 __IO uint16_t NVMPROG; /*!< (@ 0x40050004) NVM Programming Control Register */
\r
337 __I uint16_t RESERVED1;
\r
338 __IO uint16_t NVMCONF; /*!< (@ 0x40050008) NVM Configuration Register */
\r
342 /* ================================================================================ */
\r
343 /* ================ WDT ================ */
\r
344 /* ================================================================================ */
\r
348 * @brief Watch Dog Timer (WDT)
\r
351 typedef struct { /*!< (@ 0x40020000) WDT Structure */
\r
352 __I uint32_t ID; /*!< (@ 0x40020000) WDT Module ID Register */
\r
353 __IO uint32_t CTR; /*!< (@ 0x40020004) WDT Control Register */
\r
354 __O uint32_t SRV; /*!< (@ 0x40020008) WDT Service Register */
\r
355 __I uint32_t TIM; /*!< (@ 0x4002000C) WDT Timer Register */
\r
356 __IO uint32_t WLB; /*!< (@ 0x40020010) WDT Window Lower Bound Register */
\r
357 __IO uint32_t WUB; /*!< (@ 0x40020014) WDT Window Upper Bound Register */
\r
358 __I uint32_t WDTSTS; /*!< (@ 0x40020018) WDT Status Register */
\r
359 __O uint32_t WDTCLR; /*!< (@ 0x4002001C) WDT Clear Register */
\r
360 } WDT_GLOBAL_TypeDef;
\r
363 /* ================================================================================ */
\r
364 /* ================ RTC ================ */
\r
365 /* ================================================================================ */
\r
369 * @brief Real Time Clock (RTC)
\r
372 typedef struct { /*!< (@ 0x40010A00) RTC Structure */
\r
373 __I uint32_t ID; /*!< (@ 0x40010A00) RTC Module ID Register */
\r
374 __IO uint32_t CTR; /*!< (@ 0x40010A04) RTC Control Register */
\r
375 __I uint32_t RAWSTAT; /*!< (@ 0x40010A08) RTC Raw Service Request Register */
\r
376 __I uint32_t STSSR; /*!< (@ 0x40010A0C) RTC Service Request Status Register */
\r
377 __IO uint32_t MSKSR; /*!< (@ 0x40010A10) RTC Service Request Mask Register */
\r
378 __O uint32_t CLRSR; /*!< (@ 0x40010A14) RTC Clear Service Request Register */
\r
379 __IO uint32_t ATIM0; /*!< (@ 0x40010A18) RTC Alarm Time Register 0 */
\r
380 __IO uint32_t ATIM1; /*!< (@ 0x40010A1C) RTC Alarm Time Register 1 */
\r
381 __IO uint32_t TIM0; /*!< (@ 0x40010A20) RTC Time Register 0 */
\r
382 __IO uint32_t TIM1; /*!< (@ 0x40010A24) RTC Time Register 1 */
\r
383 } RTC_GLOBAL_TypeDef;
\r
386 /* ================================================================================ */
\r
387 /* ================ PRNG ================ */
\r
388 /* ================================================================================ */
\r
392 * @brief PRNG Unit (PRNG)
\r
395 typedef struct { /*!< (@ 0x48020000) PRNG Structure */
\r
396 __IO uint16_t WORD; /*!< (@ 0x48020000) Pseudo RNG Word Register */
\r
397 __I uint16_t RESERVED0;
\r
398 __I uint16_t CHK; /*!< (@ 0x48020004) Pseudo RNG Status Check Register */
\r
399 __I uint16_t RESERVED1[3];
\r
400 __IO uint16_t CTRL; /*!< (@ 0x4802000C) Pseudo RNG Control Register */
\r
404 /* ================================================================================ */
\r
405 /* ================ USIC [USIC0] ================ */
\r
406 /* ================================================================================ */
\r
410 * @brief Universal Serial Interface Controller 0 (USIC)
\r
413 typedef struct { /*!< (@ 0x48000008) USIC Structure */
\r
414 __I uint32_t ID; /*!< (@ 0x48000008) Module Identification Register */
\r
415 } USIC_GLOBAL_TypeDef;
\r
418 /* ================================================================================ */
\r
419 /* ================ USIC_CH [USIC0_CH0] ================ */
\r
420 /* ================================================================================ */
\r
424 * @brief Universal Serial Interface Controller 0 (USIC_CH)
\r
427 typedef struct { /*!< (@ 0x48000000) USIC_CH Structure */
\r
428 __I uint32_t RESERVED0;
\r
429 __I uint32_t CCFG; /*!< (@ 0x48000004) Channel Configuration Register */
\r
430 __I uint32_t RESERVED1;
\r
431 __IO uint32_t KSCFG; /*!< (@ 0x4800000C) Kernel State Configuration Register */
\r
432 __IO uint32_t FDR; /*!< (@ 0x48000010) Fractional Divider Register */
\r
433 __IO uint32_t BRG; /*!< (@ 0x48000014) Baud Rate Generator Register */
\r
434 __IO uint32_t INPR; /*!< (@ 0x48000018) Interrupt Node Pointer Register */
\r
435 __IO uint32_t DX0CR; /*!< (@ 0x4800001C) Input Control Register 0 */
\r
436 __IO uint32_t DX1CR; /*!< (@ 0x48000020) Input Control Register 1 */
\r
437 __IO uint32_t DX2CR; /*!< (@ 0x48000024) Input Control Register 2 */
\r
438 __IO uint32_t DX3CR; /*!< (@ 0x48000028) Input Control Register 3 */
\r
439 __IO uint32_t DX4CR; /*!< (@ 0x4800002C) Input Control Register 4 */
\r
440 __IO uint32_t DX5CR; /*!< (@ 0x48000030) Input Control Register 5 */
\r
441 __IO uint32_t SCTR; /*!< (@ 0x48000034) Shift Control Register */
\r
442 __IO uint32_t TCSR; /*!< (@ 0x48000038) Transmit Control/Status Register */
\r
445 __IO uint32_t PCR_IICMode; /*!< (@ 0x4800003C) Protocol Control Register [IIC Mode] */
\r
446 __IO uint32_t PCR_IISMode; /*!< (@ 0x4800003C) Protocol Control Register [IIS Mode] */
\r
447 __IO uint32_t PCR_SSCMode; /*!< (@ 0x4800003C) Protocol Control Register [SSC Mode] */
\r
448 __IO uint32_t PCR; /*!< (@ 0x4800003C) Protocol Control Register */
\r
449 __IO uint32_t PCR_ASCMode; /*!< (@ 0x4800003C) Protocol Control Register [ASC Mode] */
\r
451 __IO uint32_t CCR; /*!< (@ 0x48000040) Channel Control Register */
\r
452 __IO uint32_t CMTR; /*!< (@ 0x48000044) Capture Mode Timer Register */
\r
455 __IO uint32_t PSR_IICMode; /*!< (@ 0x48000048) Protocol Status Register [IIC Mode] */
\r
456 __IO uint32_t PSR_IISMode; /*!< (@ 0x48000048) Protocol Status Register [IIS Mode] */
\r
457 __IO uint32_t PSR_SSCMode; /*!< (@ 0x48000048) Protocol Status Register [SSC Mode] */
\r
458 __IO uint32_t PSR; /*!< (@ 0x48000048) Protocol Status Register */
\r
459 __IO uint32_t PSR_ASCMode; /*!< (@ 0x48000048) Protocol Status Register [ASC Mode] */
\r
461 __O uint32_t PSCR; /*!< (@ 0x4800004C) Protocol Status Clear Register */
\r
462 __I uint32_t RBUFSR; /*!< (@ 0x48000050) Receiver Buffer Status Register */
\r
463 __I uint32_t RBUF; /*!< (@ 0x48000054) Receiver Buffer Register */
\r
464 __I uint32_t RBUFD; /*!< (@ 0x48000058) Receiver Buffer Register for Debugger */
\r
465 __I uint32_t RBUF0; /*!< (@ 0x4800005C) Receiver Buffer Register 0 */
\r
466 __I uint32_t RBUF1; /*!< (@ 0x48000060) Receiver Buffer Register 1 */
\r
467 __I uint32_t RBUF01SR; /*!< (@ 0x48000064) Receiver Buffer 01 Status Register */
\r
468 __O uint32_t FMR; /*!< (@ 0x48000068) Flag Modification Register */
\r
469 __I uint32_t RESERVED2[5];
\r
470 __IO uint32_t TBUF[32]; /*!< (@ 0x48000080) Transmit Buffer */
\r
471 __IO uint32_t BYP; /*!< (@ 0x48000100) Bypass Data Register */
\r
472 __IO uint32_t BYPCR; /*!< (@ 0x48000104) Bypass Control Register */
\r
473 __IO uint32_t TBCTR; /*!< (@ 0x48000108) Transmitter Buffer Control Register */
\r
474 __IO uint32_t RBCTR; /*!< (@ 0x4800010C) Receiver Buffer Control Register */
\r
475 __I uint32_t TRBPTR; /*!< (@ 0x48000110) Transmit/Receive Buffer Pointer Register */
\r
476 __IO uint32_t TRBSR; /*!< (@ 0x48000114) Transmit/Receive Buffer Status Register */
\r
477 __O uint32_t TRBSCR; /*!< (@ 0x48000118) Transmit/Receive Buffer Status Clear Register */
\r
478 __I uint32_t OUTR; /*!< (@ 0x4800011C) Receiver Buffer Output Register */
\r
479 __I uint32_t OUTDR; /*!< (@ 0x48000120) Receiver Buffer Output Register L for Debugger */
\r
480 __I uint32_t RESERVED3[23];
\r
481 __O uint32_t IN[32]; /*!< (@ 0x48000180) Transmit FIFO Buffer */
\r
485 /* ================================================================================ */
\r
486 /* ================ SCU_GENERAL ================ */
\r
487 /* ================================================================================ */
\r
491 * @brief System Control Unit (SCU_GENERAL)
\r
494 typedef struct { /*!< (@ 0x40010000) SCU_GENERAL Structure */
\r
495 __I uint32_t DBGROMID; /*!< (@ 0x40010000) Debug System ROM ID Register */
\r
496 __I uint32_t IDCHIP; /*!< (@ 0x40010004) Chip ID Register */
\r
497 __I uint32_t ID; /*!< (@ 0x40010008) SCU Module ID Register */
\r
498 __I uint32_t RESERVED0[2];
\r
499 __IO uint32_t SSW0; /*!< (@ 0x40010014) SSW Register 0 */
\r
500 __I uint32_t RESERVED1[3];
\r
501 __IO uint32_t PASSWD; /*!< (@ 0x40010024) Password Register */
\r
502 __I uint32_t RESERVED2[2];
\r
503 __IO uint32_t CCUCON; /*!< (@ 0x40010030) CCU Control Register */
\r
504 __I uint32_t RESERVED3[5];
\r
505 __I uint32_t MIRRSTS; /*!< (@ 0x40010048) Mirror Update Status Register */
\r
506 __I uint32_t RESERVED4[2];
\r
507 __IO uint32_t PMTSR; /*!< (@ 0x40010054) Parity Memory Test Select Register */
\r
508 } SCU_GENERAL_Type;
\r
511 /* ================================================================================ */
\r
512 /* ================ SCU_INTERRUPT ================ */
\r
513 /* ================================================================================ */
\r
517 * @brief System Control Unit (SCU_INTERRUPT)
\r
520 typedef struct { /*!< (@ 0x40010038) SCU_INTERRUPT Structure */
\r
521 __I uint32_t SRRAW; /*!< (@ 0x40010038) SCU Raw Service Request Status */
\r
522 __IO uint32_t SRMSK; /*!< (@ 0x4001003C) SCU Service Request Mask */
\r
523 __O uint32_t SRCLR; /*!< (@ 0x40010040) SCU Service Request Clear */
\r
524 __O uint32_t SRSET; /*!< (@ 0x40010044) SCU Service Request Set */
\r
525 } SCU_INTERRUPT_TypeDef;
\r
528 /* ================================================================================ */
\r
529 /* ================ SCU_POWER ================ */
\r
530 /* ================================================================================ */
\r
534 * @brief System Control Unit (SCU_POWER)
\r
537 typedef struct { /*!< (@ 0x40010200) SCU_POWER Structure */
\r
538 __I uint32_t VDESR; /*!< (@ 0x40010200) Voltage Detector Status Register */
\r
542 /* ================================================================================ */
\r
543 /* ================ SCU_CLK ================ */
\r
544 /* ================================================================================ */
\r
548 * @brief System Control Unit (SCU_CLK)
\r
551 typedef struct { /*!< (@ 0x40010300) SCU_CLK Structure */
\r
552 __IO uint32_t CLKCR; /*!< (@ 0x40010300) Clock Control Register */
\r
553 __IO uint32_t PWRSVCR; /*!< (@ 0x40010304) Power Save Control Register */
\r
554 __I uint32_t CGATSTAT0; /*!< (@ 0x40010308) Peripheral 0 Clock Gating Status */
\r
555 __O uint32_t CGATSET0; /*!< (@ 0x4001030C) Peripheral 0 Clock Gating Set */
\r
556 __O uint32_t CGATCLR0; /*!< (@ 0x40010310) Peripheral 0 Clock Gating Clear */
\r
557 __IO uint32_t OSCCSR; /*!< (@ 0x40010314) Oscillator Control and Status Register */
\r
561 /* ================================================================================ */
\r
562 /* ================ SCU_RESET ================ */
\r
563 /* ================================================================================ */
\r
567 * @brief System Control Unit (SCU_RESET)
\r
570 typedef struct { /*!< (@ 0x40010400) SCU_RESET Structure */
\r
571 __I uint32_t RSTSTAT; /*!< (@ 0x40010400) RCU Reset Status */
\r
572 __O uint32_t RSTSET; /*!< (@ 0x40010404) RCU Reset Set Register */
\r
573 __O uint32_t RSTCLR; /*!< (@ 0x40010408) RCU Reset Clear Register */
\r
574 __IO uint32_t RSTCON; /*!< (@ 0x4001040C) RCU Reset Control Register */
\r
578 /* ================================================================================ */
\r
579 /* ================ COMPARATOR ================ */
\r
580 /* ================================================================================ */
\r
584 * @brief System Control Unit (COMPARATOR)
\r
587 typedef struct { /*!< (@ 0x40010500) COMPARATOR Structure */
\r
588 __IO uint32_t ORCCTRL; /*!< (@ 0x40010500) Out Of Range Comparator Control Register */
\r
589 __I uint32_t RESERVED0[726];
\r
590 __IO uint16_t ANACMP0; /*!< (@ 0x4001105C) Analog Comparator 0 Control Register */
\r
591 __I uint16_t RESERVED1;
\r
592 __IO uint16_t ANACMP1; /*!< (@ 0x40011060) Analog Comparator 1 Control Register */
\r
593 __I uint16_t RESERVED2;
\r
594 __IO uint16_t ANACMP2; /*!< (@ 0x40011064) Analog Comparator 2 Control Register */
\r
598 /* ================================================================================ */
\r
599 /* ================ SCU_ANALOG ================ */
\r
600 /* ================================================================================ */
\r
604 * @brief System Control Unit (SCU_ANALOG)
\r
607 typedef struct { /*!< (@ 0x40011000) SCU_ANALOG Structure */
\r
608 __I uint32_t RESERVED0[9];
\r
609 __IO uint16_t ANATSECTRL; /*!< (@ 0x40011024) Temperature Sensor Control Register */
\r
610 __I uint16_t RESERVED1[5];
\r
611 __IO uint16_t ANATSEIH; /*!< (@ 0x40011030) Temperature Sensor High Temperature Interrupt
\r
613 __I uint16_t RESERVED2;
\r
614 __IO uint16_t ANATSEIL; /*!< (@ 0x40011034) Temperature Sensor Low Temperature Interrupt
\r
616 __I uint16_t RESERVED3[5];
\r
617 __I uint16_t ANATSEMON; /*!< (@ 0x40011040) Temperature Sensor Counter2 Monitor Register */
\r
618 __I uint16_t RESERVED4[7];
\r
619 __IO uint16_t ANAVDEL; /*!< (@ 0x40011050) Voltage Detector Control Register */
\r
620 __I uint16_t RESERVED5[13];
\r
621 __IO uint16_t ANAOFFSET; /*!< (@ 0x4001106C) DCO1 Offset Register */
\r
625 /* ================================================================================ */
\r
626 /* ================ CCU4 [CCU40] ================ */
\r
627 /* ================================================================================ */
\r
631 * @brief Capture Compare Unit 4 - Unit 0 (CCU4)
\r
634 typedef struct { /*!< (@ 0x48040000) CCU4 Structure */
\r
635 __IO uint32_t GCTRL; /*!< (@ 0x48040000) Global Control Register */
\r
636 __I uint32_t GSTAT; /*!< (@ 0x48040004) Global Status Register */
\r
637 __O uint32_t GIDLS; /*!< (@ 0x48040008) Global Idle Set */
\r
638 __O uint32_t GIDLC; /*!< (@ 0x4804000C) Global Idle Clear */
\r
639 __O uint32_t GCSS; /*!< (@ 0x48040010) Global Channel Set */
\r
640 __O uint32_t GCSC; /*!< (@ 0x48040014) Global Channel Clear */
\r
641 __I uint32_t GCST; /*!< (@ 0x48040018) Global Channel Status */
\r
642 __I uint32_t RESERVED0[25];
\r
643 __I uint32_t MIDR; /*!< (@ 0x48040080) Module Identification */
\r
644 } CCU4_GLOBAL_TypeDef;
\r
647 /* ================================================================================ */
\r
648 /* ================ CCU4_CC4 [CCU40_CC40] ================ */
\r
649 /* ================================================================================ */
\r
653 * @brief Capture Compare Unit 4 - Unit 0 (CCU4_CC4)
\r
656 typedef struct { /*!< (@ 0x48040100) CCU4_CC4 Structure */
\r
657 __IO uint32_t INS; /*!< (@ 0x48040100) Input Selector Configuration */
\r
658 __IO uint32_t CMC; /*!< (@ 0x48040104) Connection Matrix Control */
\r
659 __I uint32_t TCST; /*!< (@ 0x48040108) Slice Timer Status */
\r
660 __O uint32_t TCSET; /*!< (@ 0x4804010C) Slice Timer Run Set */
\r
661 __O uint32_t TCCLR; /*!< (@ 0x48040110) Slice Timer Clear */
\r
662 __IO uint32_t TC; /*!< (@ 0x48040114) Slice Timer Control */
\r
663 __IO uint32_t PSL; /*!< (@ 0x48040118) Passive Level Config */
\r
664 __I uint32_t DIT; /*!< (@ 0x4804011C) Dither Config */
\r
665 __IO uint32_t DITS; /*!< (@ 0x48040120) Dither Shadow Register */
\r
666 __IO uint32_t PSC; /*!< (@ 0x48040124) Prescaler Control */
\r
667 __IO uint32_t FPC; /*!< (@ 0x48040128) Floating Prescaler Control */
\r
668 __IO uint32_t FPCS; /*!< (@ 0x4804012C) Floating Prescaler Shadow */
\r
669 __I uint32_t PR; /*!< (@ 0x48040130) Timer Period Value */
\r
670 __IO uint32_t PRS; /*!< (@ 0x48040134) Timer Shadow Period Value */
\r
671 __I uint32_t CR; /*!< (@ 0x48040138) Timer Compare Value */
\r
672 __IO uint32_t CRS; /*!< (@ 0x4804013C) Timer Shadow Compare Value */
\r
673 __I uint32_t RESERVED0[12];
\r
674 __IO uint32_t TIMER; /*!< (@ 0x48040170) Timer Value */
\r
675 __I uint32_t CV[4]; /*!< (@ 0x48040174) Capture Register 0 */
\r
676 __I uint32_t RESERVED1[7];
\r
677 __I uint32_t INTS; /*!< (@ 0x480401A0) Interrupt Status */
\r
678 __IO uint32_t INTE; /*!< (@ 0x480401A4) Interrupt Enable Control */
\r
679 __IO uint32_t SRS; /*!< (@ 0x480401A8) Service Request Selector */
\r
680 __O uint32_t SWS; /*!< (@ 0x480401AC) Interrupt Status Set */
\r
681 __O uint32_t SWR; /*!< (@ 0x480401B0) Interrupt Status Clear */
\r
682 __I uint32_t RESERVED2;
\r
683 __I uint32_t ECRD0; /*!< (@ 0x480401B8) Extended Read Back 0 */
\r
684 __I uint32_t ECRD1; /*!< (@ 0x480401BC) Extended Read Back 1 */
\r
685 } CCU4_CC4_TypeDef;
\r
688 /* ================================================================================ */
\r
689 /* ================ CCU8 [CCU80] ================ */
\r
690 /* ================================================================================ */
\r
694 * @brief Capture Compare Unit 8 - Unit 0 (CCU8)
\r
697 typedef struct { /*!< (@ 0x50000000) CCU8 Structure */
\r
698 __IO uint32_t GCTRL; /*!< (@ 0x50000000) Global Control Register */
\r
699 __I uint32_t GSTAT; /*!< (@ 0x50000004) Global Status Register */
\r
700 __O uint32_t GIDLS; /*!< (@ 0x50000008) Global Idle Set */
\r
701 __O uint32_t GIDLC; /*!< (@ 0x5000000C) Global Idle Clear */
\r
702 __O uint32_t GCSS; /*!< (@ 0x50000010) Global Channel Set */
\r
703 __O uint32_t GCSC; /*!< (@ 0x50000014) Global Channel Clear */
\r
704 __I uint32_t GCST; /*!< (@ 0x50000018) Global Channel status */
\r
705 __IO uint32_t GPCHK; /*!< (@ 0x5000001C) Parity Checker Configuration */
\r
706 __I uint32_t RESERVED0[24];
\r
707 __I uint32_t MIDR; /*!< (@ 0x50000080) Module Identification */
\r
708 } CCU8_GLOBAL_TypeDef;
\r
711 /* ================================================================================ */
\r
712 /* ================ CCU8_CC8 [CCU80_CC80] ================ */
\r
713 /* ================================================================================ */
\r
717 * @brief Capture Compare Unit 8 - Unit 0 (CCU8_CC8)
\r
720 typedef struct { /*!< (@ 0x50000100) CCU8_CC8 Structure */
\r
721 __IO uint32_t INS; /*!< (@ 0x50000100) Input Selector Configuration */
\r
722 __IO uint32_t CMC; /*!< (@ 0x50000104) Connection Matrix Control */
\r
723 __I uint32_t TCST; /*!< (@ 0x50000108) Slice Timer Status */
\r
724 __O uint32_t TCSET; /*!< (@ 0x5000010C) Slice Timer Run Set */
\r
725 __O uint32_t TCCLR; /*!< (@ 0x50000110) Slice Timer Clear */
\r
726 __IO uint32_t TC; /*!< (@ 0x50000114) Slice Timer Control */
\r
727 __IO uint32_t PSL; /*!< (@ 0x50000118) Passive Level Config */
\r
728 __I uint32_t DIT; /*!< (@ 0x5000011C) Dither Config */
\r
729 __IO uint32_t DITS; /*!< (@ 0x50000120) Dither Shadow Register */
\r
730 __IO uint32_t PSC; /*!< (@ 0x50000124) Prescaler Control */
\r
731 __IO uint32_t FPC; /*!< (@ 0x50000128) Floating Prescaler Control */
\r
732 __IO uint32_t FPCS; /*!< (@ 0x5000012C) Floating Prescaler Shadow */
\r
733 __I uint32_t PR; /*!< (@ 0x50000130) Timer Period Value */
\r
734 __IO uint32_t PRS; /*!< (@ 0x50000134) Timer Shadow Period Value */
\r
735 __I uint32_t CR1; /*!< (@ 0x50000138) Channel 1 Compare Value */
\r
736 __IO uint32_t CR1S; /*!< (@ 0x5000013C) Channel 1 Compare Shadow Value */
\r
737 __I uint32_t CR2; /*!< (@ 0x50000140) Channel 2 Compare Value */
\r
738 __IO uint32_t CR2S; /*!< (@ 0x50000144) Channel 2 Compare Shadow Value */
\r
739 __IO uint32_t CHC; /*!< (@ 0x50000148) Channel Control */
\r
740 __IO uint32_t DTC; /*!< (@ 0x5000014C) Dead Time Control */
\r
741 __IO uint32_t DC1R; /*!< (@ 0x50000150) Channel 1 Dead Time Values */
\r
742 __IO uint32_t DC2R; /*!< (@ 0x50000154) Channel 2 Dead Time Values */
\r
743 __I uint32_t RESERVED0[6];
\r
744 __IO uint32_t TIMER; /*!< (@ 0x50000170) Timer Value */
\r
745 __I uint32_t CV[4]; /*!< (@ 0x50000174) Capture Register 0 */
\r
746 __I uint32_t RESERVED1[7];
\r
747 __I uint32_t INTS; /*!< (@ 0x500001A0) Interrupt Status */
\r
748 __IO uint32_t INTE; /*!< (@ 0x500001A4) Interrupt Enable Control */
\r
749 __IO uint32_t SRS; /*!< (@ 0x500001A8) Service Request Selector */
\r
750 __O uint32_t SWS; /*!< (@ 0x500001AC) Interrupt Status Set */
\r
751 __O uint32_t SWR; /*!< (@ 0x500001B0) Interrupt Status Clear */
\r
752 __IO uint32_t STC; /*!< (@ 0x500001B4) Shadow transfer control */
\r
753 __I uint32_t ECRD0; /*!< (@ 0x500001B8) Extended Read Back 0 */
\r
754 __I uint32_t ECRD1; /*!< (@ 0x500001BC) Extended Read Back 1 */
\r
755 } CCU8_CC8_TypeDef;
\r
758 /* ================================================================================ */
\r
759 /* ================ POSIF [POSIF0] ================ */
\r
760 /* ================================================================================ */
\r
764 * @brief Position Interface 0 (POSIF)
\r
767 typedef struct { /*!< (@ 0x50010000) POSIF Structure */
\r
768 __IO uint32_t PCONF; /*!< (@ 0x50010000) CORDIC Coprocessor configuration */
\r
769 __IO uint32_t PSUS; /*!< (@ 0x50010004) CORDIC Coprocessor Suspend Config */
\r
770 __O uint32_t PRUNS; /*!< (@ 0x50010008) CORDIC Coprocessor Run Bit Set */
\r
771 __O uint32_t PRUNC; /*!< (@ 0x5001000C) CORDIC Coprocessor Run Bit Clear */
\r
772 __I uint32_t PRUN; /*!< (@ 0x50010010) CORDIC Coprocessor Run Bit Status */
\r
773 __I uint32_t RESERVED0[3];
\r
774 __I uint32_t MIDR; /*!< (@ 0x50010020) Module Identification register */
\r
775 __I uint32_t RESERVED1[3];
\r
776 __I uint32_t HALP; /*!< (@ 0x50010030) Hall Sensor Patterns */
\r
777 __IO uint32_t HALPS; /*!< (@ 0x50010034) Hall Sensor Shadow Patterns */
\r
778 __I uint32_t RESERVED2[2];
\r
779 __I uint32_t MCM; /*!< (@ 0x50010040) Multi-Channel Pattern */
\r
780 __IO uint32_t MCSM; /*!< (@ 0x50010044) Multi-Channel Shadow Pattern */
\r
781 __O uint32_t MCMS; /*!< (@ 0x50010048) Multi-Channel Pattern Control set */
\r
782 __O uint32_t MCMC; /*!< (@ 0x5001004C) Multi-Channel Pattern Control clear */
\r
783 __I uint32_t MCMF; /*!< (@ 0x50010050) Multi-Channel Pattern Control flag */
\r
784 __I uint32_t RESERVED3[3];
\r
785 __IO uint32_t QDC; /*!< (@ 0x50010060) Quadrature Decoder Control */
\r
786 __I uint32_t RESERVED4[3];
\r
787 __I uint32_t PFLG; /*!< (@ 0x50010070) CORDIC Coprocessor Interrupt Flags */
\r
788 __IO uint32_t PFLGE; /*!< (@ 0x50010074) CORDIC Coprocessor Interrupt Enable */
\r
789 __O uint32_t SPFLG; /*!< (@ 0x50010078) CORDIC Coprocessor Interrupt Set */
\r
790 __O uint32_t RPFLG; /*!< (@ 0x5001007C) CORDIC Coprocessor Interrupt Clear */
\r
791 __I uint32_t RESERVED5[32];
\r
792 __I uint32_t PDBG; /*!< (@ 0x50010100) CORDIC Coprocessor Debug register */
\r
793 } POSIF_GLOBAL_TypeDef;
\r
796 /* ================================================================================ */
\r
797 /* ================ VADC [VADC] ================ */
\r
798 /* ================================================================================ */
\r
802 * @brief Analog to Digital Converter (VADC)
\r
805 typedef struct { /*!< (@ 0x48030000) VADC Structure */
\r
806 __IO uint32_t CLC; /*!< (@ 0x48030000) Clock Control Register */
\r
807 __I uint32_t RESERVED0;
\r
808 __I uint32_t ID; /*!< (@ 0x48030008) Module Identification Register */
\r
809 __I uint32_t RESERVED1[7];
\r
810 __IO uint32_t OCS; /*!< (@ 0x48030028) OCDS Control and Status Register */
\r
811 __I uint32_t RESERVED2[21];
\r
812 __IO uint32_t GLOBCFG; /*!< (@ 0x48030080) Global Configuration Register */
\r
813 __I uint32_t RESERVED3;
\r
814 __IO uint32_t ACCPROT0; /*!< (@ 0x48030088) Access Protection Register */
\r
815 __IO uint32_t ACCPROT1; /*!< (@ 0x4803008C) Access Protection Register */
\r
816 __I uint32_t RESERVED4[4];
\r
817 __IO uint32_t GLOBICLASS[2]; /*!< (@ 0x480300A0) Input Class Register, Global */
\r
818 __I uint32_t RESERVED5[4];
\r
819 __IO uint32_t GLOBBOUND; /*!< (@ 0x480300B8) Global Boundary Select Register */
\r
820 __I uint32_t RESERVED6[9];
\r
821 __IO uint32_t GLOBEFLAG; /*!< (@ 0x480300E0) Global Event Flag Register */
\r
822 __I uint32_t RESERVED7[23];
\r
823 __IO uint32_t GLOBEVNP; /*!< (@ 0x48030140) Global Event Node Pointer Register */
\r
824 __I uint32_t RESERVED8[15];
\r
825 __IO uint32_t BRSSEL[2]; /*!< (@ 0x48030180) Background Request Source Channel Select Register */
\r
826 __I uint32_t RESERVED9[14];
\r
827 __IO uint32_t BRSPND[2]; /*!< (@ 0x480301C0) Background Request Source Pending Register */
\r
828 __I uint32_t RESERVED10[14];
\r
829 __IO uint32_t BRSCTRL; /*!< (@ 0x48030200) Background Request Source Control Register */
\r
830 __IO uint32_t BRSMR; /*!< (@ 0x48030204) Background Request Source Mode Register */
\r
831 __I uint32_t RESERVED11[30];
\r
832 __IO uint32_t GLOBRCR; /*!< (@ 0x48030280) Global Result Control Register */
\r
833 __I uint32_t RESERVED12[31];
\r
834 __IO uint32_t GLOBRES; /*!< (@ 0x48030300) Global Result Register */
\r
835 __I uint32_t RESERVED13[31];
\r
836 __IO uint32_t GLOBRESD; /*!< (@ 0x48030380) Global Result Register, Debug */
\r
837 __I uint32_t RESERVED14[27];
\r
838 __IO uint32_t EMUXSEL; /*!< (@ 0x480303F0) External Multiplexer Select Register */
\r
839 } VADC_GLOBAL_TypeDef;
\r
842 /* ================================================================================ */
\r
843 /* ================ VADC_G [VADC_G0] ================ */
\r
844 /* ================================================================================ */
\r
848 * @brief Analog to Digital Converter (VADC_G)
\r
851 typedef struct { /*!< (@ 0x48030400) VADC_G Structure */
\r
852 __I uint32_t RESERVED0[32];
\r
853 __IO uint32_t ARBCFG; /*!< (@ 0x48030480) Arbitration Configuration Register */
\r
854 __IO uint32_t ARBPR; /*!< (@ 0x48030484) Arbitration Priority Register */
\r
855 __IO uint32_t CHASS; /*!< (@ 0x48030488) Channel Assignment Register */
\r
856 __IO uint32_t RRASS; /*!< (@ 0x4803048C) Result Assignment Register */
\r
857 __I uint32_t RESERVED1[4];
\r
858 __IO uint32_t ICLASS[2]; /*!< (@ 0x480304A0) Input Class Register 0 */
\r
859 __I uint32_t RESERVED2[2];
\r
860 __IO uint32_t ALIAS; /*!< (@ 0x480304B0) Alias Register */
\r
861 __I uint32_t RESERVED3;
\r
862 __IO uint32_t BOUND; /*!< (@ 0x480304B8) Boundary Select Register */
\r
863 __I uint32_t RESERVED4;
\r
864 __IO uint32_t SYNCTR; /*!< (@ 0x480304C0) Synchronization Control Register */
\r
865 __I uint32_t RESERVED5;
\r
866 __IO uint32_t BFL; /*!< (@ 0x480304C8) Boundary Flag Register */
\r
867 __O uint32_t BFLS; /*!< (@ 0x480304CC) Boundary Flag Software Register */
\r
868 __IO uint32_t BFLC; /*!< (@ 0x480304D0) Boundary Flag Control Register */
\r
869 __IO uint32_t BFLNP; /*!< (@ 0x480304D4) Boundary Flag Node Pointer Register */
\r
870 __I uint32_t RESERVED6[10];
\r
871 __IO uint32_t QCTRL0; /*!< (@ 0x48030500) Queue 0 Source Control Register */
\r
872 __IO uint32_t QMR0; /*!< (@ 0x48030504) Queue 0 Mode Register */
\r
873 __I uint32_t QSR0; /*!< (@ 0x48030508) Queue 0 Status Register */
\r
874 __I uint32_t Q0R0; /*!< (@ 0x4803050C) Queue 0 Register 0 */
\r
877 __I uint32_t QBUR0; /*!< (@ 0x48030510) Queue 0 Backup Register */
\r
878 __O uint32_t QINR0; /*!< (@ 0x48030510) Queue 0 Input Register */
\r
880 __I uint32_t RESERVED7[3];
\r
881 __IO uint32_t ASCTRL; /*!< (@ 0x48030520) Autoscan Source Control Register */
\r
882 __IO uint32_t ASMR; /*!< (@ 0x48030524) Autoscan Source Mode Register */
\r
883 __IO uint32_t ASSEL; /*!< (@ 0x48030528) Autoscan Source Channel Select Register */
\r
884 __IO uint32_t ASPND; /*!< (@ 0x4803052C) Autoscan Source Pending Register */
\r
885 __I uint32_t RESERVED8[20];
\r
886 __IO uint32_t CEFLAG; /*!< (@ 0x48030580) Channel Event Flag Register */
\r
887 __IO uint32_t REFLAG; /*!< (@ 0x48030584) Result Event Flag Register */
\r
888 __IO uint32_t SEFLAG; /*!< (@ 0x48030588) Source Event Flag Register */
\r
889 __I uint32_t RESERVED9;
\r
890 __O uint32_t CEFCLR; /*!< (@ 0x48030590) Channel Event Flag Clear Register */
\r
891 __O uint32_t REFCLR; /*!< (@ 0x48030594) Result Event Flag Clear Register */
\r
892 __O uint32_t SEFCLR; /*!< (@ 0x48030598) Source Event Flag Clear Register */
\r
893 __I uint32_t RESERVED10;
\r
894 __IO uint32_t CEVNP0; /*!< (@ 0x480305A0) Channel Event Node Pointer Register 0 */
\r
895 __I uint32_t RESERVED11[3];
\r
896 __IO uint32_t REVNP0; /*!< (@ 0x480305B0) Result Event Node Pointer Register 0 */
\r
897 __IO uint32_t REVNP1; /*!< (@ 0x480305B4) Result Event Node Pointer Register 1 */
\r
898 __I uint32_t RESERVED12[2];
\r
899 __IO uint32_t SEVNP; /*!< (@ 0x480305C0) Source Event Node Pointer Register */
\r
900 __I uint32_t RESERVED13;
\r
901 __O uint32_t SRACT; /*!< (@ 0x480305C8) Service Request Software Activation Trigger */
\r
902 __I uint32_t RESERVED14[9];
\r
903 __IO uint32_t EMUXCTR; /*!< (@ 0x480305F0) E0ternal Multiplexer Control Register, Group
\r
905 __I uint32_t RESERVED15;
\r
906 __IO uint32_t VFR; /*!< (@ 0x480305F8) Valid Flag Register, Group 0 */
\r
907 __I uint32_t RESERVED16;
\r
908 __IO uint32_t CHCTR[8]; /*!< (@ 0x48030600) Channel Ctrl. Reg. */
\r
909 __I uint32_t RESERVED17[24];
\r
910 __IO uint32_t RCR[16]; /*!< (@ 0x48030680) Result Control Reg. */
\r
911 __I uint32_t RESERVED18[16];
\r
912 __IO uint32_t RES[16]; /*!< (@ 0x48030700) Result Register */
\r
913 __I uint32_t RESERVED19[16];
\r
914 __I uint32_t RESD[16]; /*!< (@ 0x48030780) Result Register, Debug */
\r
918 /* ================================================================================ */
\r
919 /* ================ SHS [SHS0] ================ */
\r
920 /* ================================================================================ */
\r
924 * @brief Sample and Hold ADC Sequencer (SHS)
\r
927 typedef struct { /*!< (@ 0x48034000) SHS Structure */
\r
928 __I uint32_t RESERVED0[2];
\r
929 __I uint32_t ID; /*!< (@ 0x48034008) Module Identification Register */
\r
930 __I uint32_t RESERVED1[13];
\r
931 __IO uint32_t SHSCFG; /*!< (@ 0x48034040) SHS Configuration Register */
\r
932 __IO uint32_t STEPCFG; /*!< (@ 0x48034044) Stepper Configuration Register */
\r
933 __I uint32_t RESERVED2[2];
\r
934 __IO uint32_t LOOP; /*!< (@ 0x48034050) Loop Control Register */
\r
935 __I uint32_t RESERVED3[11];
\r
936 __IO uint32_t TIMCFG0; /*!< (@ 0x48034080) Timing Configuration Register 0 */
\r
937 __IO uint32_t TIMCFG1; /*!< (@ 0x48034084) Timing Configuration Register 1 */
\r
938 __I uint32_t RESERVED4[13];
\r
939 __IO uint32_t CALCTR; /*!< (@ 0x480340BC) Calibration Control Register */
\r
940 __IO uint32_t CALGC0; /*!< (@ 0x480340C0) Gain Calibration Control Register 0 */
\r
941 __IO uint32_t CALGC1; /*!< (@ 0x480340C4) Gain Calibration Control Register 1 */
\r
942 __I uint32_t RESERVED5[46];
\r
943 __IO uint32_t GNCTR00; /*!< (@ 0x48034180) Gain Control Register 00 */
\r
944 __I uint32_t RESERVED6[3];
\r
945 __IO uint32_t GNCTR10; /*!< (@ 0x48034190) Gain Control Register 10 */
\r
949 /* ================================================================================ */
\r
950 /* ================ BCCU [BCCU0] ================ */
\r
951 /* ================================================================================ */
\r
955 * @brief BCCU Unit 0 (BCCU)
\r
958 typedef struct { /*!< (@ 0x50030000) BCCU Structure */
\r
959 __IO uint32_t GLOBCON; /*!< (@ 0x50030000) Global Control */
\r
960 __IO uint32_t GLOBCLK; /*!< (@ 0x50030004) Global Clock */
\r
961 __I uint32_t ID; /*!< (@ 0x50030008) Module Identification */
\r
962 __IO uint32_t CHEN; /*!< (@ 0x5003000C) Channel Enable */
\r
963 __IO uint32_t CHOCON; /*!< (@ 0x50030010) Channel Output Control */
\r
964 __IO uint32_t CHTRIG; /*!< (@ 0x50030014) Channel Trigger */
\r
965 __IO uint32_t CHSTRCON; /*!< (@ 0x50030018) Channel Shadow Transfer */
\r
966 __I uint32_t LTCHOL; /*!< (@ 0x5003001C) Last Trigger Channel Output Level */
\r
967 __IO uint32_t DEEN; /*!< (@ 0x50030020) Dimming Engine Enable */
\r
968 __IO uint32_t DESTRCON; /*!< (@ 0x50030024) Dimming Shadow Transfer */
\r
969 __IO uint32_t GLOBDIM; /*!< (@ 0x50030028) Global Dimming Level */
\r
970 __IO uint32_t EVIER; /*!< (@ 0x5003002C) Event Interrupt Enable */
\r
971 __I uint32_t EVFR; /*!< (@ 0x50030030) Event Flag */
\r
972 __O uint32_t EVFSR; /*!< (@ 0x50030034) Event Flag Set */
\r
973 __O uint32_t EVFCR; /*!< (@ 0x50030038) Event Flag Clear */
\r
977 /* ================================================================================ */
\r
978 /* ================ BCCU_CH [BCCU0_CH0] ================ */
\r
979 /* ================================================================================ */
\r
983 * @brief BCCU Unit 0 (BCCU_CH)
\r
986 typedef struct { /*!< (@ 0x5003003C) BCCU_CH Structure */
\r
987 __IO uint32_t INTS; /*!< (@ 0x5003003C) Channel Intensit0 Shadow */
\r
988 __I uint32_t INT; /*!< (@ 0x50030040) Channel Intensit0 */
\r
989 __IO uint32_t CHCONFIG; /*!< (@ 0x50030044) Channel Configuration */
\r
990 __IO uint32_t PKCMP; /*!< (@ 0x50030048) Packer Compare */
\r
991 __IO uint32_t PKCNTR; /*!< (@ 0x5003004C) Packer Counter */
\r
995 /* ================================================================================ */
\r
996 /* ================ BCCU_DE [BCCU0_DE0] ================ */
\r
997 /* ================================================================================ */
\r
1001 * @brief BCCU Unit 0 (BCCU_DE)
\r
1004 typedef struct { /*!< (@ 0x5003017C) BCCU_DE Structure */
\r
1005 __IO uint32_t DLS; /*!< (@ 0x5003017C) Dimming Level Shadow */
\r
1006 __I uint32_t DL; /*!< (@ 0x50030180) Dimming Level */
\r
1007 __IO uint32_t DTT; /*!< (@ 0x50030184) Dimming Transition Time */
\r
1011 /* ================================================================================ */
\r
1012 /* ================ PORT0 ================ */
\r
1013 /* ================================================================================ */
\r
1017 * @brief Port 0 (PORT0)
\r
1020 typedef struct { /*!< (@ 0x40040000) PORT0 Structure */
\r
1021 __IO uint32_t OUT; /*!< (@ 0x40040000) Port 0 Output Register */
\r
1022 __O uint32_t OMR; /*!< (@ 0x40040004) Port 0 Output Modification Register */
\r
1023 __I uint32_t RESERVED0[2];
\r
1024 __IO uint32_t IOCR0; /*!< (@ 0x40040010) Port 0 Input/Output Control Register 0 */
\r
1025 __IO uint32_t IOCR4; /*!< (@ 0x40040014) Port 0 Input/Output Control Register 4 */
\r
1026 __IO uint32_t IOCR8; /*!< (@ 0x40040018) Port 0 Input/Output Control Register 8 */
\r
1027 __IO uint32_t IOCR12; /*!< (@ 0x4004001C) Port 0 Input/Output Control Register 12 */
\r
1028 __I uint32_t RESERVED1;
\r
1029 __I uint32_t IN; /*!< (@ 0x40040024) Port 0 Input Register */
\r
1030 __I uint32_t RESERVED2[6];
\r
1031 __IO uint32_t PHCR0; /*!< (@ 0x40040040) Port 0 Pad Hysteresis Control Register 0 */
\r
1032 __IO uint32_t PHCR1; /*!< (@ 0x40040044) Port 0 Pad Hysteresis Control Register 1 */
\r
1033 __I uint32_t RESERVED3[6];
\r
1034 __I uint32_t PDISC; /*!< (@ 0x40040060) Port 0 Pin Function Decision Control Register */
\r
1035 __I uint32_t RESERVED4[3];
\r
1036 __IO uint32_t PPS; /*!< (@ 0x40040070) Port 0 Pin Power Save Register */
\r
1037 __IO uint32_t HWSEL; /*!< (@ 0x40040074) Port 0 Pin Hardware Select Register */
\r
1041 /* ================================================================================ */
\r
1042 /* ================ PORT1 ================ */
\r
1043 /* ================================================================================ */
\r
1047 * @brief Port 1 (PORT1)
\r
1050 typedef struct { /*!< (@ 0x40040100) PORT1 Structure */
\r
1051 __IO uint32_t OUT; /*!< (@ 0x40040100) Port 1 Output Register */
\r
1052 __O uint32_t OMR; /*!< (@ 0x40040104) Port 1 Output Modification Register */
\r
1053 __I uint32_t RESERVED0[2];
\r
1054 __IO uint32_t IOCR0; /*!< (@ 0x40040110) Port 1 Input/Output Control Register 0 */
\r
1055 __IO uint32_t IOCR4; /*!< (@ 0x40040114) Port 1 Input/Output Control Register 4 */
\r
1056 __I uint32_t RESERVED1[3];
\r
1057 __I uint32_t IN; /*!< (@ 0x40040124) Port 1 Input Register */
\r
1058 __I uint32_t RESERVED2[6];
\r
1059 __IO uint32_t PHCR0; /*!< (@ 0x40040140) Port 1 Pad Hysteresis Control Register 0 */
\r
1060 __I uint32_t RESERVED3[7];
\r
1061 __I uint32_t PDISC; /*!< (@ 0x40040160) Port 1 Pin Function Decision Control Register */
\r
1062 __I uint32_t RESERVED4[3];
\r
1063 __IO uint32_t PPS; /*!< (@ 0x40040170) Port 1 Pin Power Save Register */
\r
1064 __IO uint32_t HWSEL; /*!< (@ 0x40040174) Port 1 Pin Hardware Select Register */
\r
1068 /* ================================================================================ */
\r
1069 /* ================ PORT2 ================ */
\r
1070 /* ================================================================================ */
\r
1074 * @brief Port 2 (PORT2)
\r
1077 typedef struct { /*!< (@ 0x40040200) PORT2 Structure */
\r
1078 __IO uint32_t OUT; /*!< (@ 0x40040200) Port 2 Output Register */
\r
1079 __O uint32_t OMR; /*!< (@ 0x40040204) Port 2 Output Modification Register */
\r
1080 __I uint32_t RESERVED0[2];
\r
1081 __IO uint32_t IOCR0; /*!< (@ 0x40040210) Port 2 Input/Output Control Register 0 */
\r
1082 __IO uint32_t IOCR4; /*!< (@ 0x40040214) Port 2 Input/Output Control Register 4 */
\r
1083 __IO uint32_t IOCR8; /*!< (@ 0x40040218) Port 2 Input/Output Control Register 8 */
\r
1084 __I uint32_t RESERVED1[2];
\r
1085 __I uint32_t IN; /*!< (@ 0x40040224) Port 2 Input Register */
\r
1086 __I uint32_t RESERVED2[6];
\r
1087 __IO uint32_t PHCR0; /*!< (@ 0x40040240) Port 2 Pad Hysteresis Control Register 0 */
\r
1088 __IO uint32_t PHCR1; /*!< (@ 0x40040244) Port 2 Pad Hysteresis Control Register 1 */
\r
1089 __I uint32_t RESERVED3[6];
\r
1090 __IO uint32_t PDISC; /*!< (@ 0x40040260) Port 2 Pin Function Decision Control Register */
\r
1091 __I uint32_t RESERVED4[3];
\r
1092 __IO uint32_t PPS; /*!< (@ 0x40040270) Port 2 Pin Power Save Register */
\r
1093 __IO uint32_t HWSEL; /*!< (@ 0x40040274) Port 2 Pin Hardware Select Register */
\r
1097 /* -------------------- End of section using anonymous unions ------------------- */
\r
1098 #if defined(__CC_ARM)
\r
1100 #elif defined(__ICCARM__)
\r
1101 /* leave anonymous unions enabled */
\r
1102 #elif defined(__GNUC__)
\r
1103 /* anonymous unions are enabled by default */
\r
1104 #elif defined(__TMS470__)
\r
1105 /* anonymous unions are enabled by default */
\r
1106 #elif defined(__TASKING__)
\r
1107 #pragma warning restore
\r
1109 #warning Not supported compiler type
\r
1114 /* ================================================================================ */
\r
1115 /* ================ struct 'PPB' Position & Mask ================ */
\r
1116 /* ================================================================================ */
\r
1119 /* -------------------------------- PPB_SYST_CSR -------------------------------- */
\r
1120 #define PPB_SYST_CSR_ENABLE_Pos 0 /*!< PPB SYST_CSR: ENABLE Position */
\r
1121 #define PPB_SYST_CSR_ENABLE_Msk (0x01UL << PPB_SYST_CSR_ENABLE_Pos) /*!< PPB SYST_CSR: ENABLE Mask */
\r
1122 #define PPB_SYST_CSR_TICKINT_Pos 1 /*!< PPB SYST_CSR: TICKINT Position */
\r
1123 #define PPB_SYST_CSR_TICKINT_Msk (0x01UL << PPB_SYST_CSR_TICKINT_Pos) /*!< PPB SYST_CSR: TICKINT Mask */
\r
1124 #define PPB_SYST_CSR_CLKSOURCE_Pos 2 /*!< PPB SYST_CSR: CLKSOURCE Position */
\r
1125 #define PPB_SYST_CSR_CLKSOURCE_Msk (0x01UL << PPB_SYST_CSR_CLKSOURCE_Pos) /*!< PPB SYST_CSR: CLKSOURCE Mask */
\r
1126 #define PPB_SYST_CSR_COUNTFLAG_Pos 16 /*!< PPB SYST_CSR: COUNTFLAG Position */
\r
1127 #define PPB_SYST_CSR_COUNTFLAG_Msk (0x01UL << PPB_SYST_CSR_COUNTFLAG_Pos) /*!< PPB SYST_CSR: COUNTFLAG Mask */
\r
1129 /* -------------------------------- PPB_SYST_RVR -------------------------------- */
\r
1130 #define PPB_SYST_RVR_RELOAD_Pos 0 /*!< PPB SYST_RVR: RELOAD Position */
\r
1131 #define PPB_SYST_RVR_RELOAD_Msk (0x00ffffffUL << PPB_SYST_RVR_RELOAD_Pos) /*!< PPB SYST_RVR: RELOAD Mask */
\r
1133 /* -------------------------------- PPB_SYST_CVR -------------------------------- */
\r
1134 #define PPB_SYST_CVR_CURRENT_Pos 0 /*!< PPB SYST_CVR: CURRENT Position */
\r
1135 #define PPB_SYST_CVR_CURRENT_Msk (0x00ffffffUL << PPB_SYST_CVR_CURRENT_Pos) /*!< PPB SYST_CVR: CURRENT Mask */
\r
1137 /* ------------------------------- PPB_SYST_CALIB ------------------------------- */
\r
1138 #define PPB_SYST_CALIB_TENMS_Pos 0 /*!< PPB SYST_CALIB: TENMS Position */
\r
1139 #define PPB_SYST_CALIB_TENMS_Msk (0x00ffffffUL << PPB_SYST_CALIB_TENMS_Pos) /*!< PPB SYST_CALIB: TENMS Mask */
\r
1140 #define PPB_SYST_CALIB_SKEW_Pos 30 /*!< PPB SYST_CALIB: SKEW Position */
\r
1141 #define PPB_SYST_CALIB_SKEW_Msk (0x01UL << PPB_SYST_CALIB_SKEW_Pos) /*!< PPB SYST_CALIB: SKEW Mask */
\r
1142 #define PPB_SYST_CALIB_NOREF_Pos 31 /*!< PPB SYST_CALIB: NOREF Position */
\r
1143 #define PPB_SYST_CALIB_NOREF_Msk (0x01UL << PPB_SYST_CALIB_NOREF_Pos) /*!< PPB SYST_CALIB: NOREF Mask */
\r
1145 /* -------------------------------- PPB_NVIC_ISER ------------------------------- */
\r
1146 #define PPB_NVIC_ISER_SETENA_Pos 0 /*!< PPB NVIC_ISER: SETENA Position */
\r
1147 #define PPB_NVIC_ISER_SETENA_Msk (0xffffffffUL << PPB_NVIC_ISER_SETENA_Pos) /*!< PPB NVIC_ISER: SETENA Mask */
\r
1149 /* -------------------------------- PPB_NVIC_ICER ------------------------------- */
\r
1150 #define PPB_NVIC_ICER_CLRENA_Pos 0 /*!< PPB NVIC_ICER: CLRENA Position */
\r
1151 #define PPB_NVIC_ICER_CLRENA_Msk (0xffffffffUL << PPB_NVIC_ICER_CLRENA_Pos) /*!< PPB NVIC_ICER: CLRENA Mask */
\r
1153 /* -------------------------------- PPB_NVIC_ISPR ------------------------------- */
\r
1154 #define PPB_NVIC_ISPR_SETPEND_Pos 0 /*!< PPB NVIC_ISPR: SETPEND Position */
\r
1155 #define PPB_NVIC_ISPR_SETPEND_Msk (0xffffffffUL << PPB_NVIC_ISPR_SETPEND_Pos) /*!< PPB NVIC_ISPR: SETPEND Mask */
\r
1157 /* -------------------------------- PPB_NVIC_ICPR ------------------------------- */
\r
1158 #define PPB_NVIC_ICPR_CLRPEND_Pos 0 /*!< PPB NVIC_ICPR: CLRPEND Position */
\r
1159 #define PPB_NVIC_ICPR_CLRPEND_Msk (0xffffffffUL << PPB_NVIC_ICPR_CLRPEND_Pos) /*!< PPB NVIC_ICPR: CLRPEND Mask */
\r
1161 /* -------------------------------- PPB_NVIC_IPR0 ------------------------------- */
\r
1162 #define PPB_NVIC_IPR0_PRI_0_Pos 0 /*!< PPB NVIC_IPR0: PRI_0 Position */
\r
1163 #define PPB_NVIC_IPR0_PRI_0_Msk (0x000000ffUL << PPB_NVIC_IPR0_PRI_0_Pos) /*!< PPB NVIC_IPR0: PRI_0 Mask */
\r
1164 #define PPB_NVIC_IPR0_PRI_1_Pos 8 /*!< PPB NVIC_IPR0: PRI_1 Position */
\r
1165 #define PPB_NVIC_IPR0_PRI_1_Msk (0x000000ffUL << PPB_NVIC_IPR0_PRI_1_Pos) /*!< PPB NVIC_IPR0: PRI_1 Mask */
\r
1166 #define PPB_NVIC_IPR0_PRI_2_Pos 16 /*!< PPB NVIC_IPR0: PRI_2 Position */
\r
1167 #define PPB_NVIC_IPR0_PRI_2_Msk (0x000000ffUL << PPB_NVIC_IPR0_PRI_2_Pos) /*!< PPB NVIC_IPR0: PRI_2 Mask */
\r
1168 #define PPB_NVIC_IPR0_PRI_3_Pos 24 /*!< PPB NVIC_IPR0: PRI_3 Position */
\r
1169 #define PPB_NVIC_IPR0_PRI_3_Msk (0x000000ffUL << PPB_NVIC_IPR0_PRI_3_Pos) /*!< PPB NVIC_IPR0: PRI_3 Mask */
\r
1171 /* -------------------------------- PPB_NVIC_IPR1 ------------------------------- */
\r
1172 #define PPB_NVIC_IPR1_PRI_0_Pos 0 /*!< PPB NVIC_IPR1: PRI_0 Position */
\r
1173 #define PPB_NVIC_IPR1_PRI_0_Msk (0x000000ffUL << PPB_NVIC_IPR1_PRI_0_Pos) /*!< PPB NVIC_IPR1: PRI_0 Mask */
\r
1174 #define PPB_NVIC_IPR1_PRI_1_Pos 8 /*!< PPB NVIC_IPR1: PRI_1 Position */
\r
1175 #define PPB_NVIC_IPR1_PRI_1_Msk (0x000000ffUL << PPB_NVIC_IPR1_PRI_1_Pos) /*!< PPB NVIC_IPR1: PRI_1 Mask */
\r
1176 #define PPB_NVIC_IPR1_PRI_2_Pos 16 /*!< PPB NVIC_IPR1: PRI_2 Position */
\r
1177 #define PPB_NVIC_IPR1_PRI_2_Msk (0x000000ffUL << PPB_NVIC_IPR1_PRI_2_Pos) /*!< PPB NVIC_IPR1: PRI_2 Mask */
\r
1178 #define PPB_NVIC_IPR1_PRI_3_Pos 24 /*!< PPB NVIC_IPR1: PRI_3 Position */
\r
1179 #define PPB_NVIC_IPR1_PRI_3_Msk (0x000000ffUL << PPB_NVIC_IPR1_PRI_3_Pos) /*!< PPB NVIC_IPR1: PRI_3 Mask */
\r
1181 /* -------------------------------- PPB_NVIC_IPR2 ------------------------------- */
\r
1182 #define PPB_NVIC_IPR2_PRI_0_Pos 0 /*!< PPB NVIC_IPR2: PRI_0 Position */
\r
1183 #define PPB_NVIC_IPR2_PRI_0_Msk (0x000000ffUL << PPB_NVIC_IPR2_PRI_0_Pos) /*!< PPB NVIC_IPR2: PRI_0 Mask */
\r
1184 #define PPB_NVIC_IPR2_PRI_1_Pos 8 /*!< PPB NVIC_IPR2: PRI_1 Position */
\r
1185 #define PPB_NVIC_IPR2_PRI_1_Msk (0x000000ffUL << PPB_NVIC_IPR2_PRI_1_Pos) /*!< PPB NVIC_IPR2: PRI_1 Mask */
\r
1186 #define PPB_NVIC_IPR2_PRI_2_Pos 16 /*!< PPB NVIC_IPR2: PRI_2 Position */
\r
1187 #define PPB_NVIC_IPR2_PRI_2_Msk (0x000000ffUL << PPB_NVIC_IPR2_PRI_2_Pos) /*!< PPB NVIC_IPR2: PRI_2 Mask */
\r
1188 #define PPB_NVIC_IPR2_PRI_3_Pos 24 /*!< PPB NVIC_IPR2: PRI_3 Position */
\r
1189 #define PPB_NVIC_IPR2_PRI_3_Msk (0x000000ffUL << PPB_NVIC_IPR2_PRI_3_Pos) /*!< PPB NVIC_IPR2: PRI_3 Mask */
\r
1191 /* -------------------------------- PPB_NVIC_IPR3 ------------------------------- */
\r
1192 #define PPB_NVIC_IPR3_PRI_0_Pos 0 /*!< PPB NVIC_IPR3: PRI_0 Position */
\r
1193 #define PPB_NVIC_IPR3_PRI_0_Msk (0x000000ffUL << PPB_NVIC_IPR3_PRI_0_Pos) /*!< PPB NVIC_IPR3: PRI_0 Mask */
\r
1194 #define PPB_NVIC_IPR3_PRI_1_Pos 8 /*!< PPB NVIC_IPR3: PRI_1 Position */
\r
1195 #define PPB_NVIC_IPR3_PRI_1_Msk (0x000000ffUL << PPB_NVIC_IPR3_PRI_1_Pos) /*!< PPB NVIC_IPR3: PRI_1 Mask */
\r
1196 #define PPB_NVIC_IPR3_PRI_2_Pos 16 /*!< PPB NVIC_IPR3: PRI_2 Position */
\r
1197 #define PPB_NVIC_IPR3_PRI_2_Msk (0x000000ffUL << PPB_NVIC_IPR3_PRI_2_Pos) /*!< PPB NVIC_IPR3: PRI_2 Mask */
\r
1198 #define PPB_NVIC_IPR3_PRI_3_Pos 24 /*!< PPB NVIC_IPR3: PRI_3 Position */
\r
1199 #define PPB_NVIC_IPR3_PRI_3_Msk (0x000000ffUL << PPB_NVIC_IPR3_PRI_3_Pos) /*!< PPB NVIC_IPR3: PRI_3 Mask */
\r
1201 /* -------------------------------- PPB_NVIC_IPR4 ------------------------------- */
\r
1202 #define PPB_NVIC_IPR4_PRI_0_Pos 0 /*!< PPB NVIC_IPR4: PRI_0 Position */
\r
1203 #define PPB_NVIC_IPR4_PRI_0_Msk (0x000000ffUL << PPB_NVIC_IPR4_PRI_0_Pos) /*!< PPB NVIC_IPR4: PRI_0 Mask */
\r
1204 #define PPB_NVIC_IPR4_PRI_1_Pos 8 /*!< PPB NVIC_IPR4: PRI_1 Position */
\r
1205 #define PPB_NVIC_IPR4_PRI_1_Msk (0x000000ffUL << PPB_NVIC_IPR4_PRI_1_Pos) /*!< PPB NVIC_IPR4: PRI_1 Mask */
\r
1206 #define PPB_NVIC_IPR4_PRI_2_Pos 16 /*!< PPB NVIC_IPR4: PRI_2 Position */
\r
1207 #define PPB_NVIC_IPR4_PRI_2_Msk (0x000000ffUL << PPB_NVIC_IPR4_PRI_2_Pos) /*!< PPB NVIC_IPR4: PRI_2 Mask */
\r
1208 #define PPB_NVIC_IPR4_PRI_3_Pos 24 /*!< PPB NVIC_IPR4: PRI_3 Position */
\r
1209 #define PPB_NVIC_IPR4_PRI_3_Msk (0x000000ffUL << PPB_NVIC_IPR4_PRI_3_Pos) /*!< PPB NVIC_IPR4: PRI_3 Mask */
\r
1211 /* -------------------------------- PPB_NVIC_IPR5 ------------------------------- */
\r
1212 #define PPB_NVIC_IPR5_PRI_0_Pos 0 /*!< PPB NVIC_IPR5: PRI_0 Position */
\r
1213 #define PPB_NVIC_IPR5_PRI_0_Msk (0x000000ffUL << PPB_NVIC_IPR5_PRI_0_Pos) /*!< PPB NVIC_IPR5: PRI_0 Mask */
\r
1214 #define PPB_NVIC_IPR5_PRI_1_Pos 8 /*!< PPB NVIC_IPR5: PRI_1 Position */
\r
1215 #define PPB_NVIC_IPR5_PRI_1_Msk (0x000000ffUL << PPB_NVIC_IPR5_PRI_1_Pos) /*!< PPB NVIC_IPR5: PRI_1 Mask */
\r
1216 #define PPB_NVIC_IPR5_PRI_2_Pos 16 /*!< PPB NVIC_IPR5: PRI_2 Position */
\r
1217 #define PPB_NVIC_IPR5_PRI_2_Msk (0x000000ffUL << PPB_NVIC_IPR5_PRI_2_Pos) /*!< PPB NVIC_IPR5: PRI_2 Mask */
\r
1218 #define PPB_NVIC_IPR5_PRI_3_Pos 24 /*!< PPB NVIC_IPR5: PRI_3 Position */
\r
1219 #define PPB_NVIC_IPR5_PRI_3_Msk (0x000000ffUL << PPB_NVIC_IPR5_PRI_3_Pos) /*!< PPB NVIC_IPR5: PRI_3 Mask */
\r
1221 /* -------------------------------- PPB_NVIC_IPR6 ------------------------------- */
\r
1222 #define PPB_NVIC_IPR6_PRI_0_Pos 0 /*!< PPB NVIC_IPR6: PRI_0 Position */
\r
1223 #define PPB_NVIC_IPR6_PRI_0_Msk (0x000000ffUL << PPB_NVIC_IPR6_PRI_0_Pos) /*!< PPB NVIC_IPR6: PRI_0 Mask */
\r
1224 #define PPB_NVIC_IPR6_PRI_1_Pos 8 /*!< PPB NVIC_IPR6: PRI_1 Position */
\r
1225 #define PPB_NVIC_IPR6_PRI_1_Msk (0x000000ffUL << PPB_NVIC_IPR6_PRI_1_Pos) /*!< PPB NVIC_IPR6: PRI_1 Mask */
\r
1226 #define PPB_NVIC_IPR6_PRI_2_Pos 16 /*!< PPB NVIC_IPR6: PRI_2 Position */
\r
1227 #define PPB_NVIC_IPR6_PRI_2_Msk (0x000000ffUL << PPB_NVIC_IPR6_PRI_2_Pos) /*!< PPB NVIC_IPR6: PRI_2 Mask */
\r
1228 #define PPB_NVIC_IPR6_PRI_3_Pos 24 /*!< PPB NVIC_IPR6: PRI_3 Position */
\r
1229 #define PPB_NVIC_IPR6_PRI_3_Msk (0x000000ffUL << PPB_NVIC_IPR6_PRI_3_Pos) /*!< PPB NVIC_IPR6: PRI_3 Mask */
\r
1231 /* -------------------------------- PPB_NVIC_IPR7 ------------------------------- */
\r
1232 #define PPB_NVIC_IPR7_PRI_0_Pos 0 /*!< PPB NVIC_IPR7: PRI_0 Position */
\r
1233 #define PPB_NVIC_IPR7_PRI_0_Msk (0x000000ffUL << PPB_NVIC_IPR7_PRI_0_Pos) /*!< PPB NVIC_IPR7: PRI_0 Mask */
\r
1234 #define PPB_NVIC_IPR7_PRI_1_Pos 8 /*!< PPB NVIC_IPR7: PRI_1 Position */
\r
1235 #define PPB_NVIC_IPR7_PRI_1_Msk (0x000000ffUL << PPB_NVIC_IPR7_PRI_1_Pos) /*!< PPB NVIC_IPR7: PRI_1 Mask */
\r
1236 #define PPB_NVIC_IPR7_PRI_2_Pos 16 /*!< PPB NVIC_IPR7: PRI_2 Position */
\r
1237 #define PPB_NVIC_IPR7_PRI_2_Msk (0x000000ffUL << PPB_NVIC_IPR7_PRI_2_Pos) /*!< PPB NVIC_IPR7: PRI_2 Mask */
\r
1238 #define PPB_NVIC_IPR7_PRI_3_Pos 24 /*!< PPB NVIC_IPR7: PRI_3 Position */
\r
1239 #define PPB_NVIC_IPR7_PRI_3_Msk (0x000000ffUL << PPB_NVIC_IPR7_PRI_3_Pos) /*!< PPB NVIC_IPR7: PRI_3 Mask */
\r
1241 /* ---------------------------------- PPB_CPUID --------------------------------- */
\r
1242 #define PPB_CPUID_Revision_Pos 0 /*!< PPB CPUID: Revision Position */
\r
1243 #define PPB_CPUID_Revision_Msk (0x0fUL << PPB_CPUID_Revision_Pos) /*!< PPB CPUID: Revision Mask */
\r
1244 #define PPB_CPUID_PartNo_Pos 4 /*!< PPB CPUID: PartNo Position */
\r
1245 #define PPB_CPUID_PartNo_Msk (0x00000fffUL << PPB_CPUID_PartNo_Pos) /*!< PPB CPUID: PartNo Mask */
\r
1246 #define PPB_CPUID_Architecture_Pos 16 /*!< PPB CPUID: Architecture Position */
\r
1247 #define PPB_CPUID_Architecture_Msk (0x0fUL << PPB_CPUID_Architecture_Pos) /*!< PPB CPUID: Architecture Mask */
\r
1248 #define PPB_CPUID_Variant_Pos 20 /*!< PPB CPUID: Variant Position */
\r
1249 #define PPB_CPUID_Variant_Msk (0x0fUL << PPB_CPUID_Variant_Pos) /*!< PPB CPUID: Variant Mask */
\r
1250 #define PPB_CPUID_Implementer_Pos 24 /*!< PPB CPUID: Implementer Position */
\r
1251 #define PPB_CPUID_Implementer_Msk (0x000000ffUL << PPB_CPUID_Implementer_Pos) /*!< PPB CPUID: Implementer Mask */
\r
1253 /* ---------------------------------- PPB_ICSR ---------------------------------- */
\r
1254 #define PPB_ICSR_VECTACTIVE_Pos 0 /*!< PPB ICSR: VECTACTIVE Position */
\r
1255 #define PPB_ICSR_VECTACTIVE_Msk (0x3fUL << PPB_ICSR_VECTACTIVE_Pos) /*!< PPB ICSR: VECTACTIVE Mask */
\r
1256 #define PPB_ICSR_VECTPENDING_Pos 12 /*!< PPB ICSR: VECTPENDING Position */
\r
1257 #define PPB_ICSR_VECTPENDING_Msk (0x3fUL << PPB_ICSR_VECTPENDING_Pos) /*!< PPB ICSR: VECTPENDING Mask */
\r
1258 #define PPB_ICSR_ISRPENDING_Pos 22 /*!< PPB ICSR: ISRPENDING Position */
\r
1259 #define PPB_ICSR_ISRPENDING_Msk (0x01UL << PPB_ICSR_ISRPENDING_Pos) /*!< PPB ICSR: ISRPENDING Mask */
\r
1260 #define PPB_ICSR_PENDSTCLR_Pos 25 /*!< PPB ICSR: PENDSTCLR Position */
\r
1261 #define PPB_ICSR_PENDSTCLR_Msk (0x01UL << PPB_ICSR_PENDSTCLR_Pos) /*!< PPB ICSR: PENDSTCLR Mask */
\r
1262 #define PPB_ICSR_PENDSTSET_Pos 26 /*!< PPB ICSR: PENDSTSET Position */
\r
1263 #define PPB_ICSR_PENDSTSET_Msk (0x01UL << PPB_ICSR_PENDSTSET_Pos) /*!< PPB ICSR: PENDSTSET Mask */
\r
1264 #define PPB_ICSR_PENDSVCLR_Pos 27 /*!< PPB ICSR: PENDSVCLR Position */
\r
1265 #define PPB_ICSR_PENDSVCLR_Msk (0x01UL << PPB_ICSR_PENDSVCLR_Pos) /*!< PPB ICSR: PENDSVCLR Mask */
\r
1266 #define PPB_ICSR_PENDSVSET_Pos 28 /*!< PPB ICSR: PENDSVSET Position */
\r
1267 #define PPB_ICSR_PENDSVSET_Msk (0x01UL << PPB_ICSR_PENDSVSET_Pos) /*!< PPB ICSR: PENDSVSET Mask */
\r
1269 /* ---------------------------------- PPB_AIRCR --------------------------------- */
\r
1270 #define PPB_AIRCR_SYSRESETREQ_Pos 2 /*!< PPB AIRCR: SYSRESETREQ Position */
\r
1271 #define PPB_AIRCR_SYSRESETREQ_Msk (0x01UL << PPB_AIRCR_SYSRESETREQ_Pos) /*!< PPB AIRCR: SYSRESETREQ Mask */
\r
1272 #define PPB_AIRCR_ENDIANNESS_Pos 15 /*!< PPB AIRCR: ENDIANNESS Position */
\r
1273 #define PPB_AIRCR_ENDIANNESS_Msk (0x01UL << PPB_AIRCR_ENDIANNESS_Pos) /*!< PPB AIRCR: ENDIANNESS Mask */
\r
1274 #define PPB_AIRCR_VECTKEY_Pos 16 /*!< PPB AIRCR: VECTKEY Position */
\r
1275 #define PPB_AIRCR_VECTKEY_Msk (0x0000ffffUL << PPB_AIRCR_VECTKEY_Pos) /*!< PPB AIRCR: VECTKEY Mask */
\r
1277 /* ----------------------------------- PPB_SCR ---------------------------------- */
\r
1278 #define PPB_SCR_SLEEPONEXIT_Pos 1 /*!< PPB SCR: SLEEPONEXIT Position */
\r
1279 #define PPB_SCR_SLEEPONEXIT_Msk (0x01UL << PPB_SCR_SLEEPONEXIT_Pos) /*!< PPB SCR: SLEEPONEXIT Mask */
\r
1280 #define PPB_SCR_SLEEPDEEP_Pos 2 /*!< PPB SCR: SLEEPDEEP Position */
\r
1281 #define PPB_SCR_SLEEPDEEP_Msk (0x01UL << PPB_SCR_SLEEPDEEP_Pos) /*!< PPB SCR: SLEEPDEEP Mask */
\r
1282 #define PPB_SCR_SEVONPEND_Pos 4 /*!< PPB SCR: SEVONPEND Position */
\r
1283 #define PPB_SCR_SEVONPEND_Msk (0x01UL << PPB_SCR_SEVONPEND_Pos) /*!< PPB SCR: SEVONPEND Mask */
\r
1285 /* ----------------------------------- PPB_CCR ---------------------------------- */
\r
1286 #define PPB_CCR_UNALIGN_TRP_Pos 3 /*!< PPB CCR: UNALIGN_TRP Position */
\r
1287 #define PPB_CCR_UNALIGN_TRP_Msk (0x01UL << PPB_CCR_UNALIGN_TRP_Pos) /*!< PPB CCR: UNALIGN_TRP Mask */
\r
1288 #define PPB_CCR_STKALIGN_Pos 9 /*!< PPB CCR: STKALIGN Position */
\r
1289 #define PPB_CCR_STKALIGN_Msk (0x01UL << PPB_CCR_STKALIGN_Pos) /*!< PPB CCR: STKALIGN Mask */
\r
1291 /* ---------------------------------- PPB_SHPR2 --------------------------------- */
\r
1292 #define PPB_SHPR2_PRI_11_Pos 24 /*!< PPB SHPR2: PRI_11 Position */
\r
1293 #define PPB_SHPR2_PRI_11_Msk (0x000000ffUL << PPB_SHPR2_PRI_11_Pos) /*!< PPB SHPR2: PRI_11 Mask */
\r
1295 /* ---------------------------------- PPB_SHPR3 --------------------------------- */
\r
1296 #define PPB_SHPR3_PRI_14_Pos 16 /*!< PPB SHPR3: PRI_14 Position */
\r
1297 #define PPB_SHPR3_PRI_14_Msk (0x000000ffUL << PPB_SHPR3_PRI_14_Pos) /*!< PPB SHPR3: PRI_14 Mask */
\r
1298 #define PPB_SHPR3_PRI_15_Pos 24 /*!< PPB SHPR3: PRI_15 Position */
\r
1299 #define PPB_SHPR3_PRI_15_Msk (0x000000ffUL << PPB_SHPR3_PRI_15_Pos) /*!< PPB SHPR3: PRI_15 Mask */
\r
1301 /* ---------------------------------- PPB_SHCSR --------------------------------- */
\r
1302 #define PPB_SHCSR_SVCALLPENDED_Pos 15 /*!< PPB SHCSR: SVCALLPENDED Position */
\r
1303 #define PPB_SHCSR_SVCALLPENDED_Msk (0x01UL << PPB_SHCSR_SVCALLPENDED_Pos) /*!< PPB SHCSR: SVCALLPENDED Mask */
\r
1306 /* ================================================================================ */
\r
1307 /* ================ Group 'ERU' Position & Mask ================ */
\r
1308 /* ================================================================================ */
\r
1311 /* --------------------------------- ERU_EXISEL --------------------------------- */
\r
1312 #define ERU_EXISEL_EXS0A_Pos 0 /*!< ERU EXISEL: EXS0A Position */
\r
1313 #define ERU_EXISEL_EXS0A_Msk (0x03UL << ERU_EXISEL_EXS0A_Pos) /*!< ERU EXISEL: EXS0A Mask */
\r
1314 #define ERU_EXISEL_EXS0B_Pos 2 /*!< ERU EXISEL: EXS0B Position */
\r
1315 #define ERU_EXISEL_EXS0B_Msk (0x03UL << ERU_EXISEL_EXS0B_Pos) /*!< ERU EXISEL: EXS0B Mask */
\r
1316 #define ERU_EXISEL_EXS1A_Pos 4 /*!< ERU EXISEL: EXS1A Position */
\r
1317 #define ERU_EXISEL_EXS1A_Msk (0x03UL << ERU_EXISEL_EXS1A_Pos) /*!< ERU EXISEL: EXS1A Mask */
\r
1318 #define ERU_EXISEL_EXS1B_Pos 6 /*!< ERU EXISEL: EXS1B Position */
\r
1319 #define ERU_EXISEL_EXS1B_Msk (0x03UL << ERU_EXISEL_EXS1B_Pos) /*!< ERU EXISEL: EXS1B Mask */
\r
1320 #define ERU_EXISEL_EXS2A_Pos 8 /*!< ERU EXISEL: EXS2A Position */
\r
1321 #define ERU_EXISEL_EXS2A_Msk (0x03UL << ERU_EXISEL_EXS2A_Pos) /*!< ERU EXISEL: EXS2A Mask */
\r
1322 #define ERU_EXISEL_EXS2B_Pos 10 /*!< ERU EXISEL: EXS2B Position */
\r
1323 #define ERU_EXISEL_EXS2B_Msk (0x03UL << ERU_EXISEL_EXS2B_Pos) /*!< ERU EXISEL: EXS2B Mask */
\r
1324 #define ERU_EXISEL_EXS3A_Pos 12 /*!< ERU EXISEL: EXS3A Position */
\r
1325 #define ERU_EXISEL_EXS3A_Msk (0x03UL << ERU_EXISEL_EXS3A_Pos) /*!< ERU EXISEL: EXS3A Mask */
\r
1326 #define ERU_EXISEL_EXS3B_Pos 14 /*!< ERU EXISEL: EXS3B Position */
\r
1327 #define ERU_EXISEL_EXS3B_Msk (0x03UL << ERU_EXISEL_EXS3B_Pos) /*!< ERU EXISEL: EXS3B Mask */
\r
1329 /* --------------------------------- ERU_EXICON --------------------------------- */
\r
1330 #define ERU_EXICON_PE_Pos 0 /*!< ERU EXICON: PE Position */
\r
1331 #define ERU_EXICON_PE_Msk (0x01UL << ERU_EXICON_PE_Pos) /*!< ERU EXICON: PE Mask */
\r
1332 #define ERU_EXICON_LD_Pos 1 /*!< ERU EXICON: LD Position */
\r
1333 #define ERU_EXICON_LD_Msk (0x01UL << ERU_EXICON_LD_Pos) /*!< ERU EXICON: LD Mask */
\r
1334 #define ERU_EXICON_RE_Pos 2 /*!< ERU EXICON: RE Position */
\r
1335 #define ERU_EXICON_RE_Msk (0x01UL << ERU_EXICON_RE_Pos) /*!< ERU EXICON: RE Mask */
\r
1336 #define ERU_EXICON_FE_Pos 3 /*!< ERU EXICON: FE Position */
\r
1337 #define ERU_EXICON_FE_Msk (0x01UL << ERU_EXICON_FE_Pos) /*!< ERU EXICON: FE Mask */
\r
1338 #define ERU_EXICON_OCS_Pos 4 /*!< ERU EXICON: OCS Position */
\r
1339 #define ERU_EXICON_OCS_Msk (0x07UL << ERU_EXICON_OCS_Pos) /*!< ERU EXICON: OCS Mask */
\r
1340 #define ERU_EXICON_FL_Pos 7 /*!< ERU EXICON: FL Position */
\r
1341 #define ERU_EXICON_FL_Msk (0x01UL << ERU_EXICON_FL_Pos) /*!< ERU EXICON: FL Mask */
\r
1342 #define ERU_EXICON_SS_Pos 8 /*!< ERU EXICON: SS Position */
\r
1343 #define ERU_EXICON_SS_Msk (0x03UL << ERU_EXICON_SS_Pos) /*!< ERU EXICON: SS Mask */
\r
1344 #define ERU_EXICON_NA_Pos 10 /*!< ERU EXICON: NA Position */
\r
1345 #define ERU_EXICON_NA_Msk (0x01UL << ERU_EXICON_NA_Pos) /*!< ERU EXICON: NA Mask */
\r
1346 #define ERU_EXICON_NB_Pos 11 /*!< ERU EXICON: NB Position */
\r
1347 #define ERU_EXICON_NB_Msk (0x01UL << ERU_EXICON_NB_Pos) /*!< ERU EXICON: NB Mask */
\r
1349 /* --------------------------------- ERU_EXOCON --------------------------------- */
\r
1350 #define ERU_EXOCON_ISS_Pos 0 /*!< ERU EXOCON: ISS Position */
\r
1351 #define ERU_EXOCON_ISS_Msk (0x03UL << ERU_EXOCON_ISS_Pos) /*!< ERU EXOCON: ISS Mask */
\r
1352 #define ERU_EXOCON_GEEN_Pos 2 /*!< ERU EXOCON: GEEN Position */
\r
1353 #define ERU_EXOCON_GEEN_Msk (0x01UL << ERU_EXOCON_GEEN_Pos) /*!< ERU EXOCON: GEEN Mask */
\r
1354 #define ERU_EXOCON_PDR_Pos 3 /*!< ERU EXOCON: PDR Position */
\r
1355 #define ERU_EXOCON_PDR_Msk (0x01UL << ERU_EXOCON_PDR_Pos) /*!< ERU EXOCON: PDR Mask */
\r
1356 #define ERU_EXOCON_GP_Pos 4 /*!< ERU EXOCON: GP Position */
\r
1357 #define ERU_EXOCON_GP_Msk (0x03UL << ERU_EXOCON_GP_Pos) /*!< ERU EXOCON: GP Mask */
\r
1358 #define ERU_EXOCON_IPEN0_Pos 12 /*!< ERU EXOCON: IPEN0 Position */
\r
1359 #define ERU_EXOCON_IPEN0_Msk (0x01UL << ERU_EXOCON_IPEN0_Pos) /*!< ERU EXOCON: IPEN0 Mask */
\r
1360 #define ERU_EXOCON_IPEN1_Pos 13 /*!< ERU EXOCON: IPEN1 Position */
\r
1361 #define ERU_EXOCON_IPEN1_Msk (0x01UL << ERU_EXOCON_IPEN1_Pos) /*!< ERU EXOCON: IPEN1 Mask */
\r
1362 #define ERU_EXOCON_IPEN2_Pos 14 /*!< ERU EXOCON: IPEN2 Position */
\r
1363 #define ERU_EXOCON_IPEN2_Msk (0x01UL << ERU_EXOCON_IPEN2_Pos) /*!< ERU EXOCON: IPEN2 Mask */
\r
1364 #define ERU_EXOCON_IPEN3_Pos 15 /*!< ERU EXOCON: IPEN3 Position */
\r
1365 #define ERU_EXOCON_IPEN3_Msk (0x01UL << ERU_EXOCON_IPEN3_Pos) /*!< ERU EXOCON: IPEN3 Mask */
\r
1368 /* ================================================================================ */
\r
1369 /* ================ struct 'MATH' Position & Mask ================ */
\r
1370 /* ================================================================================ */
\r
1373 /* --------------------------------- MATH_GLBCON -------------------------------- */
\r
1374 #define MATH_GLBCON_DVDRC_Pos 0 /*!< MATH GLBCON: DVDRC Position */
\r
1375 #define MATH_GLBCON_DVDRC_Msk (0x07UL << MATH_GLBCON_DVDRC_Pos) /*!< MATH GLBCON: DVDRC Mask */
\r
1376 #define MATH_GLBCON_DVSRC_Pos 3 /*!< MATH GLBCON: DVSRC Position */
\r
1377 #define MATH_GLBCON_DVSRC_Msk (0x07UL << MATH_GLBCON_DVSRC_Pos) /*!< MATH GLBCON: DVSRC Mask */
\r
1378 #define MATH_GLBCON_CORDXRC_Pos 6 /*!< MATH GLBCON: CORDXRC Position */
\r
1379 #define MATH_GLBCON_CORDXRC_Msk (0x03UL << MATH_GLBCON_CORDXRC_Pos) /*!< MATH GLBCON: CORDXRC Mask */
\r
1380 #define MATH_GLBCON_CORDYRC_Pos 9 /*!< MATH GLBCON: CORDYRC Position */
\r
1381 #define MATH_GLBCON_CORDYRC_Msk (0x03UL << MATH_GLBCON_CORDYRC_Pos) /*!< MATH GLBCON: CORDYRC Mask */
\r
1382 #define MATH_GLBCON_CORDZRC_Pos 12 /*!< MATH GLBCON: CORDZRC Position */
\r
1383 #define MATH_GLBCON_CORDZRC_Msk (0x03UL << MATH_GLBCON_CORDZRC_Pos) /*!< MATH GLBCON: CORDZRC Mask */
\r
1384 #define MATH_GLBCON_SUSCFG_Pos 16 /*!< MATH GLBCON: SUSCFG Position */
\r
1385 #define MATH_GLBCON_SUSCFG_Msk (0x03UL << MATH_GLBCON_SUSCFG_Pos) /*!< MATH GLBCON: SUSCFG Mask */
\r
1387 /* ----------------------------------- MATH_ID ---------------------------------- */
\r
1388 #define MATH_ID_MOD_REV_Pos 0 /*!< MATH ID: MOD_REV Position */
\r
1389 #define MATH_ID_MOD_REV_Msk (0x000000ffUL << MATH_ID_MOD_REV_Pos) /*!< MATH ID: MOD_REV Mask */
\r
1390 #define MATH_ID_MOD_TYPE_Pos 8 /*!< MATH ID: MOD_TYPE Position */
\r
1391 #define MATH_ID_MOD_TYPE_Msk (0x000000ffUL << MATH_ID_MOD_TYPE_Pos) /*!< MATH ID: MOD_TYPE Mask */
\r
1392 #define MATH_ID_MOD_NUMBER_Pos 16 /*!< MATH ID: MOD_NUMBER Position */
\r
1393 #define MATH_ID_MOD_NUMBER_Msk (0x0000ffffUL << MATH_ID_MOD_NUMBER_Pos) /*!< MATH ID: MOD_NUMBER Mask */
\r
1395 /* --------------------------------- MATH_EVIER --------------------------------- */
\r
1396 #define MATH_EVIER_DIVEOCIEN_Pos 0 /*!< MATH EVIER: DIVEOCIEN Position */
\r
1397 #define MATH_EVIER_DIVEOCIEN_Msk (0x01UL << MATH_EVIER_DIVEOCIEN_Pos) /*!< MATH EVIER: DIVEOCIEN Mask */
\r
1398 #define MATH_EVIER_DIVERRIEN_Pos 1 /*!< MATH EVIER: DIVERRIEN Position */
\r
1399 #define MATH_EVIER_DIVERRIEN_Msk (0x01UL << MATH_EVIER_DIVERRIEN_Pos) /*!< MATH EVIER: DIVERRIEN Mask */
\r
1400 #define MATH_EVIER_CDEOCIEN_Pos 2 /*!< MATH EVIER: CDEOCIEN Position */
\r
1401 #define MATH_EVIER_CDEOCIEN_Msk (0x01UL << MATH_EVIER_CDEOCIEN_Pos) /*!< MATH EVIER: CDEOCIEN Mask */
\r
1402 #define MATH_EVIER_CDERRIEN_Pos 3 /*!< MATH EVIER: CDERRIEN Position */
\r
1403 #define MATH_EVIER_CDERRIEN_Msk (0x01UL << MATH_EVIER_CDERRIEN_Pos) /*!< MATH EVIER: CDERRIEN Mask */
\r
1405 /* ---------------------------------- MATH_EVFR --------------------------------- */
\r
1406 #define MATH_EVFR_DIVEOC_Pos 0 /*!< MATH EVFR: DIVEOC Position */
\r
1407 #define MATH_EVFR_DIVEOC_Msk (0x01UL << MATH_EVFR_DIVEOC_Pos) /*!< MATH EVFR: DIVEOC Mask */
\r
1408 #define MATH_EVFR_DIVERR_Pos 1 /*!< MATH EVFR: DIVERR Position */
\r
1409 #define MATH_EVFR_DIVERR_Msk (0x01UL << MATH_EVFR_DIVERR_Pos) /*!< MATH EVFR: DIVERR Mask */
\r
1410 #define MATH_EVFR_CDEOC_Pos 2 /*!< MATH EVFR: CDEOC Position */
\r
1411 #define MATH_EVFR_CDEOC_Msk (0x01UL << MATH_EVFR_CDEOC_Pos) /*!< MATH EVFR: CDEOC Mask */
\r
1412 #define MATH_EVFR_CDERR_Pos 3 /*!< MATH EVFR: CDERR Position */
\r
1413 #define MATH_EVFR_CDERR_Msk (0x01UL << MATH_EVFR_CDERR_Pos) /*!< MATH EVFR: CDERR Mask */
\r
1415 /* --------------------------------- MATH_EVFSR --------------------------------- */
\r
1416 #define MATH_EVFSR_DIVEOCS_Pos 0 /*!< MATH EVFSR: DIVEOCS Position */
\r
1417 #define MATH_EVFSR_DIVEOCS_Msk (0x01UL << MATH_EVFSR_DIVEOCS_Pos) /*!< MATH EVFSR: DIVEOCS Mask */
\r
1418 #define MATH_EVFSR_DIVERRS_Pos 1 /*!< MATH EVFSR: DIVERRS Position */
\r
1419 #define MATH_EVFSR_DIVERRS_Msk (0x01UL << MATH_EVFSR_DIVERRS_Pos) /*!< MATH EVFSR: DIVERRS Mask */
\r
1420 #define MATH_EVFSR_CDEOCS_Pos 2 /*!< MATH EVFSR: CDEOCS Position */
\r
1421 #define MATH_EVFSR_CDEOCS_Msk (0x01UL << MATH_EVFSR_CDEOCS_Pos) /*!< MATH EVFSR: CDEOCS Mask */
\r
1422 #define MATH_EVFSR_CDERRS_Pos 3 /*!< MATH EVFSR: CDERRS Position */
\r
1423 #define MATH_EVFSR_CDERRS_Msk (0x01UL << MATH_EVFSR_CDERRS_Pos) /*!< MATH EVFSR: CDERRS Mask */
\r
1425 /* --------------------------------- MATH_EVFCR --------------------------------- */
\r
1426 #define MATH_EVFCR_DIVEOCC_Pos 0 /*!< MATH EVFCR: DIVEOCC Position */
\r
1427 #define MATH_EVFCR_DIVEOCC_Msk (0x01UL << MATH_EVFCR_DIVEOCC_Pos) /*!< MATH EVFCR: DIVEOCC Mask */
\r
1428 #define MATH_EVFCR_DIVERRC_Pos 1 /*!< MATH EVFCR: DIVERRC Position */
\r
1429 #define MATH_EVFCR_DIVERRC_Msk (0x01UL << MATH_EVFCR_DIVERRC_Pos) /*!< MATH EVFCR: DIVERRC Mask */
\r
1430 #define MATH_EVFCR_CDEOCC_Pos 2 /*!< MATH EVFCR: CDEOCC Position */
\r
1431 #define MATH_EVFCR_CDEOCC_Msk (0x01UL << MATH_EVFCR_CDEOCC_Pos) /*!< MATH EVFCR: CDEOCC Mask */
\r
1432 #define MATH_EVFCR_CDERRC_Pos 3 /*!< MATH EVFCR: CDERRC Position */
\r
1433 #define MATH_EVFCR_CDERRC_Msk (0x01UL << MATH_EVFCR_CDERRC_Pos) /*!< MATH EVFCR: CDERRC Mask */
\r
1435 /* ---------------------------------- MATH_DVD ---------------------------------- */
\r
1436 #define MATH_DVD_VAL_Pos 0 /*!< MATH DVD: VAL Position */
\r
1437 #define MATH_DVD_VAL_Msk (0xffffffffUL << MATH_DVD_VAL_Pos) /*!< MATH DVD: VAL Mask */
\r
1439 /* ---------------------------------- MATH_DVS ---------------------------------- */
\r
1440 #define MATH_DVS_VAL_Pos 0 /*!< MATH DVS: VAL Position */
\r
1441 #define MATH_DVS_VAL_Msk (0xffffffffUL << MATH_DVS_VAL_Pos) /*!< MATH DVS: VAL Mask */
\r
1443 /* ---------------------------------- MATH_QUOT --------------------------------- */
\r
1444 #define MATH_QUOT_VAL_Pos 0 /*!< MATH QUOT: VAL Position */
\r
1445 #define MATH_QUOT_VAL_Msk (0xffffffffUL << MATH_QUOT_VAL_Pos) /*!< MATH QUOT: VAL Mask */
\r
1447 /* ---------------------------------- MATH_RMD ---------------------------------- */
\r
1448 #define MATH_RMD_VAL_Pos 0 /*!< MATH RMD: VAL Position */
\r
1449 #define MATH_RMD_VAL_Msk (0xffffffffUL << MATH_RMD_VAL_Pos) /*!< MATH RMD: VAL Mask */
\r
1451 /* --------------------------------- MATH_DIVST --------------------------------- */
\r
1452 #define MATH_DIVST_BSY_Pos 0 /*!< MATH DIVST: BSY Position */
\r
1453 #define MATH_DIVST_BSY_Msk (0x01UL << MATH_DIVST_BSY_Pos) /*!< MATH DIVST: BSY Mask */
\r
1455 /* --------------------------------- MATH_DIVCON -------------------------------- */
\r
1456 #define MATH_DIVCON_ST_Pos 0 /*!< MATH DIVCON: ST Position */
\r
1457 #define MATH_DIVCON_ST_Msk (0x01UL << MATH_DIVCON_ST_Pos) /*!< MATH DIVCON: ST Mask */
\r
1458 #define MATH_DIVCON_STMODE_Pos 1 /*!< MATH DIVCON: STMODE Position */
\r
1459 #define MATH_DIVCON_STMODE_Msk (0x01UL << MATH_DIVCON_STMODE_Pos) /*!< MATH DIVCON: STMODE Mask */
\r
1460 #define MATH_DIVCON_USIGN_Pos 2 /*!< MATH DIVCON: USIGN Position */
\r
1461 #define MATH_DIVCON_USIGN_Msk (0x01UL << MATH_DIVCON_USIGN_Pos) /*!< MATH DIVCON: USIGN Mask */
\r
1462 #define MATH_DIVCON_DIVMODE_Pos 3 /*!< MATH DIVCON: DIVMODE Position */
\r
1463 #define MATH_DIVCON_DIVMODE_Msk (0x03UL << MATH_DIVCON_DIVMODE_Pos) /*!< MATH DIVCON: DIVMODE Mask */
\r
1464 #define MATH_DIVCON_QSCNT_Pos 8 /*!< MATH DIVCON: QSCNT Position */
\r
1465 #define MATH_DIVCON_QSCNT_Msk (0x1fUL << MATH_DIVCON_QSCNT_Pos) /*!< MATH DIVCON: QSCNT Mask */
\r
1466 #define MATH_DIVCON_QSDIR_Pos 15 /*!< MATH DIVCON: QSDIR Position */
\r
1467 #define MATH_DIVCON_QSDIR_Msk (0x01UL << MATH_DIVCON_QSDIR_Pos) /*!< MATH DIVCON: QSDIR Mask */
\r
1468 #define MATH_DIVCON_DVDSLC_Pos 16 /*!< MATH DIVCON: DVDSLC Position */
\r
1469 #define MATH_DIVCON_DVDSLC_Msk (0x1fUL << MATH_DIVCON_DVDSLC_Pos) /*!< MATH DIVCON: DVDSLC Mask */
\r
1470 #define MATH_DIVCON_DVSSRC_Pos 24 /*!< MATH DIVCON: DVSSRC Position */
\r
1471 #define MATH_DIVCON_DVSSRC_Msk (0x1fUL << MATH_DIVCON_DVSSRC_Pos) /*!< MATH DIVCON: DVSSRC Mask */
\r
1473 /* --------------------------------- MATH_STATC --------------------------------- */
\r
1474 #define MATH_STATC_BSY_Pos 0 /*!< MATH STATC: BSY Position */
\r
1475 #define MATH_STATC_BSY_Msk (0x01UL << MATH_STATC_BSY_Pos) /*!< MATH STATC: BSY Mask */
\r
1476 #define MATH_STATC_KEEPX_Pos 5 /*!< MATH STATC: KEEPX Position */
\r
1477 #define MATH_STATC_KEEPX_Msk (0x01UL << MATH_STATC_KEEPX_Pos) /*!< MATH STATC: KEEPX Mask */
\r
1478 #define MATH_STATC_KEEPY_Pos 6 /*!< MATH STATC: KEEPY Position */
\r
1479 #define MATH_STATC_KEEPY_Msk (0x01UL << MATH_STATC_KEEPY_Pos) /*!< MATH STATC: KEEPY Mask */
\r
1480 #define MATH_STATC_KEEPZ_Pos 7 /*!< MATH STATC: KEEPZ Position */
\r
1481 #define MATH_STATC_KEEPZ_Msk (0x01UL << MATH_STATC_KEEPZ_Pos) /*!< MATH STATC: KEEPZ Mask */
\r
1483 /* ---------------------------------- MATH_CON ---------------------------------- */
\r
1484 #define MATH_CON_ST_Pos 0 /*!< MATH CON: ST Position */
\r
1485 #define MATH_CON_ST_Msk (0x01UL << MATH_CON_ST_Pos) /*!< MATH CON: ST Mask */
\r
1486 #define MATH_CON_MODE_Pos 1 /*!< MATH CON: MODE Position */
\r
1487 #define MATH_CON_MODE_Msk (0x03UL << MATH_CON_MODE_Pos) /*!< MATH CON: MODE Mask */
\r
1488 #define MATH_CON_ROTVEC_Pos 3 /*!< MATH CON: ROTVEC Position */
\r
1489 #define MATH_CON_ROTVEC_Msk (0x01UL << MATH_CON_ROTVEC_Pos) /*!< MATH CON: ROTVEC Mask */
\r
1490 #define MATH_CON_ST_MODE_Pos 4 /*!< MATH CON: ST_MODE Position */
\r
1491 #define MATH_CON_ST_MODE_Msk (0x01UL << MATH_CON_ST_MODE_Pos) /*!< MATH CON: ST_MODE Mask */
\r
1492 #define MATH_CON_X_USIGN_Pos 5 /*!< MATH CON: X_USIGN Position */
\r
1493 #define MATH_CON_X_USIGN_Msk (0x01UL << MATH_CON_X_USIGN_Pos) /*!< MATH CON: X_USIGN Mask */
\r
1494 #define MATH_CON_MPS_Pos 6 /*!< MATH CON: MPS Position */
\r
1495 #define MATH_CON_MPS_Msk (0x03UL << MATH_CON_MPS_Pos) /*!< MATH CON: MPS Mask */
\r
1497 /* --------------------------------- MATH_CORDX --------------------------------- */
\r
1498 #define MATH_CORDX_DATA_Pos 8 /*!< MATH CORDX: DATA Position */
\r
1499 #define MATH_CORDX_DATA_Msk (0x00ffffffUL << MATH_CORDX_DATA_Pos) /*!< MATH CORDX: DATA Mask */
\r
1501 /* --------------------------------- MATH_CORDY --------------------------------- */
\r
1502 #define MATH_CORDY_DATA_Pos 8 /*!< MATH CORDY: DATA Position */
\r
1503 #define MATH_CORDY_DATA_Msk (0x00ffffffUL << MATH_CORDY_DATA_Pos) /*!< MATH CORDY: DATA Mask */
\r
1505 /* --------------------------------- MATH_CORDZ --------------------------------- */
\r
1506 #define MATH_CORDZ_DATA_Pos 8 /*!< MATH CORDZ: DATA Position */
\r
1507 #define MATH_CORDZ_DATA_Msk (0x00ffffffUL << MATH_CORDZ_DATA_Pos) /*!< MATH CORDZ: DATA Mask */
\r
1509 /* --------------------------------- MATH_CORRX --------------------------------- */
\r
1510 #define MATH_CORRX_RESULT_Pos 8 /*!< MATH CORRX: RESULT Position */
\r
1511 #define MATH_CORRX_RESULT_Msk (0x00ffffffUL << MATH_CORRX_RESULT_Pos) /*!< MATH CORRX: RESULT Mask */
\r
1513 /* --------------------------------- MATH_CORRY --------------------------------- */
\r
1514 #define MATH_CORRY_RESULT_Pos 8 /*!< MATH CORRY: RESULT Position */
\r
1515 #define MATH_CORRY_RESULT_Msk (0x00ffffffUL << MATH_CORRY_RESULT_Pos) /*!< MATH CORRY: RESULT Mask */
\r
1517 /* --------------------------------- MATH_CORRZ --------------------------------- */
\r
1518 #define MATH_CORRZ_RESULT_Pos 8 /*!< MATH CORRZ: RESULT Position */
\r
1519 #define MATH_CORRZ_RESULT_Msk (0x00ffffffUL << MATH_CORRZ_RESULT_Pos) /*!< MATH CORRZ: RESULT Mask */
\r
1522 /* ================================================================================ */
\r
1523 /* ================ struct 'PAU' Position & Mask ================ */
\r
1524 /* ================================================================================ */
\r
1527 /* --------------------------------- PAU_AVAIL0 --------------------------------- */
\r
1528 #define PAU_AVAIL0_AVAIL20_Pos 20 /*!< PAU AVAIL0: AVAIL20 Position */
\r
1529 #define PAU_AVAIL0_AVAIL20_Msk (0x01UL << PAU_AVAIL0_AVAIL20_Pos) /*!< PAU AVAIL0: AVAIL20 Mask */
\r
1530 #define PAU_AVAIL0_AVAIL21_Pos 21 /*!< PAU AVAIL0: AVAIL21 Position */
\r
1531 #define PAU_AVAIL0_AVAIL21_Msk (0x01UL << PAU_AVAIL0_AVAIL21_Pos) /*!< PAU AVAIL0: AVAIL21 Mask */
\r
1532 #define PAU_AVAIL0_AVAIL22_Pos 22 /*!< PAU AVAIL0: AVAIL22 Position */
\r
1533 #define PAU_AVAIL0_AVAIL22_Msk (0x01UL << PAU_AVAIL0_AVAIL22_Pos) /*!< PAU AVAIL0: AVAIL22 Mask */
\r
1534 #define PAU_AVAIL0_AVAIL23_Pos 23 /*!< PAU AVAIL0: AVAIL23 Position */
\r
1535 #define PAU_AVAIL0_AVAIL23_Msk (0x01UL << PAU_AVAIL0_AVAIL23_Pos) /*!< PAU AVAIL0: AVAIL23 Mask */
\r
1536 #define PAU_AVAIL0_AVAIL24_Pos 24 /*!< PAU AVAIL0: AVAIL24 Position */
\r
1537 #define PAU_AVAIL0_AVAIL24_Msk (0x01UL << PAU_AVAIL0_AVAIL24_Pos) /*!< PAU AVAIL0: AVAIL24 Mask */
\r
1539 /* --------------------------------- PAU_AVAIL1 --------------------------------- */
\r
1540 #define PAU_AVAIL1_AVAIL0_Pos 0 /*!< PAU AVAIL1: AVAIL0 Position */
\r
1541 #define PAU_AVAIL1_AVAIL0_Msk (0x01UL << PAU_AVAIL1_AVAIL0_Pos) /*!< PAU AVAIL1: AVAIL0 Mask */
\r
1542 #define PAU_AVAIL1_AVAIL1_Pos 1 /*!< PAU AVAIL1: AVAIL1 Position */
\r
1543 #define PAU_AVAIL1_AVAIL1_Msk (0x01UL << PAU_AVAIL1_AVAIL1_Pos) /*!< PAU AVAIL1: AVAIL1 Mask */
\r
1544 #define PAU_AVAIL1_AVAIL4_Pos 4 /*!< PAU AVAIL1: AVAIL4 Position */
\r
1545 #define PAU_AVAIL1_AVAIL4_Msk (0x01UL << PAU_AVAIL1_AVAIL4_Pos) /*!< PAU AVAIL1: AVAIL4 Mask */
\r
1546 #define PAU_AVAIL1_AVAIL5_Pos 5 /*!< PAU AVAIL1: AVAIL5 Position */
\r
1547 #define PAU_AVAIL1_AVAIL5_Msk (0x01UL << PAU_AVAIL1_AVAIL5_Pos) /*!< PAU AVAIL1: AVAIL5 Mask */
\r
1548 #define PAU_AVAIL1_AVAIL6_Pos 6 /*!< PAU AVAIL1: AVAIL6 Position */
\r
1549 #define PAU_AVAIL1_AVAIL6_Msk (0x01UL << PAU_AVAIL1_AVAIL6_Pos) /*!< PAU AVAIL1: AVAIL6 Mask */
\r
1550 #define PAU_AVAIL1_AVAIL7_Pos 7 /*!< PAU AVAIL1: AVAIL7 Position */
\r
1551 #define PAU_AVAIL1_AVAIL7_Msk (0x01UL << PAU_AVAIL1_AVAIL7_Pos) /*!< PAU AVAIL1: AVAIL7 Mask */
\r
1552 #define PAU_AVAIL1_AVAIL8_Pos 8 /*!< PAU AVAIL1: AVAIL8 Position */
\r
1553 #define PAU_AVAIL1_AVAIL8_Msk (0x01UL << PAU_AVAIL1_AVAIL8_Pos) /*!< PAU AVAIL1: AVAIL8 Mask */
\r
1554 #define PAU_AVAIL1_AVAIL9_Pos 9 /*!< PAU AVAIL1: AVAIL9 Position */
\r
1555 #define PAU_AVAIL1_AVAIL9_Msk (0x01UL << PAU_AVAIL1_AVAIL9_Pos) /*!< PAU AVAIL1: AVAIL9 Mask */
\r
1556 #define PAU_AVAIL1_AVAIL10_Pos 10 /*!< PAU AVAIL1: AVAIL10 Position */
\r
1557 #define PAU_AVAIL1_AVAIL10_Msk (0x01UL << PAU_AVAIL1_AVAIL10_Pos) /*!< PAU AVAIL1: AVAIL10 Mask */
\r
1558 #define PAU_AVAIL1_AVAIL11_Pos 11 /*!< PAU AVAIL1: AVAIL11 Position */
\r
1559 #define PAU_AVAIL1_AVAIL11_Msk (0x01UL << PAU_AVAIL1_AVAIL11_Pos) /*!< PAU AVAIL1: AVAIL11 Mask */
\r
1560 #define PAU_AVAIL1_AVAIL12_Pos 12 /*!< PAU AVAIL1: AVAIL12 Position */
\r
1561 #define PAU_AVAIL1_AVAIL12_Msk (0x01UL << PAU_AVAIL1_AVAIL12_Pos) /*!< PAU AVAIL1: AVAIL12 Mask */
\r
1563 /* --------------------------------- PAU_AVAIL2 --------------------------------- */
\r
1564 #define PAU_AVAIL2_AVAIL0_Pos 0 /*!< PAU AVAIL2: AVAIL0 Position */
\r
1565 #define PAU_AVAIL2_AVAIL0_Msk (0x01UL << PAU_AVAIL2_AVAIL0_Pos) /*!< PAU AVAIL2: AVAIL0 Mask */
\r
1566 #define PAU_AVAIL2_AVAIL1_Pos 1 /*!< PAU AVAIL2: AVAIL1 Position */
\r
1567 #define PAU_AVAIL2_AVAIL1_Msk (0x01UL << PAU_AVAIL2_AVAIL1_Pos) /*!< PAU AVAIL2: AVAIL1 Mask */
\r
1568 #define PAU_AVAIL2_AVAIL2_Pos 2 /*!< PAU AVAIL2: AVAIL2 Position */
\r
1569 #define PAU_AVAIL2_AVAIL2_Msk (0x01UL << PAU_AVAIL2_AVAIL2_Pos) /*!< PAU AVAIL2: AVAIL2 Mask */
\r
1570 #define PAU_AVAIL2_AVAIL3_Pos 3 /*!< PAU AVAIL2: AVAIL3 Position */
\r
1571 #define PAU_AVAIL2_AVAIL3_Msk (0x01UL << PAU_AVAIL2_AVAIL3_Pos) /*!< PAU AVAIL2: AVAIL3 Mask */
\r
1572 #define PAU_AVAIL2_AVAIL12_Pos 12 /*!< PAU AVAIL2: AVAIL12 Position */
\r
1573 #define PAU_AVAIL2_AVAIL12_Msk (0x01UL << PAU_AVAIL2_AVAIL12_Pos) /*!< PAU AVAIL2: AVAIL12 Mask */
\r
1574 #define PAU_AVAIL2_AVAIL15_Pos 15 /*!< PAU AVAIL2: AVAIL15 Position */
\r
1575 #define PAU_AVAIL2_AVAIL15_Msk (0x01UL << PAU_AVAIL2_AVAIL15_Pos) /*!< PAU AVAIL2: AVAIL15 Mask */
\r
1577 /* -------------------------------- PAU_PRIVDIS0 -------------------------------- */
\r
1578 #define PAU_PRIVDIS0_PDIS2_Pos 2 /*!< PAU PRIVDIS0: PDIS2 Position */
\r
1579 #define PAU_PRIVDIS0_PDIS2_Msk (0x01UL << PAU_PRIVDIS0_PDIS2_Pos) /*!< PAU PRIVDIS0: PDIS2 Mask */
\r
1580 #define PAU_PRIVDIS0_PDIS5_Pos 5 /*!< PAU PRIVDIS0: PDIS5 Position */
\r
1581 #define PAU_PRIVDIS0_PDIS5_Msk (0x01UL << PAU_PRIVDIS0_PDIS5_Pos) /*!< PAU PRIVDIS0: PDIS5 Mask */
\r
1582 #define PAU_PRIVDIS0_PDIS6_Pos 6 /*!< PAU PRIVDIS0: PDIS6 Position */
\r
1583 #define PAU_PRIVDIS0_PDIS6_Msk (0x01UL << PAU_PRIVDIS0_PDIS6_Pos) /*!< PAU PRIVDIS0: PDIS6 Mask */
\r
1584 #define PAU_PRIVDIS0_PDIS7_Pos 7 /*!< PAU PRIVDIS0: PDIS7 Position */
\r
1585 #define PAU_PRIVDIS0_PDIS7_Msk (0x01UL << PAU_PRIVDIS0_PDIS7_Pos) /*!< PAU PRIVDIS0: PDIS7 Mask */
\r
1586 #define PAU_PRIVDIS0_PDIS19_Pos 19 /*!< PAU PRIVDIS0: PDIS19 Position */
\r
1587 #define PAU_PRIVDIS0_PDIS19_Msk (0x01UL << PAU_PRIVDIS0_PDIS19_Pos) /*!< PAU PRIVDIS0: PDIS19 Mask */
\r
1588 #define PAU_PRIVDIS0_PDIS20_Pos 20 /*!< PAU PRIVDIS0: PDIS20 Position */
\r
1589 #define PAU_PRIVDIS0_PDIS20_Msk (0x01UL << PAU_PRIVDIS0_PDIS20_Pos) /*!< PAU PRIVDIS0: PDIS20 Mask */
\r
1590 #define PAU_PRIVDIS0_PDIS21_Pos 21 /*!< PAU PRIVDIS0: PDIS21 Position */
\r
1591 #define PAU_PRIVDIS0_PDIS21_Msk (0x01UL << PAU_PRIVDIS0_PDIS21_Pos) /*!< PAU PRIVDIS0: PDIS21 Mask */
\r
1592 #define PAU_PRIVDIS0_PDIS22_Pos 22 /*!< PAU PRIVDIS0: PDIS22 Position */
\r
1593 #define PAU_PRIVDIS0_PDIS22_Msk (0x01UL << PAU_PRIVDIS0_PDIS22_Pos) /*!< PAU PRIVDIS0: PDIS22 Mask */
\r
1594 #define PAU_PRIVDIS0_PDIS23_Pos 23 /*!< PAU PRIVDIS0: PDIS23 Position */
\r
1595 #define PAU_PRIVDIS0_PDIS23_Msk (0x01UL << PAU_PRIVDIS0_PDIS23_Pos) /*!< PAU PRIVDIS0: PDIS23 Mask */
\r
1596 #define PAU_PRIVDIS0_PDIS24_Pos 24 /*!< PAU PRIVDIS0: PDIS24 Position */
\r
1597 #define PAU_PRIVDIS0_PDIS24_Msk (0x01UL << PAU_PRIVDIS0_PDIS24_Pos) /*!< PAU PRIVDIS0: PDIS24 Mask */
\r
1599 /* -------------------------------- PAU_PRIVDIS1 -------------------------------- */
\r
1600 #define PAU_PRIVDIS1_PDIS0_Pos 0 /*!< PAU PRIVDIS1: PDIS0 Position */
\r
1601 #define PAU_PRIVDIS1_PDIS0_Msk (0x01UL << PAU_PRIVDIS1_PDIS0_Pos) /*!< PAU PRIVDIS1: PDIS0 Mask */
\r
1602 #define PAU_PRIVDIS1_PDIS1_Pos 1 /*!< PAU PRIVDIS1: PDIS1 Position */
\r
1603 #define PAU_PRIVDIS1_PDIS1_Msk (0x01UL << PAU_PRIVDIS1_PDIS1_Pos) /*!< PAU PRIVDIS1: PDIS1 Mask */
\r
1604 #define PAU_PRIVDIS1_PDIS5_Pos 5 /*!< PAU PRIVDIS1: PDIS5 Position */
\r
1605 #define PAU_PRIVDIS1_PDIS5_Msk (0x01UL << PAU_PRIVDIS1_PDIS5_Pos) /*!< PAU PRIVDIS1: PDIS5 Mask */
\r
1606 #define PAU_PRIVDIS1_PDIS6_Pos 6 /*!< PAU PRIVDIS1: PDIS6 Position */
\r
1607 #define PAU_PRIVDIS1_PDIS6_Msk (0x01UL << PAU_PRIVDIS1_PDIS6_Pos) /*!< PAU PRIVDIS1: PDIS6 Mask */
\r
1608 #define PAU_PRIVDIS1_PDIS7_Pos 7 /*!< PAU PRIVDIS1: PDIS7 Position */
\r
1609 #define PAU_PRIVDIS1_PDIS7_Msk (0x01UL << PAU_PRIVDIS1_PDIS7_Pos) /*!< PAU PRIVDIS1: PDIS7 Mask */
\r
1610 #define PAU_PRIVDIS1_PDIS8_Pos 8 /*!< PAU PRIVDIS1: PDIS8 Position */
\r
1611 #define PAU_PRIVDIS1_PDIS8_Msk (0x01UL << PAU_PRIVDIS1_PDIS8_Pos) /*!< PAU PRIVDIS1: PDIS8 Mask */
\r
1612 #define PAU_PRIVDIS1_PDIS9_Pos 9 /*!< PAU PRIVDIS1: PDIS9 Position */
\r
1613 #define PAU_PRIVDIS1_PDIS9_Msk (0x01UL << PAU_PRIVDIS1_PDIS9_Pos) /*!< PAU PRIVDIS1: PDIS9 Mask */
\r
1614 #define PAU_PRIVDIS1_PDIS10_Pos 10 /*!< PAU PRIVDIS1: PDIS10 Position */
\r
1615 #define PAU_PRIVDIS1_PDIS10_Msk (0x01UL << PAU_PRIVDIS1_PDIS10_Pos) /*!< PAU PRIVDIS1: PDIS10 Mask */
\r
1616 #define PAU_PRIVDIS1_PDIS11_Pos 11 /*!< PAU PRIVDIS1: PDIS11 Position */
\r
1617 #define PAU_PRIVDIS1_PDIS11_Msk (0x01UL << PAU_PRIVDIS1_PDIS11_Pos) /*!< PAU PRIVDIS1: PDIS11 Mask */
\r
1618 #define PAU_PRIVDIS1_PDIS12_Pos 12 /*!< PAU PRIVDIS1: PDIS12 Position */
\r
1619 #define PAU_PRIVDIS1_PDIS12_Msk (0x01UL << PAU_PRIVDIS1_PDIS12_Pos) /*!< PAU PRIVDIS1: PDIS12 Mask */
\r
1621 /* -------------------------------- PAU_PRIVDIS2 -------------------------------- */
\r
1622 #define PAU_PRIVDIS2_PDIS0_Pos 0 /*!< PAU PRIVDIS2: PDIS0 Position */
\r
1623 #define PAU_PRIVDIS2_PDIS0_Msk (0x01UL << PAU_PRIVDIS2_PDIS0_Pos) /*!< PAU PRIVDIS2: PDIS0 Mask */
\r
1624 #define PAU_PRIVDIS2_PDIS1_Pos 1 /*!< PAU PRIVDIS2: PDIS1 Position */
\r
1625 #define PAU_PRIVDIS2_PDIS1_Msk (0x01UL << PAU_PRIVDIS2_PDIS1_Pos) /*!< PAU PRIVDIS2: PDIS1 Mask */
\r
1626 #define PAU_PRIVDIS2_PDIS2_Pos 2 /*!< PAU PRIVDIS2: PDIS2 Position */
\r
1627 #define PAU_PRIVDIS2_PDIS2_Msk (0x01UL << PAU_PRIVDIS2_PDIS2_Pos) /*!< PAU PRIVDIS2: PDIS2 Mask */
\r
1628 #define PAU_PRIVDIS2_PDIS3_Pos 3 /*!< PAU PRIVDIS2: PDIS3 Position */
\r
1629 #define PAU_PRIVDIS2_PDIS3_Msk (0x01UL << PAU_PRIVDIS2_PDIS3_Pos) /*!< PAU PRIVDIS2: PDIS3 Mask */
\r
1630 #define PAU_PRIVDIS2_PDIS12_Pos 12 /*!< PAU PRIVDIS2: PDIS12 Position */
\r
1631 #define PAU_PRIVDIS2_PDIS12_Msk (0x01UL << PAU_PRIVDIS2_PDIS12_Pos) /*!< PAU PRIVDIS2: PDIS12 Mask */
\r
1632 #define PAU_PRIVDIS2_PDIS15_Pos 15 /*!< PAU PRIVDIS2: PDIS15 Position */
\r
1633 #define PAU_PRIVDIS2_PDIS15_Msk (0x01UL << PAU_PRIVDIS2_PDIS15_Pos) /*!< PAU PRIVDIS2: PDIS15 Mask */
\r
1635 /* --------------------------------- PAU_ROMSIZE -------------------------------- */
\r
1636 #define PAU_ROMSIZE_ADDR_Pos 8 /*!< PAU ROMSIZE: ADDR Position */
\r
1637 #define PAU_ROMSIZE_ADDR_Msk (0x3fUL << PAU_ROMSIZE_ADDR_Pos) /*!< PAU ROMSIZE: ADDR Mask */
\r
1639 /* --------------------------------- PAU_FLSIZE --------------------------------- */
\r
1640 #define PAU_FLSIZE_ADDR_Pos 12 /*!< PAU FLSIZE: ADDR Position */
\r
1641 #define PAU_FLSIZE_ADDR_Msk (0x3fUL << PAU_FLSIZE_ADDR_Pos) /*!< PAU FLSIZE: ADDR Mask */
\r
1643 /* -------------------------------- PAU_RAM0SIZE -------------------------------- */
\r
1644 #define PAU_RAM0SIZE_ADDR_Pos 8 /*!< PAU RAM0SIZE: ADDR Position */
\r
1645 #define PAU_RAM0SIZE_ADDR_Msk (0x1fUL << PAU_RAM0SIZE_ADDR_Pos) /*!< PAU RAM0SIZE: ADDR Mask */
\r
1648 /* ================================================================================ */
\r
1649 /* ================ struct 'NVM' Position & Mask ================ */
\r
1650 /* ================================================================================ */
\r
1653 /* -------------------------------- NVM_NVMSTATUS ------------------------------- */
\r
1654 #define NVM_NVMSTATUS_BUSY_Pos 0 /*!< NVM NVMSTATUS: BUSY Position */
\r
1655 #define NVM_NVMSTATUS_BUSY_Msk (0x01UL << NVM_NVMSTATUS_BUSY_Pos) /*!< NVM NVMSTATUS: BUSY Mask */
\r
1656 #define NVM_NVMSTATUS_SLEEP_Pos 1 /*!< NVM NVMSTATUS: SLEEP Position */
\r
1657 #define NVM_NVMSTATUS_SLEEP_Msk (0x01UL << NVM_NVMSTATUS_SLEEP_Pos) /*!< NVM NVMSTATUS: SLEEP Mask */
\r
1658 #define NVM_NVMSTATUS_VERR_Pos 2 /*!< NVM NVMSTATUS: VERR Position */
\r
1659 #define NVM_NVMSTATUS_VERR_Msk (0x03UL << NVM_NVMSTATUS_VERR_Pos) /*!< NVM NVMSTATUS: VERR Mask */
\r
1660 #define NVM_NVMSTATUS_ECC1READ_Pos 4 /*!< NVM NVMSTATUS: ECC1READ Position */
\r
1661 #define NVM_NVMSTATUS_ECC1READ_Msk (0x01UL << NVM_NVMSTATUS_ECC1READ_Pos) /*!< NVM NVMSTATUS: ECC1READ Mask */
\r
1662 #define NVM_NVMSTATUS_ECC2READ_Pos 5 /*!< NVM NVMSTATUS: ECC2READ Position */
\r
1663 #define NVM_NVMSTATUS_ECC2READ_Msk (0x01UL << NVM_NVMSTATUS_ECC2READ_Pos) /*!< NVM NVMSTATUS: ECC2READ Mask */
\r
1664 #define NVM_NVMSTATUS_WRPERR_Pos 6 /*!< NVM NVMSTATUS: WRPERR Position */
\r
1665 #define NVM_NVMSTATUS_WRPERR_Msk (0x01UL << NVM_NVMSTATUS_WRPERR_Pos) /*!< NVM NVMSTATUS: WRPERR Mask */
\r
1667 /* --------------------------------- NVM_NVMPROG -------------------------------- */
\r
1668 #define NVM_NVMPROG_ACTION_Pos 0 /*!< NVM NVMPROG: ACTION Position */
\r
1669 #define NVM_NVMPROG_ACTION_Msk (0x000000ffUL << NVM_NVMPROG_ACTION_Pos) /*!< NVM NVMPROG: ACTION Mask */
\r
1670 #define NVM_NVMPROG_RSTVERR_Pos 12 /*!< NVM NVMPROG: RSTVERR Position */
\r
1671 #define NVM_NVMPROG_RSTVERR_Msk (0x01UL << NVM_NVMPROG_RSTVERR_Pos) /*!< NVM NVMPROG: RSTVERR Mask */
\r
1672 #define NVM_NVMPROG_RSTECC_Pos 13 /*!< NVM NVMPROG: RSTECC Position */
\r
1673 #define NVM_NVMPROG_RSTECC_Msk (0x01UL << NVM_NVMPROG_RSTECC_Pos) /*!< NVM NVMPROG: RSTECC Mask */
\r
1675 /* --------------------------------- NVM_NVMCONF -------------------------------- */
\r
1676 #define NVM_NVMCONF_HRLEV_Pos 1 /*!< NVM NVMCONF: HRLEV Position */
\r
1677 #define NVM_NVMCONF_HRLEV_Msk (0x03UL << NVM_NVMCONF_HRLEV_Pos) /*!< NVM NVMCONF: HRLEV Mask */
\r
1678 #define NVM_NVMCONF_SECPROT_Pos 4 /*!< NVM NVMCONF: SECPROT Position */
\r
1679 #define NVM_NVMCONF_SECPROT_Msk (0x000000ffUL << NVM_NVMCONF_SECPROT_Pos) /*!< NVM NVMCONF: SECPROT Mask */
\r
1680 #define NVM_NVMCONF_INT_ON_Pos 14 /*!< NVM NVMCONF: INT_ON Position */
\r
1681 #define NVM_NVMCONF_INT_ON_Msk (0x01UL << NVM_NVMCONF_INT_ON_Pos) /*!< NVM NVMCONF: INT_ON Mask */
\r
1682 #define NVM_NVMCONF_NVM_ON_Pos 15 /*!< NVM NVMCONF: NVM_ON Position */
\r
1683 #define NVM_NVMCONF_NVM_ON_Msk (0x01UL << NVM_NVMCONF_NVM_ON_Pos) /*!< NVM NVMCONF: NVM_ON Mask */
\r
1686 /* ================================================================================ */
\r
1687 /* ================ struct 'WDT' Position & Mask ================ */
\r
1688 /* ================================================================================ */
\r
1691 /* ----------------------------------- WDT_ID ----------------------------------- */
\r
1692 #define WDT_ID_MOD_REV_Pos 0 /*!< WDT ID: MOD_REV Position */
\r
1693 #define WDT_ID_MOD_REV_Msk (0x000000ffUL << WDT_ID_MOD_REV_Pos) /*!< WDT ID: MOD_REV Mask */
\r
1694 #define WDT_ID_MOD_TYPE_Pos 8 /*!< WDT ID: MOD_TYPE Position */
\r
1695 #define WDT_ID_MOD_TYPE_Msk (0x000000ffUL << WDT_ID_MOD_TYPE_Pos) /*!< WDT ID: MOD_TYPE Mask */
\r
1696 #define WDT_ID_MOD_NUMBER_Pos 16 /*!< WDT ID: MOD_NUMBER Position */
\r
1697 #define WDT_ID_MOD_NUMBER_Msk (0x0000ffffUL << WDT_ID_MOD_NUMBER_Pos) /*!< WDT ID: MOD_NUMBER Mask */
\r
1699 /* ----------------------------------- WDT_CTR ---------------------------------- */
\r
1700 #define WDT_CTR_ENB_Pos 0 /*!< WDT CTR: ENB Position */
\r
1701 #define WDT_CTR_ENB_Msk (0x01UL << WDT_CTR_ENB_Pos) /*!< WDT CTR: ENB Mask */
\r
1702 #define WDT_CTR_PRE_Pos 1 /*!< WDT CTR: PRE Position */
\r
1703 #define WDT_CTR_PRE_Msk (0x01UL << WDT_CTR_PRE_Pos) /*!< WDT CTR: PRE Mask */
\r
1704 #define WDT_CTR_DSP_Pos 4 /*!< WDT CTR: DSP Position */
\r
1705 #define WDT_CTR_DSP_Msk (0x01UL << WDT_CTR_DSP_Pos) /*!< WDT CTR: DSP Mask */
\r
1706 #define WDT_CTR_SPW_Pos 8 /*!< WDT CTR: SPW Position */
\r
1707 #define WDT_CTR_SPW_Msk (0x000000ffUL << WDT_CTR_SPW_Pos) /*!< WDT CTR: SPW Mask */
\r
1709 /* ----------------------------------- WDT_SRV ---------------------------------- */
\r
1710 #define WDT_SRV_SRV_Pos 0 /*!< WDT SRV: SRV Position */
\r
1711 #define WDT_SRV_SRV_Msk (0xffffffffUL << WDT_SRV_SRV_Pos) /*!< WDT SRV: SRV Mask */
\r
1713 /* ----------------------------------- WDT_TIM ---------------------------------- */
\r
1714 #define WDT_TIM_TIM_Pos 0 /*!< WDT TIM: TIM Position */
\r
1715 #define WDT_TIM_TIM_Msk (0xffffffffUL << WDT_TIM_TIM_Pos) /*!< WDT TIM: TIM Mask */
\r
1717 /* ----------------------------------- WDT_WLB ---------------------------------- */
\r
1718 #define WDT_WLB_WLB_Pos 0 /*!< WDT WLB: WLB Position */
\r
1719 #define WDT_WLB_WLB_Msk (0xffffffffUL << WDT_WLB_WLB_Pos) /*!< WDT WLB: WLB Mask */
\r
1721 /* ----------------------------------- WDT_WUB ---------------------------------- */
\r
1722 #define WDT_WUB_WUB_Pos 0 /*!< WDT WUB: WUB Position */
\r
1723 #define WDT_WUB_WUB_Msk (0xffffffffUL << WDT_WUB_WUB_Pos) /*!< WDT WUB: WUB Mask */
\r
1725 /* --------------------------------- WDT_WDTSTS --------------------------------- */
\r
1726 #define WDT_WDTSTS_ALMS_Pos 0 /*!< WDT WDTSTS: ALMS Position */
\r
1727 #define WDT_WDTSTS_ALMS_Msk (0x01UL << WDT_WDTSTS_ALMS_Pos) /*!< WDT WDTSTS: ALMS Mask */
\r
1729 /* --------------------------------- WDT_WDTCLR --------------------------------- */
\r
1730 #define WDT_WDTCLR_ALMC_Pos 0 /*!< WDT WDTCLR: ALMC Position */
\r
1731 #define WDT_WDTCLR_ALMC_Msk (0x01UL << WDT_WDTCLR_ALMC_Pos) /*!< WDT WDTCLR: ALMC Mask */
\r
1734 /* ================================================================================ */
\r
1735 /* ================ struct 'RTC' Position & Mask ================ */
\r
1736 /* ================================================================================ */
\r
1739 /* ----------------------------------- RTC_ID ----------------------------------- */
\r
1740 #define RTC_ID_MOD_REV_Pos 0 /*!< RTC ID: MOD_REV Position */
\r
1741 #define RTC_ID_MOD_REV_Msk (0x000000ffUL << RTC_ID_MOD_REV_Pos) /*!< RTC ID: MOD_REV Mask */
\r
1742 #define RTC_ID_MOD_TYPE_Pos 8 /*!< RTC ID: MOD_TYPE Position */
\r
1743 #define RTC_ID_MOD_TYPE_Msk (0x000000ffUL << RTC_ID_MOD_TYPE_Pos) /*!< RTC ID: MOD_TYPE Mask */
\r
1744 #define RTC_ID_MOD_NUMBER_Pos 16 /*!< RTC ID: MOD_NUMBER Position */
\r
1745 #define RTC_ID_MOD_NUMBER_Msk (0x0000ffffUL << RTC_ID_MOD_NUMBER_Pos) /*!< RTC ID: MOD_NUMBER Mask */
\r
1747 /* ----------------------------------- RTC_CTR ---------------------------------- */
\r
1748 #define RTC_CTR_ENB_Pos 0 /*!< RTC CTR: ENB Position */
\r
1749 #define RTC_CTR_ENB_Msk (0x01UL << RTC_CTR_ENB_Pos) /*!< RTC CTR: ENB Mask */
\r
1750 #define RTC_CTR_SUS_Pos 1 /*!< RTC CTR: SUS Position */
\r
1751 #define RTC_CTR_SUS_Msk (0x01UL << RTC_CTR_SUS_Pos) /*!< RTC CTR: SUS Mask */
\r
1752 #define RTC_CTR_DIV_Pos 16 /*!< RTC CTR: DIV Position */
\r
1753 #define RTC_CTR_DIV_Msk (0x0000ffffUL << RTC_CTR_DIV_Pos) /*!< RTC CTR: DIV Mask */
\r
1755 /* --------------------------------- RTC_RAWSTAT -------------------------------- */
\r
1756 #define RTC_RAWSTAT_RPSE_Pos 0 /*!< RTC RAWSTAT: RPSE Position */
\r
1757 #define RTC_RAWSTAT_RPSE_Msk (0x01UL << RTC_RAWSTAT_RPSE_Pos) /*!< RTC RAWSTAT: RPSE Mask */
\r
1758 #define RTC_RAWSTAT_RPMI_Pos 1 /*!< RTC RAWSTAT: RPMI Position */
\r
1759 #define RTC_RAWSTAT_RPMI_Msk (0x01UL << RTC_RAWSTAT_RPMI_Pos) /*!< RTC RAWSTAT: RPMI Mask */
\r
1760 #define RTC_RAWSTAT_RPHO_Pos 2 /*!< RTC RAWSTAT: RPHO Position */
\r
1761 #define RTC_RAWSTAT_RPHO_Msk (0x01UL << RTC_RAWSTAT_RPHO_Pos) /*!< RTC RAWSTAT: RPHO Mask */
\r
1762 #define RTC_RAWSTAT_RPDA_Pos 3 /*!< RTC RAWSTAT: RPDA Position */
\r
1763 #define RTC_RAWSTAT_RPDA_Msk (0x01UL << RTC_RAWSTAT_RPDA_Pos) /*!< RTC RAWSTAT: RPDA Mask */
\r
1764 #define RTC_RAWSTAT_RPMO_Pos 5 /*!< RTC RAWSTAT: RPMO Position */
\r
1765 #define RTC_RAWSTAT_RPMO_Msk (0x01UL << RTC_RAWSTAT_RPMO_Pos) /*!< RTC RAWSTAT: RPMO Mask */
\r
1766 #define RTC_RAWSTAT_RPYE_Pos 6 /*!< RTC RAWSTAT: RPYE Position */
\r
1767 #define RTC_RAWSTAT_RPYE_Msk (0x01UL << RTC_RAWSTAT_RPYE_Pos) /*!< RTC RAWSTAT: RPYE Mask */
\r
1768 #define RTC_RAWSTAT_RAI_Pos 8 /*!< RTC RAWSTAT: RAI Position */
\r
1769 #define RTC_RAWSTAT_RAI_Msk (0x01UL << RTC_RAWSTAT_RAI_Pos) /*!< RTC RAWSTAT: RAI Mask */
\r
1771 /* ---------------------------------- RTC_STSSR --------------------------------- */
\r
1772 #define RTC_STSSR_SPSE_Pos 0 /*!< RTC STSSR: SPSE Position */
\r
1773 #define RTC_STSSR_SPSE_Msk (0x01UL << RTC_STSSR_SPSE_Pos) /*!< RTC STSSR: SPSE Mask */
\r
1774 #define RTC_STSSR_SPMI_Pos 1 /*!< RTC STSSR: SPMI Position */
\r
1775 #define RTC_STSSR_SPMI_Msk (0x01UL << RTC_STSSR_SPMI_Pos) /*!< RTC STSSR: SPMI Mask */
\r
1776 #define RTC_STSSR_SPHO_Pos 2 /*!< RTC STSSR: SPHO Position */
\r
1777 #define RTC_STSSR_SPHO_Msk (0x01UL << RTC_STSSR_SPHO_Pos) /*!< RTC STSSR: SPHO Mask */
\r
1778 #define RTC_STSSR_SPDA_Pos 3 /*!< RTC STSSR: SPDA Position */
\r
1779 #define RTC_STSSR_SPDA_Msk (0x01UL << RTC_STSSR_SPDA_Pos) /*!< RTC STSSR: SPDA Mask */
\r
1780 #define RTC_STSSR_SPMO_Pos 5 /*!< RTC STSSR: SPMO Position */
\r
1781 #define RTC_STSSR_SPMO_Msk (0x01UL << RTC_STSSR_SPMO_Pos) /*!< RTC STSSR: SPMO Mask */
\r
1782 #define RTC_STSSR_SPYE_Pos 6 /*!< RTC STSSR: SPYE Position */
\r
1783 #define RTC_STSSR_SPYE_Msk (0x01UL << RTC_STSSR_SPYE_Pos) /*!< RTC STSSR: SPYE Mask */
\r
1784 #define RTC_STSSR_SAI_Pos 8 /*!< RTC STSSR: SAI Position */
\r
1785 #define RTC_STSSR_SAI_Msk (0x01UL << RTC_STSSR_SAI_Pos) /*!< RTC STSSR: SAI Mask */
\r
1787 /* ---------------------------------- RTC_MSKSR --------------------------------- */
\r
1788 #define RTC_MSKSR_MPSE_Pos 0 /*!< RTC MSKSR: MPSE Position */
\r
1789 #define RTC_MSKSR_MPSE_Msk (0x01UL << RTC_MSKSR_MPSE_Pos) /*!< RTC MSKSR: MPSE Mask */
\r
1790 #define RTC_MSKSR_MPMI_Pos 1 /*!< RTC MSKSR: MPMI Position */
\r
1791 #define RTC_MSKSR_MPMI_Msk (0x01UL << RTC_MSKSR_MPMI_Pos) /*!< RTC MSKSR: MPMI Mask */
\r
1792 #define RTC_MSKSR_MPHO_Pos 2 /*!< RTC MSKSR: MPHO Position */
\r
1793 #define RTC_MSKSR_MPHO_Msk (0x01UL << RTC_MSKSR_MPHO_Pos) /*!< RTC MSKSR: MPHO Mask */
\r
1794 #define RTC_MSKSR_MPDA_Pos 3 /*!< RTC MSKSR: MPDA Position */
\r
1795 #define RTC_MSKSR_MPDA_Msk (0x01UL << RTC_MSKSR_MPDA_Pos) /*!< RTC MSKSR: MPDA Mask */
\r
1796 #define RTC_MSKSR_MPMO_Pos 5 /*!< RTC MSKSR: MPMO Position */
\r
1797 #define RTC_MSKSR_MPMO_Msk (0x01UL << RTC_MSKSR_MPMO_Pos) /*!< RTC MSKSR: MPMO Mask */
\r
1798 #define RTC_MSKSR_MPYE_Pos 6 /*!< RTC MSKSR: MPYE Position */
\r
1799 #define RTC_MSKSR_MPYE_Msk (0x01UL << RTC_MSKSR_MPYE_Pos) /*!< RTC MSKSR: MPYE Mask */
\r
1800 #define RTC_MSKSR_MAI_Pos 8 /*!< RTC MSKSR: MAI Position */
\r
1801 #define RTC_MSKSR_MAI_Msk (0x01UL << RTC_MSKSR_MAI_Pos) /*!< RTC MSKSR: MAI Mask */
\r
1803 /* ---------------------------------- RTC_CLRSR --------------------------------- */
\r
1804 #define RTC_CLRSR_RPSE_Pos 0 /*!< RTC CLRSR: RPSE Position */
\r
1805 #define RTC_CLRSR_RPSE_Msk (0x01UL << RTC_CLRSR_RPSE_Pos) /*!< RTC CLRSR: RPSE Mask */
\r
1806 #define RTC_CLRSR_RPMI_Pos 1 /*!< RTC CLRSR: RPMI Position */
\r
1807 #define RTC_CLRSR_RPMI_Msk (0x01UL << RTC_CLRSR_RPMI_Pos) /*!< RTC CLRSR: RPMI Mask */
\r
1808 #define RTC_CLRSR_RPHO_Pos 2 /*!< RTC CLRSR: RPHO Position */
\r
1809 #define RTC_CLRSR_RPHO_Msk (0x01UL << RTC_CLRSR_RPHO_Pos) /*!< RTC CLRSR: RPHO Mask */
\r
1810 #define RTC_CLRSR_RPDA_Pos 3 /*!< RTC CLRSR: RPDA Position */
\r
1811 #define RTC_CLRSR_RPDA_Msk (0x01UL << RTC_CLRSR_RPDA_Pos) /*!< RTC CLRSR: RPDA Mask */
\r
1812 #define RTC_CLRSR_RPMO_Pos 5 /*!< RTC CLRSR: RPMO Position */
\r
1813 #define RTC_CLRSR_RPMO_Msk (0x01UL << RTC_CLRSR_RPMO_Pos) /*!< RTC CLRSR: RPMO Mask */
\r
1814 #define RTC_CLRSR_RPYE_Pos 6 /*!< RTC CLRSR: RPYE Position */
\r
1815 #define RTC_CLRSR_RPYE_Msk (0x01UL << RTC_CLRSR_RPYE_Pos) /*!< RTC CLRSR: RPYE Mask */
\r
1816 #define RTC_CLRSR_RAI_Pos 8 /*!< RTC CLRSR: RAI Position */
\r
1817 #define RTC_CLRSR_RAI_Msk (0x01UL << RTC_CLRSR_RAI_Pos) /*!< RTC CLRSR: RAI Mask */
\r
1819 /* ---------------------------------- RTC_ATIM0 --------------------------------- */
\r
1820 #define RTC_ATIM0_ASE_Pos 0 /*!< RTC ATIM0: ASE Position */
\r
1821 #define RTC_ATIM0_ASE_Msk (0x3fUL << RTC_ATIM0_ASE_Pos) /*!< RTC ATIM0: ASE Mask */
\r
1822 #define RTC_ATIM0_AMI_Pos 8 /*!< RTC ATIM0: AMI Position */
\r
1823 #define RTC_ATIM0_AMI_Msk (0x3fUL << RTC_ATIM0_AMI_Pos) /*!< RTC ATIM0: AMI Mask */
\r
1824 #define RTC_ATIM0_AHO_Pos 16 /*!< RTC ATIM0: AHO Position */
\r
1825 #define RTC_ATIM0_AHO_Msk (0x1fUL << RTC_ATIM0_AHO_Pos) /*!< RTC ATIM0: AHO Mask */
\r
1826 #define RTC_ATIM0_ADA_Pos 24 /*!< RTC ATIM0: ADA Position */
\r
1827 #define RTC_ATIM0_ADA_Msk (0x1fUL << RTC_ATIM0_ADA_Pos) /*!< RTC ATIM0: ADA Mask */
\r
1829 /* ---------------------------------- RTC_ATIM1 --------------------------------- */
\r
1830 #define RTC_ATIM1_AMO_Pos 8 /*!< RTC ATIM1: AMO Position */
\r
1831 #define RTC_ATIM1_AMO_Msk (0x0fUL << RTC_ATIM1_AMO_Pos) /*!< RTC ATIM1: AMO Mask */
\r
1832 #define RTC_ATIM1_AYE_Pos 16 /*!< RTC ATIM1: AYE Position */
\r
1833 #define RTC_ATIM1_AYE_Msk (0x0000ffffUL << RTC_ATIM1_AYE_Pos) /*!< RTC ATIM1: AYE Mask */
\r
1835 /* ---------------------------------- RTC_TIM0 ---------------------------------- */
\r
1836 #define RTC_TIM0_SE_Pos 0 /*!< RTC TIM0: SE Position */
\r
1837 #define RTC_TIM0_SE_Msk (0x3fUL << RTC_TIM0_SE_Pos) /*!< RTC TIM0: SE Mask */
\r
1838 #define RTC_TIM0_MI_Pos 8 /*!< RTC TIM0: MI Position */
\r
1839 #define RTC_TIM0_MI_Msk (0x3fUL << RTC_TIM0_MI_Pos) /*!< RTC TIM0: MI Mask */
\r
1840 #define RTC_TIM0_HO_Pos 16 /*!< RTC TIM0: HO Position */
\r
1841 #define RTC_TIM0_HO_Msk (0x1fUL << RTC_TIM0_HO_Pos) /*!< RTC TIM0: HO Mask */
\r
1842 #define RTC_TIM0_DA_Pos 24 /*!< RTC TIM0: DA Position */
\r
1843 #define RTC_TIM0_DA_Msk (0x1fUL << RTC_TIM0_DA_Pos) /*!< RTC TIM0: DA Mask */
\r
1845 /* ---------------------------------- RTC_TIM1 ---------------------------------- */
\r
1846 #define RTC_TIM1_DAWE_Pos 0 /*!< RTC TIM1: DAWE Position */
\r
1847 #define RTC_TIM1_DAWE_Msk (0x07UL << RTC_TIM1_DAWE_Pos) /*!< RTC TIM1: DAWE Mask */
\r
1848 #define RTC_TIM1_MO_Pos 8 /*!< RTC TIM1: MO Position */
\r
1849 #define RTC_TIM1_MO_Msk (0x0fUL << RTC_TIM1_MO_Pos) /*!< RTC TIM1: MO Mask */
\r
1850 #define RTC_TIM1_YE_Pos 16 /*!< RTC TIM1: YE Position */
\r
1851 #define RTC_TIM1_YE_Msk (0x0000ffffUL << RTC_TIM1_YE_Pos) /*!< RTC TIM1: YE Mask */
\r
1854 /* ================================================================================ */
\r
1855 /* ================ struct 'PRNG' Position & Mask ================ */
\r
1856 /* ================================================================================ */
\r
1859 /* ---------------------------------- PRNG_WORD --------------------------------- */
\r
1860 #define PRNG_WORD_RDATA_Pos 0 /*!< PRNG WORD: RDATA Position */
\r
1861 #define PRNG_WORD_RDATA_Msk (0x0000ffffUL << PRNG_WORD_RDATA_Pos) /*!< PRNG WORD: RDATA Mask */
\r
1863 /* ---------------------------------- PRNG_CHK ---------------------------------- */
\r
1864 #define PRNG_CHK_RDV_Pos 0 /*!< PRNG CHK: RDV Position */
\r
1865 #define PRNG_CHK_RDV_Msk (0x01UL << PRNG_CHK_RDV_Pos) /*!< PRNG CHK: RDV Mask */
\r
1867 /* ---------------------------------- PRNG_CTRL --------------------------------- */
\r
1868 #define PRNG_CTRL_RDBS_Pos 1 /*!< PRNG CTRL: RDBS Position */
\r
1869 #define PRNG_CTRL_RDBS_Msk (0x03UL << PRNG_CTRL_RDBS_Pos) /*!< PRNG CTRL: RDBS Mask */
\r
1870 #define PRNG_CTRL_KLD_Pos 3 /*!< PRNG CTRL: KLD Position */
\r
1871 #define PRNG_CTRL_KLD_Msk (0x01UL << PRNG_CTRL_KLD_Pos) /*!< PRNG CTRL: KLD Mask */
\r
1874 /* ================================================================================ */
\r
1875 /* ================ Group 'USIC' Position & Mask ================ */
\r
1876 /* ================================================================================ */
\r
1879 /* ----------------------------------- USIC_ID ---------------------------------- */
\r
1880 #define USIC_ID_MOD_REV_Pos 0 /*!< USIC ID: MOD_REV Position */
\r
1881 #define USIC_ID_MOD_REV_Msk (0x000000ffUL << USIC_ID_MOD_REV_Pos) /*!< USIC ID: MOD_REV Mask */
\r
1882 #define USIC_ID_MOD_TYPE_Pos 8 /*!< USIC ID: MOD_TYPE Position */
\r
1883 #define USIC_ID_MOD_TYPE_Msk (0x000000ffUL << USIC_ID_MOD_TYPE_Pos) /*!< USIC ID: MOD_TYPE Mask */
\r
1884 #define USIC_ID_MOD_NUMBER_Pos 16 /*!< USIC ID: MOD_NUMBER Position */
\r
1885 #define USIC_ID_MOD_NUMBER_Msk (0x0000ffffUL << USIC_ID_MOD_NUMBER_Pos) /*!< USIC ID: MOD_NUMBER Mask */
\r
1888 /* ================================================================================ */
\r
1889 /* ================ Group 'USIC_CH' Position & Mask ================ */
\r
1890 /* ================================================================================ */
\r
1893 /* -------------------------------- USIC_CH_CCFG -------------------------------- */
\r
1894 #define USIC_CH_CCFG_SSC_Pos 0 /*!< USIC_CH CCFG: SSC Position */
\r
1895 #define USIC_CH_CCFG_SSC_Msk (0x01UL << USIC_CH_CCFG_SSC_Pos) /*!< USIC_CH CCFG: SSC Mask */
\r
1896 #define USIC_CH_CCFG_ASC_Pos 1 /*!< USIC_CH CCFG: ASC Position */
\r
1897 #define USIC_CH_CCFG_ASC_Msk (0x01UL << USIC_CH_CCFG_ASC_Pos) /*!< USIC_CH CCFG: ASC Mask */
\r
1898 #define USIC_CH_CCFG_IIC_Pos 2 /*!< USIC_CH CCFG: IIC Position */
\r
1899 #define USIC_CH_CCFG_IIC_Msk (0x01UL << USIC_CH_CCFG_IIC_Pos) /*!< USIC_CH CCFG: IIC Mask */
\r
1900 #define USIC_CH_CCFG_IIS_Pos 3 /*!< USIC_CH CCFG: IIS Position */
\r
1901 #define USIC_CH_CCFG_IIS_Msk (0x01UL << USIC_CH_CCFG_IIS_Pos) /*!< USIC_CH CCFG: IIS Mask */
\r
1902 #define USIC_CH_CCFG_RB_Pos 6 /*!< USIC_CH CCFG: RB Position */
\r
1903 #define USIC_CH_CCFG_RB_Msk (0x01UL << USIC_CH_CCFG_RB_Pos) /*!< USIC_CH CCFG: RB Mask */
\r
1904 #define USIC_CH_CCFG_TB_Pos 7 /*!< USIC_CH CCFG: TB Position */
\r
1905 #define USIC_CH_CCFG_TB_Msk (0x01UL << USIC_CH_CCFG_TB_Pos) /*!< USIC_CH CCFG: TB Mask */
\r
1907 /* -------------------------------- USIC_CH_KSCFG ------------------------------- */
\r
1908 #define USIC_CH_KSCFG_MODEN_Pos 0 /*!< USIC_CH KSCFG: MODEN Position */
\r
1909 #define USIC_CH_KSCFG_MODEN_Msk (0x01UL << USIC_CH_KSCFG_MODEN_Pos) /*!< USIC_CH KSCFG: MODEN Mask */
\r
1910 #define USIC_CH_KSCFG_BPMODEN_Pos 1 /*!< USIC_CH KSCFG: BPMODEN Position */
\r
1911 #define USIC_CH_KSCFG_BPMODEN_Msk (0x01UL << USIC_CH_KSCFG_BPMODEN_Pos) /*!< USIC_CH KSCFG: BPMODEN Mask */
\r
1912 #define USIC_CH_KSCFG_NOMCFG_Pos 4 /*!< USIC_CH KSCFG: NOMCFG Position */
\r
1913 #define USIC_CH_KSCFG_NOMCFG_Msk (0x03UL << USIC_CH_KSCFG_NOMCFG_Pos) /*!< USIC_CH KSCFG: NOMCFG Mask */
\r
1914 #define USIC_CH_KSCFG_BPNOM_Pos 7 /*!< USIC_CH KSCFG: BPNOM Position */
\r
1915 #define USIC_CH_KSCFG_BPNOM_Msk (0x01UL << USIC_CH_KSCFG_BPNOM_Pos) /*!< USIC_CH KSCFG: BPNOM Mask */
\r
1916 #define USIC_CH_KSCFG_SUMCFG_Pos 8 /*!< USIC_CH KSCFG: SUMCFG Position */
\r
1917 #define USIC_CH_KSCFG_SUMCFG_Msk (0x03UL << USIC_CH_KSCFG_SUMCFG_Pos) /*!< USIC_CH KSCFG: SUMCFG Mask */
\r
1918 #define USIC_CH_KSCFG_BPSUM_Pos 11 /*!< USIC_CH KSCFG: BPSUM Position */
\r
1919 #define USIC_CH_KSCFG_BPSUM_Msk (0x01UL << USIC_CH_KSCFG_BPSUM_Pos) /*!< USIC_CH KSCFG: BPSUM Mask */
\r
1921 /* --------------------------------- USIC_CH_FDR -------------------------------- */
\r
1922 #define USIC_CH_FDR_STEP_Pos 0 /*!< USIC_CH FDR: STEP Position */
\r
1923 #define USIC_CH_FDR_STEP_Msk (0x000003ffUL << USIC_CH_FDR_STEP_Pos) /*!< USIC_CH FDR: STEP Mask */
\r
1924 #define USIC_CH_FDR_DM_Pos 14 /*!< USIC_CH FDR: DM Position */
\r
1925 #define USIC_CH_FDR_DM_Msk (0x03UL << USIC_CH_FDR_DM_Pos) /*!< USIC_CH FDR: DM Mask */
\r
1926 #define USIC_CH_FDR_RESULT_Pos 16 /*!< USIC_CH FDR: RESULT Position */
\r
1927 #define USIC_CH_FDR_RESULT_Msk (0x000003ffUL << USIC_CH_FDR_RESULT_Pos) /*!< USIC_CH FDR: RESULT Mask */
\r
1929 /* --------------------------------- USIC_CH_BRG -------------------------------- */
\r
1930 #define USIC_CH_BRG_CLKSEL_Pos 0 /*!< USIC_CH BRG: CLKSEL Position */
\r
1931 #define USIC_CH_BRG_CLKSEL_Msk (0x03UL << USIC_CH_BRG_CLKSEL_Pos) /*!< USIC_CH BRG: CLKSEL Mask */
\r
1932 #define USIC_CH_BRG_TMEN_Pos 3 /*!< USIC_CH BRG: TMEN Position */
\r
1933 #define USIC_CH_BRG_TMEN_Msk (0x01UL << USIC_CH_BRG_TMEN_Pos) /*!< USIC_CH BRG: TMEN Mask */
\r
1934 #define USIC_CH_BRG_PPPEN_Pos 4 /*!< USIC_CH BRG: PPPEN Position */
\r
1935 #define USIC_CH_BRG_PPPEN_Msk (0x01UL << USIC_CH_BRG_PPPEN_Pos) /*!< USIC_CH BRG: PPPEN Mask */
\r
1936 #define USIC_CH_BRG_CTQSEL_Pos 6 /*!< USIC_CH BRG: CTQSEL Position */
\r
1937 #define USIC_CH_BRG_CTQSEL_Msk (0x03UL << USIC_CH_BRG_CTQSEL_Pos) /*!< USIC_CH BRG: CTQSEL Mask */
\r
1938 #define USIC_CH_BRG_PCTQ_Pos 8 /*!< USIC_CH BRG: PCTQ Position */
\r
1939 #define USIC_CH_BRG_PCTQ_Msk (0x03UL << USIC_CH_BRG_PCTQ_Pos) /*!< USIC_CH BRG: PCTQ Mask */
\r
1940 #define USIC_CH_BRG_DCTQ_Pos 10 /*!< USIC_CH BRG: DCTQ Position */
\r
1941 #define USIC_CH_BRG_DCTQ_Msk (0x1fUL << USIC_CH_BRG_DCTQ_Pos) /*!< USIC_CH BRG: DCTQ Mask */
\r
1942 #define USIC_CH_BRG_PDIV_Pos 16 /*!< USIC_CH BRG: PDIV Position */
\r
1943 #define USIC_CH_BRG_PDIV_Msk (0x000003ffUL << USIC_CH_BRG_PDIV_Pos) /*!< USIC_CH BRG: PDIV Mask */
\r
1944 #define USIC_CH_BRG_SCLKOSEL_Pos 28 /*!< USIC_CH BRG: SCLKOSEL Position */
\r
1945 #define USIC_CH_BRG_SCLKOSEL_Msk (0x01UL << USIC_CH_BRG_SCLKOSEL_Pos) /*!< USIC_CH BRG: SCLKOSEL Mask */
\r
1946 #define USIC_CH_BRG_MCLKCFG_Pos 29 /*!< USIC_CH BRG: MCLKCFG Position */
\r
1947 #define USIC_CH_BRG_MCLKCFG_Msk (0x01UL << USIC_CH_BRG_MCLKCFG_Pos) /*!< USIC_CH BRG: MCLKCFG Mask */
\r
1948 #define USIC_CH_BRG_SCLKCFG_Pos 30 /*!< USIC_CH BRG: SCLKCFG Position */
\r
1949 #define USIC_CH_BRG_SCLKCFG_Msk (0x03UL << USIC_CH_BRG_SCLKCFG_Pos) /*!< USIC_CH BRG: SCLKCFG Mask */
\r
1951 /* -------------------------------- USIC_CH_INPR -------------------------------- */
\r
1952 #define USIC_CH_INPR_TSINP_Pos 0 /*!< USIC_CH INPR: TSINP Position */
\r
1953 #define USIC_CH_INPR_TSINP_Msk (0x07UL << USIC_CH_INPR_TSINP_Pos) /*!< USIC_CH INPR: TSINP Mask */
\r
1954 #define USIC_CH_INPR_TBINP_Pos 4 /*!< USIC_CH INPR: TBINP Position */
\r
1955 #define USIC_CH_INPR_TBINP_Msk (0x07UL << USIC_CH_INPR_TBINP_Pos) /*!< USIC_CH INPR: TBINP Mask */
\r
1956 #define USIC_CH_INPR_RINP_Pos 8 /*!< USIC_CH INPR: RINP Position */
\r
1957 #define USIC_CH_INPR_RINP_Msk (0x07UL << USIC_CH_INPR_RINP_Pos) /*!< USIC_CH INPR: RINP Mask */
\r
1958 #define USIC_CH_INPR_AINP_Pos 12 /*!< USIC_CH INPR: AINP Position */
\r
1959 #define USIC_CH_INPR_AINP_Msk (0x07UL << USIC_CH_INPR_AINP_Pos) /*!< USIC_CH INPR: AINP Mask */
\r
1960 #define USIC_CH_INPR_PINP_Pos 16 /*!< USIC_CH INPR: PINP Position */
\r
1961 #define USIC_CH_INPR_PINP_Msk (0x07UL << USIC_CH_INPR_PINP_Pos) /*!< USIC_CH INPR: PINP Mask */
\r
1963 /* -------------------------------- USIC_CH_DX0CR ------------------------------- */
\r
1964 #define USIC_CH_DX0CR_DSEL_Pos 0 /*!< USIC_CH DX0CR: DSEL Position */
\r
1965 #define USIC_CH_DX0CR_DSEL_Msk (0x07UL << USIC_CH_DX0CR_DSEL_Pos) /*!< USIC_CH DX0CR: DSEL Mask */
\r
1966 #define USIC_CH_DX0CR_INSW_Pos 4 /*!< USIC_CH DX0CR: INSW Position */
\r
1967 #define USIC_CH_DX0CR_INSW_Msk (0x01UL << USIC_CH_DX0CR_INSW_Pos) /*!< USIC_CH DX0CR: INSW Mask */
\r
1968 #define USIC_CH_DX0CR_DFEN_Pos 5 /*!< USIC_CH DX0CR: DFEN Position */
\r
1969 #define USIC_CH_DX0CR_DFEN_Msk (0x01UL << USIC_CH_DX0CR_DFEN_Pos) /*!< USIC_CH DX0CR: DFEN Mask */
\r
1970 #define USIC_CH_DX0CR_DSEN_Pos 6 /*!< USIC_CH DX0CR: DSEN Position */
\r
1971 #define USIC_CH_DX0CR_DSEN_Msk (0x01UL << USIC_CH_DX0CR_DSEN_Pos) /*!< USIC_CH DX0CR: DSEN Mask */
\r
1972 #define USIC_CH_DX0CR_DPOL_Pos 8 /*!< USIC_CH DX0CR: DPOL Position */
\r
1973 #define USIC_CH_DX0CR_DPOL_Msk (0x01UL << USIC_CH_DX0CR_DPOL_Pos) /*!< USIC_CH DX0CR: DPOL Mask */
\r
1974 #define USIC_CH_DX0CR_SFSEL_Pos 9 /*!< USIC_CH DX0CR: SFSEL Position */
\r
1975 #define USIC_CH_DX0CR_SFSEL_Msk (0x01UL << USIC_CH_DX0CR_SFSEL_Pos) /*!< USIC_CH DX0CR: SFSEL Mask */
\r
1976 #define USIC_CH_DX0CR_CM_Pos 10 /*!< USIC_CH DX0CR: CM Position */
\r
1977 #define USIC_CH_DX0CR_CM_Msk (0x03UL << USIC_CH_DX0CR_CM_Pos) /*!< USIC_CH DX0CR: CM Mask */
\r
1978 #define USIC_CH_DX0CR_DXS_Pos 15 /*!< USIC_CH DX0CR: DXS Position */
\r
1979 #define USIC_CH_DX0CR_DXS_Msk (0x01UL << USIC_CH_DX0CR_DXS_Pos) /*!< USIC_CH DX0CR: DXS Mask */
\r
1981 /* -------------------------------- USIC_CH_DX1CR ------------------------------- */
\r
1982 #define USIC_CH_DX1CR_DSEL_Pos 0 /*!< USIC_CH DX1CR: DSEL Position */
\r
1983 #define USIC_CH_DX1CR_DSEL_Msk (0x07UL << USIC_CH_DX1CR_DSEL_Pos) /*!< USIC_CH DX1CR: DSEL Mask */
\r
1984 #define USIC_CH_DX1CR_DCEN_Pos 3 /*!< USIC_CH DX1CR: DCEN Position */
\r
1985 #define USIC_CH_DX1CR_DCEN_Msk (0x01UL << USIC_CH_DX1CR_DCEN_Pos) /*!< USIC_CH DX1CR: DCEN Mask */
\r
1986 #define USIC_CH_DX1CR_INSW_Pos 4 /*!< USIC_CH DX1CR: INSW Position */
\r
1987 #define USIC_CH_DX1CR_INSW_Msk (0x01UL << USIC_CH_DX1CR_INSW_Pos) /*!< USIC_CH DX1CR: INSW Mask */
\r
1988 #define USIC_CH_DX1CR_DFEN_Pos 5 /*!< USIC_CH DX1CR: DFEN Position */
\r
1989 #define USIC_CH_DX1CR_DFEN_Msk (0x01UL << USIC_CH_DX1CR_DFEN_Pos) /*!< USIC_CH DX1CR: DFEN Mask */
\r
1990 #define USIC_CH_DX1CR_DSEN_Pos 6 /*!< USIC_CH DX1CR: DSEN Position */
\r
1991 #define USIC_CH_DX1CR_DSEN_Msk (0x01UL << USIC_CH_DX1CR_DSEN_Pos) /*!< USIC_CH DX1CR: DSEN Mask */
\r
1992 #define USIC_CH_DX1CR_DPOL_Pos 8 /*!< USIC_CH DX1CR: DPOL Position */
\r
1993 #define USIC_CH_DX1CR_DPOL_Msk (0x01UL << USIC_CH_DX1CR_DPOL_Pos) /*!< USIC_CH DX1CR: DPOL Mask */
\r
1994 #define USIC_CH_DX1CR_SFSEL_Pos 9 /*!< USIC_CH DX1CR: SFSEL Position */
\r
1995 #define USIC_CH_DX1CR_SFSEL_Msk (0x01UL << USIC_CH_DX1CR_SFSEL_Pos) /*!< USIC_CH DX1CR: SFSEL Mask */
\r
1996 #define USIC_CH_DX1CR_CM_Pos 10 /*!< USIC_CH DX1CR: CM Position */
\r
1997 #define USIC_CH_DX1CR_CM_Msk (0x03UL << USIC_CH_DX1CR_CM_Pos) /*!< USIC_CH DX1CR: CM Mask */
\r
1998 #define USIC_CH_DX1CR_DXS_Pos 15 /*!< USIC_CH DX1CR: DXS Position */
\r
1999 #define USIC_CH_DX1CR_DXS_Msk (0x01UL << USIC_CH_DX1CR_DXS_Pos) /*!< USIC_CH DX1CR: DXS Mask */
\r
2001 /* -------------------------------- USIC_CH_DX2CR ------------------------------- */
\r
2002 #define USIC_CH_DX2CR_DSEL_Pos 0 /*!< USIC_CH DX2CR: DSEL Position */
\r
2003 #define USIC_CH_DX2CR_DSEL_Msk (0x07UL << USIC_CH_DX2CR_DSEL_Pos) /*!< USIC_CH DX2CR: DSEL Mask */
\r
2004 #define USIC_CH_DX2CR_INSW_Pos 4 /*!< USIC_CH DX2CR: INSW Position */
\r
2005 #define USIC_CH_DX2CR_INSW_Msk (0x01UL << USIC_CH_DX2CR_INSW_Pos) /*!< USIC_CH DX2CR: INSW Mask */
\r
2006 #define USIC_CH_DX2CR_DFEN_Pos 5 /*!< USIC_CH DX2CR: DFEN Position */
\r
2007 #define USIC_CH_DX2CR_DFEN_Msk (0x01UL << USIC_CH_DX2CR_DFEN_Pos) /*!< USIC_CH DX2CR: DFEN Mask */
\r
2008 #define USIC_CH_DX2CR_DSEN_Pos 6 /*!< USIC_CH DX2CR: DSEN Position */
\r
2009 #define USIC_CH_DX2CR_DSEN_Msk (0x01UL << USIC_CH_DX2CR_DSEN_Pos) /*!< USIC_CH DX2CR: DSEN Mask */
\r
2010 #define USIC_CH_DX2CR_DPOL_Pos 8 /*!< USIC_CH DX2CR: DPOL Position */
\r
2011 #define USIC_CH_DX2CR_DPOL_Msk (0x01UL << USIC_CH_DX2CR_DPOL_Pos) /*!< USIC_CH DX2CR: DPOL Mask */
\r
2012 #define USIC_CH_DX2CR_SFSEL_Pos 9 /*!< USIC_CH DX2CR: SFSEL Position */
\r
2013 #define USIC_CH_DX2CR_SFSEL_Msk (0x01UL << USIC_CH_DX2CR_SFSEL_Pos) /*!< USIC_CH DX2CR: SFSEL Mask */
\r
2014 #define USIC_CH_DX2CR_CM_Pos 10 /*!< USIC_CH DX2CR: CM Position */
\r
2015 #define USIC_CH_DX2CR_CM_Msk (0x03UL << USIC_CH_DX2CR_CM_Pos) /*!< USIC_CH DX2CR: CM Mask */
\r
2016 #define USIC_CH_DX2CR_DXS_Pos 15 /*!< USIC_CH DX2CR: DXS Position */
\r
2017 #define USIC_CH_DX2CR_DXS_Msk (0x01UL << USIC_CH_DX2CR_DXS_Pos) /*!< USIC_CH DX2CR: DXS Mask */
\r
2019 /* -------------------------------- USIC_CH_DX3CR ------------------------------- */
\r
2020 #define USIC_CH_DX3CR_DSEL_Pos 0 /*!< USIC_CH DX3CR: DSEL Position */
\r
2021 #define USIC_CH_DX3CR_DSEL_Msk (0x07UL << USIC_CH_DX3CR_DSEL_Pos) /*!< USIC_CH DX3CR: DSEL Mask */
\r
2022 #define USIC_CH_DX3CR_INSW_Pos 4 /*!< USIC_CH DX3CR: INSW Position */
\r
2023 #define USIC_CH_DX3CR_INSW_Msk (0x01UL << USIC_CH_DX3CR_INSW_Pos) /*!< USIC_CH DX3CR: INSW Mask */
\r
2024 #define USIC_CH_DX3CR_DFEN_Pos 5 /*!< USIC_CH DX3CR: DFEN Position */
\r
2025 #define USIC_CH_DX3CR_DFEN_Msk (0x01UL << USIC_CH_DX3CR_DFEN_Pos) /*!< USIC_CH DX3CR: DFEN Mask */
\r
2026 #define USIC_CH_DX3CR_DSEN_Pos 6 /*!< USIC_CH DX3CR: DSEN Position */
\r
2027 #define USIC_CH_DX3CR_DSEN_Msk (0x01UL << USIC_CH_DX3CR_DSEN_Pos) /*!< USIC_CH DX3CR: DSEN Mask */
\r
2028 #define USIC_CH_DX3CR_DPOL_Pos 8 /*!< USIC_CH DX3CR: DPOL Position */
\r
2029 #define USIC_CH_DX3CR_DPOL_Msk (0x01UL << USIC_CH_DX3CR_DPOL_Pos) /*!< USIC_CH DX3CR: DPOL Mask */
\r
2030 #define USIC_CH_DX3CR_SFSEL_Pos 9 /*!< USIC_CH DX3CR: SFSEL Position */
\r
2031 #define USIC_CH_DX3CR_SFSEL_Msk (0x01UL << USIC_CH_DX3CR_SFSEL_Pos) /*!< USIC_CH DX3CR: SFSEL Mask */
\r
2032 #define USIC_CH_DX3CR_CM_Pos 10 /*!< USIC_CH DX3CR: CM Position */
\r
2033 #define USIC_CH_DX3CR_CM_Msk (0x03UL << USIC_CH_DX3CR_CM_Pos) /*!< USIC_CH DX3CR: CM Mask */
\r
2034 #define USIC_CH_DX3CR_DXS_Pos 15 /*!< USIC_CH DX3CR: DXS Position */
\r
2035 #define USIC_CH_DX3CR_DXS_Msk (0x01UL << USIC_CH_DX3CR_DXS_Pos) /*!< USIC_CH DX3CR: DXS Mask */
\r
2037 /* -------------------------------- USIC_CH_DX4CR ------------------------------- */
\r
2038 #define USIC_CH_DX4CR_DSEL_Pos 0 /*!< USIC_CH DX4CR: DSEL Position */
\r
2039 #define USIC_CH_DX4CR_DSEL_Msk (0x07UL << USIC_CH_DX4CR_DSEL_Pos) /*!< USIC_CH DX4CR: DSEL Mask */
\r
2040 #define USIC_CH_DX4CR_INSW_Pos 4 /*!< USIC_CH DX4CR: INSW Position */
\r
2041 #define USIC_CH_DX4CR_INSW_Msk (0x01UL << USIC_CH_DX4CR_INSW_Pos) /*!< USIC_CH DX4CR: INSW Mask */
\r
2042 #define USIC_CH_DX4CR_DFEN_Pos 5 /*!< USIC_CH DX4CR: DFEN Position */
\r
2043 #define USIC_CH_DX4CR_DFEN_Msk (0x01UL << USIC_CH_DX4CR_DFEN_Pos) /*!< USIC_CH DX4CR: DFEN Mask */
\r
2044 #define USIC_CH_DX4CR_DSEN_Pos 6 /*!< USIC_CH DX4CR: DSEN Position */
\r
2045 #define USIC_CH_DX4CR_DSEN_Msk (0x01UL << USIC_CH_DX4CR_DSEN_Pos) /*!< USIC_CH DX4CR: DSEN Mask */
\r
2046 #define USIC_CH_DX4CR_DPOL_Pos 8 /*!< USIC_CH DX4CR: DPOL Position */
\r
2047 #define USIC_CH_DX4CR_DPOL_Msk (0x01UL << USIC_CH_DX4CR_DPOL_Pos) /*!< USIC_CH DX4CR: DPOL Mask */
\r
2048 #define USIC_CH_DX4CR_SFSEL_Pos 9 /*!< USIC_CH DX4CR: SFSEL Position */
\r
2049 #define USIC_CH_DX4CR_SFSEL_Msk (0x01UL << USIC_CH_DX4CR_SFSEL_Pos) /*!< USIC_CH DX4CR: SFSEL Mask */
\r
2050 #define USIC_CH_DX4CR_CM_Pos 10 /*!< USIC_CH DX4CR: CM Position */
\r
2051 #define USIC_CH_DX4CR_CM_Msk (0x03UL << USIC_CH_DX4CR_CM_Pos) /*!< USIC_CH DX4CR: CM Mask */
\r
2052 #define USIC_CH_DX4CR_DXS_Pos 15 /*!< USIC_CH DX4CR: DXS Position */
\r
2053 #define USIC_CH_DX4CR_DXS_Msk (0x01UL << USIC_CH_DX4CR_DXS_Pos) /*!< USIC_CH DX4CR: DXS Mask */
\r
2055 /* -------------------------------- USIC_CH_DX5CR ------------------------------- */
\r
2056 #define USIC_CH_DX5CR_DSEL_Pos 0 /*!< USIC_CH DX5CR: DSEL Position */
\r
2057 #define USIC_CH_DX5CR_DSEL_Msk (0x07UL << USIC_CH_DX5CR_DSEL_Pos) /*!< USIC_CH DX5CR: DSEL Mask */
\r
2058 #define USIC_CH_DX5CR_INSW_Pos 4 /*!< USIC_CH DX5CR: INSW Position */
\r
2059 #define USIC_CH_DX5CR_INSW_Msk (0x01UL << USIC_CH_DX5CR_INSW_Pos) /*!< USIC_CH DX5CR: INSW Mask */
\r
2060 #define USIC_CH_DX5CR_DFEN_Pos 5 /*!< USIC_CH DX5CR: DFEN Position */
\r
2061 #define USIC_CH_DX5CR_DFEN_Msk (0x01UL << USIC_CH_DX5CR_DFEN_Pos) /*!< USIC_CH DX5CR: DFEN Mask */
\r
2062 #define USIC_CH_DX5CR_DSEN_Pos 6 /*!< USIC_CH DX5CR: DSEN Position */
\r
2063 #define USIC_CH_DX5CR_DSEN_Msk (0x01UL << USIC_CH_DX5CR_DSEN_Pos) /*!< USIC_CH DX5CR: DSEN Mask */
\r
2064 #define USIC_CH_DX5CR_DPOL_Pos 8 /*!< USIC_CH DX5CR: DPOL Position */
\r
2065 #define USIC_CH_DX5CR_DPOL_Msk (0x01UL << USIC_CH_DX5CR_DPOL_Pos) /*!< USIC_CH DX5CR: DPOL Mask */
\r
2066 #define USIC_CH_DX5CR_SFSEL_Pos 9 /*!< USIC_CH DX5CR: SFSEL Position */
\r
2067 #define USIC_CH_DX5CR_SFSEL_Msk (0x01UL << USIC_CH_DX5CR_SFSEL_Pos) /*!< USIC_CH DX5CR: SFSEL Mask */
\r
2068 #define USIC_CH_DX5CR_CM_Pos 10 /*!< USIC_CH DX5CR: CM Position */
\r
2069 #define USIC_CH_DX5CR_CM_Msk (0x03UL << USIC_CH_DX5CR_CM_Pos) /*!< USIC_CH DX5CR: CM Mask */
\r
2070 #define USIC_CH_DX5CR_DXS_Pos 15 /*!< USIC_CH DX5CR: DXS Position */
\r
2071 #define USIC_CH_DX5CR_DXS_Msk (0x01UL << USIC_CH_DX5CR_DXS_Pos) /*!< USIC_CH DX5CR: DXS Mask */
\r
2073 /* -------------------------------- USIC_CH_SCTR -------------------------------- */
\r
2074 #define USIC_CH_SCTR_SDIR_Pos 0 /*!< USIC_CH SCTR: SDIR Position */
\r
2075 #define USIC_CH_SCTR_SDIR_Msk (0x01UL << USIC_CH_SCTR_SDIR_Pos) /*!< USIC_CH SCTR: SDIR Mask */
\r
2076 #define USIC_CH_SCTR_PDL_Pos 1 /*!< USIC_CH SCTR: PDL Position */
\r
2077 #define USIC_CH_SCTR_PDL_Msk (0x01UL << USIC_CH_SCTR_PDL_Pos) /*!< USIC_CH SCTR: PDL Mask */
\r
2078 #define USIC_CH_SCTR_DSM_Pos 2 /*!< USIC_CH SCTR: DSM Position */
\r
2079 #define USIC_CH_SCTR_DSM_Msk (0x03UL << USIC_CH_SCTR_DSM_Pos) /*!< USIC_CH SCTR: DSM Mask */
\r
2080 #define USIC_CH_SCTR_HPCDIR_Pos 4 /*!< USIC_CH SCTR: HPCDIR Position */
\r
2081 #define USIC_CH_SCTR_HPCDIR_Msk (0x01UL << USIC_CH_SCTR_HPCDIR_Pos) /*!< USIC_CH SCTR: HPCDIR Mask */
\r
2082 #define USIC_CH_SCTR_DOCFG_Pos 6 /*!< USIC_CH SCTR: DOCFG Position */
\r
2083 #define USIC_CH_SCTR_DOCFG_Msk (0x03UL << USIC_CH_SCTR_DOCFG_Pos) /*!< USIC_CH SCTR: DOCFG Mask */
\r
2084 #define USIC_CH_SCTR_TRM_Pos 8 /*!< USIC_CH SCTR: TRM Position */
\r
2085 #define USIC_CH_SCTR_TRM_Msk (0x03UL << USIC_CH_SCTR_TRM_Pos) /*!< USIC_CH SCTR: TRM Mask */
\r
2086 #define USIC_CH_SCTR_FLE_Pos 16 /*!< USIC_CH SCTR: FLE Position */
\r
2087 #define USIC_CH_SCTR_FLE_Msk (0x3fUL << USIC_CH_SCTR_FLE_Pos) /*!< USIC_CH SCTR: FLE Mask */
\r
2088 #define USIC_CH_SCTR_WLE_Pos 24 /*!< USIC_CH SCTR: WLE Position */
\r
2089 #define USIC_CH_SCTR_WLE_Msk (0x0fUL << USIC_CH_SCTR_WLE_Pos) /*!< USIC_CH SCTR: WLE Mask */
\r
2091 /* -------------------------------- USIC_CH_TCSR -------------------------------- */
\r
2092 #define USIC_CH_TCSR_WLEMD_Pos 0 /*!< USIC_CH TCSR: WLEMD Position */
\r
2093 #define USIC_CH_TCSR_WLEMD_Msk (0x01UL << USIC_CH_TCSR_WLEMD_Pos) /*!< USIC_CH TCSR: WLEMD Mask */
\r
2094 #define USIC_CH_TCSR_SELMD_Pos 1 /*!< USIC_CH TCSR: SELMD Position */
\r
2095 #define USIC_CH_TCSR_SELMD_Msk (0x01UL << USIC_CH_TCSR_SELMD_Pos) /*!< USIC_CH TCSR: SELMD Mask */
\r
2096 #define USIC_CH_TCSR_FLEMD_Pos 2 /*!< USIC_CH TCSR: FLEMD Position */
\r
2097 #define USIC_CH_TCSR_FLEMD_Msk (0x01UL << USIC_CH_TCSR_FLEMD_Pos) /*!< USIC_CH TCSR: FLEMD Mask */
\r
2098 #define USIC_CH_TCSR_WAMD_Pos 3 /*!< USIC_CH TCSR: WAMD Position */
\r
2099 #define USIC_CH_TCSR_WAMD_Msk (0x01UL << USIC_CH_TCSR_WAMD_Pos) /*!< USIC_CH TCSR: WAMD Mask */
\r
2100 #define USIC_CH_TCSR_HPCMD_Pos 4 /*!< USIC_CH TCSR: HPCMD Position */
\r
2101 #define USIC_CH_TCSR_HPCMD_Msk (0x01UL << USIC_CH_TCSR_HPCMD_Pos) /*!< USIC_CH TCSR: HPCMD Mask */
\r
2102 #define USIC_CH_TCSR_SOF_Pos 5 /*!< USIC_CH TCSR: SOF Position */
\r
2103 #define USIC_CH_TCSR_SOF_Msk (0x01UL << USIC_CH_TCSR_SOF_Pos) /*!< USIC_CH TCSR: SOF Mask */
\r
2104 #define USIC_CH_TCSR_EOF_Pos 6 /*!< USIC_CH TCSR: EOF Position */
\r
2105 #define USIC_CH_TCSR_EOF_Msk (0x01UL << USIC_CH_TCSR_EOF_Pos) /*!< USIC_CH TCSR: EOF Mask */
\r
2106 #define USIC_CH_TCSR_TDV_Pos 7 /*!< USIC_CH TCSR: TDV Position */
\r
2107 #define USIC_CH_TCSR_TDV_Msk (0x01UL << USIC_CH_TCSR_TDV_Pos) /*!< USIC_CH TCSR: TDV Mask */
\r
2108 #define USIC_CH_TCSR_TDSSM_Pos 8 /*!< USIC_CH TCSR: TDSSM Position */
\r
2109 #define USIC_CH_TCSR_TDSSM_Msk (0x01UL << USIC_CH_TCSR_TDSSM_Pos) /*!< USIC_CH TCSR: TDSSM Mask */
\r
2110 #define USIC_CH_TCSR_TDEN_Pos 10 /*!< USIC_CH TCSR: TDEN Position */
\r
2111 #define USIC_CH_TCSR_TDEN_Msk (0x03UL << USIC_CH_TCSR_TDEN_Pos) /*!< USIC_CH TCSR: TDEN Mask */
\r
2112 #define USIC_CH_TCSR_TDVTR_Pos 12 /*!< USIC_CH TCSR: TDVTR Position */
\r
2113 #define USIC_CH_TCSR_TDVTR_Msk (0x01UL << USIC_CH_TCSR_TDVTR_Pos) /*!< USIC_CH TCSR: TDVTR Mask */
\r
2114 #define USIC_CH_TCSR_WA_Pos 13 /*!< USIC_CH TCSR: WA Position */
\r
2115 #define USIC_CH_TCSR_WA_Msk (0x01UL << USIC_CH_TCSR_WA_Pos) /*!< USIC_CH TCSR: WA Mask */
\r
2116 #define USIC_CH_TCSR_TSOF_Pos 24 /*!< USIC_CH TCSR: TSOF Position */
\r
2117 #define USIC_CH_TCSR_TSOF_Msk (0x01UL << USIC_CH_TCSR_TSOF_Pos) /*!< USIC_CH TCSR: TSOF Mask */
\r
2118 #define USIC_CH_TCSR_TV_Pos 26 /*!< USIC_CH TCSR: TV Position */
\r
2119 #define USIC_CH_TCSR_TV_Msk (0x01UL << USIC_CH_TCSR_TV_Pos) /*!< USIC_CH TCSR: TV Mask */
\r
2120 #define USIC_CH_TCSR_TVC_Pos 27 /*!< USIC_CH TCSR: TVC Position */
\r
2121 #define USIC_CH_TCSR_TVC_Msk (0x01UL << USIC_CH_TCSR_TVC_Pos) /*!< USIC_CH TCSR: TVC Mask */
\r
2122 #define USIC_CH_TCSR_TE_Pos 28 /*!< USIC_CH TCSR: TE Position */
\r
2123 #define USIC_CH_TCSR_TE_Msk (0x01UL << USIC_CH_TCSR_TE_Pos) /*!< USIC_CH TCSR: TE Mask */
\r
2125 /* --------------------------------- USIC_CH_PCR -------------------------------- */
\r
2126 #define USIC_CH_PCR_CTR0_Pos 0 /*!< USIC_CH PCR: CTR0 Position */
\r
2127 #define USIC_CH_PCR_CTR0_Msk (0x01UL << USIC_CH_PCR_CTR0_Pos) /*!< USIC_CH PCR: CTR0 Mask */
\r
2128 #define USIC_CH_PCR_CTR1_Pos 1 /*!< USIC_CH PCR: CTR1 Position */
\r
2129 #define USIC_CH_PCR_CTR1_Msk (0x01UL << USIC_CH_PCR_CTR1_Pos) /*!< USIC_CH PCR: CTR1 Mask */
\r
2130 #define USIC_CH_PCR_CTR2_Pos 2 /*!< USIC_CH PCR: CTR2 Position */
\r
2131 #define USIC_CH_PCR_CTR2_Msk (0x01UL << USIC_CH_PCR_CTR2_Pos) /*!< USIC_CH PCR: CTR2 Mask */
\r
2132 #define USIC_CH_PCR_CTR3_Pos 3 /*!< USIC_CH PCR: CTR3 Position */
\r
2133 #define USIC_CH_PCR_CTR3_Msk (0x01UL << USIC_CH_PCR_CTR3_Pos) /*!< USIC_CH PCR: CTR3 Mask */
\r
2134 #define USIC_CH_PCR_CTR4_Pos 4 /*!< USIC_CH PCR: CTR4 Position */
\r
2135 #define USIC_CH_PCR_CTR4_Msk (0x01UL << USIC_CH_PCR_CTR4_Pos) /*!< USIC_CH PCR: CTR4 Mask */
\r
2136 #define USIC_CH_PCR_CTR5_Pos 5 /*!< USIC_CH PCR: CTR5 Position */
\r
2137 #define USIC_CH_PCR_CTR5_Msk (0x01UL << USIC_CH_PCR_CTR5_Pos) /*!< USIC_CH PCR: CTR5 Mask */
\r
2138 #define USIC_CH_PCR_CTR6_Pos 6 /*!< USIC_CH PCR: CTR6 Position */
\r
2139 #define USIC_CH_PCR_CTR6_Msk (0x01UL << USIC_CH_PCR_CTR6_Pos) /*!< USIC_CH PCR: CTR6 Mask */
\r
2140 #define USIC_CH_PCR_CTR7_Pos 7 /*!< USIC_CH PCR: CTR7 Position */
\r
2141 #define USIC_CH_PCR_CTR7_Msk (0x01UL << USIC_CH_PCR_CTR7_Pos) /*!< USIC_CH PCR: CTR7 Mask */
\r
2142 #define USIC_CH_PCR_CTR8_Pos 8 /*!< USIC_CH PCR: CTR8 Position */
\r
2143 #define USIC_CH_PCR_CTR8_Msk (0x01UL << USIC_CH_PCR_CTR8_Pos) /*!< USIC_CH PCR: CTR8 Mask */
\r
2144 #define USIC_CH_PCR_CTR9_Pos 9 /*!< USIC_CH PCR: CTR9 Position */
\r
2145 #define USIC_CH_PCR_CTR9_Msk (0x01UL << USIC_CH_PCR_CTR9_Pos) /*!< USIC_CH PCR: CTR9 Mask */
\r
2146 #define USIC_CH_PCR_CTR10_Pos 10 /*!< USIC_CH PCR: CTR10 Position */
\r
2147 #define USIC_CH_PCR_CTR10_Msk (0x01UL << USIC_CH_PCR_CTR10_Pos) /*!< USIC_CH PCR: CTR10 Mask */
\r
2148 #define USIC_CH_PCR_CTR11_Pos 11 /*!< USIC_CH PCR: CTR11 Position */
\r
2149 #define USIC_CH_PCR_CTR11_Msk (0x01UL << USIC_CH_PCR_CTR11_Pos) /*!< USIC_CH PCR: CTR11 Mask */
\r
2150 #define USIC_CH_PCR_CTR12_Pos 12 /*!< USIC_CH PCR: CTR12 Position */
\r
2151 #define USIC_CH_PCR_CTR12_Msk (0x01UL << USIC_CH_PCR_CTR12_Pos) /*!< USIC_CH PCR: CTR12 Mask */
\r
2152 #define USIC_CH_PCR_CTR13_Pos 13 /*!< USIC_CH PCR: CTR13 Position */
\r
2153 #define USIC_CH_PCR_CTR13_Msk (0x01UL << USIC_CH_PCR_CTR13_Pos) /*!< USIC_CH PCR: CTR13 Mask */
\r
2154 #define USIC_CH_PCR_CTR14_Pos 14 /*!< USIC_CH PCR: CTR14 Position */
\r
2155 #define USIC_CH_PCR_CTR14_Msk (0x01UL << USIC_CH_PCR_CTR14_Pos) /*!< USIC_CH PCR: CTR14 Mask */
\r
2156 #define USIC_CH_PCR_CTR15_Pos 15 /*!< USIC_CH PCR: CTR15 Position */
\r
2157 #define USIC_CH_PCR_CTR15_Msk (0x01UL << USIC_CH_PCR_CTR15_Pos) /*!< USIC_CH PCR: CTR15 Mask */
\r
2158 #define USIC_CH_PCR_CTR16_Pos 16 /*!< USIC_CH PCR: CTR16 Position */
\r
2159 #define USIC_CH_PCR_CTR16_Msk (0x01UL << USIC_CH_PCR_CTR16_Pos) /*!< USIC_CH PCR: CTR16 Mask */
\r
2160 #define USIC_CH_PCR_CTR17_Pos 17 /*!< USIC_CH PCR: CTR17 Position */
\r
2161 #define USIC_CH_PCR_CTR17_Msk (0x01UL << USIC_CH_PCR_CTR17_Pos) /*!< USIC_CH PCR: CTR17 Mask */
\r
2162 #define USIC_CH_PCR_CTR18_Pos 18 /*!< USIC_CH PCR: CTR18 Position */
\r
2163 #define USIC_CH_PCR_CTR18_Msk (0x01UL << USIC_CH_PCR_CTR18_Pos) /*!< USIC_CH PCR: CTR18 Mask */
\r
2164 #define USIC_CH_PCR_CTR19_Pos 19 /*!< USIC_CH PCR: CTR19 Position */
\r
2165 #define USIC_CH_PCR_CTR19_Msk (0x01UL << USIC_CH_PCR_CTR19_Pos) /*!< USIC_CH PCR: CTR19 Mask */
\r
2166 #define USIC_CH_PCR_CTR20_Pos 20 /*!< USIC_CH PCR: CTR20 Position */
\r
2167 #define USIC_CH_PCR_CTR20_Msk (0x01UL << USIC_CH_PCR_CTR20_Pos) /*!< USIC_CH PCR: CTR20 Mask */
\r
2168 #define USIC_CH_PCR_CTR21_Pos 21 /*!< USIC_CH PCR: CTR21 Position */
\r
2169 #define USIC_CH_PCR_CTR21_Msk (0x01UL << USIC_CH_PCR_CTR21_Pos) /*!< USIC_CH PCR: CTR21 Mask */
\r
2170 #define USIC_CH_PCR_CTR22_Pos 22 /*!< USIC_CH PCR: CTR22 Position */
\r
2171 #define USIC_CH_PCR_CTR22_Msk (0x01UL << USIC_CH_PCR_CTR22_Pos) /*!< USIC_CH PCR: CTR22 Mask */
\r
2172 #define USIC_CH_PCR_CTR23_Pos 23 /*!< USIC_CH PCR: CTR23 Position */
\r
2173 #define USIC_CH_PCR_CTR23_Msk (0x01UL << USIC_CH_PCR_CTR23_Pos) /*!< USIC_CH PCR: CTR23 Mask */
\r
2174 #define USIC_CH_PCR_CTR24_Pos 24 /*!< USIC_CH PCR: CTR24 Position */
\r
2175 #define USIC_CH_PCR_CTR24_Msk (0x01UL << USIC_CH_PCR_CTR24_Pos) /*!< USIC_CH PCR: CTR24 Mask */
\r
2176 #define USIC_CH_PCR_CTR25_Pos 25 /*!< USIC_CH PCR: CTR25 Position */
\r
2177 #define USIC_CH_PCR_CTR25_Msk (0x01UL << USIC_CH_PCR_CTR25_Pos) /*!< USIC_CH PCR: CTR25 Mask */
\r
2178 #define USIC_CH_PCR_CTR26_Pos 26 /*!< USIC_CH PCR: CTR26 Position */
\r
2179 #define USIC_CH_PCR_CTR26_Msk (0x01UL << USIC_CH_PCR_CTR26_Pos) /*!< USIC_CH PCR: CTR26 Mask */
\r
2180 #define USIC_CH_PCR_CTR27_Pos 27 /*!< USIC_CH PCR: CTR27 Position */
\r
2181 #define USIC_CH_PCR_CTR27_Msk (0x01UL << USIC_CH_PCR_CTR27_Pos) /*!< USIC_CH PCR: CTR27 Mask */
\r
2182 #define USIC_CH_PCR_CTR28_Pos 28 /*!< USIC_CH PCR: CTR28 Position */
\r
2183 #define USIC_CH_PCR_CTR28_Msk (0x01UL << USIC_CH_PCR_CTR28_Pos) /*!< USIC_CH PCR: CTR28 Mask */
\r
2184 #define USIC_CH_PCR_CTR29_Pos 29 /*!< USIC_CH PCR: CTR29 Position */
\r
2185 #define USIC_CH_PCR_CTR29_Msk (0x01UL << USIC_CH_PCR_CTR29_Pos) /*!< USIC_CH PCR: CTR29 Mask */
\r
2186 #define USIC_CH_PCR_CTR30_Pos 30 /*!< USIC_CH PCR: CTR30 Position */
\r
2187 #define USIC_CH_PCR_CTR30_Msk (0x01UL << USIC_CH_PCR_CTR30_Pos) /*!< USIC_CH PCR: CTR30 Mask */
\r
2188 #define USIC_CH_PCR_CTR31_Pos 31 /*!< USIC_CH PCR: CTR31 Position */
\r
2189 #define USIC_CH_PCR_CTR31_Msk (0x01UL << USIC_CH_PCR_CTR31_Pos) /*!< USIC_CH PCR: CTR31 Mask */
\r
2191 /* ----------------------------- USIC_CH_PCR_ASCMode ---------------------------- */
\r
2192 #define USIC_CH_PCR_ASCMode_SMD_Pos 0 /*!< USIC_CH PCR_ASCMode: SMD Position */
\r
2193 #define USIC_CH_PCR_ASCMode_SMD_Msk (0x01UL << USIC_CH_PCR_ASCMode_SMD_Pos) /*!< USIC_CH PCR_ASCMode: SMD Mask */
\r
2194 #define USIC_CH_PCR_ASCMode_STPB_Pos 1 /*!< USIC_CH PCR_ASCMode: STPB Position */
\r
2195 #define USIC_CH_PCR_ASCMode_STPB_Msk (0x01UL << USIC_CH_PCR_ASCMode_STPB_Pos) /*!< USIC_CH PCR_ASCMode: STPB Mask */
\r
2196 #define USIC_CH_PCR_ASCMode_IDM_Pos 2 /*!< USIC_CH PCR_ASCMode: IDM Position */
\r
2197 #define USIC_CH_PCR_ASCMode_IDM_Msk (0x01UL << USIC_CH_PCR_ASCMode_IDM_Pos) /*!< USIC_CH PCR_ASCMode: IDM Mask */
\r
2198 #define USIC_CH_PCR_ASCMode_SBIEN_Pos 3 /*!< USIC_CH PCR_ASCMode: SBIEN Position */
\r
2199 #define USIC_CH_PCR_ASCMode_SBIEN_Msk (0x01UL << USIC_CH_PCR_ASCMode_SBIEN_Pos) /*!< USIC_CH PCR_ASCMode: SBIEN Mask */
\r
2200 #define USIC_CH_PCR_ASCMode_CDEN_Pos 4 /*!< USIC_CH PCR_ASCMode: CDEN Position */
\r
2201 #define USIC_CH_PCR_ASCMode_CDEN_Msk (0x01UL << USIC_CH_PCR_ASCMode_CDEN_Pos) /*!< USIC_CH PCR_ASCMode: CDEN Mask */
\r
2202 #define USIC_CH_PCR_ASCMode_RNIEN_Pos 5 /*!< USIC_CH PCR_ASCMode: RNIEN Position */
\r
2203 #define USIC_CH_PCR_ASCMode_RNIEN_Msk (0x01UL << USIC_CH_PCR_ASCMode_RNIEN_Pos) /*!< USIC_CH PCR_ASCMode: RNIEN Mask */
\r
2204 #define USIC_CH_PCR_ASCMode_FEIEN_Pos 6 /*!< USIC_CH PCR_ASCMode: FEIEN Position */
\r
2205 #define USIC_CH_PCR_ASCMode_FEIEN_Msk (0x01UL << USIC_CH_PCR_ASCMode_FEIEN_Pos) /*!< USIC_CH PCR_ASCMode: FEIEN Mask */
\r
2206 #define USIC_CH_PCR_ASCMode_FFIEN_Pos 7 /*!< USIC_CH PCR_ASCMode: FFIEN Position */
\r
2207 #define USIC_CH_PCR_ASCMode_FFIEN_Msk (0x01UL << USIC_CH_PCR_ASCMode_FFIEN_Pos) /*!< USIC_CH PCR_ASCMode: FFIEN Mask */
\r
2208 #define USIC_CH_PCR_ASCMode_SP_Pos 8 /*!< USIC_CH PCR_ASCMode: SP Position */
\r
2209 #define USIC_CH_PCR_ASCMode_SP_Msk (0x1fUL << USIC_CH_PCR_ASCMode_SP_Pos) /*!< USIC_CH PCR_ASCMode: SP Mask */
\r
2210 #define USIC_CH_PCR_ASCMode_PL_Pos 13 /*!< USIC_CH PCR_ASCMode: PL Position */
\r
2211 #define USIC_CH_PCR_ASCMode_PL_Msk (0x07UL << USIC_CH_PCR_ASCMode_PL_Pos) /*!< USIC_CH PCR_ASCMode: PL Mask */
\r
2212 #define USIC_CH_PCR_ASCMode_RSTEN_Pos 16 /*!< USIC_CH PCR_ASCMode: RSTEN Position */
\r
2213 #define USIC_CH_PCR_ASCMode_RSTEN_Msk (0x01UL << USIC_CH_PCR_ASCMode_RSTEN_Pos) /*!< USIC_CH PCR_ASCMode: RSTEN Mask */
\r
2214 #define USIC_CH_PCR_ASCMode_TSTEN_Pos 17 /*!< USIC_CH PCR_ASCMode: TSTEN Position */
\r
2215 #define USIC_CH_PCR_ASCMode_TSTEN_Msk (0x01UL << USIC_CH_PCR_ASCMode_TSTEN_Pos) /*!< USIC_CH PCR_ASCMode: TSTEN Mask */
\r
2216 #define USIC_CH_PCR_ASCMode_MCLK_Pos 31 /*!< USIC_CH PCR_ASCMode: MCLK Position */
\r
2217 #define USIC_CH_PCR_ASCMode_MCLK_Msk (0x01UL << USIC_CH_PCR_ASCMode_MCLK_Pos) /*!< USIC_CH PCR_ASCMode: MCLK Mask */
\r
2219 /* ----------------------------- USIC_CH_PCR_SSCMode ---------------------------- */
\r
2220 #define USIC_CH_PCR_SSCMode_MSLSEN_Pos 0 /*!< USIC_CH PCR_SSCMode: MSLSEN Position */
\r
2221 #define USIC_CH_PCR_SSCMode_MSLSEN_Msk (0x01UL << USIC_CH_PCR_SSCMode_MSLSEN_Pos) /*!< USIC_CH PCR_SSCMode: MSLSEN Mask */
\r
2222 #define USIC_CH_PCR_SSCMode_SELCTR_Pos 1 /*!< USIC_CH PCR_SSCMode: SELCTR Position */
\r
2223 #define USIC_CH_PCR_SSCMode_SELCTR_Msk (0x01UL << USIC_CH_PCR_SSCMode_SELCTR_Pos) /*!< USIC_CH PCR_SSCMode: SELCTR Mask */
\r
2224 #define USIC_CH_PCR_SSCMode_SELINV_Pos 2 /*!< USIC_CH PCR_SSCMode: SELINV Position */
\r
2225 #define USIC_CH_PCR_SSCMode_SELINV_Msk (0x01UL << USIC_CH_PCR_SSCMode_SELINV_Pos) /*!< USIC_CH PCR_SSCMode: SELINV Mask */
\r
2226 #define USIC_CH_PCR_SSCMode_FEM_Pos 3 /*!< USIC_CH PCR_SSCMode: FEM Position */
\r
2227 #define USIC_CH_PCR_SSCMode_FEM_Msk (0x01UL << USIC_CH_PCR_SSCMode_FEM_Pos) /*!< USIC_CH PCR_SSCMode: FEM Mask */
\r
2228 #define USIC_CH_PCR_SSCMode_CTQSEL1_Pos 4 /*!< USIC_CH PCR_SSCMode: CTQSEL1 Position */
\r
2229 #define USIC_CH_PCR_SSCMode_CTQSEL1_Msk (0x03UL << USIC_CH_PCR_SSCMode_CTQSEL1_Pos) /*!< USIC_CH PCR_SSCMode: CTQSEL1 Mask */
\r
2230 #define USIC_CH_PCR_SSCMode_PCTQ1_Pos 6 /*!< USIC_CH PCR_SSCMode: PCTQ1 Position */
\r
2231 #define USIC_CH_PCR_SSCMode_PCTQ1_Msk (0x03UL << USIC_CH_PCR_SSCMode_PCTQ1_Pos) /*!< USIC_CH PCR_SSCMode: PCTQ1 Mask */
\r
2232 #define USIC_CH_PCR_SSCMode_DCTQ1_Pos 8 /*!< USIC_CH PCR_SSCMode: DCTQ1 Position */
\r
2233 #define USIC_CH_PCR_SSCMode_DCTQ1_Msk (0x1fUL << USIC_CH_PCR_SSCMode_DCTQ1_Pos) /*!< USIC_CH PCR_SSCMode: DCTQ1 Mask */
\r
2234 #define USIC_CH_PCR_SSCMode_PARIEN_Pos 13 /*!< USIC_CH PCR_SSCMode: PARIEN Position */
\r
2235 #define USIC_CH_PCR_SSCMode_PARIEN_Msk (0x01UL << USIC_CH_PCR_SSCMode_PARIEN_Pos) /*!< USIC_CH PCR_SSCMode: PARIEN Mask */
\r
2236 #define USIC_CH_PCR_SSCMode_MSLSIEN_Pos 14 /*!< USIC_CH PCR_SSCMode: MSLSIEN Position */
\r
2237 #define USIC_CH_PCR_SSCMode_MSLSIEN_Msk (0x01UL << USIC_CH_PCR_SSCMode_MSLSIEN_Pos) /*!< USIC_CH PCR_SSCMode: MSLSIEN Mask */
\r
2238 #define USIC_CH_PCR_SSCMode_DX2TIEN_Pos 15 /*!< USIC_CH PCR_SSCMode: DX2TIEN Position */
\r
2239 #define USIC_CH_PCR_SSCMode_DX2TIEN_Msk (0x01UL << USIC_CH_PCR_SSCMode_DX2TIEN_Pos) /*!< USIC_CH PCR_SSCMode: DX2TIEN Mask */
\r
2240 #define USIC_CH_PCR_SSCMode_SELO_Pos 16 /*!< USIC_CH PCR_SSCMode: SELO Position */
\r
2241 #define USIC_CH_PCR_SSCMode_SELO_Msk (0x000000ffUL << USIC_CH_PCR_SSCMode_SELO_Pos) /*!< USIC_CH PCR_SSCMode: SELO Mask */
\r
2242 #define USIC_CH_PCR_SSCMode_TIWEN_Pos 24 /*!< USIC_CH PCR_SSCMode: TIWEN Position */
\r
2243 #define USIC_CH_PCR_SSCMode_TIWEN_Msk (0x01UL << USIC_CH_PCR_SSCMode_TIWEN_Pos) /*!< USIC_CH PCR_SSCMode: TIWEN Mask */
\r
2244 #define USIC_CH_PCR_SSCMode_MCLK_Pos 31 /*!< USIC_CH PCR_SSCMode: MCLK Position */
\r
2245 #define USIC_CH_PCR_SSCMode_MCLK_Msk (0x01UL << USIC_CH_PCR_SSCMode_MCLK_Pos) /*!< USIC_CH PCR_SSCMode: MCLK Mask */
\r
2247 /* ----------------------------- USIC_CH_PCR_IICMode ---------------------------- */
\r
2248 #define USIC_CH_PCR_IICMode_SLAD_Pos 0 /*!< USIC_CH PCR_IICMode: SLAD Position */
\r
2249 #define USIC_CH_PCR_IICMode_SLAD_Msk (0x0000ffffUL << USIC_CH_PCR_IICMode_SLAD_Pos) /*!< USIC_CH PCR_IICMode: SLAD Mask */
\r
2250 #define USIC_CH_PCR_IICMode_ACK00_Pos 16 /*!< USIC_CH PCR_IICMode: ACK00 Position */
\r
2251 #define USIC_CH_PCR_IICMode_ACK00_Msk (0x01UL << USIC_CH_PCR_IICMode_ACK00_Pos) /*!< USIC_CH PCR_IICMode: ACK00 Mask */
\r
2252 #define USIC_CH_PCR_IICMode_STIM_Pos 17 /*!< USIC_CH PCR_IICMode: STIM Position */
\r
2253 #define USIC_CH_PCR_IICMode_STIM_Msk (0x01UL << USIC_CH_PCR_IICMode_STIM_Pos) /*!< USIC_CH PCR_IICMode: STIM Mask */
\r
2254 #define USIC_CH_PCR_IICMode_SCRIEN_Pos 18 /*!< USIC_CH PCR_IICMode: SCRIEN Position */
\r
2255 #define USIC_CH_PCR_IICMode_SCRIEN_Msk (0x01UL << USIC_CH_PCR_IICMode_SCRIEN_Pos) /*!< USIC_CH PCR_IICMode: SCRIEN Mask */
\r
2256 #define USIC_CH_PCR_IICMode_RSCRIEN_Pos 19 /*!< USIC_CH PCR_IICMode: RSCRIEN Position */
\r
2257 #define USIC_CH_PCR_IICMode_RSCRIEN_Msk (0x01UL << USIC_CH_PCR_IICMode_RSCRIEN_Pos) /*!< USIC_CH PCR_IICMode: RSCRIEN Mask */
\r
2258 #define USIC_CH_PCR_IICMode_PCRIEN_Pos 20 /*!< USIC_CH PCR_IICMode: PCRIEN Position */
\r
2259 #define USIC_CH_PCR_IICMode_PCRIEN_Msk (0x01UL << USIC_CH_PCR_IICMode_PCRIEN_Pos) /*!< USIC_CH PCR_IICMode: PCRIEN Mask */
\r
2260 #define USIC_CH_PCR_IICMode_NACKIEN_Pos 21 /*!< USIC_CH PCR_IICMode: NACKIEN Position */
\r
2261 #define USIC_CH_PCR_IICMode_NACKIEN_Msk (0x01UL << USIC_CH_PCR_IICMode_NACKIEN_Pos) /*!< USIC_CH PCR_IICMode: NACKIEN Mask */
\r
2262 #define USIC_CH_PCR_IICMode_ARLIEN_Pos 22 /*!< USIC_CH PCR_IICMode: ARLIEN Position */
\r
2263 #define USIC_CH_PCR_IICMode_ARLIEN_Msk (0x01UL << USIC_CH_PCR_IICMode_ARLIEN_Pos) /*!< USIC_CH PCR_IICMode: ARLIEN Mask */
\r
2264 #define USIC_CH_PCR_IICMode_SRRIEN_Pos 23 /*!< USIC_CH PCR_IICMode: SRRIEN Position */
\r
2265 #define USIC_CH_PCR_IICMode_SRRIEN_Msk (0x01UL << USIC_CH_PCR_IICMode_SRRIEN_Pos) /*!< USIC_CH PCR_IICMode: SRRIEN Mask */
\r
2266 #define USIC_CH_PCR_IICMode_ERRIEN_Pos 24 /*!< USIC_CH PCR_IICMode: ERRIEN Position */
\r
2267 #define USIC_CH_PCR_IICMode_ERRIEN_Msk (0x01UL << USIC_CH_PCR_IICMode_ERRIEN_Pos) /*!< USIC_CH PCR_IICMode: ERRIEN Mask */
\r
2268 #define USIC_CH_PCR_IICMode_SACKDIS_Pos 25 /*!< USIC_CH PCR_IICMode: SACKDIS Position */
\r
2269 #define USIC_CH_PCR_IICMode_SACKDIS_Msk (0x01UL << USIC_CH_PCR_IICMode_SACKDIS_Pos) /*!< USIC_CH PCR_IICMode: SACKDIS Mask */
\r
2270 #define USIC_CH_PCR_IICMode_HDEL_Pos 26 /*!< USIC_CH PCR_IICMode: HDEL Position */
\r
2271 #define USIC_CH_PCR_IICMode_HDEL_Msk (0x0fUL << USIC_CH_PCR_IICMode_HDEL_Pos) /*!< USIC_CH PCR_IICMode: HDEL Mask */
\r
2272 #define USIC_CH_PCR_IICMode_ACKIEN_Pos 30 /*!< USIC_CH PCR_IICMode: ACKIEN Position */
\r
2273 #define USIC_CH_PCR_IICMode_ACKIEN_Msk (0x01UL << USIC_CH_PCR_IICMode_ACKIEN_Pos) /*!< USIC_CH PCR_IICMode: ACKIEN Mask */
\r
2274 #define USIC_CH_PCR_IICMode_MCLK_Pos 31 /*!< USIC_CH PCR_IICMode: MCLK Position */
\r
2275 #define USIC_CH_PCR_IICMode_MCLK_Msk (0x01UL << USIC_CH_PCR_IICMode_MCLK_Pos) /*!< USIC_CH PCR_IICMode: MCLK Mask */
\r
2277 /* ----------------------------- USIC_CH_PCR_IISMode ---------------------------- */
\r
2278 #define USIC_CH_PCR_IISMode_WAGEN_Pos 0 /*!< USIC_CH PCR_IISMode: WAGEN Position */
\r
2279 #define USIC_CH_PCR_IISMode_WAGEN_Msk (0x01UL << USIC_CH_PCR_IISMode_WAGEN_Pos) /*!< USIC_CH PCR_IISMode: WAGEN Mask */
\r
2280 #define USIC_CH_PCR_IISMode_DTEN_Pos 1 /*!< USIC_CH PCR_IISMode: DTEN Position */
\r
2281 #define USIC_CH_PCR_IISMode_DTEN_Msk (0x01UL << USIC_CH_PCR_IISMode_DTEN_Pos) /*!< USIC_CH PCR_IISMode: DTEN Mask */
\r
2282 #define USIC_CH_PCR_IISMode_SELINV_Pos 2 /*!< USIC_CH PCR_IISMode: SELINV Position */
\r
2283 #define USIC_CH_PCR_IISMode_SELINV_Msk (0x01UL << USIC_CH_PCR_IISMode_SELINV_Pos) /*!< USIC_CH PCR_IISMode: SELINV Mask */
\r
2284 #define USIC_CH_PCR_IISMode_WAFEIEN_Pos 4 /*!< USIC_CH PCR_IISMode: WAFEIEN Position */
\r
2285 #define USIC_CH_PCR_IISMode_WAFEIEN_Msk (0x01UL << USIC_CH_PCR_IISMode_WAFEIEN_Pos) /*!< USIC_CH PCR_IISMode: WAFEIEN Mask */
\r
2286 #define USIC_CH_PCR_IISMode_WAREIEN_Pos 5 /*!< USIC_CH PCR_IISMode: WAREIEN Position */
\r
2287 #define USIC_CH_PCR_IISMode_WAREIEN_Msk (0x01UL << USIC_CH_PCR_IISMode_WAREIEN_Pos) /*!< USIC_CH PCR_IISMode: WAREIEN Mask */
\r
2288 #define USIC_CH_PCR_IISMode_ENDIEN_Pos 6 /*!< USIC_CH PCR_IISMode: ENDIEN Position */
\r
2289 #define USIC_CH_PCR_IISMode_ENDIEN_Msk (0x01UL << USIC_CH_PCR_IISMode_ENDIEN_Pos) /*!< USIC_CH PCR_IISMode: ENDIEN Mask */
\r
2290 #define USIC_CH_PCR_IISMode_DX2TIEN_Pos 15 /*!< USIC_CH PCR_IISMode: DX2TIEN Position */
\r
2291 #define USIC_CH_PCR_IISMode_DX2TIEN_Msk (0x01UL << USIC_CH_PCR_IISMode_DX2TIEN_Pos) /*!< USIC_CH PCR_IISMode: DX2TIEN Mask */
\r
2292 #define USIC_CH_PCR_IISMode_TDEL_Pos 16 /*!< USIC_CH PCR_IISMode: TDEL Position */
\r
2293 #define USIC_CH_PCR_IISMode_TDEL_Msk (0x3fUL << USIC_CH_PCR_IISMode_TDEL_Pos) /*!< USIC_CH PCR_IISMode: TDEL Mask */
\r
2294 #define USIC_CH_PCR_IISMode_MCLK_Pos 31 /*!< USIC_CH PCR_IISMode: MCLK Position */
\r
2295 #define USIC_CH_PCR_IISMode_MCLK_Msk (0x01UL << USIC_CH_PCR_IISMode_MCLK_Pos) /*!< USIC_CH PCR_IISMode: MCLK Mask */
\r
2297 /* --------------------------------- USIC_CH_CCR -------------------------------- */
\r
2298 #define USIC_CH_CCR_MODE_Pos 0 /*!< USIC_CH CCR: MODE Position */
\r
2299 #define USIC_CH_CCR_MODE_Msk (0x0fUL << USIC_CH_CCR_MODE_Pos) /*!< USIC_CH CCR: MODE Mask */
\r
2300 #define USIC_CH_CCR_HPCEN_Pos 6 /*!< USIC_CH CCR: HPCEN Position */
\r
2301 #define USIC_CH_CCR_HPCEN_Msk (0x03UL << USIC_CH_CCR_HPCEN_Pos) /*!< USIC_CH CCR: HPCEN Mask */
\r
2302 #define USIC_CH_CCR_PM_Pos 8 /*!< USIC_CH CCR: PM Position */
\r
2303 #define USIC_CH_CCR_PM_Msk (0x03UL << USIC_CH_CCR_PM_Pos) /*!< USIC_CH CCR: PM Mask */
\r
2304 #define USIC_CH_CCR_RSIEN_Pos 10 /*!< USIC_CH CCR: RSIEN Position */
\r
2305 #define USIC_CH_CCR_RSIEN_Msk (0x01UL << USIC_CH_CCR_RSIEN_Pos) /*!< USIC_CH CCR: RSIEN Mask */
\r
2306 #define USIC_CH_CCR_DLIEN_Pos 11 /*!< USIC_CH CCR: DLIEN Position */
\r
2307 #define USIC_CH_CCR_DLIEN_Msk (0x01UL << USIC_CH_CCR_DLIEN_Pos) /*!< USIC_CH CCR: DLIEN Mask */
\r
2308 #define USIC_CH_CCR_TSIEN_Pos 12 /*!< USIC_CH CCR: TSIEN Position */
\r
2309 #define USIC_CH_CCR_TSIEN_Msk (0x01UL << USIC_CH_CCR_TSIEN_Pos) /*!< USIC_CH CCR: TSIEN Mask */
\r
2310 #define USIC_CH_CCR_TBIEN_Pos 13 /*!< USIC_CH CCR: TBIEN Position */
\r
2311 #define USIC_CH_CCR_TBIEN_Msk (0x01UL << USIC_CH_CCR_TBIEN_Pos) /*!< USIC_CH CCR: TBIEN Mask */
\r
2312 #define USIC_CH_CCR_RIEN_Pos 14 /*!< USIC_CH CCR: RIEN Position */
\r
2313 #define USIC_CH_CCR_RIEN_Msk (0x01UL << USIC_CH_CCR_RIEN_Pos) /*!< USIC_CH CCR: RIEN Mask */
\r
2314 #define USIC_CH_CCR_AIEN_Pos 15 /*!< USIC_CH CCR: AIEN Position */
\r
2315 #define USIC_CH_CCR_AIEN_Msk (0x01UL << USIC_CH_CCR_AIEN_Pos) /*!< USIC_CH CCR: AIEN Mask */
\r
2316 #define USIC_CH_CCR_BRGIEN_Pos 16 /*!< USIC_CH CCR: BRGIEN Position */
\r
2317 #define USIC_CH_CCR_BRGIEN_Msk (0x01UL << USIC_CH_CCR_BRGIEN_Pos) /*!< USIC_CH CCR: BRGIEN Mask */
\r
2319 /* -------------------------------- USIC_CH_CMTR -------------------------------- */
\r
2320 #define USIC_CH_CMTR_CTV_Pos 0 /*!< USIC_CH CMTR: CTV Position */
\r
2321 #define USIC_CH_CMTR_CTV_Msk (0x000003ffUL << USIC_CH_CMTR_CTV_Pos) /*!< USIC_CH CMTR: CTV Mask */
\r
2323 /* --------------------------------- USIC_CH_PSR -------------------------------- */
\r
2324 #define USIC_CH_PSR_ST0_Pos 0 /*!< USIC_CH PSR: ST0 Position */
\r
2325 #define USIC_CH_PSR_ST0_Msk (0x01UL << USIC_CH_PSR_ST0_Pos) /*!< USIC_CH PSR: ST0 Mask */
\r
2326 #define USIC_CH_PSR_ST1_Pos 1 /*!< USIC_CH PSR: ST1 Position */
\r
2327 #define USIC_CH_PSR_ST1_Msk (0x01UL << USIC_CH_PSR_ST1_Pos) /*!< USIC_CH PSR: ST1 Mask */
\r
2328 #define USIC_CH_PSR_ST2_Pos 2 /*!< USIC_CH PSR: ST2 Position */
\r
2329 #define USIC_CH_PSR_ST2_Msk (0x01UL << USIC_CH_PSR_ST2_Pos) /*!< USIC_CH PSR: ST2 Mask */
\r
2330 #define USIC_CH_PSR_ST3_Pos 3 /*!< USIC_CH PSR: ST3 Position */
\r
2331 #define USIC_CH_PSR_ST3_Msk (0x01UL << USIC_CH_PSR_ST3_Pos) /*!< USIC_CH PSR: ST3 Mask */
\r
2332 #define USIC_CH_PSR_ST4_Pos 4 /*!< USIC_CH PSR: ST4 Position */
\r
2333 #define USIC_CH_PSR_ST4_Msk (0x01UL << USIC_CH_PSR_ST4_Pos) /*!< USIC_CH PSR: ST4 Mask */
\r
2334 #define USIC_CH_PSR_ST5_Pos 5 /*!< USIC_CH PSR: ST5 Position */
\r
2335 #define USIC_CH_PSR_ST5_Msk (0x01UL << USIC_CH_PSR_ST5_Pos) /*!< USIC_CH PSR: ST5 Mask */
\r
2336 #define USIC_CH_PSR_ST6_Pos 6 /*!< USIC_CH PSR: ST6 Position */
\r
2337 #define USIC_CH_PSR_ST6_Msk (0x01UL << USIC_CH_PSR_ST6_Pos) /*!< USIC_CH PSR: ST6 Mask */
\r
2338 #define USIC_CH_PSR_ST7_Pos 7 /*!< USIC_CH PSR: ST7 Position */
\r
2339 #define USIC_CH_PSR_ST7_Msk (0x01UL << USIC_CH_PSR_ST7_Pos) /*!< USIC_CH PSR: ST7 Mask */
\r
2340 #define USIC_CH_PSR_ST8_Pos 8 /*!< USIC_CH PSR: ST8 Position */
\r
2341 #define USIC_CH_PSR_ST8_Msk (0x01UL << USIC_CH_PSR_ST8_Pos) /*!< USIC_CH PSR: ST8 Mask */
\r
2342 #define USIC_CH_PSR_ST9_Pos 9 /*!< USIC_CH PSR: ST9 Position */
\r
2343 #define USIC_CH_PSR_ST9_Msk (0x01UL << USIC_CH_PSR_ST9_Pos) /*!< USIC_CH PSR: ST9 Mask */
\r
2344 #define USIC_CH_PSR_RSIF_Pos 10 /*!< USIC_CH PSR: RSIF Position */
\r
2345 #define USIC_CH_PSR_RSIF_Msk (0x01UL << USIC_CH_PSR_RSIF_Pos) /*!< USIC_CH PSR: RSIF Mask */
\r
2346 #define USIC_CH_PSR_DLIF_Pos 11 /*!< USIC_CH PSR: DLIF Position */
\r
2347 #define USIC_CH_PSR_DLIF_Msk (0x01UL << USIC_CH_PSR_DLIF_Pos) /*!< USIC_CH PSR: DLIF Mask */
\r
2348 #define USIC_CH_PSR_TSIF_Pos 12 /*!< USIC_CH PSR: TSIF Position */
\r
2349 #define USIC_CH_PSR_TSIF_Msk (0x01UL << USIC_CH_PSR_TSIF_Pos) /*!< USIC_CH PSR: TSIF Mask */
\r
2350 #define USIC_CH_PSR_TBIF_Pos 13 /*!< USIC_CH PSR: TBIF Position */
\r
2351 #define USIC_CH_PSR_TBIF_Msk (0x01UL << USIC_CH_PSR_TBIF_Pos) /*!< USIC_CH PSR: TBIF Mask */
\r
2352 #define USIC_CH_PSR_RIF_Pos 14 /*!< USIC_CH PSR: RIF Position */
\r
2353 #define USIC_CH_PSR_RIF_Msk (0x01UL << USIC_CH_PSR_RIF_Pos) /*!< USIC_CH PSR: RIF Mask */
\r
2354 #define USIC_CH_PSR_AIF_Pos 15 /*!< USIC_CH PSR: AIF Position */
\r
2355 #define USIC_CH_PSR_AIF_Msk (0x01UL << USIC_CH_PSR_AIF_Pos) /*!< USIC_CH PSR: AIF Mask */
\r
2356 #define USIC_CH_PSR_BRGIF_Pos 16 /*!< USIC_CH PSR: BRGIF Position */
\r
2357 #define USIC_CH_PSR_BRGIF_Msk (0x01UL << USIC_CH_PSR_BRGIF_Pos) /*!< USIC_CH PSR: BRGIF Mask */
\r
2359 /* ----------------------------- USIC_CH_PSR_ASCMode ---------------------------- */
\r
2360 #define USIC_CH_PSR_ASCMode_TXIDLE_Pos 0 /*!< USIC_CH PSR_ASCMode: TXIDLE Position */
\r
2361 #define USIC_CH_PSR_ASCMode_TXIDLE_Msk (0x01UL << USIC_CH_PSR_ASCMode_TXIDLE_Pos) /*!< USIC_CH PSR_ASCMode: TXIDLE Mask */
\r
2362 #define USIC_CH_PSR_ASCMode_RXIDLE_Pos 1 /*!< USIC_CH PSR_ASCMode: RXIDLE Position */
\r
2363 #define USIC_CH_PSR_ASCMode_RXIDLE_Msk (0x01UL << USIC_CH_PSR_ASCMode_RXIDLE_Pos) /*!< USIC_CH PSR_ASCMode: RXIDLE Mask */
\r
2364 #define USIC_CH_PSR_ASCMode_SBD_Pos 2 /*!< USIC_CH PSR_ASCMode: SBD Position */
\r
2365 #define USIC_CH_PSR_ASCMode_SBD_Msk (0x01UL << USIC_CH_PSR_ASCMode_SBD_Pos) /*!< USIC_CH PSR_ASCMode: SBD Mask */
\r
2366 #define USIC_CH_PSR_ASCMode_COL_Pos 3 /*!< USIC_CH PSR_ASCMode: COL Position */
\r
2367 #define USIC_CH_PSR_ASCMode_COL_Msk (0x01UL << USIC_CH_PSR_ASCMode_COL_Pos) /*!< USIC_CH PSR_ASCMode: COL Mask */
\r
2368 #define USIC_CH_PSR_ASCMode_RNS_Pos 4 /*!< USIC_CH PSR_ASCMode: RNS Position */
\r
2369 #define USIC_CH_PSR_ASCMode_RNS_Msk (0x01UL << USIC_CH_PSR_ASCMode_RNS_Pos) /*!< USIC_CH PSR_ASCMode: RNS Mask */
\r
2370 #define USIC_CH_PSR_ASCMode_FER0_Pos 5 /*!< USIC_CH PSR_ASCMode: FER0 Position */
\r
2371 #define USIC_CH_PSR_ASCMode_FER0_Msk (0x01UL << USIC_CH_PSR_ASCMode_FER0_Pos) /*!< USIC_CH PSR_ASCMode: FER0 Mask */
\r
2372 #define USIC_CH_PSR_ASCMode_FER1_Pos 6 /*!< USIC_CH PSR_ASCMode: FER1 Position */
\r
2373 #define USIC_CH_PSR_ASCMode_FER1_Msk (0x01UL << USIC_CH_PSR_ASCMode_FER1_Pos) /*!< USIC_CH PSR_ASCMode: FER1 Mask */
\r
2374 #define USIC_CH_PSR_ASCMode_RFF_Pos 7 /*!< USIC_CH PSR_ASCMode: RFF Position */
\r
2375 #define USIC_CH_PSR_ASCMode_RFF_Msk (0x01UL << USIC_CH_PSR_ASCMode_RFF_Pos) /*!< USIC_CH PSR_ASCMode: RFF Mask */
\r
2376 #define USIC_CH_PSR_ASCMode_TFF_Pos 8 /*!< USIC_CH PSR_ASCMode: TFF Position */
\r
2377 #define USIC_CH_PSR_ASCMode_TFF_Msk (0x01UL << USIC_CH_PSR_ASCMode_TFF_Pos) /*!< USIC_CH PSR_ASCMode: TFF Mask */
\r
2378 #define USIC_CH_PSR_ASCMode_BUSY_Pos 9 /*!< USIC_CH PSR_ASCMode: BUSY Position */
\r
2379 #define USIC_CH_PSR_ASCMode_BUSY_Msk (0x01UL << USIC_CH_PSR_ASCMode_BUSY_Pos) /*!< USIC_CH PSR_ASCMode: BUSY Mask */
\r
2380 #define USIC_CH_PSR_ASCMode_RSIF_Pos 10 /*!< USIC_CH PSR_ASCMode: RSIF Position */
\r
2381 #define USIC_CH_PSR_ASCMode_RSIF_Msk (0x01UL << USIC_CH_PSR_ASCMode_RSIF_Pos) /*!< USIC_CH PSR_ASCMode: RSIF Mask */
\r
2382 #define USIC_CH_PSR_ASCMode_DLIF_Pos 11 /*!< USIC_CH PSR_ASCMode: DLIF Position */
\r
2383 #define USIC_CH_PSR_ASCMode_DLIF_Msk (0x01UL << USIC_CH_PSR_ASCMode_DLIF_Pos) /*!< USIC_CH PSR_ASCMode: DLIF Mask */
\r
2384 #define USIC_CH_PSR_ASCMode_TSIF_Pos 12 /*!< USIC_CH PSR_ASCMode: TSIF Position */
\r
2385 #define USIC_CH_PSR_ASCMode_TSIF_Msk (0x01UL << USIC_CH_PSR_ASCMode_TSIF_Pos) /*!< USIC_CH PSR_ASCMode: TSIF Mask */
\r
2386 #define USIC_CH_PSR_ASCMode_TBIF_Pos 13 /*!< USIC_CH PSR_ASCMode: TBIF Position */
\r
2387 #define USIC_CH_PSR_ASCMode_TBIF_Msk (0x01UL << USIC_CH_PSR_ASCMode_TBIF_Pos) /*!< USIC_CH PSR_ASCMode: TBIF Mask */
\r
2388 #define USIC_CH_PSR_ASCMode_RIF_Pos 14 /*!< USIC_CH PSR_ASCMode: RIF Position */
\r
2389 #define USIC_CH_PSR_ASCMode_RIF_Msk (0x01UL << USIC_CH_PSR_ASCMode_RIF_Pos) /*!< USIC_CH PSR_ASCMode: RIF Mask */
\r
2390 #define USIC_CH_PSR_ASCMode_AIF_Pos 15 /*!< USIC_CH PSR_ASCMode: AIF Position */
\r
2391 #define USIC_CH_PSR_ASCMode_AIF_Msk (0x01UL << USIC_CH_PSR_ASCMode_AIF_Pos) /*!< USIC_CH PSR_ASCMode: AIF Mask */
\r
2392 #define USIC_CH_PSR_ASCMode_BRGIF_Pos 16 /*!< USIC_CH PSR_ASCMode: BRGIF Position */
\r
2393 #define USIC_CH_PSR_ASCMode_BRGIF_Msk (0x01UL << USIC_CH_PSR_ASCMode_BRGIF_Pos) /*!< USIC_CH PSR_ASCMode: BRGIF Mask */
\r
2395 /* ----------------------------- USIC_CH_PSR_SSCMode ---------------------------- */
\r
2396 #define USIC_CH_PSR_SSCMode_MSLS_Pos 0 /*!< USIC_CH PSR_SSCMode: MSLS Position */
\r
2397 #define USIC_CH_PSR_SSCMode_MSLS_Msk (0x01UL << USIC_CH_PSR_SSCMode_MSLS_Pos) /*!< USIC_CH PSR_SSCMode: MSLS Mask */
\r
2398 #define USIC_CH_PSR_SSCMode_DX2S_Pos 1 /*!< USIC_CH PSR_SSCMode: DX2S Position */
\r
2399 #define USIC_CH_PSR_SSCMode_DX2S_Msk (0x01UL << USIC_CH_PSR_SSCMode_DX2S_Pos) /*!< USIC_CH PSR_SSCMode: DX2S Mask */
\r
2400 #define USIC_CH_PSR_SSCMode_MSLSEV_Pos 2 /*!< USIC_CH PSR_SSCMode: MSLSEV Position */
\r
2401 #define USIC_CH_PSR_SSCMode_MSLSEV_Msk (0x01UL << USIC_CH_PSR_SSCMode_MSLSEV_Pos) /*!< USIC_CH PSR_SSCMode: MSLSEV Mask */
\r
2402 #define USIC_CH_PSR_SSCMode_DX2TEV_Pos 3 /*!< USIC_CH PSR_SSCMode: DX2TEV Position */
\r
2403 #define USIC_CH_PSR_SSCMode_DX2TEV_Msk (0x01UL << USIC_CH_PSR_SSCMode_DX2TEV_Pos) /*!< USIC_CH PSR_SSCMode: DX2TEV Mask */
\r
2404 #define USIC_CH_PSR_SSCMode_PARERR_Pos 4 /*!< USIC_CH PSR_SSCMode: PARERR Position */
\r
2405 #define USIC_CH_PSR_SSCMode_PARERR_Msk (0x01UL << USIC_CH_PSR_SSCMode_PARERR_Pos) /*!< USIC_CH PSR_SSCMode: PARERR Mask */
\r
2406 #define USIC_CH_PSR_SSCMode_RSIF_Pos 10 /*!< USIC_CH PSR_SSCMode: RSIF Position */
\r
2407 #define USIC_CH_PSR_SSCMode_RSIF_Msk (0x01UL << USIC_CH_PSR_SSCMode_RSIF_Pos) /*!< USIC_CH PSR_SSCMode: RSIF Mask */
\r
2408 #define USIC_CH_PSR_SSCMode_DLIF_Pos 11 /*!< USIC_CH PSR_SSCMode: DLIF Position */
\r
2409 #define USIC_CH_PSR_SSCMode_DLIF_Msk (0x01UL << USIC_CH_PSR_SSCMode_DLIF_Pos) /*!< USIC_CH PSR_SSCMode: DLIF Mask */
\r
2410 #define USIC_CH_PSR_SSCMode_TSIF_Pos 12 /*!< USIC_CH PSR_SSCMode: TSIF Position */
\r
2411 #define USIC_CH_PSR_SSCMode_TSIF_Msk (0x01UL << USIC_CH_PSR_SSCMode_TSIF_Pos) /*!< USIC_CH PSR_SSCMode: TSIF Mask */
\r
2412 #define USIC_CH_PSR_SSCMode_TBIF_Pos 13 /*!< USIC_CH PSR_SSCMode: TBIF Position */
\r
2413 #define USIC_CH_PSR_SSCMode_TBIF_Msk (0x01UL << USIC_CH_PSR_SSCMode_TBIF_Pos) /*!< USIC_CH PSR_SSCMode: TBIF Mask */
\r
2414 #define USIC_CH_PSR_SSCMode_RIF_Pos 14 /*!< USIC_CH PSR_SSCMode: RIF Position */
\r
2415 #define USIC_CH_PSR_SSCMode_RIF_Msk (0x01UL << USIC_CH_PSR_SSCMode_RIF_Pos) /*!< USIC_CH PSR_SSCMode: RIF Mask */
\r
2416 #define USIC_CH_PSR_SSCMode_AIF_Pos 15 /*!< USIC_CH PSR_SSCMode: AIF Position */
\r
2417 #define USIC_CH_PSR_SSCMode_AIF_Msk (0x01UL << USIC_CH_PSR_SSCMode_AIF_Pos) /*!< USIC_CH PSR_SSCMode: AIF Mask */
\r
2418 #define USIC_CH_PSR_SSCMode_BRGIF_Pos 16 /*!< USIC_CH PSR_SSCMode: BRGIF Position */
\r
2419 #define USIC_CH_PSR_SSCMode_BRGIF_Msk (0x01UL << USIC_CH_PSR_SSCMode_BRGIF_Pos) /*!< USIC_CH PSR_SSCMode: BRGIF Mask */
\r
2421 /* ----------------------------- USIC_CH_PSR_IICMode ---------------------------- */
\r
2422 #define USIC_CH_PSR_IICMode_SLSEL_Pos 0 /*!< USIC_CH PSR_IICMode: SLSEL Position */
\r
2423 #define USIC_CH_PSR_IICMode_SLSEL_Msk (0x01UL << USIC_CH_PSR_IICMode_SLSEL_Pos) /*!< USIC_CH PSR_IICMode: SLSEL Mask */
\r
2424 #define USIC_CH_PSR_IICMode_WTDF_Pos 1 /*!< USIC_CH PSR_IICMode: WTDF Position */
\r
2425 #define USIC_CH_PSR_IICMode_WTDF_Msk (0x01UL << USIC_CH_PSR_IICMode_WTDF_Pos) /*!< USIC_CH PSR_IICMode: WTDF Mask */
\r
2426 #define USIC_CH_PSR_IICMode_SCR_Pos 2 /*!< USIC_CH PSR_IICMode: SCR Position */
\r
2427 #define USIC_CH_PSR_IICMode_SCR_Msk (0x01UL << USIC_CH_PSR_IICMode_SCR_Pos) /*!< USIC_CH PSR_IICMode: SCR Mask */
\r
2428 #define USIC_CH_PSR_IICMode_RSCR_Pos 3 /*!< USIC_CH PSR_IICMode: RSCR Position */
\r
2429 #define USIC_CH_PSR_IICMode_RSCR_Msk (0x01UL << USIC_CH_PSR_IICMode_RSCR_Pos) /*!< USIC_CH PSR_IICMode: RSCR Mask */
\r
2430 #define USIC_CH_PSR_IICMode_PCR_Pos 4 /*!< USIC_CH PSR_IICMode: PCR Position */
\r
2431 #define USIC_CH_PSR_IICMode_PCR_Msk (0x01UL << USIC_CH_PSR_IICMode_PCR_Pos) /*!< USIC_CH PSR_IICMode: PCR Mask */
\r
2432 #define USIC_CH_PSR_IICMode_NACK_Pos 5 /*!< USIC_CH PSR_IICMode: NACK Position */
\r
2433 #define USIC_CH_PSR_IICMode_NACK_Msk (0x01UL << USIC_CH_PSR_IICMode_NACK_Pos) /*!< USIC_CH PSR_IICMode: NACK Mask */
\r
2434 #define USIC_CH_PSR_IICMode_ARL_Pos 6 /*!< USIC_CH PSR_IICMode: ARL Position */
\r
2435 #define USIC_CH_PSR_IICMode_ARL_Msk (0x01UL << USIC_CH_PSR_IICMode_ARL_Pos) /*!< USIC_CH PSR_IICMode: ARL Mask */
\r
2436 #define USIC_CH_PSR_IICMode_SRR_Pos 7 /*!< USIC_CH PSR_IICMode: SRR Position */
\r
2437 #define USIC_CH_PSR_IICMode_SRR_Msk (0x01UL << USIC_CH_PSR_IICMode_SRR_Pos) /*!< USIC_CH PSR_IICMode: SRR Mask */
\r
2438 #define USIC_CH_PSR_IICMode_ERR_Pos 8 /*!< USIC_CH PSR_IICMode: ERR Position */
\r
2439 #define USIC_CH_PSR_IICMode_ERR_Msk (0x01UL << USIC_CH_PSR_IICMode_ERR_Pos) /*!< USIC_CH PSR_IICMode: ERR Mask */
\r
2440 #define USIC_CH_PSR_IICMode_ACK_Pos 9 /*!< USIC_CH PSR_IICMode: ACK Position */
\r
2441 #define USIC_CH_PSR_IICMode_ACK_Msk (0x01UL << USIC_CH_PSR_IICMode_ACK_Pos) /*!< USIC_CH PSR_IICMode: ACK Mask */
\r
2442 #define USIC_CH_PSR_IICMode_RSIF_Pos 10 /*!< USIC_CH PSR_IICMode: RSIF Position */
\r
2443 #define USIC_CH_PSR_IICMode_RSIF_Msk (0x01UL << USIC_CH_PSR_IICMode_RSIF_Pos) /*!< USIC_CH PSR_IICMode: RSIF Mask */
\r
2444 #define USIC_CH_PSR_IICMode_DLIF_Pos 11 /*!< USIC_CH PSR_IICMode: DLIF Position */
\r
2445 #define USIC_CH_PSR_IICMode_DLIF_Msk (0x01UL << USIC_CH_PSR_IICMode_DLIF_Pos) /*!< USIC_CH PSR_IICMode: DLIF Mask */
\r
2446 #define USIC_CH_PSR_IICMode_TSIF_Pos 12 /*!< USIC_CH PSR_IICMode: TSIF Position */
\r
2447 #define USIC_CH_PSR_IICMode_TSIF_Msk (0x01UL << USIC_CH_PSR_IICMode_TSIF_Pos) /*!< USIC_CH PSR_IICMode: TSIF Mask */
\r
2448 #define USIC_CH_PSR_IICMode_TBIF_Pos 13 /*!< USIC_CH PSR_IICMode: TBIF Position */
\r
2449 #define USIC_CH_PSR_IICMode_TBIF_Msk (0x01UL << USIC_CH_PSR_IICMode_TBIF_Pos) /*!< USIC_CH PSR_IICMode: TBIF Mask */
\r
2450 #define USIC_CH_PSR_IICMode_RIF_Pos 14 /*!< USIC_CH PSR_IICMode: RIF Position */
\r
2451 #define USIC_CH_PSR_IICMode_RIF_Msk (0x01UL << USIC_CH_PSR_IICMode_RIF_Pos) /*!< USIC_CH PSR_IICMode: RIF Mask */
\r
2452 #define USIC_CH_PSR_IICMode_AIF_Pos 15 /*!< USIC_CH PSR_IICMode: AIF Position */
\r
2453 #define USIC_CH_PSR_IICMode_AIF_Msk (0x01UL << USIC_CH_PSR_IICMode_AIF_Pos) /*!< USIC_CH PSR_IICMode: AIF Mask */
\r
2454 #define USIC_CH_PSR_IICMode_BRGIF_Pos 16 /*!< USIC_CH PSR_IICMode: BRGIF Position */
\r
2455 #define USIC_CH_PSR_IICMode_BRGIF_Msk (0x01UL << USIC_CH_PSR_IICMode_BRGIF_Pos) /*!< USIC_CH PSR_IICMode: BRGIF Mask */
\r
2457 /* ----------------------------- USIC_CH_PSR_IISMode ---------------------------- */
\r
2458 #define USIC_CH_PSR_IISMode_WA_Pos 0 /*!< USIC_CH PSR_IISMode: WA Position */
\r
2459 #define USIC_CH_PSR_IISMode_WA_Msk (0x01UL << USIC_CH_PSR_IISMode_WA_Pos) /*!< USIC_CH PSR_IISMode: WA Mask */
\r
2460 #define USIC_CH_PSR_IISMode_DX2S_Pos 1 /*!< USIC_CH PSR_IISMode: DX2S Position */
\r
2461 #define USIC_CH_PSR_IISMode_DX2S_Msk (0x01UL << USIC_CH_PSR_IISMode_DX2S_Pos) /*!< USIC_CH PSR_IISMode: DX2S Mask */
\r
2462 #define USIC_CH_PSR_IISMode_DX2TEV_Pos 3 /*!< USIC_CH PSR_IISMode: DX2TEV Position */
\r
2463 #define USIC_CH_PSR_IISMode_DX2TEV_Msk (0x01UL << USIC_CH_PSR_IISMode_DX2TEV_Pos) /*!< USIC_CH PSR_IISMode: DX2TEV Mask */
\r
2464 #define USIC_CH_PSR_IISMode_WAFE_Pos 4 /*!< USIC_CH PSR_IISMode: WAFE Position */
\r
2465 #define USIC_CH_PSR_IISMode_WAFE_Msk (0x01UL << USIC_CH_PSR_IISMode_WAFE_Pos) /*!< USIC_CH PSR_IISMode: WAFE Mask */
\r
2466 #define USIC_CH_PSR_IISMode_WARE_Pos 5 /*!< USIC_CH PSR_IISMode: WARE Position */
\r
2467 #define USIC_CH_PSR_IISMode_WARE_Msk (0x01UL << USIC_CH_PSR_IISMode_WARE_Pos) /*!< USIC_CH PSR_IISMode: WARE Mask */
\r
2468 #define USIC_CH_PSR_IISMode_END_Pos 6 /*!< USIC_CH PSR_IISMode: END Position */
\r
2469 #define USIC_CH_PSR_IISMode_END_Msk (0x01UL << USIC_CH_PSR_IISMode_END_Pos) /*!< USIC_CH PSR_IISMode: END Mask */
\r
2470 #define USIC_CH_PSR_IISMode_RSIF_Pos 10 /*!< USIC_CH PSR_IISMode: RSIF Position */
\r
2471 #define USIC_CH_PSR_IISMode_RSIF_Msk (0x01UL << USIC_CH_PSR_IISMode_RSIF_Pos) /*!< USIC_CH PSR_IISMode: RSIF Mask */
\r
2472 #define USIC_CH_PSR_IISMode_DLIF_Pos 11 /*!< USIC_CH PSR_IISMode: DLIF Position */
\r
2473 #define USIC_CH_PSR_IISMode_DLIF_Msk (0x01UL << USIC_CH_PSR_IISMode_DLIF_Pos) /*!< USIC_CH PSR_IISMode: DLIF Mask */
\r
2474 #define USIC_CH_PSR_IISMode_TSIF_Pos 12 /*!< USIC_CH PSR_IISMode: TSIF Position */
\r
2475 #define USIC_CH_PSR_IISMode_TSIF_Msk (0x01UL << USIC_CH_PSR_IISMode_TSIF_Pos) /*!< USIC_CH PSR_IISMode: TSIF Mask */
\r
2476 #define USIC_CH_PSR_IISMode_TBIF_Pos 13 /*!< USIC_CH PSR_IISMode: TBIF Position */
\r
2477 #define USIC_CH_PSR_IISMode_TBIF_Msk (0x01UL << USIC_CH_PSR_IISMode_TBIF_Pos) /*!< USIC_CH PSR_IISMode: TBIF Mask */
\r
2478 #define USIC_CH_PSR_IISMode_RIF_Pos 14 /*!< USIC_CH PSR_IISMode: RIF Position */
\r
2479 #define USIC_CH_PSR_IISMode_RIF_Msk (0x01UL << USIC_CH_PSR_IISMode_RIF_Pos) /*!< USIC_CH PSR_IISMode: RIF Mask */
\r
2480 #define USIC_CH_PSR_IISMode_AIF_Pos 15 /*!< USIC_CH PSR_IISMode: AIF Position */
\r
2481 #define USIC_CH_PSR_IISMode_AIF_Msk (0x01UL << USIC_CH_PSR_IISMode_AIF_Pos) /*!< USIC_CH PSR_IISMode: AIF Mask */
\r
2482 #define USIC_CH_PSR_IISMode_BRGIF_Pos 16 /*!< USIC_CH PSR_IISMode: BRGIF Position */
\r
2483 #define USIC_CH_PSR_IISMode_BRGIF_Msk (0x01UL << USIC_CH_PSR_IISMode_BRGIF_Pos) /*!< USIC_CH PSR_IISMode: BRGIF Mask */
\r
2485 /* -------------------------------- USIC_CH_PSCR -------------------------------- */
\r
2486 #define USIC_CH_PSCR_CST0_Pos 0 /*!< USIC_CH PSCR: CST0 Position */
\r
2487 #define USIC_CH_PSCR_CST0_Msk (0x01UL << USIC_CH_PSCR_CST0_Pos) /*!< USIC_CH PSCR: CST0 Mask */
\r
2488 #define USIC_CH_PSCR_CST1_Pos 1 /*!< USIC_CH PSCR: CST1 Position */
\r
2489 #define USIC_CH_PSCR_CST1_Msk (0x01UL << USIC_CH_PSCR_CST1_Pos) /*!< USIC_CH PSCR: CST1 Mask */
\r
2490 #define USIC_CH_PSCR_CST2_Pos 2 /*!< USIC_CH PSCR: CST2 Position */
\r
2491 #define USIC_CH_PSCR_CST2_Msk (0x01UL << USIC_CH_PSCR_CST2_Pos) /*!< USIC_CH PSCR: CST2 Mask */
\r
2492 #define USIC_CH_PSCR_CST3_Pos 3 /*!< USIC_CH PSCR: CST3 Position */
\r
2493 #define USIC_CH_PSCR_CST3_Msk (0x01UL << USIC_CH_PSCR_CST3_Pos) /*!< USIC_CH PSCR: CST3 Mask */
\r
2494 #define USIC_CH_PSCR_CST4_Pos 4 /*!< USIC_CH PSCR: CST4 Position */
\r
2495 #define USIC_CH_PSCR_CST4_Msk (0x01UL << USIC_CH_PSCR_CST4_Pos) /*!< USIC_CH PSCR: CST4 Mask */
\r
2496 #define USIC_CH_PSCR_CST5_Pos 5 /*!< USIC_CH PSCR: CST5 Position */
\r
2497 #define USIC_CH_PSCR_CST5_Msk (0x01UL << USIC_CH_PSCR_CST5_Pos) /*!< USIC_CH PSCR: CST5 Mask */
\r
2498 #define USIC_CH_PSCR_CST6_Pos 6 /*!< USIC_CH PSCR: CST6 Position */
\r
2499 #define USIC_CH_PSCR_CST6_Msk (0x01UL << USIC_CH_PSCR_CST6_Pos) /*!< USIC_CH PSCR: CST6 Mask */
\r
2500 #define USIC_CH_PSCR_CST7_Pos 7 /*!< USIC_CH PSCR: CST7 Position */
\r
2501 #define USIC_CH_PSCR_CST7_Msk (0x01UL << USIC_CH_PSCR_CST7_Pos) /*!< USIC_CH PSCR: CST7 Mask */
\r
2502 #define USIC_CH_PSCR_CST8_Pos 8 /*!< USIC_CH PSCR: CST8 Position */
\r
2503 #define USIC_CH_PSCR_CST8_Msk (0x01UL << USIC_CH_PSCR_CST8_Pos) /*!< USIC_CH PSCR: CST8 Mask */
\r
2504 #define USIC_CH_PSCR_CST9_Pos 9 /*!< USIC_CH PSCR: CST9 Position */
\r
2505 #define USIC_CH_PSCR_CST9_Msk (0x01UL << USIC_CH_PSCR_CST9_Pos) /*!< USIC_CH PSCR: CST9 Mask */
\r
2506 #define USIC_CH_PSCR_CRSIF_Pos 10 /*!< USIC_CH PSCR: CRSIF Position */
\r
2507 #define USIC_CH_PSCR_CRSIF_Msk (0x01UL << USIC_CH_PSCR_CRSIF_Pos) /*!< USIC_CH PSCR: CRSIF Mask */
\r
2508 #define USIC_CH_PSCR_CDLIF_Pos 11 /*!< USIC_CH PSCR: CDLIF Position */
\r
2509 #define USIC_CH_PSCR_CDLIF_Msk (0x01UL << USIC_CH_PSCR_CDLIF_Pos) /*!< USIC_CH PSCR: CDLIF Mask */
\r
2510 #define USIC_CH_PSCR_CTSIF_Pos 12 /*!< USIC_CH PSCR: CTSIF Position */
\r
2511 #define USIC_CH_PSCR_CTSIF_Msk (0x01UL << USIC_CH_PSCR_CTSIF_Pos) /*!< USIC_CH PSCR: CTSIF Mask */
\r
2512 #define USIC_CH_PSCR_CTBIF_Pos 13 /*!< USIC_CH PSCR: CTBIF Position */
\r
2513 #define USIC_CH_PSCR_CTBIF_Msk (0x01UL << USIC_CH_PSCR_CTBIF_Pos) /*!< USIC_CH PSCR: CTBIF Mask */
\r
2514 #define USIC_CH_PSCR_CRIF_Pos 14 /*!< USIC_CH PSCR: CRIF Position */
\r
2515 #define USIC_CH_PSCR_CRIF_Msk (0x01UL << USIC_CH_PSCR_CRIF_Pos) /*!< USIC_CH PSCR: CRIF Mask */
\r
2516 #define USIC_CH_PSCR_CAIF_Pos 15 /*!< USIC_CH PSCR: CAIF Position */
\r
2517 #define USIC_CH_PSCR_CAIF_Msk (0x01UL << USIC_CH_PSCR_CAIF_Pos) /*!< USIC_CH PSCR: CAIF Mask */
\r
2518 #define USIC_CH_PSCR_CBRGIF_Pos 16 /*!< USIC_CH PSCR: CBRGIF Position */
\r
2519 #define USIC_CH_PSCR_CBRGIF_Msk (0x01UL << USIC_CH_PSCR_CBRGIF_Pos) /*!< USIC_CH PSCR: CBRGIF Mask */
\r
2521 /* ------------------------------- USIC_CH_RBUFSR ------------------------------- */
\r
2522 #define USIC_CH_RBUFSR_WLEN_Pos 0 /*!< USIC_CH RBUFSR: WLEN Position */
\r
2523 #define USIC_CH_RBUFSR_WLEN_Msk (0x0fUL << USIC_CH_RBUFSR_WLEN_Pos) /*!< USIC_CH RBUFSR: WLEN Mask */
\r
2524 #define USIC_CH_RBUFSR_SOF_Pos 6 /*!< USIC_CH RBUFSR: SOF Position */
\r
2525 #define USIC_CH_RBUFSR_SOF_Msk (0x01UL << USIC_CH_RBUFSR_SOF_Pos) /*!< USIC_CH RBUFSR: SOF Mask */
\r
2526 #define USIC_CH_RBUFSR_PAR_Pos 8 /*!< USIC_CH RBUFSR: PAR Position */
\r
2527 #define USIC_CH_RBUFSR_PAR_Msk (0x01UL << USIC_CH_RBUFSR_PAR_Pos) /*!< USIC_CH RBUFSR: PAR Mask */
\r
2528 #define USIC_CH_RBUFSR_PERR_Pos 9 /*!< USIC_CH RBUFSR: PERR Position */
\r
2529 #define USIC_CH_RBUFSR_PERR_Msk (0x01UL << USIC_CH_RBUFSR_PERR_Pos) /*!< USIC_CH RBUFSR: PERR Mask */
\r
2530 #define USIC_CH_RBUFSR_RDV0_Pos 13 /*!< USIC_CH RBUFSR: RDV0 Position */
\r
2531 #define USIC_CH_RBUFSR_RDV0_Msk (0x01UL << USIC_CH_RBUFSR_RDV0_Pos) /*!< USIC_CH RBUFSR: RDV0 Mask */
\r
2532 #define USIC_CH_RBUFSR_RDV1_Pos 14 /*!< USIC_CH RBUFSR: RDV1 Position */
\r
2533 #define USIC_CH_RBUFSR_RDV1_Msk (0x01UL << USIC_CH_RBUFSR_RDV1_Pos) /*!< USIC_CH RBUFSR: RDV1 Mask */
\r
2534 #define USIC_CH_RBUFSR_DS_Pos 15 /*!< USIC_CH RBUFSR: DS Position */
\r
2535 #define USIC_CH_RBUFSR_DS_Msk (0x01UL << USIC_CH_RBUFSR_DS_Pos) /*!< USIC_CH RBUFSR: DS Mask */
\r
2537 /* -------------------------------- USIC_CH_RBUF -------------------------------- */
\r
2538 #define USIC_CH_RBUF_DSR_Pos 0 /*!< USIC_CH RBUF: DSR Position */
\r
2539 #define USIC_CH_RBUF_DSR_Msk (0x0000ffffUL << USIC_CH_RBUF_DSR_Pos) /*!< USIC_CH RBUF: DSR Mask */
\r
2541 /* -------------------------------- USIC_CH_RBUFD ------------------------------- */
\r
2542 #define USIC_CH_RBUFD_DSR_Pos 0 /*!< USIC_CH RBUFD: DSR Position */
\r
2543 #define USIC_CH_RBUFD_DSR_Msk (0x0000ffffUL << USIC_CH_RBUFD_DSR_Pos) /*!< USIC_CH RBUFD: DSR Mask */
\r
2545 /* -------------------------------- USIC_CH_RBUF0 ------------------------------- */
\r
2546 #define USIC_CH_RBUF0_DSR0_Pos 0 /*!< USIC_CH RBUF0: DSR0 Position */
\r
2547 #define USIC_CH_RBUF0_DSR0_Msk (0x0000ffffUL << USIC_CH_RBUF0_DSR0_Pos) /*!< USIC_CH RBUF0: DSR0 Mask */
\r
2549 /* -------------------------------- USIC_CH_RBUF1 ------------------------------- */
\r
2550 #define USIC_CH_RBUF1_DSR1_Pos 0 /*!< USIC_CH RBUF1: DSR1 Position */
\r
2551 #define USIC_CH_RBUF1_DSR1_Msk (0x0000ffffUL << USIC_CH_RBUF1_DSR1_Pos) /*!< USIC_CH RBUF1: DSR1 Mask */
\r
2553 /* ------------------------------ USIC_CH_RBUF01SR ------------------------------ */
\r
2554 #define USIC_CH_RBUF01SR_WLEN0_Pos 0 /*!< USIC_CH RBUF01SR: WLEN0 Position */
\r
2555 #define USIC_CH_RBUF01SR_WLEN0_Msk (0x0fUL << USIC_CH_RBUF01SR_WLEN0_Pos) /*!< USIC_CH RBUF01SR: WLEN0 Mask */
\r
2556 #define USIC_CH_RBUF01SR_SOF0_Pos 6 /*!< USIC_CH RBUF01SR: SOF0 Position */
\r
2557 #define USIC_CH_RBUF01SR_SOF0_Msk (0x01UL << USIC_CH_RBUF01SR_SOF0_Pos) /*!< USIC_CH RBUF01SR: SOF0 Mask */
\r
2558 #define USIC_CH_RBUF01SR_PAR0_Pos 8 /*!< USIC_CH RBUF01SR: PAR0 Position */
\r
2559 #define USIC_CH_RBUF01SR_PAR0_Msk (0x01UL << USIC_CH_RBUF01SR_PAR0_Pos) /*!< USIC_CH RBUF01SR: PAR0 Mask */
\r
2560 #define USIC_CH_RBUF01SR_PERR0_Pos 9 /*!< USIC_CH RBUF01SR: PERR0 Position */
\r
2561 #define USIC_CH_RBUF01SR_PERR0_Msk (0x01UL << USIC_CH_RBUF01SR_PERR0_Pos) /*!< USIC_CH RBUF01SR: PERR0 Mask */
\r
2562 #define USIC_CH_RBUF01SR_RDV00_Pos 13 /*!< USIC_CH RBUF01SR: RDV00 Position */
\r
2563 #define USIC_CH_RBUF01SR_RDV00_Msk (0x01UL << USIC_CH_RBUF01SR_RDV00_Pos) /*!< USIC_CH RBUF01SR: RDV00 Mask */
\r
2564 #define USIC_CH_RBUF01SR_RDV01_Pos 14 /*!< USIC_CH RBUF01SR: RDV01 Position */
\r
2565 #define USIC_CH_RBUF01SR_RDV01_Msk (0x01UL << USIC_CH_RBUF01SR_RDV01_Pos) /*!< USIC_CH RBUF01SR: RDV01 Mask */
\r
2566 #define USIC_CH_RBUF01SR_DS0_Pos 15 /*!< USIC_CH RBUF01SR: DS0 Position */
\r
2567 #define USIC_CH_RBUF01SR_DS0_Msk (0x01UL << USIC_CH_RBUF01SR_DS0_Pos) /*!< USIC_CH RBUF01SR: DS0 Mask */
\r
2568 #define USIC_CH_RBUF01SR_WLEN1_Pos 16 /*!< USIC_CH RBUF01SR: WLEN1 Position */
\r
2569 #define USIC_CH_RBUF01SR_WLEN1_Msk (0x0fUL << USIC_CH_RBUF01SR_WLEN1_Pos) /*!< USIC_CH RBUF01SR: WLEN1 Mask */
\r
2570 #define USIC_CH_RBUF01SR_SOF1_Pos 22 /*!< USIC_CH RBUF01SR: SOF1 Position */
\r
2571 #define USIC_CH_RBUF01SR_SOF1_Msk (0x01UL << USIC_CH_RBUF01SR_SOF1_Pos) /*!< USIC_CH RBUF01SR: SOF1 Mask */
\r
2572 #define USIC_CH_RBUF01SR_PAR1_Pos 24 /*!< USIC_CH RBUF01SR: PAR1 Position */
\r
2573 #define USIC_CH_RBUF01SR_PAR1_Msk (0x01UL << USIC_CH_RBUF01SR_PAR1_Pos) /*!< USIC_CH RBUF01SR: PAR1 Mask */
\r
2574 #define USIC_CH_RBUF01SR_PERR1_Pos 25 /*!< USIC_CH RBUF01SR: PERR1 Position */
\r
2575 #define USIC_CH_RBUF01SR_PERR1_Msk (0x01UL << USIC_CH_RBUF01SR_PERR1_Pos) /*!< USIC_CH RBUF01SR: PERR1 Mask */
\r
2576 #define USIC_CH_RBUF01SR_RDV10_Pos 29 /*!< USIC_CH RBUF01SR: RDV10 Position */
\r
2577 #define USIC_CH_RBUF01SR_RDV10_Msk (0x01UL << USIC_CH_RBUF01SR_RDV10_Pos) /*!< USIC_CH RBUF01SR: RDV10 Mask */
\r
2578 #define USIC_CH_RBUF01SR_RDV11_Pos 30 /*!< USIC_CH RBUF01SR: RDV11 Position */
\r
2579 #define USIC_CH_RBUF01SR_RDV11_Msk (0x01UL << USIC_CH_RBUF01SR_RDV11_Pos) /*!< USIC_CH RBUF01SR: RDV11 Mask */
\r
2580 #define USIC_CH_RBUF01SR_DS1_Pos 31 /*!< USIC_CH RBUF01SR: DS1 Position */
\r
2581 #define USIC_CH_RBUF01SR_DS1_Msk (0x01UL << USIC_CH_RBUF01SR_DS1_Pos) /*!< USIC_CH RBUF01SR: DS1 Mask */
\r
2583 /* --------------------------------- USIC_CH_FMR -------------------------------- */
\r
2584 #define USIC_CH_FMR_MTDV_Pos 0 /*!< USIC_CH FMR: MTDV Position */
\r
2585 #define USIC_CH_FMR_MTDV_Msk (0x03UL << USIC_CH_FMR_MTDV_Pos) /*!< USIC_CH FMR: MTDV Mask */
\r
2586 #define USIC_CH_FMR_ATVC_Pos 4 /*!< USIC_CH FMR: ATVC Position */
\r
2587 #define USIC_CH_FMR_ATVC_Msk (0x01UL << USIC_CH_FMR_ATVC_Pos) /*!< USIC_CH FMR: ATVC Mask */
\r
2588 #define USIC_CH_FMR_CRDV0_Pos 14 /*!< USIC_CH FMR: CRDV0 Position */
\r
2589 #define USIC_CH_FMR_CRDV0_Msk (0x01UL << USIC_CH_FMR_CRDV0_Pos) /*!< USIC_CH FMR: CRDV0 Mask */
\r
2590 #define USIC_CH_FMR_CRDV1_Pos 15 /*!< USIC_CH FMR: CRDV1 Position */
\r
2591 #define USIC_CH_FMR_CRDV1_Msk (0x01UL << USIC_CH_FMR_CRDV1_Pos) /*!< USIC_CH FMR: CRDV1 Mask */
\r
2592 #define USIC_CH_FMR_SIO0_Pos 16 /*!< USIC_CH FMR: SIO0 Position */
\r
2593 #define USIC_CH_FMR_SIO0_Msk (0x01UL << USIC_CH_FMR_SIO0_Pos) /*!< USIC_CH FMR: SIO0 Mask */
\r
2594 #define USIC_CH_FMR_SIO1_Pos 17 /*!< USIC_CH FMR: SIO1 Position */
\r
2595 #define USIC_CH_FMR_SIO1_Msk (0x01UL << USIC_CH_FMR_SIO1_Pos) /*!< USIC_CH FMR: SIO1 Mask */
\r
2596 #define USIC_CH_FMR_SIO2_Pos 18 /*!< USIC_CH FMR: SIO2 Position */
\r
2597 #define USIC_CH_FMR_SIO2_Msk (0x01UL << USIC_CH_FMR_SIO2_Pos) /*!< USIC_CH FMR: SIO2 Mask */
\r
2598 #define USIC_CH_FMR_SIO3_Pos 19 /*!< USIC_CH FMR: SIO3 Position */
\r
2599 #define USIC_CH_FMR_SIO3_Msk (0x01UL << USIC_CH_FMR_SIO3_Pos) /*!< USIC_CH FMR: SIO3 Mask */
\r
2600 #define USIC_CH_FMR_SIO4_Pos 20 /*!< USIC_CH FMR: SIO4 Position */
\r
2601 #define USIC_CH_FMR_SIO4_Msk (0x01UL << USIC_CH_FMR_SIO4_Pos) /*!< USIC_CH FMR: SIO4 Mask */
\r
2602 #define USIC_CH_FMR_SIO5_Pos 21 /*!< USIC_CH FMR: SIO5 Position */
\r
2603 #define USIC_CH_FMR_SIO5_Msk (0x01UL << USIC_CH_FMR_SIO5_Pos) /*!< USIC_CH FMR: SIO5 Mask */
\r
2605 /* -------------------------------- USIC_CH_TBUF -------------------------------- */
\r
2606 #define USIC_CH_TBUF_TDATA_Pos 0 /*!< USIC_CH TBUF: TDATA Position */
\r
2607 #define USIC_CH_TBUF_TDATA_Msk (0x0000ffffUL << USIC_CH_TBUF_TDATA_Pos) /*!< USIC_CH TBUF: TDATA Mask */
\r
2609 /* --------------------------------- USIC_CH_BYP -------------------------------- */
\r
2610 #define USIC_CH_BYP_BDATA_Pos 0 /*!< USIC_CH BYP: BDATA Position */
\r
2611 #define USIC_CH_BYP_BDATA_Msk (0x0000ffffUL << USIC_CH_BYP_BDATA_Pos) /*!< USIC_CH BYP: BDATA Mask */
\r
2613 /* -------------------------------- USIC_CH_BYPCR ------------------------------- */
\r
2614 #define USIC_CH_BYPCR_BWLE_Pos 0 /*!< USIC_CH BYPCR: BWLE Position */
\r
2615 #define USIC_CH_BYPCR_BWLE_Msk (0x0fUL << USIC_CH_BYPCR_BWLE_Pos) /*!< USIC_CH BYPCR: BWLE Mask */
\r
2616 #define USIC_CH_BYPCR_BDSSM_Pos 8 /*!< USIC_CH BYPCR: BDSSM Position */
\r
2617 #define USIC_CH_BYPCR_BDSSM_Msk (0x01UL << USIC_CH_BYPCR_BDSSM_Pos) /*!< USIC_CH BYPCR: BDSSM Mask */
\r
2618 #define USIC_CH_BYPCR_BDEN_Pos 10 /*!< USIC_CH BYPCR: BDEN Position */
\r
2619 #define USIC_CH_BYPCR_BDEN_Msk (0x03UL << USIC_CH_BYPCR_BDEN_Pos) /*!< USIC_CH BYPCR: BDEN Mask */
\r
2620 #define USIC_CH_BYPCR_BDVTR_Pos 12 /*!< USIC_CH BYPCR: BDVTR Position */
\r
2621 #define USIC_CH_BYPCR_BDVTR_Msk (0x01UL << USIC_CH_BYPCR_BDVTR_Pos) /*!< USIC_CH BYPCR: BDVTR Mask */
\r
2622 #define USIC_CH_BYPCR_BPRIO_Pos 13 /*!< USIC_CH BYPCR: BPRIO Position */
\r
2623 #define USIC_CH_BYPCR_BPRIO_Msk (0x01UL << USIC_CH_BYPCR_BPRIO_Pos) /*!< USIC_CH BYPCR: BPRIO Mask */
\r
2624 #define USIC_CH_BYPCR_BDV_Pos 15 /*!< USIC_CH BYPCR: BDV Position */
\r
2625 #define USIC_CH_BYPCR_BDV_Msk (0x01UL << USIC_CH_BYPCR_BDV_Pos) /*!< USIC_CH BYPCR: BDV Mask */
\r
2626 #define USIC_CH_BYPCR_BSELO_Pos 16 /*!< USIC_CH BYPCR: BSELO Position */
\r
2627 #define USIC_CH_BYPCR_BSELO_Msk (0x1fUL << USIC_CH_BYPCR_BSELO_Pos) /*!< USIC_CH BYPCR: BSELO Mask */
\r
2628 #define USIC_CH_BYPCR_BHPC_Pos 21 /*!< USIC_CH BYPCR: BHPC Position */
\r
2629 #define USIC_CH_BYPCR_BHPC_Msk (0x07UL << USIC_CH_BYPCR_BHPC_Pos) /*!< USIC_CH BYPCR: BHPC Mask */
\r
2631 /* -------------------------------- USIC_CH_TBCTR ------------------------------- */
\r
2632 #define USIC_CH_TBCTR_DPTR_Pos 0 /*!< USIC_CH TBCTR: DPTR Position */
\r
2633 #define USIC_CH_TBCTR_DPTR_Msk (0x3fUL << USIC_CH_TBCTR_DPTR_Pos) /*!< USIC_CH TBCTR: DPTR Mask */
\r
2634 #define USIC_CH_TBCTR_LIMIT_Pos 8 /*!< USIC_CH TBCTR: LIMIT Position */
\r
2635 #define USIC_CH_TBCTR_LIMIT_Msk (0x3fUL << USIC_CH_TBCTR_LIMIT_Pos) /*!< USIC_CH TBCTR: LIMIT Mask */
\r
2636 #define USIC_CH_TBCTR_STBTM_Pos 14 /*!< USIC_CH TBCTR: STBTM Position */
\r
2637 #define USIC_CH_TBCTR_STBTM_Msk (0x01UL << USIC_CH_TBCTR_STBTM_Pos) /*!< USIC_CH TBCTR: STBTM Mask */
\r
2638 #define USIC_CH_TBCTR_STBTEN_Pos 15 /*!< USIC_CH TBCTR: STBTEN Position */
\r
2639 #define USIC_CH_TBCTR_STBTEN_Msk (0x01UL << USIC_CH_TBCTR_STBTEN_Pos) /*!< USIC_CH TBCTR: STBTEN Mask */
\r
2640 #define USIC_CH_TBCTR_STBINP_Pos 16 /*!< USIC_CH TBCTR: STBINP Position */
\r
2641 #define USIC_CH_TBCTR_STBINP_Msk (0x07UL << USIC_CH_TBCTR_STBINP_Pos) /*!< USIC_CH TBCTR: STBINP Mask */
\r
2642 #define USIC_CH_TBCTR_ATBINP_Pos 19 /*!< USIC_CH TBCTR: ATBINP Position */
\r
2643 #define USIC_CH_TBCTR_ATBINP_Msk (0x07UL << USIC_CH_TBCTR_ATBINP_Pos) /*!< USIC_CH TBCTR: ATBINP Mask */
\r
2644 #define USIC_CH_TBCTR_SIZE_Pos 24 /*!< USIC_CH TBCTR: SIZE Position */
\r
2645 #define USIC_CH_TBCTR_SIZE_Msk (0x07UL << USIC_CH_TBCTR_SIZE_Pos) /*!< USIC_CH TBCTR: SIZE Mask */
\r
2646 #define USIC_CH_TBCTR_LOF_Pos 28 /*!< USIC_CH TBCTR: LOF Position */
\r
2647 #define USIC_CH_TBCTR_LOF_Msk (0x01UL << USIC_CH_TBCTR_LOF_Pos) /*!< USIC_CH TBCTR: LOF Mask */
\r
2648 #define USIC_CH_TBCTR_STBIEN_Pos 30 /*!< USIC_CH TBCTR: STBIEN Position */
\r
2649 #define USIC_CH_TBCTR_STBIEN_Msk (0x01UL << USIC_CH_TBCTR_STBIEN_Pos) /*!< USIC_CH TBCTR: STBIEN Mask */
\r
2650 #define USIC_CH_TBCTR_TBERIEN_Pos 31 /*!< USIC_CH TBCTR: TBERIEN Position */
\r
2651 #define USIC_CH_TBCTR_TBERIEN_Msk (0x01UL << USIC_CH_TBCTR_TBERIEN_Pos) /*!< USIC_CH TBCTR: TBERIEN Mask */
\r
2653 /* -------------------------------- USIC_CH_RBCTR ------------------------------- */
\r
2654 #define USIC_CH_RBCTR_DPTR_Pos 0 /*!< USIC_CH RBCTR: DPTR Position */
\r
2655 #define USIC_CH_RBCTR_DPTR_Msk (0x3fUL << USIC_CH_RBCTR_DPTR_Pos) /*!< USIC_CH RBCTR: DPTR Mask */
\r
2656 #define USIC_CH_RBCTR_LIMIT_Pos 8 /*!< USIC_CH RBCTR: LIMIT Position */
\r
2657 #define USIC_CH_RBCTR_LIMIT_Msk (0x3fUL << USIC_CH_RBCTR_LIMIT_Pos) /*!< USIC_CH RBCTR: LIMIT Mask */
\r
2658 #define USIC_CH_RBCTR_SRBTM_Pos 14 /*!< USIC_CH RBCTR: SRBTM Position */
\r
2659 #define USIC_CH_RBCTR_SRBTM_Msk (0x01UL << USIC_CH_RBCTR_SRBTM_Pos) /*!< USIC_CH RBCTR: SRBTM Mask */
\r
2660 #define USIC_CH_RBCTR_SRBTEN_Pos 15 /*!< USIC_CH RBCTR: SRBTEN Position */
\r
2661 #define USIC_CH_RBCTR_SRBTEN_Msk (0x01UL << USIC_CH_RBCTR_SRBTEN_Pos) /*!< USIC_CH RBCTR: SRBTEN Mask */
\r
2662 #define USIC_CH_RBCTR_SRBINP_Pos 16 /*!< USIC_CH RBCTR: SRBINP Position */
\r
2663 #define USIC_CH_RBCTR_SRBINP_Msk (0x07UL << USIC_CH_RBCTR_SRBINP_Pos) /*!< USIC_CH RBCTR: SRBINP Mask */
\r
2664 #define USIC_CH_RBCTR_ARBINP_Pos 19 /*!< USIC_CH RBCTR: ARBINP Position */
\r
2665 #define USIC_CH_RBCTR_ARBINP_Msk (0x07UL << USIC_CH_RBCTR_ARBINP_Pos) /*!< USIC_CH RBCTR: ARBINP Mask */
\r
2666 #define USIC_CH_RBCTR_RCIM_Pos 22 /*!< USIC_CH RBCTR: RCIM Position */
\r
2667 #define USIC_CH_RBCTR_RCIM_Msk (0x03UL << USIC_CH_RBCTR_RCIM_Pos) /*!< USIC_CH RBCTR: RCIM Mask */
\r
2668 #define USIC_CH_RBCTR_SIZE_Pos 24 /*!< USIC_CH RBCTR: SIZE Position */
\r
2669 #define USIC_CH_RBCTR_SIZE_Msk (0x07UL << USIC_CH_RBCTR_SIZE_Pos) /*!< USIC_CH RBCTR: SIZE Mask */
\r
2670 #define USIC_CH_RBCTR_RNM_Pos 27 /*!< USIC_CH RBCTR: RNM Position */
\r
2671 #define USIC_CH_RBCTR_RNM_Msk (0x01UL << USIC_CH_RBCTR_RNM_Pos) /*!< USIC_CH RBCTR: RNM Mask */
\r
2672 #define USIC_CH_RBCTR_LOF_Pos 28 /*!< USIC_CH RBCTR: LOF Position */
\r
2673 #define USIC_CH_RBCTR_LOF_Msk (0x01UL << USIC_CH_RBCTR_LOF_Pos) /*!< USIC_CH RBCTR: LOF Mask */
\r
2674 #define USIC_CH_RBCTR_ARBIEN_Pos 29 /*!< USIC_CH RBCTR: ARBIEN Position */
\r
2675 #define USIC_CH_RBCTR_ARBIEN_Msk (0x01UL << USIC_CH_RBCTR_ARBIEN_Pos) /*!< USIC_CH RBCTR: ARBIEN Mask */
\r
2676 #define USIC_CH_RBCTR_SRBIEN_Pos 30 /*!< USIC_CH RBCTR: SRBIEN Position */
\r
2677 #define USIC_CH_RBCTR_SRBIEN_Msk (0x01UL << USIC_CH_RBCTR_SRBIEN_Pos) /*!< USIC_CH RBCTR: SRBIEN Mask */
\r
2678 #define USIC_CH_RBCTR_RBERIEN_Pos 31 /*!< USIC_CH RBCTR: RBERIEN Position */
\r
2679 #define USIC_CH_RBCTR_RBERIEN_Msk (0x01UL << USIC_CH_RBCTR_RBERIEN_Pos) /*!< USIC_CH RBCTR: RBERIEN Mask */
\r
2681 /* ------------------------------- USIC_CH_TRBPTR ------------------------------- */
\r
2682 #define USIC_CH_TRBPTR_TDIPTR_Pos 0 /*!< USIC_CH TRBPTR: TDIPTR Position */
\r
2683 #define USIC_CH_TRBPTR_TDIPTR_Msk (0x3fUL << USIC_CH_TRBPTR_TDIPTR_Pos) /*!< USIC_CH TRBPTR: TDIPTR Mask */
\r
2684 #define USIC_CH_TRBPTR_TDOPTR_Pos 8 /*!< USIC_CH TRBPTR: TDOPTR Position */
\r
2685 #define USIC_CH_TRBPTR_TDOPTR_Msk (0x3fUL << USIC_CH_TRBPTR_TDOPTR_Pos) /*!< USIC_CH TRBPTR: TDOPTR Mask */
\r
2686 #define USIC_CH_TRBPTR_RDIPTR_Pos 16 /*!< USIC_CH TRBPTR: RDIPTR Position */
\r
2687 #define USIC_CH_TRBPTR_RDIPTR_Msk (0x3fUL << USIC_CH_TRBPTR_RDIPTR_Pos) /*!< USIC_CH TRBPTR: RDIPTR Mask */
\r
2688 #define USIC_CH_TRBPTR_RDOPTR_Pos 24 /*!< USIC_CH TRBPTR: RDOPTR Position */
\r
2689 #define USIC_CH_TRBPTR_RDOPTR_Msk (0x3fUL << USIC_CH_TRBPTR_RDOPTR_Pos) /*!< USIC_CH TRBPTR: RDOPTR Mask */
\r
2691 /* -------------------------------- USIC_CH_TRBSR ------------------------------- */
\r
2692 #define USIC_CH_TRBSR_SRBI_Pos 0 /*!< USIC_CH TRBSR: SRBI Position */
\r
2693 #define USIC_CH_TRBSR_SRBI_Msk (0x01UL << USIC_CH_TRBSR_SRBI_Pos) /*!< USIC_CH TRBSR: SRBI Mask */
\r
2694 #define USIC_CH_TRBSR_RBERI_Pos 1 /*!< USIC_CH TRBSR: RBERI Position */
\r
2695 #define USIC_CH_TRBSR_RBERI_Msk (0x01UL << USIC_CH_TRBSR_RBERI_Pos) /*!< USIC_CH TRBSR: RBERI Mask */
\r
2696 #define USIC_CH_TRBSR_ARBI_Pos 2 /*!< USIC_CH TRBSR: ARBI Position */
\r
2697 #define USIC_CH_TRBSR_ARBI_Msk (0x01UL << USIC_CH_TRBSR_ARBI_Pos) /*!< USIC_CH TRBSR: ARBI Mask */
\r
2698 #define USIC_CH_TRBSR_REMPTY_Pos 3 /*!< USIC_CH TRBSR: REMPTY Position */
\r
2699 #define USIC_CH_TRBSR_REMPTY_Msk (0x01UL << USIC_CH_TRBSR_REMPTY_Pos) /*!< USIC_CH TRBSR: REMPTY Mask */
\r
2700 #define USIC_CH_TRBSR_RFULL_Pos 4 /*!< USIC_CH TRBSR: RFULL Position */
\r
2701 #define USIC_CH_TRBSR_RFULL_Msk (0x01UL << USIC_CH_TRBSR_RFULL_Pos) /*!< USIC_CH TRBSR: RFULL Mask */
\r
2702 #define USIC_CH_TRBSR_RBUS_Pos 5 /*!< USIC_CH TRBSR: RBUS Position */
\r
2703 #define USIC_CH_TRBSR_RBUS_Msk (0x01UL << USIC_CH_TRBSR_RBUS_Pos) /*!< USIC_CH TRBSR: RBUS Mask */
\r
2704 #define USIC_CH_TRBSR_SRBT_Pos 6 /*!< USIC_CH TRBSR: SRBT Position */
\r
2705 #define USIC_CH_TRBSR_SRBT_Msk (0x01UL << USIC_CH_TRBSR_SRBT_Pos) /*!< USIC_CH TRBSR: SRBT Mask */
\r
2706 #define USIC_CH_TRBSR_STBI_Pos 8 /*!< USIC_CH TRBSR: STBI Position */
\r
2707 #define USIC_CH_TRBSR_STBI_Msk (0x01UL << USIC_CH_TRBSR_STBI_Pos) /*!< USIC_CH TRBSR: STBI Mask */
\r
2708 #define USIC_CH_TRBSR_TBERI_Pos 9 /*!< USIC_CH TRBSR: TBERI Position */
\r
2709 #define USIC_CH_TRBSR_TBERI_Msk (0x01UL << USIC_CH_TRBSR_TBERI_Pos) /*!< USIC_CH TRBSR: TBERI Mask */
\r
2710 #define USIC_CH_TRBSR_TEMPTY_Pos 11 /*!< USIC_CH TRBSR: TEMPTY Position */
\r
2711 #define USIC_CH_TRBSR_TEMPTY_Msk (0x01UL << USIC_CH_TRBSR_TEMPTY_Pos) /*!< USIC_CH TRBSR: TEMPTY Mask */
\r
2712 #define USIC_CH_TRBSR_TFULL_Pos 12 /*!< USIC_CH TRBSR: TFULL Position */
\r
2713 #define USIC_CH_TRBSR_TFULL_Msk (0x01UL << USIC_CH_TRBSR_TFULL_Pos) /*!< USIC_CH TRBSR: TFULL Mask */
\r
2714 #define USIC_CH_TRBSR_TBUS_Pos 13 /*!< USIC_CH TRBSR: TBUS Position */
\r
2715 #define USIC_CH_TRBSR_TBUS_Msk (0x01UL << USIC_CH_TRBSR_TBUS_Pos) /*!< USIC_CH TRBSR: TBUS Mask */
\r
2716 #define USIC_CH_TRBSR_STBT_Pos 14 /*!< USIC_CH TRBSR: STBT Position */
\r
2717 #define USIC_CH_TRBSR_STBT_Msk (0x01UL << USIC_CH_TRBSR_STBT_Pos) /*!< USIC_CH TRBSR: STBT Mask */
\r
2718 #define USIC_CH_TRBSR_RBFLVL_Pos 16 /*!< USIC_CH TRBSR: RBFLVL Position */
\r
2719 #define USIC_CH_TRBSR_RBFLVL_Msk (0x7fUL << USIC_CH_TRBSR_RBFLVL_Pos) /*!< USIC_CH TRBSR: RBFLVL Mask */
\r
2720 #define USIC_CH_TRBSR_TBFLVL_Pos 24 /*!< USIC_CH TRBSR: TBFLVL Position */
\r
2721 #define USIC_CH_TRBSR_TBFLVL_Msk (0x7fUL << USIC_CH_TRBSR_TBFLVL_Pos) /*!< USIC_CH TRBSR: TBFLVL Mask */
\r
2723 /* ------------------------------- USIC_CH_TRBSCR ------------------------------- */
\r
2724 #define USIC_CH_TRBSCR_CSRBI_Pos 0 /*!< USIC_CH TRBSCR: CSRBI Position */
\r
2725 #define USIC_CH_TRBSCR_CSRBI_Msk (0x01UL << USIC_CH_TRBSCR_CSRBI_Pos) /*!< USIC_CH TRBSCR: CSRBI Mask */
\r
2726 #define USIC_CH_TRBSCR_CRBERI_Pos 1 /*!< USIC_CH TRBSCR: CRBERI Position */
\r
2727 #define USIC_CH_TRBSCR_CRBERI_Msk (0x01UL << USIC_CH_TRBSCR_CRBERI_Pos) /*!< USIC_CH TRBSCR: CRBERI Mask */
\r
2728 #define USIC_CH_TRBSCR_CARBI_Pos 2 /*!< USIC_CH TRBSCR: CARBI Position */
\r
2729 #define USIC_CH_TRBSCR_CARBI_Msk (0x01UL << USIC_CH_TRBSCR_CARBI_Pos) /*!< USIC_CH TRBSCR: CARBI Mask */
\r
2730 #define USIC_CH_TRBSCR_CSTBI_Pos 8 /*!< USIC_CH TRBSCR: CSTBI Position */
\r
2731 #define USIC_CH_TRBSCR_CSTBI_Msk (0x01UL << USIC_CH_TRBSCR_CSTBI_Pos) /*!< USIC_CH TRBSCR: CSTBI Mask */
\r
2732 #define USIC_CH_TRBSCR_CTBERI_Pos 9 /*!< USIC_CH TRBSCR: CTBERI Position */
\r
2733 #define USIC_CH_TRBSCR_CTBERI_Msk (0x01UL << USIC_CH_TRBSCR_CTBERI_Pos) /*!< USIC_CH TRBSCR: CTBERI Mask */
\r
2734 #define USIC_CH_TRBSCR_CBDV_Pos 10 /*!< USIC_CH TRBSCR: CBDV Position */
\r
2735 #define USIC_CH_TRBSCR_CBDV_Msk (0x01UL << USIC_CH_TRBSCR_CBDV_Pos) /*!< USIC_CH TRBSCR: CBDV Mask */
\r
2736 #define USIC_CH_TRBSCR_FLUSHRB_Pos 14 /*!< USIC_CH TRBSCR: FLUSHRB Position */
\r
2737 #define USIC_CH_TRBSCR_FLUSHRB_Msk (0x01UL << USIC_CH_TRBSCR_FLUSHRB_Pos) /*!< USIC_CH TRBSCR: FLUSHRB Mask */
\r
2738 #define USIC_CH_TRBSCR_FLUSHTB_Pos 15 /*!< USIC_CH TRBSCR: FLUSHTB Position */
\r
2739 #define USIC_CH_TRBSCR_FLUSHTB_Msk (0x01UL << USIC_CH_TRBSCR_FLUSHTB_Pos) /*!< USIC_CH TRBSCR: FLUSHTB Mask */
\r
2741 /* -------------------------------- USIC_CH_OUTR -------------------------------- */
\r
2742 #define USIC_CH_OUTR_DSR_Pos 0 /*!< USIC_CH OUTR: DSR Position */
\r
2743 #define USIC_CH_OUTR_DSR_Msk (0x0000ffffUL << USIC_CH_OUTR_DSR_Pos) /*!< USIC_CH OUTR: DSR Mask */
\r
2744 #define USIC_CH_OUTR_RCI_Pos 16 /*!< USIC_CH OUTR: RCI Position */
\r
2745 #define USIC_CH_OUTR_RCI_Msk (0x1fUL << USIC_CH_OUTR_RCI_Pos) /*!< USIC_CH OUTR: RCI Mask */
\r
2747 /* -------------------------------- USIC_CH_OUTDR ------------------------------- */
\r
2748 #define USIC_CH_OUTDR_DSR_Pos 0 /*!< USIC_CH OUTDR: DSR Position */
\r
2749 #define USIC_CH_OUTDR_DSR_Msk (0x0000ffffUL << USIC_CH_OUTDR_DSR_Pos) /*!< USIC_CH OUTDR: DSR Mask */
\r
2750 #define USIC_CH_OUTDR_RCI_Pos 16 /*!< USIC_CH OUTDR: RCI Position */
\r
2751 #define USIC_CH_OUTDR_RCI_Msk (0x1fUL << USIC_CH_OUTDR_RCI_Pos) /*!< USIC_CH OUTDR: RCI Mask */
\r
2753 /* --------------------------------- USIC_CH_IN --------------------------------- */
\r
2754 #define USIC_CH_IN_TDATA_Pos 0 /*!< USIC_CH IN: TDATA Position */
\r
2755 #define USIC_CH_IN_TDATA_Msk (0x0000ffffUL << USIC_CH_IN_TDATA_Pos) /*!< USIC_CH IN: TDATA Mask */
\r
2758 /* ================================================================================ */
\r
2759 /* ================ struct 'SCU_GENERAL' Position & Mask ================ */
\r
2760 /* ================================================================================ */
\r
2763 /* ---------------------------- SCU_GENERAL_DBGROMID ---------------------------- */
\r
2764 #define SCU_GENERAL_DBGROMID_MANUFID_Pos 1 /*!< SCU_GENERAL DBGROMID: MANUFID Position */
\r
2765 #define SCU_GENERAL_DBGROMID_MANUFID_Msk (0x000007ffUL << SCU_GENERAL_DBGROMID_MANUFID_Pos) /*!< SCU_GENERAL DBGROMID: MANUFID Mask */
\r
2766 #define SCU_GENERAL_DBGROMID_PARTNO_Pos 12 /*!< SCU_GENERAL DBGROMID: PARTNO Position */
\r
2767 #define SCU_GENERAL_DBGROMID_PARTNO_Msk (0x0000ffffUL << SCU_GENERAL_DBGROMID_PARTNO_Pos) /*!< SCU_GENERAL DBGROMID: PARTNO Mask */
\r
2768 #define SCU_GENERAL_DBGROMID_VERSION_Pos 28 /*!< SCU_GENERAL DBGROMID: VERSION Position */
\r
2769 #define SCU_GENERAL_DBGROMID_VERSION_Msk (0x0fUL << SCU_GENERAL_DBGROMID_VERSION_Pos) /*!< SCU_GENERAL DBGROMID: VERSION Mask */
\r
2771 /* ----------------------------- SCU_GENERAL_IDCHIP ----------------------------- */
\r
2772 #define SCU_GENERAL_IDCHIP_IDCHIP_Pos 0 /*!< SCU_GENERAL IDCHIP: IDCHIP Position */
\r
2773 #define SCU_GENERAL_IDCHIP_IDCHIP_Msk (0xffffffffUL << SCU_GENERAL_IDCHIP_IDCHIP_Pos) /*!< SCU_GENERAL IDCHIP: IDCHIP Mask */
\r
2775 /* ------------------------------- SCU_GENERAL_ID ------------------------------- */
\r
2776 #define SCU_GENERAL_ID_MOD_REV_Pos 0 /*!< SCU_GENERAL ID: MOD_REV Position */
\r
2777 #define SCU_GENERAL_ID_MOD_REV_Msk (0x000000ffUL << SCU_GENERAL_ID_MOD_REV_Pos) /*!< SCU_GENERAL ID: MOD_REV Mask */
\r
2778 #define SCU_GENERAL_ID_MOD_TYPE_Pos 8 /*!< SCU_GENERAL ID: MOD_TYPE Position */
\r
2779 #define SCU_GENERAL_ID_MOD_TYPE_Msk (0x000000ffUL << SCU_GENERAL_ID_MOD_TYPE_Pos) /*!< SCU_GENERAL ID: MOD_TYPE Mask */
\r
2780 #define SCU_GENERAL_ID_MOD_NUMBER_Pos 16 /*!< SCU_GENERAL ID: MOD_NUMBER Position */
\r
2781 #define SCU_GENERAL_ID_MOD_NUMBER_Msk (0x0000ffffUL << SCU_GENERAL_ID_MOD_NUMBER_Pos) /*!< SCU_GENERAL ID: MOD_NUMBER Mask */
\r
2783 /* ------------------------------ SCU_GENERAL_SSW0 ------------------------------ */
\r
2784 #define SCU_GENERAL_SSW0_DAT_Pos 0 /*!< SCU_GENERAL SSW0: DAT Position */
\r
2785 #define SCU_GENERAL_SSW0_DAT_Msk (0xffffffffUL << SCU_GENERAL_SSW0_DAT_Pos) /*!< SCU_GENERAL SSW0: DAT Mask */
\r
2787 /* ----------------------------- SCU_GENERAL_PASSWD ----------------------------- */
\r
2788 #define SCU_GENERAL_PASSWD_MODE_Pos 0 /*!< SCU_GENERAL PASSWD: MODE Position */
\r
2789 #define SCU_GENERAL_PASSWD_MODE_Msk (0x03UL << SCU_GENERAL_PASSWD_MODE_Pos) /*!< SCU_GENERAL PASSWD: MODE Mask */
\r
2790 #define SCU_GENERAL_PASSWD_PROTS_Pos 2 /*!< SCU_GENERAL PASSWD: PROTS Position */
\r
2791 #define SCU_GENERAL_PASSWD_PROTS_Msk (0x01UL << SCU_GENERAL_PASSWD_PROTS_Pos) /*!< SCU_GENERAL PASSWD: PROTS Mask */
\r
2792 #define SCU_GENERAL_PASSWD_PASS_Pos 3 /*!< SCU_GENERAL PASSWD: PASS Position */
\r
2793 #define SCU_GENERAL_PASSWD_PASS_Msk (0x1fUL << SCU_GENERAL_PASSWD_PASS_Pos) /*!< SCU_GENERAL PASSWD: PASS Mask */
\r
2795 /* ----------------------------- SCU_GENERAL_CCUCON ----------------------------- */
\r
2796 #define SCU_GENERAL_CCUCON_GSC40_Pos 0 /*!< SCU_GENERAL CCUCON: GSC40 Position */
\r
2797 #define SCU_GENERAL_CCUCON_GSC40_Msk (0x01UL << SCU_GENERAL_CCUCON_GSC40_Pos) /*!< SCU_GENERAL CCUCON: GSC40 Mask */
\r
2798 #define SCU_GENERAL_CCUCON_GSC80_Pos 8 /*!< SCU_GENERAL CCUCON: GSC80 Position */
\r
2799 #define SCU_GENERAL_CCUCON_GSC80_Msk (0x01UL << SCU_GENERAL_CCUCON_GSC80_Pos) /*!< SCU_GENERAL CCUCON: GSC80 Mask */
\r
2801 /* ----------------------------- SCU_GENERAL_MIRRSTS ---------------------------- */
\r
2802 #define SCU_GENERAL_MIRRSTS_RTC_CTR_Pos 0 /*!< SCU_GENERAL MIRRSTS: RTC_CTR Position */
\r
2803 #define SCU_GENERAL_MIRRSTS_RTC_CTR_Msk (0x01UL << SCU_GENERAL_MIRRSTS_RTC_CTR_Pos) /*!< SCU_GENERAL MIRRSTS: RTC_CTR Mask */
\r
2804 #define SCU_GENERAL_MIRRSTS_RTC_ATIM0_Pos 1 /*!< SCU_GENERAL MIRRSTS: RTC_ATIM0 Position */
\r
2805 #define SCU_GENERAL_MIRRSTS_RTC_ATIM0_Msk (0x01UL << SCU_GENERAL_MIRRSTS_RTC_ATIM0_Pos) /*!< SCU_GENERAL MIRRSTS: RTC_ATIM0 Mask */
\r
2806 #define SCU_GENERAL_MIRRSTS_RTC_ATIM1_Pos 2 /*!< SCU_GENERAL MIRRSTS: RTC_ATIM1 Position */
\r
2807 #define SCU_GENERAL_MIRRSTS_RTC_ATIM1_Msk (0x01UL << SCU_GENERAL_MIRRSTS_RTC_ATIM1_Pos) /*!< SCU_GENERAL MIRRSTS: RTC_ATIM1 Mask */
\r
2808 #define SCU_GENERAL_MIRRSTS_RTC_TIM0_Pos 3 /*!< SCU_GENERAL MIRRSTS: RTC_TIM0 Position */
\r
2809 #define SCU_GENERAL_MIRRSTS_RTC_TIM0_Msk (0x01UL << SCU_GENERAL_MIRRSTS_RTC_TIM0_Pos) /*!< SCU_GENERAL MIRRSTS: RTC_TIM0 Mask */
\r
2810 #define SCU_GENERAL_MIRRSTS_RTC_TIM1_Pos 4 /*!< SCU_GENERAL MIRRSTS: RTC_TIM1 Position */
\r
2811 #define SCU_GENERAL_MIRRSTS_RTC_TIM1_Msk (0x01UL << SCU_GENERAL_MIRRSTS_RTC_TIM1_Pos) /*!< SCU_GENERAL MIRRSTS: RTC_TIM1 Mask */
\r
2813 /* ------------------------------ SCU_GENERAL_PMTSR ----------------------------- */
\r
2814 #define SCU_GENERAL_PMTSR_MTENS_Pos 0 /*!< SCU_GENERAL PMTSR: MTENS Position */
\r
2815 #define SCU_GENERAL_PMTSR_MTENS_Msk (0x01UL << SCU_GENERAL_PMTSR_MTENS_Pos) /*!< SCU_GENERAL PMTSR: MTENS Mask */
\r
2818 /* ================================================================================ */
\r
2819 /* ================ struct 'SCU_INTERRUPT' Position & Mask ================ */
\r
2820 /* ================================================================================ */
\r
2823 /* ----------------------------- SCU_INTERRUPT_SRRAW ---------------------------- */
\r
2824 #define SCU_INTERRUPT_SRRAW_PRWARN_Pos 0 /*!< SCU_INTERRUPT SRRAW: PRWARN Position */
\r
2825 #define SCU_INTERRUPT_SRRAW_PRWARN_Msk (0x01UL << SCU_INTERRUPT_SRRAW_PRWARN_Pos) /*!< SCU_INTERRUPT SRRAW: PRWARN Mask */
\r
2826 #define SCU_INTERRUPT_SRRAW_PI_Pos 1 /*!< SCU_INTERRUPT SRRAW: PI Position */
\r
2827 #define SCU_INTERRUPT_SRRAW_PI_Msk (0x01UL << SCU_INTERRUPT_SRRAW_PI_Pos) /*!< SCU_INTERRUPT SRRAW: PI Mask */
\r
2828 #define SCU_INTERRUPT_SRRAW_AI_Pos 2 /*!< SCU_INTERRUPT SRRAW: AI Position */
\r
2829 #define SCU_INTERRUPT_SRRAW_AI_Msk (0x01UL << SCU_INTERRUPT_SRRAW_AI_Pos) /*!< SCU_INTERRUPT SRRAW: AI Mask */
\r
2830 #define SCU_INTERRUPT_SRRAW_VDDPI_Pos 3 /*!< SCU_INTERRUPT SRRAW: VDDPI Position */
\r
2831 #define SCU_INTERRUPT_SRRAW_VDDPI_Msk (0x01UL << SCU_INTERRUPT_SRRAW_VDDPI_Pos) /*!< SCU_INTERRUPT SRRAW: VDDPI Mask */
\r
2832 #define SCU_INTERRUPT_SRRAW_ACMP0I_Pos 4 /*!< SCU_INTERRUPT SRRAW: ACMP0I Position */
\r
2833 #define SCU_INTERRUPT_SRRAW_ACMP0I_Msk (0x01UL << SCU_INTERRUPT_SRRAW_ACMP0I_Pos) /*!< SCU_INTERRUPT SRRAW: ACMP0I Mask */
\r
2834 #define SCU_INTERRUPT_SRRAW_ACMP1I_Pos 5 /*!< SCU_INTERRUPT SRRAW: ACMP1I Position */
\r
2835 #define SCU_INTERRUPT_SRRAW_ACMP1I_Msk (0x01UL << SCU_INTERRUPT_SRRAW_ACMP1I_Pos) /*!< SCU_INTERRUPT SRRAW: ACMP1I Mask */
\r
2836 #define SCU_INTERRUPT_SRRAW_ACMP2I_Pos 6 /*!< SCU_INTERRUPT SRRAW: ACMP2I Position */
\r
2837 #define SCU_INTERRUPT_SRRAW_ACMP2I_Msk (0x01UL << SCU_INTERRUPT_SRRAW_ACMP2I_Pos) /*!< SCU_INTERRUPT SRRAW: ACMP2I Mask */
\r
2838 #define SCU_INTERRUPT_SRRAW_VDROPI_Pos 7 /*!< SCU_INTERRUPT SRRAW: VDROPI Position */
\r
2839 #define SCU_INTERRUPT_SRRAW_VDROPI_Msk (0x01UL << SCU_INTERRUPT_SRRAW_VDROPI_Pos) /*!< SCU_INTERRUPT SRRAW: VDROPI Mask */
\r
2840 #define SCU_INTERRUPT_SRRAW_ORC0I_Pos 8 /*!< SCU_INTERRUPT SRRAW: ORC0I Position */
\r
2841 #define SCU_INTERRUPT_SRRAW_ORC0I_Msk (0x01UL << SCU_INTERRUPT_SRRAW_ORC0I_Pos) /*!< SCU_INTERRUPT SRRAW: ORC0I Mask */
\r
2842 #define SCU_INTERRUPT_SRRAW_ORC1I_Pos 9 /*!< SCU_INTERRUPT SRRAW: ORC1I Position */
\r
2843 #define SCU_INTERRUPT_SRRAW_ORC1I_Msk (0x01UL << SCU_INTERRUPT_SRRAW_ORC1I_Pos) /*!< SCU_INTERRUPT SRRAW: ORC1I Mask */
\r
2844 #define SCU_INTERRUPT_SRRAW_ORC2I_Pos 10 /*!< SCU_INTERRUPT SRRAW: ORC2I Position */
\r
2845 #define SCU_INTERRUPT_SRRAW_ORC2I_Msk (0x01UL << SCU_INTERRUPT_SRRAW_ORC2I_Pos) /*!< SCU_INTERRUPT SRRAW: ORC2I Mask */
\r
2846 #define SCU_INTERRUPT_SRRAW_ORC3I_Pos 11 /*!< SCU_INTERRUPT SRRAW: ORC3I Position */
\r
2847 #define SCU_INTERRUPT_SRRAW_ORC3I_Msk (0x01UL << SCU_INTERRUPT_SRRAW_ORC3I_Pos) /*!< SCU_INTERRUPT SRRAW: ORC3I Mask */
\r
2848 #define SCU_INTERRUPT_SRRAW_ORC4I_Pos 12 /*!< SCU_INTERRUPT SRRAW: ORC4I Position */
\r
2849 #define SCU_INTERRUPT_SRRAW_ORC4I_Msk (0x01UL << SCU_INTERRUPT_SRRAW_ORC4I_Pos) /*!< SCU_INTERRUPT SRRAW: ORC4I Mask */
\r
2850 #define SCU_INTERRUPT_SRRAW_ORC5I_Pos 13 /*!< SCU_INTERRUPT SRRAW: ORC5I Position */
\r
2851 #define SCU_INTERRUPT_SRRAW_ORC5I_Msk (0x01UL << SCU_INTERRUPT_SRRAW_ORC5I_Pos) /*!< SCU_INTERRUPT SRRAW: ORC5I Mask */
\r
2852 #define SCU_INTERRUPT_SRRAW_ORC6I_Pos 14 /*!< SCU_INTERRUPT SRRAW: ORC6I Position */
\r
2853 #define SCU_INTERRUPT_SRRAW_ORC6I_Msk (0x01UL << SCU_INTERRUPT_SRRAW_ORC6I_Pos) /*!< SCU_INTERRUPT SRRAW: ORC6I Mask */
\r
2854 #define SCU_INTERRUPT_SRRAW_ORC7I_Pos 15 /*!< SCU_INTERRUPT SRRAW: ORC7I Position */
\r
2855 #define SCU_INTERRUPT_SRRAW_ORC7I_Msk (0x01UL << SCU_INTERRUPT_SRRAW_ORC7I_Pos) /*!< SCU_INTERRUPT SRRAW: ORC7I Mask */
\r
2856 #define SCU_INTERRUPT_SRRAW_LOCI_Pos 16 /*!< SCU_INTERRUPT SRRAW: LOCI Position */
\r
2857 #define SCU_INTERRUPT_SRRAW_LOCI_Msk (0x01UL << SCU_INTERRUPT_SRRAW_LOCI_Pos) /*!< SCU_INTERRUPT SRRAW: LOCI Mask */
\r
2858 #define SCU_INTERRUPT_SRRAW_PESRAMI_Pos 17 /*!< SCU_INTERRUPT SRRAW: PESRAMI Position */
\r
2859 #define SCU_INTERRUPT_SRRAW_PESRAMI_Msk (0x01UL << SCU_INTERRUPT_SRRAW_PESRAMI_Pos) /*!< SCU_INTERRUPT SRRAW: PESRAMI Mask */
\r
2860 #define SCU_INTERRUPT_SRRAW_PEU0I_Pos 18 /*!< SCU_INTERRUPT SRRAW: PEU0I Position */
\r
2861 #define SCU_INTERRUPT_SRRAW_PEU0I_Msk (0x01UL << SCU_INTERRUPT_SRRAW_PEU0I_Pos) /*!< SCU_INTERRUPT SRRAW: PEU0I Mask */
\r
2862 #define SCU_INTERRUPT_SRRAW_FLECC2I_Pos 19 /*!< SCU_INTERRUPT SRRAW: FLECC2I Position */
\r
2863 #define SCU_INTERRUPT_SRRAW_FLECC2I_Msk (0x01UL << SCU_INTERRUPT_SRRAW_FLECC2I_Pos) /*!< SCU_INTERRUPT SRRAW: FLECC2I Mask */
\r
2864 #define SCU_INTERRUPT_SRRAW_FLCMPLTI_Pos 20 /*!< SCU_INTERRUPT SRRAW: FLCMPLTI Position */
\r
2865 #define SCU_INTERRUPT_SRRAW_FLCMPLTI_Msk (0x01UL << SCU_INTERRUPT_SRRAW_FLCMPLTI_Pos) /*!< SCU_INTERRUPT SRRAW: FLCMPLTI Mask */
\r
2866 #define SCU_INTERRUPT_SRRAW_VCLIPI_Pos 21 /*!< SCU_INTERRUPT SRRAW: VCLIPI Position */
\r
2867 #define SCU_INTERRUPT_SRRAW_VCLIPI_Msk (0x01UL << SCU_INTERRUPT_SRRAW_VCLIPI_Pos) /*!< SCU_INTERRUPT SRRAW: VCLIPI Mask */
\r
2868 #define SCU_INTERRUPT_SRRAW_SBYCLKFI_Pos 22 /*!< SCU_INTERRUPT SRRAW: SBYCLKFI Position */
\r
2869 #define SCU_INTERRUPT_SRRAW_SBYCLKFI_Msk (0x01UL << SCU_INTERRUPT_SRRAW_SBYCLKFI_Pos) /*!< SCU_INTERRUPT SRRAW: SBYCLKFI Mask */
\r
2870 #define SCU_INTERRUPT_SRRAW_RTC_CTR_Pos 24 /*!< SCU_INTERRUPT SRRAW: RTC_CTR Position */
\r
2871 #define SCU_INTERRUPT_SRRAW_RTC_CTR_Msk (0x01UL << SCU_INTERRUPT_SRRAW_RTC_CTR_Pos) /*!< SCU_INTERRUPT SRRAW: RTC_CTR Mask */
\r
2872 #define SCU_INTERRUPT_SRRAW_RTC_ATIM0_Pos 25 /*!< SCU_INTERRUPT SRRAW: RTC_ATIM0 Position */
\r
2873 #define SCU_INTERRUPT_SRRAW_RTC_ATIM0_Msk (0x01UL << SCU_INTERRUPT_SRRAW_RTC_ATIM0_Pos) /*!< SCU_INTERRUPT SRRAW: RTC_ATIM0 Mask */
\r
2874 #define SCU_INTERRUPT_SRRAW_RTC_ATIM1_Pos 26 /*!< SCU_INTERRUPT SRRAW: RTC_ATIM1 Position */
\r
2875 #define SCU_INTERRUPT_SRRAW_RTC_ATIM1_Msk (0x01UL << SCU_INTERRUPT_SRRAW_RTC_ATIM1_Pos) /*!< SCU_INTERRUPT SRRAW: RTC_ATIM1 Mask */
\r
2876 #define SCU_INTERRUPT_SRRAW_RTC_TIM0_Pos 27 /*!< SCU_INTERRUPT SRRAW: RTC_TIM0 Position */
\r
2877 #define SCU_INTERRUPT_SRRAW_RTC_TIM0_Msk (0x01UL << SCU_INTERRUPT_SRRAW_RTC_TIM0_Pos) /*!< SCU_INTERRUPT SRRAW: RTC_TIM0 Mask */
\r
2878 #define SCU_INTERRUPT_SRRAW_RTC_TIM1_Pos 28 /*!< SCU_INTERRUPT SRRAW: RTC_TIM1 Position */
\r
2879 #define SCU_INTERRUPT_SRRAW_RTC_TIM1_Msk (0x01UL << SCU_INTERRUPT_SRRAW_RTC_TIM1_Pos) /*!< SCU_INTERRUPT SRRAW: RTC_TIM1 Mask */
\r
2880 #define SCU_INTERRUPT_SRRAW_TSE_DONE_Pos 29 /*!< SCU_INTERRUPT SRRAW: TSE_DONE Position */
\r
2881 #define SCU_INTERRUPT_SRRAW_TSE_DONE_Msk (0x01UL << SCU_INTERRUPT_SRRAW_TSE_DONE_Pos) /*!< SCU_INTERRUPT SRRAW: TSE_DONE Mask */
\r
2882 #define SCU_INTERRUPT_SRRAW_TSE_HIGH_Pos 30 /*!< SCU_INTERRUPT SRRAW: TSE_HIGH Position */
\r
2883 #define SCU_INTERRUPT_SRRAW_TSE_HIGH_Msk (0x01UL << SCU_INTERRUPT_SRRAW_TSE_HIGH_Pos) /*!< SCU_INTERRUPT SRRAW: TSE_HIGH Mask */
\r
2884 #define SCU_INTERRUPT_SRRAW_TSE_LOW_Pos 31 /*!< SCU_INTERRUPT SRRAW: TSE_LOW Position */
\r
2885 #define SCU_INTERRUPT_SRRAW_TSE_LOW_Msk (0x01UL << SCU_INTERRUPT_SRRAW_TSE_LOW_Pos) /*!< SCU_INTERRUPT SRRAW: TSE_LOW Mask */
\r
2887 /* ----------------------------- SCU_INTERRUPT_SRMSK ---------------------------- */
\r
2888 #define SCU_INTERRUPT_SRMSK_PRWARN_Pos 0 /*!< SCU_INTERRUPT SRMSK: PRWARN Position */
\r
2889 #define SCU_INTERRUPT_SRMSK_PRWARN_Msk (0x01UL << SCU_INTERRUPT_SRMSK_PRWARN_Pos) /*!< SCU_INTERRUPT SRMSK: PRWARN Mask */
\r
2890 #define SCU_INTERRUPT_SRMSK_VDDPI_Pos 3 /*!< SCU_INTERRUPT SRMSK: VDDPI Position */
\r
2891 #define SCU_INTERRUPT_SRMSK_VDDPI_Msk (0x01UL << SCU_INTERRUPT_SRMSK_VDDPI_Pos) /*!< SCU_INTERRUPT SRMSK: VDDPI Mask */
\r
2892 #define SCU_INTERRUPT_SRMSK_ACMP0I_Pos 4 /*!< SCU_INTERRUPT SRMSK: ACMP0I Position */
\r
2893 #define SCU_INTERRUPT_SRMSK_ACMP0I_Msk (0x01UL << SCU_INTERRUPT_SRMSK_ACMP0I_Pos) /*!< SCU_INTERRUPT SRMSK: ACMP0I Mask */
\r
2894 #define SCU_INTERRUPT_SRMSK_ACMP1I_Pos 5 /*!< SCU_INTERRUPT SRMSK: ACMP1I Position */
\r
2895 #define SCU_INTERRUPT_SRMSK_ACMP1I_Msk (0x01UL << SCU_INTERRUPT_SRMSK_ACMP1I_Pos) /*!< SCU_INTERRUPT SRMSK: ACMP1I Mask */
\r
2896 #define SCU_INTERRUPT_SRMSK_ACMP2I_Pos 6 /*!< SCU_INTERRUPT SRMSK: ACMP2I Position */
\r
2897 #define SCU_INTERRUPT_SRMSK_ACMP2I_Msk (0x01UL << SCU_INTERRUPT_SRMSK_ACMP2I_Pos) /*!< SCU_INTERRUPT SRMSK: ACMP2I Mask */
\r
2898 #define SCU_INTERRUPT_SRMSK_VDROPI_Pos 7 /*!< SCU_INTERRUPT SRMSK: VDROPI Position */
\r
2899 #define SCU_INTERRUPT_SRMSK_VDROPI_Msk (0x01UL << SCU_INTERRUPT_SRMSK_VDROPI_Pos) /*!< SCU_INTERRUPT SRMSK: VDROPI Mask */
\r
2900 #define SCU_INTERRUPT_SRMSK_ORC0I_Pos 8 /*!< SCU_INTERRUPT SRMSK: ORC0I Position */
\r
2901 #define SCU_INTERRUPT_SRMSK_ORC0I_Msk (0x01UL << SCU_INTERRUPT_SRMSK_ORC0I_Pos) /*!< SCU_INTERRUPT SRMSK: ORC0I Mask */
\r
2902 #define SCU_INTERRUPT_SRMSK_ORC1I_Pos 9 /*!< SCU_INTERRUPT SRMSK: ORC1I Position */
\r
2903 #define SCU_INTERRUPT_SRMSK_ORC1I_Msk (0x01UL << SCU_INTERRUPT_SRMSK_ORC1I_Pos) /*!< SCU_INTERRUPT SRMSK: ORC1I Mask */
\r
2904 #define SCU_INTERRUPT_SRMSK_ORC2I_Pos 10 /*!< SCU_INTERRUPT SRMSK: ORC2I Position */
\r
2905 #define SCU_INTERRUPT_SRMSK_ORC2I_Msk (0x01UL << SCU_INTERRUPT_SRMSK_ORC2I_Pos) /*!< SCU_INTERRUPT SRMSK: ORC2I Mask */
\r
2906 #define SCU_INTERRUPT_SRMSK_ORC3I_Pos 11 /*!< SCU_INTERRUPT SRMSK: ORC3I Position */
\r
2907 #define SCU_INTERRUPT_SRMSK_ORC3I_Msk (0x01UL << SCU_INTERRUPT_SRMSK_ORC3I_Pos) /*!< SCU_INTERRUPT SRMSK: ORC3I Mask */
\r
2908 #define SCU_INTERRUPT_SRMSK_ORC4I_Pos 12 /*!< SCU_INTERRUPT SRMSK: ORC4I Position */
\r
2909 #define SCU_INTERRUPT_SRMSK_ORC4I_Msk (0x01UL << SCU_INTERRUPT_SRMSK_ORC4I_Pos) /*!< SCU_INTERRUPT SRMSK: ORC4I Mask */
\r
2910 #define SCU_INTERRUPT_SRMSK_ORC5I_Pos 13 /*!< SCU_INTERRUPT SRMSK: ORC5I Position */
\r
2911 #define SCU_INTERRUPT_SRMSK_ORC5I_Msk (0x01UL << SCU_INTERRUPT_SRMSK_ORC5I_Pos) /*!< SCU_INTERRUPT SRMSK: ORC5I Mask */
\r
2912 #define SCU_INTERRUPT_SRMSK_ORC6I_Pos 14 /*!< SCU_INTERRUPT SRMSK: ORC6I Position */
\r
2913 #define SCU_INTERRUPT_SRMSK_ORC6I_Msk (0x01UL << SCU_INTERRUPT_SRMSK_ORC6I_Pos) /*!< SCU_INTERRUPT SRMSK: ORC6I Mask */
\r
2914 #define SCU_INTERRUPT_SRMSK_ORC7I_Pos 15 /*!< SCU_INTERRUPT SRMSK: ORC7I Position */
\r
2915 #define SCU_INTERRUPT_SRMSK_ORC7I_Msk (0x01UL << SCU_INTERRUPT_SRMSK_ORC7I_Pos) /*!< SCU_INTERRUPT SRMSK: ORC7I Mask */
\r
2916 #define SCU_INTERRUPT_SRMSK_LOCI_Pos 16 /*!< SCU_INTERRUPT SRMSK: LOCI Position */
\r
2917 #define SCU_INTERRUPT_SRMSK_LOCI_Msk (0x01UL << SCU_INTERRUPT_SRMSK_LOCI_Pos) /*!< SCU_INTERRUPT SRMSK: LOCI Mask */
\r
2918 #define SCU_INTERRUPT_SRMSK_PESRAMI_Pos 17 /*!< SCU_INTERRUPT SRMSK: PESRAMI Position */
\r
2919 #define SCU_INTERRUPT_SRMSK_PESRAMI_Msk (0x01UL << SCU_INTERRUPT_SRMSK_PESRAMI_Pos) /*!< SCU_INTERRUPT SRMSK: PESRAMI Mask */
\r
2920 #define SCU_INTERRUPT_SRMSK_PEU0I_Pos 18 /*!< SCU_INTERRUPT SRMSK: PEU0I Position */
\r
2921 #define SCU_INTERRUPT_SRMSK_PEU0I_Msk (0x01UL << SCU_INTERRUPT_SRMSK_PEU0I_Pos) /*!< SCU_INTERRUPT SRMSK: PEU0I Mask */
\r
2922 #define SCU_INTERRUPT_SRMSK_FLECC2I_Pos 19 /*!< SCU_INTERRUPT SRMSK: FLECC2I Position */
\r
2923 #define SCU_INTERRUPT_SRMSK_FLECC2I_Msk (0x01UL << SCU_INTERRUPT_SRMSK_FLECC2I_Pos) /*!< SCU_INTERRUPT SRMSK: FLECC2I Mask */
\r
2924 #define SCU_INTERRUPT_SRMSK_VCLIPI_Pos 21 /*!< SCU_INTERRUPT SRMSK: VCLIPI Position */
\r
2925 #define SCU_INTERRUPT_SRMSK_VCLIPI_Msk (0x01UL << SCU_INTERRUPT_SRMSK_VCLIPI_Pos) /*!< SCU_INTERRUPT SRMSK: VCLIPI Mask */
\r
2926 #define SCU_INTERRUPT_SRMSK_SBYCLKFI_Pos 22 /*!< SCU_INTERRUPT SRMSK: SBYCLKFI Position */
\r
2927 #define SCU_INTERRUPT_SRMSK_SBYCLKFI_Msk (0x01UL << SCU_INTERRUPT_SRMSK_SBYCLKFI_Pos) /*!< SCU_INTERRUPT SRMSK: SBYCLKFI Mask */
\r
2928 #define SCU_INTERRUPT_SRMSK_RTC_CTR_Pos 24 /*!< SCU_INTERRUPT SRMSK: RTC_CTR Position */
\r
2929 #define SCU_INTERRUPT_SRMSK_RTC_CTR_Msk (0x01UL << SCU_INTERRUPT_SRMSK_RTC_CTR_Pos) /*!< SCU_INTERRUPT SRMSK: RTC_CTR Mask */
\r
2930 #define SCU_INTERRUPT_SRMSK_RTC_ATIM0_Pos 25 /*!< SCU_INTERRUPT SRMSK: RTC_ATIM0 Position */
\r
2931 #define SCU_INTERRUPT_SRMSK_RTC_ATIM0_Msk (0x01UL << SCU_INTERRUPT_SRMSK_RTC_ATIM0_Pos) /*!< SCU_INTERRUPT SRMSK: RTC_ATIM0 Mask */
\r
2932 #define SCU_INTERRUPT_SRMSK_RTC_ATIM1_Pos 26 /*!< SCU_INTERRUPT SRMSK: RTC_ATIM1 Position */
\r
2933 #define SCU_INTERRUPT_SRMSK_RTC_ATIM1_Msk (0x01UL << SCU_INTERRUPT_SRMSK_RTC_ATIM1_Pos) /*!< SCU_INTERRUPT SRMSK: RTC_ATIM1 Mask */
\r
2934 #define SCU_INTERRUPT_SRMSK_RTC_TIM0_Pos 27 /*!< SCU_INTERRUPT SRMSK: RTC_TIM0 Position */
\r
2935 #define SCU_INTERRUPT_SRMSK_RTC_TIM0_Msk (0x01UL << SCU_INTERRUPT_SRMSK_RTC_TIM0_Pos) /*!< SCU_INTERRUPT SRMSK: RTC_TIM0 Mask */
\r
2936 #define SCU_INTERRUPT_SRMSK_RTC_TIM1_Pos 28 /*!< SCU_INTERRUPT SRMSK: RTC_TIM1 Position */
\r
2937 #define SCU_INTERRUPT_SRMSK_RTC_TIM1_Msk (0x01UL << SCU_INTERRUPT_SRMSK_RTC_TIM1_Pos) /*!< SCU_INTERRUPT SRMSK: RTC_TIM1 Mask */
\r
2938 #define SCU_INTERRUPT_SRMSK_TSE_DONE_Pos 29 /*!< SCU_INTERRUPT SRMSK: TSE_DONE Position */
\r
2939 #define SCU_INTERRUPT_SRMSK_TSE_DONE_Msk (0x01UL << SCU_INTERRUPT_SRMSK_TSE_DONE_Pos) /*!< SCU_INTERRUPT SRMSK: TSE_DONE Mask */
\r
2940 #define SCU_INTERRUPT_SRMSK_TSE_HIGH_Pos 30 /*!< SCU_INTERRUPT SRMSK: TSE_HIGH Position */
\r
2941 #define SCU_INTERRUPT_SRMSK_TSE_HIGH_Msk (0x01UL << SCU_INTERRUPT_SRMSK_TSE_HIGH_Pos) /*!< SCU_INTERRUPT SRMSK: TSE_HIGH Mask */
\r
2942 #define SCU_INTERRUPT_SRMSK_TSE_LOW_Pos 31 /*!< SCU_INTERRUPT SRMSK: TSE_LOW Position */
\r
2943 #define SCU_INTERRUPT_SRMSK_TSE_LOW_Msk (0x01UL << SCU_INTERRUPT_SRMSK_TSE_LOW_Pos) /*!< SCU_INTERRUPT SRMSK: TSE_LOW Mask */
\r
2945 /* ----------------------------- SCU_INTERRUPT_SRCLR ---------------------------- */
\r
2946 #define SCU_INTERRUPT_SRCLR_PRWARN_Pos 0 /*!< SCU_INTERRUPT SRCLR: PRWARN Position */
\r
2947 #define SCU_INTERRUPT_SRCLR_PRWARN_Msk (0x01UL << SCU_INTERRUPT_SRCLR_PRWARN_Pos) /*!< SCU_INTERRUPT SRCLR: PRWARN Mask */
\r
2948 #define SCU_INTERRUPT_SRCLR_PI_Pos 1 /*!< SCU_INTERRUPT SRCLR: PI Position */
\r
2949 #define SCU_INTERRUPT_SRCLR_PI_Msk (0x01UL << SCU_INTERRUPT_SRCLR_PI_Pos) /*!< SCU_INTERRUPT SRCLR: PI Mask */
\r
2950 #define SCU_INTERRUPT_SRCLR_AI_Pos 2 /*!< SCU_INTERRUPT SRCLR: AI Position */
\r
2951 #define SCU_INTERRUPT_SRCLR_AI_Msk (0x01UL << SCU_INTERRUPT_SRCLR_AI_Pos) /*!< SCU_INTERRUPT SRCLR: AI Mask */
\r
2952 #define SCU_INTERRUPT_SRCLR_VDDPI_Pos 3 /*!< SCU_INTERRUPT SRCLR: VDDPI Position */
\r
2953 #define SCU_INTERRUPT_SRCLR_VDDPI_Msk (0x01UL << SCU_INTERRUPT_SRCLR_VDDPI_Pos) /*!< SCU_INTERRUPT SRCLR: VDDPI Mask */
\r
2954 #define SCU_INTERRUPT_SRCLR_ACMP0I_Pos 4 /*!< SCU_INTERRUPT SRCLR: ACMP0I Position */
\r
2955 #define SCU_INTERRUPT_SRCLR_ACMP0I_Msk (0x01UL << SCU_INTERRUPT_SRCLR_ACMP0I_Pos) /*!< SCU_INTERRUPT SRCLR: ACMP0I Mask */
\r
2956 #define SCU_INTERRUPT_SRCLR_ACMP1I_Pos 5 /*!< SCU_INTERRUPT SRCLR: ACMP1I Position */
\r
2957 #define SCU_INTERRUPT_SRCLR_ACMP1I_Msk (0x01UL << SCU_INTERRUPT_SRCLR_ACMP1I_Pos) /*!< SCU_INTERRUPT SRCLR: ACMP1I Mask */
\r
2958 #define SCU_INTERRUPT_SRCLR_ACMP2I_Pos 6 /*!< SCU_INTERRUPT SRCLR: ACMP2I Position */
\r
2959 #define SCU_INTERRUPT_SRCLR_ACMP2I_Msk (0x01UL << SCU_INTERRUPT_SRCLR_ACMP2I_Pos) /*!< SCU_INTERRUPT SRCLR: ACMP2I Mask */
\r
2960 #define SCU_INTERRUPT_SRCLR_VDROPI_Pos 7 /*!< SCU_INTERRUPT SRCLR: VDROPI Position */
\r
2961 #define SCU_INTERRUPT_SRCLR_VDROPI_Msk (0x01UL << SCU_INTERRUPT_SRCLR_VDROPI_Pos) /*!< SCU_INTERRUPT SRCLR: VDROPI Mask */
\r
2962 #define SCU_INTERRUPT_SRCLR_ORC0I_Pos 8 /*!< SCU_INTERRUPT SRCLR: ORC0I Position */
\r
2963 #define SCU_INTERRUPT_SRCLR_ORC0I_Msk (0x01UL << SCU_INTERRUPT_SRCLR_ORC0I_Pos) /*!< SCU_INTERRUPT SRCLR: ORC0I Mask */
\r
2964 #define SCU_INTERRUPT_SRCLR_ORC1I_Pos 9 /*!< SCU_INTERRUPT SRCLR: ORC1I Position */
\r
2965 #define SCU_INTERRUPT_SRCLR_ORC1I_Msk (0x01UL << SCU_INTERRUPT_SRCLR_ORC1I_Pos) /*!< SCU_INTERRUPT SRCLR: ORC1I Mask */
\r
2966 #define SCU_INTERRUPT_SRCLR_ORC2I_Pos 10 /*!< SCU_INTERRUPT SRCLR: ORC2I Position */
\r
2967 #define SCU_INTERRUPT_SRCLR_ORC2I_Msk (0x01UL << SCU_INTERRUPT_SRCLR_ORC2I_Pos) /*!< SCU_INTERRUPT SRCLR: ORC2I Mask */
\r
2968 #define SCU_INTERRUPT_SRCLR_ORC3I_Pos 11 /*!< SCU_INTERRUPT SRCLR: ORC3I Position */
\r
2969 #define SCU_INTERRUPT_SRCLR_ORC3I_Msk (0x01UL << SCU_INTERRUPT_SRCLR_ORC3I_Pos) /*!< SCU_INTERRUPT SRCLR: ORC3I Mask */
\r
2970 #define SCU_INTERRUPT_SRCLR_ORC4I_Pos 12 /*!< SCU_INTERRUPT SRCLR: ORC4I Position */
\r
2971 #define SCU_INTERRUPT_SRCLR_ORC4I_Msk (0x01UL << SCU_INTERRUPT_SRCLR_ORC4I_Pos) /*!< SCU_INTERRUPT SRCLR: ORC4I Mask */
\r
2972 #define SCU_INTERRUPT_SRCLR_ORC5I_Pos 13 /*!< SCU_INTERRUPT SRCLR: ORC5I Position */
\r
2973 #define SCU_INTERRUPT_SRCLR_ORC5I_Msk (0x01UL << SCU_INTERRUPT_SRCLR_ORC5I_Pos) /*!< SCU_INTERRUPT SRCLR: ORC5I Mask */
\r
2974 #define SCU_INTERRUPT_SRCLR_ORC6I_Pos 14 /*!< SCU_INTERRUPT SRCLR: ORC6I Position */
\r
2975 #define SCU_INTERRUPT_SRCLR_ORC6I_Msk (0x01UL << SCU_INTERRUPT_SRCLR_ORC6I_Pos) /*!< SCU_INTERRUPT SRCLR: ORC6I Mask */
\r
2976 #define SCU_INTERRUPT_SRCLR_ORC7I_Pos 15 /*!< SCU_INTERRUPT SRCLR: ORC7I Position */
\r
2977 #define SCU_INTERRUPT_SRCLR_ORC7I_Msk (0x01UL << SCU_INTERRUPT_SRCLR_ORC7I_Pos) /*!< SCU_INTERRUPT SRCLR: ORC7I Mask */
\r
2978 #define SCU_INTERRUPT_SRCLR_LOCI_Pos 16 /*!< SCU_INTERRUPT SRCLR: LOCI Position */
\r
2979 #define SCU_INTERRUPT_SRCLR_LOCI_Msk (0x01UL << SCU_INTERRUPT_SRCLR_LOCI_Pos) /*!< SCU_INTERRUPT SRCLR: LOCI Mask */
\r
2980 #define SCU_INTERRUPT_SRCLR_PESRAMI_Pos 17 /*!< SCU_INTERRUPT SRCLR: PESRAMI Position */
\r
2981 #define SCU_INTERRUPT_SRCLR_PESRAMI_Msk (0x01UL << SCU_INTERRUPT_SRCLR_PESRAMI_Pos) /*!< SCU_INTERRUPT SRCLR: PESRAMI Mask */
\r
2982 #define SCU_INTERRUPT_SRCLR_PEU0I_Pos 18 /*!< SCU_INTERRUPT SRCLR: PEU0I Position */
\r
2983 #define SCU_INTERRUPT_SRCLR_PEU0I_Msk (0x01UL << SCU_INTERRUPT_SRCLR_PEU0I_Pos) /*!< SCU_INTERRUPT SRCLR: PEU0I Mask */
\r
2984 #define SCU_INTERRUPT_SRCLR_FLECC2I_Pos 19 /*!< SCU_INTERRUPT SRCLR: FLECC2I Position */
\r
2985 #define SCU_INTERRUPT_SRCLR_FLECC2I_Msk (0x01UL << SCU_INTERRUPT_SRCLR_FLECC2I_Pos) /*!< SCU_INTERRUPT SRCLR: FLECC2I Mask */
\r
2986 #define SCU_INTERRUPT_SRCLR_FLCMPLTI_Pos 20 /*!< SCU_INTERRUPT SRCLR: FLCMPLTI Position */
\r
2987 #define SCU_INTERRUPT_SRCLR_FLCMPLTI_Msk (0x01UL << SCU_INTERRUPT_SRCLR_FLCMPLTI_Pos) /*!< SCU_INTERRUPT SRCLR: FLCMPLTI Mask */
\r
2988 #define SCU_INTERRUPT_SRCLR_VCLIPI_Pos 21 /*!< SCU_INTERRUPT SRCLR: VCLIPI Position */
\r
2989 #define SCU_INTERRUPT_SRCLR_VCLIPI_Msk (0x01UL << SCU_INTERRUPT_SRCLR_VCLIPI_Pos) /*!< SCU_INTERRUPT SRCLR: VCLIPI Mask */
\r
2990 #define SCU_INTERRUPT_SRCLR_SBYCLKFI_Pos 22 /*!< SCU_INTERRUPT SRCLR: SBYCLKFI Position */
\r
2991 #define SCU_INTERRUPT_SRCLR_SBYCLKFI_Msk (0x01UL << SCU_INTERRUPT_SRCLR_SBYCLKFI_Pos) /*!< SCU_INTERRUPT SRCLR: SBYCLKFI Mask */
\r
2992 #define SCU_INTERRUPT_SRCLR_RTC_CTR_Pos 24 /*!< SCU_INTERRUPT SRCLR: RTC_CTR Position */
\r
2993 #define SCU_INTERRUPT_SRCLR_RTC_CTR_Msk (0x01UL << SCU_INTERRUPT_SRCLR_RTC_CTR_Pos) /*!< SCU_INTERRUPT SRCLR: RTC_CTR Mask */
\r
2994 #define SCU_INTERRUPT_SRCLR_RTC_ATIM0_Pos 25 /*!< SCU_INTERRUPT SRCLR: RTC_ATIM0 Position */
\r
2995 #define SCU_INTERRUPT_SRCLR_RTC_ATIM0_Msk (0x01UL << SCU_INTERRUPT_SRCLR_RTC_ATIM0_Pos) /*!< SCU_INTERRUPT SRCLR: RTC_ATIM0 Mask */
\r
2996 #define SCU_INTERRUPT_SRCLR_RTC_ATIM1_Pos 26 /*!< SCU_INTERRUPT SRCLR: RTC_ATIM1 Position */
\r
2997 #define SCU_INTERRUPT_SRCLR_RTC_ATIM1_Msk (0x01UL << SCU_INTERRUPT_SRCLR_RTC_ATIM1_Pos) /*!< SCU_INTERRUPT SRCLR: RTC_ATIM1 Mask */
\r
2998 #define SCU_INTERRUPT_SRCLR_RTC_TIM0_Pos 27 /*!< SCU_INTERRUPT SRCLR: RTC_TIM0 Position */
\r
2999 #define SCU_INTERRUPT_SRCLR_RTC_TIM0_Msk (0x01UL << SCU_INTERRUPT_SRCLR_RTC_TIM0_Pos) /*!< SCU_INTERRUPT SRCLR: RTC_TIM0 Mask */
\r
3000 #define SCU_INTERRUPT_SRCLR_RTC_TIM1_Pos 28 /*!< SCU_INTERRUPT SRCLR: RTC_TIM1 Position */
\r
3001 #define SCU_INTERRUPT_SRCLR_RTC_TIM1_Msk (0x01UL << SCU_INTERRUPT_SRCLR_RTC_TIM1_Pos) /*!< SCU_INTERRUPT SRCLR: RTC_TIM1 Mask */
\r
3002 #define SCU_INTERRUPT_SRCLR_TSE_DONE_Pos 29 /*!< SCU_INTERRUPT SRCLR: TSE_DONE Position */
\r
3003 #define SCU_INTERRUPT_SRCLR_TSE_DONE_Msk (0x01UL << SCU_INTERRUPT_SRCLR_TSE_DONE_Pos) /*!< SCU_INTERRUPT SRCLR: TSE_DONE Mask */
\r
3004 #define SCU_INTERRUPT_SRCLR_TSE_HIGH_Pos 30 /*!< SCU_INTERRUPT SRCLR: TSE_HIGH Position */
\r
3005 #define SCU_INTERRUPT_SRCLR_TSE_HIGH_Msk (0x01UL << SCU_INTERRUPT_SRCLR_TSE_HIGH_Pos) /*!< SCU_INTERRUPT SRCLR: TSE_HIGH Mask */
\r
3006 #define SCU_INTERRUPT_SRCLR_TSE_LOW_Pos 31 /*!< SCU_INTERRUPT SRCLR: TSE_LOW Position */
\r
3007 #define SCU_INTERRUPT_SRCLR_TSE_LOW_Msk (0x01UL << SCU_INTERRUPT_SRCLR_TSE_LOW_Pos) /*!< SCU_INTERRUPT SRCLR: TSE_LOW Mask */
\r
3009 /* ----------------------------- SCU_INTERRUPT_SRSET ---------------------------- */
\r
3010 #define SCU_INTERRUPT_SRSET_PRWARN_Pos 0 /*!< SCU_INTERRUPT SRSET: PRWARN Position */
\r
3011 #define SCU_INTERRUPT_SRSET_PRWARN_Msk (0x01UL << SCU_INTERRUPT_SRSET_PRWARN_Pos) /*!< SCU_INTERRUPT SRSET: PRWARN Mask */
\r
3012 #define SCU_INTERRUPT_SRSET_PI_Pos 1 /*!< SCU_INTERRUPT SRSET: PI Position */
\r
3013 #define SCU_INTERRUPT_SRSET_PI_Msk (0x01UL << SCU_INTERRUPT_SRSET_PI_Pos) /*!< SCU_INTERRUPT SRSET: PI Mask */
\r
3014 #define SCU_INTERRUPT_SRSET_AI_Pos 2 /*!< SCU_INTERRUPT SRSET: AI Position */
\r
3015 #define SCU_INTERRUPT_SRSET_AI_Msk (0x01UL << SCU_INTERRUPT_SRSET_AI_Pos) /*!< SCU_INTERRUPT SRSET: AI Mask */
\r
3016 #define SCU_INTERRUPT_SRSET_VDDPI_Pos 3 /*!< SCU_INTERRUPT SRSET: VDDPI Position */
\r
3017 #define SCU_INTERRUPT_SRSET_VDDPI_Msk (0x01UL << SCU_INTERRUPT_SRSET_VDDPI_Pos) /*!< SCU_INTERRUPT SRSET: VDDPI Mask */
\r
3018 #define SCU_INTERRUPT_SRSET_ACMP0I_Pos 4 /*!< SCU_INTERRUPT SRSET: ACMP0I Position */
\r
3019 #define SCU_INTERRUPT_SRSET_ACMP0I_Msk (0x01UL << SCU_INTERRUPT_SRSET_ACMP0I_Pos) /*!< SCU_INTERRUPT SRSET: ACMP0I Mask */
\r
3020 #define SCU_INTERRUPT_SRSET_ACMP1I_Pos 5 /*!< SCU_INTERRUPT SRSET: ACMP1I Position */
\r
3021 #define SCU_INTERRUPT_SRSET_ACMP1I_Msk (0x01UL << SCU_INTERRUPT_SRSET_ACMP1I_Pos) /*!< SCU_INTERRUPT SRSET: ACMP1I Mask */
\r
3022 #define SCU_INTERRUPT_SRSET_ACMP2I_Pos 6 /*!< SCU_INTERRUPT SRSET: ACMP2I Position */
\r
3023 #define SCU_INTERRUPT_SRSET_ACMP2I_Msk (0x01UL << SCU_INTERRUPT_SRSET_ACMP2I_Pos) /*!< SCU_INTERRUPT SRSET: ACMP2I Mask */
\r
3024 #define SCU_INTERRUPT_SRSET_VDROPI_Pos 7 /*!< SCU_INTERRUPT SRSET: VDROPI Position */
\r
3025 #define SCU_INTERRUPT_SRSET_VDROPI_Msk (0x01UL << SCU_INTERRUPT_SRSET_VDROPI_Pos) /*!< SCU_INTERRUPT SRSET: VDROPI Mask */
\r
3026 #define SCU_INTERRUPT_SRSET_ORC0I_Pos 8 /*!< SCU_INTERRUPT SRSET: ORC0I Position */
\r
3027 #define SCU_INTERRUPT_SRSET_ORC0I_Msk (0x01UL << SCU_INTERRUPT_SRSET_ORC0I_Pos) /*!< SCU_INTERRUPT SRSET: ORC0I Mask */
\r
3028 #define SCU_INTERRUPT_SRSET_ORC1I_Pos 9 /*!< SCU_INTERRUPT SRSET: ORC1I Position */
\r
3029 #define SCU_INTERRUPT_SRSET_ORC1I_Msk (0x01UL << SCU_INTERRUPT_SRSET_ORC1I_Pos) /*!< SCU_INTERRUPT SRSET: ORC1I Mask */
\r
3030 #define SCU_INTERRUPT_SRSET_ORC2I_Pos 10 /*!< SCU_INTERRUPT SRSET: ORC2I Position */
\r
3031 #define SCU_INTERRUPT_SRSET_ORC2I_Msk (0x01UL << SCU_INTERRUPT_SRSET_ORC2I_Pos) /*!< SCU_INTERRUPT SRSET: ORC2I Mask */
\r
3032 #define SCU_INTERRUPT_SRSET_ORC3I_Pos 11 /*!< SCU_INTERRUPT SRSET: ORC3I Position */
\r
3033 #define SCU_INTERRUPT_SRSET_ORC3I_Msk (0x01UL << SCU_INTERRUPT_SRSET_ORC3I_Pos) /*!< SCU_INTERRUPT SRSET: ORC3I Mask */
\r
3034 #define SCU_INTERRUPT_SRSET_ORC4I_Pos 12 /*!< SCU_INTERRUPT SRSET: ORC4I Position */
\r
3035 #define SCU_INTERRUPT_SRSET_ORC4I_Msk (0x01UL << SCU_INTERRUPT_SRSET_ORC4I_Pos) /*!< SCU_INTERRUPT SRSET: ORC4I Mask */
\r
3036 #define SCU_INTERRUPT_SRSET_ORC5I_Pos 13 /*!< SCU_INTERRUPT SRSET: ORC5I Position */
\r
3037 #define SCU_INTERRUPT_SRSET_ORC5I_Msk (0x01UL << SCU_INTERRUPT_SRSET_ORC5I_Pos) /*!< SCU_INTERRUPT SRSET: ORC5I Mask */
\r
3038 #define SCU_INTERRUPT_SRSET_ORC6I_Pos 14 /*!< SCU_INTERRUPT SRSET: ORC6I Position */
\r
3039 #define SCU_INTERRUPT_SRSET_ORC6I_Msk (0x01UL << SCU_INTERRUPT_SRSET_ORC6I_Pos) /*!< SCU_INTERRUPT SRSET: ORC6I Mask */
\r
3040 #define SCU_INTERRUPT_SRSET_ORC7I_Pos 15 /*!< SCU_INTERRUPT SRSET: ORC7I Position */
\r
3041 #define SCU_INTERRUPT_SRSET_ORC7I_Msk (0x01UL << SCU_INTERRUPT_SRSET_ORC7I_Pos) /*!< SCU_INTERRUPT SRSET: ORC7I Mask */
\r
3042 #define SCU_INTERRUPT_SRSET_LOCI_Pos 16 /*!< SCU_INTERRUPT SRSET: LOCI Position */
\r
3043 #define SCU_INTERRUPT_SRSET_LOCI_Msk (0x01UL << SCU_INTERRUPT_SRSET_LOCI_Pos) /*!< SCU_INTERRUPT SRSET: LOCI Mask */
\r
3044 #define SCU_INTERRUPT_SRSET_PESRAMI_Pos 17 /*!< SCU_INTERRUPT SRSET: PESRAMI Position */
\r
3045 #define SCU_INTERRUPT_SRSET_PESRAMI_Msk (0x01UL << SCU_INTERRUPT_SRSET_PESRAMI_Pos) /*!< SCU_INTERRUPT SRSET: PESRAMI Mask */
\r
3046 #define SCU_INTERRUPT_SRSET_PEU0I_Pos 18 /*!< SCU_INTERRUPT SRSET: PEU0I Position */
\r
3047 #define SCU_INTERRUPT_SRSET_PEU0I_Msk (0x01UL << SCU_INTERRUPT_SRSET_PEU0I_Pos) /*!< SCU_INTERRUPT SRSET: PEU0I Mask */
\r
3048 #define SCU_INTERRUPT_SRSET_FLECC2I_Pos 19 /*!< SCU_INTERRUPT SRSET: FLECC2I Position */
\r
3049 #define SCU_INTERRUPT_SRSET_FLECC2I_Msk (0x01UL << SCU_INTERRUPT_SRSET_FLECC2I_Pos) /*!< SCU_INTERRUPT SRSET: FLECC2I Mask */
\r
3050 #define SCU_INTERRUPT_SRSET_FLCMPLTI_Pos 20 /*!< SCU_INTERRUPT SRSET: FLCMPLTI Position */
\r
3051 #define SCU_INTERRUPT_SRSET_FLCMPLTI_Msk (0x01UL << SCU_INTERRUPT_SRSET_FLCMPLTI_Pos) /*!< SCU_INTERRUPT SRSET: FLCMPLTI Mask */
\r
3052 #define SCU_INTERRUPT_SRSET_VCLIPI_Pos 21 /*!< SCU_INTERRUPT SRSET: VCLIPI Position */
\r
3053 #define SCU_INTERRUPT_SRSET_VCLIPI_Msk (0x01UL << SCU_INTERRUPT_SRSET_VCLIPI_Pos) /*!< SCU_INTERRUPT SRSET: VCLIPI Mask */
\r
3054 #define SCU_INTERRUPT_SRSET_SBYCLKFI_Pos 22 /*!< SCU_INTERRUPT SRSET: SBYCLKFI Position */
\r
3055 #define SCU_INTERRUPT_SRSET_SBYCLKFI_Msk (0x01UL << SCU_INTERRUPT_SRSET_SBYCLKFI_Pos) /*!< SCU_INTERRUPT SRSET: SBYCLKFI Mask */
\r
3056 #define SCU_INTERRUPT_SRSET_RTC_CTR_Pos 24 /*!< SCU_INTERRUPT SRSET: RTC_CTR Position */
\r
3057 #define SCU_INTERRUPT_SRSET_RTC_CTR_Msk (0x01UL << SCU_INTERRUPT_SRSET_RTC_CTR_Pos) /*!< SCU_INTERRUPT SRSET: RTC_CTR Mask */
\r
3058 #define SCU_INTERRUPT_SRSET_RTC_ATIM0_Pos 25 /*!< SCU_INTERRUPT SRSET: RTC_ATIM0 Position */
\r
3059 #define SCU_INTERRUPT_SRSET_RTC_ATIM0_Msk (0x01UL << SCU_INTERRUPT_SRSET_RTC_ATIM0_Pos) /*!< SCU_INTERRUPT SRSET: RTC_ATIM0 Mask */
\r
3060 #define SCU_INTERRUPT_SRSET_RTC_ATIM1_Pos 26 /*!< SCU_INTERRUPT SRSET: RTC_ATIM1 Position */
\r
3061 #define SCU_INTERRUPT_SRSET_RTC_ATIM1_Msk (0x01UL << SCU_INTERRUPT_SRSET_RTC_ATIM1_Pos) /*!< SCU_INTERRUPT SRSET: RTC_ATIM1 Mask */
\r
3062 #define SCU_INTERRUPT_SRSET_RTC_TIM0_Pos 27 /*!< SCU_INTERRUPT SRSET: RTC_TIM0 Position */
\r
3063 #define SCU_INTERRUPT_SRSET_RTC_TIM0_Msk (0x01UL << SCU_INTERRUPT_SRSET_RTC_TIM0_Pos) /*!< SCU_INTERRUPT SRSET: RTC_TIM0 Mask */
\r
3064 #define SCU_INTERRUPT_SRSET_RTC_TIM1_Pos 28 /*!< SCU_INTERRUPT SRSET: RTC_TIM1 Position */
\r
3065 #define SCU_INTERRUPT_SRSET_RTC_TIM1_Msk (0x01UL << SCU_INTERRUPT_SRSET_RTC_TIM1_Pos) /*!< SCU_INTERRUPT SRSET: RTC_TIM1 Mask */
\r
3066 #define SCU_INTERRUPT_SRSET_TSE_DONE_Pos 29 /*!< SCU_INTERRUPT SRSET: TSE_DONE Position */
\r
3067 #define SCU_INTERRUPT_SRSET_TSE_DONE_Msk (0x01UL << SCU_INTERRUPT_SRSET_TSE_DONE_Pos) /*!< SCU_INTERRUPT SRSET: TSE_DONE Mask */
\r
3068 #define SCU_INTERRUPT_SRSET_TSE_HIGH_Pos 30 /*!< SCU_INTERRUPT SRSET: TSE_HIGH Position */
\r
3069 #define SCU_INTERRUPT_SRSET_TSE_HIGH_Msk (0x01UL << SCU_INTERRUPT_SRSET_TSE_HIGH_Pos) /*!< SCU_INTERRUPT SRSET: TSE_HIGH Mask */
\r
3070 #define SCU_INTERRUPT_SRSET_TSE_LOW_Pos 31 /*!< SCU_INTERRUPT SRSET: TSE_LOW Position */
\r
3071 #define SCU_INTERRUPT_SRSET_TSE_LOW_Msk (0x01UL << SCU_INTERRUPT_SRSET_TSE_LOW_Pos) /*!< SCU_INTERRUPT SRSET: TSE_LOW Mask */
\r
3074 /* ================================================================================ */
\r
3075 /* ================ struct 'SCU_POWER' Position & Mask ================ */
\r
3076 /* ================================================================================ */
\r
3079 /* ------------------------------- SCU_POWER_VDESR ------------------------------ */
\r
3080 #define SCU_POWER_VDESR_VCLIP_Pos 0 /*!< SCU_POWER VDESR: VCLIP Position */
\r
3081 #define SCU_POWER_VDESR_VCLIP_Msk (0x01UL << SCU_POWER_VDESR_VCLIP_Pos) /*!< SCU_POWER VDESR: VCLIP Mask */
\r
3082 #define SCU_POWER_VDESR_VDDPPW_Pos 1 /*!< SCU_POWER VDESR: VDDPPW Position */
\r
3083 #define SCU_POWER_VDESR_VDDPPW_Msk (0x01UL << SCU_POWER_VDESR_VDDPPW_Pos) /*!< SCU_POWER VDESR: VDDPPW Mask */
\r
3086 /* ================================================================================ */
\r
3087 /* ================ struct 'SCU_CLK' Position & Mask ================ */
\r
3088 /* ================================================================================ */
\r
3091 /* -------------------------------- SCU_CLK_CLKCR ------------------------------- */
\r
3092 #define SCU_CLK_CLKCR_FDIV_Pos 0 /*!< SCU_CLK CLKCR: FDIV Position */
\r
3093 #define SCU_CLK_CLKCR_FDIV_Msk (0x000000ffUL << SCU_CLK_CLKCR_FDIV_Pos) /*!< SCU_CLK CLKCR: FDIV Mask */
\r
3094 #define SCU_CLK_CLKCR_IDIV_Pos 8 /*!< SCU_CLK CLKCR: IDIV Position */
\r
3095 #define SCU_CLK_CLKCR_IDIV_Msk (0x000000ffUL << SCU_CLK_CLKCR_IDIV_Pos) /*!< SCU_CLK CLKCR: IDIV Mask */
\r
3096 #define SCU_CLK_CLKCR_PCLKSEL_Pos 16 /*!< SCU_CLK CLKCR: PCLKSEL Position */
\r
3097 #define SCU_CLK_CLKCR_PCLKSEL_Msk (0x01UL << SCU_CLK_CLKCR_PCLKSEL_Pos) /*!< SCU_CLK CLKCR: PCLKSEL Mask */
\r
3098 #define SCU_CLK_CLKCR_RTCCLKSEL_Pos 17 /*!< SCU_CLK CLKCR: RTCCLKSEL Position */
\r
3099 #define SCU_CLK_CLKCR_RTCCLKSEL_Msk (0x07UL << SCU_CLK_CLKCR_RTCCLKSEL_Pos) /*!< SCU_CLK CLKCR: RTCCLKSEL Mask */
\r
3100 #define SCU_CLK_CLKCR_CNTADJ_Pos 20 /*!< SCU_CLK CLKCR: CNTADJ Position */
\r
3101 #define SCU_CLK_CLKCR_CNTADJ_Msk (0x000003ffUL << SCU_CLK_CLKCR_CNTADJ_Pos) /*!< SCU_CLK CLKCR: CNTADJ Mask */
\r
3102 #define SCU_CLK_CLKCR_VDDC2LOW_Pos 30 /*!< SCU_CLK CLKCR: VDDC2LOW Position */
\r
3103 #define SCU_CLK_CLKCR_VDDC2LOW_Msk (0x01UL << SCU_CLK_CLKCR_VDDC2LOW_Pos) /*!< SCU_CLK CLKCR: VDDC2LOW Mask */
\r
3104 #define SCU_CLK_CLKCR_VDDC2HIGH_Pos 31 /*!< SCU_CLK CLKCR: VDDC2HIGH Position */
\r
3105 #define SCU_CLK_CLKCR_VDDC2HIGH_Msk (0x01UL << SCU_CLK_CLKCR_VDDC2HIGH_Pos) /*!< SCU_CLK CLKCR: VDDC2HIGH Mask */
\r
3107 /* ------------------------------- SCU_CLK_PWRSVCR ------------------------------ */
\r
3108 #define SCU_CLK_PWRSVCR_FPD_Pos 0 /*!< SCU_CLK PWRSVCR: FPD Position */
\r
3109 #define SCU_CLK_PWRSVCR_FPD_Msk (0x01UL << SCU_CLK_PWRSVCR_FPD_Pos) /*!< SCU_CLK PWRSVCR: FPD Mask */
\r
3111 /* ------------------------------ SCU_CLK_CGATSTAT0 ----------------------------- */
\r
3112 #define SCU_CLK_CGATSTAT0_VADC_Pos 0 /*!< SCU_CLK CGATSTAT0: VADC Position */
\r
3113 #define SCU_CLK_CGATSTAT0_VADC_Msk (0x01UL << SCU_CLK_CGATSTAT0_VADC_Pos) /*!< SCU_CLK CGATSTAT0: VADC Mask */
\r
3114 #define SCU_CLK_CGATSTAT0_CCU80_Pos 1 /*!< SCU_CLK CGATSTAT0: CCU80 Position */
\r
3115 #define SCU_CLK_CGATSTAT0_CCU80_Msk (0x01UL << SCU_CLK_CGATSTAT0_CCU80_Pos) /*!< SCU_CLK CGATSTAT0: CCU80 Mask */
\r
3116 #define SCU_CLK_CGATSTAT0_CCU40_Pos 2 /*!< SCU_CLK CGATSTAT0: CCU40 Position */
\r
3117 #define SCU_CLK_CGATSTAT0_CCU40_Msk (0x01UL << SCU_CLK_CGATSTAT0_CCU40_Pos) /*!< SCU_CLK CGATSTAT0: CCU40 Mask */
\r
3118 #define SCU_CLK_CGATSTAT0_USIC0_Pos 3 /*!< SCU_CLK CGATSTAT0: USIC0 Position */
\r
3119 #define SCU_CLK_CGATSTAT0_USIC0_Msk (0x01UL << SCU_CLK_CGATSTAT0_USIC0_Pos) /*!< SCU_CLK CGATSTAT0: USIC0 Mask */
\r
3120 #define SCU_CLK_CGATSTAT0_BCCU0_Pos 4 /*!< SCU_CLK CGATSTAT0: BCCU0 Position */
\r
3121 #define SCU_CLK_CGATSTAT0_BCCU0_Msk (0x01UL << SCU_CLK_CGATSTAT0_BCCU0_Pos) /*!< SCU_CLK CGATSTAT0: BCCU0 Mask */
\r
3122 #define SCU_CLK_CGATSTAT0_POSIF0_Pos 7 /*!< SCU_CLK CGATSTAT0: POSIF0 Position */
\r
3123 #define SCU_CLK_CGATSTAT0_POSIF0_Msk (0x01UL << SCU_CLK_CGATSTAT0_POSIF0_Pos) /*!< SCU_CLK CGATSTAT0: POSIF0 Mask */
\r
3124 #define SCU_CLK_CGATSTAT0_MATH_Pos 8 /*!< SCU_CLK CGATSTAT0: MATH Position */
\r
3125 #define SCU_CLK_CGATSTAT0_MATH_Msk (0x01UL << SCU_CLK_CGATSTAT0_MATH_Pos) /*!< SCU_CLK CGATSTAT0: MATH Mask */
\r
3126 #define SCU_CLK_CGATSTAT0_WDT_Pos 9 /*!< SCU_CLK CGATSTAT0: WDT Position */
\r
3127 #define SCU_CLK_CGATSTAT0_WDT_Msk (0x01UL << SCU_CLK_CGATSTAT0_WDT_Pos) /*!< SCU_CLK CGATSTAT0: WDT Mask */
\r
3128 #define SCU_CLK_CGATSTAT0_RTC_Pos 10 /*!< SCU_CLK CGATSTAT0: RTC Position */
\r
3129 #define SCU_CLK_CGATSTAT0_RTC_Msk (0x01UL << SCU_CLK_CGATSTAT0_RTC_Pos) /*!< SCU_CLK CGATSTAT0: RTC Mask */
\r
3131 /* ------------------------------ SCU_CLK_CGATSET0 ------------------------------ */
\r
3132 #define SCU_CLK_CGATSET0_VADC_Pos 0 /*!< SCU_CLK CGATSET0: VADC Position */
\r
3133 #define SCU_CLK_CGATSET0_VADC_Msk (0x01UL << SCU_CLK_CGATSET0_VADC_Pos) /*!< SCU_CLK CGATSET0: VADC Mask */
\r
3134 #define SCU_CLK_CGATSET0_CCU80_Pos 1 /*!< SCU_CLK CGATSET0: CCU80 Position */
\r
3135 #define SCU_CLK_CGATSET0_CCU80_Msk (0x01UL << SCU_CLK_CGATSET0_CCU80_Pos) /*!< SCU_CLK CGATSET0: CCU80 Mask */
\r
3136 #define SCU_CLK_CGATSET0_CCU40_Pos 2 /*!< SCU_CLK CGATSET0: CCU40 Position */
\r
3137 #define SCU_CLK_CGATSET0_CCU40_Msk (0x01UL << SCU_CLK_CGATSET0_CCU40_Pos) /*!< SCU_CLK CGATSET0: CCU40 Mask */
\r
3138 #define SCU_CLK_CGATSET0_USIC0_Pos 3 /*!< SCU_CLK CGATSET0: USIC0 Position */
\r
3139 #define SCU_CLK_CGATSET0_USIC0_Msk (0x01UL << SCU_CLK_CGATSET0_USIC0_Pos) /*!< SCU_CLK CGATSET0: USIC0 Mask */
\r
3140 #define SCU_CLK_CGATSET0_BCCU0_Pos 4 /*!< SCU_CLK CGATSET0: BCCU0 Position */
\r
3141 #define SCU_CLK_CGATSET0_BCCU0_Msk (0x01UL << SCU_CLK_CGATSET0_BCCU0_Pos) /*!< SCU_CLK CGATSET0: BCCU0 Mask */
\r
3142 #define SCU_CLK_CGATSET0_POSIF0_Pos 7 /*!< SCU_CLK CGATSET0: POSIF0 Position */
\r
3143 #define SCU_CLK_CGATSET0_POSIF0_Msk (0x01UL << SCU_CLK_CGATSET0_POSIF0_Pos) /*!< SCU_CLK CGATSET0: POSIF0 Mask */
\r
3144 #define SCU_CLK_CGATSET0_MATH_Pos 8 /*!< SCU_CLK CGATSET0: MATH Position */
\r
3145 #define SCU_CLK_CGATSET0_MATH_Msk (0x01UL << SCU_CLK_CGATSET0_MATH_Pos) /*!< SCU_CLK CGATSET0: MATH Mask */
\r
3146 #define SCU_CLK_CGATSET0_WDT_Pos 9 /*!< SCU_CLK CGATSET0: WDT Position */
\r
3147 #define SCU_CLK_CGATSET0_WDT_Msk (0x01UL << SCU_CLK_CGATSET0_WDT_Pos) /*!< SCU_CLK CGATSET0: WDT Mask */
\r
3148 #define SCU_CLK_CGATSET0_RTC_Pos 10 /*!< SCU_CLK CGATSET0: RTC Position */
\r
3149 #define SCU_CLK_CGATSET0_RTC_Msk (0x01UL << SCU_CLK_CGATSET0_RTC_Pos) /*!< SCU_CLK CGATSET0: RTC Mask */
\r
3151 /* ------------------------------ SCU_CLK_CGATCLR0 ------------------------------ */
\r
3152 #define SCU_CLK_CGATCLR0_VADC_Pos 0 /*!< SCU_CLK CGATCLR0: VADC Position */
\r
3153 #define SCU_CLK_CGATCLR0_VADC_Msk (0x01UL << SCU_CLK_CGATCLR0_VADC_Pos) /*!< SCU_CLK CGATCLR0: VADC Mask */
\r
3154 #define SCU_CLK_CGATCLR0_CCU80_Pos 1 /*!< SCU_CLK CGATCLR0: CCU80 Position */
\r
3155 #define SCU_CLK_CGATCLR0_CCU80_Msk (0x01UL << SCU_CLK_CGATCLR0_CCU80_Pos) /*!< SCU_CLK CGATCLR0: CCU80 Mask */
\r
3156 #define SCU_CLK_CGATCLR0_CCU40_Pos 2 /*!< SCU_CLK CGATCLR0: CCU40 Position */
\r
3157 #define SCU_CLK_CGATCLR0_CCU40_Msk (0x01UL << SCU_CLK_CGATCLR0_CCU40_Pos) /*!< SCU_CLK CGATCLR0: CCU40 Mask */
\r
3158 #define SCU_CLK_CGATCLR0_USIC0_Pos 3 /*!< SCU_CLK CGATCLR0: USIC0 Position */
\r
3159 #define SCU_CLK_CGATCLR0_USIC0_Msk (0x01UL << SCU_CLK_CGATCLR0_USIC0_Pos) /*!< SCU_CLK CGATCLR0: USIC0 Mask */
\r
3160 #define SCU_CLK_CGATCLR0_BCCU0_Pos 4 /*!< SCU_CLK CGATCLR0: BCCU0 Position */
\r
3161 #define SCU_CLK_CGATCLR0_BCCU0_Msk (0x01UL << SCU_CLK_CGATCLR0_BCCU0_Pos) /*!< SCU_CLK CGATCLR0: BCCU0 Mask */
\r
3162 #define SCU_CLK_CGATCLR0_POSIF0_Pos 7 /*!< SCU_CLK CGATCLR0: POSIF0 Position */
\r
3163 #define SCU_CLK_CGATCLR0_POSIF0_Msk (0x01UL << SCU_CLK_CGATCLR0_POSIF0_Pos) /*!< SCU_CLK CGATCLR0: POSIF0 Mask */
\r
3164 #define SCU_CLK_CGATCLR0_MATH_Pos 8 /*!< SCU_CLK CGATCLR0: MATH Position */
\r
3165 #define SCU_CLK_CGATCLR0_MATH_Msk (0x01UL << SCU_CLK_CGATCLR0_MATH_Pos) /*!< SCU_CLK CGATCLR0: MATH Mask */
\r
3166 #define SCU_CLK_CGATCLR0_WDT_Pos 9 /*!< SCU_CLK CGATCLR0: WDT Position */
\r
3167 #define SCU_CLK_CGATCLR0_WDT_Msk (0x01UL << SCU_CLK_CGATCLR0_WDT_Pos) /*!< SCU_CLK CGATCLR0: WDT Mask */
\r
3168 #define SCU_CLK_CGATCLR0_RTC_Pos 10 /*!< SCU_CLK CGATCLR0: RTC Position */
\r
3169 #define SCU_CLK_CGATCLR0_RTC_Msk (0x01UL << SCU_CLK_CGATCLR0_RTC_Pos) /*!< SCU_CLK CGATCLR0: RTC Mask */
\r
3171 /* ------------------------------- SCU_CLK_OSCCSR ------------------------------- */
\r
3172 #define SCU_CLK_OSCCSR_OSC2L_Pos 0 /*!< SCU_CLK OSCCSR: OSC2L Position */
\r
3173 #define SCU_CLK_OSCCSR_OSC2L_Msk (0x01UL << SCU_CLK_OSCCSR_OSC2L_Pos) /*!< SCU_CLK OSCCSR: OSC2L Mask */
\r
3174 #define SCU_CLK_OSCCSR_OSC2H_Pos 1 /*!< SCU_CLK OSCCSR: OSC2H Position */
\r
3175 #define SCU_CLK_OSCCSR_OSC2H_Msk (0x01UL << SCU_CLK_OSCCSR_OSC2H_Pos) /*!< SCU_CLK OSCCSR: OSC2H Mask */
\r
3176 #define SCU_CLK_OSCCSR_OWDRES_Pos 16 /*!< SCU_CLK OSCCSR: OWDRES Position */
\r
3177 #define SCU_CLK_OSCCSR_OWDRES_Msk (0x01UL << SCU_CLK_OSCCSR_OWDRES_Pos) /*!< SCU_CLK OSCCSR: OWDRES Mask */
\r
3178 #define SCU_CLK_OSCCSR_OWDEN_Pos 17 /*!< SCU_CLK OSCCSR: OWDEN Position */
\r
3179 #define SCU_CLK_OSCCSR_OWDEN_Msk (0x01UL << SCU_CLK_OSCCSR_OWDEN_Pos) /*!< SCU_CLK OSCCSR: OWDEN Mask */
\r
3182 /* ================================================================================ */
\r
3183 /* ================ struct 'SCU_RESET' Position & Mask ================ */
\r
3184 /* ================================================================================ */
\r
3187 /* ------------------------------ SCU_RESET_RSTSTAT ----------------------------- */
\r
3188 #define SCU_RESET_RSTSTAT_RSTSTAT_Pos 0 /*!< SCU_RESET RSTSTAT: RSTSTAT Position */
\r
3189 #define SCU_RESET_RSTSTAT_RSTSTAT_Msk (0x000003ffUL << SCU_RESET_RSTSTAT_RSTSTAT_Pos) /*!< SCU_RESET RSTSTAT: RSTSTAT Mask */
\r
3190 #define SCU_RESET_RSTSTAT_LCKEN_Pos 10 /*!< SCU_RESET RSTSTAT: LCKEN Position */
\r
3191 #define SCU_RESET_RSTSTAT_LCKEN_Msk (0x01UL << SCU_RESET_RSTSTAT_LCKEN_Pos) /*!< SCU_RESET RSTSTAT: LCKEN Mask */
\r
3193 /* ------------------------------ SCU_RESET_RSTSET ------------------------------ */
\r
3194 #define SCU_RESET_RSTSET_LCKEN_Pos 10 /*!< SCU_RESET RSTSET: LCKEN Position */
\r
3195 #define SCU_RESET_RSTSET_LCKEN_Msk (0x01UL << SCU_RESET_RSTSET_LCKEN_Pos) /*!< SCU_RESET RSTSET: LCKEN Mask */
\r
3197 /* ------------------------------ SCU_RESET_RSTCLR ------------------------------ */
\r
3198 #define SCU_RESET_RSTCLR_RSCLR_Pos 0 /*!< SCU_RESET RSTCLR: RSCLR Position */
\r
3199 #define SCU_RESET_RSTCLR_RSCLR_Msk (0x01UL << SCU_RESET_RSTCLR_RSCLR_Pos) /*!< SCU_RESET RSTCLR: RSCLR Mask */
\r
3200 #define SCU_RESET_RSTCLR_LCKEN_Pos 10 /*!< SCU_RESET RSTCLR: LCKEN Position */
\r
3201 #define SCU_RESET_RSTCLR_LCKEN_Msk (0x01UL << SCU_RESET_RSTCLR_LCKEN_Pos) /*!< SCU_RESET RSTCLR: LCKEN Mask */
\r
3203 /* ------------------------------ SCU_RESET_RSTCON ------------------------------ */
\r
3204 #define SCU_RESET_RSTCON_ECCRSTEN_Pos 0 /*!< SCU_RESET RSTCON: ECCRSTEN Position */
\r
3205 #define SCU_RESET_RSTCON_ECCRSTEN_Msk (0x01UL << SCU_RESET_RSTCON_ECCRSTEN_Pos) /*!< SCU_RESET RSTCON: ECCRSTEN Mask */
\r
3206 #define SCU_RESET_RSTCON_LOCRSTEN_Pos 1 /*!< SCU_RESET RSTCON: LOCRSTEN Position */
\r
3207 #define SCU_RESET_RSTCON_LOCRSTEN_Msk (0x01UL << SCU_RESET_RSTCON_LOCRSTEN_Pos) /*!< SCU_RESET RSTCON: LOCRSTEN Mask */
\r
3208 #define SCU_RESET_RSTCON_SPERSTEN_Pos 2 /*!< SCU_RESET RSTCON: SPERSTEN Position */
\r
3209 #define SCU_RESET_RSTCON_SPERSTEN_Msk (0x01UL << SCU_RESET_RSTCON_SPERSTEN_Pos) /*!< SCU_RESET RSTCON: SPERSTEN Mask */
\r
3210 #define SCU_RESET_RSTCON_U0PERSTEN_Pos 3 /*!< SCU_RESET RSTCON: U0PERSTEN Position */
\r
3211 #define SCU_RESET_RSTCON_U0PERSTEN_Msk (0x01UL << SCU_RESET_RSTCON_U0PERSTEN_Pos) /*!< SCU_RESET RSTCON: U0PERSTEN Mask */
\r
3212 #define SCU_RESET_RSTCON_MRSTEN_Pos 16 /*!< SCU_RESET RSTCON: MRSTEN Position */
\r
3213 #define SCU_RESET_RSTCON_MRSTEN_Msk (0x01UL << SCU_RESET_RSTCON_MRSTEN_Pos) /*!< SCU_RESET RSTCON: MRSTEN Mask */
\r
3216 /* ================================================================================ */
\r
3217 /* ================ struct 'COMPARATOR' Position & Mask ================ */
\r
3218 /* ================================================================================ */
\r
3221 /* ----------------------------- COMPARATOR_ORCCTRL ----------------------------- */
\r
3222 #define COMPARATOR_ORCCTRL_ENORC0_Pos 0 /*!< COMPARATOR ORCCTRL: ENORC0 Position */
\r
3223 #define COMPARATOR_ORCCTRL_ENORC0_Msk (0x01UL << COMPARATOR_ORCCTRL_ENORC0_Pos) /*!< COMPARATOR ORCCTRL: ENORC0 Mask */
\r
3224 #define COMPARATOR_ORCCTRL_ENORC1_Pos 1 /*!< COMPARATOR ORCCTRL: ENORC1 Position */
\r
3225 #define COMPARATOR_ORCCTRL_ENORC1_Msk (0x01UL << COMPARATOR_ORCCTRL_ENORC1_Pos) /*!< COMPARATOR ORCCTRL: ENORC1 Mask */
\r
3226 #define COMPARATOR_ORCCTRL_ENORC2_Pos 2 /*!< COMPARATOR ORCCTRL: ENORC2 Position */
\r
3227 #define COMPARATOR_ORCCTRL_ENORC2_Msk (0x01UL << COMPARATOR_ORCCTRL_ENORC2_Pos) /*!< COMPARATOR ORCCTRL: ENORC2 Mask */
\r
3228 #define COMPARATOR_ORCCTRL_ENORC3_Pos 3 /*!< COMPARATOR ORCCTRL: ENORC3 Position */
\r
3229 #define COMPARATOR_ORCCTRL_ENORC3_Msk (0x01UL << COMPARATOR_ORCCTRL_ENORC3_Pos) /*!< COMPARATOR ORCCTRL: ENORC3 Mask */
\r
3230 #define COMPARATOR_ORCCTRL_ENORC4_Pos 4 /*!< COMPARATOR ORCCTRL: ENORC4 Position */
\r
3231 #define COMPARATOR_ORCCTRL_ENORC4_Msk (0x01UL << COMPARATOR_ORCCTRL_ENORC4_Pos) /*!< COMPARATOR ORCCTRL: ENORC4 Mask */
\r
3232 #define COMPARATOR_ORCCTRL_ENORC5_Pos 5 /*!< COMPARATOR ORCCTRL: ENORC5 Position */
\r
3233 #define COMPARATOR_ORCCTRL_ENORC5_Msk (0x01UL << COMPARATOR_ORCCTRL_ENORC5_Pos) /*!< COMPARATOR ORCCTRL: ENORC5 Mask */
\r
3234 #define COMPARATOR_ORCCTRL_ENORC6_Pos 6 /*!< COMPARATOR ORCCTRL: ENORC6 Position */
\r
3235 #define COMPARATOR_ORCCTRL_ENORC6_Msk (0x01UL << COMPARATOR_ORCCTRL_ENORC6_Pos) /*!< COMPARATOR ORCCTRL: ENORC6 Mask */
\r
3236 #define COMPARATOR_ORCCTRL_ENORC7_Pos 7 /*!< COMPARATOR ORCCTRL: ENORC7 Position */
\r
3237 #define COMPARATOR_ORCCTRL_ENORC7_Msk (0x01UL << COMPARATOR_ORCCTRL_ENORC7_Pos) /*!< COMPARATOR ORCCTRL: ENORC7 Mask */
\r
3238 #define COMPARATOR_ORCCTRL_CNF0_Pos 16 /*!< COMPARATOR ORCCTRL: CNF0 Position */
\r
3239 #define COMPARATOR_ORCCTRL_CNF0_Msk (0x01UL << COMPARATOR_ORCCTRL_CNF0_Pos) /*!< COMPARATOR ORCCTRL: CNF0 Mask */
\r
3240 #define COMPARATOR_ORCCTRL_CNF1_Pos 17 /*!< COMPARATOR ORCCTRL: CNF1 Position */
\r
3241 #define COMPARATOR_ORCCTRL_CNF1_Msk (0x01UL << COMPARATOR_ORCCTRL_CNF1_Pos) /*!< COMPARATOR ORCCTRL: CNF1 Mask */
\r
3242 #define COMPARATOR_ORCCTRL_CNF2_Pos 18 /*!< COMPARATOR ORCCTRL: CNF2 Position */
\r
3243 #define COMPARATOR_ORCCTRL_CNF2_Msk (0x01UL << COMPARATOR_ORCCTRL_CNF2_Pos) /*!< COMPARATOR ORCCTRL: CNF2 Mask */
\r
3244 #define COMPARATOR_ORCCTRL_CNF3_Pos 19 /*!< COMPARATOR ORCCTRL: CNF3 Position */
\r
3245 #define COMPARATOR_ORCCTRL_CNF3_Msk (0x01UL << COMPARATOR_ORCCTRL_CNF3_Pos) /*!< COMPARATOR ORCCTRL: CNF3 Mask */
\r
3246 #define COMPARATOR_ORCCTRL_CNF4_Pos 20 /*!< COMPARATOR ORCCTRL: CNF4 Position */
\r
3247 #define COMPARATOR_ORCCTRL_CNF4_Msk (0x01UL << COMPARATOR_ORCCTRL_CNF4_Pos) /*!< COMPARATOR ORCCTRL: CNF4 Mask */
\r
3248 #define COMPARATOR_ORCCTRL_CNF5_Pos 21 /*!< COMPARATOR ORCCTRL: CNF5 Position */
\r
3249 #define COMPARATOR_ORCCTRL_CNF5_Msk (0x01UL << COMPARATOR_ORCCTRL_CNF5_Pos) /*!< COMPARATOR ORCCTRL: CNF5 Mask */
\r
3250 #define COMPARATOR_ORCCTRL_CNF6_Pos 22 /*!< COMPARATOR ORCCTRL: CNF6 Position */
\r
3251 #define COMPARATOR_ORCCTRL_CNF6_Msk (0x01UL << COMPARATOR_ORCCTRL_CNF6_Pos) /*!< COMPARATOR ORCCTRL: CNF6 Mask */
\r
3252 #define COMPARATOR_ORCCTRL_CNF7_Pos 23 /*!< COMPARATOR ORCCTRL: CNF7 Position */
\r
3253 #define COMPARATOR_ORCCTRL_CNF7_Msk (0x01UL << COMPARATOR_ORCCTRL_CNF7_Pos) /*!< COMPARATOR ORCCTRL: CNF7 Mask */
\r
3255 /* ----------------------------- COMPARATOR_ANACMP0 ----------------------------- */
\r
3256 #define COMPARATOR_ANACMP0_CMP_EN_Pos 0 /*!< COMPARATOR ANACMP0: CMP_EN Position */
\r
3257 #define COMPARATOR_ANACMP0_CMP_EN_Msk (0x01UL << COMPARATOR_ANACMP0_CMP_EN_Pos) /*!< COMPARATOR ANACMP0: CMP_EN Mask */
\r
3258 #define COMPARATOR_ANACMP0_CMP_FLT_OFF_Pos 1 /*!< COMPARATOR ANACMP0: CMP_FLT_OFF Position */
\r
3259 #define COMPARATOR_ANACMP0_CMP_FLT_OFF_Msk (0x01UL << COMPARATOR_ANACMP0_CMP_FLT_OFF_Pos) /*!< COMPARATOR ANACMP0: CMP_FLT_OFF Mask */
\r
3260 #define COMPARATOR_ANACMP0_CMP_INV_OUT_Pos 3 /*!< COMPARATOR ANACMP0: CMP_INV_OUT Position */
\r
3261 #define COMPARATOR_ANACMP0_CMP_INV_OUT_Msk (0x01UL << COMPARATOR_ANACMP0_CMP_INV_OUT_Pos) /*!< COMPARATOR ANACMP0: CMP_INV_OUT Mask */
\r
3262 #define COMPARATOR_ANACMP0_CMP_HYST_ADJ_Pos 4 /*!< COMPARATOR ANACMP0: CMP_HYST_ADJ Position */
\r
3263 #define COMPARATOR_ANACMP0_CMP_HYST_ADJ_Msk (0x03UL << COMPARATOR_ANACMP0_CMP_HYST_ADJ_Pos) /*!< COMPARATOR ANACMP0: CMP_HYST_ADJ Mask */
\r
3264 #define COMPARATOR_ANACMP0_ACMP0_SEL_Pos 6 /*!< COMPARATOR ANACMP0: ACMP0_SEL Position */
\r
3265 #define COMPARATOR_ANACMP0_ACMP0_SEL_Msk (0x01UL << COMPARATOR_ANACMP0_ACMP0_SEL_Pos) /*!< COMPARATOR ANACMP0: ACMP0_SEL Mask */
\r
3266 #define COMPARATOR_ANACMP0_CMP_LPWR_Pos 8 /*!< COMPARATOR ANACMP0: CMP_LPWR Position */
\r
3267 #define COMPARATOR_ANACMP0_CMP_LPWR_Msk (0x01UL << COMPARATOR_ANACMP0_CMP_LPWR_Pos) /*!< COMPARATOR ANACMP0: CMP_LPWR Mask */
\r
3268 #define COMPARATOR_ANACMP0_CMP_OUT_Pos 15 /*!< COMPARATOR ANACMP0: CMP_OUT Position */
\r
3269 #define COMPARATOR_ANACMP0_CMP_OUT_Msk (0x01UL << COMPARATOR_ANACMP0_CMP_OUT_Pos) /*!< COMPARATOR ANACMP0: CMP_OUT Mask */
\r
3271 /* ----------------------------- COMPARATOR_ANACMP1 ----------------------------- */
\r
3272 #define COMPARATOR_ANACMP1_CMP_EN_Pos 0 /*!< COMPARATOR ANACMP1: CMP_EN Position */
\r
3273 #define COMPARATOR_ANACMP1_CMP_EN_Msk (0x01UL << COMPARATOR_ANACMP1_CMP_EN_Pos) /*!< COMPARATOR ANACMP1: CMP_EN Mask */
\r
3274 #define COMPARATOR_ANACMP1_CMP_FLT_OFF_Pos 1 /*!< COMPARATOR ANACMP1: CMP_FLT_OFF Position */
\r
3275 #define COMPARATOR_ANACMP1_CMP_FLT_OFF_Msk (0x01UL << COMPARATOR_ANACMP1_CMP_FLT_OFF_Pos) /*!< COMPARATOR ANACMP1: CMP_FLT_OFF Mask */
\r
3276 #define COMPARATOR_ANACMP1_CMP_INV_OUT_Pos 3 /*!< COMPARATOR ANACMP1: CMP_INV_OUT Position */
\r
3277 #define COMPARATOR_ANACMP1_CMP_INV_OUT_Msk (0x01UL << COMPARATOR_ANACMP1_CMP_INV_OUT_Pos) /*!< COMPARATOR ANACMP1: CMP_INV_OUT Mask */
\r
3278 #define COMPARATOR_ANACMP1_CMP_HYST_ADJ_Pos 4 /*!< COMPARATOR ANACMP1: CMP_HYST_ADJ Position */
\r
3279 #define COMPARATOR_ANACMP1_CMP_HYST_ADJ_Msk (0x03UL << COMPARATOR_ANACMP1_CMP_HYST_ADJ_Pos) /*!< COMPARATOR ANACMP1: CMP_HYST_ADJ Mask */
\r
3280 #define COMPARATOR_ANACMP1_REF_DIV_EN_Pos 6 /*!< COMPARATOR ANACMP1: REF_DIV_EN Position */
\r
3281 #define COMPARATOR_ANACMP1_REF_DIV_EN_Msk (0x01UL << COMPARATOR_ANACMP1_REF_DIV_EN_Pos) /*!< COMPARATOR ANACMP1: REF_DIV_EN Mask */
\r
3282 #define COMPARATOR_ANACMP1_CMP_OUT_Pos 15 /*!< COMPARATOR ANACMP1: CMP_OUT Position */
\r
3283 #define COMPARATOR_ANACMP1_CMP_OUT_Msk (0x01UL << COMPARATOR_ANACMP1_CMP_OUT_Pos) /*!< COMPARATOR ANACMP1: CMP_OUT Mask */
\r
3285 /* ----------------------------- COMPARATOR_ANACMP2 ----------------------------- */
\r
3286 #define COMPARATOR_ANACMP2_CMP_EN_Pos 0 /*!< COMPARATOR ANACMP2: CMP_EN Position */
\r
3287 #define COMPARATOR_ANACMP2_CMP_EN_Msk (0x01UL << COMPARATOR_ANACMP2_CMP_EN_Pos) /*!< COMPARATOR ANACMP2: CMP_EN Mask */
\r
3288 #define COMPARATOR_ANACMP2_CMP_FLT_OFF_Pos 1 /*!< COMPARATOR ANACMP2: CMP_FLT_OFF Position */
\r
3289 #define COMPARATOR_ANACMP2_CMP_FLT_OFF_Msk (0x01UL << COMPARATOR_ANACMP2_CMP_FLT_OFF_Pos) /*!< COMPARATOR ANACMP2: CMP_FLT_OFF Mask */
\r
3290 #define COMPARATOR_ANACMP2_CMP_INV_OUT_Pos 3 /*!< COMPARATOR ANACMP2: CMP_INV_OUT Position */
\r
3291 #define COMPARATOR_ANACMP2_CMP_INV_OUT_Msk (0x01UL << COMPARATOR_ANACMP2_CMP_INV_OUT_Pos) /*!< COMPARATOR ANACMP2: CMP_INV_OUT Mask */
\r
3292 #define COMPARATOR_ANACMP2_CMP_HYST_ADJ_Pos 4 /*!< COMPARATOR ANACMP2: CMP_HYST_ADJ Position */
\r
3293 #define COMPARATOR_ANACMP2_CMP_HYST_ADJ_Msk (0x03UL << COMPARATOR_ANACMP2_CMP_HYST_ADJ_Pos) /*!< COMPARATOR ANACMP2: CMP_HYST_ADJ Mask */
\r
3294 #define COMPARATOR_ANACMP2_ACMP2_SEL_Pos 6 /*!< COMPARATOR ANACMP2: ACMP2_SEL Position */
\r
3295 #define COMPARATOR_ANACMP2_ACMP2_SEL_Msk (0x01UL << COMPARATOR_ANACMP2_ACMP2_SEL_Pos) /*!< COMPARATOR ANACMP2: ACMP2_SEL Mask */
\r
3296 #define COMPARATOR_ANACMP2_CMP_OUT_Pos 15 /*!< COMPARATOR ANACMP2: CMP_OUT Position */
\r
3297 #define COMPARATOR_ANACMP2_CMP_OUT_Msk (0x01UL << COMPARATOR_ANACMP2_CMP_OUT_Pos) /*!< COMPARATOR ANACMP2: CMP_OUT Mask */
\r
3300 /* ================================================================================ */
\r
3301 /* ================ struct 'SCU_ANALOG' Position & Mask ================ */
\r
3302 /* ================================================================================ */
\r
3305 /* ---------------------------- SCU_ANALOG_ANATSECTRL --------------------------- */
\r
3306 #define SCU_ANALOG_ANATSECTRL_TSE_EN_Pos 0 /*!< SCU_ANALOG ANATSECTRL: TSE_EN Position */
\r
3307 #define SCU_ANALOG_ANATSECTRL_TSE_EN_Msk (0x01UL << SCU_ANALOG_ANATSECTRL_TSE_EN_Pos) /*!< SCU_ANALOG ANATSECTRL: TSE_EN Mask */
\r
3309 /* ----------------------------- SCU_ANALOG_ANATSEIH ---------------------------- */
\r
3310 #define SCU_ANALOG_ANATSEIH_TSE_IH_Pos 0 /*!< SCU_ANALOG ANATSEIH: TSE_IH Position */
\r
3311 #define SCU_ANALOG_ANATSEIH_TSE_IH_Msk (0x0000ffffUL << SCU_ANALOG_ANATSEIH_TSE_IH_Pos) /*!< SCU_ANALOG ANATSEIH: TSE_IH Mask */
\r
3313 /* ----------------------------- SCU_ANALOG_ANATSEIL ---------------------------- */
\r
3314 #define SCU_ANALOG_ANATSEIL_TSE_IL_Pos 0 /*!< SCU_ANALOG ANATSEIL: TSE_IL Position */
\r
3315 #define SCU_ANALOG_ANATSEIL_TSE_IL_Msk (0x0000ffffUL << SCU_ANALOG_ANATSEIL_TSE_IL_Pos) /*!< SCU_ANALOG ANATSEIL: TSE_IL Mask */
\r
3317 /* ---------------------------- SCU_ANALOG_ANATSEMON ---------------------------- */
\r
3318 #define SCU_ANALOG_ANATSEMON_TSE_MON_Pos 0 /*!< SCU_ANALOG ANATSEMON: TSE_MON Position */
\r
3319 #define SCU_ANALOG_ANATSEMON_TSE_MON_Msk (0x0000ffffUL << SCU_ANALOG_ANATSEMON_TSE_MON_Pos) /*!< SCU_ANALOG ANATSEMON: TSE_MON Mask */
\r
3321 /* ----------------------------- SCU_ANALOG_ANAVDEL ----------------------------- */
\r
3322 #define SCU_ANALOG_ANAVDEL_VDEL_SELECT_Pos 0 /*!< SCU_ANALOG ANAVDEL: VDEL_SELECT Position */
\r
3323 #define SCU_ANALOG_ANAVDEL_VDEL_SELECT_Msk (0x03UL << SCU_ANALOG_ANAVDEL_VDEL_SELECT_Pos) /*!< SCU_ANALOG ANAVDEL: VDEL_SELECT Mask */
\r
3324 #define SCU_ANALOG_ANAVDEL_VDEL_TIM_ADJ_Pos 2 /*!< SCU_ANALOG ANAVDEL: VDEL_TIM_ADJ Position */
\r
3325 #define SCU_ANALOG_ANAVDEL_VDEL_TIM_ADJ_Msk (0x03UL << SCU_ANALOG_ANAVDEL_VDEL_TIM_ADJ_Pos) /*!< SCU_ANALOG ANAVDEL: VDEL_TIM_ADJ Mask */
\r
3326 #define SCU_ANALOG_ANAVDEL_VDEL_EN_Pos 4 /*!< SCU_ANALOG ANAVDEL: VDEL_EN Position */
\r
3327 #define SCU_ANALOG_ANAVDEL_VDEL_EN_Msk (0x01UL << SCU_ANALOG_ANAVDEL_VDEL_EN_Pos) /*!< SCU_ANALOG ANAVDEL: VDEL_EN Mask */
\r
3329 /* ---------------------------- SCU_ANALOG_ANAOFFSET ---------------------------- */
\r
3330 #define SCU_ANALOG_ANAOFFSET_ADJL_OFFSET_Pos 0 /*!< SCU_ANALOG ANAOFFSET: ADJL_OFFSET Position */
\r
3331 #define SCU_ANALOG_ANAOFFSET_ADJL_OFFSET_Msk (0x0fUL << SCU_ANALOG_ANAOFFSET_ADJL_OFFSET_Pos) /*!< SCU_ANALOG ANAOFFSET: ADJL_OFFSET Mask */
\r
3334 /* ================================================================================ */
\r
3335 /* ================ Group 'CCU4' Position & Mask ================ */
\r
3336 /* ================================================================================ */
\r
3339 /* --------------------------------- CCU4_GCTRL --------------------------------- */
\r
3340 #define CCU4_GCTRL_PRBC_Pos 0 /*!< CCU4 GCTRL: PRBC Position */
\r
3341 #define CCU4_GCTRL_PRBC_Msk (0x07UL << CCU4_GCTRL_PRBC_Pos) /*!< CCU4 GCTRL: PRBC Mask */
\r
3342 #define CCU4_GCTRL_PCIS_Pos 4 /*!< CCU4 GCTRL: PCIS Position */
\r
3343 #define CCU4_GCTRL_PCIS_Msk (0x03UL << CCU4_GCTRL_PCIS_Pos) /*!< CCU4 GCTRL: PCIS Mask */
\r
3344 #define CCU4_GCTRL_SUSCFG_Pos 8 /*!< CCU4 GCTRL: SUSCFG Position */
\r
3345 #define CCU4_GCTRL_SUSCFG_Msk (0x03UL << CCU4_GCTRL_SUSCFG_Pos) /*!< CCU4 GCTRL: SUSCFG Mask */
\r
3346 #define CCU4_GCTRL_MSE0_Pos 10 /*!< CCU4 GCTRL: MSE0 Position */
\r
3347 #define CCU4_GCTRL_MSE0_Msk (0x01UL << CCU4_GCTRL_MSE0_Pos) /*!< CCU4 GCTRL: MSE0 Mask */
\r
3348 #define CCU4_GCTRL_MSE1_Pos 11 /*!< CCU4 GCTRL: MSE1 Position */
\r
3349 #define CCU4_GCTRL_MSE1_Msk (0x01UL << CCU4_GCTRL_MSE1_Pos) /*!< CCU4 GCTRL: MSE1 Mask */
\r
3350 #define CCU4_GCTRL_MSE2_Pos 12 /*!< CCU4 GCTRL: MSE2 Position */
\r
3351 #define CCU4_GCTRL_MSE2_Msk (0x01UL << CCU4_GCTRL_MSE2_Pos) /*!< CCU4 GCTRL: MSE2 Mask */
\r
3352 #define CCU4_GCTRL_MSE3_Pos 13 /*!< CCU4 GCTRL: MSE3 Position */
\r
3353 #define CCU4_GCTRL_MSE3_Msk (0x01UL << CCU4_GCTRL_MSE3_Pos) /*!< CCU4 GCTRL: MSE3 Mask */
\r
3354 #define CCU4_GCTRL_MSDE_Pos 14 /*!< CCU4 GCTRL: MSDE Position */
\r
3355 #define CCU4_GCTRL_MSDE_Msk (0x03UL << CCU4_GCTRL_MSDE_Pos) /*!< CCU4 GCTRL: MSDE Mask */
\r
3357 /* --------------------------------- CCU4_GSTAT --------------------------------- */
\r
3358 #define CCU4_GSTAT_S0I_Pos 0 /*!< CCU4 GSTAT: S0I Position */
\r
3359 #define CCU4_GSTAT_S0I_Msk (0x01UL << CCU4_GSTAT_S0I_Pos) /*!< CCU4 GSTAT: S0I Mask */
\r
3360 #define CCU4_GSTAT_S1I_Pos 1 /*!< CCU4 GSTAT: S1I Position */
\r
3361 #define CCU4_GSTAT_S1I_Msk (0x01UL << CCU4_GSTAT_S1I_Pos) /*!< CCU4 GSTAT: S1I Mask */
\r
3362 #define CCU4_GSTAT_S2I_Pos 2 /*!< CCU4 GSTAT: S2I Position */
\r
3363 #define CCU4_GSTAT_S2I_Msk (0x01UL << CCU4_GSTAT_S2I_Pos) /*!< CCU4 GSTAT: S2I Mask */
\r
3364 #define CCU4_GSTAT_S3I_Pos 3 /*!< CCU4 GSTAT: S3I Position */
\r
3365 #define CCU4_GSTAT_S3I_Msk (0x01UL << CCU4_GSTAT_S3I_Pos) /*!< CCU4 GSTAT: S3I Mask */
\r
3366 #define CCU4_GSTAT_PRB_Pos 8 /*!< CCU4 GSTAT: PRB Position */
\r
3367 #define CCU4_GSTAT_PRB_Msk (0x01UL << CCU4_GSTAT_PRB_Pos) /*!< CCU4 GSTAT: PRB Mask */
\r
3369 /* --------------------------------- CCU4_GIDLS --------------------------------- */
\r
3370 #define CCU4_GIDLS_SS0I_Pos 0 /*!< CCU4 GIDLS: SS0I Position */
\r
3371 #define CCU4_GIDLS_SS0I_Msk (0x01UL << CCU4_GIDLS_SS0I_Pos) /*!< CCU4 GIDLS: SS0I Mask */
\r
3372 #define CCU4_GIDLS_SS1I_Pos 1 /*!< CCU4 GIDLS: SS1I Position */
\r
3373 #define CCU4_GIDLS_SS1I_Msk (0x01UL << CCU4_GIDLS_SS1I_Pos) /*!< CCU4 GIDLS: SS1I Mask */
\r
3374 #define CCU4_GIDLS_SS2I_Pos 2 /*!< CCU4 GIDLS: SS2I Position */
\r
3375 #define CCU4_GIDLS_SS2I_Msk (0x01UL << CCU4_GIDLS_SS2I_Pos) /*!< CCU4 GIDLS: SS2I Mask */
\r
3376 #define CCU4_GIDLS_SS3I_Pos 3 /*!< CCU4 GIDLS: SS3I Position */
\r
3377 #define CCU4_GIDLS_SS3I_Msk (0x01UL << CCU4_GIDLS_SS3I_Pos) /*!< CCU4 GIDLS: SS3I Mask */
\r
3378 #define CCU4_GIDLS_CPRB_Pos 8 /*!< CCU4 GIDLS: CPRB Position */
\r
3379 #define CCU4_GIDLS_CPRB_Msk (0x01UL << CCU4_GIDLS_CPRB_Pos) /*!< CCU4 GIDLS: CPRB Mask */
\r
3380 #define CCU4_GIDLS_PSIC_Pos 9 /*!< CCU4 GIDLS: PSIC Position */
\r
3381 #define CCU4_GIDLS_PSIC_Msk (0x01UL << CCU4_GIDLS_PSIC_Pos) /*!< CCU4 GIDLS: PSIC Mask */
\r
3383 /* --------------------------------- CCU4_GIDLC --------------------------------- */
\r
3384 #define CCU4_GIDLC_CS0I_Pos 0 /*!< CCU4 GIDLC: CS0I Position */
\r
3385 #define CCU4_GIDLC_CS0I_Msk (0x01UL << CCU4_GIDLC_CS0I_Pos) /*!< CCU4 GIDLC: CS0I Mask */
\r
3386 #define CCU4_GIDLC_CS1I_Pos 1 /*!< CCU4 GIDLC: CS1I Position */
\r
3387 #define CCU4_GIDLC_CS1I_Msk (0x01UL << CCU4_GIDLC_CS1I_Pos) /*!< CCU4 GIDLC: CS1I Mask */
\r
3388 #define CCU4_GIDLC_CS2I_Pos 2 /*!< CCU4 GIDLC: CS2I Position */
\r
3389 #define CCU4_GIDLC_CS2I_Msk (0x01UL << CCU4_GIDLC_CS2I_Pos) /*!< CCU4 GIDLC: CS2I Mask */
\r
3390 #define CCU4_GIDLC_CS3I_Pos 3 /*!< CCU4 GIDLC: CS3I Position */
\r
3391 #define CCU4_GIDLC_CS3I_Msk (0x01UL << CCU4_GIDLC_CS3I_Pos) /*!< CCU4 GIDLC: CS3I Mask */
\r
3392 #define CCU4_GIDLC_SPRB_Pos 8 /*!< CCU4 GIDLC: SPRB Position */
\r
3393 #define CCU4_GIDLC_SPRB_Msk (0x01UL << CCU4_GIDLC_SPRB_Pos) /*!< CCU4 GIDLC: SPRB Mask */
\r
3395 /* ---------------------------------- CCU4_GCSS --------------------------------- */
\r
3396 #define CCU4_GCSS_S0SE_Pos 0 /*!< CCU4 GCSS: S0SE Position */
\r
3397 #define CCU4_GCSS_S0SE_Msk (0x01UL << CCU4_GCSS_S0SE_Pos) /*!< CCU4 GCSS: S0SE Mask */
\r
3398 #define CCU4_GCSS_S0DSE_Pos 1 /*!< CCU4 GCSS: S0DSE Position */
\r
3399 #define CCU4_GCSS_S0DSE_Msk (0x01UL << CCU4_GCSS_S0DSE_Pos) /*!< CCU4 GCSS: S0DSE Mask */
\r
3400 #define CCU4_GCSS_S0PSE_Pos 2 /*!< CCU4 GCSS: S0PSE Position */
\r
3401 #define CCU4_GCSS_S0PSE_Msk (0x01UL << CCU4_GCSS_S0PSE_Pos) /*!< CCU4 GCSS: S0PSE Mask */
\r
3402 #define CCU4_GCSS_S1SE_Pos 4 /*!< CCU4 GCSS: S1SE Position */
\r
3403 #define CCU4_GCSS_S1SE_Msk (0x01UL << CCU4_GCSS_S1SE_Pos) /*!< CCU4 GCSS: S1SE Mask */
\r
3404 #define CCU4_GCSS_S1DSE_Pos 5 /*!< CCU4 GCSS: S1DSE Position */
\r
3405 #define CCU4_GCSS_S1DSE_Msk (0x01UL << CCU4_GCSS_S1DSE_Pos) /*!< CCU4 GCSS: S1DSE Mask */
\r
3406 #define CCU4_GCSS_S1PSE_Pos 6 /*!< CCU4 GCSS: S1PSE Position */
\r
3407 #define CCU4_GCSS_S1PSE_Msk (0x01UL << CCU4_GCSS_S1PSE_Pos) /*!< CCU4 GCSS: S1PSE Mask */
\r
3408 #define CCU4_GCSS_S2SE_Pos 8 /*!< CCU4 GCSS: S2SE Position */
\r
3409 #define CCU4_GCSS_S2SE_Msk (0x01UL << CCU4_GCSS_S2SE_Pos) /*!< CCU4 GCSS: S2SE Mask */
\r
3410 #define CCU4_GCSS_S2DSE_Pos 9 /*!< CCU4 GCSS: S2DSE Position */
\r
3411 #define CCU4_GCSS_S2DSE_Msk (0x01UL << CCU4_GCSS_S2DSE_Pos) /*!< CCU4 GCSS: S2DSE Mask */
\r
3412 #define CCU4_GCSS_S2PSE_Pos 10 /*!< CCU4 GCSS: S2PSE Position */
\r
3413 #define CCU4_GCSS_S2PSE_Msk (0x01UL << CCU4_GCSS_S2PSE_Pos) /*!< CCU4 GCSS: S2PSE Mask */
\r
3414 #define CCU4_GCSS_S3SE_Pos 12 /*!< CCU4 GCSS: S3SE Position */
\r
3415 #define CCU4_GCSS_S3SE_Msk (0x01UL << CCU4_GCSS_S3SE_Pos) /*!< CCU4 GCSS: S3SE Mask */
\r
3416 #define CCU4_GCSS_S3DSE_Pos 13 /*!< CCU4 GCSS: S3DSE Position */
\r
3417 #define CCU4_GCSS_S3DSE_Msk (0x01UL << CCU4_GCSS_S3DSE_Pos) /*!< CCU4 GCSS: S3DSE Mask */
\r
3418 #define CCU4_GCSS_S3PSE_Pos 14 /*!< CCU4 GCSS: S3PSE Position */
\r
3419 #define CCU4_GCSS_S3PSE_Msk (0x01UL << CCU4_GCSS_S3PSE_Pos) /*!< CCU4 GCSS: S3PSE Mask */
\r
3420 #define CCU4_GCSS_S0STS_Pos 16 /*!< CCU4 GCSS: S0STS Position */
\r
3421 #define CCU4_GCSS_S0STS_Msk (0x01UL << CCU4_GCSS_S0STS_Pos) /*!< CCU4 GCSS: S0STS Mask */
\r
3422 #define CCU4_GCSS_S1STS_Pos 17 /*!< CCU4 GCSS: S1STS Position */
\r
3423 #define CCU4_GCSS_S1STS_Msk (0x01UL << CCU4_GCSS_S1STS_Pos) /*!< CCU4 GCSS: S1STS Mask */
\r
3424 #define CCU4_GCSS_S2STS_Pos 18 /*!< CCU4 GCSS: S2STS Position */
\r
3425 #define CCU4_GCSS_S2STS_Msk (0x01UL << CCU4_GCSS_S2STS_Pos) /*!< CCU4 GCSS: S2STS Mask */
\r
3426 #define CCU4_GCSS_S3STS_Pos 19 /*!< CCU4 GCSS: S3STS Position */
\r
3427 #define CCU4_GCSS_S3STS_Msk (0x01UL << CCU4_GCSS_S3STS_Pos) /*!< CCU4 GCSS: S3STS Mask */
\r
3429 /* ---------------------------------- CCU4_GCSC --------------------------------- */
\r
3430 #define CCU4_GCSC_S0SC_Pos 0 /*!< CCU4 GCSC: S0SC Position */
\r
3431 #define CCU4_GCSC_S0SC_Msk (0x01UL << CCU4_GCSC_S0SC_Pos) /*!< CCU4 GCSC: S0SC Mask */
\r
3432 #define CCU4_GCSC_S0DSC_Pos 1 /*!< CCU4 GCSC: S0DSC Position */
\r
3433 #define CCU4_GCSC_S0DSC_Msk (0x01UL << CCU4_GCSC_S0DSC_Pos) /*!< CCU4 GCSC: S0DSC Mask */
\r
3434 #define CCU4_GCSC_S0PSC_Pos 2 /*!< CCU4 GCSC: S0PSC Position */
\r
3435 #define CCU4_GCSC_S0PSC_Msk (0x01UL << CCU4_GCSC_S0PSC_Pos) /*!< CCU4 GCSC: S0PSC Mask */
\r
3436 #define CCU4_GCSC_S1SC_Pos 4 /*!< CCU4 GCSC: S1SC Position */
\r
3437 #define CCU4_GCSC_S1SC_Msk (0x01UL << CCU4_GCSC_S1SC_Pos) /*!< CCU4 GCSC: S1SC Mask */
\r
3438 #define CCU4_GCSC_S1DSC_Pos 5 /*!< CCU4 GCSC: S1DSC Position */
\r
3439 #define CCU4_GCSC_S1DSC_Msk (0x01UL << CCU4_GCSC_S1DSC_Pos) /*!< CCU4 GCSC: S1DSC Mask */
\r
3440 #define CCU4_GCSC_S1PSC_Pos 6 /*!< CCU4 GCSC: S1PSC Position */
\r
3441 #define CCU4_GCSC_S1PSC_Msk (0x01UL << CCU4_GCSC_S1PSC_Pos) /*!< CCU4 GCSC: S1PSC Mask */
\r
3442 #define CCU4_GCSC_S2SC_Pos 8 /*!< CCU4 GCSC: S2SC Position */
\r
3443 #define CCU4_GCSC_S2SC_Msk (0x01UL << CCU4_GCSC_S2SC_Pos) /*!< CCU4 GCSC: S2SC Mask */
\r
3444 #define CCU4_GCSC_S2DSC_Pos 9 /*!< CCU4 GCSC: S2DSC Position */
\r
3445 #define CCU4_GCSC_S2DSC_Msk (0x01UL << CCU4_GCSC_S2DSC_Pos) /*!< CCU4 GCSC: S2DSC Mask */
\r
3446 #define CCU4_GCSC_S2PSC_Pos 10 /*!< CCU4 GCSC: S2PSC Position */
\r
3447 #define CCU4_GCSC_S2PSC_Msk (0x01UL << CCU4_GCSC_S2PSC_Pos) /*!< CCU4 GCSC: S2PSC Mask */
\r
3448 #define CCU4_GCSC_S3SC_Pos 12 /*!< CCU4 GCSC: S3SC Position */
\r
3449 #define CCU4_GCSC_S3SC_Msk (0x01UL << CCU4_GCSC_S3SC_Pos) /*!< CCU4 GCSC: S3SC Mask */
\r
3450 #define CCU4_GCSC_S3DSC_Pos 13 /*!< CCU4 GCSC: S3DSC Position */
\r
3451 #define CCU4_GCSC_S3DSC_Msk (0x01UL << CCU4_GCSC_S3DSC_Pos) /*!< CCU4 GCSC: S3DSC Mask */
\r
3452 #define CCU4_GCSC_S3PSC_Pos 14 /*!< CCU4 GCSC: S3PSC Position */
\r
3453 #define CCU4_GCSC_S3PSC_Msk (0x01UL << CCU4_GCSC_S3PSC_Pos) /*!< CCU4 GCSC: S3PSC Mask */
\r
3454 #define CCU4_GCSC_S0STC_Pos 16 /*!< CCU4 GCSC: S0STC Position */
\r
3455 #define CCU4_GCSC_S0STC_Msk (0x01UL << CCU4_GCSC_S0STC_Pos) /*!< CCU4 GCSC: S0STC Mask */
\r
3456 #define CCU4_GCSC_S1STC_Pos 17 /*!< CCU4 GCSC: S1STC Position */
\r
3457 #define CCU4_GCSC_S1STC_Msk (0x01UL << CCU4_GCSC_S1STC_Pos) /*!< CCU4 GCSC: S1STC Mask */
\r
3458 #define CCU4_GCSC_S2STC_Pos 18 /*!< CCU4 GCSC: S2STC Position */
\r
3459 #define CCU4_GCSC_S2STC_Msk (0x01UL << CCU4_GCSC_S2STC_Pos) /*!< CCU4 GCSC: S2STC Mask */
\r
3460 #define CCU4_GCSC_S3STC_Pos 19 /*!< CCU4 GCSC: S3STC Position */
\r
3461 #define CCU4_GCSC_S3STC_Msk (0x01UL << CCU4_GCSC_S3STC_Pos) /*!< CCU4 GCSC: S3STC Mask */
\r
3463 /* ---------------------------------- CCU4_GCST --------------------------------- */
\r
3464 #define CCU4_GCST_S0SS_Pos 0 /*!< CCU4 GCST: S0SS Position */
\r
3465 #define CCU4_GCST_S0SS_Msk (0x01UL << CCU4_GCST_S0SS_Pos) /*!< CCU4 GCST: S0SS Mask */
\r
3466 #define CCU4_GCST_S0DSS_Pos 1 /*!< CCU4 GCST: S0DSS Position */
\r
3467 #define CCU4_GCST_S0DSS_Msk (0x01UL << CCU4_GCST_S0DSS_Pos) /*!< CCU4 GCST: S0DSS Mask */
\r
3468 #define CCU4_GCST_S0PSS_Pos 2 /*!< CCU4 GCST: S0PSS Position */
\r
3469 #define CCU4_GCST_S0PSS_Msk (0x01UL << CCU4_GCST_S0PSS_Pos) /*!< CCU4 GCST: S0PSS Mask */
\r
3470 #define CCU4_GCST_S1SS_Pos 4 /*!< CCU4 GCST: S1SS Position */
\r
3471 #define CCU4_GCST_S1SS_Msk (0x01UL << CCU4_GCST_S1SS_Pos) /*!< CCU4 GCST: S1SS Mask */
\r
3472 #define CCU4_GCST_S1DSS_Pos 5 /*!< CCU4 GCST: S1DSS Position */
\r
3473 #define CCU4_GCST_S1DSS_Msk (0x01UL << CCU4_GCST_S1DSS_Pos) /*!< CCU4 GCST: S1DSS Mask */
\r
3474 #define CCU4_GCST_S1PSS_Pos 6 /*!< CCU4 GCST: S1PSS Position */
\r
3475 #define CCU4_GCST_S1PSS_Msk (0x01UL << CCU4_GCST_S1PSS_Pos) /*!< CCU4 GCST: S1PSS Mask */
\r
3476 #define CCU4_GCST_S2SS_Pos 8 /*!< CCU4 GCST: S2SS Position */
\r
3477 #define CCU4_GCST_S2SS_Msk (0x01UL << CCU4_GCST_S2SS_Pos) /*!< CCU4 GCST: S2SS Mask */
\r
3478 #define CCU4_GCST_S2DSS_Pos 9 /*!< CCU4 GCST: S2DSS Position */
\r
3479 #define CCU4_GCST_S2DSS_Msk (0x01UL << CCU4_GCST_S2DSS_Pos) /*!< CCU4 GCST: S2DSS Mask */
\r
3480 #define CCU4_GCST_S2PSS_Pos 10 /*!< CCU4 GCST: S2PSS Position */
\r
3481 #define CCU4_GCST_S2PSS_Msk (0x01UL << CCU4_GCST_S2PSS_Pos) /*!< CCU4 GCST: S2PSS Mask */
\r
3482 #define CCU4_GCST_S3SS_Pos 12 /*!< CCU4 GCST: S3SS Position */
\r
3483 #define CCU4_GCST_S3SS_Msk (0x01UL << CCU4_GCST_S3SS_Pos) /*!< CCU4 GCST: S3SS Mask */
\r
3484 #define CCU4_GCST_S3DSS_Pos 13 /*!< CCU4 GCST: S3DSS Position */
\r
3485 #define CCU4_GCST_S3DSS_Msk (0x01UL << CCU4_GCST_S3DSS_Pos) /*!< CCU4 GCST: S3DSS Mask */
\r
3486 #define CCU4_GCST_S3PSS_Pos 14 /*!< CCU4 GCST: S3PSS Position */
\r
3487 #define CCU4_GCST_S3PSS_Msk (0x01UL << CCU4_GCST_S3PSS_Pos) /*!< CCU4 GCST: S3PSS Mask */
\r
3488 #define CCU4_GCST_CC40ST_Pos 16 /*!< CCU4 GCST: CC40ST Position */
\r
3489 #define CCU4_GCST_CC40ST_Msk (0x01UL << CCU4_GCST_CC40ST_Pos) /*!< CCU4 GCST: CC40ST Mask */
\r
3490 #define CCU4_GCST_CC41ST_Pos 17 /*!< CCU4 GCST: CC41ST Position */
\r
3491 #define CCU4_GCST_CC41ST_Msk (0x01UL << CCU4_GCST_CC41ST_Pos) /*!< CCU4 GCST: CC41ST Mask */
\r
3492 #define CCU4_GCST_CC42ST_Pos 18 /*!< CCU4 GCST: CC42ST Position */
\r
3493 #define CCU4_GCST_CC42ST_Msk (0x01UL << CCU4_GCST_CC42ST_Pos) /*!< CCU4 GCST: CC42ST Mask */
\r
3494 #define CCU4_GCST_CC43ST_Pos 19 /*!< CCU4 GCST: CC43ST Position */
\r
3495 #define CCU4_GCST_CC43ST_Msk (0x01UL << CCU4_GCST_CC43ST_Pos) /*!< CCU4 GCST: CC43ST Mask */
\r
3497 /* ---------------------------------- CCU4_MIDR --------------------------------- */
\r
3498 #define CCU4_MIDR_MODR_Pos 0 /*!< CCU4 MIDR: MODR Position */
\r
3499 #define CCU4_MIDR_MODR_Msk (0x000000ffUL << CCU4_MIDR_MODR_Pos) /*!< CCU4 MIDR: MODR Mask */
\r
3500 #define CCU4_MIDR_MODT_Pos 8 /*!< CCU4 MIDR: MODT Position */
\r
3501 #define CCU4_MIDR_MODT_Msk (0x000000ffUL << CCU4_MIDR_MODT_Pos) /*!< CCU4 MIDR: MODT Mask */
\r
3502 #define CCU4_MIDR_MODN_Pos 16 /*!< CCU4 MIDR: MODN Position */
\r
3503 #define CCU4_MIDR_MODN_Msk (0x0000ffffUL << CCU4_MIDR_MODN_Pos) /*!< CCU4 MIDR: MODN Mask */
\r
3506 /* ================================================================================ */
\r
3507 /* ================ Group 'CCU4_CC4' Position & Mask ================ */
\r
3508 /* ================================================================================ */
\r
3511 /* -------------------------------- CCU4_CC4_INS -------------------------------- */
\r
3512 #define CCU4_CC4_INS_EV0IS_Pos 0 /*!< CCU4_CC4 INS: EV0IS Position */
\r
3513 #define CCU4_CC4_INS_EV0IS_Msk (0x0fUL << CCU4_CC4_INS_EV0IS_Pos) /*!< CCU4_CC4 INS: EV0IS Mask */
\r
3514 #define CCU4_CC4_INS_EV1IS_Pos 4 /*!< CCU4_CC4 INS: EV1IS Position */
\r
3515 #define CCU4_CC4_INS_EV1IS_Msk (0x0fUL << CCU4_CC4_INS_EV1IS_Pos) /*!< CCU4_CC4 INS: EV1IS Mask */
\r
3516 #define CCU4_CC4_INS_EV2IS_Pos 8 /*!< CCU4_CC4 INS: EV2IS Position */
\r
3517 #define CCU4_CC4_INS_EV2IS_Msk (0x0fUL << CCU4_CC4_INS_EV2IS_Pos) /*!< CCU4_CC4 INS: EV2IS Mask */
\r
3518 #define CCU4_CC4_INS_EV0EM_Pos 16 /*!< CCU4_CC4 INS: EV0EM Position */
\r
3519 #define CCU4_CC4_INS_EV0EM_Msk (0x03UL << CCU4_CC4_INS_EV0EM_Pos) /*!< CCU4_CC4 INS: EV0EM Mask */
\r
3520 #define CCU4_CC4_INS_EV1EM_Pos 18 /*!< CCU4_CC4 INS: EV1EM Position */
\r
3521 #define CCU4_CC4_INS_EV1EM_Msk (0x03UL << CCU4_CC4_INS_EV1EM_Pos) /*!< CCU4_CC4 INS: EV1EM Mask */
\r
3522 #define CCU4_CC4_INS_EV2EM_Pos 20 /*!< CCU4_CC4 INS: EV2EM Position */
\r
3523 #define CCU4_CC4_INS_EV2EM_Msk (0x03UL << CCU4_CC4_INS_EV2EM_Pos) /*!< CCU4_CC4 INS: EV2EM Mask */
\r
3524 #define CCU4_CC4_INS_EV0LM_Pos 22 /*!< CCU4_CC4 INS: EV0LM Position */
\r
3525 #define CCU4_CC4_INS_EV0LM_Msk (0x01UL << CCU4_CC4_INS_EV0LM_Pos) /*!< CCU4_CC4 INS: EV0LM Mask */
\r
3526 #define CCU4_CC4_INS_EV1LM_Pos 23 /*!< CCU4_CC4 INS: EV1LM Position */
\r
3527 #define CCU4_CC4_INS_EV1LM_Msk (0x01UL << CCU4_CC4_INS_EV1LM_Pos) /*!< CCU4_CC4 INS: EV1LM Mask */
\r
3528 #define CCU4_CC4_INS_EV2LM_Pos 24 /*!< CCU4_CC4 INS: EV2LM Position */
\r
3529 #define CCU4_CC4_INS_EV2LM_Msk (0x01UL << CCU4_CC4_INS_EV2LM_Pos) /*!< CCU4_CC4 INS: EV2LM Mask */
\r
3530 #define CCU4_CC4_INS_LPF0M_Pos 25 /*!< CCU4_CC4 INS: LPF0M Position */
\r
3531 #define CCU4_CC4_INS_LPF0M_Msk (0x03UL << CCU4_CC4_INS_LPF0M_Pos) /*!< CCU4_CC4 INS: LPF0M Mask */
\r
3532 #define CCU4_CC4_INS_LPF1M_Pos 27 /*!< CCU4_CC4 INS: LPF1M Position */
\r
3533 #define CCU4_CC4_INS_LPF1M_Msk (0x03UL << CCU4_CC4_INS_LPF1M_Pos) /*!< CCU4_CC4 INS: LPF1M Mask */
\r
3534 #define CCU4_CC4_INS_LPF2M_Pos 29 /*!< CCU4_CC4 INS: LPF2M Position */
\r
3535 #define CCU4_CC4_INS_LPF2M_Msk (0x03UL << CCU4_CC4_INS_LPF2M_Pos) /*!< CCU4_CC4 INS: LPF2M Mask */
\r
3537 /* -------------------------------- CCU4_CC4_CMC -------------------------------- */
\r
3538 #define CCU4_CC4_CMC_STRTS_Pos 0 /*!< CCU4_CC4 CMC: STRTS Position */
\r
3539 #define CCU4_CC4_CMC_STRTS_Msk (0x03UL << CCU4_CC4_CMC_STRTS_Pos) /*!< CCU4_CC4 CMC: STRTS Mask */
\r
3540 #define CCU4_CC4_CMC_ENDS_Pos 2 /*!< CCU4_CC4 CMC: ENDS Position */
\r
3541 #define CCU4_CC4_CMC_ENDS_Msk (0x03UL << CCU4_CC4_CMC_ENDS_Pos) /*!< CCU4_CC4 CMC: ENDS Mask */
\r
3542 #define CCU4_CC4_CMC_CAP0S_Pos 4 /*!< CCU4_CC4 CMC: CAP0S Position */
\r
3543 #define CCU4_CC4_CMC_CAP0S_Msk (0x03UL << CCU4_CC4_CMC_CAP0S_Pos) /*!< CCU4_CC4 CMC: CAP0S Mask */
\r
3544 #define CCU4_CC4_CMC_CAP1S_Pos 6 /*!< CCU4_CC4 CMC: CAP1S Position */
\r
3545 #define CCU4_CC4_CMC_CAP1S_Msk (0x03UL << CCU4_CC4_CMC_CAP1S_Pos) /*!< CCU4_CC4 CMC: CAP1S Mask */
\r
3546 #define CCU4_CC4_CMC_GATES_Pos 8 /*!< CCU4_CC4 CMC: GATES Position */
\r
3547 #define CCU4_CC4_CMC_GATES_Msk (0x03UL << CCU4_CC4_CMC_GATES_Pos) /*!< CCU4_CC4 CMC: GATES Mask */
\r
3548 #define CCU4_CC4_CMC_UDS_Pos 10 /*!< CCU4_CC4 CMC: UDS Position */
\r
3549 #define CCU4_CC4_CMC_UDS_Msk (0x03UL << CCU4_CC4_CMC_UDS_Pos) /*!< CCU4_CC4 CMC: UDS Mask */
\r
3550 #define CCU4_CC4_CMC_LDS_Pos 12 /*!< CCU4_CC4 CMC: LDS Position */
\r
3551 #define CCU4_CC4_CMC_LDS_Msk (0x03UL << CCU4_CC4_CMC_LDS_Pos) /*!< CCU4_CC4 CMC: LDS Mask */
\r
3552 #define CCU4_CC4_CMC_CNTS_Pos 14 /*!< CCU4_CC4 CMC: CNTS Position */
\r
3553 #define CCU4_CC4_CMC_CNTS_Msk (0x03UL << CCU4_CC4_CMC_CNTS_Pos) /*!< CCU4_CC4 CMC: CNTS Mask */
\r
3554 #define CCU4_CC4_CMC_OFS_Pos 16 /*!< CCU4_CC4 CMC: OFS Position */
\r
3555 #define CCU4_CC4_CMC_OFS_Msk (0x01UL << CCU4_CC4_CMC_OFS_Pos) /*!< CCU4_CC4 CMC: OFS Mask */
\r
3556 #define CCU4_CC4_CMC_TS_Pos 17 /*!< CCU4_CC4 CMC: TS Position */
\r
3557 #define CCU4_CC4_CMC_TS_Msk (0x01UL << CCU4_CC4_CMC_TS_Pos) /*!< CCU4_CC4 CMC: TS Mask */
\r
3558 #define CCU4_CC4_CMC_MOS_Pos 18 /*!< CCU4_CC4 CMC: MOS Position */
\r
3559 #define CCU4_CC4_CMC_MOS_Msk (0x03UL << CCU4_CC4_CMC_MOS_Pos) /*!< CCU4_CC4 CMC: MOS Mask */
\r
3560 #define CCU4_CC4_CMC_TCE_Pos 20 /*!< CCU4_CC4 CMC: TCE Position */
\r
3561 #define CCU4_CC4_CMC_TCE_Msk (0x01UL << CCU4_CC4_CMC_TCE_Pos) /*!< CCU4_CC4 CMC: TCE Mask */
\r
3563 /* -------------------------------- CCU4_CC4_TCST ------------------------------- */
\r
3564 #define CCU4_CC4_TCST_TRB_Pos 0 /*!< CCU4_CC4 TCST: TRB Position */
\r
3565 #define CCU4_CC4_TCST_TRB_Msk (0x01UL << CCU4_CC4_TCST_TRB_Pos) /*!< CCU4_CC4 TCST: TRB Mask */
\r
3566 #define CCU4_CC4_TCST_CDIR_Pos 1 /*!< CCU4_CC4 TCST: CDIR Position */
\r
3567 #define CCU4_CC4_TCST_CDIR_Msk (0x01UL << CCU4_CC4_TCST_CDIR_Pos) /*!< CCU4_CC4 TCST: CDIR Mask */
\r
3569 /* ------------------------------- CCU4_CC4_TCSET ------------------------------- */
\r
3570 #define CCU4_CC4_TCSET_TRBS_Pos 0 /*!< CCU4_CC4 TCSET: TRBS Position */
\r
3571 #define CCU4_CC4_TCSET_TRBS_Msk (0x01UL << CCU4_CC4_TCSET_TRBS_Pos) /*!< CCU4_CC4 TCSET: TRBS Mask */
\r
3573 /* ------------------------------- CCU4_CC4_TCCLR ------------------------------- */
\r
3574 #define CCU4_CC4_TCCLR_TRBC_Pos 0 /*!< CCU4_CC4 TCCLR: TRBC Position */
\r
3575 #define CCU4_CC4_TCCLR_TRBC_Msk (0x01UL << CCU4_CC4_TCCLR_TRBC_Pos) /*!< CCU4_CC4 TCCLR: TRBC Mask */
\r
3576 #define CCU4_CC4_TCCLR_TCC_Pos 1 /*!< CCU4_CC4 TCCLR: TCC Position */
\r
3577 #define CCU4_CC4_TCCLR_TCC_Msk (0x01UL << CCU4_CC4_TCCLR_TCC_Pos) /*!< CCU4_CC4 TCCLR: TCC Mask */
\r
3578 #define CCU4_CC4_TCCLR_DITC_Pos 2 /*!< CCU4_CC4 TCCLR: DITC Position */
\r
3579 #define CCU4_CC4_TCCLR_DITC_Msk (0x01UL << CCU4_CC4_TCCLR_DITC_Pos) /*!< CCU4_CC4 TCCLR: DITC Mask */
\r
3581 /* --------------------------------- CCU4_CC4_TC -------------------------------- */
\r
3582 #define CCU4_CC4_TC_TCM_Pos 0 /*!< CCU4_CC4 TC: TCM Position */
\r
3583 #define CCU4_CC4_TC_TCM_Msk (0x01UL << CCU4_CC4_TC_TCM_Pos) /*!< CCU4_CC4 TC: TCM Mask */
\r
3584 #define CCU4_CC4_TC_TSSM_Pos 1 /*!< CCU4_CC4 TC: TSSM Position */
\r
3585 #define CCU4_CC4_TC_TSSM_Msk (0x01UL << CCU4_CC4_TC_TSSM_Pos) /*!< CCU4_CC4 TC: TSSM Mask */
\r
3586 #define CCU4_CC4_TC_CLST_Pos 2 /*!< CCU4_CC4 TC: CLST Position */
\r
3587 #define CCU4_CC4_TC_CLST_Msk (0x01UL << CCU4_CC4_TC_CLST_Pos) /*!< CCU4_CC4 TC: CLST Mask */
\r
3588 #define CCU4_CC4_TC_CMOD_Pos 3 /*!< CCU4_CC4 TC: CMOD Position */
\r
3589 #define CCU4_CC4_TC_CMOD_Msk (0x01UL << CCU4_CC4_TC_CMOD_Pos) /*!< CCU4_CC4 TC: CMOD Mask */
\r
3590 #define CCU4_CC4_TC_ECM_Pos 4 /*!< CCU4_CC4 TC: ECM Position */
\r
3591 #define CCU4_CC4_TC_ECM_Msk (0x01UL << CCU4_CC4_TC_ECM_Pos) /*!< CCU4_CC4 TC: ECM Mask */
\r
3592 #define CCU4_CC4_TC_CAPC_Pos 5 /*!< CCU4_CC4 TC: CAPC Position */
\r
3593 #define CCU4_CC4_TC_CAPC_Msk (0x03UL << CCU4_CC4_TC_CAPC_Pos) /*!< CCU4_CC4 TC: CAPC Mask */
\r
3594 #define CCU4_CC4_TC_ENDM_Pos 8 /*!< CCU4_CC4 TC: ENDM Position */
\r
3595 #define CCU4_CC4_TC_ENDM_Msk (0x03UL << CCU4_CC4_TC_ENDM_Pos) /*!< CCU4_CC4 TC: ENDM Mask */
\r
3596 #define CCU4_CC4_TC_STRM_Pos 10 /*!< CCU4_CC4 TC: STRM Position */
\r
3597 #define CCU4_CC4_TC_STRM_Msk (0x01UL << CCU4_CC4_TC_STRM_Pos) /*!< CCU4_CC4 TC: STRM Mask */
\r
3598 #define CCU4_CC4_TC_SCE_Pos 11 /*!< CCU4_CC4 TC: SCE Position */
\r
3599 #define CCU4_CC4_TC_SCE_Msk (0x01UL << CCU4_CC4_TC_SCE_Pos) /*!< CCU4_CC4 TC: SCE Mask */
\r
3600 #define CCU4_CC4_TC_CCS_Pos 12 /*!< CCU4_CC4 TC: CCS Position */
\r
3601 #define CCU4_CC4_TC_CCS_Msk (0x01UL << CCU4_CC4_TC_CCS_Pos) /*!< CCU4_CC4 TC: CCS Mask */
\r
3602 #define CCU4_CC4_TC_DITHE_Pos 13 /*!< CCU4_CC4 TC: DITHE Position */
\r
3603 #define CCU4_CC4_TC_DITHE_Msk (0x03UL << CCU4_CC4_TC_DITHE_Pos) /*!< CCU4_CC4 TC: DITHE Mask */
\r
3604 #define CCU4_CC4_TC_DIM_Pos 15 /*!< CCU4_CC4 TC: DIM Position */
\r
3605 #define CCU4_CC4_TC_DIM_Msk (0x01UL << CCU4_CC4_TC_DIM_Pos) /*!< CCU4_CC4 TC: DIM Mask */
\r
3606 #define CCU4_CC4_TC_FPE_Pos 16 /*!< CCU4_CC4 TC: FPE Position */
\r
3607 #define CCU4_CC4_TC_FPE_Msk (0x01UL << CCU4_CC4_TC_FPE_Pos) /*!< CCU4_CC4 TC: FPE Mask */
\r
3608 #define CCU4_CC4_TC_TRAPE_Pos 17 /*!< CCU4_CC4 TC: TRAPE Position */
\r
3609 #define CCU4_CC4_TC_TRAPE_Msk (0x01UL << CCU4_CC4_TC_TRAPE_Pos) /*!< CCU4_CC4 TC: TRAPE Mask */
\r
3610 #define CCU4_CC4_TC_TRPSE_Pos 21 /*!< CCU4_CC4 TC: TRPSE Position */
\r
3611 #define CCU4_CC4_TC_TRPSE_Msk (0x01UL << CCU4_CC4_TC_TRPSE_Pos) /*!< CCU4_CC4 TC: TRPSE Mask */
\r
3612 #define CCU4_CC4_TC_TRPSW_Pos 22 /*!< CCU4_CC4 TC: TRPSW Position */
\r
3613 #define CCU4_CC4_TC_TRPSW_Msk (0x01UL << CCU4_CC4_TC_TRPSW_Pos) /*!< CCU4_CC4 TC: TRPSW Mask */
\r
3614 #define CCU4_CC4_TC_EMS_Pos 23 /*!< CCU4_CC4 TC: EMS Position */
\r
3615 #define CCU4_CC4_TC_EMS_Msk (0x01UL << CCU4_CC4_TC_EMS_Pos) /*!< CCU4_CC4 TC: EMS Mask */
\r
3616 #define CCU4_CC4_TC_EMT_Pos 24 /*!< CCU4_CC4 TC: EMT Position */
\r
3617 #define CCU4_CC4_TC_EMT_Msk (0x01UL << CCU4_CC4_TC_EMT_Pos) /*!< CCU4_CC4 TC: EMT Mask */
\r
3618 #define CCU4_CC4_TC_MCME_Pos 25 /*!< CCU4_CC4 TC: MCME Position */
\r
3619 #define CCU4_CC4_TC_MCME_Msk (0x01UL << CCU4_CC4_TC_MCME_Pos) /*!< CCU4_CC4 TC: MCME Mask */
\r
3621 /* -------------------------------- CCU4_CC4_PSL -------------------------------- */
\r
3622 #define CCU4_CC4_PSL_PSL_Pos 0 /*!< CCU4_CC4 PSL: PSL Position */
\r
3623 #define CCU4_CC4_PSL_PSL_Msk (0x01UL << CCU4_CC4_PSL_PSL_Pos) /*!< CCU4_CC4 PSL: PSL Mask */
\r
3625 /* -------------------------------- CCU4_CC4_DIT -------------------------------- */
\r
3626 #define CCU4_CC4_DIT_DCV_Pos 0 /*!< CCU4_CC4 DIT: DCV Position */
\r
3627 #define CCU4_CC4_DIT_DCV_Msk (0x0fUL << CCU4_CC4_DIT_DCV_Pos) /*!< CCU4_CC4 DIT: DCV Mask */
\r
3628 #define CCU4_CC4_DIT_DCNT_Pos 8 /*!< CCU4_CC4 DIT: DCNT Position */
\r
3629 #define CCU4_CC4_DIT_DCNT_Msk (0x0fUL << CCU4_CC4_DIT_DCNT_Pos) /*!< CCU4_CC4 DIT: DCNT Mask */
\r
3631 /* -------------------------------- CCU4_CC4_DITS ------------------------------- */
\r
3632 #define CCU4_CC4_DITS_DCVS_Pos 0 /*!< CCU4_CC4 DITS: DCVS Position */
\r
3633 #define CCU4_CC4_DITS_DCVS_Msk (0x0fUL << CCU4_CC4_DITS_DCVS_Pos) /*!< CCU4_CC4 DITS: DCVS Mask */
\r
3635 /* -------------------------------- CCU4_CC4_PSC -------------------------------- */
\r
3636 #define CCU4_CC4_PSC_PSIV_Pos 0 /*!< CCU4_CC4 PSC: PSIV Position */
\r
3637 #define CCU4_CC4_PSC_PSIV_Msk (0x0fUL << CCU4_CC4_PSC_PSIV_Pos) /*!< CCU4_CC4 PSC: PSIV Mask */
\r
3639 /* -------------------------------- CCU4_CC4_FPC -------------------------------- */
\r
3640 #define CCU4_CC4_FPC_PCMP_Pos 0 /*!< CCU4_CC4 FPC: PCMP Position */
\r
3641 #define CCU4_CC4_FPC_PCMP_Msk (0x0fUL << CCU4_CC4_FPC_PCMP_Pos) /*!< CCU4_CC4 FPC: PCMP Mask */
\r
3642 #define CCU4_CC4_FPC_PVAL_Pos 8 /*!< CCU4_CC4 FPC: PVAL Position */
\r
3643 #define CCU4_CC4_FPC_PVAL_Msk (0x0fUL << CCU4_CC4_FPC_PVAL_Pos) /*!< CCU4_CC4 FPC: PVAL Mask */
\r
3645 /* -------------------------------- CCU4_CC4_FPCS ------------------------------- */
\r
3646 #define CCU4_CC4_FPCS_PCMP_Pos 0 /*!< CCU4_CC4 FPCS: PCMP Position */
\r
3647 #define CCU4_CC4_FPCS_PCMP_Msk (0x0fUL << CCU4_CC4_FPCS_PCMP_Pos) /*!< CCU4_CC4 FPCS: PCMP Mask */
\r
3649 /* --------------------------------- CCU4_CC4_PR -------------------------------- */
\r
3650 #define CCU4_CC4_PR_PR_Pos 0 /*!< CCU4_CC4 PR: PR Position */
\r
3651 #define CCU4_CC4_PR_PR_Msk (0x0000ffffUL << CCU4_CC4_PR_PR_Pos) /*!< CCU4_CC4 PR: PR Mask */
\r
3653 /* -------------------------------- CCU4_CC4_PRS -------------------------------- */
\r
3654 #define CCU4_CC4_PRS_PRS_Pos 0 /*!< CCU4_CC4 PRS: PRS Position */
\r
3655 #define CCU4_CC4_PRS_PRS_Msk (0x0000ffffUL << CCU4_CC4_PRS_PRS_Pos) /*!< CCU4_CC4 PRS: PRS Mask */
\r
3657 /* --------------------------------- CCU4_CC4_CR -------------------------------- */
\r
3658 #define CCU4_CC4_CR_CR_Pos 0 /*!< CCU4_CC4 CR: CR Position */
\r
3659 #define CCU4_CC4_CR_CR_Msk (0x0000ffffUL << CCU4_CC4_CR_CR_Pos) /*!< CCU4_CC4 CR: CR Mask */
\r
3661 /* -------------------------------- CCU4_CC4_CRS -------------------------------- */
\r
3662 #define CCU4_CC4_CRS_CRS_Pos 0 /*!< CCU4_CC4 CRS: CRS Position */
\r
3663 #define CCU4_CC4_CRS_CRS_Msk (0x0000ffffUL << CCU4_CC4_CRS_CRS_Pos) /*!< CCU4_CC4 CRS: CRS Mask */
\r
3665 /* ------------------------------- CCU4_CC4_TIMER ------------------------------- */
\r
3666 #define CCU4_CC4_TIMER_TVAL_Pos 0 /*!< CCU4_CC4 TIMER: TVAL Position */
\r
3667 #define CCU4_CC4_TIMER_TVAL_Msk (0x0000ffffUL << CCU4_CC4_TIMER_TVAL_Pos) /*!< CCU4_CC4 TIMER: TVAL Mask */
\r
3669 /* --------------------------------- CCU4_CC4_CV -------------------------------- */
\r
3670 #define CCU4_CC4_CV_CAPTV_Pos 0 /*!< CCU4_CC4 CV: CAPTV Position */
\r
3671 #define CCU4_CC4_CV_CAPTV_Msk (0x0000ffffUL << CCU4_CC4_CV_CAPTV_Pos) /*!< CCU4_CC4 CV: CAPTV Mask */
\r
3672 #define CCU4_CC4_CV_FPCV_Pos 16 /*!< CCU4_CC4 CV: FPCV Position */
\r
3673 #define CCU4_CC4_CV_FPCV_Msk (0x0fUL << CCU4_CC4_CV_FPCV_Pos) /*!< CCU4_CC4 CV: FPCV Mask */
\r
3674 #define CCU4_CC4_CV_FFL_Pos 20 /*!< CCU4_CC4 CV: FFL Position */
\r
3675 #define CCU4_CC4_CV_FFL_Msk (0x01UL << CCU4_CC4_CV_FFL_Pos) /*!< CCU4_CC4 CV: FFL Mask */
\r
3677 /* -------------------------------- CCU4_CC4_INTS ------------------------------- */
\r
3678 #define CCU4_CC4_INTS_PMUS_Pos 0 /*!< CCU4_CC4 INTS: PMUS Position */
\r
3679 #define CCU4_CC4_INTS_PMUS_Msk (0x01UL << CCU4_CC4_INTS_PMUS_Pos) /*!< CCU4_CC4 INTS: PMUS Mask */
\r
3680 #define CCU4_CC4_INTS_OMDS_Pos 1 /*!< CCU4_CC4 INTS: OMDS Position */
\r
3681 #define CCU4_CC4_INTS_OMDS_Msk (0x01UL << CCU4_CC4_INTS_OMDS_Pos) /*!< CCU4_CC4 INTS: OMDS Mask */
\r
3682 #define CCU4_CC4_INTS_CMUS_Pos 2 /*!< CCU4_CC4 INTS: CMUS Position */
\r
3683 #define CCU4_CC4_INTS_CMUS_Msk (0x01UL << CCU4_CC4_INTS_CMUS_Pos) /*!< CCU4_CC4 INTS: CMUS Mask */
\r
3684 #define CCU4_CC4_INTS_CMDS_Pos 3 /*!< CCU4_CC4 INTS: CMDS Position */
\r
3685 #define CCU4_CC4_INTS_CMDS_Msk (0x01UL << CCU4_CC4_INTS_CMDS_Pos) /*!< CCU4_CC4 INTS: CMDS Mask */
\r
3686 #define CCU4_CC4_INTS_E0AS_Pos 8 /*!< CCU4_CC4 INTS: E0AS Position */
\r
3687 #define CCU4_CC4_INTS_E0AS_Msk (0x01UL << CCU4_CC4_INTS_E0AS_Pos) /*!< CCU4_CC4 INTS: E0AS Mask */
\r
3688 #define CCU4_CC4_INTS_E1AS_Pos 9 /*!< CCU4_CC4 INTS: E1AS Position */
\r
3689 #define CCU4_CC4_INTS_E1AS_Msk (0x01UL << CCU4_CC4_INTS_E1AS_Pos) /*!< CCU4_CC4 INTS: E1AS Mask */
\r
3690 #define CCU4_CC4_INTS_E2AS_Pos 10 /*!< CCU4_CC4 INTS: E2AS Position */
\r
3691 #define CCU4_CC4_INTS_E2AS_Msk (0x01UL << CCU4_CC4_INTS_E2AS_Pos) /*!< CCU4_CC4 INTS: E2AS Mask */
\r
3692 #define CCU4_CC4_INTS_TRPF_Pos 11 /*!< CCU4_CC4 INTS: TRPF Position */
\r
3693 #define CCU4_CC4_INTS_TRPF_Msk (0x01UL << CCU4_CC4_INTS_TRPF_Pos) /*!< CCU4_CC4 INTS: TRPF Mask */
\r
3695 /* -------------------------------- CCU4_CC4_INTE ------------------------------- */
\r
3696 #define CCU4_CC4_INTE_PME_Pos 0 /*!< CCU4_CC4 INTE: PME Position */
\r
3697 #define CCU4_CC4_INTE_PME_Msk (0x01UL << CCU4_CC4_INTE_PME_Pos) /*!< CCU4_CC4 INTE: PME Mask */
\r
3698 #define CCU4_CC4_INTE_OME_Pos 1 /*!< CCU4_CC4 INTE: OME Position */
\r
3699 #define CCU4_CC4_INTE_OME_Msk (0x01UL << CCU4_CC4_INTE_OME_Pos) /*!< CCU4_CC4 INTE: OME Mask */
\r
3700 #define CCU4_CC4_INTE_CMUE_Pos 2 /*!< CCU4_CC4 INTE: CMUE Position */
\r
3701 #define CCU4_CC4_INTE_CMUE_Msk (0x01UL << CCU4_CC4_INTE_CMUE_Pos) /*!< CCU4_CC4 INTE: CMUE Mask */
\r
3702 #define CCU4_CC4_INTE_CMDE_Pos 3 /*!< CCU4_CC4 INTE: CMDE Position */
\r
3703 #define CCU4_CC4_INTE_CMDE_Msk (0x01UL << CCU4_CC4_INTE_CMDE_Pos) /*!< CCU4_CC4 INTE: CMDE Mask */
\r
3704 #define CCU4_CC4_INTE_E0AE_Pos 8 /*!< CCU4_CC4 INTE: E0AE Position */
\r
3705 #define CCU4_CC4_INTE_E0AE_Msk (0x01UL << CCU4_CC4_INTE_E0AE_Pos) /*!< CCU4_CC4 INTE: E0AE Mask */
\r
3706 #define CCU4_CC4_INTE_E1AE_Pos 9 /*!< CCU4_CC4 INTE: E1AE Position */
\r
3707 #define CCU4_CC4_INTE_E1AE_Msk (0x01UL << CCU4_CC4_INTE_E1AE_Pos) /*!< CCU4_CC4 INTE: E1AE Mask */
\r
3708 #define CCU4_CC4_INTE_E2AE_Pos 10 /*!< CCU4_CC4 INTE: E2AE Position */
\r
3709 #define CCU4_CC4_INTE_E2AE_Msk (0x01UL << CCU4_CC4_INTE_E2AE_Pos) /*!< CCU4_CC4 INTE: E2AE Mask */
\r
3711 /* -------------------------------- CCU4_CC4_SRS -------------------------------- */
\r
3712 #define CCU4_CC4_SRS_POSR_Pos 0 /*!< CCU4_CC4 SRS: POSR Position */
\r
3713 #define CCU4_CC4_SRS_POSR_Msk (0x03UL << CCU4_CC4_SRS_POSR_Pos) /*!< CCU4_CC4 SRS: POSR Mask */
\r
3714 #define CCU4_CC4_SRS_CMSR_Pos 2 /*!< CCU4_CC4 SRS: CMSR Position */
\r
3715 #define CCU4_CC4_SRS_CMSR_Msk (0x03UL << CCU4_CC4_SRS_CMSR_Pos) /*!< CCU4_CC4 SRS: CMSR Mask */
\r
3716 #define CCU4_CC4_SRS_E0SR_Pos 8 /*!< CCU4_CC4 SRS: E0SR Position */
\r
3717 #define CCU4_CC4_SRS_E0SR_Msk (0x03UL << CCU4_CC4_SRS_E0SR_Pos) /*!< CCU4_CC4 SRS: E0SR Mask */
\r
3718 #define CCU4_CC4_SRS_E1SR_Pos 10 /*!< CCU4_CC4 SRS: E1SR Position */
\r
3719 #define CCU4_CC4_SRS_E1SR_Msk (0x03UL << CCU4_CC4_SRS_E1SR_Pos) /*!< CCU4_CC4 SRS: E1SR Mask */
\r
3720 #define CCU4_CC4_SRS_E2SR_Pos 12 /*!< CCU4_CC4 SRS: E2SR Position */
\r
3721 #define CCU4_CC4_SRS_E2SR_Msk (0x03UL << CCU4_CC4_SRS_E2SR_Pos) /*!< CCU4_CC4 SRS: E2SR Mask */
\r
3723 /* -------------------------------- CCU4_CC4_SWS -------------------------------- */
\r
3724 #define CCU4_CC4_SWS_SPM_Pos 0 /*!< CCU4_CC4 SWS: SPM Position */
\r
3725 #define CCU4_CC4_SWS_SPM_Msk (0x01UL << CCU4_CC4_SWS_SPM_Pos) /*!< CCU4_CC4 SWS: SPM Mask */
\r
3726 #define CCU4_CC4_SWS_SOM_Pos 1 /*!< CCU4_CC4 SWS: SOM Position */
\r
3727 #define CCU4_CC4_SWS_SOM_Msk (0x01UL << CCU4_CC4_SWS_SOM_Pos) /*!< CCU4_CC4 SWS: SOM Mask */
\r
3728 #define CCU4_CC4_SWS_SCMU_Pos 2 /*!< CCU4_CC4 SWS: SCMU Position */
\r
3729 #define CCU4_CC4_SWS_SCMU_Msk (0x01UL << CCU4_CC4_SWS_SCMU_Pos) /*!< CCU4_CC4 SWS: SCMU Mask */
\r
3730 #define CCU4_CC4_SWS_SCMD_Pos 3 /*!< CCU4_CC4 SWS: SCMD Position */
\r
3731 #define CCU4_CC4_SWS_SCMD_Msk (0x01UL << CCU4_CC4_SWS_SCMD_Pos) /*!< CCU4_CC4 SWS: SCMD Mask */
\r
3732 #define CCU4_CC4_SWS_SE0A_Pos 8 /*!< CCU4_CC4 SWS: SE0A Position */
\r
3733 #define CCU4_CC4_SWS_SE0A_Msk (0x01UL << CCU4_CC4_SWS_SE0A_Pos) /*!< CCU4_CC4 SWS: SE0A Mask */
\r
3734 #define CCU4_CC4_SWS_SE1A_Pos 9 /*!< CCU4_CC4 SWS: SE1A Position */
\r
3735 #define CCU4_CC4_SWS_SE1A_Msk (0x01UL << CCU4_CC4_SWS_SE1A_Pos) /*!< CCU4_CC4 SWS: SE1A Mask */
\r
3736 #define CCU4_CC4_SWS_SE2A_Pos 10 /*!< CCU4_CC4 SWS: SE2A Position */
\r
3737 #define CCU4_CC4_SWS_SE2A_Msk (0x01UL << CCU4_CC4_SWS_SE2A_Pos) /*!< CCU4_CC4 SWS: SE2A Mask */
\r
3738 #define CCU4_CC4_SWS_STRPF_Pos 11 /*!< CCU4_CC4 SWS: STRPF Position */
\r
3739 #define CCU4_CC4_SWS_STRPF_Msk (0x01UL << CCU4_CC4_SWS_STRPF_Pos) /*!< CCU4_CC4 SWS: STRPF Mask */
\r
3741 /* -------------------------------- CCU4_CC4_SWR -------------------------------- */
\r
3742 #define CCU4_CC4_SWR_RPM_Pos 0 /*!< CCU4_CC4 SWR: RPM Position */
\r
3743 #define CCU4_CC4_SWR_RPM_Msk (0x01UL << CCU4_CC4_SWR_RPM_Pos) /*!< CCU4_CC4 SWR: RPM Mask */
\r
3744 #define CCU4_CC4_SWR_ROM_Pos 1 /*!< CCU4_CC4 SWR: ROM Position */
\r
3745 #define CCU4_CC4_SWR_ROM_Msk (0x01UL << CCU4_CC4_SWR_ROM_Pos) /*!< CCU4_CC4 SWR: ROM Mask */
\r
3746 #define CCU4_CC4_SWR_RCMU_Pos 2 /*!< CCU4_CC4 SWR: RCMU Position */
\r
3747 #define CCU4_CC4_SWR_RCMU_Msk (0x01UL << CCU4_CC4_SWR_RCMU_Pos) /*!< CCU4_CC4 SWR: RCMU Mask */
\r
3748 #define CCU4_CC4_SWR_RCMD_Pos 3 /*!< CCU4_CC4 SWR: RCMD Position */
\r
3749 #define CCU4_CC4_SWR_RCMD_Msk (0x01UL << CCU4_CC4_SWR_RCMD_Pos) /*!< CCU4_CC4 SWR: RCMD Mask */
\r
3750 #define CCU4_CC4_SWR_RE0A_Pos 8 /*!< CCU4_CC4 SWR: RE0A Position */
\r
3751 #define CCU4_CC4_SWR_RE0A_Msk (0x01UL << CCU4_CC4_SWR_RE0A_Pos) /*!< CCU4_CC4 SWR: RE0A Mask */
\r
3752 #define CCU4_CC4_SWR_RE1A_Pos 9 /*!< CCU4_CC4 SWR: RE1A Position */
\r
3753 #define CCU4_CC4_SWR_RE1A_Msk (0x01UL << CCU4_CC4_SWR_RE1A_Pos) /*!< CCU4_CC4 SWR: RE1A Mask */
\r
3754 #define CCU4_CC4_SWR_RE2A_Pos 10 /*!< CCU4_CC4 SWR: RE2A Position */
\r
3755 #define CCU4_CC4_SWR_RE2A_Msk (0x01UL << CCU4_CC4_SWR_RE2A_Pos) /*!< CCU4_CC4 SWR: RE2A Mask */
\r
3756 #define CCU4_CC4_SWR_RTRPF_Pos 11 /*!< CCU4_CC4 SWR: RTRPF Position */
\r
3757 #define CCU4_CC4_SWR_RTRPF_Msk (0x01UL << CCU4_CC4_SWR_RTRPF_Pos) /*!< CCU4_CC4 SWR: RTRPF Mask */
\r
3759 /* ------------------------------- CCU4_CC4_ECRD0 ------------------------------- */
\r
3760 #define CCU4_CC4_ECRD0_CAPV_Pos 0 /*!< CCU4_CC4 ECRD0: CAPV Position */
\r
3761 #define CCU4_CC4_ECRD0_CAPV_Msk (0x0000ffffUL << CCU4_CC4_ECRD0_CAPV_Pos) /*!< CCU4_CC4 ECRD0: CAPV Mask */
\r
3762 #define CCU4_CC4_ECRD0_FPCV_Pos 16 /*!< CCU4_CC4 ECRD0: FPCV Position */
\r
3763 #define CCU4_CC4_ECRD0_FPCV_Msk (0x0fUL << CCU4_CC4_ECRD0_FPCV_Pos) /*!< CCU4_CC4 ECRD0: FPCV Mask */
\r
3764 #define CCU4_CC4_ECRD0_SPTR_Pos 20 /*!< CCU4_CC4 ECRD0: SPTR Position */
\r
3765 #define CCU4_CC4_ECRD0_SPTR_Msk (0x03UL << CCU4_CC4_ECRD0_SPTR_Pos) /*!< CCU4_CC4 ECRD0: SPTR Mask */
\r
3766 #define CCU4_CC4_ECRD0_VPTR_Pos 22 /*!< CCU4_CC4 ECRD0: VPTR Position */
\r
3767 #define CCU4_CC4_ECRD0_VPTR_Msk (0x03UL << CCU4_CC4_ECRD0_VPTR_Pos) /*!< CCU4_CC4 ECRD0: VPTR Mask */
\r
3768 #define CCU4_CC4_ECRD0_FFL_Pos 24 /*!< CCU4_CC4 ECRD0: FFL Position */
\r
3769 #define CCU4_CC4_ECRD0_FFL_Msk (0x01UL << CCU4_CC4_ECRD0_FFL_Pos) /*!< CCU4_CC4 ECRD0: FFL Mask */
\r
3770 #define CCU4_CC4_ECRD0_LCV_Pos 25 /*!< CCU4_CC4 ECRD0: LCV Position */
\r
3771 #define CCU4_CC4_ECRD0_LCV_Msk (0x01UL << CCU4_CC4_ECRD0_LCV_Pos) /*!< CCU4_CC4 ECRD0: LCV Mask */
\r
3773 /* ------------------------------- CCU4_CC4_ECRD1 ------------------------------- */
\r
3774 #define CCU4_CC4_ECRD1_CAPV_Pos 0 /*!< CCU4_CC4 ECRD1: CAPV Position */
\r
3775 #define CCU4_CC4_ECRD1_CAPV_Msk (0x0000ffffUL << CCU4_CC4_ECRD1_CAPV_Pos) /*!< CCU4_CC4 ECRD1: CAPV Mask */
\r
3776 #define CCU4_CC4_ECRD1_FPCV_Pos 16 /*!< CCU4_CC4 ECRD1: FPCV Position */
\r
3777 #define CCU4_CC4_ECRD1_FPCV_Msk (0x0fUL << CCU4_CC4_ECRD1_FPCV_Pos) /*!< CCU4_CC4 ECRD1: FPCV Mask */
\r
3778 #define CCU4_CC4_ECRD1_SPTR_Pos 20 /*!< CCU4_CC4 ECRD1: SPTR Position */
\r
3779 #define CCU4_CC4_ECRD1_SPTR_Msk (0x03UL << CCU4_CC4_ECRD1_SPTR_Pos) /*!< CCU4_CC4 ECRD1: SPTR Mask */
\r
3780 #define CCU4_CC4_ECRD1_VPTR_Pos 22 /*!< CCU4_CC4 ECRD1: VPTR Position */
\r
3781 #define CCU4_CC4_ECRD1_VPTR_Msk (0x03UL << CCU4_CC4_ECRD1_VPTR_Pos) /*!< CCU4_CC4 ECRD1: VPTR Mask */
\r
3782 #define CCU4_CC4_ECRD1_FFL_Pos 24 /*!< CCU4_CC4 ECRD1: FFL Position */
\r
3783 #define CCU4_CC4_ECRD1_FFL_Msk (0x01UL << CCU4_CC4_ECRD1_FFL_Pos) /*!< CCU4_CC4 ECRD1: FFL Mask */
\r
3784 #define CCU4_CC4_ECRD1_LCV_Pos 25 /*!< CCU4_CC4 ECRD1: LCV Position */
\r
3785 #define CCU4_CC4_ECRD1_LCV_Msk (0x01UL << CCU4_CC4_ECRD1_LCV_Pos) /*!< CCU4_CC4 ECRD1: LCV Mask */
\r
3788 /* ================================================================================ */
\r
3789 /* ================ Group 'CCU8' Position & Mask ================ */
\r
3790 /* ================================================================================ */
\r
3793 /* --------------------------------- CCU8_GCTRL --------------------------------- */
\r
3794 #define CCU8_GCTRL_PRBC_Pos 0 /*!< CCU8 GCTRL: PRBC Position */
\r
3795 #define CCU8_GCTRL_PRBC_Msk (0x07UL << CCU8_GCTRL_PRBC_Pos) /*!< CCU8 GCTRL: PRBC Mask */
\r
3796 #define CCU8_GCTRL_PCIS_Pos 4 /*!< CCU8 GCTRL: PCIS Position */
\r
3797 #define CCU8_GCTRL_PCIS_Msk (0x03UL << CCU8_GCTRL_PCIS_Pos) /*!< CCU8 GCTRL: PCIS Mask */
\r
3798 #define CCU8_GCTRL_SUSCFG_Pos 8 /*!< CCU8 GCTRL: SUSCFG Position */
\r
3799 #define CCU8_GCTRL_SUSCFG_Msk (0x03UL << CCU8_GCTRL_SUSCFG_Pos) /*!< CCU8 GCTRL: SUSCFG Mask */
\r
3800 #define CCU8_GCTRL_MSE0_Pos 10 /*!< CCU8 GCTRL: MSE0 Position */
\r
3801 #define CCU8_GCTRL_MSE0_Msk (0x01UL << CCU8_GCTRL_MSE0_Pos) /*!< CCU8 GCTRL: MSE0 Mask */
\r
3802 #define CCU8_GCTRL_MSE1_Pos 11 /*!< CCU8 GCTRL: MSE1 Position */
\r
3803 #define CCU8_GCTRL_MSE1_Msk (0x01UL << CCU8_GCTRL_MSE1_Pos) /*!< CCU8 GCTRL: MSE1 Mask */
\r
3804 #define CCU8_GCTRL_MSE2_Pos 12 /*!< CCU8 GCTRL: MSE2 Position */
\r
3805 #define CCU8_GCTRL_MSE2_Msk (0x01UL << CCU8_GCTRL_MSE2_Pos) /*!< CCU8 GCTRL: MSE2 Mask */
\r
3806 #define CCU8_GCTRL_MSE3_Pos 13 /*!< CCU8 GCTRL: MSE3 Position */
\r
3807 #define CCU8_GCTRL_MSE3_Msk (0x01UL << CCU8_GCTRL_MSE3_Pos) /*!< CCU8 GCTRL: MSE3 Mask */
\r
3808 #define CCU8_GCTRL_MSDE_Pos 14 /*!< CCU8 GCTRL: MSDE Position */
\r
3809 #define CCU8_GCTRL_MSDE_Msk (0x03UL << CCU8_GCTRL_MSDE_Pos) /*!< CCU8 GCTRL: MSDE Mask */
\r
3811 /* --------------------------------- CCU8_GSTAT --------------------------------- */
\r
3812 #define CCU8_GSTAT_S0I_Pos 0 /*!< CCU8 GSTAT: S0I Position */
\r
3813 #define CCU8_GSTAT_S0I_Msk (0x01UL << CCU8_GSTAT_S0I_Pos) /*!< CCU8 GSTAT: S0I Mask */
\r
3814 #define CCU8_GSTAT_S1I_Pos 1 /*!< CCU8 GSTAT: S1I Position */
\r
3815 #define CCU8_GSTAT_S1I_Msk (0x01UL << CCU8_GSTAT_S1I_Pos) /*!< CCU8 GSTAT: S1I Mask */
\r
3816 #define CCU8_GSTAT_S2I_Pos 2 /*!< CCU8 GSTAT: S2I Position */
\r
3817 #define CCU8_GSTAT_S2I_Msk (0x01UL << CCU8_GSTAT_S2I_Pos) /*!< CCU8 GSTAT: S2I Mask */
\r
3818 #define CCU8_GSTAT_S3I_Pos 3 /*!< CCU8 GSTAT: S3I Position */
\r
3819 #define CCU8_GSTAT_S3I_Msk (0x01UL << CCU8_GSTAT_S3I_Pos) /*!< CCU8 GSTAT: S3I Mask */
\r
3820 #define CCU8_GSTAT_PRB_Pos 8 /*!< CCU8 GSTAT: PRB Position */
\r
3821 #define CCU8_GSTAT_PRB_Msk (0x01UL << CCU8_GSTAT_PRB_Pos) /*!< CCU8 GSTAT: PRB Mask */
\r
3822 #define CCU8_GSTAT_PCRB_Pos 10 /*!< CCU8 GSTAT: PCRB Position */
\r
3823 #define CCU8_GSTAT_PCRB_Msk (0x01UL << CCU8_GSTAT_PCRB_Pos) /*!< CCU8 GSTAT: PCRB Mask */
\r
3825 /* --------------------------------- CCU8_GIDLS --------------------------------- */
\r
3826 #define CCU8_GIDLS_SS0I_Pos 0 /*!< CCU8 GIDLS: SS0I Position */
\r
3827 #define CCU8_GIDLS_SS0I_Msk (0x01UL << CCU8_GIDLS_SS0I_Pos) /*!< CCU8 GIDLS: SS0I Mask */
\r
3828 #define CCU8_GIDLS_SS1I_Pos 1 /*!< CCU8 GIDLS: SS1I Position */
\r
3829 #define CCU8_GIDLS_SS1I_Msk (0x01UL << CCU8_GIDLS_SS1I_Pos) /*!< CCU8 GIDLS: SS1I Mask */
\r
3830 #define CCU8_GIDLS_SS2I_Pos 2 /*!< CCU8 GIDLS: SS2I Position */
\r
3831 #define CCU8_GIDLS_SS2I_Msk (0x01UL << CCU8_GIDLS_SS2I_Pos) /*!< CCU8 GIDLS: SS2I Mask */
\r
3832 #define CCU8_GIDLS_SS3I_Pos 3 /*!< CCU8 GIDLS: SS3I Position */
\r
3833 #define CCU8_GIDLS_SS3I_Msk (0x01UL << CCU8_GIDLS_SS3I_Pos) /*!< CCU8 GIDLS: SS3I Mask */
\r
3834 #define CCU8_GIDLS_CPRB_Pos 8 /*!< CCU8 GIDLS: CPRB Position */
\r
3835 #define CCU8_GIDLS_CPRB_Msk (0x01UL << CCU8_GIDLS_CPRB_Pos) /*!< CCU8 GIDLS: CPRB Mask */
\r
3836 #define CCU8_GIDLS_PSIC_Pos 9 /*!< CCU8 GIDLS: PSIC Position */
\r
3837 #define CCU8_GIDLS_PSIC_Msk (0x01UL << CCU8_GIDLS_PSIC_Pos) /*!< CCU8 GIDLS: PSIC Mask */
\r
3838 #define CCU8_GIDLS_CPCH_Pos 10 /*!< CCU8 GIDLS: CPCH Position */
\r
3839 #define CCU8_GIDLS_CPCH_Msk (0x01UL << CCU8_GIDLS_CPCH_Pos) /*!< CCU8 GIDLS: CPCH Mask */
\r
3841 /* --------------------------------- CCU8_GIDLC --------------------------------- */
\r
3842 #define CCU8_GIDLC_CS0I_Pos 0 /*!< CCU8 GIDLC: CS0I Position */
\r
3843 #define CCU8_GIDLC_CS0I_Msk (0x01UL << CCU8_GIDLC_CS0I_Pos) /*!< CCU8 GIDLC: CS0I Mask */
\r
3844 #define CCU8_GIDLC_CS1I_Pos 1 /*!< CCU8 GIDLC: CS1I Position */
\r
3845 #define CCU8_GIDLC_CS1I_Msk (0x01UL << CCU8_GIDLC_CS1I_Pos) /*!< CCU8 GIDLC: CS1I Mask */
\r
3846 #define CCU8_GIDLC_CS2I_Pos 2 /*!< CCU8 GIDLC: CS2I Position */
\r
3847 #define CCU8_GIDLC_CS2I_Msk (0x01UL << CCU8_GIDLC_CS2I_Pos) /*!< CCU8 GIDLC: CS2I Mask */
\r
3848 #define CCU8_GIDLC_CS3I_Pos 3 /*!< CCU8 GIDLC: CS3I Position */
\r
3849 #define CCU8_GIDLC_CS3I_Msk (0x01UL << CCU8_GIDLC_CS3I_Pos) /*!< CCU8 GIDLC: CS3I Mask */
\r
3850 #define CCU8_GIDLC_SPRB_Pos 8 /*!< CCU8 GIDLC: SPRB Position */
\r
3851 #define CCU8_GIDLC_SPRB_Msk (0x01UL << CCU8_GIDLC_SPRB_Pos) /*!< CCU8 GIDLC: SPRB Mask */
\r
3852 #define CCU8_GIDLC_SPCH_Pos 10 /*!< CCU8 GIDLC: SPCH Position */
\r
3853 #define CCU8_GIDLC_SPCH_Msk (0x01UL << CCU8_GIDLC_SPCH_Pos) /*!< CCU8 GIDLC: SPCH Mask */
\r
3855 /* ---------------------------------- CCU8_GCSS --------------------------------- */
\r
3856 #define CCU8_GCSS_S0SE_Pos 0 /*!< CCU8 GCSS: S0SE Position */
\r
3857 #define CCU8_GCSS_S0SE_Msk (0x01UL << CCU8_GCSS_S0SE_Pos) /*!< CCU8 GCSS: S0SE Mask */
\r
3858 #define CCU8_GCSS_S0DSE_Pos 1 /*!< CCU8 GCSS: S0DSE Position */
\r
3859 #define CCU8_GCSS_S0DSE_Msk (0x01UL << CCU8_GCSS_S0DSE_Pos) /*!< CCU8 GCSS: S0DSE Mask */
\r
3860 #define CCU8_GCSS_S0PSE_Pos 2 /*!< CCU8 GCSS: S0PSE Position */
\r
3861 #define CCU8_GCSS_S0PSE_Msk (0x01UL << CCU8_GCSS_S0PSE_Pos) /*!< CCU8 GCSS: S0PSE Mask */
\r
3862 #define CCU8_GCSS_S1SE_Pos 4 /*!< CCU8 GCSS: S1SE Position */
\r
3863 #define CCU8_GCSS_S1SE_Msk (0x01UL << CCU8_GCSS_S1SE_Pos) /*!< CCU8 GCSS: S1SE Mask */
\r
3864 #define CCU8_GCSS_S1DSE_Pos 5 /*!< CCU8 GCSS: S1DSE Position */
\r
3865 #define CCU8_GCSS_S1DSE_Msk (0x01UL << CCU8_GCSS_S1DSE_Pos) /*!< CCU8 GCSS: S1DSE Mask */
\r
3866 #define CCU8_GCSS_S1PSE_Pos 6 /*!< CCU8 GCSS: S1PSE Position */
\r
3867 #define CCU8_GCSS_S1PSE_Msk (0x01UL << CCU8_GCSS_S1PSE_Pos) /*!< CCU8 GCSS: S1PSE Mask */
\r
3868 #define CCU8_GCSS_S2SE_Pos 8 /*!< CCU8 GCSS: S2SE Position */
\r
3869 #define CCU8_GCSS_S2SE_Msk (0x01UL << CCU8_GCSS_S2SE_Pos) /*!< CCU8 GCSS: S2SE Mask */
\r
3870 #define CCU8_GCSS_S2DSE_Pos 9 /*!< CCU8 GCSS: S2DSE Position */
\r
3871 #define CCU8_GCSS_S2DSE_Msk (0x01UL << CCU8_GCSS_S2DSE_Pos) /*!< CCU8 GCSS: S2DSE Mask */
\r
3872 #define CCU8_GCSS_S2PSE_Pos 10 /*!< CCU8 GCSS: S2PSE Position */
\r
3873 #define CCU8_GCSS_S2PSE_Msk (0x01UL << CCU8_GCSS_S2PSE_Pos) /*!< CCU8 GCSS: S2PSE Mask */
\r
3874 #define CCU8_GCSS_S3SE_Pos 12 /*!< CCU8 GCSS: S3SE Position */
\r
3875 #define CCU8_GCSS_S3SE_Msk (0x01UL << CCU8_GCSS_S3SE_Pos) /*!< CCU8 GCSS: S3SE Mask */
\r
3876 #define CCU8_GCSS_S3DSE_Pos 13 /*!< CCU8 GCSS: S3DSE Position */
\r
3877 #define CCU8_GCSS_S3DSE_Msk (0x01UL << CCU8_GCSS_S3DSE_Pos) /*!< CCU8 GCSS: S3DSE Mask */
\r
3878 #define CCU8_GCSS_S3PSE_Pos 14 /*!< CCU8 GCSS: S3PSE Position */
\r
3879 #define CCU8_GCSS_S3PSE_Msk (0x01UL << CCU8_GCSS_S3PSE_Pos) /*!< CCU8 GCSS: S3PSE Mask */
\r
3880 #define CCU8_GCSS_S0ST1S_Pos 16 /*!< CCU8 GCSS: S0ST1S Position */
\r
3881 #define CCU8_GCSS_S0ST1S_Msk (0x01UL << CCU8_GCSS_S0ST1S_Pos) /*!< CCU8 GCSS: S0ST1S Mask */
\r
3882 #define CCU8_GCSS_S1ST1S_Pos 17 /*!< CCU8 GCSS: S1ST1S Position */
\r
3883 #define CCU8_GCSS_S1ST1S_Msk (0x01UL << CCU8_GCSS_S1ST1S_Pos) /*!< CCU8 GCSS: S1ST1S Mask */
\r
3884 #define CCU8_GCSS_S2ST1S_Pos 18 /*!< CCU8 GCSS: S2ST1S Position */
\r
3885 #define CCU8_GCSS_S2ST1S_Msk (0x01UL << CCU8_GCSS_S2ST1S_Pos) /*!< CCU8 GCSS: S2ST1S Mask */
\r
3886 #define CCU8_GCSS_S3ST1S_Pos 19 /*!< CCU8 GCSS: S3ST1S Position */
\r
3887 #define CCU8_GCSS_S3ST1S_Msk (0x01UL << CCU8_GCSS_S3ST1S_Pos) /*!< CCU8 GCSS: S3ST1S Mask */
\r
3888 #define CCU8_GCSS_S0ST2S_Pos 20 /*!< CCU8 GCSS: S0ST2S Position */
\r
3889 #define CCU8_GCSS_S0ST2S_Msk (0x01UL << CCU8_GCSS_S0ST2S_Pos) /*!< CCU8 GCSS: S0ST2S Mask */
\r
3890 #define CCU8_GCSS_S1ST2S_Pos 21 /*!< CCU8 GCSS: S1ST2S Position */
\r
3891 #define CCU8_GCSS_S1ST2S_Msk (0x01UL << CCU8_GCSS_S1ST2S_Pos) /*!< CCU8 GCSS: S1ST2S Mask */
\r
3892 #define CCU8_GCSS_S2ST2S_Pos 22 /*!< CCU8 GCSS: S2ST2S Position */
\r
3893 #define CCU8_GCSS_S2ST2S_Msk (0x01UL << CCU8_GCSS_S2ST2S_Pos) /*!< CCU8 GCSS: S2ST2S Mask */
\r
3894 #define CCU8_GCSS_S3ST2S_Pos 23 /*!< CCU8 GCSS: S3ST2S Position */
\r
3895 #define CCU8_GCSS_S3ST2S_Msk (0x01UL << CCU8_GCSS_S3ST2S_Pos) /*!< CCU8 GCSS: S3ST2S Mask */
\r
3897 /* ---------------------------------- CCU8_GCSC --------------------------------- */
\r
3898 #define CCU8_GCSC_S0SC_Pos 0 /*!< CCU8 GCSC: S0SC Position */
\r
3899 #define CCU8_GCSC_S0SC_Msk (0x01UL << CCU8_GCSC_S0SC_Pos) /*!< CCU8 GCSC: S0SC Mask */
\r
3900 #define CCU8_GCSC_S0DSC_Pos 1 /*!< CCU8 GCSC: S0DSC Position */
\r
3901 #define CCU8_GCSC_S0DSC_Msk (0x01UL << CCU8_GCSC_S0DSC_Pos) /*!< CCU8 GCSC: S0DSC Mask */
\r
3902 #define CCU8_GCSC_S0PSC_Pos 2 /*!< CCU8 GCSC: S0PSC Position */
\r
3903 #define CCU8_GCSC_S0PSC_Msk (0x01UL << CCU8_GCSC_S0PSC_Pos) /*!< CCU8 GCSC: S0PSC Mask */
\r
3904 #define CCU8_GCSC_S1SC_Pos 4 /*!< CCU8 GCSC: S1SC Position */
\r
3905 #define CCU8_GCSC_S1SC_Msk (0x01UL << CCU8_GCSC_S1SC_Pos) /*!< CCU8 GCSC: S1SC Mask */
\r
3906 #define CCU8_GCSC_S1DSC_Pos 5 /*!< CCU8 GCSC: S1DSC Position */
\r
3907 #define CCU8_GCSC_S1DSC_Msk (0x01UL << CCU8_GCSC_S1DSC_Pos) /*!< CCU8 GCSC: S1DSC Mask */
\r
3908 #define CCU8_GCSC_S1PSC_Pos 6 /*!< CCU8 GCSC: S1PSC Position */
\r
3909 #define CCU8_GCSC_S1PSC_Msk (0x01UL << CCU8_GCSC_S1PSC_Pos) /*!< CCU8 GCSC: S1PSC Mask */
\r
3910 #define CCU8_GCSC_S2SC_Pos 8 /*!< CCU8 GCSC: S2SC Position */
\r
3911 #define CCU8_GCSC_S2SC_Msk (0x01UL << CCU8_GCSC_S2SC_Pos) /*!< CCU8 GCSC: S2SC Mask */
\r
3912 #define CCU8_GCSC_S2DSC_Pos 9 /*!< CCU8 GCSC: S2DSC Position */
\r
3913 #define CCU8_GCSC_S2DSC_Msk (0x01UL << CCU8_GCSC_S2DSC_Pos) /*!< CCU8 GCSC: S2DSC Mask */
\r
3914 #define CCU8_GCSC_S2PSC_Pos 10 /*!< CCU8 GCSC: S2PSC Position */
\r
3915 #define CCU8_GCSC_S2PSC_Msk (0x01UL << CCU8_GCSC_S2PSC_Pos) /*!< CCU8 GCSC: S2PSC Mask */
\r
3916 #define CCU8_GCSC_S3SC_Pos 12 /*!< CCU8 GCSC: S3SC Position */
\r
3917 #define CCU8_GCSC_S3SC_Msk (0x01UL << CCU8_GCSC_S3SC_Pos) /*!< CCU8 GCSC: S3SC Mask */
\r
3918 #define CCU8_GCSC_S3DSC_Pos 13 /*!< CCU8 GCSC: S3DSC Position */
\r
3919 #define CCU8_GCSC_S3DSC_Msk (0x01UL << CCU8_GCSC_S3DSC_Pos) /*!< CCU8 GCSC: S3DSC Mask */
\r
3920 #define CCU8_GCSC_S3PSC_Pos 14 /*!< CCU8 GCSC: S3PSC Position */
\r
3921 #define CCU8_GCSC_S3PSC_Msk (0x01UL << CCU8_GCSC_S3PSC_Pos) /*!< CCU8 GCSC: S3PSC Mask */
\r
3922 #define CCU8_GCSC_S0ST1C_Pos 16 /*!< CCU8 GCSC: S0ST1C Position */
\r
3923 #define CCU8_GCSC_S0ST1C_Msk (0x01UL << CCU8_GCSC_S0ST1C_Pos) /*!< CCU8 GCSC: S0ST1C Mask */
\r
3924 #define CCU8_GCSC_S1ST1C_Pos 17 /*!< CCU8 GCSC: S1ST1C Position */
\r
3925 #define CCU8_GCSC_S1ST1C_Msk (0x01UL << CCU8_GCSC_S1ST1C_Pos) /*!< CCU8 GCSC: S1ST1C Mask */
\r
3926 #define CCU8_GCSC_S2ST1C_Pos 18 /*!< CCU8 GCSC: S2ST1C Position */
\r
3927 #define CCU8_GCSC_S2ST1C_Msk (0x01UL << CCU8_GCSC_S2ST1C_Pos) /*!< CCU8 GCSC: S2ST1C Mask */
\r
3928 #define CCU8_GCSC_S3ST1C_Pos 19 /*!< CCU8 GCSC: S3ST1C Position */
\r
3929 #define CCU8_GCSC_S3ST1C_Msk (0x01UL << CCU8_GCSC_S3ST1C_Pos) /*!< CCU8 GCSC: S3ST1C Mask */
\r
3930 #define CCU8_GCSC_S0ST2C_Pos 20 /*!< CCU8 GCSC: S0ST2C Position */
\r
3931 #define CCU8_GCSC_S0ST2C_Msk (0x01UL << CCU8_GCSC_S0ST2C_Pos) /*!< CCU8 GCSC: S0ST2C Mask */
\r
3932 #define CCU8_GCSC_S1ST2C_Pos 21 /*!< CCU8 GCSC: S1ST2C Position */
\r
3933 #define CCU8_GCSC_S1ST2C_Msk (0x01UL << CCU8_GCSC_S1ST2C_Pos) /*!< CCU8 GCSC: S1ST2C Mask */
\r
3934 #define CCU8_GCSC_S2ST2C_Pos 22 /*!< CCU8 GCSC: S2ST2C Position */
\r
3935 #define CCU8_GCSC_S2ST2C_Msk (0x01UL << CCU8_GCSC_S2ST2C_Pos) /*!< CCU8 GCSC: S2ST2C Mask */
\r
3936 #define CCU8_GCSC_S3ST2C_Pos 23 /*!< CCU8 GCSC: S3ST2C Position */
\r
3937 #define CCU8_GCSC_S3ST2C_Msk (0x01UL << CCU8_GCSC_S3ST2C_Pos) /*!< CCU8 GCSC: S3ST2C Mask */
\r
3939 /* ---------------------------------- CCU8_GCST --------------------------------- */
\r
3940 #define CCU8_GCST_S0SS_Pos 0 /*!< CCU8 GCST: S0SS Position */
\r
3941 #define CCU8_GCST_S0SS_Msk (0x01UL << CCU8_GCST_S0SS_Pos) /*!< CCU8 GCST: S0SS Mask */
\r
3942 #define CCU8_GCST_S0DSS_Pos 1 /*!< CCU8 GCST: S0DSS Position */
\r
3943 #define CCU8_GCST_S0DSS_Msk (0x01UL << CCU8_GCST_S0DSS_Pos) /*!< CCU8 GCST: S0DSS Mask */
\r
3944 #define CCU8_GCST_S0PSS_Pos 2 /*!< CCU8 GCST: S0PSS Position */
\r
3945 #define CCU8_GCST_S0PSS_Msk (0x01UL << CCU8_GCST_S0PSS_Pos) /*!< CCU8 GCST: S0PSS Mask */
\r
3946 #define CCU8_GCST_S1SS_Pos 4 /*!< CCU8 GCST: S1SS Position */
\r
3947 #define CCU8_GCST_S1SS_Msk (0x01UL << CCU8_GCST_S1SS_Pos) /*!< CCU8 GCST: S1SS Mask */
\r
3948 #define CCU8_GCST_S1DSS_Pos 5 /*!< CCU8 GCST: S1DSS Position */
\r
3949 #define CCU8_GCST_S1DSS_Msk (0x01UL << CCU8_GCST_S1DSS_Pos) /*!< CCU8 GCST: S1DSS Mask */
\r
3950 #define CCU8_GCST_S1PSS_Pos 6 /*!< CCU8 GCST: S1PSS Position */
\r
3951 #define CCU8_GCST_S1PSS_Msk (0x01UL << CCU8_GCST_S1PSS_Pos) /*!< CCU8 GCST: S1PSS Mask */
\r
3952 #define CCU8_GCST_S2SS_Pos 8 /*!< CCU8 GCST: S2SS Position */
\r
3953 #define CCU8_GCST_S2SS_Msk (0x01UL << CCU8_GCST_S2SS_Pos) /*!< CCU8 GCST: S2SS Mask */
\r
3954 #define CCU8_GCST_S2DSS_Pos 9 /*!< CCU8 GCST: S2DSS Position */
\r
3955 #define CCU8_GCST_S2DSS_Msk (0x01UL << CCU8_GCST_S2DSS_Pos) /*!< CCU8 GCST: S2DSS Mask */
\r
3956 #define CCU8_GCST_S2PSS_Pos 10 /*!< CCU8 GCST: S2PSS Position */
\r
3957 #define CCU8_GCST_S2PSS_Msk (0x01UL << CCU8_GCST_S2PSS_Pos) /*!< CCU8 GCST: S2PSS Mask */
\r
3958 #define CCU8_GCST_S3SS_Pos 12 /*!< CCU8 GCST: S3SS Position */
\r
3959 #define CCU8_GCST_S3SS_Msk (0x01UL << CCU8_GCST_S3SS_Pos) /*!< CCU8 GCST: S3SS Mask */
\r
3960 #define CCU8_GCST_S3DSS_Pos 13 /*!< CCU8 GCST: S3DSS Position */
\r
3961 #define CCU8_GCST_S3DSS_Msk (0x01UL << CCU8_GCST_S3DSS_Pos) /*!< CCU8 GCST: S3DSS Mask */
\r
3962 #define CCU8_GCST_S3PSS_Pos 14 /*!< CCU8 GCST: S3PSS Position */
\r
3963 #define CCU8_GCST_S3PSS_Msk (0x01UL << CCU8_GCST_S3PSS_Pos) /*!< CCU8 GCST: S3PSS Mask */
\r
3964 #define CCU8_GCST_CC80ST1_Pos 16 /*!< CCU8 GCST: CC80ST1 Position */
\r
3965 #define CCU8_GCST_CC80ST1_Msk (0x01UL << CCU8_GCST_CC80ST1_Pos) /*!< CCU8 GCST: CC80ST1 Mask */
\r
3966 #define CCU8_GCST_CC81ST1_Pos 17 /*!< CCU8 GCST: CC81ST1 Position */
\r
3967 #define CCU8_GCST_CC81ST1_Msk (0x01UL << CCU8_GCST_CC81ST1_Pos) /*!< CCU8 GCST: CC81ST1 Mask */
\r
3968 #define CCU8_GCST_CC82ST1_Pos 18 /*!< CCU8 GCST: CC82ST1 Position */
\r
3969 #define CCU8_GCST_CC82ST1_Msk (0x01UL << CCU8_GCST_CC82ST1_Pos) /*!< CCU8 GCST: CC82ST1 Mask */
\r
3970 #define CCU8_GCST_CC83ST1_Pos 19 /*!< CCU8 GCST: CC83ST1 Position */
\r
3971 #define CCU8_GCST_CC83ST1_Msk (0x01UL << CCU8_GCST_CC83ST1_Pos) /*!< CCU8 GCST: CC83ST1 Mask */
\r
3972 #define CCU8_GCST_CC80ST2_Pos 20 /*!< CCU8 GCST: CC80ST2 Position */
\r
3973 #define CCU8_GCST_CC80ST2_Msk (0x01UL << CCU8_GCST_CC80ST2_Pos) /*!< CCU8 GCST: CC80ST2 Mask */
\r
3974 #define CCU8_GCST_CC81ST2_Pos 21 /*!< CCU8 GCST: CC81ST2 Position */
\r
3975 #define CCU8_GCST_CC81ST2_Msk (0x01UL << CCU8_GCST_CC81ST2_Pos) /*!< CCU8 GCST: CC81ST2 Mask */
\r
3976 #define CCU8_GCST_CC82ST2_Pos 22 /*!< CCU8 GCST: CC82ST2 Position */
\r
3977 #define CCU8_GCST_CC82ST2_Msk (0x01UL << CCU8_GCST_CC82ST2_Pos) /*!< CCU8 GCST: CC82ST2 Mask */
\r
3978 #define CCU8_GCST_CC83ST2_Pos 23 /*!< CCU8 GCST: CC83ST2 Position */
\r
3979 #define CCU8_GCST_CC83ST2_Msk (0x01UL << CCU8_GCST_CC83ST2_Pos) /*!< CCU8 GCST: CC83ST2 Mask */
\r
3981 /* --------------------------------- CCU8_GPCHK --------------------------------- */
\r
3982 #define CCU8_GPCHK_PASE_Pos 0 /*!< CCU8 GPCHK: PASE Position */
\r
3983 #define CCU8_GPCHK_PASE_Msk (0x01UL << CCU8_GPCHK_PASE_Pos) /*!< CCU8 GPCHK: PASE Mask */
\r
3984 #define CCU8_GPCHK_PACS_Pos 1 /*!< CCU8 GPCHK: PACS Position */
\r
3985 #define CCU8_GPCHK_PACS_Msk (0x03UL << CCU8_GPCHK_PACS_Pos) /*!< CCU8 GPCHK: PACS Mask */
\r
3986 #define CCU8_GPCHK_PISEL_Pos 3 /*!< CCU8 GPCHK: PISEL Position */
\r
3987 #define CCU8_GPCHK_PISEL_Msk (0x03UL << CCU8_GPCHK_PISEL_Pos) /*!< CCU8 GPCHK: PISEL Mask */
\r
3988 #define CCU8_GPCHK_PCDS_Pos 5 /*!< CCU8 GPCHK: PCDS Position */
\r
3989 #define CCU8_GPCHK_PCDS_Msk (0x03UL << CCU8_GPCHK_PCDS_Pos) /*!< CCU8 GPCHK: PCDS Mask */
\r
3990 #define CCU8_GPCHK_PCTS_Pos 7 /*!< CCU8 GPCHK: PCTS Position */
\r
3991 #define CCU8_GPCHK_PCTS_Msk (0x01UL << CCU8_GPCHK_PCTS_Pos) /*!< CCU8 GPCHK: PCTS Mask */
\r
3992 #define CCU8_GPCHK_PCST_Pos 15 /*!< CCU8 GPCHK: PCST Position */
\r
3993 #define CCU8_GPCHK_PCST_Msk (0x01UL << CCU8_GPCHK_PCST_Pos) /*!< CCU8 GPCHK: PCST Mask */
\r
3994 #define CCU8_GPCHK_PCSEL0_Pos 16 /*!< CCU8 GPCHK: PCSEL0 Position */
\r
3995 #define CCU8_GPCHK_PCSEL0_Msk (0x0fUL << CCU8_GPCHK_PCSEL0_Pos) /*!< CCU8 GPCHK: PCSEL0 Mask */
\r
3996 #define CCU8_GPCHK_PCSEL1_Pos 20 /*!< CCU8 GPCHK: PCSEL1 Position */
\r
3997 #define CCU8_GPCHK_PCSEL1_Msk (0x0fUL << CCU8_GPCHK_PCSEL1_Pos) /*!< CCU8 GPCHK: PCSEL1 Mask */
\r
3998 #define CCU8_GPCHK_PCSEL2_Pos 24 /*!< CCU8 GPCHK: PCSEL2 Position */
\r
3999 #define CCU8_GPCHK_PCSEL2_Msk (0x0fUL << CCU8_GPCHK_PCSEL2_Pos) /*!< CCU8 GPCHK: PCSEL2 Mask */
\r
4000 #define CCU8_GPCHK_PCSEL3_Pos 28 /*!< CCU8 GPCHK: PCSEL3 Position */
\r
4001 #define CCU8_GPCHK_PCSEL3_Msk (0x0fUL << CCU8_GPCHK_PCSEL3_Pos) /*!< CCU8 GPCHK: PCSEL3 Mask */
\r
4003 /* ---------------------------------- CCU8_MIDR --------------------------------- */
\r
4004 #define CCU8_MIDR_MODR_Pos 0 /*!< CCU8 MIDR: MODR Position */
\r
4005 #define CCU8_MIDR_MODR_Msk (0x000000ffUL << CCU8_MIDR_MODR_Pos) /*!< CCU8 MIDR: MODR Mask */
\r
4006 #define CCU8_MIDR_MODT_Pos 8 /*!< CCU8 MIDR: MODT Position */
\r
4007 #define CCU8_MIDR_MODT_Msk (0x000000ffUL << CCU8_MIDR_MODT_Pos) /*!< CCU8 MIDR: MODT Mask */
\r
4008 #define CCU8_MIDR_MODN_Pos 16 /*!< CCU8 MIDR: MODN Position */
\r
4009 #define CCU8_MIDR_MODN_Msk (0x0000ffffUL << CCU8_MIDR_MODN_Pos) /*!< CCU8 MIDR: MODN Mask */
\r
4012 /* ================================================================================ */
\r
4013 /* ================ Group 'CCU8_CC8' Position & Mask ================ */
\r
4014 /* ================================================================================ */
\r
4017 /* -------------------------------- CCU8_CC8_INS -------------------------------- */
\r
4018 #define CCU8_CC8_INS_EV0IS_Pos 0 /*!< CCU8_CC8 INS: EV0IS Position */
\r
4019 #define CCU8_CC8_INS_EV0IS_Msk (0x0fUL << CCU8_CC8_INS_EV0IS_Pos) /*!< CCU8_CC8 INS: EV0IS Mask */
\r
4020 #define CCU8_CC8_INS_EV1IS_Pos 4 /*!< CCU8_CC8 INS: EV1IS Position */
\r
4021 #define CCU8_CC8_INS_EV1IS_Msk (0x0fUL << CCU8_CC8_INS_EV1IS_Pos) /*!< CCU8_CC8 INS: EV1IS Mask */
\r
4022 #define CCU8_CC8_INS_EV2IS_Pos 8 /*!< CCU8_CC8 INS: EV2IS Position */
\r
4023 #define CCU8_CC8_INS_EV2IS_Msk (0x0fUL << CCU8_CC8_INS_EV2IS_Pos) /*!< CCU8_CC8 INS: EV2IS Mask */
\r
4024 #define CCU8_CC8_INS_EV0EM_Pos 16 /*!< CCU8_CC8 INS: EV0EM Position */
\r
4025 #define CCU8_CC8_INS_EV0EM_Msk (0x03UL << CCU8_CC8_INS_EV0EM_Pos) /*!< CCU8_CC8 INS: EV0EM Mask */
\r
4026 #define CCU8_CC8_INS_EV1EM_Pos 18 /*!< CCU8_CC8 INS: EV1EM Position */
\r
4027 #define CCU8_CC8_INS_EV1EM_Msk (0x03UL << CCU8_CC8_INS_EV1EM_Pos) /*!< CCU8_CC8 INS: EV1EM Mask */
\r
4028 #define CCU8_CC8_INS_EV2EM_Pos 20 /*!< CCU8_CC8 INS: EV2EM Position */
\r
4029 #define CCU8_CC8_INS_EV2EM_Msk (0x03UL << CCU8_CC8_INS_EV2EM_Pos) /*!< CCU8_CC8 INS: EV2EM Mask */
\r
4030 #define CCU8_CC8_INS_EV0LM_Pos 22 /*!< CCU8_CC8 INS: EV0LM Position */
\r
4031 #define CCU8_CC8_INS_EV0LM_Msk (0x01UL << CCU8_CC8_INS_EV0LM_Pos) /*!< CCU8_CC8 INS: EV0LM Mask */
\r
4032 #define CCU8_CC8_INS_EV1LM_Pos 23 /*!< CCU8_CC8 INS: EV1LM Position */
\r
4033 #define CCU8_CC8_INS_EV1LM_Msk (0x01UL << CCU8_CC8_INS_EV1LM_Pos) /*!< CCU8_CC8 INS: EV1LM Mask */
\r
4034 #define CCU8_CC8_INS_EV2LM_Pos 24 /*!< CCU8_CC8 INS: EV2LM Position */
\r
4035 #define CCU8_CC8_INS_EV2LM_Msk (0x01UL << CCU8_CC8_INS_EV2LM_Pos) /*!< CCU8_CC8 INS: EV2LM Mask */
\r
4036 #define CCU8_CC8_INS_LPF0M_Pos 25 /*!< CCU8_CC8 INS: LPF0M Position */
\r
4037 #define CCU8_CC8_INS_LPF0M_Msk (0x03UL << CCU8_CC8_INS_LPF0M_Pos) /*!< CCU8_CC8 INS: LPF0M Mask */
\r
4038 #define CCU8_CC8_INS_LPF1M_Pos 27 /*!< CCU8_CC8 INS: LPF1M Position */
\r
4039 #define CCU8_CC8_INS_LPF1M_Msk (0x03UL << CCU8_CC8_INS_LPF1M_Pos) /*!< CCU8_CC8 INS: LPF1M Mask */
\r
4040 #define CCU8_CC8_INS_LPF2M_Pos 29 /*!< CCU8_CC8 INS: LPF2M Position */
\r
4041 #define CCU8_CC8_INS_LPF2M_Msk (0x03UL << CCU8_CC8_INS_LPF2M_Pos) /*!< CCU8_CC8 INS: LPF2M Mask */
\r
4043 /* -------------------------------- CCU8_CC8_CMC -------------------------------- */
\r
4044 #define CCU8_CC8_CMC_STRTS_Pos 0 /*!< CCU8_CC8 CMC: STRTS Position */
\r
4045 #define CCU8_CC8_CMC_STRTS_Msk (0x03UL << CCU8_CC8_CMC_STRTS_Pos) /*!< CCU8_CC8 CMC: STRTS Mask */
\r
4046 #define CCU8_CC8_CMC_ENDS_Pos 2 /*!< CCU8_CC8 CMC: ENDS Position */
\r
4047 #define CCU8_CC8_CMC_ENDS_Msk (0x03UL << CCU8_CC8_CMC_ENDS_Pos) /*!< CCU8_CC8 CMC: ENDS Mask */
\r
4048 #define CCU8_CC8_CMC_CAP0S_Pos 4 /*!< CCU8_CC8 CMC: CAP0S Position */
\r
4049 #define CCU8_CC8_CMC_CAP0S_Msk (0x03UL << CCU8_CC8_CMC_CAP0S_Pos) /*!< CCU8_CC8 CMC: CAP0S Mask */
\r
4050 #define CCU8_CC8_CMC_CAP1S_Pos 6 /*!< CCU8_CC8 CMC: CAP1S Position */
\r
4051 #define CCU8_CC8_CMC_CAP1S_Msk (0x03UL << CCU8_CC8_CMC_CAP1S_Pos) /*!< CCU8_CC8 CMC: CAP1S Mask */
\r
4052 #define CCU8_CC8_CMC_GATES_Pos 8 /*!< CCU8_CC8 CMC: GATES Position */
\r
4053 #define CCU8_CC8_CMC_GATES_Msk (0x03UL << CCU8_CC8_CMC_GATES_Pos) /*!< CCU8_CC8 CMC: GATES Mask */
\r
4054 #define CCU8_CC8_CMC_UDS_Pos 10 /*!< CCU8_CC8 CMC: UDS Position */
\r
4055 #define CCU8_CC8_CMC_UDS_Msk (0x03UL << CCU8_CC8_CMC_UDS_Pos) /*!< CCU8_CC8 CMC: UDS Mask */
\r
4056 #define CCU8_CC8_CMC_LDS_Pos 12 /*!< CCU8_CC8 CMC: LDS Position */
\r
4057 #define CCU8_CC8_CMC_LDS_Msk (0x03UL << CCU8_CC8_CMC_LDS_Pos) /*!< CCU8_CC8 CMC: LDS Mask */
\r
4058 #define CCU8_CC8_CMC_CNTS_Pos 14 /*!< CCU8_CC8 CMC: CNTS Position */
\r
4059 #define CCU8_CC8_CMC_CNTS_Msk (0x03UL << CCU8_CC8_CMC_CNTS_Pos) /*!< CCU8_CC8 CMC: CNTS Mask */
\r
4060 #define CCU8_CC8_CMC_OFS_Pos 16 /*!< CCU8_CC8 CMC: OFS Position */
\r
4061 #define CCU8_CC8_CMC_OFS_Msk (0x01UL << CCU8_CC8_CMC_OFS_Pos) /*!< CCU8_CC8 CMC: OFS Mask */
\r
4062 #define CCU8_CC8_CMC_TS_Pos 17 /*!< CCU8_CC8 CMC: TS Position */
\r
4063 #define CCU8_CC8_CMC_TS_Msk (0x01UL << CCU8_CC8_CMC_TS_Pos) /*!< CCU8_CC8 CMC: TS Mask */
\r
4064 #define CCU8_CC8_CMC_MOS_Pos 18 /*!< CCU8_CC8 CMC: MOS Position */
\r
4065 #define CCU8_CC8_CMC_MOS_Msk (0x03UL << CCU8_CC8_CMC_MOS_Pos) /*!< CCU8_CC8 CMC: MOS Mask */
\r
4066 #define CCU8_CC8_CMC_TCE_Pos 20 /*!< CCU8_CC8 CMC: TCE Position */
\r
4067 #define CCU8_CC8_CMC_TCE_Msk (0x01UL << CCU8_CC8_CMC_TCE_Pos) /*!< CCU8_CC8 CMC: TCE Mask */
\r
4069 /* -------------------------------- CCU8_CC8_TCST ------------------------------- */
\r
4070 #define CCU8_CC8_TCST_TRB_Pos 0 /*!< CCU8_CC8 TCST: TRB Position */
\r
4071 #define CCU8_CC8_TCST_TRB_Msk (0x01UL << CCU8_CC8_TCST_TRB_Pos) /*!< CCU8_CC8 TCST: TRB Mask */
\r
4072 #define CCU8_CC8_TCST_CDIR_Pos 1 /*!< CCU8_CC8 TCST: CDIR Position */
\r
4073 #define CCU8_CC8_TCST_CDIR_Msk (0x01UL << CCU8_CC8_TCST_CDIR_Pos) /*!< CCU8_CC8 TCST: CDIR Mask */
\r
4074 #define CCU8_CC8_TCST_DTR1_Pos 3 /*!< CCU8_CC8 TCST: DTR1 Position */
\r
4075 #define CCU8_CC8_TCST_DTR1_Msk (0x01UL << CCU8_CC8_TCST_DTR1_Pos) /*!< CCU8_CC8 TCST: DTR1 Mask */
\r
4076 #define CCU8_CC8_TCST_DTR2_Pos 4 /*!< CCU8_CC8 TCST: DTR2 Position */
\r
4077 #define CCU8_CC8_TCST_DTR2_Msk (0x01UL << CCU8_CC8_TCST_DTR2_Pos) /*!< CCU8_CC8 TCST: DTR2 Mask */
\r
4079 /* ------------------------------- CCU8_CC8_TCSET ------------------------------- */
\r
4080 #define CCU8_CC8_TCSET_TRBS_Pos 0 /*!< CCU8_CC8 TCSET: TRBS Position */
\r
4081 #define CCU8_CC8_TCSET_TRBS_Msk (0x01UL << CCU8_CC8_TCSET_TRBS_Pos) /*!< CCU8_CC8 TCSET: TRBS Mask */
\r
4083 /* ------------------------------- CCU8_CC8_TCCLR ------------------------------- */
\r
4084 #define CCU8_CC8_TCCLR_TRBC_Pos 0 /*!< CCU8_CC8 TCCLR: TRBC Position */
\r
4085 #define CCU8_CC8_TCCLR_TRBC_Msk (0x01UL << CCU8_CC8_TCCLR_TRBC_Pos) /*!< CCU8_CC8 TCCLR: TRBC Mask */
\r
4086 #define CCU8_CC8_TCCLR_TCC_Pos 1 /*!< CCU8_CC8 TCCLR: TCC Position */
\r
4087 #define CCU8_CC8_TCCLR_TCC_Msk (0x01UL << CCU8_CC8_TCCLR_TCC_Pos) /*!< CCU8_CC8 TCCLR: TCC Mask */
\r
4088 #define CCU8_CC8_TCCLR_DITC_Pos 2 /*!< CCU8_CC8 TCCLR: DITC Position */
\r
4089 #define CCU8_CC8_TCCLR_DITC_Msk (0x01UL << CCU8_CC8_TCCLR_DITC_Pos) /*!< CCU8_CC8 TCCLR: DITC Mask */
\r
4090 #define CCU8_CC8_TCCLR_DTC1C_Pos 3 /*!< CCU8_CC8 TCCLR: DTC1C Position */
\r
4091 #define CCU8_CC8_TCCLR_DTC1C_Msk (0x01UL << CCU8_CC8_TCCLR_DTC1C_Pos) /*!< CCU8_CC8 TCCLR: DTC1C Mask */
\r
4092 #define CCU8_CC8_TCCLR_DTC2C_Pos 4 /*!< CCU8_CC8 TCCLR: DTC2C Position */
\r
4093 #define CCU8_CC8_TCCLR_DTC2C_Msk (0x01UL << CCU8_CC8_TCCLR_DTC2C_Pos) /*!< CCU8_CC8 TCCLR: DTC2C Mask */
\r
4095 /* --------------------------------- CCU8_CC8_TC -------------------------------- */
\r
4096 #define CCU8_CC8_TC_TCM_Pos 0 /*!< CCU8_CC8 TC: TCM Position */
\r
4097 #define CCU8_CC8_TC_TCM_Msk (0x01UL << CCU8_CC8_TC_TCM_Pos) /*!< CCU8_CC8 TC: TCM Mask */
\r
4098 #define CCU8_CC8_TC_TSSM_Pos 1 /*!< CCU8_CC8 TC: TSSM Position */
\r
4099 #define CCU8_CC8_TC_TSSM_Msk (0x01UL << CCU8_CC8_TC_TSSM_Pos) /*!< CCU8_CC8 TC: TSSM Mask */
\r
4100 #define CCU8_CC8_TC_CLST_Pos 2 /*!< CCU8_CC8 TC: CLST Position */
\r
4101 #define CCU8_CC8_TC_CLST_Msk (0x01UL << CCU8_CC8_TC_CLST_Pos) /*!< CCU8_CC8 TC: CLST Mask */
\r
4102 #define CCU8_CC8_TC_CMOD_Pos 3 /*!< CCU8_CC8 TC: CMOD Position */
\r
4103 #define CCU8_CC8_TC_CMOD_Msk (0x01UL << CCU8_CC8_TC_CMOD_Pos) /*!< CCU8_CC8 TC: CMOD Mask */
\r
4104 #define CCU8_CC8_TC_ECM_Pos 4 /*!< CCU8_CC8 TC: ECM Position */
\r
4105 #define CCU8_CC8_TC_ECM_Msk (0x01UL << CCU8_CC8_TC_ECM_Pos) /*!< CCU8_CC8 TC: ECM Mask */
\r
4106 #define CCU8_CC8_TC_CAPC_Pos 5 /*!< CCU8_CC8 TC: CAPC Position */
\r
4107 #define CCU8_CC8_TC_CAPC_Msk (0x03UL << CCU8_CC8_TC_CAPC_Pos) /*!< CCU8_CC8 TC: CAPC Mask */
\r
4108 #define CCU8_CC8_TC_TLS_Pos 7 /*!< CCU8_CC8 TC: TLS Position */
\r
4109 #define CCU8_CC8_TC_TLS_Msk (0x01UL << CCU8_CC8_TC_TLS_Pos) /*!< CCU8_CC8 TC: TLS Mask */
\r
4110 #define CCU8_CC8_TC_ENDM_Pos 8 /*!< CCU8_CC8 TC: ENDM Position */
\r
4111 #define CCU8_CC8_TC_ENDM_Msk (0x03UL << CCU8_CC8_TC_ENDM_Pos) /*!< CCU8_CC8 TC: ENDM Mask */
\r
4112 #define CCU8_CC8_TC_STRM_Pos 10 /*!< CCU8_CC8 TC: STRM Position */
\r
4113 #define CCU8_CC8_TC_STRM_Msk (0x01UL << CCU8_CC8_TC_STRM_Pos) /*!< CCU8_CC8 TC: STRM Mask */
\r
4114 #define CCU8_CC8_TC_SCE_Pos 11 /*!< CCU8_CC8 TC: SCE Position */
\r
4115 #define CCU8_CC8_TC_SCE_Msk (0x01UL << CCU8_CC8_TC_SCE_Pos) /*!< CCU8_CC8 TC: SCE Mask */
\r
4116 #define CCU8_CC8_TC_CCS_Pos 12 /*!< CCU8_CC8 TC: CCS Position */
\r
4117 #define CCU8_CC8_TC_CCS_Msk (0x01UL << CCU8_CC8_TC_CCS_Pos) /*!< CCU8_CC8 TC: CCS Mask */
\r
4118 #define CCU8_CC8_TC_DITHE_Pos 13 /*!< CCU8_CC8 TC: DITHE Position */
\r
4119 #define CCU8_CC8_TC_DITHE_Msk (0x03UL << CCU8_CC8_TC_DITHE_Pos) /*!< CCU8_CC8 TC: DITHE Mask */
\r
4120 #define CCU8_CC8_TC_DIM_Pos 15 /*!< CCU8_CC8 TC: DIM Position */
\r
4121 #define CCU8_CC8_TC_DIM_Msk (0x01UL << CCU8_CC8_TC_DIM_Pos) /*!< CCU8_CC8 TC: DIM Mask */
\r
4122 #define CCU8_CC8_TC_FPE_Pos 16 /*!< CCU8_CC8 TC: FPE Position */
\r
4123 #define CCU8_CC8_TC_FPE_Msk (0x01UL << CCU8_CC8_TC_FPE_Pos) /*!< CCU8_CC8 TC: FPE Mask */
\r
4124 #define CCU8_CC8_TC_TRAPE0_Pos 17 /*!< CCU8_CC8 TC: TRAPE0 Position */
\r
4125 #define CCU8_CC8_TC_TRAPE0_Msk (0x01UL << CCU8_CC8_TC_TRAPE0_Pos) /*!< CCU8_CC8 TC: TRAPE0 Mask */
\r
4126 #define CCU8_CC8_TC_TRAPE1_Pos 18 /*!< CCU8_CC8 TC: TRAPE1 Position */
\r
4127 #define CCU8_CC8_TC_TRAPE1_Msk (0x01UL << CCU8_CC8_TC_TRAPE1_Pos) /*!< CCU8_CC8 TC: TRAPE1 Mask */
\r
4128 #define CCU8_CC8_TC_TRAPE2_Pos 19 /*!< CCU8_CC8 TC: TRAPE2 Position */
\r
4129 #define CCU8_CC8_TC_TRAPE2_Msk (0x01UL << CCU8_CC8_TC_TRAPE2_Pos) /*!< CCU8_CC8 TC: TRAPE2 Mask */
\r
4130 #define CCU8_CC8_TC_TRAPE3_Pos 20 /*!< CCU8_CC8 TC: TRAPE3 Position */
\r
4131 #define CCU8_CC8_TC_TRAPE3_Msk (0x01UL << CCU8_CC8_TC_TRAPE3_Pos) /*!< CCU8_CC8 TC: TRAPE3 Mask */
\r
4132 #define CCU8_CC8_TC_TRPSE_Pos 21 /*!< CCU8_CC8 TC: TRPSE Position */
\r
4133 #define CCU8_CC8_TC_TRPSE_Msk (0x01UL << CCU8_CC8_TC_TRPSE_Pos) /*!< CCU8_CC8 TC: TRPSE Mask */
\r
4134 #define CCU8_CC8_TC_TRPSW_Pos 22 /*!< CCU8_CC8 TC: TRPSW Position */
\r
4135 #define CCU8_CC8_TC_TRPSW_Msk (0x01UL << CCU8_CC8_TC_TRPSW_Pos) /*!< CCU8_CC8 TC: TRPSW Mask */
\r
4136 #define CCU8_CC8_TC_EMS_Pos 23 /*!< CCU8_CC8 TC: EMS Position */
\r
4137 #define CCU8_CC8_TC_EMS_Msk (0x01UL << CCU8_CC8_TC_EMS_Pos) /*!< CCU8_CC8 TC: EMS Mask */
\r
4138 #define CCU8_CC8_TC_EMT_Pos 24 /*!< CCU8_CC8 TC: EMT Position */
\r
4139 #define CCU8_CC8_TC_EMT_Msk (0x01UL << CCU8_CC8_TC_EMT_Pos) /*!< CCU8_CC8 TC: EMT Mask */
\r
4140 #define CCU8_CC8_TC_MCME1_Pos 25 /*!< CCU8_CC8 TC: MCME1 Position */
\r
4141 #define CCU8_CC8_TC_MCME1_Msk (0x01UL << CCU8_CC8_TC_MCME1_Pos) /*!< CCU8_CC8 TC: MCME1 Mask */
\r
4142 #define CCU8_CC8_TC_MCME2_Pos 26 /*!< CCU8_CC8 TC: MCME2 Position */
\r
4143 #define CCU8_CC8_TC_MCME2_Msk (0x01UL << CCU8_CC8_TC_MCME2_Pos) /*!< CCU8_CC8 TC: MCME2 Mask */
\r
4144 #define CCU8_CC8_TC_EME_Pos 27 /*!< CCU8_CC8 TC: EME Position */
\r
4145 #define CCU8_CC8_TC_EME_Msk (0x03UL << CCU8_CC8_TC_EME_Pos) /*!< CCU8_CC8 TC: EME Mask */
\r
4146 #define CCU8_CC8_TC_STOS_Pos 29 /*!< CCU8_CC8 TC: STOS Position */
\r
4147 #define CCU8_CC8_TC_STOS_Msk (0x03UL << CCU8_CC8_TC_STOS_Pos) /*!< CCU8_CC8 TC: STOS Mask */
\r
4149 /* -------------------------------- CCU8_CC8_PSL -------------------------------- */
\r
4150 #define CCU8_CC8_PSL_PSL11_Pos 0 /*!< CCU8_CC8 PSL: PSL11 Position */
\r
4151 #define CCU8_CC8_PSL_PSL11_Msk (0x01UL << CCU8_CC8_PSL_PSL11_Pos) /*!< CCU8_CC8 PSL: PSL11 Mask */
\r
4152 #define CCU8_CC8_PSL_PSL12_Pos 1 /*!< CCU8_CC8 PSL: PSL12 Position */
\r
4153 #define CCU8_CC8_PSL_PSL12_Msk (0x01UL << CCU8_CC8_PSL_PSL12_Pos) /*!< CCU8_CC8 PSL: PSL12 Mask */
\r
4154 #define CCU8_CC8_PSL_PSL21_Pos 2 /*!< CCU8_CC8 PSL: PSL21 Position */
\r
4155 #define CCU8_CC8_PSL_PSL21_Msk (0x01UL << CCU8_CC8_PSL_PSL21_Pos) /*!< CCU8_CC8 PSL: PSL21 Mask */
\r
4156 #define CCU8_CC8_PSL_PSL22_Pos 3 /*!< CCU8_CC8 PSL: PSL22 Position */
\r
4157 #define CCU8_CC8_PSL_PSL22_Msk (0x01UL << CCU8_CC8_PSL_PSL22_Pos) /*!< CCU8_CC8 PSL: PSL22 Mask */
\r
4159 /* -------------------------------- CCU8_CC8_DIT -------------------------------- */
\r
4160 #define CCU8_CC8_DIT_DCV_Pos 0 /*!< CCU8_CC8 DIT: DCV Position */
\r
4161 #define CCU8_CC8_DIT_DCV_Msk (0x0fUL << CCU8_CC8_DIT_DCV_Pos) /*!< CCU8_CC8 DIT: DCV Mask */
\r
4162 #define CCU8_CC8_DIT_DCNT_Pos 8 /*!< CCU8_CC8 DIT: DCNT Position */
\r
4163 #define CCU8_CC8_DIT_DCNT_Msk (0x0fUL << CCU8_CC8_DIT_DCNT_Pos) /*!< CCU8_CC8 DIT: DCNT Mask */
\r
4165 /* -------------------------------- CCU8_CC8_DITS ------------------------------- */
\r
4166 #define CCU8_CC8_DITS_DCVS_Pos 0 /*!< CCU8_CC8 DITS: DCVS Position */
\r
4167 #define CCU8_CC8_DITS_DCVS_Msk (0x0fUL << CCU8_CC8_DITS_DCVS_Pos) /*!< CCU8_CC8 DITS: DCVS Mask */
\r
4169 /* -------------------------------- CCU8_CC8_PSC -------------------------------- */
\r
4170 #define CCU8_CC8_PSC_PSIV_Pos 0 /*!< CCU8_CC8 PSC: PSIV Position */
\r
4171 #define CCU8_CC8_PSC_PSIV_Msk (0x0fUL << CCU8_CC8_PSC_PSIV_Pos) /*!< CCU8_CC8 PSC: PSIV Mask */
\r
4173 /* -------------------------------- CCU8_CC8_FPC -------------------------------- */
\r
4174 #define CCU8_CC8_FPC_PCMP_Pos 0 /*!< CCU8_CC8 FPC: PCMP Position */
\r
4175 #define CCU8_CC8_FPC_PCMP_Msk (0x0fUL << CCU8_CC8_FPC_PCMP_Pos) /*!< CCU8_CC8 FPC: PCMP Mask */
\r
4176 #define CCU8_CC8_FPC_PVAL_Pos 8 /*!< CCU8_CC8 FPC: PVAL Position */
\r
4177 #define CCU8_CC8_FPC_PVAL_Msk (0x0fUL << CCU8_CC8_FPC_PVAL_Pos) /*!< CCU8_CC8 FPC: PVAL Mask */
\r
4179 /* -------------------------------- CCU8_CC8_FPCS ------------------------------- */
\r
4180 #define CCU8_CC8_FPCS_PCMP_Pos 0 /*!< CCU8_CC8 FPCS: PCMP Position */
\r
4181 #define CCU8_CC8_FPCS_PCMP_Msk (0x0fUL << CCU8_CC8_FPCS_PCMP_Pos) /*!< CCU8_CC8 FPCS: PCMP Mask */
\r
4183 /* --------------------------------- CCU8_CC8_PR -------------------------------- */
\r
4184 #define CCU8_CC8_PR_PR_Pos 0 /*!< CCU8_CC8 PR: PR Position */
\r
4185 #define CCU8_CC8_PR_PR_Msk (0x0000ffffUL << CCU8_CC8_PR_PR_Pos) /*!< CCU8_CC8 PR: PR Mask */
\r
4187 /* -------------------------------- CCU8_CC8_PRS -------------------------------- */
\r
4188 #define CCU8_CC8_PRS_PRS_Pos 0 /*!< CCU8_CC8 PRS: PRS Position */
\r
4189 #define CCU8_CC8_PRS_PRS_Msk (0x0000ffffUL << CCU8_CC8_PRS_PRS_Pos) /*!< CCU8_CC8 PRS: PRS Mask */
\r
4191 /* -------------------------------- CCU8_CC8_CR1 -------------------------------- */
\r
4192 #define CCU8_CC8_CR1_CR1_Pos 0 /*!< CCU8_CC8 CR1: CR1 Position */
\r
4193 #define CCU8_CC8_CR1_CR1_Msk (0x0000ffffUL << CCU8_CC8_CR1_CR1_Pos) /*!< CCU8_CC8 CR1: CR1 Mask */
\r
4195 /* -------------------------------- CCU8_CC8_CR1S ------------------------------- */
\r
4196 #define CCU8_CC8_CR1S_CR1S_Pos 0 /*!< CCU8_CC8 CR1S: CR1S Position */
\r
4197 #define CCU8_CC8_CR1S_CR1S_Msk (0x0000ffffUL << CCU8_CC8_CR1S_CR1S_Pos) /*!< CCU8_CC8 CR1S: CR1S Mask */
\r
4199 /* -------------------------------- CCU8_CC8_CR2 -------------------------------- */
\r
4200 #define CCU8_CC8_CR2_CR2_Pos 0 /*!< CCU8_CC8 CR2: CR2 Position */
\r
4201 #define CCU8_CC8_CR2_CR2_Msk (0x0000ffffUL << CCU8_CC8_CR2_CR2_Pos) /*!< CCU8_CC8 CR2: CR2 Mask */
\r
4203 /* -------------------------------- CCU8_CC8_CR2S ------------------------------- */
\r
4204 #define CCU8_CC8_CR2S_CR2S_Pos 0 /*!< CCU8_CC8 CR2S: CR2S Position */
\r
4205 #define CCU8_CC8_CR2S_CR2S_Msk (0x0000ffffUL << CCU8_CC8_CR2S_CR2S_Pos) /*!< CCU8_CC8 CR2S: CR2S Mask */
\r
4207 /* -------------------------------- CCU8_CC8_CHC -------------------------------- */
\r
4208 #define CCU8_CC8_CHC_ASE_Pos 0 /*!< CCU8_CC8 CHC: ASE Position */
\r
4209 #define CCU8_CC8_CHC_ASE_Msk (0x01UL << CCU8_CC8_CHC_ASE_Pos) /*!< CCU8_CC8 CHC: ASE Mask */
\r
4210 #define CCU8_CC8_CHC_OCS1_Pos 1 /*!< CCU8_CC8 CHC: OCS1 Position */
\r
4211 #define CCU8_CC8_CHC_OCS1_Msk (0x01UL << CCU8_CC8_CHC_OCS1_Pos) /*!< CCU8_CC8 CHC: OCS1 Mask */
\r
4212 #define CCU8_CC8_CHC_OCS2_Pos 2 /*!< CCU8_CC8 CHC: OCS2 Position */
\r
4213 #define CCU8_CC8_CHC_OCS2_Msk (0x01UL << CCU8_CC8_CHC_OCS2_Pos) /*!< CCU8_CC8 CHC: OCS2 Mask */
\r
4214 #define CCU8_CC8_CHC_OCS3_Pos 3 /*!< CCU8_CC8 CHC: OCS3 Position */
\r
4215 #define CCU8_CC8_CHC_OCS3_Msk (0x01UL << CCU8_CC8_CHC_OCS3_Pos) /*!< CCU8_CC8 CHC: OCS3 Mask */
\r
4216 #define CCU8_CC8_CHC_OCS4_Pos 4 /*!< CCU8_CC8 CHC: OCS4 Position */
\r
4217 #define CCU8_CC8_CHC_OCS4_Msk (0x01UL << CCU8_CC8_CHC_OCS4_Pos) /*!< CCU8_CC8 CHC: OCS4 Mask */
\r
4219 /* -------------------------------- CCU8_CC8_DTC -------------------------------- */
\r
4220 #define CCU8_CC8_DTC_DTE1_Pos 0 /*!< CCU8_CC8 DTC: DTE1 Position */
\r
4221 #define CCU8_CC8_DTC_DTE1_Msk (0x01UL << CCU8_CC8_DTC_DTE1_Pos) /*!< CCU8_CC8 DTC: DTE1 Mask */
\r
4222 #define CCU8_CC8_DTC_DTE2_Pos 1 /*!< CCU8_CC8 DTC: DTE2 Position */
\r
4223 #define CCU8_CC8_DTC_DTE2_Msk (0x01UL << CCU8_CC8_DTC_DTE2_Pos) /*!< CCU8_CC8 DTC: DTE2 Mask */
\r
4224 #define CCU8_CC8_DTC_DCEN1_Pos 2 /*!< CCU8_CC8 DTC: DCEN1 Position */
\r
4225 #define CCU8_CC8_DTC_DCEN1_Msk (0x01UL << CCU8_CC8_DTC_DCEN1_Pos) /*!< CCU8_CC8 DTC: DCEN1 Mask */
\r
4226 #define CCU8_CC8_DTC_DCEN2_Pos 3 /*!< CCU8_CC8 DTC: DCEN2 Position */
\r
4227 #define CCU8_CC8_DTC_DCEN2_Msk (0x01UL << CCU8_CC8_DTC_DCEN2_Pos) /*!< CCU8_CC8 DTC: DCEN2 Mask */
\r
4228 #define CCU8_CC8_DTC_DCEN3_Pos 4 /*!< CCU8_CC8 DTC: DCEN3 Position */
\r
4229 #define CCU8_CC8_DTC_DCEN3_Msk (0x01UL << CCU8_CC8_DTC_DCEN3_Pos) /*!< CCU8_CC8 DTC: DCEN3 Mask */
\r
4230 #define CCU8_CC8_DTC_DCEN4_Pos 5 /*!< CCU8_CC8 DTC: DCEN4 Position */
\r
4231 #define CCU8_CC8_DTC_DCEN4_Msk (0x01UL << CCU8_CC8_DTC_DCEN4_Pos) /*!< CCU8_CC8 DTC: DCEN4 Mask */
\r
4232 #define CCU8_CC8_DTC_DTCC_Pos 6 /*!< CCU8_CC8 DTC: DTCC Position */
\r
4233 #define CCU8_CC8_DTC_DTCC_Msk (0x03UL << CCU8_CC8_DTC_DTCC_Pos) /*!< CCU8_CC8 DTC: DTCC Mask */
\r
4235 /* -------------------------------- CCU8_CC8_DC1R ------------------------------- */
\r
4236 #define CCU8_CC8_DC1R_DT1R_Pos 0 /*!< CCU8_CC8 DC1R: DT1R Position */
\r
4237 #define CCU8_CC8_DC1R_DT1R_Msk (0x000000ffUL << CCU8_CC8_DC1R_DT1R_Pos) /*!< CCU8_CC8 DC1R: DT1R Mask */
\r
4238 #define CCU8_CC8_DC1R_DT1F_Pos 8 /*!< CCU8_CC8 DC1R: DT1F Position */
\r
4239 #define CCU8_CC8_DC1R_DT1F_Msk (0x000000ffUL << CCU8_CC8_DC1R_DT1F_Pos) /*!< CCU8_CC8 DC1R: DT1F Mask */
\r
4241 /* -------------------------------- CCU8_CC8_DC2R ------------------------------- */
\r
4242 #define CCU8_CC8_DC2R_DT2R_Pos 0 /*!< CCU8_CC8 DC2R: DT2R Position */
\r
4243 #define CCU8_CC8_DC2R_DT2R_Msk (0x000000ffUL << CCU8_CC8_DC2R_DT2R_Pos) /*!< CCU8_CC8 DC2R: DT2R Mask */
\r
4244 #define CCU8_CC8_DC2R_DT2F_Pos 8 /*!< CCU8_CC8 DC2R: DT2F Position */
\r
4245 #define CCU8_CC8_DC2R_DT2F_Msk (0x000000ffUL << CCU8_CC8_DC2R_DT2F_Pos) /*!< CCU8_CC8 DC2R: DT2F Mask */
\r
4247 /* ------------------------------- CCU8_CC8_TIMER ------------------------------- */
\r
4248 #define CCU8_CC8_TIMER_TVAL_Pos 0 /*!< CCU8_CC8 TIMER: TVAL Position */
\r
4249 #define CCU8_CC8_TIMER_TVAL_Msk (0x0000ffffUL << CCU8_CC8_TIMER_TVAL_Pos) /*!< CCU8_CC8 TIMER: TVAL Mask */
\r
4251 /* --------------------------------- CCU8_CC8_CV -------------------------------- */
\r
4252 #define CCU8_CC8_CV_CAPTV_Pos 0 /*!< CCU8_CC8 CV: CAPTV Position */
\r
4253 #define CCU8_CC8_CV_CAPTV_Msk (0x0000ffffUL << CCU8_CC8_CV_CAPTV_Pos) /*!< CCU8_CC8 CV: CAPTV Mask */
\r
4254 #define CCU8_CC8_CV_FPCV_Pos 16 /*!< CCU8_CC8 CV: FPCV Position */
\r
4255 #define CCU8_CC8_CV_FPCV_Msk (0x0fUL << CCU8_CC8_CV_FPCV_Pos) /*!< CCU8_CC8 CV: FPCV Mask */
\r
4256 #define CCU8_CC8_CV_FFL_Pos 20 /*!< CCU8_CC8 CV: FFL Position */
\r
4257 #define CCU8_CC8_CV_FFL_Msk (0x01UL << CCU8_CC8_CV_FFL_Pos) /*!< CCU8_CC8 CV: FFL Mask */
\r
4259 /* -------------------------------- CCU8_CC8_INTS ------------------------------- */
\r
4260 #define CCU8_CC8_INTS_PMUS_Pos 0 /*!< CCU8_CC8 INTS: PMUS Position */
\r
4261 #define CCU8_CC8_INTS_PMUS_Msk (0x01UL << CCU8_CC8_INTS_PMUS_Pos) /*!< CCU8_CC8 INTS: PMUS Mask */
\r
4262 #define CCU8_CC8_INTS_OMDS_Pos 1 /*!< CCU8_CC8 INTS: OMDS Position */
\r
4263 #define CCU8_CC8_INTS_OMDS_Msk (0x01UL << CCU8_CC8_INTS_OMDS_Pos) /*!< CCU8_CC8 INTS: OMDS Mask */
\r
4264 #define CCU8_CC8_INTS_CMU1S_Pos 2 /*!< CCU8_CC8 INTS: CMU1S Position */
\r
4265 #define CCU8_CC8_INTS_CMU1S_Msk (0x01UL << CCU8_CC8_INTS_CMU1S_Pos) /*!< CCU8_CC8 INTS: CMU1S Mask */
\r
4266 #define CCU8_CC8_INTS_CMD1S_Pos 3 /*!< CCU8_CC8 INTS: CMD1S Position */
\r
4267 #define CCU8_CC8_INTS_CMD1S_Msk (0x01UL << CCU8_CC8_INTS_CMD1S_Pos) /*!< CCU8_CC8 INTS: CMD1S Mask */
\r
4268 #define CCU8_CC8_INTS_CMU2S_Pos 4 /*!< CCU8_CC8 INTS: CMU2S Position */
\r
4269 #define CCU8_CC8_INTS_CMU2S_Msk (0x01UL << CCU8_CC8_INTS_CMU2S_Pos) /*!< CCU8_CC8 INTS: CMU2S Mask */
\r
4270 #define CCU8_CC8_INTS_CMD2S_Pos 5 /*!< CCU8_CC8 INTS: CMD2S Position */
\r
4271 #define CCU8_CC8_INTS_CMD2S_Msk (0x01UL << CCU8_CC8_INTS_CMD2S_Pos) /*!< CCU8_CC8 INTS: CMD2S Mask */
\r
4272 #define CCU8_CC8_INTS_E0AS_Pos 8 /*!< CCU8_CC8 INTS: E0AS Position */
\r
4273 #define CCU8_CC8_INTS_E0AS_Msk (0x01UL << CCU8_CC8_INTS_E0AS_Pos) /*!< CCU8_CC8 INTS: E0AS Mask */
\r
4274 #define CCU8_CC8_INTS_E1AS_Pos 9 /*!< CCU8_CC8 INTS: E1AS Position */
\r
4275 #define CCU8_CC8_INTS_E1AS_Msk (0x01UL << CCU8_CC8_INTS_E1AS_Pos) /*!< CCU8_CC8 INTS: E1AS Mask */
\r
4276 #define CCU8_CC8_INTS_E2AS_Pos 10 /*!< CCU8_CC8 INTS: E2AS Position */
\r
4277 #define CCU8_CC8_INTS_E2AS_Msk (0x01UL << CCU8_CC8_INTS_E2AS_Pos) /*!< CCU8_CC8 INTS: E2AS Mask */
\r
4278 #define CCU8_CC8_INTS_TRPF_Pos 11 /*!< CCU8_CC8 INTS: TRPF Position */
\r
4279 #define CCU8_CC8_INTS_TRPF_Msk (0x01UL << CCU8_CC8_INTS_TRPF_Pos) /*!< CCU8_CC8 INTS: TRPF Mask */
\r
4281 /* -------------------------------- CCU8_CC8_INTE ------------------------------- */
\r
4282 #define CCU8_CC8_INTE_PME_Pos 0 /*!< CCU8_CC8 INTE: PME Position */
\r
4283 #define CCU8_CC8_INTE_PME_Msk (0x01UL << CCU8_CC8_INTE_PME_Pos) /*!< CCU8_CC8 INTE: PME Mask */
\r
4284 #define CCU8_CC8_INTE_OME_Pos 1 /*!< CCU8_CC8 INTE: OME Position */
\r
4285 #define CCU8_CC8_INTE_OME_Msk (0x01UL << CCU8_CC8_INTE_OME_Pos) /*!< CCU8_CC8 INTE: OME Mask */
\r
4286 #define CCU8_CC8_INTE_CMU1E_Pos 2 /*!< CCU8_CC8 INTE: CMU1E Position */
\r
4287 #define CCU8_CC8_INTE_CMU1E_Msk (0x01UL << CCU8_CC8_INTE_CMU1E_Pos) /*!< CCU8_CC8 INTE: CMU1E Mask */
\r
4288 #define CCU8_CC8_INTE_CMD1E_Pos 3 /*!< CCU8_CC8 INTE: CMD1E Position */
\r
4289 #define CCU8_CC8_INTE_CMD1E_Msk (0x01UL << CCU8_CC8_INTE_CMD1E_Pos) /*!< CCU8_CC8 INTE: CMD1E Mask */
\r
4290 #define CCU8_CC8_INTE_CMU2E_Pos 4 /*!< CCU8_CC8 INTE: CMU2E Position */
\r
4291 #define CCU8_CC8_INTE_CMU2E_Msk (0x01UL << CCU8_CC8_INTE_CMU2E_Pos) /*!< CCU8_CC8 INTE: CMU2E Mask */
\r
4292 #define CCU8_CC8_INTE_CMD2E_Pos 5 /*!< CCU8_CC8 INTE: CMD2E Position */
\r
4293 #define CCU8_CC8_INTE_CMD2E_Msk (0x01UL << CCU8_CC8_INTE_CMD2E_Pos) /*!< CCU8_CC8 INTE: CMD2E Mask */
\r
4294 #define CCU8_CC8_INTE_E0AE_Pos 8 /*!< CCU8_CC8 INTE: E0AE Position */
\r
4295 #define CCU8_CC8_INTE_E0AE_Msk (0x01UL << CCU8_CC8_INTE_E0AE_Pos) /*!< CCU8_CC8 INTE: E0AE Mask */
\r
4296 #define CCU8_CC8_INTE_E1AE_Pos 9 /*!< CCU8_CC8 INTE: E1AE Position */
\r
4297 #define CCU8_CC8_INTE_E1AE_Msk (0x01UL << CCU8_CC8_INTE_E1AE_Pos) /*!< CCU8_CC8 INTE: E1AE Mask */
\r
4298 #define CCU8_CC8_INTE_E2AE_Pos 10 /*!< CCU8_CC8 INTE: E2AE Position */
\r
4299 #define CCU8_CC8_INTE_E2AE_Msk (0x01UL << CCU8_CC8_INTE_E2AE_Pos) /*!< CCU8_CC8 INTE: E2AE Mask */
\r
4301 /* -------------------------------- CCU8_CC8_SRS -------------------------------- */
\r
4302 #define CCU8_CC8_SRS_POSR_Pos 0 /*!< CCU8_CC8 SRS: POSR Position */
\r
4303 #define CCU8_CC8_SRS_POSR_Msk (0x03UL << CCU8_CC8_SRS_POSR_Pos) /*!< CCU8_CC8 SRS: POSR Mask */
\r
4304 #define CCU8_CC8_SRS_CM1SR_Pos 2 /*!< CCU8_CC8 SRS: CM1SR Position */
\r
4305 #define CCU8_CC8_SRS_CM1SR_Msk (0x03UL << CCU8_CC8_SRS_CM1SR_Pos) /*!< CCU8_CC8 SRS: CM1SR Mask */
\r
4306 #define CCU8_CC8_SRS_CM2SR_Pos 4 /*!< CCU8_CC8 SRS: CM2SR Position */
\r
4307 #define CCU8_CC8_SRS_CM2SR_Msk (0x03UL << CCU8_CC8_SRS_CM2SR_Pos) /*!< CCU8_CC8 SRS: CM2SR Mask */
\r
4308 #define CCU8_CC8_SRS_E0SR_Pos 8 /*!< CCU8_CC8 SRS: E0SR Position */
\r
4309 #define CCU8_CC8_SRS_E0SR_Msk (0x03UL << CCU8_CC8_SRS_E0SR_Pos) /*!< CCU8_CC8 SRS: E0SR Mask */
\r
4310 #define CCU8_CC8_SRS_E1SR_Pos 10 /*!< CCU8_CC8 SRS: E1SR Position */
\r
4311 #define CCU8_CC8_SRS_E1SR_Msk (0x03UL << CCU8_CC8_SRS_E1SR_Pos) /*!< CCU8_CC8 SRS: E1SR Mask */
\r
4312 #define CCU8_CC8_SRS_E2SR_Pos 12 /*!< CCU8_CC8 SRS: E2SR Position */
\r
4313 #define CCU8_CC8_SRS_E2SR_Msk (0x03UL << CCU8_CC8_SRS_E2SR_Pos) /*!< CCU8_CC8 SRS: E2SR Mask */
\r
4315 /* -------------------------------- CCU8_CC8_SWS -------------------------------- */
\r
4316 #define CCU8_CC8_SWS_SPM_Pos 0 /*!< CCU8_CC8 SWS: SPM Position */
\r
4317 #define CCU8_CC8_SWS_SPM_Msk (0x01UL << CCU8_CC8_SWS_SPM_Pos) /*!< CCU8_CC8 SWS: SPM Mask */
\r
4318 #define CCU8_CC8_SWS_SOM_Pos 1 /*!< CCU8_CC8 SWS: SOM Position */
\r
4319 #define CCU8_CC8_SWS_SOM_Msk (0x01UL << CCU8_CC8_SWS_SOM_Pos) /*!< CCU8_CC8 SWS: SOM Mask */
\r
4320 #define CCU8_CC8_SWS_SCM1U_Pos 2 /*!< CCU8_CC8 SWS: SCM1U Position */
\r
4321 #define CCU8_CC8_SWS_SCM1U_Msk (0x01UL << CCU8_CC8_SWS_SCM1U_Pos) /*!< CCU8_CC8 SWS: SCM1U Mask */
\r
4322 #define CCU8_CC8_SWS_SCM1D_Pos 3 /*!< CCU8_CC8 SWS: SCM1D Position */
\r
4323 #define CCU8_CC8_SWS_SCM1D_Msk (0x01UL << CCU8_CC8_SWS_SCM1D_Pos) /*!< CCU8_CC8 SWS: SCM1D Mask */
\r
4324 #define CCU8_CC8_SWS_SCM2U_Pos 4 /*!< CCU8_CC8 SWS: SCM2U Position */
\r
4325 #define CCU8_CC8_SWS_SCM2U_Msk (0x01UL << CCU8_CC8_SWS_SCM2U_Pos) /*!< CCU8_CC8 SWS: SCM2U Mask */
\r
4326 #define CCU8_CC8_SWS_SCM2D_Pos 5 /*!< CCU8_CC8 SWS: SCM2D Position */
\r
4327 #define CCU8_CC8_SWS_SCM2D_Msk (0x01UL << CCU8_CC8_SWS_SCM2D_Pos) /*!< CCU8_CC8 SWS: SCM2D Mask */
\r
4328 #define CCU8_CC8_SWS_SE0A_Pos 8 /*!< CCU8_CC8 SWS: SE0A Position */
\r
4329 #define CCU8_CC8_SWS_SE0A_Msk (0x01UL << CCU8_CC8_SWS_SE0A_Pos) /*!< CCU8_CC8 SWS: SE0A Mask */
\r
4330 #define CCU8_CC8_SWS_SE1A_Pos 9 /*!< CCU8_CC8 SWS: SE1A Position */
\r
4331 #define CCU8_CC8_SWS_SE1A_Msk (0x01UL << CCU8_CC8_SWS_SE1A_Pos) /*!< CCU8_CC8 SWS: SE1A Mask */
\r
4332 #define CCU8_CC8_SWS_SE2A_Pos 10 /*!< CCU8_CC8 SWS: SE2A Position */
\r
4333 #define CCU8_CC8_SWS_SE2A_Msk (0x01UL << CCU8_CC8_SWS_SE2A_Pos) /*!< CCU8_CC8 SWS: SE2A Mask */
\r
4334 #define CCU8_CC8_SWS_STRPF_Pos 11 /*!< CCU8_CC8 SWS: STRPF Position */
\r
4335 #define CCU8_CC8_SWS_STRPF_Msk (0x01UL << CCU8_CC8_SWS_STRPF_Pos) /*!< CCU8_CC8 SWS: STRPF Mask */
\r
4337 /* -------------------------------- CCU8_CC8_SWR -------------------------------- */
\r
4338 #define CCU8_CC8_SWR_RPM_Pos 0 /*!< CCU8_CC8 SWR: RPM Position */
\r
4339 #define CCU8_CC8_SWR_RPM_Msk (0x01UL << CCU8_CC8_SWR_RPM_Pos) /*!< CCU8_CC8 SWR: RPM Mask */
\r
4340 #define CCU8_CC8_SWR_ROM_Pos 1 /*!< CCU8_CC8 SWR: ROM Position */
\r
4341 #define CCU8_CC8_SWR_ROM_Msk (0x01UL << CCU8_CC8_SWR_ROM_Pos) /*!< CCU8_CC8 SWR: ROM Mask */
\r
4342 #define CCU8_CC8_SWR_RCM1U_Pos 2 /*!< CCU8_CC8 SWR: RCM1U Position */
\r
4343 #define CCU8_CC8_SWR_RCM1U_Msk (0x01UL << CCU8_CC8_SWR_RCM1U_Pos) /*!< CCU8_CC8 SWR: RCM1U Mask */
\r
4344 #define CCU8_CC8_SWR_RCM1D_Pos 3 /*!< CCU8_CC8 SWR: RCM1D Position */
\r
4345 #define CCU8_CC8_SWR_RCM1D_Msk (0x01UL << CCU8_CC8_SWR_RCM1D_Pos) /*!< CCU8_CC8 SWR: RCM1D Mask */
\r
4346 #define CCU8_CC8_SWR_RCM2U_Pos 4 /*!< CCU8_CC8 SWR: RCM2U Position */
\r
4347 #define CCU8_CC8_SWR_RCM2U_Msk (0x01UL << CCU8_CC8_SWR_RCM2U_Pos) /*!< CCU8_CC8 SWR: RCM2U Mask */
\r
4348 #define CCU8_CC8_SWR_RCM2D_Pos 5 /*!< CCU8_CC8 SWR: RCM2D Position */
\r
4349 #define CCU8_CC8_SWR_RCM2D_Msk (0x01UL << CCU8_CC8_SWR_RCM2D_Pos) /*!< CCU8_CC8 SWR: RCM2D Mask */
\r
4350 #define CCU8_CC8_SWR_RE0A_Pos 8 /*!< CCU8_CC8 SWR: RE0A Position */
\r
4351 #define CCU8_CC8_SWR_RE0A_Msk (0x01UL << CCU8_CC8_SWR_RE0A_Pos) /*!< CCU8_CC8 SWR: RE0A Mask */
\r
4352 #define CCU8_CC8_SWR_RE1A_Pos 9 /*!< CCU8_CC8 SWR: RE1A Position */
\r
4353 #define CCU8_CC8_SWR_RE1A_Msk (0x01UL << CCU8_CC8_SWR_RE1A_Pos) /*!< CCU8_CC8 SWR: RE1A Mask */
\r
4354 #define CCU8_CC8_SWR_RE2A_Pos 10 /*!< CCU8_CC8 SWR: RE2A Position */
\r
4355 #define CCU8_CC8_SWR_RE2A_Msk (0x01UL << CCU8_CC8_SWR_RE2A_Pos) /*!< CCU8_CC8 SWR: RE2A Mask */
\r
4356 #define CCU8_CC8_SWR_RTRPF_Pos 11 /*!< CCU8_CC8 SWR: RTRPF Position */
\r
4357 #define CCU8_CC8_SWR_RTRPF_Msk (0x01UL << CCU8_CC8_SWR_RTRPF_Pos) /*!< CCU8_CC8 SWR: RTRPF Mask */
\r
4359 /* -------------------------------- CCU8_CC8_STC -------------------------------- */
\r
4360 #define CCU8_CC8_STC_CSE_Pos 0 /*!< CCU8_CC8 STC: CSE Position */
\r
4361 #define CCU8_CC8_STC_CSE_Msk (0x01UL << CCU8_CC8_STC_CSE_Pos) /*!< CCU8_CC8 STC: CSE Mask */
\r
4362 #define CCU8_CC8_STC_STM_Pos 1 /*!< CCU8_CC8 STC: STM Position */
\r
4363 #define CCU8_CC8_STC_STM_Msk (0x03UL << CCU8_CC8_STC_STM_Pos) /*!< CCU8_CC8 STC: STM Mask */
\r
4365 /* ------------------------------- CCU8_CC8_ECRD0 ------------------------------- */
\r
4366 #define CCU8_CC8_ECRD0_CAPV_Pos 0 /*!< CCU8_CC8 ECRD0: CAPV Position */
\r
4367 #define CCU8_CC8_ECRD0_CAPV_Msk (0x0000ffffUL << CCU8_CC8_ECRD0_CAPV_Pos) /*!< CCU8_CC8 ECRD0: CAPV Mask */
\r
4368 #define CCU8_CC8_ECRD0_FPCV_Pos 16 /*!< CCU8_CC8 ECRD0: FPCV Position */
\r
4369 #define CCU8_CC8_ECRD0_FPCV_Msk (0x0fUL << CCU8_CC8_ECRD0_FPCV_Pos) /*!< CCU8_CC8 ECRD0: FPCV Mask */
\r
4370 #define CCU8_CC8_ECRD0_SPTR_Pos 20 /*!< CCU8_CC8 ECRD0: SPTR Position */
\r
4371 #define CCU8_CC8_ECRD0_SPTR_Msk (0x03UL << CCU8_CC8_ECRD0_SPTR_Pos) /*!< CCU8_CC8 ECRD0: SPTR Mask */
\r
4372 #define CCU8_CC8_ECRD0_VPTR_Pos 22 /*!< CCU8_CC8 ECRD0: VPTR Position */
\r
4373 #define CCU8_CC8_ECRD0_VPTR_Msk (0x03UL << CCU8_CC8_ECRD0_VPTR_Pos) /*!< CCU8_CC8 ECRD0: VPTR Mask */
\r
4374 #define CCU8_CC8_ECRD0_FFL_Pos 24 /*!< CCU8_CC8 ECRD0: FFL Position */
\r
4375 #define CCU8_CC8_ECRD0_FFL_Msk (0x01UL << CCU8_CC8_ECRD0_FFL_Pos) /*!< CCU8_CC8 ECRD0: FFL Mask */
\r
4376 #define CCU8_CC8_ECRD0_LCV_Pos 25 /*!< CCU8_CC8 ECRD0: LCV Position */
\r
4377 #define CCU8_CC8_ECRD0_LCV_Msk (0x01UL << CCU8_CC8_ECRD0_LCV_Pos) /*!< CCU8_CC8 ECRD0: LCV Mask */
\r
4379 /* ------------------------------- CCU8_CC8_ECRD1 ------------------------------- */
\r
4380 #define CCU8_CC8_ECRD1_CAPV_Pos 0 /*!< CCU8_CC8 ECRD1: CAPV Position */
\r
4381 #define CCU8_CC8_ECRD1_CAPV_Msk (0x0000ffffUL << CCU8_CC8_ECRD1_CAPV_Pos) /*!< CCU8_CC8 ECRD1: CAPV Mask */
\r
4382 #define CCU8_CC8_ECRD1_FPCV_Pos 16 /*!< CCU8_CC8 ECRD1: FPCV Position */
\r
4383 #define CCU8_CC8_ECRD1_FPCV_Msk (0x0fUL << CCU8_CC8_ECRD1_FPCV_Pos) /*!< CCU8_CC8 ECRD1: FPCV Mask */
\r
4384 #define CCU8_CC8_ECRD1_SPTR_Pos 20 /*!< CCU8_CC8 ECRD1: SPTR Position */
\r
4385 #define CCU8_CC8_ECRD1_SPTR_Msk (0x03UL << CCU8_CC8_ECRD1_SPTR_Pos) /*!< CCU8_CC8 ECRD1: SPTR Mask */
\r
4386 #define CCU8_CC8_ECRD1_VPTR_Pos 22 /*!< CCU8_CC8 ECRD1: VPTR Position */
\r
4387 #define CCU8_CC8_ECRD1_VPTR_Msk (0x03UL << CCU8_CC8_ECRD1_VPTR_Pos) /*!< CCU8_CC8 ECRD1: VPTR Mask */
\r
4388 #define CCU8_CC8_ECRD1_FFL_Pos 24 /*!< CCU8_CC8 ECRD1: FFL Position */
\r
4389 #define CCU8_CC8_ECRD1_FFL_Msk (0x01UL << CCU8_CC8_ECRD1_FFL_Pos) /*!< CCU8_CC8 ECRD1: FFL Mask */
\r
4390 #define CCU8_CC8_ECRD1_LCV_Pos 25 /*!< CCU8_CC8 ECRD1: LCV Position */
\r
4391 #define CCU8_CC8_ECRD1_LCV_Msk (0x01UL << CCU8_CC8_ECRD1_LCV_Pos) /*!< CCU8_CC8 ECRD1: LCV Mask */
\r
4394 /* ================================================================================ */
\r
4395 /* ================ Group 'POSIF' Position & Mask ================ */
\r
4396 /* ================================================================================ */
\r
4399 /* --------------------------------- POSIF_PCONF -------------------------------- */
\r
4400 #define POSIF_PCONF_FSEL_Pos 0 /*!< POSIF PCONF: FSEL Position */
\r
4401 #define POSIF_PCONF_FSEL_Msk (0x03UL << POSIF_PCONF_FSEL_Pos) /*!< POSIF PCONF: FSEL Mask */
\r
4402 #define POSIF_PCONF_QDCM_Pos 2 /*!< POSIF PCONF: QDCM Position */
\r
4403 #define POSIF_PCONF_QDCM_Msk (0x01UL << POSIF_PCONF_QDCM_Pos) /*!< POSIF PCONF: QDCM Mask */
\r
4404 #define POSIF_PCONF_HIDG_Pos 4 /*!< POSIF PCONF: HIDG Position */
\r
4405 #define POSIF_PCONF_HIDG_Msk (0x01UL << POSIF_PCONF_HIDG_Pos) /*!< POSIF PCONF: HIDG Mask */
\r
4406 #define POSIF_PCONF_MCUE_Pos 5 /*!< POSIF PCONF: MCUE Position */
\r
4407 #define POSIF_PCONF_MCUE_Msk (0x01UL << POSIF_PCONF_MCUE_Pos) /*!< POSIF PCONF: MCUE Mask */
\r
4408 #define POSIF_PCONF_INSEL0_Pos 8 /*!< POSIF PCONF: INSEL0 Position */
\r
4409 #define POSIF_PCONF_INSEL0_Msk (0x03UL << POSIF_PCONF_INSEL0_Pos) /*!< POSIF PCONF: INSEL0 Mask */
\r
4410 #define POSIF_PCONF_INSEL1_Pos 10 /*!< POSIF PCONF: INSEL1 Position */
\r
4411 #define POSIF_PCONF_INSEL1_Msk (0x03UL << POSIF_PCONF_INSEL1_Pos) /*!< POSIF PCONF: INSEL1 Mask */
\r
4412 #define POSIF_PCONF_INSEL2_Pos 12 /*!< POSIF PCONF: INSEL2 Position */
\r
4413 #define POSIF_PCONF_INSEL2_Msk (0x03UL << POSIF_PCONF_INSEL2_Pos) /*!< POSIF PCONF: INSEL2 Mask */
\r
4414 #define POSIF_PCONF_DSEL_Pos 16 /*!< POSIF PCONF: DSEL Position */
\r
4415 #define POSIF_PCONF_DSEL_Msk (0x01UL << POSIF_PCONF_DSEL_Pos) /*!< POSIF PCONF: DSEL Mask */
\r
4416 #define POSIF_PCONF_SPES_Pos 17 /*!< POSIF PCONF: SPES Position */
\r
4417 #define POSIF_PCONF_SPES_Msk (0x01UL << POSIF_PCONF_SPES_Pos) /*!< POSIF PCONF: SPES Mask */
\r
4418 #define POSIF_PCONF_MSETS_Pos 18 /*!< POSIF PCONF: MSETS Position */
\r
4419 #define POSIF_PCONF_MSETS_Msk (0x07UL << POSIF_PCONF_MSETS_Pos) /*!< POSIF PCONF: MSETS Mask */
\r
4420 #define POSIF_PCONF_MSES_Pos 21 /*!< POSIF PCONF: MSES Position */
\r
4421 #define POSIF_PCONF_MSES_Msk (0x01UL << POSIF_PCONF_MSES_Pos) /*!< POSIF PCONF: MSES Mask */
\r
4422 #define POSIF_PCONF_MSYNS_Pos 22 /*!< POSIF PCONF: MSYNS Position */
\r
4423 #define POSIF_PCONF_MSYNS_Msk (0x03UL << POSIF_PCONF_MSYNS_Pos) /*!< POSIF PCONF: MSYNS Mask */
\r
4424 #define POSIF_PCONF_EWIS_Pos 24 /*!< POSIF PCONF: EWIS Position */
\r
4425 #define POSIF_PCONF_EWIS_Msk (0x03UL << POSIF_PCONF_EWIS_Pos) /*!< POSIF PCONF: EWIS Mask */
\r
4426 #define POSIF_PCONF_EWIE_Pos 26 /*!< POSIF PCONF: EWIE Position */
\r
4427 #define POSIF_PCONF_EWIE_Msk (0x01UL << POSIF_PCONF_EWIE_Pos) /*!< POSIF PCONF: EWIE Mask */
\r
4428 #define POSIF_PCONF_EWIL_Pos 27 /*!< POSIF PCONF: EWIL Position */
\r
4429 #define POSIF_PCONF_EWIL_Msk (0x01UL << POSIF_PCONF_EWIL_Pos) /*!< POSIF PCONF: EWIL Mask */
\r
4430 #define POSIF_PCONF_LPC_Pos 28 /*!< POSIF PCONF: LPC Position */
\r
4431 #define POSIF_PCONF_LPC_Msk (0x07UL << POSIF_PCONF_LPC_Pos) /*!< POSIF PCONF: LPC Mask */
\r
4433 /* --------------------------------- POSIF_PSUS --------------------------------- */
\r
4434 #define POSIF_PSUS_QSUS_Pos 0 /*!< POSIF PSUS: QSUS Position */
\r
4435 #define POSIF_PSUS_QSUS_Msk (0x03UL << POSIF_PSUS_QSUS_Pos) /*!< POSIF PSUS: QSUS Mask */
\r
4436 #define POSIF_PSUS_MSUS_Pos 2 /*!< POSIF PSUS: MSUS Position */
\r
4437 #define POSIF_PSUS_MSUS_Msk (0x03UL << POSIF_PSUS_MSUS_Pos) /*!< POSIF PSUS: MSUS Mask */
\r
4439 /* --------------------------------- POSIF_PRUNS -------------------------------- */
\r
4440 #define POSIF_PRUNS_SRB_Pos 0 /*!< POSIF PRUNS: SRB Position */
\r
4441 #define POSIF_PRUNS_SRB_Msk (0x01UL << POSIF_PRUNS_SRB_Pos) /*!< POSIF PRUNS: SRB Mask */
\r
4443 /* --------------------------------- POSIF_PRUNC -------------------------------- */
\r
4444 #define POSIF_PRUNC_CRB_Pos 0 /*!< POSIF PRUNC: CRB Position */
\r
4445 #define POSIF_PRUNC_CRB_Msk (0x01UL << POSIF_PRUNC_CRB_Pos) /*!< POSIF PRUNC: CRB Mask */
\r
4446 #define POSIF_PRUNC_CSM_Pos 1 /*!< POSIF PRUNC: CSM Position */
\r
4447 #define POSIF_PRUNC_CSM_Msk (0x01UL << POSIF_PRUNC_CSM_Pos) /*!< POSIF PRUNC: CSM Mask */
\r
4449 /* --------------------------------- POSIF_PRUN --------------------------------- */
\r
4450 #define POSIF_PRUN_RB_Pos 0 /*!< POSIF PRUN: RB Position */
\r
4451 #define POSIF_PRUN_RB_Msk (0x01UL << POSIF_PRUN_RB_Pos) /*!< POSIF PRUN: RB Mask */
\r
4453 /* --------------------------------- POSIF_MIDR --------------------------------- */
\r
4454 #define POSIF_MIDR_MODR_Pos 0 /*!< POSIF MIDR: MODR Position */
\r
4455 #define POSIF_MIDR_MODR_Msk (0x000000ffUL << POSIF_MIDR_MODR_Pos) /*!< POSIF MIDR: MODR Mask */
\r
4456 #define POSIF_MIDR_MODT_Pos 8 /*!< POSIF MIDR: MODT Position */
\r
4457 #define POSIF_MIDR_MODT_Msk (0x000000ffUL << POSIF_MIDR_MODT_Pos) /*!< POSIF MIDR: MODT Mask */
\r
4458 #define POSIF_MIDR_MODN_Pos 16 /*!< POSIF MIDR: MODN Position */
\r
4459 #define POSIF_MIDR_MODN_Msk (0x0000ffffUL << POSIF_MIDR_MODN_Pos) /*!< POSIF MIDR: MODN Mask */
\r
4461 /* --------------------------------- POSIF_HALP --------------------------------- */
\r
4462 #define POSIF_HALP_HCP_Pos 0 /*!< POSIF HALP: HCP Position */
\r
4463 #define POSIF_HALP_HCP_Msk (0x07UL << POSIF_HALP_HCP_Pos) /*!< POSIF HALP: HCP Mask */
\r
4464 #define POSIF_HALP_HEP_Pos 3 /*!< POSIF HALP: HEP Position */
\r
4465 #define POSIF_HALP_HEP_Msk (0x07UL << POSIF_HALP_HEP_Pos) /*!< POSIF HALP: HEP Mask */
\r
4467 /* --------------------------------- POSIF_HALPS -------------------------------- */
\r
4468 #define POSIF_HALPS_HCPS_Pos 0 /*!< POSIF HALPS: HCPS Position */
\r
4469 #define POSIF_HALPS_HCPS_Msk (0x07UL << POSIF_HALPS_HCPS_Pos) /*!< POSIF HALPS: HCPS Mask */
\r
4470 #define POSIF_HALPS_HEPS_Pos 3 /*!< POSIF HALPS: HEPS Position */
\r
4471 #define POSIF_HALPS_HEPS_Msk (0x07UL << POSIF_HALPS_HEPS_Pos) /*!< POSIF HALPS: HEPS Mask */
\r
4473 /* ---------------------------------- POSIF_MCM --------------------------------- */
\r
4474 #define POSIF_MCM_MCMP_Pos 0 /*!< POSIF MCM: MCMP Position */
\r
4475 #define POSIF_MCM_MCMP_Msk (0x0000ffffUL << POSIF_MCM_MCMP_Pos) /*!< POSIF MCM: MCMP Mask */
\r
4477 /* --------------------------------- POSIF_MCSM --------------------------------- */
\r
4478 #define POSIF_MCSM_MCMPS_Pos 0 /*!< POSIF MCSM: MCMPS Position */
\r
4479 #define POSIF_MCSM_MCMPS_Msk (0x0000ffffUL << POSIF_MCSM_MCMPS_Pos) /*!< POSIF MCSM: MCMPS Mask */
\r
4481 /* --------------------------------- POSIF_MCMS --------------------------------- */
\r
4482 #define POSIF_MCMS_MNPS_Pos 0 /*!< POSIF MCMS: MNPS Position */
\r
4483 #define POSIF_MCMS_MNPS_Msk (0x01UL << POSIF_MCMS_MNPS_Pos) /*!< POSIF MCMS: MNPS Mask */
\r
4484 #define POSIF_MCMS_STHR_Pos 1 /*!< POSIF MCMS: STHR Position */
\r
4485 #define POSIF_MCMS_STHR_Msk (0x01UL << POSIF_MCMS_STHR_Pos) /*!< POSIF MCMS: STHR Mask */
\r
4486 #define POSIF_MCMS_STMR_Pos 2 /*!< POSIF MCMS: STMR Position */
\r
4487 #define POSIF_MCMS_STMR_Msk (0x01UL << POSIF_MCMS_STMR_Pos) /*!< POSIF MCMS: STMR Mask */
\r
4489 /* --------------------------------- POSIF_MCMC --------------------------------- */
\r
4490 #define POSIF_MCMC_MNPC_Pos 0 /*!< POSIF MCMC: MNPC Position */
\r
4491 #define POSIF_MCMC_MNPC_Msk (0x01UL << POSIF_MCMC_MNPC_Pos) /*!< POSIF MCMC: MNPC Mask */
\r
4492 #define POSIF_MCMC_MPC_Pos 1 /*!< POSIF MCMC: MPC Position */
\r
4493 #define POSIF_MCMC_MPC_Msk (0x01UL << POSIF_MCMC_MPC_Pos) /*!< POSIF MCMC: MPC Mask */
\r
4495 /* --------------------------------- POSIF_MCMF --------------------------------- */
\r
4496 #define POSIF_MCMF_MSS_Pos 0 /*!< POSIF MCMF: MSS Position */
\r
4497 #define POSIF_MCMF_MSS_Msk (0x01UL << POSIF_MCMF_MSS_Pos) /*!< POSIF MCMF: MSS Mask */
\r
4499 /* ---------------------------------- POSIF_QDC --------------------------------- */
\r
4500 #define POSIF_QDC_PALS_Pos 0 /*!< POSIF QDC: PALS Position */
\r
4501 #define POSIF_QDC_PALS_Msk (0x01UL << POSIF_QDC_PALS_Pos) /*!< POSIF QDC: PALS Mask */
\r
4502 #define POSIF_QDC_PBLS_Pos 1 /*!< POSIF QDC: PBLS Position */
\r
4503 #define POSIF_QDC_PBLS_Msk (0x01UL << POSIF_QDC_PBLS_Pos) /*!< POSIF QDC: PBLS Mask */
\r
4504 #define POSIF_QDC_PHS_Pos 2 /*!< POSIF QDC: PHS Position */
\r
4505 #define POSIF_QDC_PHS_Msk (0x01UL << POSIF_QDC_PHS_Pos) /*!< POSIF QDC: PHS Mask */
\r
4506 #define POSIF_QDC_ICM_Pos 4 /*!< POSIF QDC: ICM Position */
\r
4507 #define POSIF_QDC_ICM_Msk (0x03UL << POSIF_QDC_ICM_Pos) /*!< POSIF QDC: ICM Mask */
\r
4508 #define POSIF_QDC_DVAL_Pos 8 /*!< POSIF QDC: DVAL Position */
\r
4509 #define POSIF_QDC_DVAL_Msk (0x01UL << POSIF_QDC_DVAL_Pos) /*!< POSIF QDC: DVAL Mask */
\r
4511 /* --------------------------------- POSIF_PFLG --------------------------------- */
\r
4512 #define POSIF_PFLG_CHES_Pos 0 /*!< POSIF PFLG: CHES Position */
\r
4513 #define POSIF_PFLG_CHES_Msk (0x01UL << POSIF_PFLG_CHES_Pos) /*!< POSIF PFLG: CHES Mask */
\r
4514 #define POSIF_PFLG_WHES_Pos 1 /*!< POSIF PFLG: WHES Position */
\r
4515 #define POSIF_PFLG_WHES_Msk (0x01UL << POSIF_PFLG_WHES_Pos) /*!< POSIF PFLG: WHES Mask */
\r
4516 #define POSIF_PFLG_HIES_Pos 2 /*!< POSIF PFLG: HIES Position */
\r
4517 #define POSIF_PFLG_HIES_Msk (0x01UL << POSIF_PFLG_HIES_Pos) /*!< POSIF PFLG: HIES Mask */
\r
4518 #define POSIF_PFLG_MSTS_Pos 4 /*!< POSIF PFLG: MSTS Position */
\r
4519 #define POSIF_PFLG_MSTS_Msk (0x01UL << POSIF_PFLG_MSTS_Pos) /*!< POSIF PFLG: MSTS Mask */
\r
4520 #define POSIF_PFLG_INDXS_Pos 8 /*!< POSIF PFLG: INDXS Position */
\r
4521 #define POSIF_PFLG_INDXS_Msk (0x01UL << POSIF_PFLG_INDXS_Pos) /*!< POSIF PFLG: INDXS Mask */
\r
4522 #define POSIF_PFLG_ERRS_Pos 9 /*!< POSIF PFLG: ERRS Position */
\r
4523 #define POSIF_PFLG_ERRS_Msk (0x01UL << POSIF_PFLG_ERRS_Pos) /*!< POSIF PFLG: ERRS Mask */
\r
4524 #define POSIF_PFLG_CNTS_Pos 10 /*!< POSIF PFLG: CNTS Position */
\r
4525 #define POSIF_PFLG_CNTS_Msk (0x01UL << POSIF_PFLG_CNTS_Pos) /*!< POSIF PFLG: CNTS Mask */
\r
4526 #define POSIF_PFLG_DIRS_Pos 11 /*!< POSIF PFLG: DIRS Position */
\r
4527 #define POSIF_PFLG_DIRS_Msk (0x01UL << POSIF_PFLG_DIRS_Pos) /*!< POSIF PFLG: DIRS Mask */
\r
4528 #define POSIF_PFLG_PCLKS_Pos 12 /*!< POSIF PFLG: PCLKS Position */
\r
4529 #define POSIF_PFLG_PCLKS_Msk (0x01UL << POSIF_PFLG_PCLKS_Pos) /*!< POSIF PFLG: PCLKS Mask */
\r
4531 /* --------------------------------- POSIF_PFLGE -------------------------------- */
\r
4532 #define POSIF_PFLGE_ECHE_Pos 0 /*!< POSIF PFLGE: ECHE Position */
\r
4533 #define POSIF_PFLGE_ECHE_Msk (0x01UL << POSIF_PFLGE_ECHE_Pos) /*!< POSIF PFLGE: ECHE Mask */
\r
4534 #define POSIF_PFLGE_EWHE_Pos 1 /*!< POSIF PFLGE: EWHE Position */
\r
4535 #define POSIF_PFLGE_EWHE_Msk (0x01UL << POSIF_PFLGE_EWHE_Pos) /*!< POSIF PFLGE: EWHE Mask */
\r
4536 #define POSIF_PFLGE_EHIE_Pos 2 /*!< POSIF PFLGE: EHIE Position */
\r
4537 #define POSIF_PFLGE_EHIE_Msk (0x01UL << POSIF_PFLGE_EHIE_Pos) /*!< POSIF PFLGE: EHIE Mask */
\r
4538 #define POSIF_PFLGE_EMST_Pos 4 /*!< POSIF PFLGE: EMST Position */
\r
4539 #define POSIF_PFLGE_EMST_Msk (0x01UL << POSIF_PFLGE_EMST_Pos) /*!< POSIF PFLGE: EMST Mask */
\r
4540 #define POSIF_PFLGE_EINDX_Pos 8 /*!< POSIF PFLGE: EINDX Position */
\r
4541 #define POSIF_PFLGE_EINDX_Msk (0x01UL << POSIF_PFLGE_EINDX_Pos) /*!< POSIF PFLGE: EINDX Mask */
\r
4542 #define POSIF_PFLGE_EERR_Pos 9 /*!< POSIF PFLGE: EERR Position */
\r
4543 #define POSIF_PFLGE_EERR_Msk (0x01UL << POSIF_PFLGE_EERR_Pos) /*!< POSIF PFLGE: EERR Mask */
\r
4544 #define POSIF_PFLGE_ECNT_Pos 10 /*!< POSIF PFLGE: ECNT Position */
\r
4545 #define POSIF_PFLGE_ECNT_Msk (0x01UL << POSIF_PFLGE_ECNT_Pos) /*!< POSIF PFLGE: ECNT Mask */
\r
4546 #define POSIF_PFLGE_EDIR_Pos 11 /*!< POSIF PFLGE: EDIR Position */
\r
4547 #define POSIF_PFLGE_EDIR_Msk (0x01UL << POSIF_PFLGE_EDIR_Pos) /*!< POSIF PFLGE: EDIR Mask */
\r
4548 #define POSIF_PFLGE_EPCLK_Pos 12 /*!< POSIF PFLGE: EPCLK Position */
\r
4549 #define POSIF_PFLGE_EPCLK_Msk (0x01UL << POSIF_PFLGE_EPCLK_Pos) /*!< POSIF PFLGE: EPCLK Mask */
\r
4550 #define POSIF_PFLGE_CHESEL_Pos 16 /*!< POSIF PFLGE: CHESEL Position */
\r
4551 #define POSIF_PFLGE_CHESEL_Msk (0x01UL << POSIF_PFLGE_CHESEL_Pos) /*!< POSIF PFLGE: CHESEL Mask */
\r
4552 #define POSIF_PFLGE_WHESEL_Pos 17 /*!< POSIF PFLGE: WHESEL Position */
\r
4553 #define POSIF_PFLGE_WHESEL_Msk (0x01UL << POSIF_PFLGE_WHESEL_Pos) /*!< POSIF PFLGE: WHESEL Mask */
\r
4554 #define POSIF_PFLGE_HIESEL_Pos 18 /*!< POSIF PFLGE: HIESEL Position */
\r
4555 #define POSIF_PFLGE_HIESEL_Msk (0x01UL << POSIF_PFLGE_HIESEL_Pos) /*!< POSIF PFLGE: HIESEL Mask */
\r
4556 #define POSIF_PFLGE_MSTSEL_Pos 20 /*!< POSIF PFLGE: MSTSEL Position */
\r
4557 #define POSIF_PFLGE_MSTSEL_Msk (0x01UL << POSIF_PFLGE_MSTSEL_Pos) /*!< POSIF PFLGE: MSTSEL Mask */
\r
4558 #define POSIF_PFLGE_INDSEL_Pos 24 /*!< POSIF PFLGE: INDSEL Position */
\r
4559 #define POSIF_PFLGE_INDSEL_Msk (0x01UL << POSIF_PFLGE_INDSEL_Pos) /*!< POSIF PFLGE: INDSEL Mask */
\r
4560 #define POSIF_PFLGE_ERRSEL_Pos 25 /*!< POSIF PFLGE: ERRSEL Position */
\r
4561 #define POSIF_PFLGE_ERRSEL_Msk (0x01UL << POSIF_PFLGE_ERRSEL_Pos) /*!< POSIF PFLGE: ERRSEL Mask */
\r
4562 #define POSIF_PFLGE_CNTSEL_Pos 26 /*!< POSIF PFLGE: CNTSEL Position */
\r
4563 #define POSIF_PFLGE_CNTSEL_Msk (0x01UL << POSIF_PFLGE_CNTSEL_Pos) /*!< POSIF PFLGE: CNTSEL Mask */
\r
4564 #define POSIF_PFLGE_DIRSEL_Pos 27 /*!< POSIF PFLGE: DIRSEL Position */
\r
4565 #define POSIF_PFLGE_DIRSEL_Msk (0x01UL << POSIF_PFLGE_DIRSEL_Pos) /*!< POSIF PFLGE: DIRSEL Mask */
\r
4566 #define POSIF_PFLGE_PCLSEL_Pos 28 /*!< POSIF PFLGE: PCLSEL Position */
\r
4567 #define POSIF_PFLGE_PCLSEL_Msk (0x01UL << POSIF_PFLGE_PCLSEL_Pos) /*!< POSIF PFLGE: PCLSEL Mask */
\r
4569 /* --------------------------------- POSIF_SPFLG -------------------------------- */
\r
4570 #define POSIF_SPFLG_SCHE_Pos 0 /*!< POSIF SPFLG: SCHE Position */
\r
4571 #define POSIF_SPFLG_SCHE_Msk (0x01UL << POSIF_SPFLG_SCHE_Pos) /*!< POSIF SPFLG: SCHE Mask */
\r
4572 #define POSIF_SPFLG_SWHE_Pos 1 /*!< POSIF SPFLG: SWHE Position */
\r
4573 #define POSIF_SPFLG_SWHE_Msk (0x01UL << POSIF_SPFLG_SWHE_Pos) /*!< POSIF SPFLG: SWHE Mask */
\r
4574 #define POSIF_SPFLG_SHIE_Pos 2 /*!< POSIF SPFLG: SHIE Position */
\r
4575 #define POSIF_SPFLG_SHIE_Msk (0x01UL << POSIF_SPFLG_SHIE_Pos) /*!< POSIF SPFLG: SHIE Mask */
\r
4576 #define POSIF_SPFLG_SMST_Pos 4 /*!< POSIF SPFLG: SMST Position */
\r
4577 #define POSIF_SPFLG_SMST_Msk (0x01UL << POSIF_SPFLG_SMST_Pos) /*!< POSIF SPFLG: SMST Mask */
\r
4578 #define POSIF_SPFLG_SINDX_Pos 8 /*!< POSIF SPFLG: SINDX Position */
\r
4579 #define POSIF_SPFLG_SINDX_Msk (0x01UL << POSIF_SPFLG_SINDX_Pos) /*!< POSIF SPFLG: SINDX Mask */
\r
4580 #define POSIF_SPFLG_SERR_Pos 9 /*!< POSIF SPFLG: SERR Position */
\r
4581 #define POSIF_SPFLG_SERR_Msk (0x01UL << POSIF_SPFLG_SERR_Pos) /*!< POSIF SPFLG: SERR Mask */
\r
4582 #define POSIF_SPFLG_SCNT_Pos 10 /*!< POSIF SPFLG: SCNT Position */
\r
4583 #define POSIF_SPFLG_SCNT_Msk (0x01UL << POSIF_SPFLG_SCNT_Pos) /*!< POSIF SPFLG: SCNT Mask */
\r
4584 #define POSIF_SPFLG_SDIR_Pos 11 /*!< POSIF SPFLG: SDIR Position */
\r
4585 #define POSIF_SPFLG_SDIR_Msk (0x01UL << POSIF_SPFLG_SDIR_Pos) /*!< POSIF SPFLG: SDIR Mask */
\r
4586 #define POSIF_SPFLG_SPCLK_Pos 12 /*!< POSIF SPFLG: SPCLK Position */
\r
4587 #define POSIF_SPFLG_SPCLK_Msk (0x01UL << POSIF_SPFLG_SPCLK_Pos) /*!< POSIF SPFLG: SPCLK Mask */
\r
4589 /* --------------------------------- POSIF_RPFLG -------------------------------- */
\r
4590 #define POSIF_RPFLG_RCHE_Pos 0 /*!< POSIF RPFLG: RCHE Position */
\r
4591 #define POSIF_RPFLG_RCHE_Msk (0x01UL << POSIF_RPFLG_RCHE_Pos) /*!< POSIF RPFLG: RCHE Mask */
\r
4592 #define POSIF_RPFLG_RWHE_Pos 1 /*!< POSIF RPFLG: RWHE Position */
\r
4593 #define POSIF_RPFLG_RWHE_Msk (0x01UL << POSIF_RPFLG_RWHE_Pos) /*!< POSIF RPFLG: RWHE Mask */
\r
4594 #define POSIF_RPFLG_RHIE_Pos 2 /*!< POSIF RPFLG: RHIE Position */
\r
4595 #define POSIF_RPFLG_RHIE_Msk (0x01UL << POSIF_RPFLG_RHIE_Pos) /*!< POSIF RPFLG: RHIE Mask */
\r
4596 #define POSIF_RPFLG_RMST_Pos 4 /*!< POSIF RPFLG: RMST Position */
\r
4597 #define POSIF_RPFLG_RMST_Msk (0x01UL << POSIF_RPFLG_RMST_Pos) /*!< POSIF RPFLG: RMST Mask */
\r
4598 #define POSIF_RPFLG_RINDX_Pos 8 /*!< POSIF RPFLG: RINDX Position */
\r
4599 #define POSIF_RPFLG_RINDX_Msk (0x01UL << POSIF_RPFLG_RINDX_Pos) /*!< POSIF RPFLG: RINDX Mask */
\r
4600 #define POSIF_RPFLG_RERR_Pos 9 /*!< POSIF RPFLG: RERR Position */
\r
4601 #define POSIF_RPFLG_RERR_Msk (0x01UL << POSIF_RPFLG_RERR_Pos) /*!< POSIF RPFLG: RERR Mask */
\r
4602 #define POSIF_RPFLG_RCNT_Pos 10 /*!< POSIF RPFLG: RCNT Position */
\r
4603 #define POSIF_RPFLG_RCNT_Msk (0x01UL << POSIF_RPFLG_RCNT_Pos) /*!< POSIF RPFLG: RCNT Mask */
\r
4604 #define POSIF_RPFLG_RDIR_Pos 11 /*!< POSIF RPFLG: RDIR Position */
\r
4605 #define POSIF_RPFLG_RDIR_Msk (0x01UL << POSIF_RPFLG_RDIR_Pos) /*!< POSIF RPFLG: RDIR Mask */
\r
4606 #define POSIF_RPFLG_RPCLK_Pos 12 /*!< POSIF RPFLG: RPCLK Position */
\r
4607 #define POSIF_RPFLG_RPCLK_Msk (0x01UL << POSIF_RPFLG_RPCLK_Pos) /*!< POSIF RPFLG: RPCLK Mask */
\r
4609 /* --------------------------------- POSIF_PDBG --------------------------------- */
\r
4610 #define POSIF_PDBG_QCSV_Pos 0 /*!< POSIF PDBG: QCSV Position */
\r
4611 #define POSIF_PDBG_QCSV_Msk (0x03UL << POSIF_PDBG_QCSV_Pos) /*!< POSIF PDBG: QCSV Mask */
\r
4612 #define POSIF_PDBG_QPSV_Pos 2 /*!< POSIF PDBG: QPSV Position */
\r
4613 #define POSIF_PDBG_QPSV_Msk (0x03UL << POSIF_PDBG_QPSV_Pos) /*!< POSIF PDBG: QPSV Mask */
\r
4614 #define POSIF_PDBG_IVAL_Pos 4 /*!< POSIF PDBG: IVAL Position */
\r
4615 #define POSIF_PDBG_IVAL_Msk (0x01UL << POSIF_PDBG_IVAL_Pos) /*!< POSIF PDBG: IVAL Mask */
\r
4616 #define POSIF_PDBG_HSP_Pos 5 /*!< POSIF PDBG: HSP Position */
\r
4617 #define POSIF_PDBG_HSP_Msk (0x07UL << POSIF_PDBG_HSP_Pos) /*!< POSIF PDBG: HSP Mask */
\r
4618 #define POSIF_PDBG_LPP0_Pos 8 /*!< POSIF PDBG: LPP0 Position */
\r
4619 #define POSIF_PDBG_LPP0_Msk (0x3fUL << POSIF_PDBG_LPP0_Pos) /*!< POSIF PDBG: LPP0 Mask */
\r
4620 #define POSIF_PDBG_LPP1_Pos 16 /*!< POSIF PDBG: LPP1 Position */
\r
4621 #define POSIF_PDBG_LPP1_Msk (0x3fUL << POSIF_PDBG_LPP1_Pos) /*!< POSIF PDBG: LPP1 Mask */
\r
4622 #define POSIF_PDBG_LPP2_Pos 22 /*!< POSIF PDBG: LPP2 Position */
\r
4623 #define POSIF_PDBG_LPP2_Msk (0x3fUL << POSIF_PDBG_LPP2_Pos) /*!< POSIF PDBG: LPP2 Mask */
\r
4626 /* ================================================================================ */
\r
4627 /* ================ Group 'VADC' Position & Mask ================ */
\r
4628 /* ================================================================================ */
\r
4631 /* ---------------------------------- VADC_CLC ---------------------------------- */
\r
4632 #define VADC_CLC_DISR_Pos 0 /*!< VADC CLC: DISR Position */
\r
4633 #define VADC_CLC_DISR_Msk (0x01UL << VADC_CLC_DISR_Pos) /*!< VADC CLC: DISR Mask */
\r
4634 #define VADC_CLC_DISS_Pos 1 /*!< VADC CLC: DISS Position */
\r
4635 #define VADC_CLC_DISS_Msk (0x01UL << VADC_CLC_DISS_Pos) /*!< VADC CLC: DISS Mask */
\r
4636 #define VADC_CLC_EDIS_Pos 3 /*!< VADC CLC: EDIS Position */
\r
4637 #define VADC_CLC_EDIS_Msk (0x01UL << VADC_CLC_EDIS_Pos) /*!< VADC CLC: EDIS Mask */
\r
4639 /* ----------------------------------- VADC_ID ---------------------------------- */
\r
4640 #define VADC_ID_MOD_REV_Pos 0 /*!< VADC ID: MOD_REV Position */
\r
4641 #define VADC_ID_MOD_REV_Msk (0x000000ffUL << VADC_ID_MOD_REV_Pos) /*!< VADC ID: MOD_REV Mask */
\r
4642 #define VADC_ID_MOD_TYPE_Pos 8 /*!< VADC ID: MOD_TYPE Position */
\r
4643 #define VADC_ID_MOD_TYPE_Msk (0x000000ffUL << VADC_ID_MOD_TYPE_Pos) /*!< VADC ID: MOD_TYPE Mask */
\r
4644 #define VADC_ID_MOD_NUMBER_Pos 16 /*!< VADC ID: MOD_NUMBER Position */
\r
4645 #define VADC_ID_MOD_NUMBER_Msk (0x0000ffffUL << VADC_ID_MOD_NUMBER_Pos) /*!< VADC ID: MOD_NUMBER Mask */
\r
4647 /* ---------------------------------- VADC_OCS ---------------------------------- */
\r
4648 #define VADC_OCS_TGS_Pos 0 /*!< VADC OCS: TGS Position */
\r
4649 #define VADC_OCS_TGS_Msk (0x03UL << VADC_OCS_TGS_Pos) /*!< VADC OCS: TGS Mask */
\r
4650 #define VADC_OCS_TGB_Pos 2 /*!< VADC OCS: TGB Position */
\r
4651 #define VADC_OCS_TGB_Msk (0x01UL << VADC_OCS_TGB_Pos) /*!< VADC OCS: TGB Mask */
\r
4652 #define VADC_OCS_TG_P_Pos 3 /*!< VADC OCS: TG_P Position */
\r
4653 #define VADC_OCS_TG_P_Msk (0x01UL << VADC_OCS_TG_P_Pos) /*!< VADC OCS: TG_P Mask */
\r
4654 #define VADC_OCS_SUS_Pos 24 /*!< VADC OCS: SUS Position */
\r
4655 #define VADC_OCS_SUS_Msk (0x0fUL << VADC_OCS_SUS_Pos) /*!< VADC OCS: SUS Mask */
\r
4656 #define VADC_OCS_SUS_P_Pos 28 /*!< VADC OCS: SUS_P Position */
\r
4657 #define VADC_OCS_SUS_P_Msk (0x01UL << VADC_OCS_SUS_P_Pos) /*!< VADC OCS: SUS_P Mask */
\r
4658 #define VADC_OCS_SUSSTA_Pos 29 /*!< VADC OCS: SUSSTA Position */
\r
4659 #define VADC_OCS_SUSSTA_Msk (0x01UL << VADC_OCS_SUSSTA_Pos) /*!< VADC OCS: SUSSTA Mask */
\r
4661 /* -------------------------------- VADC_GLOBCFG -------------------------------- */
\r
4662 #define VADC_GLOBCFG_DIVA_Pos 0 /*!< VADC GLOBCFG: DIVA Position */
\r
4663 #define VADC_GLOBCFG_DIVA_Msk (0x1fUL << VADC_GLOBCFG_DIVA_Pos) /*!< VADC GLOBCFG: DIVA Mask */
\r
4664 #define VADC_GLOBCFG_DCMSB_Pos 7 /*!< VADC GLOBCFG: DCMSB Position */
\r
4665 #define VADC_GLOBCFG_DCMSB_Msk (0x01UL << VADC_GLOBCFG_DCMSB_Pos) /*!< VADC GLOBCFG: DCMSB Mask */
\r
4666 #define VADC_GLOBCFG_DIVD_Pos 8 /*!< VADC GLOBCFG: DIVD Position */
\r
4667 #define VADC_GLOBCFG_DIVD_Msk (0x03UL << VADC_GLOBCFG_DIVD_Pos) /*!< VADC GLOBCFG: DIVD Mask */
\r
4668 #define VADC_GLOBCFG_DIVWC_Pos 15 /*!< VADC GLOBCFG: DIVWC Position */
\r
4669 #define VADC_GLOBCFG_DIVWC_Msk (0x01UL << VADC_GLOBCFG_DIVWC_Pos) /*!< VADC GLOBCFG: DIVWC Mask */
\r
4670 #define VADC_GLOBCFG_DPCAL0_Pos 16 /*!< VADC GLOBCFG: DPCAL0 Position */
\r
4671 #define VADC_GLOBCFG_DPCAL0_Msk (0x01UL << VADC_GLOBCFG_DPCAL0_Pos) /*!< VADC GLOBCFG: DPCAL0 Mask */
\r
4672 #define VADC_GLOBCFG_DPCAL1_Pos 17 /*!< VADC GLOBCFG: DPCAL1 Position */
\r
4673 #define VADC_GLOBCFG_DPCAL1_Msk (0x01UL << VADC_GLOBCFG_DPCAL1_Pos) /*!< VADC GLOBCFG: DPCAL1 Mask */
\r
4674 #define VADC_GLOBCFG_SUCAL_Pos 31 /*!< VADC GLOBCFG: SUCAL Position */
\r
4675 #define VADC_GLOBCFG_SUCAL_Msk (0x01UL << VADC_GLOBCFG_SUCAL_Pos) /*!< VADC GLOBCFG: SUCAL Mask */
\r
4677 /* -------------------------------- VADC_ACCPROT0 ------------------------------- */
\r
4678 #define VADC_ACCPROT0_APC0_Pos 0 /*!< VADC ACCPROT0: APC0 Position */
\r
4679 #define VADC_ACCPROT0_APC0_Msk (0x01UL << VADC_ACCPROT0_APC0_Pos) /*!< VADC ACCPROT0: APC0 Mask */
\r
4680 #define VADC_ACCPROT0_APC1_Pos 1 /*!< VADC ACCPROT0: APC1 Position */
\r
4681 #define VADC_ACCPROT0_APC1_Msk (0x01UL << VADC_ACCPROT0_APC1_Pos) /*!< VADC ACCPROT0: APC1 Mask */
\r
4682 #define VADC_ACCPROT0_APEM_Pos 15 /*!< VADC ACCPROT0: APEM Position */
\r
4683 #define VADC_ACCPROT0_APEM_Msk (0x01UL << VADC_ACCPROT0_APEM_Pos) /*!< VADC ACCPROT0: APEM Mask */
\r
4684 #define VADC_ACCPROT0_API0_Pos 16 /*!< VADC ACCPROT0: API0 Position */
\r
4685 #define VADC_ACCPROT0_API0_Msk (0x01UL << VADC_ACCPROT0_API0_Pos) /*!< VADC ACCPROT0: API0 Mask */
\r
4686 #define VADC_ACCPROT0_API1_Pos 17 /*!< VADC ACCPROT0: API1 Position */
\r
4687 #define VADC_ACCPROT0_API1_Msk (0x01UL << VADC_ACCPROT0_API1_Pos) /*!< VADC ACCPROT0: API1 Mask */
\r
4688 #define VADC_ACCPROT0_APGC_Pos 31 /*!< VADC ACCPROT0: APGC Position */
\r
4689 #define VADC_ACCPROT0_APGC_Msk (0x01UL << VADC_ACCPROT0_APGC_Pos) /*!< VADC ACCPROT0: APGC Mask */
\r
4691 /* -------------------------------- VADC_ACCPROT1 ------------------------------- */
\r
4692 #define VADC_ACCPROT1_APS0_Pos 0 /*!< VADC ACCPROT1: APS0 Position */
\r
4693 #define VADC_ACCPROT1_APS0_Msk (0x01UL << VADC_ACCPROT1_APS0_Pos) /*!< VADC ACCPROT1: APS0 Mask */
\r
4694 #define VADC_ACCPROT1_APS1_Pos 1 /*!< VADC ACCPROT1: APS1 Position */
\r
4695 #define VADC_ACCPROT1_APS1_Msk (0x01UL << VADC_ACCPROT1_APS1_Pos) /*!< VADC ACCPROT1: APS1 Mask */
\r
4696 #define VADC_ACCPROT1_APTF_Pos 15 /*!< VADC ACCPROT1: APTF Position */
\r
4697 #define VADC_ACCPROT1_APTF_Msk (0x01UL << VADC_ACCPROT1_APTF_Pos) /*!< VADC ACCPROT1: APTF Mask */
\r
4698 #define VADC_ACCPROT1_APR0_Pos 16 /*!< VADC ACCPROT1: APR0 Position */
\r
4699 #define VADC_ACCPROT1_APR0_Msk (0x01UL << VADC_ACCPROT1_APR0_Pos) /*!< VADC ACCPROT1: APR0 Mask */
\r
4700 #define VADC_ACCPROT1_APR1_Pos 17 /*!< VADC ACCPROT1: APR1 Position */
\r
4701 #define VADC_ACCPROT1_APR1_Msk (0x01UL << VADC_ACCPROT1_APR1_Pos) /*!< VADC ACCPROT1: APR1 Mask */
\r
4703 /* ------------------------------- VADC_GLOBICLASS ------------------------------ */
\r
4704 #define VADC_GLOBICLASS_STCS_Pos 0 /*!< VADC GLOBICLASS: STCS Position */
\r
4705 #define VADC_GLOBICLASS_STCS_Msk (0x1fUL << VADC_GLOBICLASS_STCS_Pos) /*!< VADC GLOBICLASS: STCS Mask */
\r
4706 #define VADC_GLOBICLASS_CMS_Pos 8 /*!< VADC GLOBICLASS: CMS Position */
\r
4707 #define VADC_GLOBICLASS_CMS_Msk (0x07UL << VADC_GLOBICLASS_CMS_Pos) /*!< VADC GLOBICLASS: CMS Mask */
\r
4708 #define VADC_GLOBICLASS_STCE_Pos 16 /*!< VADC GLOBICLASS: STCE Position */
\r
4709 #define VADC_GLOBICLASS_STCE_Msk (0x1fUL << VADC_GLOBICLASS_STCE_Pos) /*!< VADC GLOBICLASS: STCE Mask */
\r
4710 #define VADC_GLOBICLASS_CME_Pos 24 /*!< VADC GLOBICLASS: CME Position */
\r
4711 #define VADC_GLOBICLASS_CME_Msk (0x07UL << VADC_GLOBICLASS_CME_Pos) /*!< VADC GLOBICLASS: CME Mask */
\r
4713 /* ------------------------------- VADC_GLOBBOUND ------------------------------- */
\r
4714 #define VADC_GLOBBOUND_BOUNDARY0_Pos 0 /*!< VADC GLOBBOUND: BOUNDARY0 Position */
\r
4715 #define VADC_GLOBBOUND_BOUNDARY0_Msk (0x00000fffUL << VADC_GLOBBOUND_BOUNDARY0_Pos) /*!< VADC GLOBBOUND: BOUNDARY0 Mask */
\r
4716 #define VADC_GLOBBOUND_BOUNDARY1_Pos 16 /*!< VADC GLOBBOUND: BOUNDARY1 Position */
\r
4717 #define VADC_GLOBBOUND_BOUNDARY1_Msk (0x00000fffUL << VADC_GLOBBOUND_BOUNDARY1_Pos) /*!< VADC GLOBBOUND: BOUNDARY1 Mask */
\r
4719 /* ------------------------------- VADC_GLOBEFLAG ------------------------------- */
\r
4720 #define VADC_GLOBEFLAG_SEVGLB_Pos 0 /*!< VADC GLOBEFLAG: SEVGLB Position */
\r
4721 #define VADC_GLOBEFLAG_SEVGLB_Msk (0x01UL << VADC_GLOBEFLAG_SEVGLB_Pos) /*!< VADC GLOBEFLAG: SEVGLB Mask */
\r
4722 #define VADC_GLOBEFLAG_REVGLB_Pos 8 /*!< VADC GLOBEFLAG: REVGLB Position */
\r
4723 #define VADC_GLOBEFLAG_REVGLB_Msk (0x01UL << VADC_GLOBEFLAG_REVGLB_Pos) /*!< VADC GLOBEFLAG: REVGLB Mask */
\r
4724 #define VADC_GLOBEFLAG_SEVGLBCLR_Pos 16 /*!< VADC GLOBEFLAG: SEVGLBCLR Position */
\r
4725 #define VADC_GLOBEFLAG_SEVGLBCLR_Msk (0x01UL << VADC_GLOBEFLAG_SEVGLBCLR_Pos) /*!< VADC GLOBEFLAG: SEVGLBCLR Mask */
\r
4726 #define VADC_GLOBEFLAG_REVGLBCLR_Pos 24 /*!< VADC GLOBEFLAG: REVGLBCLR Position */
\r
4727 #define VADC_GLOBEFLAG_REVGLBCLR_Msk (0x01UL << VADC_GLOBEFLAG_REVGLBCLR_Pos) /*!< VADC GLOBEFLAG: REVGLBCLR Mask */
\r
4729 /* -------------------------------- VADC_GLOBEVNP ------------------------------- */
\r
4730 #define VADC_GLOBEVNP_SEV0NP_Pos 0 /*!< VADC GLOBEVNP: SEV0NP Position */
\r
4731 #define VADC_GLOBEVNP_SEV0NP_Msk (0x0fUL << VADC_GLOBEVNP_SEV0NP_Pos) /*!< VADC GLOBEVNP: SEV0NP Mask */
\r
4732 #define VADC_GLOBEVNP_REV0NP_Pos 16 /*!< VADC GLOBEVNP: REV0NP Position */
\r
4733 #define VADC_GLOBEVNP_REV0NP_Msk (0x0fUL << VADC_GLOBEVNP_REV0NP_Pos) /*!< VADC GLOBEVNP: REV0NP Mask */
\r
4735 /* --------------------------------- VADC_BRSSEL -------------------------------- */
\r
4736 #define VADC_BRSSEL_CHSELG0_Pos 0 /*!< VADC BRSSEL: CHSELG0 Position */
\r
4737 #define VADC_BRSSEL_CHSELG0_Msk (0x01UL << VADC_BRSSEL_CHSELG0_Pos) /*!< VADC BRSSEL: CHSELG0 Mask */
\r
4738 #define VADC_BRSSEL_CHSELG1_Pos 1 /*!< VADC BRSSEL: CHSELG1 Position */
\r
4739 #define VADC_BRSSEL_CHSELG1_Msk (0x01UL << VADC_BRSSEL_CHSELG1_Pos) /*!< VADC BRSSEL: CHSELG1 Mask */
\r
4740 #define VADC_BRSSEL_CHSELG2_Pos 2 /*!< VADC BRSSEL: CHSELG2 Position */
\r
4741 #define VADC_BRSSEL_CHSELG2_Msk (0x01UL << VADC_BRSSEL_CHSELG2_Pos) /*!< VADC BRSSEL: CHSELG2 Mask */
\r
4742 #define VADC_BRSSEL_CHSELG3_Pos 3 /*!< VADC BRSSEL: CHSELG3 Position */
\r
4743 #define VADC_BRSSEL_CHSELG3_Msk (0x01UL << VADC_BRSSEL_CHSELG3_Pos) /*!< VADC BRSSEL: CHSELG3 Mask */
\r
4744 #define VADC_BRSSEL_CHSELG4_Pos 4 /*!< VADC BRSSEL: CHSELG4 Position */
\r
4745 #define VADC_BRSSEL_CHSELG4_Msk (0x01UL << VADC_BRSSEL_CHSELG4_Pos) /*!< VADC BRSSEL: CHSELG4 Mask */
\r
4746 #define VADC_BRSSEL_CHSELG5_Pos 5 /*!< VADC BRSSEL: CHSELG5 Position */
\r
4747 #define VADC_BRSSEL_CHSELG5_Msk (0x01UL << VADC_BRSSEL_CHSELG5_Pos) /*!< VADC BRSSEL: CHSELG5 Mask */
\r
4748 #define VADC_BRSSEL_CHSELG6_Pos 6 /*!< VADC BRSSEL: CHSELG6 Position */
\r
4749 #define VADC_BRSSEL_CHSELG6_Msk (0x01UL << VADC_BRSSEL_CHSELG6_Pos) /*!< VADC BRSSEL: CHSELG6 Mask */
\r
4750 #define VADC_BRSSEL_CHSELG7_Pos 7 /*!< VADC BRSSEL: CHSELG7 Position */
\r
4751 #define VADC_BRSSEL_CHSELG7_Msk (0x01UL << VADC_BRSSEL_CHSELG7_Pos) /*!< VADC BRSSEL: CHSELG7 Mask */
\r
4753 /* --------------------------------- VADC_BRSPND -------------------------------- */
\r
4754 #define VADC_BRSPND_CHPNDG0_Pos 0 /*!< VADC BRSPND: CHPNDG0 Position */
\r
4755 #define VADC_BRSPND_CHPNDG0_Msk (0x01UL << VADC_BRSPND_CHPNDG0_Pos) /*!< VADC BRSPND: CHPNDG0 Mask */
\r
4756 #define VADC_BRSPND_CHPNDG1_Pos 1 /*!< VADC BRSPND: CHPNDG1 Position */
\r
4757 #define VADC_BRSPND_CHPNDG1_Msk (0x01UL << VADC_BRSPND_CHPNDG1_Pos) /*!< VADC BRSPND: CHPNDG1 Mask */
\r
4758 #define VADC_BRSPND_CHPNDG2_Pos 2 /*!< VADC BRSPND: CHPNDG2 Position */
\r
4759 #define VADC_BRSPND_CHPNDG2_Msk (0x01UL << VADC_BRSPND_CHPNDG2_Pos) /*!< VADC BRSPND: CHPNDG2 Mask */
\r
4760 #define VADC_BRSPND_CHPNDG3_Pos 3 /*!< VADC BRSPND: CHPNDG3 Position */
\r
4761 #define VADC_BRSPND_CHPNDG3_Msk (0x01UL << VADC_BRSPND_CHPNDG3_Pos) /*!< VADC BRSPND: CHPNDG3 Mask */
\r
4762 #define VADC_BRSPND_CHPNDG4_Pos 4 /*!< VADC BRSPND: CHPNDG4 Position */
\r
4763 #define VADC_BRSPND_CHPNDG4_Msk (0x01UL << VADC_BRSPND_CHPNDG4_Pos) /*!< VADC BRSPND: CHPNDG4 Mask */
\r
4764 #define VADC_BRSPND_CHPNDG5_Pos 5 /*!< VADC BRSPND: CHPNDG5 Position */
\r
4765 #define VADC_BRSPND_CHPNDG5_Msk (0x01UL << VADC_BRSPND_CHPNDG5_Pos) /*!< VADC BRSPND: CHPNDG5 Mask */
\r
4766 #define VADC_BRSPND_CHPNDG6_Pos 6 /*!< VADC BRSPND: CHPNDG6 Position */
\r
4767 #define VADC_BRSPND_CHPNDG6_Msk (0x01UL << VADC_BRSPND_CHPNDG6_Pos) /*!< VADC BRSPND: CHPNDG6 Mask */
\r
4768 #define VADC_BRSPND_CHPNDG7_Pos 7 /*!< VADC BRSPND: CHPNDG7 Position */
\r
4769 #define VADC_BRSPND_CHPNDG7_Msk (0x01UL << VADC_BRSPND_CHPNDG7_Pos) /*!< VADC BRSPND: CHPNDG7 Mask */
\r
4771 /* -------------------------------- VADC_BRSCTRL -------------------------------- */
\r
4772 #define VADC_BRSCTRL_SRCRESREG_Pos 0 /*!< VADC BRSCTRL: SRCRESREG Position */
\r
4773 #define VADC_BRSCTRL_SRCRESREG_Msk (0x0fUL << VADC_BRSCTRL_SRCRESREG_Pos) /*!< VADC BRSCTRL: SRCRESREG Mask */
\r
4774 #define VADC_BRSCTRL_XTSEL_Pos 8 /*!< VADC BRSCTRL: XTSEL Position */
\r
4775 #define VADC_BRSCTRL_XTSEL_Msk (0x0fUL << VADC_BRSCTRL_XTSEL_Pos) /*!< VADC BRSCTRL: XTSEL Mask */
\r
4776 #define VADC_BRSCTRL_XTLVL_Pos 12 /*!< VADC BRSCTRL: XTLVL Position */
\r
4777 #define VADC_BRSCTRL_XTLVL_Msk (0x01UL << VADC_BRSCTRL_XTLVL_Pos) /*!< VADC BRSCTRL: XTLVL Mask */
\r
4778 #define VADC_BRSCTRL_XTMODE_Pos 13 /*!< VADC BRSCTRL: XTMODE Position */
\r
4779 #define VADC_BRSCTRL_XTMODE_Msk (0x03UL << VADC_BRSCTRL_XTMODE_Pos) /*!< VADC BRSCTRL: XTMODE Mask */
\r
4780 #define VADC_BRSCTRL_XTWC_Pos 15 /*!< VADC BRSCTRL: XTWC Position */
\r
4781 #define VADC_BRSCTRL_XTWC_Msk (0x01UL << VADC_BRSCTRL_XTWC_Pos) /*!< VADC BRSCTRL: XTWC Mask */
\r
4782 #define VADC_BRSCTRL_GTSEL_Pos 16 /*!< VADC BRSCTRL: GTSEL Position */
\r
4783 #define VADC_BRSCTRL_GTSEL_Msk (0x0fUL << VADC_BRSCTRL_GTSEL_Pos) /*!< VADC BRSCTRL: GTSEL Mask */
\r
4784 #define VADC_BRSCTRL_GTLVL_Pos 20 /*!< VADC BRSCTRL: GTLVL Position */
\r
4785 #define VADC_BRSCTRL_GTLVL_Msk (0x01UL << VADC_BRSCTRL_GTLVL_Pos) /*!< VADC BRSCTRL: GTLVL Mask */
\r
4786 #define VADC_BRSCTRL_GTWC_Pos 23 /*!< VADC BRSCTRL: GTWC Position */
\r
4787 #define VADC_BRSCTRL_GTWC_Msk (0x01UL << VADC_BRSCTRL_GTWC_Pos) /*!< VADC BRSCTRL: GTWC Mask */
\r
4789 /* --------------------------------- VADC_BRSMR --------------------------------- */
\r
4790 #define VADC_BRSMR_ENGT_Pos 0 /*!< VADC BRSMR: ENGT Position */
\r
4791 #define VADC_BRSMR_ENGT_Msk (0x03UL << VADC_BRSMR_ENGT_Pos) /*!< VADC BRSMR: ENGT Mask */
\r
4792 #define VADC_BRSMR_ENTR_Pos 2 /*!< VADC BRSMR: ENTR Position */
\r
4793 #define VADC_BRSMR_ENTR_Msk (0x01UL << VADC_BRSMR_ENTR_Pos) /*!< VADC BRSMR: ENTR Mask */
\r
4794 #define VADC_BRSMR_ENSI_Pos 3 /*!< VADC BRSMR: ENSI Position */
\r
4795 #define VADC_BRSMR_ENSI_Msk (0x01UL << VADC_BRSMR_ENSI_Pos) /*!< VADC BRSMR: ENSI Mask */
\r
4796 #define VADC_BRSMR_SCAN_Pos 4 /*!< VADC BRSMR: SCAN Position */
\r
4797 #define VADC_BRSMR_SCAN_Msk (0x01UL << VADC_BRSMR_SCAN_Pos) /*!< VADC BRSMR: SCAN Mask */
\r
4798 #define VADC_BRSMR_LDM_Pos 5 /*!< VADC BRSMR: LDM Position */
\r
4799 #define VADC_BRSMR_LDM_Msk (0x01UL << VADC_BRSMR_LDM_Pos) /*!< VADC BRSMR: LDM Mask */
\r
4800 #define VADC_BRSMR_REQGT_Pos 7 /*!< VADC BRSMR: REQGT Position */
\r
4801 #define VADC_BRSMR_REQGT_Msk (0x01UL << VADC_BRSMR_REQGT_Pos) /*!< VADC BRSMR: REQGT Mask */
\r
4802 #define VADC_BRSMR_CLRPND_Pos 8 /*!< VADC BRSMR: CLRPND Position */
\r
4803 #define VADC_BRSMR_CLRPND_Msk (0x01UL << VADC_BRSMR_CLRPND_Pos) /*!< VADC BRSMR: CLRPND Mask */
\r
4804 #define VADC_BRSMR_LDEV_Pos 9 /*!< VADC BRSMR: LDEV Position */
\r
4805 #define VADC_BRSMR_LDEV_Msk (0x01UL << VADC_BRSMR_LDEV_Pos) /*!< VADC BRSMR: LDEV Mask */
\r
4806 #define VADC_BRSMR_RPTDIS_Pos 16 /*!< VADC BRSMR: RPTDIS Position */
\r
4807 #define VADC_BRSMR_RPTDIS_Msk (0x01UL << VADC_BRSMR_RPTDIS_Pos) /*!< VADC BRSMR: RPTDIS Mask */
\r
4809 /* -------------------------------- VADC_GLOBRCR -------------------------------- */
\r
4810 #define VADC_GLOBRCR_DRCTR_Pos 16 /*!< VADC GLOBRCR: DRCTR Position */
\r
4811 #define VADC_GLOBRCR_DRCTR_Msk (0x0fUL << VADC_GLOBRCR_DRCTR_Pos) /*!< VADC GLOBRCR: DRCTR Mask */
\r
4812 #define VADC_GLOBRCR_WFR_Pos 24 /*!< VADC GLOBRCR: WFR Position */
\r
4813 #define VADC_GLOBRCR_WFR_Msk (0x01UL << VADC_GLOBRCR_WFR_Pos) /*!< VADC GLOBRCR: WFR Mask */
\r
4814 #define VADC_GLOBRCR_SRGEN_Pos 31 /*!< VADC GLOBRCR: SRGEN Position */
\r
4815 #define VADC_GLOBRCR_SRGEN_Msk (0x01UL << VADC_GLOBRCR_SRGEN_Pos) /*!< VADC GLOBRCR: SRGEN Mask */
\r
4817 /* -------------------------------- VADC_GLOBRES -------------------------------- */
\r
4818 #define VADC_GLOBRES_RESULT_Pos 0 /*!< VADC GLOBRES: RESULT Position */
\r
4819 #define VADC_GLOBRES_RESULT_Msk (0x0000ffffUL << VADC_GLOBRES_RESULT_Pos) /*!< VADC GLOBRES: RESULT Mask */
\r
4820 #define VADC_GLOBRES_GNR_Pos 16 /*!< VADC GLOBRES: GNR Position */
\r
4821 #define VADC_GLOBRES_GNR_Msk (0x0fUL << VADC_GLOBRES_GNR_Pos) /*!< VADC GLOBRES: GNR Mask */
\r
4822 #define VADC_GLOBRES_CHNR_Pos 20 /*!< VADC GLOBRES: CHNR Position */
\r
4823 #define VADC_GLOBRES_CHNR_Msk (0x1fUL << VADC_GLOBRES_CHNR_Pos) /*!< VADC GLOBRES: CHNR Mask */
\r
4824 #define VADC_GLOBRES_EMUX_Pos 25 /*!< VADC GLOBRES: EMUX Position */
\r
4825 #define VADC_GLOBRES_EMUX_Msk (0x07UL << VADC_GLOBRES_EMUX_Pos) /*!< VADC GLOBRES: EMUX Mask */
\r
4826 #define VADC_GLOBRES_CRS_Pos 28 /*!< VADC GLOBRES: CRS Position */
\r
4827 #define VADC_GLOBRES_CRS_Msk (0x03UL << VADC_GLOBRES_CRS_Pos) /*!< VADC GLOBRES: CRS Mask */
\r
4828 #define VADC_GLOBRES_FCR_Pos 30 /*!< VADC GLOBRES: FCR Position */
\r
4829 #define VADC_GLOBRES_FCR_Msk (0x01UL << VADC_GLOBRES_FCR_Pos) /*!< VADC GLOBRES: FCR Mask */
\r
4830 #define VADC_GLOBRES_VF_Pos 31 /*!< VADC GLOBRES: VF Position */
\r
4831 #define VADC_GLOBRES_VF_Msk (0x01UL << VADC_GLOBRES_VF_Pos) /*!< VADC GLOBRES: VF Mask */
\r
4833 /* -------------------------------- VADC_GLOBRESD ------------------------------- */
\r
4834 #define VADC_GLOBRESD_RESULT_Pos 0 /*!< VADC GLOBRESD: RESULT Position */
\r
4835 #define VADC_GLOBRESD_RESULT_Msk (0x0000ffffUL << VADC_GLOBRESD_RESULT_Pos) /*!< VADC GLOBRESD: RESULT Mask */
\r
4836 #define VADC_GLOBRESD_GNR_Pos 16 /*!< VADC GLOBRESD: GNR Position */
\r
4837 #define VADC_GLOBRESD_GNR_Msk (0x0fUL << VADC_GLOBRESD_GNR_Pos) /*!< VADC GLOBRESD: GNR Mask */
\r
4838 #define VADC_GLOBRESD_CHNR_Pos 20 /*!< VADC GLOBRESD: CHNR Position */
\r
4839 #define VADC_GLOBRESD_CHNR_Msk (0x1fUL << VADC_GLOBRESD_CHNR_Pos) /*!< VADC GLOBRESD: CHNR Mask */
\r
4840 #define VADC_GLOBRESD_EMUX_Pos 25 /*!< VADC GLOBRESD: EMUX Position */
\r
4841 #define VADC_GLOBRESD_EMUX_Msk (0x07UL << VADC_GLOBRESD_EMUX_Pos) /*!< VADC GLOBRESD: EMUX Mask */
\r
4842 #define VADC_GLOBRESD_CRS_Pos 28 /*!< VADC GLOBRESD: CRS Position */
\r
4843 #define VADC_GLOBRESD_CRS_Msk (0x03UL << VADC_GLOBRESD_CRS_Pos) /*!< VADC GLOBRESD: CRS Mask */
\r
4844 #define VADC_GLOBRESD_FCR_Pos 30 /*!< VADC GLOBRESD: FCR Position */
\r
4845 #define VADC_GLOBRESD_FCR_Msk (0x01UL << VADC_GLOBRESD_FCR_Pos) /*!< VADC GLOBRESD: FCR Mask */
\r
4846 #define VADC_GLOBRESD_VF_Pos 31 /*!< VADC GLOBRESD: VF Position */
\r
4847 #define VADC_GLOBRESD_VF_Msk (0x01UL << VADC_GLOBRESD_VF_Pos) /*!< VADC GLOBRESD: VF Mask */
\r
4849 /* -------------------------------- VADC_EMUXSEL -------------------------------- */
\r
4850 #define VADC_EMUXSEL_EMUXGRP0_Pos 0 /*!< VADC EMUXSEL: EMUXGRP0 Position */
\r
4851 #define VADC_EMUXSEL_EMUXGRP0_Msk (0x0fUL << VADC_EMUXSEL_EMUXGRP0_Pos) /*!< VADC EMUXSEL: EMUXGRP0 Mask */
\r
4852 #define VADC_EMUXSEL_EMUXGRP1_Pos 4 /*!< VADC EMUXSEL: EMUXGRP1 Position */
\r
4853 #define VADC_EMUXSEL_EMUXGRP1_Msk (0x0fUL << VADC_EMUXSEL_EMUXGRP1_Pos) /*!< VADC EMUXSEL: EMUXGRP1 Mask */
\r
4856 /* ================================================================================ */
\r
4857 /* ================ Group 'VADC_G' Position & Mask ================ */
\r
4858 /* ================================================================================ */
\r
4861 /* -------------------------------- VADC_G_ARBCFG ------------------------------- */
\r
4862 #define VADC_G_ARBCFG_ANONC_Pos 0 /*!< VADC_G ARBCFG: ANONC Position */
\r
4863 #define VADC_G_ARBCFG_ANONC_Msk (0x03UL << VADC_G_ARBCFG_ANONC_Pos) /*!< VADC_G ARBCFG: ANONC Mask */
\r
4864 #define VADC_G_ARBCFG_ARBRND_Pos 4 /*!< VADC_G ARBCFG: ARBRND Position */
\r
4865 #define VADC_G_ARBCFG_ARBRND_Msk (0x03UL << VADC_G_ARBCFG_ARBRND_Pos) /*!< VADC_G ARBCFG: ARBRND Mask */
\r
4866 #define VADC_G_ARBCFG_ARBM_Pos 7 /*!< VADC_G ARBCFG: ARBM Position */
\r
4867 #define VADC_G_ARBCFG_ARBM_Msk (0x01UL << VADC_G_ARBCFG_ARBM_Pos) /*!< VADC_G ARBCFG: ARBM Mask */
\r
4868 #define VADC_G_ARBCFG_ANONS_Pos 16 /*!< VADC_G ARBCFG: ANONS Position */
\r
4869 #define VADC_G_ARBCFG_ANONS_Msk (0x03UL << VADC_G_ARBCFG_ANONS_Pos) /*!< VADC_G ARBCFG: ANONS Mask */
\r
4870 #define VADC_G_ARBCFG_CSRC_Pos 18 /*!< VADC_G ARBCFG: CSRC Position */
\r
4871 #define VADC_G_ARBCFG_CSRC_Msk (0x03UL << VADC_G_ARBCFG_CSRC_Pos) /*!< VADC_G ARBCFG: CSRC Mask */
\r
4872 #define VADC_G_ARBCFG_CHNR_Pos 20 /*!< VADC_G ARBCFG: CHNR Position */
\r
4873 #define VADC_G_ARBCFG_CHNR_Msk (0x1fUL << VADC_G_ARBCFG_CHNR_Pos) /*!< VADC_G ARBCFG: CHNR Mask */
\r
4874 #define VADC_G_ARBCFG_SYNRUN_Pos 25 /*!< VADC_G ARBCFG: SYNRUN Position */
\r
4875 #define VADC_G_ARBCFG_SYNRUN_Msk (0x01UL << VADC_G_ARBCFG_SYNRUN_Pos) /*!< VADC_G ARBCFG: SYNRUN Mask */
\r
4876 #define VADC_G_ARBCFG_CAL_Pos 28 /*!< VADC_G ARBCFG: CAL Position */
\r
4877 #define VADC_G_ARBCFG_CAL_Msk (0x01UL << VADC_G_ARBCFG_CAL_Pos) /*!< VADC_G ARBCFG: CAL Mask */
\r
4878 #define VADC_G_ARBCFG_CALS_Pos 29 /*!< VADC_G ARBCFG: CALS Position */
\r
4879 #define VADC_G_ARBCFG_CALS_Msk (0x01UL << VADC_G_ARBCFG_CALS_Pos) /*!< VADC_G ARBCFG: CALS Mask */
\r
4880 #define VADC_G_ARBCFG_BUSY_Pos 30 /*!< VADC_G ARBCFG: BUSY Position */
\r
4881 #define VADC_G_ARBCFG_BUSY_Msk (0x01UL << VADC_G_ARBCFG_BUSY_Pos) /*!< VADC_G ARBCFG: BUSY Mask */
\r
4882 #define VADC_G_ARBCFG_SAMPLE_Pos 31 /*!< VADC_G ARBCFG: SAMPLE Position */
\r
4883 #define VADC_G_ARBCFG_SAMPLE_Msk (0x01UL << VADC_G_ARBCFG_SAMPLE_Pos) /*!< VADC_G ARBCFG: SAMPLE Mask */
\r
4885 /* -------------------------------- VADC_G_ARBPR -------------------------------- */
\r
4886 #define VADC_G_ARBPR_PRIO0_Pos 0 /*!< VADC_G ARBPR: PRIO0 Position */
\r
4887 #define VADC_G_ARBPR_PRIO0_Msk (0x03UL << VADC_G_ARBPR_PRIO0_Pos) /*!< VADC_G ARBPR: PRIO0 Mask */
\r
4888 #define VADC_G_ARBPR_CSM0_Pos 3 /*!< VADC_G ARBPR: CSM0 Position */
\r
4889 #define VADC_G_ARBPR_CSM0_Msk (0x01UL << VADC_G_ARBPR_CSM0_Pos) /*!< VADC_G ARBPR: CSM0 Mask */
\r
4890 #define VADC_G_ARBPR_PRIO1_Pos 4 /*!< VADC_G ARBPR: PRIO1 Position */
\r
4891 #define VADC_G_ARBPR_PRIO1_Msk (0x03UL << VADC_G_ARBPR_PRIO1_Pos) /*!< VADC_G ARBPR: PRIO1 Mask */
\r
4892 #define VADC_G_ARBPR_CSM1_Pos 7 /*!< VADC_G ARBPR: CSM1 Position */
\r
4893 #define VADC_G_ARBPR_CSM1_Msk (0x01UL << VADC_G_ARBPR_CSM1_Pos) /*!< VADC_G ARBPR: CSM1 Mask */
\r
4894 #define VADC_G_ARBPR_PRIO2_Pos 8 /*!< VADC_G ARBPR: PRIO2 Position */
\r
4895 #define VADC_G_ARBPR_PRIO2_Msk (0x03UL << VADC_G_ARBPR_PRIO2_Pos) /*!< VADC_G ARBPR: PRIO2 Mask */
\r
4896 #define VADC_G_ARBPR_CSM2_Pos 11 /*!< VADC_G ARBPR: CSM2 Position */
\r
4897 #define VADC_G_ARBPR_CSM2_Msk (0x01UL << VADC_G_ARBPR_CSM2_Pos) /*!< VADC_G ARBPR: CSM2 Mask */
\r
4898 #define VADC_G_ARBPR_ASEN0_Pos 24 /*!< VADC_G ARBPR: ASEN0 Position */
\r
4899 #define VADC_G_ARBPR_ASEN0_Msk (0x01UL << VADC_G_ARBPR_ASEN0_Pos) /*!< VADC_G ARBPR: ASEN0 Mask */
\r
4900 #define VADC_G_ARBPR_ASEN1_Pos 25 /*!< VADC_G ARBPR: ASEN1 Position */
\r
4901 #define VADC_G_ARBPR_ASEN1_Msk (0x01UL << VADC_G_ARBPR_ASEN1_Pos) /*!< VADC_G ARBPR: ASEN1 Mask */
\r
4902 #define VADC_G_ARBPR_ASEN2_Pos 26 /*!< VADC_G ARBPR: ASEN2 Position */
\r
4903 #define VADC_G_ARBPR_ASEN2_Msk (0x01UL << VADC_G_ARBPR_ASEN2_Pos) /*!< VADC_G ARBPR: ASEN2 Mask */
\r
4905 /* -------------------------------- VADC_G_CHASS -------------------------------- */
\r
4906 #define VADC_G_CHASS_ASSCH0_Pos 0 /*!< VADC_G CHASS: ASSCH0 Position */
\r
4907 #define VADC_G_CHASS_ASSCH0_Msk (0x01UL << VADC_G_CHASS_ASSCH0_Pos) /*!< VADC_G CHASS: ASSCH0 Mask */
\r
4908 #define VADC_G_CHASS_ASSCH1_Pos 1 /*!< VADC_G CHASS: ASSCH1 Position */
\r
4909 #define VADC_G_CHASS_ASSCH1_Msk (0x01UL << VADC_G_CHASS_ASSCH1_Pos) /*!< VADC_G CHASS: ASSCH1 Mask */
\r
4910 #define VADC_G_CHASS_ASSCH2_Pos 2 /*!< VADC_G CHASS: ASSCH2 Position */
\r
4911 #define VADC_G_CHASS_ASSCH2_Msk (0x01UL << VADC_G_CHASS_ASSCH2_Pos) /*!< VADC_G CHASS: ASSCH2 Mask */
\r
4912 #define VADC_G_CHASS_ASSCH3_Pos 3 /*!< VADC_G CHASS: ASSCH3 Position */
\r
4913 #define VADC_G_CHASS_ASSCH3_Msk (0x01UL << VADC_G_CHASS_ASSCH3_Pos) /*!< VADC_G CHASS: ASSCH3 Mask */
\r
4914 #define VADC_G_CHASS_ASSCH4_Pos 4 /*!< VADC_G CHASS: ASSCH4 Position */
\r
4915 #define VADC_G_CHASS_ASSCH4_Msk (0x01UL << VADC_G_CHASS_ASSCH4_Pos) /*!< VADC_G CHASS: ASSCH4 Mask */
\r
4916 #define VADC_G_CHASS_ASSCH5_Pos 5 /*!< VADC_G CHASS: ASSCH5 Position */
\r
4917 #define VADC_G_CHASS_ASSCH5_Msk (0x01UL << VADC_G_CHASS_ASSCH5_Pos) /*!< VADC_G CHASS: ASSCH5 Mask */
\r
4918 #define VADC_G_CHASS_ASSCH6_Pos 6 /*!< VADC_G CHASS: ASSCH6 Position */
\r
4919 #define VADC_G_CHASS_ASSCH6_Msk (0x01UL << VADC_G_CHASS_ASSCH6_Pos) /*!< VADC_G CHASS: ASSCH6 Mask */
\r
4920 #define VADC_G_CHASS_ASSCH7_Pos 7 /*!< VADC_G CHASS: ASSCH7 Position */
\r
4921 #define VADC_G_CHASS_ASSCH7_Msk (0x01UL << VADC_G_CHASS_ASSCH7_Pos) /*!< VADC_G CHASS: ASSCH7 Mask */
\r
4923 /* -------------------------------- VADC_G_RRASS -------------------------------- */
\r
4924 #define VADC_G_RRASS_ASSRR0_Pos 0 /*!< VADC_G RRASS: ASSRR0 Position */
\r
4925 #define VADC_G_RRASS_ASSRR0_Msk (0x01UL << VADC_G_RRASS_ASSRR0_Pos) /*!< VADC_G RRASS: ASSRR0 Mask */
\r
4926 #define VADC_G_RRASS_ASSRR1_Pos 1 /*!< VADC_G RRASS: ASSRR1 Position */
\r
4927 #define VADC_G_RRASS_ASSRR1_Msk (0x01UL << VADC_G_RRASS_ASSRR1_Pos) /*!< VADC_G RRASS: ASSRR1 Mask */
\r
4928 #define VADC_G_RRASS_ASSRR2_Pos 2 /*!< VADC_G RRASS: ASSRR2 Position */
\r
4929 #define VADC_G_RRASS_ASSRR2_Msk (0x01UL << VADC_G_RRASS_ASSRR2_Pos) /*!< VADC_G RRASS: ASSRR2 Mask */
\r
4930 #define VADC_G_RRASS_ASSRR3_Pos 3 /*!< VADC_G RRASS: ASSRR3 Position */
\r
4931 #define VADC_G_RRASS_ASSRR3_Msk (0x01UL << VADC_G_RRASS_ASSRR3_Pos) /*!< VADC_G RRASS: ASSRR3 Mask */
\r
4932 #define VADC_G_RRASS_ASSRR4_Pos 4 /*!< VADC_G RRASS: ASSRR4 Position */
\r
4933 #define VADC_G_RRASS_ASSRR4_Msk (0x01UL << VADC_G_RRASS_ASSRR4_Pos) /*!< VADC_G RRASS: ASSRR4 Mask */
\r
4934 #define VADC_G_RRASS_ASSRR5_Pos 5 /*!< VADC_G RRASS: ASSRR5 Position */
\r
4935 #define VADC_G_RRASS_ASSRR5_Msk (0x01UL << VADC_G_RRASS_ASSRR5_Pos) /*!< VADC_G RRASS: ASSRR5 Mask */
\r
4936 #define VADC_G_RRASS_ASSRR6_Pos 6 /*!< VADC_G RRASS: ASSRR6 Position */
\r
4937 #define VADC_G_RRASS_ASSRR6_Msk (0x01UL << VADC_G_RRASS_ASSRR6_Pos) /*!< VADC_G RRASS: ASSRR6 Mask */
\r
4938 #define VADC_G_RRASS_ASSRR7_Pos 7 /*!< VADC_G RRASS: ASSRR7 Position */
\r
4939 #define VADC_G_RRASS_ASSRR7_Msk (0x01UL << VADC_G_RRASS_ASSRR7_Pos) /*!< VADC_G RRASS: ASSRR7 Mask */
\r
4940 #define VADC_G_RRASS_ASSRR8_Pos 8 /*!< VADC_G RRASS: ASSRR8 Position */
\r
4941 #define VADC_G_RRASS_ASSRR8_Msk (0x01UL << VADC_G_RRASS_ASSRR8_Pos) /*!< VADC_G RRASS: ASSRR8 Mask */
\r
4942 #define VADC_G_RRASS_ASSRR9_Pos 9 /*!< VADC_G RRASS: ASSRR9 Position */
\r
4943 #define VADC_G_RRASS_ASSRR9_Msk (0x01UL << VADC_G_RRASS_ASSRR9_Pos) /*!< VADC_G RRASS: ASSRR9 Mask */
\r
4944 #define VADC_G_RRASS_ASSRR10_Pos 10 /*!< VADC_G RRASS: ASSRR10 Position */
\r
4945 #define VADC_G_RRASS_ASSRR10_Msk (0x01UL << VADC_G_RRASS_ASSRR10_Pos) /*!< VADC_G RRASS: ASSRR10 Mask */
\r
4946 #define VADC_G_RRASS_ASSRR11_Pos 11 /*!< VADC_G RRASS: ASSRR11 Position */
\r
4947 #define VADC_G_RRASS_ASSRR11_Msk (0x01UL << VADC_G_RRASS_ASSRR11_Pos) /*!< VADC_G RRASS: ASSRR11 Mask */
\r
4948 #define VADC_G_RRASS_ASSRR12_Pos 12 /*!< VADC_G RRASS: ASSRR12 Position */
\r
4949 #define VADC_G_RRASS_ASSRR12_Msk (0x01UL << VADC_G_RRASS_ASSRR12_Pos) /*!< VADC_G RRASS: ASSRR12 Mask */
\r
4950 #define VADC_G_RRASS_ASSRR13_Pos 13 /*!< VADC_G RRASS: ASSRR13 Position */
\r
4951 #define VADC_G_RRASS_ASSRR13_Msk (0x01UL << VADC_G_RRASS_ASSRR13_Pos) /*!< VADC_G RRASS: ASSRR13 Mask */
\r
4952 #define VADC_G_RRASS_ASSRR14_Pos 14 /*!< VADC_G RRASS: ASSRR14 Position */
\r
4953 #define VADC_G_RRASS_ASSRR14_Msk (0x01UL << VADC_G_RRASS_ASSRR14_Pos) /*!< VADC_G RRASS: ASSRR14 Mask */
\r
4954 #define VADC_G_RRASS_ASSRR15_Pos 15 /*!< VADC_G RRASS: ASSRR15 Position */
\r
4955 #define VADC_G_RRASS_ASSRR15_Msk (0x01UL << VADC_G_RRASS_ASSRR15_Pos) /*!< VADC_G RRASS: ASSRR15 Mask */
\r
4957 /* -------------------------------- VADC_G_ICLASS ------------------------------- */
\r
4958 #define VADC_G_ICLASS_STCS_Pos 0 /*!< VADC_G ICLASS: STCS Position */
\r
4959 #define VADC_G_ICLASS_STCS_Msk (0x1fUL << VADC_G_ICLASS_STCS_Pos) /*!< VADC_G ICLASS: STCS Mask */
\r
4960 #define VADC_G_ICLASS_CMS_Pos 8 /*!< VADC_G ICLASS: CMS Position */
\r
4961 #define VADC_G_ICLASS_CMS_Msk (0x07UL << VADC_G_ICLASS_CMS_Pos) /*!< VADC_G ICLASS: CMS Mask */
\r
4962 #define VADC_G_ICLASS_STCE_Pos 16 /*!< VADC_G ICLASS: STCE Position */
\r
4963 #define VADC_G_ICLASS_STCE_Msk (0x1fUL << VADC_G_ICLASS_STCE_Pos) /*!< VADC_G ICLASS: STCE Mask */
\r
4964 #define VADC_G_ICLASS_CME_Pos 24 /*!< VADC_G ICLASS: CME Position */
\r
4965 #define VADC_G_ICLASS_CME_Msk (0x07UL << VADC_G_ICLASS_CME_Pos) /*!< VADC_G ICLASS: CME Mask */
\r
4967 /* -------------------------------- VADC_G_ALIAS -------------------------------- */
\r
4968 #define VADC_G_ALIAS_ALIAS0_Pos 0 /*!< VADC_G ALIAS: ALIAS0 Position */
\r
4969 #define VADC_G_ALIAS_ALIAS0_Msk (0x1fUL << VADC_G_ALIAS_ALIAS0_Pos) /*!< VADC_G ALIAS: ALIAS0 Mask */
\r
4970 #define VADC_G_ALIAS_ALIAS1_Pos 8 /*!< VADC_G ALIAS: ALIAS1 Position */
\r
4971 #define VADC_G_ALIAS_ALIAS1_Msk (0x1fUL << VADC_G_ALIAS_ALIAS1_Pos) /*!< VADC_G ALIAS: ALIAS1 Mask */
\r
4973 /* -------------------------------- VADC_G_BOUND -------------------------------- */
\r
4974 #define VADC_G_BOUND_BOUNDARY0_Pos 0 /*!< VADC_G BOUND: BOUNDARY0 Position */
\r
4975 #define VADC_G_BOUND_BOUNDARY0_Msk (0x00000fffUL << VADC_G_BOUND_BOUNDARY0_Pos) /*!< VADC_G BOUND: BOUNDARY0 Mask */
\r
4976 #define VADC_G_BOUND_BOUNDARY1_Pos 16 /*!< VADC_G BOUND: BOUNDARY1 Position */
\r
4977 #define VADC_G_BOUND_BOUNDARY1_Msk (0x00000fffUL << VADC_G_BOUND_BOUNDARY1_Pos) /*!< VADC_G BOUND: BOUNDARY1 Mask */
\r
4979 /* -------------------------------- VADC_G_SYNCTR ------------------------------- */
\r
4980 #define VADC_G_SYNCTR_STSEL_Pos 0 /*!< VADC_G SYNCTR: STSEL Position */
\r
4981 #define VADC_G_SYNCTR_STSEL_Msk (0x03UL << VADC_G_SYNCTR_STSEL_Pos) /*!< VADC_G SYNCTR: STSEL Mask */
\r
4982 #define VADC_G_SYNCTR_EVALR1_Pos 4 /*!< VADC_G SYNCTR: EVALR1 Position */
\r
4983 #define VADC_G_SYNCTR_EVALR1_Msk (0x01UL << VADC_G_SYNCTR_EVALR1_Pos) /*!< VADC_G SYNCTR: EVALR1 Mask */
\r
4985 /* --------------------------------- VADC_G_BFL --------------------------------- */
\r
4986 #define VADC_G_BFL_BFL0_Pos 0 /*!< VADC_G BFL: BFL0 Position */
\r
4987 #define VADC_G_BFL_BFL0_Msk (0x01UL << VADC_G_BFL_BFL0_Pos) /*!< VADC_G BFL: BFL0 Mask */
\r
4988 #define VADC_G_BFL_BFL1_Pos 1 /*!< VADC_G BFL: BFL1 Position */
\r
4989 #define VADC_G_BFL_BFL1_Msk (0x01UL << VADC_G_BFL_BFL1_Pos) /*!< VADC_G BFL: BFL1 Mask */
\r
4990 #define VADC_G_BFL_BFL2_Pos 2 /*!< VADC_G BFL: BFL2 Position */
\r
4991 #define VADC_G_BFL_BFL2_Msk (0x01UL << VADC_G_BFL_BFL2_Pos) /*!< VADC_G BFL: BFL2 Mask */
\r
4992 #define VADC_G_BFL_BFL3_Pos 3 /*!< VADC_G BFL: BFL3 Position */
\r
4993 #define VADC_G_BFL_BFL3_Msk (0x01UL << VADC_G_BFL_BFL3_Pos) /*!< VADC_G BFL: BFL3 Mask */
\r
4994 #define VADC_G_BFL_BFA0_Pos 8 /*!< VADC_G BFL: BFA0 Position */
\r
4995 #define VADC_G_BFL_BFA0_Msk (0x01UL << VADC_G_BFL_BFA0_Pos) /*!< VADC_G BFL: BFA0 Mask */
\r
4996 #define VADC_G_BFL_BFA1_Pos 9 /*!< VADC_G BFL: BFA1 Position */
\r
4997 #define VADC_G_BFL_BFA1_Msk (0x01UL << VADC_G_BFL_BFA1_Pos) /*!< VADC_G BFL: BFA1 Mask */
\r
4998 #define VADC_G_BFL_BFA2_Pos 10 /*!< VADC_G BFL: BFA2 Position */
\r
4999 #define VADC_G_BFL_BFA2_Msk (0x01UL << VADC_G_BFL_BFA2_Pos) /*!< VADC_G BFL: BFA2 Mask */
\r
5000 #define VADC_G_BFL_BFA3_Pos 11 /*!< VADC_G BFL: BFA3 Position */
\r
5001 #define VADC_G_BFL_BFA3_Msk (0x01UL << VADC_G_BFL_BFA3_Pos) /*!< VADC_G BFL: BFA3 Mask */
\r
5002 #define VADC_G_BFL_BFI0_Pos 16 /*!< VADC_G BFL: BFI0 Position */
\r
5003 #define VADC_G_BFL_BFI0_Msk (0x01UL << VADC_G_BFL_BFI0_Pos) /*!< VADC_G BFL: BFI0 Mask */
\r
5004 #define VADC_G_BFL_BFI1_Pos 17 /*!< VADC_G BFL: BFI1 Position */
\r
5005 #define VADC_G_BFL_BFI1_Msk (0x01UL << VADC_G_BFL_BFI1_Pos) /*!< VADC_G BFL: BFI1 Mask */
\r
5006 #define VADC_G_BFL_BFI2_Pos 18 /*!< VADC_G BFL: BFI2 Position */
\r
5007 #define VADC_G_BFL_BFI2_Msk (0x01UL << VADC_G_BFL_BFI2_Pos) /*!< VADC_G BFL: BFI2 Mask */
\r
5008 #define VADC_G_BFL_BFI3_Pos 19 /*!< VADC_G BFL: BFI3 Position */
\r
5009 #define VADC_G_BFL_BFI3_Msk (0x01UL << VADC_G_BFL_BFI3_Pos) /*!< VADC_G BFL: BFI3 Mask */
\r
5011 /* --------------------------------- VADC_G_BFLS -------------------------------- */
\r
5012 #define VADC_G_BFLS_BFC0_Pos 0 /*!< VADC_G BFLS: BFC0 Position */
\r
5013 #define VADC_G_BFLS_BFC0_Msk (0x01UL << VADC_G_BFLS_BFC0_Pos) /*!< VADC_G BFLS: BFC0 Mask */
\r
5014 #define VADC_G_BFLS_BFC1_Pos 1 /*!< VADC_G BFLS: BFC1 Position */
\r
5015 #define VADC_G_BFLS_BFC1_Msk (0x01UL << VADC_G_BFLS_BFC1_Pos) /*!< VADC_G BFLS: BFC1 Mask */
\r
5016 #define VADC_G_BFLS_BFC2_Pos 2 /*!< VADC_G BFLS: BFC2 Position */
\r
5017 #define VADC_G_BFLS_BFC2_Msk (0x01UL << VADC_G_BFLS_BFC2_Pos) /*!< VADC_G BFLS: BFC2 Mask */
\r
5018 #define VADC_G_BFLS_BFC3_Pos 3 /*!< VADC_G BFLS: BFC3 Position */
\r
5019 #define VADC_G_BFLS_BFC3_Msk (0x01UL << VADC_G_BFLS_BFC3_Pos) /*!< VADC_G BFLS: BFC3 Mask */
\r
5020 #define VADC_G_BFLS_BFS0_Pos 16 /*!< VADC_G BFLS: BFS0 Position */
\r
5021 #define VADC_G_BFLS_BFS0_Msk (0x01UL << VADC_G_BFLS_BFS0_Pos) /*!< VADC_G BFLS: BFS0 Mask */
\r
5022 #define VADC_G_BFLS_BFS1_Pos 17 /*!< VADC_G BFLS: BFS1 Position */
\r
5023 #define VADC_G_BFLS_BFS1_Msk (0x01UL << VADC_G_BFLS_BFS1_Pos) /*!< VADC_G BFLS: BFS1 Mask */
\r
5024 #define VADC_G_BFLS_BFS2_Pos 18 /*!< VADC_G BFLS: BFS2 Position */
\r
5025 #define VADC_G_BFLS_BFS2_Msk (0x01UL << VADC_G_BFLS_BFS2_Pos) /*!< VADC_G BFLS: BFS2 Mask */
\r
5026 #define VADC_G_BFLS_BFS3_Pos 19 /*!< VADC_G BFLS: BFS3 Position */
\r
5027 #define VADC_G_BFLS_BFS3_Msk (0x01UL << VADC_G_BFLS_BFS3_Pos) /*!< VADC_G BFLS: BFS3 Mask */
\r
5029 /* --------------------------------- VADC_G_BFLC -------------------------------- */
\r
5030 #define VADC_G_BFLC_BFM0_Pos 0 /*!< VADC_G BFLC: BFM0 Position */
\r
5031 #define VADC_G_BFLC_BFM0_Msk (0x0fUL << VADC_G_BFLC_BFM0_Pos) /*!< VADC_G BFLC: BFM0 Mask */
\r
5032 #define VADC_G_BFLC_BFM1_Pos 4 /*!< VADC_G BFLC: BFM1 Position */
\r
5033 #define VADC_G_BFLC_BFM1_Msk (0x0fUL << VADC_G_BFLC_BFM1_Pos) /*!< VADC_G BFLC: BFM1 Mask */
\r
5034 #define VADC_G_BFLC_BFM2_Pos 8 /*!< VADC_G BFLC: BFM2 Position */
\r
5035 #define VADC_G_BFLC_BFM2_Msk (0x0fUL << VADC_G_BFLC_BFM2_Pos) /*!< VADC_G BFLC: BFM2 Mask */
\r
5036 #define VADC_G_BFLC_BFM3_Pos 12 /*!< VADC_G BFLC: BFM3 Position */
\r
5037 #define VADC_G_BFLC_BFM3_Msk (0x0fUL << VADC_G_BFLC_BFM3_Pos) /*!< VADC_G BFLC: BFM3 Mask */
\r
5039 /* -------------------------------- VADC_G_BFLNP -------------------------------- */
\r
5040 #define VADC_G_BFLNP_BFL0NP_Pos 0 /*!< VADC_G BFLNP: BFL0NP Position */
\r
5041 #define VADC_G_BFLNP_BFL0NP_Msk (0x0fUL << VADC_G_BFLNP_BFL0NP_Pos) /*!< VADC_G BFLNP: BFL0NP Mask */
\r
5042 #define VADC_G_BFLNP_BFL1NP_Pos 4 /*!< VADC_G BFLNP: BFL1NP Position */
\r
5043 #define VADC_G_BFLNP_BFL1NP_Msk (0x0fUL << VADC_G_BFLNP_BFL1NP_Pos) /*!< VADC_G BFLNP: BFL1NP Mask */
\r
5044 #define VADC_G_BFLNP_BFL2NP_Pos 8 /*!< VADC_G BFLNP: BFL2NP Position */
\r
5045 #define VADC_G_BFLNP_BFL2NP_Msk (0x0fUL << VADC_G_BFLNP_BFL2NP_Pos) /*!< VADC_G BFLNP: BFL2NP Mask */
\r
5046 #define VADC_G_BFLNP_BFL3NP_Pos 12 /*!< VADC_G BFLNP: BFL3NP Position */
\r
5047 #define VADC_G_BFLNP_BFL3NP_Msk (0x0fUL << VADC_G_BFLNP_BFL3NP_Pos) /*!< VADC_G BFLNP: BFL3NP Mask */
\r
5049 /* -------------------------------- VADC_G_QCTRL0 ------------------------------- */
\r
5050 #define VADC_G_QCTRL0_SRCRESREG_Pos 0 /*!< VADC_G QCTRL0: SRCRESREG Position */
\r
5051 #define VADC_G_QCTRL0_SRCRESREG_Msk (0x0fUL << VADC_G_QCTRL0_SRCRESREG_Pos) /*!< VADC_G QCTRL0: SRCRESREG Mask */
\r
5052 #define VADC_G_QCTRL0_XTSEL_Pos 8 /*!< VADC_G QCTRL0: XTSEL Position */
\r
5053 #define VADC_G_QCTRL0_XTSEL_Msk (0x0fUL << VADC_G_QCTRL0_XTSEL_Pos) /*!< VADC_G QCTRL0: XTSEL Mask */
\r
5054 #define VADC_G_QCTRL0_XTLVL_Pos 12 /*!< VADC_G QCTRL0: XTLVL Position */
\r
5055 #define VADC_G_QCTRL0_XTLVL_Msk (0x01UL << VADC_G_QCTRL0_XTLVL_Pos) /*!< VADC_G QCTRL0: XTLVL Mask */
\r
5056 #define VADC_G_QCTRL0_XTMODE_Pos 13 /*!< VADC_G QCTRL0: XTMODE Position */
\r
5057 #define VADC_G_QCTRL0_XTMODE_Msk (0x03UL << VADC_G_QCTRL0_XTMODE_Pos) /*!< VADC_G QCTRL0: XTMODE Mask */
\r
5058 #define VADC_G_QCTRL0_XTWC_Pos 15 /*!< VADC_G QCTRL0: XTWC Position */
\r
5059 #define VADC_G_QCTRL0_XTWC_Msk (0x01UL << VADC_G_QCTRL0_XTWC_Pos) /*!< VADC_G QCTRL0: XTWC Mask */
\r
5060 #define VADC_G_QCTRL0_GTSEL_Pos 16 /*!< VADC_G QCTRL0: GTSEL Position */
\r
5061 #define VADC_G_QCTRL0_GTSEL_Msk (0x0fUL << VADC_G_QCTRL0_GTSEL_Pos) /*!< VADC_G QCTRL0: GTSEL Mask */
\r
5062 #define VADC_G_QCTRL0_GTLVL_Pos 20 /*!< VADC_G QCTRL0: GTLVL Position */
\r
5063 #define VADC_G_QCTRL0_GTLVL_Msk (0x01UL << VADC_G_QCTRL0_GTLVL_Pos) /*!< VADC_G QCTRL0: GTLVL Mask */
\r
5064 #define VADC_G_QCTRL0_GTWC_Pos 23 /*!< VADC_G QCTRL0: GTWC Position */
\r
5065 #define VADC_G_QCTRL0_GTWC_Msk (0x01UL << VADC_G_QCTRL0_GTWC_Pos) /*!< VADC_G QCTRL0: GTWC Mask */
\r
5066 #define VADC_G_QCTRL0_TMEN_Pos 28 /*!< VADC_G QCTRL0: TMEN Position */
\r
5067 #define VADC_G_QCTRL0_TMEN_Msk (0x01UL << VADC_G_QCTRL0_TMEN_Pos) /*!< VADC_G QCTRL0: TMEN Mask */
\r
5068 #define VADC_G_QCTRL0_TMWC_Pos 31 /*!< VADC_G QCTRL0: TMWC Position */
\r
5069 #define VADC_G_QCTRL0_TMWC_Msk (0x01UL << VADC_G_QCTRL0_TMWC_Pos) /*!< VADC_G QCTRL0: TMWC Mask */
\r
5071 /* --------------------------------- VADC_G_QMR0 -------------------------------- */
\r
5072 #define VADC_G_QMR0_ENGT_Pos 0 /*!< VADC_G QMR0: ENGT Position */
\r
5073 #define VADC_G_QMR0_ENGT_Msk (0x03UL << VADC_G_QMR0_ENGT_Pos) /*!< VADC_G QMR0: ENGT Mask */
\r
5074 #define VADC_G_QMR0_ENTR_Pos 2 /*!< VADC_G QMR0: ENTR Position */
\r
5075 #define VADC_G_QMR0_ENTR_Msk (0x01UL << VADC_G_QMR0_ENTR_Pos) /*!< VADC_G QMR0: ENTR Mask */
\r
5076 #define VADC_G_QMR0_CLRV_Pos 8 /*!< VADC_G QMR0: CLRV Position */
\r
5077 #define VADC_G_QMR0_CLRV_Msk (0x01UL << VADC_G_QMR0_CLRV_Pos) /*!< VADC_G QMR0: CLRV Mask */
\r
5078 #define VADC_G_QMR0_TREV_Pos 9 /*!< VADC_G QMR0: TREV Position */
\r
5079 #define VADC_G_QMR0_TREV_Msk (0x01UL << VADC_G_QMR0_TREV_Pos) /*!< VADC_G QMR0: TREV Mask */
\r
5080 #define VADC_G_QMR0_FLUSH_Pos 10 /*!< VADC_G QMR0: FLUSH Position */
\r
5081 #define VADC_G_QMR0_FLUSH_Msk (0x01UL << VADC_G_QMR0_FLUSH_Pos) /*!< VADC_G QMR0: FLUSH Mask */
\r
5082 #define VADC_G_QMR0_CEV_Pos 11 /*!< VADC_G QMR0: CEV Position */
\r
5083 #define VADC_G_QMR0_CEV_Msk (0x01UL << VADC_G_QMR0_CEV_Pos) /*!< VADC_G QMR0: CEV Mask */
\r
5084 #define VADC_G_QMR0_RPTDIS_Pos 16 /*!< VADC_G QMR0: RPTDIS Position */
\r
5085 #define VADC_G_QMR0_RPTDIS_Msk (0x01UL << VADC_G_QMR0_RPTDIS_Pos) /*!< VADC_G QMR0: RPTDIS Mask */
\r
5087 /* --------------------------------- VADC_G_QSR0 -------------------------------- */
\r
5088 #define VADC_G_QSR0_FILL_Pos 0 /*!< VADC_G QSR0: FILL Position */
\r
5089 #define VADC_G_QSR0_FILL_Msk (0x0fUL << VADC_G_QSR0_FILL_Pos) /*!< VADC_G QSR0: FILL Mask */
\r
5090 #define VADC_G_QSR0_EMPTY_Pos 5 /*!< VADC_G QSR0: EMPTY Position */
\r
5091 #define VADC_G_QSR0_EMPTY_Msk (0x01UL << VADC_G_QSR0_EMPTY_Pos) /*!< VADC_G QSR0: EMPTY Mask */
\r
5092 #define VADC_G_QSR0_REQGT_Pos 7 /*!< VADC_G QSR0: REQGT Position */
\r
5093 #define VADC_G_QSR0_REQGT_Msk (0x01UL << VADC_G_QSR0_REQGT_Pos) /*!< VADC_G QSR0: REQGT Mask */
\r
5094 #define VADC_G_QSR0_EV_Pos 8 /*!< VADC_G QSR0: EV Position */
\r
5095 #define VADC_G_QSR0_EV_Msk (0x01UL << VADC_G_QSR0_EV_Pos) /*!< VADC_G QSR0: EV Mask */
\r
5097 /* --------------------------------- VADC_G_Q0R0 -------------------------------- */
\r
5098 #define VADC_G_Q0R0_REQCHNR_Pos 0 /*!< VADC_G Q0R0: REQCHNR Position */
\r
5099 #define VADC_G_Q0R0_REQCHNR_Msk (0x1fUL << VADC_G_Q0R0_REQCHNR_Pos) /*!< VADC_G Q0R0: REQCHNR Mask */
\r
5100 #define VADC_G_Q0R0_RF_Pos 5 /*!< VADC_G Q0R0: RF Position */
\r
5101 #define VADC_G_Q0R0_RF_Msk (0x01UL << VADC_G_Q0R0_RF_Pos) /*!< VADC_G Q0R0: RF Mask */
\r
5102 #define VADC_G_Q0R0_ENSI_Pos 6 /*!< VADC_G Q0R0: ENSI Position */
\r
5103 #define VADC_G_Q0R0_ENSI_Msk (0x01UL << VADC_G_Q0R0_ENSI_Pos) /*!< VADC_G Q0R0: ENSI Mask */
\r
5104 #define VADC_G_Q0R0_EXTR_Pos 7 /*!< VADC_G Q0R0: EXTR Position */
\r
5105 #define VADC_G_Q0R0_EXTR_Msk (0x01UL << VADC_G_Q0R0_EXTR_Pos) /*!< VADC_G Q0R0: EXTR Mask */
\r
5106 #define VADC_G_Q0R0_V_Pos 8 /*!< VADC_G Q0R0: V Position */
\r
5107 #define VADC_G_Q0R0_V_Msk (0x01UL << VADC_G_Q0R0_V_Pos) /*!< VADC_G Q0R0: V Mask */
\r
5109 /* -------------------------------- VADC_G_QINR0 -------------------------------- */
\r
5110 #define VADC_G_QINR0_REQCHNR_Pos 0 /*!< VADC_G QINR0: REQCHNR Position */
\r
5111 #define VADC_G_QINR0_REQCHNR_Msk (0x1fUL << VADC_G_QINR0_REQCHNR_Pos) /*!< VADC_G QINR0: REQCHNR Mask */
\r
5112 #define VADC_G_QINR0_RF_Pos 5 /*!< VADC_G QINR0: RF Position */
\r
5113 #define VADC_G_QINR0_RF_Msk (0x01UL << VADC_G_QINR0_RF_Pos) /*!< VADC_G QINR0: RF Mask */
\r
5114 #define VADC_G_QINR0_ENSI_Pos 6 /*!< VADC_G QINR0: ENSI Position */
\r
5115 #define VADC_G_QINR0_ENSI_Msk (0x01UL << VADC_G_QINR0_ENSI_Pos) /*!< VADC_G QINR0: ENSI Mask */
\r
5116 #define VADC_G_QINR0_EXTR_Pos 7 /*!< VADC_G QINR0: EXTR Position */
\r
5117 #define VADC_G_QINR0_EXTR_Msk (0x01UL << VADC_G_QINR0_EXTR_Pos) /*!< VADC_G QINR0: EXTR Mask */
\r
5119 /* -------------------------------- VADC_G_QBUR0 -------------------------------- */
\r
5120 #define VADC_G_QBUR0_REQCHNR_Pos 0 /*!< VADC_G QBUR0: REQCHNR Position */
\r
5121 #define VADC_G_QBUR0_REQCHNR_Msk (0x1fUL << VADC_G_QBUR0_REQCHNR_Pos) /*!< VADC_G QBUR0: REQCHNR Mask */
\r
5122 #define VADC_G_QBUR0_RF_Pos 5 /*!< VADC_G QBUR0: RF Position */
\r
5123 #define VADC_G_QBUR0_RF_Msk (0x01UL << VADC_G_QBUR0_RF_Pos) /*!< VADC_G QBUR0: RF Mask */
\r
5124 #define VADC_G_QBUR0_ENSI_Pos 6 /*!< VADC_G QBUR0: ENSI Position */
\r
5125 #define VADC_G_QBUR0_ENSI_Msk (0x01UL << VADC_G_QBUR0_ENSI_Pos) /*!< VADC_G QBUR0: ENSI Mask */
\r
5126 #define VADC_G_QBUR0_EXTR_Pos 7 /*!< VADC_G QBUR0: EXTR Position */
\r
5127 #define VADC_G_QBUR0_EXTR_Msk (0x01UL << VADC_G_QBUR0_EXTR_Pos) /*!< VADC_G QBUR0: EXTR Mask */
\r
5128 #define VADC_G_QBUR0_V_Pos 8 /*!< VADC_G QBUR0: V Position */
\r
5129 #define VADC_G_QBUR0_V_Msk (0x01UL << VADC_G_QBUR0_V_Pos) /*!< VADC_G QBUR0: V Mask */
\r
5131 /* -------------------------------- VADC_G_ASCTRL ------------------------------- */
\r
5132 #define VADC_G_ASCTRL_SRCRESREG_Pos 0 /*!< VADC_G ASCTRL: SRCRESREG Position */
\r
5133 #define VADC_G_ASCTRL_SRCRESREG_Msk (0x0fUL << VADC_G_ASCTRL_SRCRESREG_Pos) /*!< VADC_G ASCTRL: SRCRESREG Mask */
\r
5134 #define VADC_G_ASCTRL_XTSEL_Pos 8 /*!< VADC_G ASCTRL: XTSEL Position */
\r
5135 #define VADC_G_ASCTRL_XTSEL_Msk (0x0fUL << VADC_G_ASCTRL_XTSEL_Pos) /*!< VADC_G ASCTRL: XTSEL Mask */
\r
5136 #define VADC_G_ASCTRL_XTLVL_Pos 12 /*!< VADC_G ASCTRL: XTLVL Position */
\r
5137 #define VADC_G_ASCTRL_XTLVL_Msk (0x01UL << VADC_G_ASCTRL_XTLVL_Pos) /*!< VADC_G ASCTRL: XTLVL Mask */
\r
5138 #define VADC_G_ASCTRL_XTMODE_Pos 13 /*!< VADC_G ASCTRL: XTMODE Position */
\r
5139 #define VADC_G_ASCTRL_XTMODE_Msk (0x03UL << VADC_G_ASCTRL_XTMODE_Pos) /*!< VADC_G ASCTRL: XTMODE Mask */
\r
5140 #define VADC_G_ASCTRL_XTWC_Pos 15 /*!< VADC_G ASCTRL: XTWC Position */
\r
5141 #define VADC_G_ASCTRL_XTWC_Msk (0x01UL << VADC_G_ASCTRL_XTWC_Pos) /*!< VADC_G ASCTRL: XTWC Mask */
\r
5142 #define VADC_G_ASCTRL_GTSEL_Pos 16 /*!< VADC_G ASCTRL: GTSEL Position */
\r
5143 #define VADC_G_ASCTRL_GTSEL_Msk (0x0fUL << VADC_G_ASCTRL_GTSEL_Pos) /*!< VADC_G ASCTRL: GTSEL Mask */
\r
5144 #define VADC_G_ASCTRL_GTLVL_Pos 20 /*!< VADC_G ASCTRL: GTLVL Position */
\r
5145 #define VADC_G_ASCTRL_GTLVL_Msk (0x01UL << VADC_G_ASCTRL_GTLVL_Pos) /*!< VADC_G ASCTRL: GTLVL Mask */
\r
5146 #define VADC_G_ASCTRL_GTWC_Pos 23 /*!< VADC_G ASCTRL: GTWC Position */
\r
5147 #define VADC_G_ASCTRL_GTWC_Msk (0x01UL << VADC_G_ASCTRL_GTWC_Pos) /*!< VADC_G ASCTRL: GTWC Mask */
\r
5148 #define VADC_G_ASCTRL_TMEN_Pos 28 /*!< VADC_G ASCTRL: TMEN Position */
\r
5149 #define VADC_G_ASCTRL_TMEN_Msk (0x01UL << VADC_G_ASCTRL_TMEN_Pos) /*!< VADC_G ASCTRL: TMEN Mask */
\r
5150 #define VADC_G_ASCTRL_TMWC_Pos 31 /*!< VADC_G ASCTRL: TMWC Position */
\r
5151 #define VADC_G_ASCTRL_TMWC_Msk (0x01UL << VADC_G_ASCTRL_TMWC_Pos) /*!< VADC_G ASCTRL: TMWC Mask */
\r
5153 /* --------------------------------- VADC_G_ASMR -------------------------------- */
\r
5154 #define VADC_G_ASMR_ENGT_Pos 0 /*!< VADC_G ASMR: ENGT Position */
\r
5155 #define VADC_G_ASMR_ENGT_Msk (0x03UL << VADC_G_ASMR_ENGT_Pos) /*!< VADC_G ASMR: ENGT Mask */
\r
5156 #define VADC_G_ASMR_ENTR_Pos 2 /*!< VADC_G ASMR: ENTR Position */
\r
5157 #define VADC_G_ASMR_ENTR_Msk (0x01UL << VADC_G_ASMR_ENTR_Pos) /*!< VADC_G ASMR: ENTR Mask */
\r
5158 #define VADC_G_ASMR_ENSI_Pos 3 /*!< VADC_G ASMR: ENSI Position */
\r
5159 #define VADC_G_ASMR_ENSI_Msk (0x01UL << VADC_G_ASMR_ENSI_Pos) /*!< VADC_G ASMR: ENSI Mask */
\r
5160 #define VADC_G_ASMR_SCAN_Pos 4 /*!< VADC_G ASMR: SCAN Position */
\r
5161 #define VADC_G_ASMR_SCAN_Msk (0x01UL << VADC_G_ASMR_SCAN_Pos) /*!< VADC_G ASMR: SCAN Mask */
\r
5162 #define VADC_G_ASMR_LDM_Pos 5 /*!< VADC_G ASMR: LDM Position */
\r
5163 #define VADC_G_ASMR_LDM_Msk (0x01UL << VADC_G_ASMR_LDM_Pos) /*!< VADC_G ASMR: LDM Mask */
\r
5164 #define VADC_G_ASMR_REQGT_Pos 7 /*!< VADC_G ASMR: REQGT Position */
\r
5165 #define VADC_G_ASMR_REQGT_Msk (0x01UL << VADC_G_ASMR_REQGT_Pos) /*!< VADC_G ASMR: REQGT Mask */
\r
5166 #define VADC_G_ASMR_CLRPND_Pos 8 /*!< VADC_G ASMR: CLRPND Position */
\r
5167 #define VADC_G_ASMR_CLRPND_Msk (0x01UL << VADC_G_ASMR_CLRPND_Pos) /*!< VADC_G ASMR: CLRPND Mask */
\r
5168 #define VADC_G_ASMR_LDEV_Pos 9 /*!< VADC_G ASMR: LDEV Position */
\r
5169 #define VADC_G_ASMR_LDEV_Msk (0x01UL << VADC_G_ASMR_LDEV_Pos) /*!< VADC_G ASMR: LDEV Mask */
\r
5170 #define VADC_G_ASMR_RPTDIS_Pos 16 /*!< VADC_G ASMR: RPTDIS Position */
\r
5171 #define VADC_G_ASMR_RPTDIS_Msk (0x01UL << VADC_G_ASMR_RPTDIS_Pos) /*!< VADC_G ASMR: RPTDIS Mask */
\r
5173 /* -------------------------------- VADC_G_ASSEL -------------------------------- */
\r
5174 #define VADC_G_ASSEL_CHSEL0_Pos 0 /*!< VADC_G ASSEL: CHSEL0 Position */
\r
5175 #define VADC_G_ASSEL_CHSEL0_Msk (0x01UL << VADC_G_ASSEL_CHSEL0_Pos) /*!< VADC_G ASSEL: CHSEL0 Mask */
\r
5176 #define VADC_G_ASSEL_CHSEL1_Pos 1 /*!< VADC_G ASSEL: CHSEL1 Position */
\r
5177 #define VADC_G_ASSEL_CHSEL1_Msk (0x01UL << VADC_G_ASSEL_CHSEL1_Pos) /*!< VADC_G ASSEL: CHSEL1 Mask */
\r
5178 #define VADC_G_ASSEL_CHSEL2_Pos 2 /*!< VADC_G ASSEL: CHSEL2 Position */
\r
5179 #define VADC_G_ASSEL_CHSEL2_Msk (0x01UL << VADC_G_ASSEL_CHSEL2_Pos) /*!< VADC_G ASSEL: CHSEL2 Mask */
\r
5180 #define VADC_G_ASSEL_CHSEL3_Pos 3 /*!< VADC_G ASSEL: CHSEL3 Position */
\r
5181 #define VADC_G_ASSEL_CHSEL3_Msk (0x01UL << VADC_G_ASSEL_CHSEL3_Pos) /*!< VADC_G ASSEL: CHSEL3 Mask */
\r
5182 #define VADC_G_ASSEL_CHSEL4_Pos 4 /*!< VADC_G ASSEL: CHSEL4 Position */
\r
5183 #define VADC_G_ASSEL_CHSEL4_Msk (0x01UL << VADC_G_ASSEL_CHSEL4_Pos) /*!< VADC_G ASSEL: CHSEL4 Mask */
\r
5184 #define VADC_G_ASSEL_CHSEL5_Pos 5 /*!< VADC_G ASSEL: CHSEL5 Position */
\r
5185 #define VADC_G_ASSEL_CHSEL5_Msk (0x01UL << VADC_G_ASSEL_CHSEL5_Pos) /*!< VADC_G ASSEL: CHSEL5 Mask */
\r
5186 #define VADC_G_ASSEL_CHSEL6_Pos 6 /*!< VADC_G ASSEL: CHSEL6 Position */
\r
5187 #define VADC_G_ASSEL_CHSEL6_Msk (0x01UL << VADC_G_ASSEL_CHSEL6_Pos) /*!< VADC_G ASSEL: CHSEL6 Mask */
\r
5188 #define VADC_G_ASSEL_CHSEL7_Pos 7 /*!< VADC_G ASSEL: CHSEL7 Position */
\r
5189 #define VADC_G_ASSEL_CHSEL7_Msk (0x01UL << VADC_G_ASSEL_CHSEL7_Pos) /*!< VADC_G ASSEL: CHSEL7 Mask */
\r
5191 /* -------------------------------- VADC_G_ASPND -------------------------------- */
\r
5192 #define VADC_G_ASPND_CHPND0_Pos 0 /*!< VADC_G ASPND: CHPND0 Position */
\r
5193 #define VADC_G_ASPND_CHPND0_Msk (0x01UL << VADC_G_ASPND_CHPND0_Pos) /*!< VADC_G ASPND: CHPND0 Mask */
\r
5194 #define VADC_G_ASPND_CHPND1_Pos 1 /*!< VADC_G ASPND: CHPND1 Position */
\r
5195 #define VADC_G_ASPND_CHPND1_Msk (0x01UL << VADC_G_ASPND_CHPND1_Pos) /*!< VADC_G ASPND: CHPND1 Mask */
\r
5196 #define VADC_G_ASPND_CHPND2_Pos 2 /*!< VADC_G ASPND: CHPND2 Position */
\r
5197 #define VADC_G_ASPND_CHPND2_Msk (0x01UL << VADC_G_ASPND_CHPND2_Pos) /*!< VADC_G ASPND: CHPND2 Mask */
\r
5198 #define VADC_G_ASPND_CHPND3_Pos 3 /*!< VADC_G ASPND: CHPND3 Position */
\r
5199 #define VADC_G_ASPND_CHPND3_Msk (0x01UL << VADC_G_ASPND_CHPND3_Pos) /*!< VADC_G ASPND: CHPND3 Mask */
\r
5200 #define VADC_G_ASPND_CHPND4_Pos 4 /*!< VADC_G ASPND: CHPND4 Position */
\r
5201 #define VADC_G_ASPND_CHPND4_Msk (0x01UL << VADC_G_ASPND_CHPND4_Pos) /*!< VADC_G ASPND: CHPND4 Mask */
\r
5202 #define VADC_G_ASPND_CHPND5_Pos 5 /*!< VADC_G ASPND: CHPND5 Position */
\r
5203 #define VADC_G_ASPND_CHPND5_Msk (0x01UL << VADC_G_ASPND_CHPND5_Pos) /*!< VADC_G ASPND: CHPND5 Mask */
\r
5204 #define VADC_G_ASPND_CHPND6_Pos 6 /*!< VADC_G ASPND: CHPND6 Position */
\r
5205 #define VADC_G_ASPND_CHPND6_Msk (0x01UL << VADC_G_ASPND_CHPND6_Pos) /*!< VADC_G ASPND: CHPND6 Mask */
\r
5206 #define VADC_G_ASPND_CHPND7_Pos 7 /*!< VADC_G ASPND: CHPND7 Position */
\r
5207 #define VADC_G_ASPND_CHPND7_Msk (0x01UL << VADC_G_ASPND_CHPND7_Pos) /*!< VADC_G ASPND: CHPND7 Mask */
\r
5209 /* -------------------------------- VADC_G_CEFLAG ------------------------------- */
\r
5210 #define VADC_G_CEFLAG_CEV0_Pos 0 /*!< VADC_G CEFLAG: CEV0 Position */
\r
5211 #define VADC_G_CEFLAG_CEV0_Msk (0x01UL << VADC_G_CEFLAG_CEV0_Pos) /*!< VADC_G CEFLAG: CEV0 Mask */
\r
5212 #define VADC_G_CEFLAG_CEV1_Pos 1 /*!< VADC_G CEFLAG: CEV1 Position */
\r
5213 #define VADC_G_CEFLAG_CEV1_Msk (0x01UL << VADC_G_CEFLAG_CEV1_Pos) /*!< VADC_G CEFLAG: CEV1 Mask */
\r
5214 #define VADC_G_CEFLAG_CEV2_Pos 2 /*!< VADC_G CEFLAG: CEV2 Position */
\r
5215 #define VADC_G_CEFLAG_CEV2_Msk (0x01UL << VADC_G_CEFLAG_CEV2_Pos) /*!< VADC_G CEFLAG: CEV2 Mask */
\r
5216 #define VADC_G_CEFLAG_CEV3_Pos 3 /*!< VADC_G CEFLAG: CEV3 Position */
\r
5217 #define VADC_G_CEFLAG_CEV3_Msk (0x01UL << VADC_G_CEFLAG_CEV3_Pos) /*!< VADC_G CEFLAG: CEV3 Mask */
\r
5218 #define VADC_G_CEFLAG_CEV4_Pos 4 /*!< VADC_G CEFLAG: CEV4 Position */
\r
5219 #define VADC_G_CEFLAG_CEV4_Msk (0x01UL << VADC_G_CEFLAG_CEV4_Pos) /*!< VADC_G CEFLAG: CEV4 Mask */
\r
5220 #define VADC_G_CEFLAG_CEV5_Pos 5 /*!< VADC_G CEFLAG: CEV5 Position */
\r
5221 #define VADC_G_CEFLAG_CEV5_Msk (0x01UL << VADC_G_CEFLAG_CEV5_Pos) /*!< VADC_G CEFLAG: CEV5 Mask */
\r
5222 #define VADC_G_CEFLAG_CEV6_Pos 6 /*!< VADC_G CEFLAG: CEV6 Position */
\r
5223 #define VADC_G_CEFLAG_CEV6_Msk (0x01UL << VADC_G_CEFLAG_CEV6_Pos) /*!< VADC_G CEFLAG: CEV6 Mask */
\r
5224 #define VADC_G_CEFLAG_CEV7_Pos 7 /*!< VADC_G CEFLAG: CEV7 Position */
\r
5225 #define VADC_G_CEFLAG_CEV7_Msk (0x01UL << VADC_G_CEFLAG_CEV7_Pos) /*!< VADC_G CEFLAG: CEV7 Mask */
\r
5227 /* -------------------------------- VADC_G_REFLAG ------------------------------- */
\r
5228 #define VADC_G_REFLAG_REV0_Pos 0 /*!< VADC_G REFLAG: REV0 Position */
\r
5229 #define VADC_G_REFLAG_REV0_Msk (0x01UL << VADC_G_REFLAG_REV0_Pos) /*!< VADC_G REFLAG: REV0 Mask */
\r
5230 #define VADC_G_REFLAG_REV1_Pos 1 /*!< VADC_G REFLAG: REV1 Position */
\r
5231 #define VADC_G_REFLAG_REV1_Msk (0x01UL << VADC_G_REFLAG_REV1_Pos) /*!< VADC_G REFLAG: REV1 Mask */
\r
5232 #define VADC_G_REFLAG_REV2_Pos 2 /*!< VADC_G REFLAG: REV2 Position */
\r
5233 #define VADC_G_REFLAG_REV2_Msk (0x01UL << VADC_G_REFLAG_REV2_Pos) /*!< VADC_G REFLAG: REV2 Mask */
\r
5234 #define VADC_G_REFLAG_REV3_Pos 3 /*!< VADC_G REFLAG: REV3 Position */
\r
5235 #define VADC_G_REFLAG_REV3_Msk (0x01UL << VADC_G_REFLAG_REV3_Pos) /*!< VADC_G REFLAG: REV3 Mask */
\r
5236 #define VADC_G_REFLAG_REV4_Pos 4 /*!< VADC_G REFLAG: REV4 Position */
\r
5237 #define VADC_G_REFLAG_REV4_Msk (0x01UL << VADC_G_REFLAG_REV4_Pos) /*!< VADC_G REFLAG: REV4 Mask */
\r
5238 #define VADC_G_REFLAG_REV5_Pos 5 /*!< VADC_G REFLAG: REV5 Position */
\r
5239 #define VADC_G_REFLAG_REV5_Msk (0x01UL << VADC_G_REFLAG_REV5_Pos) /*!< VADC_G REFLAG: REV5 Mask */
\r
5240 #define VADC_G_REFLAG_REV6_Pos 6 /*!< VADC_G REFLAG: REV6 Position */
\r
5241 #define VADC_G_REFLAG_REV6_Msk (0x01UL << VADC_G_REFLAG_REV6_Pos) /*!< VADC_G REFLAG: REV6 Mask */
\r
5242 #define VADC_G_REFLAG_REV7_Pos 7 /*!< VADC_G REFLAG: REV7 Position */
\r
5243 #define VADC_G_REFLAG_REV7_Msk (0x01UL << VADC_G_REFLAG_REV7_Pos) /*!< VADC_G REFLAG: REV7 Mask */
\r
5244 #define VADC_G_REFLAG_REV8_Pos 8 /*!< VADC_G REFLAG: REV8 Position */
\r
5245 #define VADC_G_REFLAG_REV8_Msk (0x01UL << VADC_G_REFLAG_REV8_Pos) /*!< VADC_G REFLAG: REV8 Mask */
\r
5246 #define VADC_G_REFLAG_REV9_Pos 9 /*!< VADC_G REFLAG: REV9 Position */
\r
5247 #define VADC_G_REFLAG_REV9_Msk (0x01UL << VADC_G_REFLAG_REV9_Pos) /*!< VADC_G REFLAG: REV9 Mask */
\r
5248 #define VADC_G_REFLAG_REV10_Pos 10 /*!< VADC_G REFLAG: REV10 Position */
\r
5249 #define VADC_G_REFLAG_REV10_Msk (0x01UL << VADC_G_REFLAG_REV10_Pos) /*!< VADC_G REFLAG: REV10 Mask */
\r
5250 #define VADC_G_REFLAG_REV11_Pos 11 /*!< VADC_G REFLAG: REV11 Position */
\r
5251 #define VADC_G_REFLAG_REV11_Msk (0x01UL << VADC_G_REFLAG_REV11_Pos) /*!< VADC_G REFLAG: REV11 Mask */
\r
5252 #define VADC_G_REFLAG_REV12_Pos 12 /*!< VADC_G REFLAG: REV12 Position */
\r
5253 #define VADC_G_REFLAG_REV12_Msk (0x01UL << VADC_G_REFLAG_REV12_Pos) /*!< VADC_G REFLAG: REV12 Mask */
\r
5254 #define VADC_G_REFLAG_REV13_Pos 13 /*!< VADC_G REFLAG: REV13 Position */
\r
5255 #define VADC_G_REFLAG_REV13_Msk (0x01UL << VADC_G_REFLAG_REV13_Pos) /*!< VADC_G REFLAG: REV13 Mask */
\r
5256 #define VADC_G_REFLAG_REV14_Pos 14 /*!< VADC_G REFLAG: REV14 Position */
\r
5257 #define VADC_G_REFLAG_REV14_Msk (0x01UL << VADC_G_REFLAG_REV14_Pos) /*!< VADC_G REFLAG: REV14 Mask */
\r
5258 #define VADC_G_REFLAG_REV15_Pos 15 /*!< VADC_G REFLAG: REV15 Position */
\r
5259 #define VADC_G_REFLAG_REV15_Msk (0x01UL << VADC_G_REFLAG_REV15_Pos) /*!< VADC_G REFLAG: REV15 Mask */
\r
5261 /* -------------------------------- VADC_G_SEFLAG ------------------------------- */
\r
5262 #define VADC_G_SEFLAG_SEV0_Pos 0 /*!< VADC_G SEFLAG: SEV0 Position */
\r
5263 #define VADC_G_SEFLAG_SEV0_Msk (0x01UL << VADC_G_SEFLAG_SEV0_Pos) /*!< VADC_G SEFLAG: SEV0 Mask */
\r
5264 #define VADC_G_SEFLAG_SEV1_Pos 1 /*!< VADC_G SEFLAG: SEV1 Position */
\r
5265 #define VADC_G_SEFLAG_SEV1_Msk (0x01UL << VADC_G_SEFLAG_SEV1_Pos) /*!< VADC_G SEFLAG: SEV1 Mask */
\r
5267 /* -------------------------------- VADC_G_CEFCLR ------------------------------- */
\r
5268 #define VADC_G_CEFCLR_CEV0_Pos 0 /*!< VADC_G CEFCLR: CEV0 Position */
\r
5269 #define VADC_G_CEFCLR_CEV0_Msk (0x01UL << VADC_G_CEFCLR_CEV0_Pos) /*!< VADC_G CEFCLR: CEV0 Mask */
\r
5270 #define VADC_G_CEFCLR_CEV1_Pos 1 /*!< VADC_G CEFCLR: CEV1 Position */
\r
5271 #define VADC_G_CEFCLR_CEV1_Msk (0x01UL << VADC_G_CEFCLR_CEV1_Pos) /*!< VADC_G CEFCLR: CEV1 Mask */
\r
5272 #define VADC_G_CEFCLR_CEV2_Pos 2 /*!< VADC_G CEFCLR: CEV2 Position */
\r
5273 #define VADC_G_CEFCLR_CEV2_Msk (0x01UL << VADC_G_CEFCLR_CEV2_Pos) /*!< VADC_G CEFCLR: CEV2 Mask */
\r
5274 #define VADC_G_CEFCLR_CEV3_Pos 3 /*!< VADC_G CEFCLR: CEV3 Position */
\r
5275 #define VADC_G_CEFCLR_CEV3_Msk (0x01UL << VADC_G_CEFCLR_CEV3_Pos) /*!< VADC_G CEFCLR: CEV3 Mask */
\r
5276 #define VADC_G_CEFCLR_CEV4_Pos 4 /*!< VADC_G CEFCLR: CEV4 Position */
\r
5277 #define VADC_G_CEFCLR_CEV4_Msk (0x01UL << VADC_G_CEFCLR_CEV4_Pos) /*!< VADC_G CEFCLR: CEV4 Mask */
\r
5278 #define VADC_G_CEFCLR_CEV5_Pos 5 /*!< VADC_G CEFCLR: CEV5 Position */
\r
5279 #define VADC_G_CEFCLR_CEV5_Msk (0x01UL << VADC_G_CEFCLR_CEV5_Pos) /*!< VADC_G CEFCLR: CEV5 Mask */
\r
5280 #define VADC_G_CEFCLR_CEV6_Pos 6 /*!< VADC_G CEFCLR: CEV6 Position */
\r
5281 #define VADC_G_CEFCLR_CEV6_Msk (0x01UL << VADC_G_CEFCLR_CEV6_Pos) /*!< VADC_G CEFCLR: CEV6 Mask */
\r
5282 #define VADC_G_CEFCLR_CEV7_Pos 7 /*!< VADC_G CEFCLR: CEV7 Position */
\r
5283 #define VADC_G_CEFCLR_CEV7_Msk (0x01UL << VADC_G_CEFCLR_CEV7_Pos) /*!< VADC_G CEFCLR: CEV7 Mask */
\r
5285 /* -------------------------------- VADC_G_REFCLR ------------------------------- */
\r
5286 #define VADC_G_REFCLR_REV0_Pos 0 /*!< VADC_G REFCLR: REV0 Position */
\r
5287 #define VADC_G_REFCLR_REV0_Msk (0x01UL << VADC_G_REFCLR_REV0_Pos) /*!< VADC_G REFCLR: REV0 Mask */
\r
5288 #define VADC_G_REFCLR_REV1_Pos 1 /*!< VADC_G REFCLR: REV1 Position */
\r
5289 #define VADC_G_REFCLR_REV1_Msk (0x01UL << VADC_G_REFCLR_REV1_Pos) /*!< VADC_G REFCLR: REV1 Mask */
\r
5290 #define VADC_G_REFCLR_REV2_Pos 2 /*!< VADC_G REFCLR: REV2 Position */
\r
5291 #define VADC_G_REFCLR_REV2_Msk (0x01UL << VADC_G_REFCLR_REV2_Pos) /*!< VADC_G REFCLR: REV2 Mask */
\r
5292 #define VADC_G_REFCLR_REV3_Pos 3 /*!< VADC_G REFCLR: REV3 Position */
\r
5293 #define VADC_G_REFCLR_REV3_Msk (0x01UL << VADC_G_REFCLR_REV3_Pos) /*!< VADC_G REFCLR: REV3 Mask */
\r
5294 #define VADC_G_REFCLR_REV4_Pos 4 /*!< VADC_G REFCLR: REV4 Position */
\r
5295 #define VADC_G_REFCLR_REV4_Msk (0x01UL << VADC_G_REFCLR_REV4_Pos) /*!< VADC_G REFCLR: REV4 Mask */
\r
5296 #define VADC_G_REFCLR_REV5_Pos 5 /*!< VADC_G REFCLR: REV5 Position */
\r
5297 #define VADC_G_REFCLR_REV5_Msk (0x01UL << VADC_G_REFCLR_REV5_Pos) /*!< VADC_G REFCLR: REV5 Mask */
\r
5298 #define VADC_G_REFCLR_REV6_Pos 6 /*!< VADC_G REFCLR: REV6 Position */
\r
5299 #define VADC_G_REFCLR_REV6_Msk (0x01UL << VADC_G_REFCLR_REV6_Pos) /*!< VADC_G REFCLR: REV6 Mask */
\r
5300 #define VADC_G_REFCLR_REV7_Pos 7 /*!< VADC_G REFCLR: REV7 Position */
\r
5301 #define VADC_G_REFCLR_REV7_Msk (0x01UL << VADC_G_REFCLR_REV7_Pos) /*!< VADC_G REFCLR: REV7 Mask */
\r
5302 #define VADC_G_REFCLR_REV8_Pos 8 /*!< VADC_G REFCLR: REV8 Position */
\r
5303 #define VADC_G_REFCLR_REV8_Msk (0x01UL << VADC_G_REFCLR_REV8_Pos) /*!< VADC_G REFCLR: REV8 Mask */
\r
5304 #define VADC_G_REFCLR_REV9_Pos 9 /*!< VADC_G REFCLR: REV9 Position */
\r
5305 #define VADC_G_REFCLR_REV9_Msk (0x01UL << VADC_G_REFCLR_REV9_Pos) /*!< VADC_G REFCLR: REV9 Mask */
\r
5306 #define VADC_G_REFCLR_REV10_Pos 10 /*!< VADC_G REFCLR: REV10 Position */
\r
5307 #define VADC_G_REFCLR_REV10_Msk (0x01UL << VADC_G_REFCLR_REV10_Pos) /*!< VADC_G REFCLR: REV10 Mask */
\r
5308 #define VADC_G_REFCLR_REV11_Pos 11 /*!< VADC_G REFCLR: REV11 Position */
\r
5309 #define VADC_G_REFCLR_REV11_Msk (0x01UL << VADC_G_REFCLR_REV11_Pos) /*!< VADC_G REFCLR: REV11 Mask */
\r
5310 #define VADC_G_REFCLR_REV12_Pos 12 /*!< VADC_G REFCLR: REV12 Position */
\r
5311 #define VADC_G_REFCLR_REV12_Msk (0x01UL << VADC_G_REFCLR_REV12_Pos) /*!< VADC_G REFCLR: REV12 Mask */
\r
5312 #define VADC_G_REFCLR_REV13_Pos 13 /*!< VADC_G REFCLR: REV13 Position */
\r
5313 #define VADC_G_REFCLR_REV13_Msk (0x01UL << VADC_G_REFCLR_REV13_Pos) /*!< VADC_G REFCLR: REV13 Mask */
\r
5314 #define VADC_G_REFCLR_REV14_Pos 14 /*!< VADC_G REFCLR: REV14 Position */
\r
5315 #define VADC_G_REFCLR_REV14_Msk (0x01UL << VADC_G_REFCLR_REV14_Pos) /*!< VADC_G REFCLR: REV14 Mask */
\r
5316 #define VADC_G_REFCLR_REV15_Pos 15 /*!< VADC_G REFCLR: REV15 Position */
\r
5317 #define VADC_G_REFCLR_REV15_Msk (0x01UL << VADC_G_REFCLR_REV15_Pos) /*!< VADC_G REFCLR: REV15 Mask */
\r
5319 /* -------------------------------- VADC_G_SEFCLR ------------------------------- */
\r
5320 #define VADC_G_SEFCLR_SEV0_Pos 0 /*!< VADC_G SEFCLR: SEV0 Position */
\r
5321 #define VADC_G_SEFCLR_SEV0_Msk (0x01UL << VADC_G_SEFCLR_SEV0_Pos) /*!< VADC_G SEFCLR: SEV0 Mask */
\r
5322 #define VADC_G_SEFCLR_SEV1_Pos 1 /*!< VADC_G SEFCLR: SEV1 Position */
\r
5323 #define VADC_G_SEFCLR_SEV1_Msk (0x01UL << VADC_G_SEFCLR_SEV1_Pos) /*!< VADC_G SEFCLR: SEV1 Mask */
\r
5325 /* -------------------------------- VADC_G_CEVNP0 ------------------------------- */
\r
5326 #define VADC_G_CEVNP0_CEV0NP_Pos 0 /*!< VADC_G CEVNP0: CEV0NP Position */
\r
5327 #define VADC_G_CEVNP0_CEV0NP_Msk (0x0fUL << VADC_G_CEVNP0_CEV0NP_Pos) /*!< VADC_G CEVNP0: CEV0NP Mask */
\r
5328 #define VADC_G_CEVNP0_CEV1NP_Pos 4 /*!< VADC_G CEVNP0: CEV1NP Position */
\r
5329 #define VADC_G_CEVNP0_CEV1NP_Msk (0x0fUL << VADC_G_CEVNP0_CEV1NP_Pos) /*!< VADC_G CEVNP0: CEV1NP Mask */
\r
5330 #define VADC_G_CEVNP0_CEV2NP_Pos 8 /*!< VADC_G CEVNP0: CEV2NP Position */
\r
5331 #define VADC_G_CEVNP0_CEV2NP_Msk (0x0fUL << VADC_G_CEVNP0_CEV2NP_Pos) /*!< VADC_G CEVNP0: CEV2NP Mask */
\r
5332 #define VADC_G_CEVNP0_CEV3NP_Pos 12 /*!< VADC_G CEVNP0: CEV3NP Position */
\r
5333 #define VADC_G_CEVNP0_CEV3NP_Msk (0x0fUL << VADC_G_CEVNP0_CEV3NP_Pos) /*!< VADC_G CEVNP0: CEV3NP Mask */
\r
5334 #define VADC_G_CEVNP0_CEV4NP_Pos 16 /*!< VADC_G CEVNP0: CEV4NP Position */
\r
5335 #define VADC_G_CEVNP0_CEV4NP_Msk (0x0fUL << VADC_G_CEVNP0_CEV4NP_Pos) /*!< VADC_G CEVNP0: CEV4NP Mask */
\r
5336 #define VADC_G_CEVNP0_CEV5NP_Pos 20 /*!< VADC_G CEVNP0: CEV5NP Position */
\r
5337 #define VADC_G_CEVNP0_CEV5NP_Msk (0x0fUL << VADC_G_CEVNP0_CEV5NP_Pos) /*!< VADC_G CEVNP0: CEV5NP Mask */
\r
5338 #define VADC_G_CEVNP0_CEV6NP_Pos 24 /*!< VADC_G CEVNP0: CEV6NP Position */
\r
5339 #define VADC_G_CEVNP0_CEV6NP_Msk (0x0fUL << VADC_G_CEVNP0_CEV6NP_Pos) /*!< VADC_G CEVNP0: CEV6NP Mask */
\r
5340 #define VADC_G_CEVNP0_CEV7NP_Pos 28 /*!< VADC_G CEVNP0: CEV7NP Position */
\r
5341 #define VADC_G_CEVNP0_CEV7NP_Msk (0x0fUL << VADC_G_CEVNP0_CEV7NP_Pos) /*!< VADC_G CEVNP0: CEV7NP Mask */
\r
5343 /* -------------------------------- VADC_G_REVNP0 ------------------------------- */
\r
5344 #define VADC_G_REVNP0_REV0NP_Pos 0 /*!< VADC_G REVNP0: REV0NP Position */
\r
5345 #define VADC_G_REVNP0_REV0NP_Msk (0x0fUL << VADC_G_REVNP0_REV0NP_Pos) /*!< VADC_G REVNP0: REV0NP Mask */
\r
5346 #define VADC_G_REVNP0_REV1NP_Pos 4 /*!< VADC_G REVNP0: REV1NP Position */
\r
5347 #define VADC_G_REVNP0_REV1NP_Msk (0x0fUL << VADC_G_REVNP0_REV1NP_Pos) /*!< VADC_G REVNP0: REV1NP Mask */
\r
5348 #define VADC_G_REVNP0_REV2NP_Pos 8 /*!< VADC_G REVNP0: REV2NP Position */
\r
5349 #define VADC_G_REVNP0_REV2NP_Msk (0x0fUL << VADC_G_REVNP0_REV2NP_Pos) /*!< VADC_G REVNP0: REV2NP Mask */
\r
5350 #define VADC_G_REVNP0_REV3NP_Pos 12 /*!< VADC_G REVNP0: REV3NP Position */
\r
5351 #define VADC_G_REVNP0_REV3NP_Msk (0x0fUL << VADC_G_REVNP0_REV3NP_Pos) /*!< VADC_G REVNP0: REV3NP Mask */
\r
5352 #define VADC_G_REVNP0_REV4NP_Pos 16 /*!< VADC_G REVNP0: REV4NP Position */
\r
5353 #define VADC_G_REVNP0_REV4NP_Msk (0x0fUL << VADC_G_REVNP0_REV4NP_Pos) /*!< VADC_G REVNP0: REV4NP Mask */
\r
5354 #define VADC_G_REVNP0_REV5NP_Pos 20 /*!< VADC_G REVNP0: REV5NP Position */
\r
5355 #define VADC_G_REVNP0_REV5NP_Msk (0x0fUL << VADC_G_REVNP0_REV5NP_Pos) /*!< VADC_G REVNP0: REV5NP Mask */
\r
5356 #define VADC_G_REVNP0_REV6NP_Pos 24 /*!< VADC_G REVNP0: REV6NP Position */
\r
5357 #define VADC_G_REVNP0_REV6NP_Msk (0x0fUL << VADC_G_REVNP0_REV6NP_Pos) /*!< VADC_G REVNP0: REV6NP Mask */
\r
5358 #define VADC_G_REVNP0_REV7NP_Pos 28 /*!< VADC_G REVNP0: REV7NP Position */
\r
5359 #define VADC_G_REVNP0_REV7NP_Msk (0x0fUL << VADC_G_REVNP0_REV7NP_Pos) /*!< VADC_G REVNP0: REV7NP Mask */
\r
5361 /* -------------------------------- VADC_G_REVNP1 ------------------------------- */
\r
5362 #define VADC_G_REVNP1_REV8NP_Pos 0 /*!< VADC_G REVNP1: REV8NP Position */
\r
5363 #define VADC_G_REVNP1_REV8NP_Msk (0x0fUL << VADC_G_REVNP1_REV8NP_Pos) /*!< VADC_G REVNP1: REV8NP Mask */
\r
5364 #define VADC_G_REVNP1_REV9NP_Pos 4 /*!< VADC_G REVNP1: REV9NP Position */
\r
5365 #define VADC_G_REVNP1_REV9NP_Msk (0x0fUL << VADC_G_REVNP1_REV9NP_Pos) /*!< VADC_G REVNP1: REV9NP Mask */
\r
5366 #define VADC_G_REVNP1_REV10NP_Pos 8 /*!< VADC_G REVNP1: REV10NP Position */
\r
5367 #define VADC_G_REVNP1_REV10NP_Msk (0x0fUL << VADC_G_REVNP1_REV10NP_Pos) /*!< VADC_G REVNP1: REV10NP Mask */
\r
5368 #define VADC_G_REVNP1_REV11NP_Pos 12 /*!< VADC_G REVNP1: REV11NP Position */
\r
5369 #define VADC_G_REVNP1_REV11NP_Msk (0x0fUL << VADC_G_REVNP1_REV11NP_Pos) /*!< VADC_G REVNP1: REV11NP Mask */
\r
5370 #define VADC_G_REVNP1_REV12NP_Pos 16 /*!< VADC_G REVNP1: REV12NP Position */
\r
5371 #define VADC_G_REVNP1_REV12NP_Msk (0x0fUL << VADC_G_REVNP1_REV12NP_Pos) /*!< VADC_G REVNP1: REV12NP Mask */
\r
5372 #define VADC_G_REVNP1_REV13NP_Pos 20 /*!< VADC_G REVNP1: REV13NP Position */
\r
5373 #define VADC_G_REVNP1_REV13NP_Msk (0x0fUL << VADC_G_REVNP1_REV13NP_Pos) /*!< VADC_G REVNP1: REV13NP Mask */
\r
5374 #define VADC_G_REVNP1_REV14NP_Pos 24 /*!< VADC_G REVNP1: REV14NP Position */
\r
5375 #define VADC_G_REVNP1_REV14NP_Msk (0x0fUL << VADC_G_REVNP1_REV14NP_Pos) /*!< VADC_G REVNP1: REV14NP Mask */
\r
5376 #define VADC_G_REVNP1_REV15NP_Pos 28 /*!< VADC_G REVNP1: REV15NP Position */
\r
5377 #define VADC_G_REVNP1_REV15NP_Msk (0x0fUL << VADC_G_REVNP1_REV15NP_Pos) /*!< VADC_G REVNP1: REV15NP Mask */
\r
5379 /* -------------------------------- VADC_G_SEVNP -------------------------------- */
\r
5380 #define VADC_G_SEVNP_SEV0NP_Pos 0 /*!< VADC_G SEVNP: SEV0NP Position */
\r
5381 #define VADC_G_SEVNP_SEV0NP_Msk (0x0fUL << VADC_G_SEVNP_SEV0NP_Pos) /*!< VADC_G SEVNP: SEV0NP Mask */
\r
5382 #define VADC_G_SEVNP_SEV1NP_Pos 4 /*!< VADC_G SEVNP: SEV1NP Position */
\r
5383 #define VADC_G_SEVNP_SEV1NP_Msk (0x0fUL << VADC_G_SEVNP_SEV1NP_Pos) /*!< VADC_G SEVNP: SEV1NP Mask */
\r
5385 /* -------------------------------- VADC_G_SRACT -------------------------------- */
\r
5386 #define VADC_G_SRACT_AGSR0_Pos 0 /*!< VADC_G SRACT: AGSR0 Position */
\r
5387 #define VADC_G_SRACT_AGSR0_Msk (0x01UL << VADC_G_SRACT_AGSR0_Pos) /*!< VADC_G SRACT: AGSR0 Mask */
\r
5388 #define VADC_G_SRACT_AGSR1_Pos 1 /*!< VADC_G SRACT: AGSR1 Position */
\r
5389 #define VADC_G_SRACT_AGSR1_Msk (0x01UL << VADC_G_SRACT_AGSR1_Pos) /*!< VADC_G SRACT: AGSR1 Mask */
\r
5390 #define VADC_G_SRACT_ASSR0_Pos 8 /*!< VADC_G SRACT: ASSR0 Position */
\r
5391 #define VADC_G_SRACT_ASSR0_Msk (0x01UL << VADC_G_SRACT_ASSR0_Pos) /*!< VADC_G SRACT: ASSR0 Mask */
\r
5392 #define VADC_G_SRACT_ASSR1_Pos 9 /*!< VADC_G SRACT: ASSR1 Position */
\r
5393 #define VADC_G_SRACT_ASSR1_Msk (0x01UL << VADC_G_SRACT_ASSR1_Pos) /*!< VADC_G SRACT: ASSR1 Mask */
\r
5394 #define VADC_G_SRACT_ASSR2_Pos 10 /*!< VADC_G SRACT: ASSR2 Position */
\r
5395 #define VADC_G_SRACT_ASSR2_Msk (0x01UL << VADC_G_SRACT_ASSR2_Pos) /*!< VADC_G SRACT: ASSR2 Mask */
\r
5396 #define VADC_G_SRACT_ASSR3_Pos 11 /*!< VADC_G SRACT: ASSR3 Position */
\r
5397 #define VADC_G_SRACT_ASSR3_Msk (0x01UL << VADC_G_SRACT_ASSR3_Pos) /*!< VADC_G SRACT: ASSR3 Mask */
\r
5399 /* ------------------------------- VADC_G_EMUXCTR ------------------------------- */
\r
5400 #define VADC_G_EMUXCTR_EMUXSET_Pos 0 /*!< VADC_G EMUXCTR: EMUXSET Position */
\r
5401 #define VADC_G_EMUXCTR_EMUXSET_Msk (0x07UL << VADC_G_EMUXCTR_EMUXSET_Pos) /*!< VADC_G EMUXCTR: EMUXSET Mask */
\r
5402 #define VADC_G_EMUXCTR_EMUXACT_Pos 8 /*!< VADC_G EMUXCTR: EMUXACT Position */
\r
5403 #define VADC_G_EMUXCTR_EMUXACT_Msk (0x07UL << VADC_G_EMUXCTR_EMUXACT_Pos) /*!< VADC_G EMUXCTR: EMUXACT Mask */
\r
5404 #define VADC_G_EMUXCTR_EMUXCH_Pos 16 /*!< VADC_G EMUXCTR: EMUXCH Position */
\r
5405 #define VADC_G_EMUXCTR_EMUXCH_Msk (0x000003ffUL << VADC_G_EMUXCTR_EMUXCH_Pos) /*!< VADC_G EMUXCTR: EMUXCH Mask */
\r
5406 #define VADC_G_EMUXCTR_EMUXMODE_Pos 26 /*!< VADC_G EMUXCTR: EMUXMODE Position */
\r
5407 #define VADC_G_EMUXCTR_EMUXMODE_Msk (0x03UL << VADC_G_EMUXCTR_EMUXMODE_Pos) /*!< VADC_G EMUXCTR: EMUXMODE Mask */
\r
5408 #define VADC_G_EMUXCTR_EMXCOD_Pos 28 /*!< VADC_G EMUXCTR: EMXCOD Position */
\r
5409 #define VADC_G_EMUXCTR_EMXCOD_Msk (0x01UL << VADC_G_EMUXCTR_EMXCOD_Pos) /*!< VADC_G EMUXCTR: EMXCOD Mask */
\r
5410 #define VADC_G_EMUXCTR_EMXST_Pos 29 /*!< VADC_G EMUXCTR: EMXST Position */
\r
5411 #define VADC_G_EMUXCTR_EMXST_Msk (0x01UL << VADC_G_EMUXCTR_EMXST_Pos) /*!< VADC_G EMUXCTR: EMXST Mask */
\r
5412 #define VADC_G_EMUXCTR_EMXCSS_Pos 30 /*!< VADC_G EMUXCTR: EMXCSS Position */
\r
5413 #define VADC_G_EMUXCTR_EMXCSS_Msk (0x01UL << VADC_G_EMUXCTR_EMXCSS_Pos) /*!< VADC_G EMUXCTR: EMXCSS Mask */
\r
5414 #define VADC_G_EMUXCTR_EMXWC_Pos 31 /*!< VADC_G EMUXCTR: EMXWC Position */
\r
5415 #define VADC_G_EMUXCTR_EMXWC_Msk (0x01UL << VADC_G_EMUXCTR_EMXWC_Pos) /*!< VADC_G EMUXCTR: EMXWC Mask */
\r
5417 /* --------------------------------- VADC_G_VFR --------------------------------- */
\r
5418 #define VADC_G_VFR_VF0_Pos 0 /*!< VADC_G VFR: VF0 Position */
\r
5419 #define VADC_G_VFR_VF0_Msk (0x01UL << VADC_G_VFR_VF0_Pos) /*!< VADC_G VFR: VF0 Mask */
\r
5420 #define VADC_G_VFR_VF1_Pos 1 /*!< VADC_G VFR: VF1 Position */
\r
5421 #define VADC_G_VFR_VF1_Msk (0x01UL << VADC_G_VFR_VF1_Pos) /*!< VADC_G VFR: VF1 Mask */
\r
5422 #define VADC_G_VFR_VF2_Pos 2 /*!< VADC_G VFR: VF2 Position */
\r
5423 #define VADC_G_VFR_VF2_Msk (0x01UL << VADC_G_VFR_VF2_Pos) /*!< VADC_G VFR: VF2 Mask */
\r
5424 #define VADC_G_VFR_VF3_Pos 3 /*!< VADC_G VFR: VF3 Position */
\r
5425 #define VADC_G_VFR_VF3_Msk (0x01UL << VADC_G_VFR_VF3_Pos) /*!< VADC_G VFR: VF3 Mask */
\r
5426 #define VADC_G_VFR_VF4_Pos 4 /*!< VADC_G VFR: VF4 Position */
\r
5427 #define VADC_G_VFR_VF4_Msk (0x01UL << VADC_G_VFR_VF4_Pos) /*!< VADC_G VFR: VF4 Mask */
\r
5428 #define VADC_G_VFR_VF5_Pos 5 /*!< VADC_G VFR: VF5 Position */
\r
5429 #define VADC_G_VFR_VF5_Msk (0x01UL << VADC_G_VFR_VF5_Pos) /*!< VADC_G VFR: VF5 Mask */
\r
5430 #define VADC_G_VFR_VF6_Pos 6 /*!< VADC_G VFR: VF6 Position */
\r
5431 #define VADC_G_VFR_VF6_Msk (0x01UL << VADC_G_VFR_VF6_Pos) /*!< VADC_G VFR: VF6 Mask */
\r
5432 #define VADC_G_VFR_VF7_Pos 7 /*!< VADC_G VFR: VF7 Position */
\r
5433 #define VADC_G_VFR_VF7_Msk (0x01UL << VADC_G_VFR_VF7_Pos) /*!< VADC_G VFR: VF7 Mask */
\r
5434 #define VADC_G_VFR_VF8_Pos 8 /*!< VADC_G VFR: VF8 Position */
\r
5435 #define VADC_G_VFR_VF8_Msk (0x01UL << VADC_G_VFR_VF8_Pos) /*!< VADC_G VFR: VF8 Mask */
\r
5436 #define VADC_G_VFR_VF9_Pos 9 /*!< VADC_G VFR: VF9 Position */
\r
5437 #define VADC_G_VFR_VF9_Msk (0x01UL << VADC_G_VFR_VF9_Pos) /*!< VADC_G VFR: VF9 Mask */
\r
5438 #define VADC_G_VFR_VF10_Pos 10 /*!< VADC_G VFR: VF10 Position */
\r
5439 #define VADC_G_VFR_VF10_Msk (0x01UL << VADC_G_VFR_VF10_Pos) /*!< VADC_G VFR: VF10 Mask */
\r
5440 #define VADC_G_VFR_VF11_Pos 11 /*!< VADC_G VFR: VF11 Position */
\r
5441 #define VADC_G_VFR_VF11_Msk (0x01UL << VADC_G_VFR_VF11_Pos) /*!< VADC_G VFR: VF11 Mask */
\r
5442 #define VADC_G_VFR_VF12_Pos 12 /*!< VADC_G VFR: VF12 Position */
\r
5443 #define VADC_G_VFR_VF12_Msk (0x01UL << VADC_G_VFR_VF12_Pos) /*!< VADC_G VFR: VF12 Mask */
\r
5444 #define VADC_G_VFR_VF13_Pos 13 /*!< VADC_G VFR: VF13 Position */
\r
5445 #define VADC_G_VFR_VF13_Msk (0x01UL << VADC_G_VFR_VF13_Pos) /*!< VADC_G VFR: VF13 Mask */
\r
5446 #define VADC_G_VFR_VF14_Pos 14 /*!< VADC_G VFR: VF14 Position */
\r
5447 #define VADC_G_VFR_VF14_Msk (0x01UL << VADC_G_VFR_VF14_Pos) /*!< VADC_G VFR: VF14 Mask */
\r
5448 #define VADC_G_VFR_VF15_Pos 15 /*!< VADC_G VFR: VF15 Position */
\r
5449 #define VADC_G_VFR_VF15_Msk (0x01UL << VADC_G_VFR_VF15_Pos) /*!< VADC_G VFR: VF15 Mask */
\r
5451 /* -------------------------------- VADC_G_CHCTR -------------------------------- */
\r
5452 #define VADC_G_CHCTR_ICLSEL_Pos 0 /*!< VADC_G CHCTR: ICLSEL Position */
\r
5453 #define VADC_G_CHCTR_ICLSEL_Msk (0x03UL << VADC_G_CHCTR_ICLSEL_Pos) /*!< VADC_G CHCTR: ICLSEL Mask */
\r
5454 #define VADC_G_CHCTR_BNDSELL_Pos 4 /*!< VADC_G CHCTR: BNDSELL Position */
\r
5455 #define VADC_G_CHCTR_BNDSELL_Msk (0x03UL << VADC_G_CHCTR_BNDSELL_Pos) /*!< VADC_G CHCTR: BNDSELL Mask */
\r
5456 #define VADC_G_CHCTR_BNDSELU_Pos 6 /*!< VADC_G CHCTR: BNDSELU Position */
\r
5457 #define VADC_G_CHCTR_BNDSELU_Msk (0x03UL << VADC_G_CHCTR_BNDSELU_Pos) /*!< VADC_G CHCTR: BNDSELU Mask */
\r
5458 #define VADC_G_CHCTR_CHEVMODE_Pos 8 /*!< VADC_G CHCTR: CHEVMODE Position */
\r
5459 #define VADC_G_CHCTR_CHEVMODE_Msk (0x03UL << VADC_G_CHCTR_CHEVMODE_Pos) /*!< VADC_G CHCTR: CHEVMODE Mask */
\r
5460 #define VADC_G_CHCTR_SYNC_Pos 10 /*!< VADC_G CHCTR: SYNC Position */
\r
5461 #define VADC_G_CHCTR_SYNC_Msk (0x01UL << VADC_G_CHCTR_SYNC_Pos) /*!< VADC_G CHCTR: SYNC Mask */
\r
5462 #define VADC_G_CHCTR_REFSEL_Pos 11 /*!< VADC_G CHCTR: REFSEL Position */
\r
5463 #define VADC_G_CHCTR_REFSEL_Msk (0x01UL << VADC_G_CHCTR_REFSEL_Pos) /*!< VADC_G CHCTR: REFSEL Mask */
\r
5464 #define VADC_G_CHCTR_BNDSELX_Pos 12 /*!< VADC_G CHCTR: BNDSELX Position */
\r
5465 #define VADC_G_CHCTR_BNDSELX_Msk (0x0fUL << VADC_G_CHCTR_BNDSELX_Pos) /*!< VADC_G CHCTR: BNDSELX Mask */
\r
5466 #define VADC_G_CHCTR_RESREG_Pos 16 /*!< VADC_G CHCTR: RESREG Position */
\r
5467 #define VADC_G_CHCTR_RESREG_Msk (0x0fUL << VADC_G_CHCTR_RESREG_Pos) /*!< VADC_G CHCTR: RESREG Mask */
\r
5468 #define VADC_G_CHCTR_RESTBS_Pos 20 /*!< VADC_G CHCTR: RESTBS Position */
\r
5469 #define VADC_G_CHCTR_RESTBS_Msk (0x01UL << VADC_G_CHCTR_RESTBS_Pos) /*!< VADC_G CHCTR: RESTBS Mask */
\r
5470 #define VADC_G_CHCTR_RESPOS_Pos 21 /*!< VADC_G CHCTR: RESPOS Position */
\r
5471 #define VADC_G_CHCTR_RESPOS_Msk (0x01UL << VADC_G_CHCTR_RESPOS_Pos) /*!< VADC_G CHCTR: RESPOS Mask */
\r
5472 #define VADC_G_CHCTR_BWDCH_Pos 28 /*!< VADC_G CHCTR: BWDCH Position */
\r
5473 #define VADC_G_CHCTR_BWDCH_Msk (0x03UL << VADC_G_CHCTR_BWDCH_Pos) /*!< VADC_G CHCTR: BWDCH Mask */
\r
5474 #define VADC_G_CHCTR_BWDEN_Pos 30 /*!< VADC_G CHCTR: BWDEN Position */
\r
5475 #define VADC_G_CHCTR_BWDEN_Msk (0x01UL << VADC_G_CHCTR_BWDEN_Pos) /*!< VADC_G CHCTR: BWDEN Mask */
\r
5477 /* --------------------------------- VADC_G_RCR --------------------------------- */
\r
5478 #define VADC_G_RCR_DRCTR_Pos 16 /*!< VADC_G RCR: DRCTR Position */
\r
5479 #define VADC_G_RCR_DRCTR_Msk (0x0fUL << VADC_G_RCR_DRCTR_Pos) /*!< VADC_G RCR: DRCTR Mask */
\r
5480 #define VADC_G_RCR_DMM_Pos 20 /*!< VADC_G RCR: DMM Position */
\r
5481 #define VADC_G_RCR_DMM_Msk (0x03UL << VADC_G_RCR_DMM_Pos) /*!< VADC_G RCR: DMM Mask */
\r
5482 #define VADC_G_RCR_WFR_Pos 24 /*!< VADC_G RCR: WFR Position */
\r
5483 #define VADC_G_RCR_WFR_Msk (0x01UL << VADC_G_RCR_WFR_Pos) /*!< VADC_G RCR: WFR Mask */
\r
5484 #define VADC_G_RCR_FEN_Pos 25 /*!< VADC_G RCR: FEN Position */
\r
5485 #define VADC_G_RCR_FEN_Msk (0x03UL << VADC_G_RCR_FEN_Pos) /*!< VADC_G RCR: FEN Mask */
\r
5486 #define VADC_G_RCR_SRGEN_Pos 31 /*!< VADC_G RCR: SRGEN Position */
\r
5487 #define VADC_G_RCR_SRGEN_Msk (0x01UL << VADC_G_RCR_SRGEN_Pos) /*!< VADC_G RCR: SRGEN Mask */
\r
5489 /* --------------------------------- VADC_G_RES --------------------------------- */
\r
5490 #define VADC_G_RES_RESULT_Pos 0 /*!< VADC_G RES: RESULT Position */
\r
5491 #define VADC_G_RES_RESULT_Msk (0x0000ffffUL << VADC_G_RES_RESULT_Pos) /*!< VADC_G RES: RESULT Mask */
\r
5492 #define VADC_G_RES_DRC_Pos 16 /*!< VADC_G RES: DRC Position */
\r
5493 #define VADC_G_RES_DRC_Msk (0x0fUL << VADC_G_RES_DRC_Pos) /*!< VADC_G RES: DRC Mask */
\r
5494 #define VADC_G_RES_CHNR_Pos 20 /*!< VADC_G RES: CHNR Position */
\r
5495 #define VADC_G_RES_CHNR_Msk (0x1fUL << VADC_G_RES_CHNR_Pos) /*!< VADC_G RES: CHNR Mask */
\r
5496 #define VADC_G_RES_EMUX_Pos 25 /*!< VADC_G RES: EMUX Position */
\r
5497 #define VADC_G_RES_EMUX_Msk (0x07UL << VADC_G_RES_EMUX_Pos) /*!< VADC_G RES: EMUX Mask */
\r
5498 #define VADC_G_RES_CRS_Pos 28 /*!< VADC_G RES: CRS Position */
\r
5499 #define VADC_G_RES_CRS_Msk (0x03UL << VADC_G_RES_CRS_Pos) /*!< VADC_G RES: CRS Mask */
\r
5500 #define VADC_G_RES_FCR_Pos 30 /*!< VADC_G RES: FCR Position */
\r
5501 #define VADC_G_RES_FCR_Msk (0x01UL << VADC_G_RES_FCR_Pos) /*!< VADC_G RES: FCR Mask */
\r
5502 #define VADC_G_RES_VF_Pos 31 /*!< VADC_G RES: VF Position */
\r
5503 #define VADC_G_RES_VF_Msk (0x01UL << VADC_G_RES_VF_Pos) /*!< VADC_G RES: VF Mask */
\r
5505 /* --------------------------------- VADC_G_RESD -------------------------------- */
\r
5506 #define VADC_G_RESD_RESULT_Pos 0 /*!< VADC_G RESD: RESULT Position */
\r
5507 #define VADC_G_RESD_RESULT_Msk (0x0000ffffUL << VADC_G_RESD_RESULT_Pos) /*!< VADC_G RESD: RESULT Mask */
\r
5508 #define VADC_G_RESD_DRC_Pos 16 /*!< VADC_G RESD: DRC Position */
\r
5509 #define VADC_G_RESD_DRC_Msk (0x0fUL << VADC_G_RESD_DRC_Pos) /*!< VADC_G RESD: DRC Mask */
\r
5510 #define VADC_G_RESD_CHNR_Pos 20 /*!< VADC_G RESD: CHNR Position */
\r
5511 #define VADC_G_RESD_CHNR_Msk (0x1fUL << VADC_G_RESD_CHNR_Pos) /*!< VADC_G RESD: CHNR Mask */
\r
5512 #define VADC_G_RESD_EMUX_Pos 25 /*!< VADC_G RESD: EMUX Position */
\r
5513 #define VADC_G_RESD_EMUX_Msk (0x07UL << VADC_G_RESD_EMUX_Pos) /*!< VADC_G RESD: EMUX Mask */
\r
5514 #define VADC_G_RESD_CRS_Pos 28 /*!< VADC_G RESD: CRS Position */
\r
5515 #define VADC_G_RESD_CRS_Msk (0x03UL << VADC_G_RESD_CRS_Pos) /*!< VADC_G RESD: CRS Mask */
\r
5516 #define VADC_G_RESD_FCR_Pos 30 /*!< VADC_G RESD: FCR Position */
\r
5517 #define VADC_G_RESD_FCR_Msk (0x01UL << VADC_G_RESD_FCR_Pos) /*!< VADC_G RESD: FCR Mask */
\r
5518 #define VADC_G_RESD_VF_Pos 31 /*!< VADC_G RESD: VF Position */
\r
5519 #define VADC_G_RESD_VF_Msk (0x01UL << VADC_G_RESD_VF_Pos) /*!< VADC_G RESD: VF Mask */
\r
5522 /* ================================================================================ */
\r
5523 /* ================ Group 'SHS' Position & Mask ================ */
\r
5524 /* ================================================================================ */
\r
5527 /* ----------------------------------- SHS_ID ----------------------------------- */
\r
5528 #define SHS_ID_MOD_REV_Pos 0 /*!< SHS ID: MOD_REV Position */
\r
5529 #define SHS_ID_MOD_REV_Msk (0x000000ffUL << SHS_ID_MOD_REV_Pos) /*!< SHS ID: MOD_REV Mask */
\r
5530 #define SHS_ID_MOD_TYPE_Pos 8 /*!< SHS ID: MOD_TYPE Position */
\r
5531 #define SHS_ID_MOD_TYPE_Msk (0x000000ffUL << SHS_ID_MOD_TYPE_Pos) /*!< SHS ID: MOD_TYPE Mask */
\r
5532 #define SHS_ID_MOD_NUMBER_Pos 16 /*!< SHS ID: MOD_NUMBER Position */
\r
5533 #define SHS_ID_MOD_NUMBER_Msk (0x0000ffffUL << SHS_ID_MOD_NUMBER_Pos) /*!< SHS ID: MOD_NUMBER Mask */
\r
5535 /* --------------------------------- SHS_SHSCFG --------------------------------- */
\r
5536 #define SHS_SHSCFG_DIVS_Pos 0 /*!< SHS SHSCFG: DIVS Position */
\r
5537 #define SHS_SHSCFG_DIVS_Msk (0x0fUL << SHS_SHSCFG_DIVS_Pos) /*!< SHS SHSCFG: DIVS Mask */
\r
5538 #define SHS_SHSCFG_AREF_Pos 10 /*!< SHS SHSCFG: AREF Position */
\r
5539 #define SHS_SHSCFG_AREF_Msk (0x03UL << SHS_SHSCFG_AREF_Pos) /*!< SHS SHSCFG: AREF Mask */
\r
5540 #define SHS_SHSCFG_ANOFF_Pos 12 /*!< SHS SHSCFG: ANOFF Position */
\r
5541 #define SHS_SHSCFG_ANOFF_Msk (0x01UL << SHS_SHSCFG_ANOFF_Pos) /*!< SHS SHSCFG: ANOFF Mask */
\r
5542 #define SHS_SHSCFG_ANRDY_Pos 14 /*!< SHS SHSCFG: ANRDY Position */
\r
5543 #define SHS_SHSCFG_ANRDY_Msk (0x01UL << SHS_SHSCFG_ANRDY_Pos) /*!< SHS SHSCFG: ANRDY Mask */
\r
5544 #define SHS_SHSCFG_SCWC_Pos 15 /*!< SHS SHSCFG: SCWC Position */
\r
5545 #define SHS_SHSCFG_SCWC_Msk (0x01UL << SHS_SHSCFG_SCWC_Pos) /*!< SHS SHSCFG: SCWC Mask */
\r
5546 #define SHS_SHSCFG_SP0_Pos 16 /*!< SHS SHSCFG: SP0 Position */
\r
5547 #define SHS_SHSCFG_SP0_Msk (0x01UL << SHS_SHSCFG_SP0_Pos) /*!< SHS SHSCFG: SP0 Mask */
\r
5548 #define SHS_SHSCFG_SP1_Pos 17 /*!< SHS SHSCFG: SP1 Position */
\r
5549 #define SHS_SHSCFG_SP1_Msk (0x01UL << SHS_SHSCFG_SP1_Pos) /*!< SHS SHSCFG: SP1 Mask */
\r
5550 #define SHS_SHSCFG_TC_Pos 24 /*!< SHS SHSCFG: TC Position */
\r
5551 #define SHS_SHSCFG_TC_Msk (0x0fUL << SHS_SHSCFG_TC_Pos) /*!< SHS SHSCFG: TC Mask */
\r
5552 #define SHS_SHSCFG_STATE_Pos 28 /*!< SHS SHSCFG: STATE Position */
\r
5553 #define SHS_SHSCFG_STATE_Msk (0x0fUL << SHS_SHSCFG_STATE_Pos) /*!< SHS SHSCFG: STATE Mask */
\r
5555 /* --------------------------------- SHS_STEPCFG -------------------------------- */
\r
5556 #define SHS_STEPCFG_KSEL0_Pos 0 /*!< SHS STEPCFG: KSEL0 Position */
\r
5557 #define SHS_STEPCFG_KSEL0_Msk (0x07UL << SHS_STEPCFG_KSEL0_Pos) /*!< SHS STEPCFG: KSEL0 Mask */
\r
5558 #define SHS_STEPCFG_SEN0_Pos 3 /*!< SHS STEPCFG: SEN0 Position */
\r
5559 #define SHS_STEPCFG_SEN0_Msk (0x01UL << SHS_STEPCFG_SEN0_Pos) /*!< SHS STEPCFG: SEN0 Mask */
\r
5560 #define SHS_STEPCFG_KSEL1_Pos 4 /*!< SHS STEPCFG: KSEL1 Position */
\r
5561 #define SHS_STEPCFG_KSEL1_Msk (0x07UL << SHS_STEPCFG_KSEL1_Pos) /*!< SHS STEPCFG: KSEL1 Mask */
\r
5562 #define SHS_STEPCFG_SEN1_Pos 7 /*!< SHS STEPCFG: SEN1 Position */
\r
5563 #define SHS_STEPCFG_SEN1_Msk (0x01UL << SHS_STEPCFG_SEN1_Pos) /*!< SHS STEPCFG: SEN1 Mask */
\r
5564 #define SHS_STEPCFG_KSEL2_Pos 8 /*!< SHS STEPCFG: KSEL2 Position */
\r
5565 #define SHS_STEPCFG_KSEL2_Msk (0x07UL << SHS_STEPCFG_KSEL2_Pos) /*!< SHS STEPCFG: KSEL2 Mask */
\r
5566 #define SHS_STEPCFG_SEN2_Pos 11 /*!< SHS STEPCFG: SEN2 Position */
\r
5567 #define SHS_STEPCFG_SEN2_Msk (0x01UL << SHS_STEPCFG_SEN2_Pos) /*!< SHS STEPCFG: SEN2 Mask */
\r
5568 #define SHS_STEPCFG_KSEL3_Pos 12 /*!< SHS STEPCFG: KSEL3 Position */
\r
5569 #define SHS_STEPCFG_KSEL3_Msk (0x07UL << SHS_STEPCFG_KSEL3_Pos) /*!< SHS STEPCFG: KSEL3 Mask */
\r
5570 #define SHS_STEPCFG_SEN3_Pos 15 /*!< SHS STEPCFG: SEN3 Position */
\r
5571 #define SHS_STEPCFG_SEN3_Msk (0x01UL << SHS_STEPCFG_SEN3_Pos) /*!< SHS STEPCFG: SEN3 Mask */
\r
5572 #define SHS_STEPCFG_KSEL4_Pos 16 /*!< SHS STEPCFG: KSEL4 Position */
\r
5573 #define SHS_STEPCFG_KSEL4_Msk (0x07UL << SHS_STEPCFG_KSEL4_Pos) /*!< SHS STEPCFG: KSEL4 Mask */
\r
5574 #define SHS_STEPCFG_SEN4_Pos 19 /*!< SHS STEPCFG: SEN4 Position */
\r
5575 #define SHS_STEPCFG_SEN4_Msk (0x01UL << SHS_STEPCFG_SEN4_Pos) /*!< SHS STEPCFG: SEN4 Mask */
\r
5576 #define SHS_STEPCFG_KSEL5_Pos 20 /*!< SHS STEPCFG: KSEL5 Position */
\r
5577 #define SHS_STEPCFG_KSEL5_Msk (0x07UL << SHS_STEPCFG_KSEL5_Pos) /*!< SHS STEPCFG: KSEL5 Mask */
\r
5578 #define SHS_STEPCFG_SEN5_Pos 23 /*!< SHS STEPCFG: SEN5 Position */
\r
5579 #define SHS_STEPCFG_SEN5_Msk (0x01UL << SHS_STEPCFG_SEN5_Pos) /*!< SHS STEPCFG: SEN5 Mask */
\r
5580 #define SHS_STEPCFG_KSEL6_Pos 24 /*!< SHS STEPCFG: KSEL6 Position */
\r
5581 #define SHS_STEPCFG_KSEL6_Msk (0x07UL << SHS_STEPCFG_KSEL6_Pos) /*!< SHS STEPCFG: KSEL6 Mask */
\r
5582 #define SHS_STEPCFG_SEN6_Pos 27 /*!< SHS STEPCFG: SEN6 Position */
\r
5583 #define SHS_STEPCFG_SEN6_Msk (0x01UL << SHS_STEPCFG_SEN6_Pos) /*!< SHS STEPCFG: SEN6 Mask */
\r
5584 #define SHS_STEPCFG_KSEL7_Pos 28 /*!< SHS STEPCFG: KSEL7 Position */
\r
5585 #define SHS_STEPCFG_KSEL7_Msk (0x07UL << SHS_STEPCFG_KSEL7_Pos) /*!< SHS STEPCFG: KSEL7 Mask */
\r
5586 #define SHS_STEPCFG_SEN7_Pos 31 /*!< SHS STEPCFG: SEN7 Position */
\r
5587 #define SHS_STEPCFG_SEN7_Msk (0x01UL << SHS_STEPCFG_SEN7_Pos) /*!< SHS STEPCFG: SEN7 Mask */
\r
5589 /* ---------------------------------- SHS_LOOP ---------------------------------- */
\r
5590 #define SHS_LOOP_LPCH0_Pos 0 /*!< SHS LOOP: LPCH0 Position */
\r
5591 #define SHS_LOOP_LPCH0_Msk (0x1fUL << SHS_LOOP_LPCH0_Pos) /*!< SHS LOOP: LPCH0 Mask */
\r
5592 #define SHS_LOOP_LPSH0_Pos 8 /*!< SHS LOOP: LPSH0 Position */
\r
5593 #define SHS_LOOP_LPSH0_Msk (0x01UL << SHS_LOOP_LPSH0_Pos) /*!< SHS LOOP: LPSH0 Mask */
\r
5594 #define SHS_LOOP_LPEN0_Pos 15 /*!< SHS LOOP: LPEN0 Position */
\r
5595 #define SHS_LOOP_LPEN0_Msk (0x01UL << SHS_LOOP_LPEN0_Pos) /*!< SHS LOOP: LPEN0 Mask */
\r
5596 #define SHS_LOOP_LPCH1_Pos 16 /*!< SHS LOOP: LPCH1 Position */
\r
5597 #define SHS_LOOP_LPCH1_Msk (0x1fUL << SHS_LOOP_LPCH1_Pos) /*!< SHS LOOP: LPCH1 Mask */
\r
5598 #define SHS_LOOP_LPSH1_Pos 24 /*!< SHS LOOP: LPSH1 Position */
\r
5599 #define SHS_LOOP_LPSH1_Msk (0x01UL << SHS_LOOP_LPSH1_Pos) /*!< SHS LOOP: LPSH1 Mask */
\r
5600 #define SHS_LOOP_LPEN1_Pos 31 /*!< SHS LOOP: LPEN1 Position */
\r
5601 #define SHS_LOOP_LPEN1_Msk (0x01UL << SHS_LOOP_LPEN1_Pos) /*!< SHS LOOP: LPEN1 Mask */
\r
5603 /* --------------------------------- SHS_TIMCFG0 -------------------------------- */
\r
5604 #define SHS_TIMCFG0_AT_Pos 0 /*!< SHS TIMCFG0: AT Position */
\r
5605 #define SHS_TIMCFG0_AT_Msk (0x01UL << SHS_TIMCFG0_AT_Pos) /*!< SHS TIMCFG0: AT Mask */
\r
5606 #define SHS_TIMCFG0_FCRT_Pos 4 /*!< SHS TIMCFG0: FCRT Position */
\r
5607 #define SHS_TIMCFG0_FCRT_Msk (0x0fUL << SHS_TIMCFG0_FCRT_Pos) /*!< SHS TIMCFG0: FCRT Mask */
\r
5608 #define SHS_TIMCFG0_SST_Pos 8 /*!< SHS TIMCFG0: SST Position */
\r
5609 #define SHS_TIMCFG0_SST_Msk (0x3fUL << SHS_TIMCFG0_SST_Pos) /*!< SHS TIMCFG0: SST Mask */
\r
5610 #define SHS_TIMCFG0_TGEN_Pos 16 /*!< SHS TIMCFG0: TGEN Position */
\r
5611 #define SHS_TIMCFG0_TGEN_Msk (0x00003fffUL << SHS_TIMCFG0_TGEN_Pos) /*!< SHS TIMCFG0: TGEN Mask */
\r
5613 /* --------------------------------- SHS_TIMCFG1 -------------------------------- */
\r
5614 #define SHS_TIMCFG1_AT_Pos 0 /*!< SHS TIMCFG1: AT Position */
\r
5615 #define SHS_TIMCFG1_AT_Msk (0x01UL << SHS_TIMCFG1_AT_Pos) /*!< SHS TIMCFG1: AT Mask */
\r
5616 #define SHS_TIMCFG1_FCRT_Pos 4 /*!< SHS TIMCFG1: FCRT Position */
\r
5617 #define SHS_TIMCFG1_FCRT_Msk (0x0fUL << SHS_TIMCFG1_FCRT_Pos) /*!< SHS TIMCFG1: FCRT Mask */
\r
5618 #define SHS_TIMCFG1_SST_Pos 8 /*!< SHS TIMCFG1: SST Position */
\r
5619 #define SHS_TIMCFG1_SST_Msk (0x3fUL << SHS_TIMCFG1_SST_Pos) /*!< SHS TIMCFG1: SST Mask */
\r
5620 #define SHS_TIMCFG1_TGEN_Pos 16 /*!< SHS TIMCFG1: TGEN Position */
\r
5621 #define SHS_TIMCFG1_TGEN_Msk (0x00003fffUL << SHS_TIMCFG1_TGEN_Pos) /*!< SHS TIMCFG1: TGEN Mask */
\r
5623 /* --------------------------------- SHS_CALCTR --------------------------------- */
\r
5624 #define SHS_CALCTR_CALORD_Pos 0 /*!< SHS CALCTR: CALORD Position */
\r
5625 #define SHS_CALCTR_CALORD_Msk (0x01UL << SHS_CALCTR_CALORD_Pos) /*!< SHS CALCTR: CALORD Mask */
\r
5626 #define SHS_CALCTR_CALGNSTC_Pos 8 /*!< SHS CALCTR: CALGNSTC Position */
\r
5627 #define SHS_CALCTR_CALGNSTC_Msk (0x3fUL << SHS_CALCTR_CALGNSTC_Pos) /*!< SHS CALCTR: CALGNSTC Mask */
\r
5628 #define SHS_CALCTR_SUCALVAL_Pos 16 /*!< SHS CALCTR: SUCALVAL Position */
\r
5629 #define SHS_CALCTR_SUCALVAL_Msk (0x7fUL << SHS_CALCTR_SUCALVAL_Pos) /*!< SHS CALCTR: SUCALVAL Mask */
\r
5630 #define SHS_CALCTR_CALMAX_Pos 24 /*!< SHS CALCTR: CALMAX Position */
\r
5631 #define SHS_CALCTR_CALMAX_Msk (0x3fUL << SHS_CALCTR_CALMAX_Pos) /*!< SHS CALCTR: CALMAX Mask */
\r
5632 #define SHS_CALCTR_SUCAL_Pos 31 /*!< SHS CALCTR: SUCAL Position */
\r
5633 #define SHS_CALCTR_SUCAL_Msk (0x01UL << SHS_CALCTR_SUCAL_Pos) /*!< SHS CALCTR: SUCAL Mask */
\r
5635 /* --------------------------------- SHS_CALGC0 --------------------------------- */
\r
5636 #define SHS_CALGC0_CALGNVALS_Pos 0 /*!< SHS CALGC0: CALGNVALS Position */
\r
5637 #define SHS_CALGC0_CALGNVALS_Msk (0x00003fffUL << SHS_CALGC0_CALGNVALS_Pos) /*!< SHS CALGC0: CALGNVALS Mask */
\r
5638 #define SHS_CALGC0_GNSWC_Pos 15 /*!< SHS CALGC0: GNSWC Position */
\r
5639 #define SHS_CALGC0_GNSWC_Msk (0x01UL << SHS_CALGC0_GNSWC_Pos) /*!< SHS CALGC0: GNSWC Mask */
\r
5640 #define SHS_CALGC0_CALGNVALA_Pos 16 /*!< SHS CALGC0: CALGNVALA Position */
\r
5641 #define SHS_CALGC0_CALGNVALA_Msk (0x00003fffUL << SHS_CALGC0_CALGNVALA_Pos) /*!< SHS CALGC0: CALGNVALA Mask */
\r
5642 #define SHS_CALGC0_GNAWC_Pos 31 /*!< SHS CALGC0: GNAWC Position */
\r
5643 #define SHS_CALGC0_GNAWC_Msk (0x01UL << SHS_CALGC0_GNAWC_Pos) /*!< SHS CALGC0: GNAWC Mask */
\r
5645 /* --------------------------------- SHS_CALGC1 --------------------------------- */
\r
5646 #define SHS_CALGC1_CALGNVALS_Pos 0 /*!< SHS CALGC1: CALGNVALS Position */
\r
5647 #define SHS_CALGC1_CALGNVALS_Msk (0x00003fffUL << SHS_CALGC1_CALGNVALS_Pos) /*!< SHS CALGC1: CALGNVALS Mask */
\r
5648 #define SHS_CALGC1_GNSWC_Pos 15 /*!< SHS CALGC1: GNSWC Position */
\r
5649 #define SHS_CALGC1_GNSWC_Msk (0x01UL << SHS_CALGC1_GNSWC_Pos) /*!< SHS CALGC1: GNSWC Mask */
\r
5650 #define SHS_CALGC1_CALGNVALA_Pos 16 /*!< SHS CALGC1: CALGNVALA Position */
\r
5651 #define SHS_CALGC1_CALGNVALA_Msk (0x00003fffUL << SHS_CALGC1_CALGNVALA_Pos) /*!< SHS CALGC1: CALGNVALA Mask */
\r
5652 #define SHS_CALGC1_GNAWC_Pos 31 /*!< SHS CALGC1: GNAWC Position */
\r
5653 #define SHS_CALGC1_GNAWC_Msk (0x01UL << SHS_CALGC1_GNAWC_Pos) /*!< SHS CALGC1: GNAWC Mask */
\r
5655 /* --------------------------------- SHS_GNCTR00 -------------------------------- */
\r
5656 #define SHS_GNCTR00_GAIN0_Pos 0 /*!< SHS GNCTR00: GAIN0 Position */
\r
5657 #define SHS_GNCTR00_GAIN0_Msk (0x0fUL << SHS_GNCTR00_GAIN0_Pos) /*!< SHS GNCTR00: GAIN0 Mask */
\r
5658 #define SHS_GNCTR00_GAIN1_Pos 4 /*!< SHS GNCTR00: GAIN1 Position */
\r
5659 #define SHS_GNCTR00_GAIN1_Msk (0x0fUL << SHS_GNCTR00_GAIN1_Pos) /*!< SHS GNCTR00: GAIN1 Mask */
\r
5660 #define SHS_GNCTR00_GAIN2_Pos 8 /*!< SHS GNCTR00: GAIN2 Position */
\r
5661 #define SHS_GNCTR00_GAIN2_Msk (0x0fUL << SHS_GNCTR00_GAIN2_Pos) /*!< SHS GNCTR00: GAIN2 Mask */
\r
5662 #define SHS_GNCTR00_GAIN3_Pos 12 /*!< SHS GNCTR00: GAIN3 Position */
\r
5663 #define SHS_GNCTR00_GAIN3_Msk (0x0fUL << SHS_GNCTR00_GAIN3_Pos) /*!< SHS GNCTR00: GAIN3 Mask */
\r
5664 #define SHS_GNCTR00_GAIN4_Pos 16 /*!< SHS GNCTR00: GAIN4 Position */
\r
5665 #define SHS_GNCTR00_GAIN4_Msk (0x0fUL << SHS_GNCTR00_GAIN4_Pos) /*!< SHS GNCTR00: GAIN4 Mask */
\r
5666 #define SHS_GNCTR00_GAIN5_Pos 20 /*!< SHS GNCTR00: GAIN5 Position */
\r
5667 #define SHS_GNCTR00_GAIN5_Msk (0x0fUL << SHS_GNCTR00_GAIN5_Pos) /*!< SHS GNCTR00: GAIN5 Mask */
\r
5668 #define SHS_GNCTR00_GAIN6_Pos 24 /*!< SHS GNCTR00: GAIN6 Position */
\r
5669 #define SHS_GNCTR00_GAIN6_Msk (0x0fUL << SHS_GNCTR00_GAIN6_Pos) /*!< SHS GNCTR00: GAIN6 Mask */
\r
5670 #define SHS_GNCTR00_GAIN7_Pos 28 /*!< SHS GNCTR00: GAIN7 Position */
\r
5671 #define SHS_GNCTR00_GAIN7_Msk (0x0fUL << SHS_GNCTR00_GAIN7_Pos) /*!< SHS GNCTR00: GAIN7 Mask */
\r
5673 /* --------------------------------- SHS_GNCTR10 -------------------------------- */
\r
5674 #define SHS_GNCTR10_GAIN0_Pos 0 /*!< SHS GNCTR10: GAIN0 Position */
\r
5675 #define SHS_GNCTR10_GAIN0_Msk (0x0fUL << SHS_GNCTR10_GAIN0_Pos) /*!< SHS GNCTR10: GAIN0 Mask */
\r
5676 #define SHS_GNCTR10_GAIN1_Pos 4 /*!< SHS GNCTR10: GAIN1 Position */
\r
5677 #define SHS_GNCTR10_GAIN1_Msk (0x0fUL << SHS_GNCTR10_GAIN1_Pos) /*!< SHS GNCTR10: GAIN1 Mask */
\r
5678 #define SHS_GNCTR10_GAIN2_Pos 8 /*!< SHS GNCTR10: GAIN2 Position */
\r
5679 #define SHS_GNCTR10_GAIN2_Msk (0x0fUL << SHS_GNCTR10_GAIN2_Pos) /*!< SHS GNCTR10: GAIN2 Mask */
\r
5680 #define SHS_GNCTR10_GAIN3_Pos 12 /*!< SHS GNCTR10: GAIN3 Position */
\r
5681 #define SHS_GNCTR10_GAIN3_Msk (0x0fUL << SHS_GNCTR10_GAIN3_Pos) /*!< SHS GNCTR10: GAIN3 Mask */
\r
5682 #define SHS_GNCTR10_GAIN4_Pos 16 /*!< SHS GNCTR10: GAIN4 Position */
\r
5683 #define SHS_GNCTR10_GAIN4_Msk (0x0fUL << SHS_GNCTR10_GAIN4_Pos) /*!< SHS GNCTR10: GAIN4 Mask */
\r
5684 #define SHS_GNCTR10_GAIN5_Pos 20 /*!< SHS GNCTR10: GAIN5 Position */
\r
5685 #define SHS_GNCTR10_GAIN5_Msk (0x0fUL << SHS_GNCTR10_GAIN5_Pos) /*!< SHS GNCTR10: GAIN5 Mask */
\r
5686 #define SHS_GNCTR10_GAIN6_Pos 24 /*!< SHS GNCTR10: GAIN6 Position */
\r
5687 #define SHS_GNCTR10_GAIN6_Msk (0x0fUL << SHS_GNCTR10_GAIN6_Pos) /*!< SHS GNCTR10: GAIN6 Mask */
\r
5688 #define SHS_GNCTR10_GAIN7_Pos 28 /*!< SHS GNCTR10: GAIN7 Position */
\r
5689 #define SHS_GNCTR10_GAIN7_Msk (0x0fUL << SHS_GNCTR10_GAIN7_Pos) /*!< SHS GNCTR10: GAIN7 Mask */
\r
5692 /* ================================================================================ */
\r
5693 /* ================ Group 'BCCU' Position & Mask ================ */
\r
5694 /* ================================================================================ */
\r
5697 /* -------------------------------- BCCU_GLOBCON -------------------------------- */
\r
5698 #define BCCU_GLOBCON_TM_Pos 0 /*!< BCCU GLOBCON: TM Position */
\r
5699 #define BCCU_GLOBCON_TM_Msk (0x01UL << BCCU_GLOBCON_TM_Pos) /*!< BCCU GLOBCON: TM Mask */
\r
5700 #define BCCU_GLOBCON_TRDEL_Pos 2 /*!< BCCU GLOBCON: TRDEL Position */
\r
5701 #define BCCU_GLOBCON_TRDEL_Msk (0x03UL << BCCU_GLOBCON_TRDEL_Pos) /*!< BCCU GLOBCON: TRDEL Mask */
\r
5702 #define BCCU_GLOBCON_SUSCFG_Pos 4 /*!< BCCU GLOBCON: SUSCFG Position */
\r
5703 #define BCCU_GLOBCON_SUSCFG_Msk (0x03UL << BCCU_GLOBCON_SUSCFG_Pos) /*!< BCCU GLOBCON: SUSCFG Mask */
\r
5704 #define BCCU_GLOBCON_TRAPIS_Pos 6 /*!< BCCU GLOBCON: TRAPIS Position */
\r
5705 #define BCCU_GLOBCON_TRAPIS_Msk (0x0fUL << BCCU_GLOBCON_TRAPIS_Pos) /*!< BCCU GLOBCON: TRAPIS Mask */
\r
5706 #define BCCU_GLOBCON_TRAPED_Pos 10 /*!< BCCU GLOBCON: TRAPED Position */
\r
5707 #define BCCU_GLOBCON_TRAPED_Msk (0x01UL << BCCU_GLOBCON_TRAPED_Pos) /*!< BCCU GLOBCON: TRAPED Mask */
\r
5708 #define BCCU_GLOBCON_LTRS_Pos 12 /*!< BCCU GLOBCON: LTRS Position */
\r
5709 #define BCCU_GLOBCON_LTRS_Msk (0x0fUL << BCCU_GLOBCON_LTRS_Pos) /*!< BCCU GLOBCON: LTRS Mask */
\r
5710 #define BCCU_GLOBCON_WDMBN_Pos 16 /*!< BCCU GLOBCON: WDMBN Position */
\r
5711 #define BCCU_GLOBCON_WDMBN_Msk (0x00000fffUL << BCCU_GLOBCON_WDMBN_Pos) /*!< BCCU GLOBCON: WDMBN Mask */
\r
5713 /* -------------------------------- BCCU_GLOBCLK -------------------------------- */
\r
5714 #define BCCU_GLOBCLK_FCLK_PS_Pos 0 /*!< BCCU GLOBCLK: FCLK_PS Position */
\r
5715 #define BCCU_GLOBCLK_FCLK_PS_Msk (0x00000fffUL << BCCU_GLOBCLK_FCLK_PS_Pos) /*!< BCCU GLOBCLK: FCLK_PS Mask */
\r
5716 #define BCCU_GLOBCLK_BCS_Pos 15 /*!< BCCU GLOBCLK: BCS Position */
\r
5717 #define BCCU_GLOBCLK_BCS_Msk (0x01UL << BCCU_GLOBCLK_BCS_Pos) /*!< BCCU GLOBCLK: BCS Mask */
\r
5718 #define BCCU_GLOBCLK_DCLK_PS_Pos 16 /*!< BCCU GLOBCLK: DCLK_PS Position */
\r
5719 #define BCCU_GLOBCLK_DCLK_PS_Msk (0x00000fffUL << BCCU_GLOBCLK_DCLK_PS_Pos) /*!< BCCU GLOBCLK: DCLK_PS Mask */
\r
5721 /* ----------------------------------- BCCU_ID ---------------------------------- */
\r
5722 #define BCCU_ID_MOD_REV_Pos 0 /*!< BCCU ID: MOD_REV Position */
\r
5723 #define BCCU_ID_MOD_REV_Msk (0x000000ffUL << BCCU_ID_MOD_REV_Pos) /*!< BCCU ID: MOD_REV Mask */
\r
5724 #define BCCU_ID_MOD_TYPE0_Pos 8 /*!< BCCU ID: MOD_TYPE0 Position */
\r
5725 #define BCCU_ID_MOD_TYPE0_Msk (0x000000ffUL << BCCU_ID_MOD_TYPE0_Pos) /*!< BCCU ID: MOD_TYPE0 Mask */
\r
5726 #define BCCU_ID_MOD_NUMBER_Pos 16 /*!< BCCU ID: MOD_NUMBER Position */
\r
5727 #define BCCU_ID_MOD_NUMBER_Msk (0x0000ffffUL << BCCU_ID_MOD_NUMBER_Pos) /*!< BCCU ID: MOD_NUMBER Mask */
\r
5729 /* ---------------------------------- BCCU_CHEN --------------------------------- */
\r
5730 #define BCCU_CHEN_ECH0_Pos 0 /*!< BCCU CHEN: ECH0 Position */
\r
5731 #define BCCU_CHEN_ECH0_Msk (0x01UL << BCCU_CHEN_ECH0_Pos) /*!< BCCU CHEN: ECH0 Mask */
\r
5732 #define BCCU_CHEN_ECH1_Pos 1 /*!< BCCU CHEN: ECH1 Position */
\r
5733 #define BCCU_CHEN_ECH1_Msk (0x01UL << BCCU_CHEN_ECH1_Pos) /*!< BCCU CHEN: ECH1 Mask */
\r
5734 #define BCCU_CHEN_ECH2_Pos 2 /*!< BCCU CHEN: ECH2 Position */
\r
5735 #define BCCU_CHEN_ECH2_Msk (0x01UL << BCCU_CHEN_ECH2_Pos) /*!< BCCU CHEN: ECH2 Mask */
\r
5736 #define BCCU_CHEN_ECH3_Pos 3 /*!< BCCU CHEN: ECH3 Position */
\r
5737 #define BCCU_CHEN_ECH3_Msk (0x01UL << BCCU_CHEN_ECH3_Pos) /*!< BCCU CHEN: ECH3 Mask */
\r
5738 #define BCCU_CHEN_ECH4_Pos 4 /*!< BCCU CHEN: ECH4 Position */
\r
5739 #define BCCU_CHEN_ECH4_Msk (0x01UL << BCCU_CHEN_ECH4_Pos) /*!< BCCU CHEN: ECH4 Mask */
\r
5740 #define BCCU_CHEN_ECH5_Pos 5 /*!< BCCU CHEN: ECH5 Position */
\r
5741 #define BCCU_CHEN_ECH5_Msk (0x01UL << BCCU_CHEN_ECH5_Pos) /*!< BCCU CHEN: ECH5 Mask */
\r
5742 #define BCCU_CHEN_ECH6_Pos 6 /*!< BCCU CHEN: ECH6 Position */
\r
5743 #define BCCU_CHEN_ECH6_Msk (0x01UL << BCCU_CHEN_ECH6_Pos) /*!< BCCU CHEN: ECH6 Mask */
\r
5744 #define BCCU_CHEN_ECH7_Pos 7 /*!< BCCU CHEN: ECH7 Position */
\r
5745 #define BCCU_CHEN_ECH7_Msk (0x01UL << BCCU_CHEN_ECH7_Pos) /*!< BCCU CHEN: ECH7 Mask */
\r
5746 #define BCCU_CHEN_ECH8_Pos 8 /*!< BCCU CHEN: ECH8 Position */
\r
5747 #define BCCU_CHEN_ECH8_Msk (0x01UL << BCCU_CHEN_ECH8_Pos) /*!< BCCU CHEN: ECH8 Mask */
\r
5749 /* --------------------------------- BCCU_CHOCON -------------------------------- */
\r
5750 #define BCCU_CHOCON_CH0OP_Pos 0 /*!< BCCU CHOCON: CH0OP Position */
\r
5751 #define BCCU_CHOCON_CH0OP_Msk (0x01UL << BCCU_CHOCON_CH0OP_Pos) /*!< BCCU CHOCON: CH0OP Mask */
\r
5752 #define BCCU_CHOCON_CH1OP_Pos 1 /*!< BCCU CHOCON: CH1OP Position */
\r
5753 #define BCCU_CHOCON_CH1OP_Msk (0x01UL << BCCU_CHOCON_CH1OP_Pos) /*!< BCCU CHOCON: CH1OP Mask */
\r
5754 #define BCCU_CHOCON_CH2OP_Pos 2 /*!< BCCU CHOCON: CH2OP Position */
\r
5755 #define BCCU_CHOCON_CH2OP_Msk (0x01UL << BCCU_CHOCON_CH2OP_Pos) /*!< BCCU CHOCON: CH2OP Mask */
\r
5756 #define BCCU_CHOCON_CH3OP_Pos 3 /*!< BCCU CHOCON: CH3OP Position */
\r
5757 #define BCCU_CHOCON_CH3OP_Msk (0x01UL << BCCU_CHOCON_CH3OP_Pos) /*!< BCCU CHOCON: CH3OP Mask */
\r
5758 #define BCCU_CHOCON_CH4OP_Pos 4 /*!< BCCU CHOCON: CH4OP Position */
\r
5759 #define BCCU_CHOCON_CH4OP_Msk (0x01UL << BCCU_CHOCON_CH4OP_Pos) /*!< BCCU CHOCON: CH4OP Mask */
\r
5760 #define BCCU_CHOCON_CH5OP_Pos 5 /*!< BCCU CHOCON: CH5OP Position */
\r
5761 #define BCCU_CHOCON_CH5OP_Msk (0x01UL << BCCU_CHOCON_CH5OP_Pos) /*!< BCCU CHOCON: CH5OP Mask */
\r
5762 #define BCCU_CHOCON_CH6OP_Pos 6 /*!< BCCU CHOCON: CH6OP Position */
\r
5763 #define BCCU_CHOCON_CH6OP_Msk (0x01UL << BCCU_CHOCON_CH6OP_Pos) /*!< BCCU CHOCON: CH6OP Mask */
\r
5764 #define BCCU_CHOCON_CH7OP_Pos 7 /*!< BCCU CHOCON: CH7OP Position */
\r
5765 #define BCCU_CHOCON_CH7OP_Msk (0x01UL << BCCU_CHOCON_CH7OP_Pos) /*!< BCCU CHOCON: CH7OP Mask */
\r
5766 #define BCCU_CHOCON_CH8OP_Pos 8 /*!< BCCU CHOCON: CH8OP Position */
\r
5767 #define BCCU_CHOCON_CH8OP_Msk (0x01UL << BCCU_CHOCON_CH8OP_Pos) /*!< BCCU CHOCON: CH8OP Mask */
\r
5768 #define BCCU_CHOCON_CH0TPE_Pos 16 /*!< BCCU CHOCON: CH0TPE Position */
\r
5769 #define BCCU_CHOCON_CH0TPE_Msk (0x01UL << BCCU_CHOCON_CH0TPE_Pos) /*!< BCCU CHOCON: CH0TPE Mask */
\r
5770 #define BCCU_CHOCON_CH1TPE_Pos 17 /*!< BCCU CHOCON: CH1TPE Position */
\r
5771 #define BCCU_CHOCON_CH1TPE_Msk (0x01UL << BCCU_CHOCON_CH1TPE_Pos) /*!< BCCU CHOCON: CH1TPE Mask */
\r
5772 #define BCCU_CHOCON_CH2TPE_Pos 18 /*!< BCCU CHOCON: CH2TPE Position */
\r
5773 #define BCCU_CHOCON_CH2TPE_Msk (0x01UL << BCCU_CHOCON_CH2TPE_Pos) /*!< BCCU CHOCON: CH2TPE Mask */
\r
5774 #define BCCU_CHOCON_CH3TPE_Pos 19 /*!< BCCU CHOCON: CH3TPE Position */
\r
5775 #define BCCU_CHOCON_CH3TPE_Msk (0x01UL << BCCU_CHOCON_CH3TPE_Pos) /*!< BCCU CHOCON: CH3TPE Mask */
\r
5776 #define BCCU_CHOCON_CH4TPE_Pos 20 /*!< BCCU CHOCON: CH4TPE Position */
\r
5777 #define BCCU_CHOCON_CH4TPE_Msk (0x01UL << BCCU_CHOCON_CH4TPE_Pos) /*!< BCCU CHOCON: CH4TPE Mask */
\r
5778 #define BCCU_CHOCON_CH5TPE_Pos 21 /*!< BCCU CHOCON: CH5TPE Position */
\r
5779 #define BCCU_CHOCON_CH5TPE_Msk (0x01UL << BCCU_CHOCON_CH5TPE_Pos) /*!< BCCU CHOCON: CH5TPE Mask */
\r
5780 #define BCCU_CHOCON_CH6TPE_Pos 22 /*!< BCCU CHOCON: CH6TPE Position */
\r
5781 #define BCCU_CHOCON_CH6TPE_Msk (0x01UL << BCCU_CHOCON_CH6TPE_Pos) /*!< BCCU CHOCON: CH6TPE Mask */
\r
5782 #define BCCU_CHOCON_CH7TPE_Pos 23 /*!< BCCU CHOCON: CH7TPE Position */
\r
5783 #define BCCU_CHOCON_CH7TPE_Msk (0x01UL << BCCU_CHOCON_CH7TPE_Pos) /*!< BCCU CHOCON: CH7TPE Mask */
\r
5784 #define BCCU_CHOCON_CH8TPE_Pos 24 /*!< BCCU CHOCON: CH8TPE Position */
\r
5785 #define BCCU_CHOCON_CH8TPE_Msk (0x01UL << BCCU_CHOCON_CH8TPE_Pos) /*!< BCCU CHOCON: CH8TPE Mask */
\r
5787 /* --------------------------------- BCCU_CHTRIG -------------------------------- */
\r
5788 #define BCCU_CHTRIG_ET0_Pos 0 /*!< BCCU CHTRIG: ET0 Position */
\r
5789 #define BCCU_CHTRIG_ET0_Msk (0x01UL << BCCU_CHTRIG_ET0_Pos) /*!< BCCU CHTRIG: ET0 Mask */
\r
5790 #define BCCU_CHTRIG_ET1_Pos 1 /*!< BCCU CHTRIG: ET1 Position */
\r
5791 #define BCCU_CHTRIG_ET1_Msk (0x01UL << BCCU_CHTRIG_ET1_Pos) /*!< BCCU CHTRIG: ET1 Mask */
\r
5792 #define BCCU_CHTRIG_ET2_Pos 2 /*!< BCCU CHTRIG: ET2 Position */
\r
5793 #define BCCU_CHTRIG_ET2_Msk (0x01UL << BCCU_CHTRIG_ET2_Pos) /*!< BCCU CHTRIG: ET2 Mask */
\r
5794 #define BCCU_CHTRIG_ET3_Pos 3 /*!< BCCU CHTRIG: ET3 Position */
\r
5795 #define BCCU_CHTRIG_ET3_Msk (0x01UL << BCCU_CHTRIG_ET3_Pos) /*!< BCCU CHTRIG: ET3 Mask */
\r
5796 #define BCCU_CHTRIG_ET4_Pos 4 /*!< BCCU CHTRIG: ET4 Position */
\r
5797 #define BCCU_CHTRIG_ET4_Msk (0x01UL << BCCU_CHTRIG_ET4_Pos) /*!< BCCU CHTRIG: ET4 Mask */
\r
5798 #define BCCU_CHTRIG_ET5_Pos 5 /*!< BCCU CHTRIG: ET5 Position */
\r
5799 #define BCCU_CHTRIG_ET5_Msk (0x01UL << BCCU_CHTRIG_ET5_Pos) /*!< BCCU CHTRIG: ET5 Mask */
\r
5800 #define BCCU_CHTRIG_ET6_Pos 6 /*!< BCCU CHTRIG: ET6 Position */
\r
5801 #define BCCU_CHTRIG_ET6_Msk (0x01UL << BCCU_CHTRIG_ET6_Pos) /*!< BCCU CHTRIG: ET6 Mask */
\r
5802 #define BCCU_CHTRIG_ET7_Pos 7 /*!< BCCU CHTRIG: ET7 Position */
\r
5803 #define BCCU_CHTRIG_ET7_Msk (0x01UL << BCCU_CHTRIG_ET7_Pos) /*!< BCCU CHTRIG: ET7 Mask */
\r
5804 #define BCCU_CHTRIG_ET8_Pos 8 /*!< BCCU CHTRIG: ET8 Position */
\r
5805 #define BCCU_CHTRIG_ET8_Msk (0x01UL << BCCU_CHTRIG_ET8_Pos) /*!< BCCU CHTRIG: ET8 Mask */
\r
5806 #define BCCU_CHTRIG_TOS0_Pos 16 /*!< BCCU CHTRIG: TOS0 Position */
\r
5807 #define BCCU_CHTRIG_TOS0_Msk (0x01UL << BCCU_CHTRIG_TOS0_Pos) /*!< BCCU CHTRIG: TOS0 Mask */
\r
5808 #define BCCU_CHTRIG_TOS1_Pos 17 /*!< BCCU CHTRIG: TOS1 Position */
\r
5809 #define BCCU_CHTRIG_TOS1_Msk (0x01UL << BCCU_CHTRIG_TOS1_Pos) /*!< BCCU CHTRIG: TOS1 Mask */
\r
5810 #define BCCU_CHTRIG_TOS2_Pos 18 /*!< BCCU CHTRIG: TOS2 Position */
\r
5811 #define BCCU_CHTRIG_TOS2_Msk (0x01UL << BCCU_CHTRIG_TOS2_Pos) /*!< BCCU CHTRIG: TOS2 Mask */
\r
5812 #define BCCU_CHTRIG_TOS3_Pos 19 /*!< BCCU CHTRIG: TOS3 Position */
\r
5813 #define BCCU_CHTRIG_TOS3_Msk (0x01UL << BCCU_CHTRIG_TOS3_Pos) /*!< BCCU CHTRIG: TOS3 Mask */
\r
5814 #define BCCU_CHTRIG_TOS4_Pos 20 /*!< BCCU CHTRIG: TOS4 Position */
\r
5815 #define BCCU_CHTRIG_TOS4_Msk (0x01UL << BCCU_CHTRIG_TOS4_Pos) /*!< BCCU CHTRIG: TOS4 Mask */
\r
5816 #define BCCU_CHTRIG_TOS5_Pos 21 /*!< BCCU CHTRIG: TOS5 Position */
\r
5817 #define BCCU_CHTRIG_TOS5_Msk (0x01UL << BCCU_CHTRIG_TOS5_Pos) /*!< BCCU CHTRIG: TOS5 Mask */
\r
5818 #define BCCU_CHTRIG_TOS6_Pos 22 /*!< BCCU CHTRIG: TOS6 Position */
\r
5819 #define BCCU_CHTRIG_TOS6_Msk (0x01UL << BCCU_CHTRIG_TOS6_Pos) /*!< BCCU CHTRIG: TOS6 Mask */
\r
5820 #define BCCU_CHTRIG_TOS7_Pos 23 /*!< BCCU CHTRIG: TOS7 Position */
\r
5821 #define BCCU_CHTRIG_TOS7_Msk (0x01UL << BCCU_CHTRIG_TOS7_Pos) /*!< BCCU CHTRIG: TOS7 Mask */
\r
5822 #define BCCU_CHTRIG_TOS8_Pos 24 /*!< BCCU CHTRIG: TOS8 Position */
\r
5823 #define BCCU_CHTRIG_TOS8_Msk (0x01UL << BCCU_CHTRIG_TOS8_Pos) /*!< BCCU CHTRIG: TOS8 Mask */
\r
5825 /* -------------------------------- BCCU_CHSTRCON ------------------------------- */
\r
5826 #define BCCU_CHSTRCON_CH0S_Pos 0 /*!< BCCU CHSTRCON: CH0S Position */
\r
5827 #define BCCU_CHSTRCON_CH0S_Msk (0x01UL << BCCU_CHSTRCON_CH0S_Pos) /*!< BCCU CHSTRCON: CH0S Mask */
\r
5828 #define BCCU_CHSTRCON_CH1S_Pos 1 /*!< BCCU CHSTRCON: CH1S Position */
\r
5829 #define BCCU_CHSTRCON_CH1S_Msk (0x01UL << BCCU_CHSTRCON_CH1S_Pos) /*!< BCCU CHSTRCON: CH1S Mask */
\r
5830 #define BCCU_CHSTRCON_CH2S_Pos 2 /*!< BCCU CHSTRCON: CH2S Position */
\r
5831 #define BCCU_CHSTRCON_CH2S_Msk (0x01UL << BCCU_CHSTRCON_CH2S_Pos) /*!< BCCU CHSTRCON: CH2S Mask */
\r
5832 #define BCCU_CHSTRCON_CH3S_Pos 3 /*!< BCCU CHSTRCON: CH3S Position */
\r
5833 #define BCCU_CHSTRCON_CH3S_Msk (0x01UL << BCCU_CHSTRCON_CH3S_Pos) /*!< BCCU CHSTRCON: CH3S Mask */
\r
5834 #define BCCU_CHSTRCON_CH4S_Pos 4 /*!< BCCU CHSTRCON: CH4S Position */
\r
5835 #define BCCU_CHSTRCON_CH4S_Msk (0x01UL << BCCU_CHSTRCON_CH4S_Pos) /*!< BCCU CHSTRCON: CH4S Mask */
\r
5836 #define BCCU_CHSTRCON_CH5S_Pos 5 /*!< BCCU CHSTRCON: CH5S Position */
\r
5837 #define BCCU_CHSTRCON_CH5S_Msk (0x01UL << BCCU_CHSTRCON_CH5S_Pos) /*!< BCCU CHSTRCON: CH5S Mask */
\r
5838 #define BCCU_CHSTRCON_CH6S_Pos 6 /*!< BCCU CHSTRCON: CH6S Position */
\r
5839 #define BCCU_CHSTRCON_CH6S_Msk (0x01UL << BCCU_CHSTRCON_CH6S_Pos) /*!< BCCU CHSTRCON: CH6S Mask */
\r
5840 #define BCCU_CHSTRCON_CH7S_Pos 7 /*!< BCCU CHSTRCON: CH7S Position */
\r
5841 #define BCCU_CHSTRCON_CH7S_Msk (0x01UL << BCCU_CHSTRCON_CH7S_Pos) /*!< BCCU CHSTRCON: CH7S Mask */
\r
5842 #define BCCU_CHSTRCON_CH8S_Pos 8 /*!< BCCU CHSTRCON: CH8S Position */
\r
5843 #define BCCU_CHSTRCON_CH8S_Msk (0x01UL << BCCU_CHSTRCON_CH8S_Pos) /*!< BCCU CHSTRCON: CH8S Mask */
\r
5844 #define BCCU_CHSTRCON_CH0A_Pos 16 /*!< BCCU CHSTRCON: CH0A Position */
\r
5845 #define BCCU_CHSTRCON_CH0A_Msk (0x01UL << BCCU_CHSTRCON_CH0A_Pos) /*!< BCCU CHSTRCON: CH0A Mask */
\r
5846 #define BCCU_CHSTRCON_CH1A_Pos 17 /*!< BCCU CHSTRCON: CH1A Position */
\r
5847 #define BCCU_CHSTRCON_CH1A_Msk (0x01UL << BCCU_CHSTRCON_CH1A_Pos) /*!< BCCU CHSTRCON: CH1A Mask */
\r
5848 #define BCCU_CHSTRCON_CH2A_Pos 18 /*!< BCCU CHSTRCON: CH2A Position */
\r
5849 #define BCCU_CHSTRCON_CH2A_Msk (0x01UL << BCCU_CHSTRCON_CH2A_Pos) /*!< BCCU CHSTRCON: CH2A Mask */
\r
5850 #define BCCU_CHSTRCON_CH3A_Pos 19 /*!< BCCU CHSTRCON: CH3A Position */
\r
5851 #define BCCU_CHSTRCON_CH3A_Msk (0x01UL << BCCU_CHSTRCON_CH3A_Pos) /*!< BCCU CHSTRCON: CH3A Mask */
\r
5852 #define BCCU_CHSTRCON_CH4A_Pos 20 /*!< BCCU CHSTRCON: CH4A Position */
\r
5853 #define BCCU_CHSTRCON_CH4A_Msk (0x01UL << BCCU_CHSTRCON_CH4A_Pos) /*!< BCCU CHSTRCON: CH4A Mask */
\r
5854 #define BCCU_CHSTRCON_CH5A_Pos 21 /*!< BCCU CHSTRCON: CH5A Position */
\r
5855 #define BCCU_CHSTRCON_CH5A_Msk (0x01UL << BCCU_CHSTRCON_CH5A_Pos) /*!< BCCU CHSTRCON: CH5A Mask */
\r
5856 #define BCCU_CHSTRCON_CH6A_Pos 22 /*!< BCCU CHSTRCON: CH6A Position */
\r
5857 #define BCCU_CHSTRCON_CH6A_Msk (0x01UL << BCCU_CHSTRCON_CH6A_Pos) /*!< BCCU CHSTRCON: CH6A Mask */
\r
5858 #define BCCU_CHSTRCON_CH7A_Pos 23 /*!< BCCU CHSTRCON: CH7A Position */
\r
5859 #define BCCU_CHSTRCON_CH7A_Msk (0x01UL << BCCU_CHSTRCON_CH7A_Pos) /*!< BCCU CHSTRCON: CH7A Mask */
\r
5860 #define BCCU_CHSTRCON_CH8A_Pos 24 /*!< BCCU CHSTRCON: CH8A Position */
\r
5861 #define BCCU_CHSTRCON_CH8A_Msk (0x01UL << BCCU_CHSTRCON_CH8A_Pos) /*!< BCCU CHSTRCON: CH8A Mask */
\r
5863 /* --------------------------------- BCCU_LTCHOL -------------------------------- */
\r
5864 #define BCCU_LTCHOL_LTOL0_Pos 0 /*!< BCCU LTCHOL: LTOL0 Position */
\r
5865 #define BCCU_LTCHOL_LTOL0_Msk (0x01UL << BCCU_LTCHOL_LTOL0_Pos) /*!< BCCU LTCHOL: LTOL0 Mask */
\r
5866 #define BCCU_LTCHOL_LTOL1_Pos 1 /*!< BCCU LTCHOL: LTOL1 Position */
\r
5867 #define BCCU_LTCHOL_LTOL1_Msk (0x01UL << BCCU_LTCHOL_LTOL1_Pos) /*!< BCCU LTCHOL: LTOL1 Mask */
\r
5868 #define BCCU_LTCHOL_LTOL2_Pos 2 /*!< BCCU LTCHOL: LTOL2 Position */
\r
5869 #define BCCU_LTCHOL_LTOL2_Msk (0x01UL << BCCU_LTCHOL_LTOL2_Pos) /*!< BCCU LTCHOL: LTOL2 Mask */
\r
5870 #define BCCU_LTCHOL_LTOL3_Pos 3 /*!< BCCU LTCHOL: LTOL3 Position */
\r
5871 #define BCCU_LTCHOL_LTOL3_Msk (0x01UL << BCCU_LTCHOL_LTOL3_Pos) /*!< BCCU LTCHOL: LTOL3 Mask */
\r
5872 #define BCCU_LTCHOL_LTOL4_Pos 4 /*!< BCCU LTCHOL: LTOL4 Position */
\r
5873 #define BCCU_LTCHOL_LTOL4_Msk (0x01UL << BCCU_LTCHOL_LTOL4_Pos) /*!< BCCU LTCHOL: LTOL4 Mask */
\r
5874 #define BCCU_LTCHOL_LTOL5_Pos 5 /*!< BCCU LTCHOL: LTOL5 Position */
\r
5875 #define BCCU_LTCHOL_LTOL5_Msk (0x01UL << BCCU_LTCHOL_LTOL5_Pos) /*!< BCCU LTCHOL: LTOL5 Mask */
\r
5876 #define BCCU_LTCHOL_LTOL6_Pos 6 /*!< BCCU LTCHOL: LTOL6 Position */
\r
5877 #define BCCU_LTCHOL_LTOL6_Msk (0x01UL << BCCU_LTCHOL_LTOL6_Pos) /*!< BCCU LTCHOL: LTOL6 Mask */
\r
5878 #define BCCU_LTCHOL_LTOL7_Pos 7 /*!< BCCU LTCHOL: LTOL7 Position */
\r
5879 #define BCCU_LTCHOL_LTOL7_Msk (0x01UL << BCCU_LTCHOL_LTOL7_Pos) /*!< BCCU LTCHOL: LTOL7 Mask */
\r
5880 #define BCCU_LTCHOL_LTOL8_Pos 8 /*!< BCCU LTCHOL: LTOL8 Position */
\r
5881 #define BCCU_LTCHOL_LTOL8_Msk (0x01UL << BCCU_LTCHOL_LTOL8_Pos) /*!< BCCU LTCHOL: LTOL8 Mask */
\r
5883 /* ---------------------------------- BCCU_DEEN --------------------------------- */
\r
5884 #define BCCU_DEEN_EDE0_Pos 0 /*!< BCCU DEEN: EDE0 Position */
\r
5885 #define BCCU_DEEN_EDE0_Msk (0x01UL << BCCU_DEEN_EDE0_Pos) /*!< BCCU DEEN: EDE0 Mask */
\r
5886 #define BCCU_DEEN_EDE1_Pos 1 /*!< BCCU DEEN: EDE1 Position */
\r
5887 #define BCCU_DEEN_EDE1_Msk (0x01UL << BCCU_DEEN_EDE1_Pos) /*!< BCCU DEEN: EDE1 Mask */
\r
5888 #define BCCU_DEEN_EDE2_Pos 2 /*!< BCCU DEEN: EDE2 Position */
\r
5889 #define BCCU_DEEN_EDE2_Msk (0x01UL << BCCU_DEEN_EDE2_Pos) /*!< BCCU DEEN: EDE2 Mask */
\r
5891 /* -------------------------------- BCCU_DESTRCON ------------------------------- */
\r
5892 #define BCCU_DESTRCON_DE0S_Pos 0 /*!< BCCU DESTRCON: DE0S Position */
\r
5893 #define BCCU_DESTRCON_DE0S_Msk (0x01UL << BCCU_DESTRCON_DE0S_Pos) /*!< BCCU DESTRCON: DE0S Mask */
\r
5894 #define BCCU_DESTRCON_DE1S_Pos 1 /*!< BCCU DESTRCON: DE1S Position */
\r
5895 #define BCCU_DESTRCON_DE1S_Msk (0x01UL << BCCU_DESTRCON_DE1S_Pos) /*!< BCCU DESTRCON: DE1S Mask */
\r
5896 #define BCCU_DESTRCON_DE2S_Pos 2 /*!< BCCU DESTRCON: DE2S Position */
\r
5897 #define BCCU_DESTRCON_DE2S_Msk (0x01UL << BCCU_DESTRCON_DE2S_Pos) /*!< BCCU DESTRCON: DE2S Mask */
\r
5898 #define BCCU_DESTRCON_DE0A_Pos 16 /*!< BCCU DESTRCON: DE0A Position */
\r
5899 #define BCCU_DESTRCON_DE0A_Msk (0x01UL << BCCU_DESTRCON_DE0A_Pos) /*!< BCCU DESTRCON: DE0A Mask */
\r
5900 #define BCCU_DESTRCON_DE1A_Pos 17 /*!< BCCU DESTRCON: DE1A Position */
\r
5901 #define BCCU_DESTRCON_DE1A_Msk (0x01UL << BCCU_DESTRCON_DE1A_Pos) /*!< BCCU DESTRCON: DE1A Mask */
\r
5902 #define BCCU_DESTRCON_DE2A_Pos 18 /*!< BCCU DESTRCON: DE2A Position */
\r
5903 #define BCCU_DESTRCON_DE2A_Msk (0x01UL << BCCU_DESTRCON_DE2A_Pos) /*!< BCCU DESTRCON: DE2A Mask */
\r
5905 /* -------------------------------- BCCU_GLOBDIM -------------------------------- */
\r
5906 #define BCCU_GLOBDIM_GLOBDIM_Pos 0 /*!< BCCU GLOBDIM: GLOBDIM Position */
\r
5907 #define BCCU_GLOBDIM_GLOBDIM_Msk (0x00000fffUL << BCCU_GLOBDIM_GLOBDIM_Pos) /*!< BCCU GLOBDIM: GLOBDIM Mask */
\r
5909 /* --------------------------------- BCCU_EVIER --------------------------------- */
\r
5910 #define BCCU_EVIER_T0IEN_Pos 0 /*!< BCCU EVIER: T0IEN Position */
\r
5911 #define BCCU_EVIER_T0IEN_Msk (0x01UL << BCCU_EVIER_T0IEN_Pos) /*!< BCCU EVIER: T0IEN Mask */
\r
5912 #define BCCU_EVIER_T1IEN_Pos 1 /*!< BCCU EVIER: T1IEN Position */
\r
5913 #define BCCU_EVIER_T1IEN_Msk (0x01UL << BCCU_EVIER_T1IEN_Pos) /*!< BCCU EVIER: T1IEN Mask */
\r
5914 #define BCCU_EVIER_FIEN_Pos 2 /*!< BCCU EVIER: FIEN Position */
\r
5915 #define BCCU_EVIER_FIEN_Msk (0x01UL << BCCU_EVIER_FIEN_Pos) /*!< BCCU EVIER: FIEN Mask */
\r
5916 #define BCCU_EVIER_EIEN_Pos 3 /*!< BCCU EVIER: EIEN Position */
\r
5917 #define BCCU_EVIER_EIEN_Msk (0x01UL << BCCU_EVIER_EIEN_Pos) /*!< BCCU EVIER: EIEN Mask */
\r
5918 #define BCCU_EVIER_TPIEN_Pos 4 /*!< BCCU EVIER: TPIEN Position */
\r
5919 #define BCCU_EVIER_TPIEN_Msk (0x01UL << BCCU_EVIER_TPIEN_Pos) /*!< BCCU EVIER: TPIEN Mask */
\r
5921 /* ---------------------------------- BCCU_EVFR --------------------------------- */
\r
5922 #define BCCU_EVFR_T0F_Pos 0 /*!< BCCU EVFR: T0F Position */
\r
5923 #define BCCU_EVFR_T0F_Msk (0x01UL << BCCU_EVFR_T0F_Pos) /*!< BCCU EVFR: T0F Mask */
\r
5924 #define BCCU_EVFR_T1F_Pos 1 /*!< BCCU EVFR: T1F Position */
\r
5925 #define BCCU_EVFR_T1F_Msk (0x01UL << BCCU_EVFR_T1F_Pos) /*!< BCCU EVFR: T1F Mask */
\r
5926 #define BCCU_EVFR_FF_Pos 2 /*!< BCCU EVFR: FF Position */
\r
5927 #define BCCU_EVFR_FF_Msk (0x01UL << BCCU_EVFR_FF_Pos) /*!< BCCU EVFR: FF Mask */
\r
5928 #define BCCU_EVFR_EF_Pos 3 /*!< BCCU EVFR: EF Position */
\r
5929 #define BCCU_EVFR_EF_Msk (0x01UL << BCCU_EVFR_EF_Pos) /*!< BCCU EVFR: EF Mask */
\r
5930 #define BCCU_EVFR_TPF_Pos 4 /*!< BCCU EVFR: TPF Position */
\r
5931 #define BCCU_EVFR_TPF_Msk (0x01UL << BCCU_EVFR_TPF_Pos) /*!< BCCU EVFR: TPF Mask */
\r
5932 #define BCCU_EVFR_TPSF_Pos 6 /*!< BCCU EVFR: TPSF Position */
\r
5933 #define BCCU_EVFR_TPSF_Msk (0x01UL << BCCU_EVFR_TPSF_Pos) /*!< BCCU EVFR: TPSF Mask */
\r
5934 #define BCCU_EVFR_TPINL_Pos 7 /*!< BCCU EVFR: TPINL Position */
\r
5935 #define BCCU_EVFR_TPINL_Msk (0x01UL << BCCU_EVFR_TPINL_Pos) /*!< BCCU EVFR: TPINL Mask */
\r
5937 /* --------------------------------- BCCU_EVFSR --------------------------------- */
\r
5938 #define BCCU_EVFSR_T0FS_Pos 0 /*!< BCCU EVFSR: T0FS Position */
\r
5939 #define BCCU_EVFSR_T0FS_Msk (0x01UL << BCCU_EVFSR_T0FS_Pos) /*!< BCCU EVFSR: T0FS Mask */
\r
5940 #define BCCU_EVFSR_T1FS_Pos 1 /*!< BCCU EVFSR: T1FS Position */
\r
5941 #define BCCU_EVFSR_T1FS_Msk (0x01UL << BCCU_EVFSR_T1FS_Pos) /*!< BCCU EVFSR: T1FS Mask */
\r
5942 #define BCCU_EVFSR_FFS_Pos 2 /*!< BCCU EVFSR: FFS Position */
\r
5943 #define BCCU_EVFSR_FFS_Msk (0x01UL << BCCU_EVFSR_FFS_Pos) /*!< BCCU EVFSR: FFS Mask */
\r
5944 #define BCCU_EVFSR_EFS_Pos 3 /*!< BCCU EVFSR: EFS Position */
\r
5945 #define BCCU_EVFSR_EFS_Msk (0x01UL << BCCU_EVFSR_EFS_Pos) /*!< BCCU EVFSR: EFS Mask */
\r
5946 #define BCCU_EVFSR_TPFS_Pos 4 /*!< BCCU EVFSR: TPFS Position */
\r
5947 #define BCCU_EVFSR_TPFS_Msk (0x01UL << BCCU_EVFSR_TPFS_Pos) /*!< BCCU EVFSR: TPFS Mask */
\r
5948 #define BCCU_EVFSR_TPS_Pos 6 /*!< BCCU EVFSR: TPS Position */
\r
5949 #define BCCU_EVFSR_TPS_Msk (0x01UL << BCCU_EVFSR_TPS_Pos) /*!< BCCU EVFSR: TPS Mask */
\r
5951 /* --------------------------------- BCCU_EVFCR --------------------------------- */
\r
5952 #define BCCU_EVFCR_T0FC_Pos 0 /*!< BCCU EVFCR: T0FC Position */
\r
5953 #define BCCU_EVFCR_T0FC_Msk (0x01UL << BCCU_EVFCR_T0FC_Pos) /*!< BCCU EVFCR: T0FC Mask */
\r
5954 #define BCCU_EVFCR_T1FC_Pos 1 /*!< BCCU EVFCR: T1FC Position */
\r
5955 #define BCCU_EVFCR_T1FC_Msk (0x01UL << BCCU_EVFCR_T1FC_Pos) /*!< BCCU EVFCR: T1FC Mask */
\r
5956 #define BCCU_EVFCR_FFC_Pos 2 /*!< BCCU EVFCR: FFC Position */
\r
5957 #define BCCU_EVFCR_FFC_Msk (0x01UL << BCCU_EVFCR_FFC_Pos) /*!< BCCU EVFCR: FFC Mask */
\r
5958 #define BCCU_EVFCR_EFC_Pos 3 /*!< BCCU EVFCR: EFC Position */
\r
5959 #define BCCU_EVFCR_EFC_Msk (0x01UL << BCCU_EVFCR_EFC_Pos) /*!< BCCU EVFCR: EFC Mask */
\r
5960 #define BCCU_EVFCR_TPFC_Pos 4 /*!< BCCU EVFCR: TPFC Position */
\r
5961 #define BCCU_EVFCR_TPFC_Msk (0x01UL << BCCU_EVFCR_TPFC_Pos) /*!< BCCU EVFCR: TPFC Mask */
\r
5962 #define BCCU_EVFCR_TPC_Pos 6 /*!< BCCU EVFCR: TPC Position */
\r
5963 #define BCCU_EVFCR_TPC_Msk (0x01UL << BCCU_EVFCR_TPC_Pos) /*!< BCCU EVFCR: TPC Mask */
\r
5966 /* ================================================================================ */
\r
5967 /* ================ Group 'BCCU_CH' Position & Mask ================ */
\r
5968 /* ================================================================================ */
\r
5971 /* -------------------------------- BCCU_CH_INTS -------------------------------- */
\r
5972 #define BCCU_CH_INTS_TCHINT_Pos 0 /*!< BCCU_CH INTS: TCHINT Position */
\r
5973 #define BCCU_CH_INTS_TCHINT_Msk (0x00000fffUL << BCCU_CH_INTS_TCHINT_Pos) /*!< BCCU_CH INTS: TCHINT Mask */
\r
5975 /* --------------------------------- BCCU_CH_INT -------------------------------- */
\r
5976 #define BCCU_CH_INT_CHINT_Pos 0 /*!< BCCU_CH INT: CHINT Position */
\r
5977 #define BCCU_CH_INT_CHINT_Msk (0x00000fffUL << BCCU_CH_INT_CHINT_Pos) /*!< BCCU_CH INT: CHINT Mask */
\r
5979 /* ------------------------------ BCCU_CH_CHCONFIG ------------------------------ */
\r
5980 #define BCCU_CH_CHCONFIG_PKTH_Pos 0 /*!< BCCU_CH CHCONFIG: PKTH Position */
\r
5981 #define BCCU_CH_CHCONFIG_PKTH_Msk (0x07UL << BCCU_CH_CHCONFIG_PKTH_Pos) /*!< BCCU_CH CHCONFIG: PKTH Mask */
\r
5982 #define BCCU_CH_CHCONFIG_PEN_Pos 3 /*!< BCCU_CH CHCONFIG: PEN Position */
\r
5983 #define BCCU_CH_CHCONFIG_PEN_Msk (0x01UL << BCCU_CH_CHCONFIG_PEN_Pos) /*!< BCCU_CH CHCONFIG: PEN Mask */
\r
5984 #define BCCU_CH_CHCONFIG_DSEL_Pos 4 /*!< BCCU_CH CHCONFIG: DSEL Position */
\r
5985 #define BCCU_CH_CHCONFIG_DSEL_Msk (0x07UL << BCCU_CH_CHCONFIG_DSEL_Pos) /*!< BCCU_CH CHCONFIG: DSEL Mask */
\r
5986 #define BCCU_CH_CHCONFIG_DBP_Pos 7 /*!< BCCU_CH CHCONFIG: DBP Position */
\r
5987 #define BCCU_CH_CHCONFIG_DBP_Msk (0x01UL << BCCU_CH_CHCONFIG_DBP_Pos) /*!< BCCU_CH CHCONFIG: DBP Mask */
\r
5988 #define BCCU_CH_CHCONFIG_GEN_Pos 8 /*!< BCCU_CH CHCONFIG: GEN Position */
\r
5989 #define BCCU_CH_CHCONFIG_GEN_Msk (0x01UL << BCCU_CH_CHCONFIG_GEN_Pos) /*!< BCCU_CH CHCONFIG: GEN Mask */
\r
5990 #define BCCU_CH_CHCONFIG_WEN_Pos 9 /*!< BCCU_CH CHCONFIG: WEN Position */
\r
5991 #define BCCU_CH_CHCONFIG_WEN_Msk (0x01UL << BCCU_CH_CHCONFIG_WEN_Pos) /*!< BCCU_CH CHCONFIG: WEN Mask */
\r
5992 #define BCCU_CH_CHCONFIG_TRED_Pos 10 /*!< BCCU_CH CHCONFIG: TRED Position */
\r
5993 #define BCCU_CH_CHCONFIG_TRED_Msk (0x01UL << BCCU_CH_CHCONFIG_TRED_Pos) /*!< BCCU_CH CHCONFIG: TRED Mask */
\r
5994 #define BCCU_CH_CHCONFIG_ENFT_Pos 11 /*!< BCCU_CH CHCONFIG: ENFT Position */
\r
5995 #define BCCU_CH_CHCONFIG_ENFT_Msk (0x01UL << BCCU_CH_CHCONFIG_ENFT_Pos) /*!< BCCU_CH CHCONFIG: ENFT Mask */
\r
5996 #define BCCU_CH_CHCONFIG_LINPRES_Pos 16 /*!< BCCU_CH CHCONFIG: LINPRES Position */
\r
5997 #define BCCU_CH_CHCONFIG_LINPRES_Msk (0x000003ffUL << BCCU_CH_CHCONFIG_LINPRES_Pos) /*!< BCCU_CH CHCONFIG: LINPRES Mask */
\r
5999 /* -------------------------------- BCCU_CH_PKCMP ------------------------------- */
\r
6000 #define BCCU_CH_PKCMP_OFFCMP_Pos 0 /*!< BCCU_CH PKCMP: OFFCMP Position */
\r
6001 #define BCCU_CH_PKCMP_OFFCMP_Msk (0x000000ffUL << BCCU_CH_PKCMP_OFFCMP_Pos) /*!< BCCU_CH PKCMP: OFFCMP Mask */
\r
6002 #define BCCU_CH_PKCMP_ONCMP_Pos 16 /*!< BCCU_CH PKCMP: ONCMP Position */
\r
6003 #define BCCU_CH_PKCMP_ONCMP_Msk (0x000000ffUL << BCCU_CH_PKCMP_ONCMP_Pos) /*!< BCCU_CH PKCMP: ONCMP Mask */
\r
6005 /* ------------------------------- BCCU_CH_PKCNTR ------------------------------- */
\r
6006 #define BCCU_CH_PKCNTR_OFFCNTVAL_Pos 0 /*!< BCCU_CH PKCNTR: OFFCNTVAL Position */
\r
6007 #define BCCU_CH_PKCNTR_OFFCNTVAL_Msk (0x000000ffUL << BCCU_CH_PKCNTR_OFFCNTVAL_Pos) /*!< BCCU_CH PKCNTR: OFFCNTVAL Mask */
\r
6008 #define BCCU_CH_PKCNTR_ONCNTVAL_Pos 16 /*!< BCCU_CH PKCNTR: ONCNTVAL Position */
\r
6009 #define BCCU_CH_PKCNTR_ONCNTVAL_Msk (0x000000ffUL << BCCU_CH_PKCNTR_ONCNTVAL_Pos) /*!< BCCU_CH PKCNTR: ONCNTVAL Mask */
\r
6012 /* ================================================================================ */
\r
6013 /* ================ Group 'BCCU_DE' Position & Mask ================ */
\r
6014 /* ================================================================================ */
\r
6017 /* --------------------------------- BCCU_DE_DLS -------------------------------- */
\r
6018 #define BCCU_DE_DLS_TDLEV_Pos 0 /*!< BCCU_DE DLS: TDLEV Position */
\r
6019 #define BCCU_DE_DLS_TDLEV_Msk (0x00000fffUL << BCCU_DE_DLS_TDLEV_Pos) /*!< BCCU_DE DLS: TDLEV Mask */
\r
6021 /* --------------------------------- BCCU_DE_DL --------------------------------- */
\r
6022 #define BCCU_DE_DL_DLEV_Pos 0 /*!< BCCU_DE DL: DLEV Position */
\r
6023 #define BCCU_DE_DL_DLEV_Msk (0x00000fffUL << BCCU_DE_DL_DLEV_Pos) /*!< BCCU_DE DL: DLEV Mask */
\r
6025 /* --------------------------------- BCCU_DE_DTT -------------------------------- */
\r
6026 #define BCCU_DE_DTT_DIMDIV_Pos 0 /*!< BCCU_DE DTT: DIMDIV Position */
\r
6027 #define BCCU_DE_DTT_DIMDIV_Msk (0x000003ffUL << BCCU_DE_DTT_DIMDIV_Pos) /*!< BCCU_DE DTT: DIMDIV Mask */
\r
6028 #define BCCU_DE_DTT_DTEN_Pos 16 /*!< BCCU_DE DTT: DTEN Position */
\r
6029 #define BCCU_DE_DTT_DTEN_Msk (0x01UL << BCCU_DE_DTT_DTEN_Pos) /*!< BCCU_DE DTT: DTEN Mask */
\r
6030 #define BCCU_DE_DTT_CSEL_Pos 17 /*!< BCCU_DE DTT: CSEL Position */
\r
6031 #define BCCU_DE_DTT_CSEL_Msk (0x01UL << BCCU_DE_DTT_CSEL_Pos) /*!< BCCU_DE DTT: CSEL Mask */
\r
6034 /* ================================================================================ */
\r
6035 /* ================ struct 'PORT0' Position & Mask ================ */
\r
6036 /* ================================================================================ */
\r
6039 /* ---------------------------------- PORT0_OUT --------------------------------- */
\r
6040 #define PORT0_OUT_P0_Pos 0 /*!< PORT0 OUT: P0 Position */
\r
6041 #define PORT0_OUT_P0_Msk (0x01UL << PORT0_OUT_P0_Pos) /*!< PORT0 OUT: P0 Mask */
\r
6042 #define PORT0_OUT_P1_Pos 1 /*!< PORT0 OUT: P1 Position */
\r
6043 #define PORT0_OUT_P1_Msk (0x01UL << PORT0_OUT_P1_Pos) /*!< PORT0 OUT: P1 Mask */
\r
6044 #define PORT0_OUT_P2_Pos 2 /*!< PORT0 OUT: P2 Position */
\r
6045 #define PORT0_OUT_P2_Msk (0x01UL << PORT0_OUT_P2_Pos) /*!< PORT0 OUT: P2 Mask */
\r
6046 #define PORT0_OUT_P3_Pos 3 /*!< PORT0 OUT: P3 Position */
\r
6047 #define PORT0_OUT_P3_Msk (0x01UL << PORT0_OUT_P3_Pos) /*!< PORT0 OUT: P3 Mask */
\r
6048 #define PORT0_OUT_P4_Pos 4 /*!< PORT0 OUT: P4 Position */
\r
6049 #define PORT0_OUT_P4_Msk (0x01UL << PORT0_OUT_P4_Pos) /*!< PORT0 OUT: P4 Mask */
\r
6050 #define PORT0_OUT_P5_Pos 5 /*!< PORT0 OUT: P5 Position */
\r
6051 #define PORT0_OUT_P5_Msk (0x01UL << PORT0_OUT_P5_Pos) /*!< PORT0 OUT: P5 Mask */
\r
6052 #define PORT0_OUT_P6_Pos 6 /*!< PORT0 OUT: P6 Position */
\r
6053 #define PORT0_OUT_P6_Msk (0x01UL << PORT0_OUT_P6_Pos) /*!< PORT0 OUT: P6 Mask */
\r
6054 #define PORT0_OUT_P7_Pos 7 /*!< PORT0 OUT: P7 Position */
\r
6055 #define PORT0_OUT_P7_Msk (0x01UL << PORT0_OUT_P7_Pos) /*!< PORT0 OUT: P7 Mask */
\r
6056 #define PORT0_OUT_P8_Pos 8 /*!< PORT0 OUT: P8 Position */
\r
6057 #define PORT0_OUT_P8_Msk (0x01UL << PORT0_OUT_P8_Pos) /*!< PORT0 OUT: P8 Mask */
\r
6058 #define PORT0_OUT_P9_Pos 9 /*!< PORT0 OUT: P9 Position */
\r
6059 #define PORT0_OUT_P9_Msk (0x01UL << PORT0_OUT_P9_Pos) /*!< PORT0 OUT: P9 Mask */
\r
6060 #define PORT0_OUT_P10_Pos 10 /*!< PORT0 OUT: P10 Position */
\r
6061 #define PORT0_OUT_P10_Msk (0x01UL << PORT0_OUT_P10_Pos) /*!< PORT0 OUT: P10 Mask */
\r
6062 #define PORT0_OUT_P11_Pos 11 /*!< PORT0 OUT: P11 Position */
\r
6063 #define PORT0_OUT_P11_Msk (0x01UL << PORT0_OUT_P11_Pos) /*!< PORT0 OUT: P11 Mask */
\r
6064 #define PORT0_OUT_P12_Pos 12 /*!< PORT0 OUT: P12 Position */
\r
6065 #define PORT0_OUT_P12_Msk (0x01UL << PORT0_OUT_P12_Pos) /*!< PORT0 OUT: P12 Mask */
\r
6066 #define PORT0_OUT_P13_Pos 13 /*!< PORT0 OUT: P13 Position */
\r
6067 #define PORT0_OUT_P13_Msk (0x01UL << PORT0_OUT_P13_Pos) /*!< PORT0 OUT: P13 Mask */
\r
6068 #define PORT0_OUT_P14_Pos 14 /*!< PORT0 OUT: P14 Position */
\r
6069 #define PORT0_OUT_P14_Msk (0x01UL << PORT0_OUT_P14_Pos) /*!< PORT0 OUT: P14 Mask */
\r
6070 #define PORT0_OUT_P15_Pos 15 /*!< PORT0 OUT: P15 Position */
\r
6071 #define PORT0_OUT_P15_Msk (0x01UL << PORT0_OUT_P15_Pos) /*!< PORT0 OUT: P15 Mask */
\r
6073 /* ---------------------------------- PORT0_OMR --------------------------------- */
\r
6074 #define PORT0_OMR_PS0_Pos 0 /*!< PORT0 OMR: PS0 Position */
\r
6075 #define PORT0_OMR_PS0_Msk (0x01UL << PORT0_OMR_PS0_Pos) /*!< PORT0 OMR: PS0 Mask */
\r
6076 #define PORT0_OMR_PS1_Pos 1 /*!< PORT0 OMR: PS1 Position */
\r
6077 #define PORT0_OMR_PS1_Msk (0x01UL << PORT0_OMR_PS1_Pos) /*!< PORT0 OMR: PS1 Mask */
\r
6078 #define PORT0_OMR_PS2_Pos 2 /*!< PORT0 OMR: PS2 Position */
\r
6079 #define PORT0_OMR_PS2_Msk (0x01UL << PORT0_OMR_PS2_Pos) /*!< PORT0 OMR: PS2 Mask */
\r
6080 #define PORT0_OMR_PS3_Pos 3 /*!< PORT0 OMR: PS3 Position */
\r
6081 #define PORT0_OMR_PS3_Msk (0x01UL << PORT0_OMR_PS3_Pos) /*!< PORT0 OMR: PS3 Mask */
\r
6082 #define PORT0_OMR_PS4_Pos 4 /*!< PORT0 OMR: PS4 Position */
\r
6083 #define PORT0_OMR_PS4_Msk (0x01UL << PORT0_OMR_PS4_Pos) /*!< PORT0 OMR: PS4 Mask */
\r
6084 #define PORT0_OMR_PS5_Pos 5 /*!< PORT0 OMR: PS5 Position */
\r
6085 #define PORT0_OMR_PS5_Msk (0x01UL << PORT0_OMR_PS5_Pos) /*!< PORT0 OMR: PS5 Mask */
\r
6086 #define PORT0_OMR_PS6_Pos 6 /*!< PORT0 OMR: PS6 Position */
\r
6087 #define PORT0_OMR_PS6_Msk (0x01UL << PORT0_OMR_PS6_Pos) /*!< PORT0 OMR: PS6 Mask */
\r
6088 #define PORT0_OMR_PS7_Pos 7 /*!< PORT0 OMR: PS7 Position */
\r
6089 #define PORT0_OMR_PS7_Msk (0x01UL << PORT0_OMR_PS7_Pos) /*!< PORT0 OMR: PS7 Mask */
\r
6090 #define PORT0_OMR_PS8_Pos 8 /*!< PORT0 OMR: PS8 Position */
\r
6091 #define PORT0_OMR_PS8_Msk (0x01UL << PORT0_OMR_PS8_Pos) /*!< PORT0 OMR: PS8 Mask */
\r
6092 #define PORT0_OMR_PS9_Pos 9 /*!< PORT0 OMR: PS9 Position */
\r
6093 #define PORT0_OMR_PS9_Msk (0x01UL << PORT0_OMR_PS9_Pos) /*!< PORT0 OMR: PS9 Mask */
\r
6094 #define PORT0_OMR_PS10_Pos 10 /*!< PORT0 OMR: PS10 Position */
\r
6095 #define PORT0_OMR_PS10_Msk (0x01UL << PORT0_OMR_PS10_Pos) /*!< PORT0 OMR: PS10 Mask */
\r
6096 #define PORT0_OMR_PS11_Pos 11 /*!< PORT0 OMR: PS11 Position */
\r
6097 #define PORT0_OMR_PS11_Msk (0x01UL << PORT0_OMR_PS11_Pos) /*!< PORT0 OMR: PS11 Mask */
\r
6098 #define PORT0_OMR_PS12_Pos 12 /*!< PORT0 OMR: PS12 Position */
\r
6099 #define PORT0_OMR_PS12_Msk (0x01UL << PORT0_OMR_PS12_Pos) /*!< PORT0 OMR: PS12 Mask */
\r
6100 #define PORT0_OMR_PS13_Pos 13 /*!< PORT0 OMR: PS13 Position */
\r
6101 #define PORT0_OMR_PS13_Msk (0x01UL << PORT0_OMR_PS13_Pos) /*!< PORT0 OMR: PS13 Mask */
\r
6102 #define PORT0_OMR_PS14_Pos 14 /*!< PORT0 OMR: PS14 Position */
\r
6103 #define PORT0_OMR_PS14_Msk (0x01UL << PORT0_OMR_PS14_Pos) /*!< PORT0 OMR: PS14 Mask */
\r
6104 #define PORT0_OMR_PS15_Pos 15 /*!< PORT0 OMR: PS15 Position */
\r
6105 #define PORT0_OMR_PS15_Msk (0x01UL << PORT0_OMR_PS15_Pos) /*!< PORT0 OMR: PS15 Mask */
\r
6106 #define PORT0_OMR_PR0_Pos 16 /*!< PORT0 OMR: PR0 Position */
\r
6107 #define PORT0_OMR_PR0_Msk (0x01UL << PORT0_OMR_PR0_Pos) /*!< PORT0 OMR: PR0 Mask */
\r
6108 #define PORT0_OMR_PR1_Pos 17 /*!< PORT0 OMR: PR1 Position */
\r
6109 #define PORT0_OMR_PR1_Msk (0x01UL << PORT0_OMR_PR1_Pos) /*!< PORT0 OMR: PR1 Mask */
\r
6110 #define PORT0_OMR_PR2_Pos 18 /*!< PORT0 OMR: PR2 Position */
\r
6111 #define PORT0_OMR_PR2_Msk (0x01UL << PORT0_OMR_PR2_Pos) /*!< PORT0 OMR: PR2 Mask */
\r
6112 #define PORT0_OMR_PR3_Pos 19 /*!< PORT0 OMR: PR3 Position */
\r
6113 #define PORT0_OMR_PR3_Msk (0x01UL << PORT0_OMR_PR3_Pos) /*!< PORT0 OMR: PR3 Mask */
\r
6114 #define PORT0_OMR_PR4_Pos 20 /*!< PORT0 OMR: PR4 Position */
\r
6115 #define PORT0_OMR_PR4_Msk (0x01UL << PORT0_OMR_PR4_Pos) /*!< PORT0 OMR: PR4 Mask */
\r
6116 #define PORT0_OMR_PR5_Pos 21 /*!< PORT0 OMR: PR5 Position */
\r
6117 #define PORT0_OMR_PR5_Msk (0x01UL << PORT0_OMR_PR5_Pos) /*!< PORT0 OMR: PR5 Mask */
\r
6118 #define PORT0_OMR_PR6_Pos 22 /*!< PORT0 OMR: PR6 Position */
\r
6119 #define PORT0_OMR_PR6_Msk (0x01UL << PORT0_OMR_PR6_Pos) /*!< PORT0 OMR: PR6 Mask */
\r
6120 #define PORT0_OMR_PR7_Pos 23 /*!< PORT0 OMR: PR7 Position */
\r
6121 #define PORT0_OMR_PR7_Msk (0x01UL << PORT0_OMR_PR7_Pos) /*!< PORT0 OMR: PR7 Mask */
\r
6122 #define PORT0_OMR_PR8_Pos 24 /*!< PORT0 OMR: PR8 Position */
\r
6123 #define PORT0_OMR_PR8_Msk (0x01UL << PORT0_OMR_PR8_Pos) /*!< PORT0 OMR: PR8 Mask */
\r
6124 #define PORT0_OMR_PR9_Pos 25 /*!< PORT0 OMR: PR9 Position */
\r
6125 #define PORT0_OMR_PR9_Msk (0x01UL << PORT0_OMR_PR9_Pos) /*!< PORT0 OMR: PR9 Mask */
\r
6126 #define PORT0_OMR_PR10_Pos 26 /*!< PORT0 OMR: PR10 Position */
\r
6127 #define PORT0_OMR_PR10_Msk (0x01UL << PORT0_OMR_PR10_Pos) /*!< PORT0 OMR: PR10 Mask */
\r
6128 #define PORT0_OMR_PR11_Pos 27 /*!< PORT0 OMR: PR11 Position */
\r
6129 #define PORT0_OMR_PR11_Msk (0x01UL << PORT0_OMR_PR11_Pos) /*!< PORT0 OMR: PR11 Mask */
\r
6130 #define PORT0_OMR_PR12_Pos 28 /*!< PORT0 OMR: PR12 Position */
\r
6131 #define PORT0_OMR_PR12_Msk (0x01UL << PORT0_OMR_PR12_Pos) /*!< PORT0 OMR: PR12 Mask */
\r
6132 #define PORT0_OMR_PR13_Pos 29 /*!< PORT0 OMR: PR13 Position */
\r
6133 #define PORT0_OMR_PR13_Msk (0x01UL << PORT0_OMR_PR13_Pos) /*!< PORT0 OMR: PR13 Mask */
\r
6134 #define PORT0_OMR_PR14_Pos 30 /*!< PORT0 OMR: PR14 Position */
\r
6135 #define PORT0_OMR_PR14_Msk (0x01UL << PORT0_OMR_PR14_Pos) /*!< PORT0 OMR: PR14 Mask */
\r
6136 #define PORT0_OMR_PR15_Pos 31 /*!< PORT0 OMR: PR15 Position */
\r
6137 #define PORT0_OMR_PR15_Msk (0x01UL << PORT0_OMR_PR15_Pos) /*!< PORT0 OMR: PR15 Mask */
\r
6139 /* --------------------------------- PORT0_IOCR0 -------------------------------- */
\r
6140 #define PORT0_IOCR0_PC0_Pos 3 /*!< PORT0 IOCR0: PC0 Position */
\r
6141 #define PORT0_IOCR0_PC0_Msk (0x1fUL << PORT0_IOCR0_PC0_Pos) /*!< PORT0 IOCR0: PC0 Mask */
\r
6142 #define PORT0_IOCR0_PC1_Pos 11 /*!< PORT0 IOCR0: PC1 Position */
\r
6143 #define PORT0_IOCR0_PC1_Msk (0x1fUL << PORT0_IOCR0_PC1_Pos) /*!< PORT0 IOCR0: PC1 Mask */
\r
6144 #define PORT0_IOCR0_PC2_Pos 19 /*!< PORT0 IOCR0: PC2 Position */
\r
6145 #define PORT0_IOCR0_PC2_Msk (0x1fUL << PORT0_IOCR0_PC2_Pos) /*!< PORT0 IOCR0: PC2 Mask */
\r
6146 #define PORT0_IOCR0_PC3_Pos 27 /*!< PORT0 IOCR0: PC3 Position */
\r
6147 #define PORT0_IOCR0_PC3_Msk (0x1fUL << PORT0_IOCR0_PC3_Pos) /*!< PORT0 IOCR0: PC3 Mask */
\r
6149 /* --------------------------------- PORT0_IOCR4 -------------------------------- */
\r
6150 #define PORT0_IOCR4_PC4_Pos 3 /*!< PORT0 IOCR4: PC4 Position */
\r
6151 #define PORT0_IOCR4_PC4_Msk (0x1fUL << PORT0_IOCR4_PC4_Pos) /*!< PORT0 IOCR4: PC4 Mask */
\r
6152 #define PORT0_IOCR4_PC5_Pos 11 /*!< PORT0 IOCR4: PC5 Position */
\r
6153 #define PORT0_IOCR4_PC5_Msk (0x1fUL << PORT0_IOCR4_PC5_Pos) /*!< PORT0 IOCR4: PC5 Mask */
\r
6154 #define PORT0_IOCR4_PC6_Pos 19 /*!< PORT0 IOCR4: PC6 Position */
\r
6155 #define PORT0_IOCR4_PC6_Msk (0x1fUL << PORT0_IOCR4_PC6_Pos) /*!< PORT0 IOCR4: PC6 Mask */
\r
6156 #define PORT0_IOCR4_PC7_Pos 27 /*!< PORT0 IOCR4: PC7 Position */
\r
6157 #define PORT0_IOCR4_PC7_Msk (0x1fUL << PORT0_IOCR4_PC7_Pos) /*!< PORT0 IOCR4: PC7 Mask */
\r
6159 /* --------------------------------- PORT0_IOCR8 -------------------------------- */
\r
6160 #define PORT0_IOCR8_PC8_Pos 3 /*!< PORT0 IOCR8: PC8 Position */
\r
6161 #define PORT0_IOCR8_PC8_Msk (0x1fUL << PORT0_IOCR8_PC8_Pos) /*!< PORT0 IOCR8: PC8 Mask */
\r
6162 #define PORT0_IOCR8_PC9_Pos 11 /*!< PORT0 IOCR8: PC9 Position */
\r
6163 #define PORT0_IOCR8_PC9_Msk (0x1fUL << PORT0_IOCR8_PC9_Pos) /*!< PORT0 IOCR8: PC9 Mask */
\r
6164 #define PORT0_IOCR8_PC10_Pos 19 /*!< PORT0 IOCR8: PC10 Position */
\r
6165 #define PORT0_IOCR8_PC10_Msk (0x1fUL << PORT0_IOCR8_PC10_Pos) /*!< PORT0 IOCR8: PC10 Mask */
\r
6166 #define PORT0_IOCR8_PC11_Pos 27 /*!< PORT0 IOCR8: PC11 Position */
\r
6167 #define PORT0_IOCR8_PC11_Msk (0x1fUL << PORT0_IOCR8_PC11_Pos) /*!< PORT0 IOCR8: PC11 Mask */
\r
6169 /* -------------------------------- PORT0_IOCR12 -------------------------------- */
\r
6170 #define PORT0_IOCR12_PC12_Pos 3 /*!< PORT0 IOCR12: PC12 Position */
\r
6171 #define PORT0_IOCR12_PC12_Msk (0x1fUL << PORT0_IOCR12_PC12_Pos) /*!< PORT0 IOCR12: PC12 Mask */
\r
6172 #define PORT0_IOCR12_PC13_Pos 11 /*!< PORT0 IOCR12: PC13 Position */
\r
6173 #define PORT0_IOCR12_PC13_Msk (0x1fUL << PORT0_IOCR12_PC13_Pos) /*!< PORT0 IOCR12: PC13 Mask */
\r
6174 #define PORT0_IOCR12_PC14_Pos 19 /*!< PORT0 IOCR12: PC14 Position */
\r
6175 #define PORT0_IOCR12_PC14_Msk (0x1fUL << PORT0_IOCR12_PC14_Pos) /*!< PORT0 IOCR12: PC14 Mask */
\r
6176 #define PORT0_IOCR12_PC15_Pos 27 /*!< PORT0 IOCR12: PC15 Position */
\r
6177 #define PORT0_IOCR12_PC15_Msk (0x1fUL << PORT0_IOCR12_PC15_Pos) /*!< PORT0 IOCR12: PC15 Mask */
\r
6179 /* ---------------------------------- PORT0_IN ---------------------------------- */
\r
6180 #define PORT0_IN_P0_Pos 0 /*!< PORT0 IN: P0 Position */
\r
6181 #define PORT0_IN_P0_Msk (0x01UL << PORT0_IN_P0_Pos) /*!< PORT0 IN: P0 Mask */
\r
6182 #define PORT0_IN_P1_Pos 1 /*!< PORT0 IN: P1 Position */
\r
6183 #define PORT0_IN_P1_Msk (0x01UL << PORT0_IN_P1_Pos) /*!< PORT0 IN: P1 Mask */
\r
6184 #define PORT0_IN_P2_Pos 2 /*!< PORT0 IN: P2 Position */
\r
6185 #define PORT0_IN_P2_Msk (0x01UL << PORT0_IN_P2_Pos) /*!< PORT0 IN: P2 Mask */
\r
6186 #define PORT0_IN_P3_Pos 3 /*!< PORT0 IN: P3 Position */
\r
6187 #define PORT0_IN_P3_Msk (0x01UL << PORT0_IN_P3_Pos) /*!< PORT0 IN: P3 Mask */
\r
6188 #define PORT0_IN_P4_Pos 4 /*!< PORT0 IN: P4 Position */
\r
6189 #define PORT0_IN_P4_Msk (0x01UL << PORT0_IN_P4_Pos) /*!< PORT0 IN: P4 Mask */
\r
6190 #define PORT0_IN_P5_Pos 5 /*!< PORT0 IN: P5 Position */
\r
6191 #define PORT0_IN_P5_Msk (0x01UL << PORT0_IN_P5_Pos) /*!< PORT0 IN: P5 Mask */
\r
6192 #define PORT0_IN_P6_Pos 6 /*!< PORT0 IN: P6 Position */
\r
6193 #define PORT0_IN_P6_Msk (0x01UL << PORT0_IN_P6_Pos) /*!< PORT0 IN: P6 Mask */
\r
6194 #define PORT0_IN_P7_Pos 7 /*!< PORT0 IN: P7 Position */
\r
6195 #define PORT0_IN_P7_Msk (0x01UL << PORT0_IN_P7_Pos) /*!< PORT0 IN: P7 Mask */
\r
6196 #define PORT0_IN_P8_Pos 8 /*!< PORT0 IN: P8 Position */
\r
6197 #define PORT0_IN_P8_Msk (0x01UL << PORT0_IN_P8_Pos) /*!< PORT0 IN: P8 Mask */
\r
6198 #define PORT0_IN_P9_Pos 9 /*!< PORT0 IN: P9 Position */
\r
6199 #define PORT0_IN_P9_Msk (0x01UL << PORT0_IN_P9_Pos) /*!< PORT0 IN: P9 Mask */
\r
6200 #define PORT0_IN_P10_Pos 10 /*!< PORT0 IN: P10 Position */
\r
6201 #define PORT0_IN_P10_Msk (0x01UL << PORT0_IN_P10_Pos) /*!< PORT0 IN: P10 Mask */
\r
6202 #define PORT0_IN_P11_Pos 11 /*!< PORT0 IN: P11 Position */
\r
6203 #define PORT0_IN_P11_Msk (0x01UL << PORT0_IN_P11_Pos) /*!< PORT0 IN: P11 Mask */
\r
6204 #define PORT0_IN_P12_Pos 12 /*!< PORT0 IN: P12 Position */
\r
6205 #define PORT0_IN_P12_Msk (0x01UL << PORT0_IN_P12_Pos) /*!< PORT0 IN: P12 Mask */
\r
6206 #define PORT0_IN_P13_Pos 13 /*!< PORT0 IN: P13 Position */
\r
6207 #define PORT0_IN_P13_Msk (0x01UL << PORT0_IN_P13_Pos) /*!< PORT0 IN: P13 Mask */
\r
6208 #define PORT0_IN_P14_Pos 14 /*!< PORT0 IN: P14 Position */
\r
6209 #define PORT0_IN_P14_Msk (0x01UL << PORT0_IN_P14_Pos) /*!< PORT0 IN: P14 Mask */
\r
6210 #define PORT0_IN_P15_Pos 15 /*!< PORT0 IN: P15 Position */
\r
6211 #define PORT0_IN_P15_Msk (0x01UL << PORT0_IN_P15_Pos) /*!< PORT0 IN: P15 Mask */
\r
6213 /* --------------------------------- PORT0_PHCR0 -------------------------------- */
\r
6214 #define PORT0_PHCR0_PH0_Pos 2 /*!< PORT0 PHCR0: PH0 Position */
\r
6215 #define PORT0_PHCR0_PH0_Msk (0x01UL << PORT0_PHCR0_PH0_Pos) /*!< PORT0 PHCR0: PH0 Mask */
\r
6216 #define PORT0_PHCR0_PH1_Pos 6 /*!< PORT0 PHCR0: PH1 Position */
\r
6217 #define PORT0_PHCR0_PH1_Msk (0x01UL << PORT0_PHCR0_PH1_Pos) /*!< PORT0 PHCR0: PH1 Mask */
\r
6218 #define PORT0_PHCR0_PH2_Pos 10 /*!< PORT0 PHCR0: PH2 Position */
\r
6219 #define PORT0_PHCR0_PH2_Msk (0x01UL << PORT0_PHCR0_PH2_Pos) /*!< PORT0 PHCR0: PH2 Mask */
\r
6220 #define PORT0_PHCR0_PH3_Pos 14 /*!< PORT0 PHCR0: PH3 Position */
\r
6221 #define PORT0_PHCR0_PH3_Msk (0x01UL << PORT0_PHCR0_PH3_Pos) /*!< PORT0 PHCR0: PH3 Mask */
\r
6222 #define PORT0_PHCR0_PH4_Pos 18 /*!< PORT0 PHCR0: PH4 Position */
\r
6223 #define PORT0_PHCR0_PH4_Msk (0x01UL << PORT0_PHCR0_PH4_Pos) /*!< PORT0 PHCR0: PH4 Mask */
\r
6224 #define PORT0_PHCR0_PH5_Pos 22 /*!< PORT0 PHCR0: PH5 Position */
\r
6225 #define PORT0_PHCR0_PH5_Msk (0x01UL << PORT0_PHCR0_PH5_Pos) /*!< PORT0 PHCR0: PH5 Mask */
\r
6226 #define PORT0_PHCR0_PH6_Pos 26 /*!< PORT0 PHCR0: PH6 Position */
\r
6227 #define PORT0_PHCR0_PH6_Msk (0x01UL << PORT0_PHCR0_PH6_Pos) /*!< PORT0 PHCR0: PH6 Mask */
\r
6228 #define PORT0_PHCR0_PH7_Pos 30 /*!< PORT0 PHCR0: PH7 Position */
\r
6229 #define PORT0_PHCR0_PH7_Msk (0x01UL << PORT0_PHCR0_PH7_Pos) /*!< PORT0 PHCR0: PH7 Mask */
\r
6231 /* --------------------------------- PORT0_PHCR1 -------------------------------- */
\r
6232 #define PORT0_PHCR1_PH8_Pos 2 /*!< PORT0 PHCR1: PH8 Position */
\r
6233 #define PORT0_PHCR1_PH8_Msk (0x01UL << PORT0_PHCR1_PH8_Pos) /*!< PORT0 PHCR1: PH8 Mask */
\r
6234 #define PORT0_PHCR1_PH9_Pos 6 /*!< PORT0 PHCR1: PH9 Position */
\r
6235 #define PORT0_PHCR1_PH9_Msk (0x01UL << PORT0_PHCR1_PH9_Pos) /*!< PORT0 PHCR1: PH9 Mask */
\r
6236 #define PORT0_PHCR1_PH10_Pos 10 /*!< PORT0 PHCR1: PH10 Position */
\r
6237 #define PORT0_PHCR1_PH10_Msk (0x01UL << PORT0_PHCR1_PH10_Pos) /*!< PORT0 PHCR1: PH10 Mask */
\r
6238 #define PORT0_PHCR1_PH11_Pos 14 /*!< PORT0 PHCR1: PH11 Position */
\r
6239 #define PORT0_PHCR1_PH11_Msk (0x01UL << PORT0_PHCR1_PH11_Pos) /*!< PORT0 PHCR1: PH11 Mask */
\r
6240 #define PORT0_PHCR1_PH12_Pos 18 /*!< PORT0 PHCR1: PH12 Position */
\r
6241 #define PORT0_PHCR1_PH12_Msk (0x01UL << PORT0_PHCR1_PH12_Pos) /*!< PORT0 PHCR1: PH12 Mask */
\r
6242 #define PORT0_PHCR1_PH13_Pos 22 /*!< PORT0 PHCR1: PH13 Position */
\r
6243 #define PORT0_PHCR1_PH13_Msk (0x01UL << PORT0_PHCR1_PH13_Pos) /*!< PORT0 PHCR1: PH13 Mask */
\r
6244 #define PORT0_PHCR1_PH14_Pos 26 /*!< PORT0 PHCR1: PH14 Position */
\r
6245 #define PORT0_PHCR1_PH14_Msk (0x01UL << PORT0_PHCR1_PH14_Pos) /*!< PORT0 PHCR1: PH14 Mask */
\r
6246 #define PORT0_PHCR1_PH15_Pos 30 /*!< PORT0 PHCR1: PH15 Position */
\r
6247 #define PORT0_PHCR1_PH15_Msk (0x01UL << PORT0_PHCR1_PH15_Pos) /*!< PORT0 PHCR1: PH15 Mask */
\r
6249 /* --------------------------------- PORT0_PDISC -------------------------------- */
\r
6250 #define PORT0_PDISC_PDIS0_Pos 0 /*!< PORT0 PDISC: PDIS0 Position */
\r
6251 #define PORT0_PDISC_PDIS0_Msk (0x01UL << PORT0_PDISC_PDIS0_Pos) /*!< PORT0 PDISC: PDIS0 Mask */
\r
6252 #define PORT0_PDISC_PDIS1_Pos 1 /*!< PORT0 PDISC: PDIS1 Position */
\r
6253 #define PORT0_PDISC_PDIS1_Msk (0x01UL << PORT0_PDISC_PDIS1_Pos) /*!< PORT0 PDISC: PDIS1 Mask */
\r
6254 #define PORT0_PDISC_PDIS2_Pos 2 /*!< PORT0 PDISC: PDIS2 Position */
\r
6255 #define PORT0_PDISC_PDIS2_Msk (0x01UL << PORT0_PDISC_PDIS2_Pos) /*!< PORT0 PDISC: PDIS2 Mask */
\r
6256 #define PORT0_PDISC_PDIS3_Pos 3 /*!< PORT0 PDISC: PDIS3 Position */
\r
6257 #define PORT0_PDISC_PDIS3_Msk (0x01UL << PORT0_PDISC_PDIS3_Pos) /*!< PORT0 PDISC: PDIS3 Mask */
\r
6258 #define PORT0_PDISC_PDIS4_Pos 4 /*!< PORT0 PDISC: PDIS4 Position */
\r
6259 #define PORT0_PDISC_PDIS4_Msk (0x01UL << PORT0_PDISC_PDIS4_Pos) /*!< PORT0 PDISC: PDIS4 Mask */
\r
6260 #define PORT0_PDISC_PDIS5_Pos 5 /*!< PORT0 PDISC: PDIS5 Position */
\r
6261 #define PORT0_PDISC_PDIS5_Msk (0x01UL << PORT0_PDISC_PDIS5_Pos) /*!< PORT0 PDISC: PDIS5 Mask */
\r
6262 #define PORT0_PDISC_PDIS6_Pos 6 /*!< PORT0 PDISC: PDIS6 Position */
\r
6263 #define PORT0_PDISC_PDIS6_Msk (0x01UL << PORT0_PDISC_PDIS6_Pos) /*!< PORT0 PDISC: PDIS6 Mask */
\r
6264 #define PORT0_PDISC_PDIS7_Pos 7 /*!< PORT0 PDISC: PDIS7 Position */
\r
6265 #define PORT0_PDISC_PDIS7_Msk (0x01UL << PORT0_PDISC_PDIS7_Pos) /*!< PORT0 PDISC: PDIS7 Mask */
\r
6266 #define PORT0_PDISC_PDIS8_Pos 8 /*!< PORT0 PDISC: PDIS8 Position */
\r
6267 #define PORT0_PDISC_PDIS8_Msk (0x01UL << PORT0_PDISC_PDIS8_Pos) /*!< PORT0 PDISC: PDIS8 Mask */
\r
6268 #define PORT0_PDISC_PDIS9_Pos 9 /*!< PORT0 PDISC: PDIS9 Position */
\r
6269 #define PORT0_PDISC_PDIS9_Msk (0x01UL << PORT0_PDISC_PDIS9_Pos) /*!< PORT0 PDISC: PDIS9 Mask */
\r
6270 #define PORT0_PDISC_PDIS10_Pos 10 /*!< PORT0 PDISC: PDIS10 Position */
\r
6271 #define PORT0_PDISC_PDIS10_Msk (0x01UL << PORT0_PDISC_PDIS10_Pos) /*!< PORT0 PDISC: PDIS10 Mask */
\r
6272 #define PORT0_PDISC_PDIS11_Pos 11 /*!< PORT0 PDISC: PDIS11 Position */
\r
6273 #define PORT0_PDISC_PDIS11_Msk (0x01UL << PORT0_PDISC_PDIS11_Pos) /*!< PORT0 PDISC: PDIS11 Mask */
\r
6274 #define PORT0_PDISC_PDIS12_Pos 12 /*!< PORT0 PDISC: PDIS12 Position */
\r
6275 #define PORT0_PDISC_PDIS12_Msk (0x01UL << PORT0_PDISC_PDIS12_Pos) /*!< PORT0 PDISC: PDIS12 Mask */
\r
6276 #define PORT0_PDISC_PDIS13_Pos 13 /*!< PORT0 PDISC: PDIS13 Position */
\r
6277 #define PORT0_PDISC_PDIS13_Msk (0x01UL << PORT0_PDISC_PDIS13_Pos) /*!< PORT0 PDISC: PDIS13 Mask */
\r
6278 #define PORT0_PDISC_PDIS14_Pos 14 /*!< PORT0 PDISC: PDIS14 Position */
\r
6279 #define PORT0_PDISC_PDIS14_Msk (0x01UL << PORT0_PDISC_PDIS14_Pos) /*!< PORT0 PDISC: PDIS14 Mask */
\r
6280 #define PORT0_PDISC_PDIS15_Pos 15 /*!< PORT0 PDISC: PDIS15 Position */
\r
6281 #define PORT0_PDISC_PDIS15_Msk (0x01UL << PORT0_PDISC_PDIS15_Pos) /*!< PORT0 PDISC: PDIS15 Mask */
\r
6283 /* ---------------------------------- PORT0_PPS --------------------------------- */
\r
6284 #define PORT0_PPS_PPS0_Pos 0 /*!< PORT0 PPS: PPS0 Position */
\r
6285 #define PORT0_PPS_PPS0_Msk (0x01UL << PORT0_PPS_PPS0_Pos) /*!< PORT0 PPS: PPS0 Mask */
\r
6286 #define PORT0_PPS_PPS1_Pos 1 /*!< PORT0 PPS: PPS1 Position */
\r
6287 #define PORT0_PPS_PPS1_Msk (0x01UL << PORT0_PPS_PPS1_Pos) /*!< PORT0 PPS: PPS1 Mask */
\r
6288 #define PORT0_PPS_PPS2_Pos 2 /*!< PORT0 PPS: PPS2 Position */
\r
6289 #define PORT0_PPS_PPS2_Msk (0x01UL << PORT0_PPS_PPS2_Pos) /*!< PORT0 PPS: PPS2 Mask */
\r
6290 #define PORT0_PPS_PPS3_Pos 3 /*!< PORT0 PPS: PPS3 Position */
\r
6291 #define PORT0_PPS_PPS3_Msk (0x01UL << PORT0_PPS_PPS3_Pos) /*!< PORT0 PPS: PPS3 Mask */
\r
6292 #define PORT0_PPS_PPS4_Pos 4 /*!< PORT0 PPS: PPS4 Position */
\r
6293 #define PORT0_PPS_PPS4_Msk (0x01UL << PORT0_PPS_PPS4_Pos) /*!< PORT0 PPS: PPS4 Mask */
\r
6294 #define PORT0_PPS_PPS5_Pos 5 /*!< PORT0 PPS: PPS5 Position */
\r
6295 #define PORT0_PPS_PPS5_Msk (0x01UL << PORT0_PPS_PPS5_Pos) /*!< PORT0 PPS: PPS5 Mask */
\r
6296 #define PORT0_PPS_PPS6_Pos 6 /*!< PORT0 PPS: PPS6 Position */
\r
6297 #define PORT0_PPS_PPS6_Msk (0x01UL << PORT0_PPS_PPS6_Pos) /*!< PORT0 PPS: PPS6 Mask */
\r
6298 #define PORT0_PPS_PPS7_Pos 7 /*!< PORT0 PPS: PPS7 Position */
\r
6299 #define PORT0_PPS_PPS7_Msk (0x01UL << PORT0_PPS_PPS7_Pos) /*!< PORT0 PPS: PPS7 Mask */
\r
6300 #define PORT0_PPS_PPS8_Pos 8 /*!< PORT0 PPS: PPS8 Position */
\r
6301 #define PORT0_PPS_PPS8_Msk (0x01UL << PORT0_PPS_PPS8_Pos) /*!< PORT0 PPS: PPS8 Mask */
\r
6302 #define PORT0_PPS_PPS9_Pos 9 /*!< PORT0 PPS: PPS9 Position */
\r
6303 #define PORT0_PPS_PPS9_Msk (0x01UL << PORT0_PPS_PPS9_Pos) /*!< PORT0 PPS: PPS9 Mask */
\r
6304 #define PORT0_PPS_PPS10_Pos 10 /*!< PORT0 PPS: PPS10 Position */
\r
6305 #define PORT0_PPS_PPS10_Msk (0x01UL << PORT0_PPS_PPS10_Pos) /*!< PORT0 PPS: PPS10 Mask */
\r
6306 #define PORT0_PPS_PPS11_Pos 11 /*!< PORT0 PPS: PPS11 Position */
\r
6307 #define PORT0_PPS_PPS11_Msk (0x01UL << PORT0_PPS_PPS11_Pos) /*!< PORT0 PPS: PPS11 Mask */
\r
6308 #define PORT0_PPS_PPS12_Pos 12 /*!< PORT0 PPS: PPS12 Position */
\r
6309 #define PORT0_PPS_PPS12_Msk (0x01UL << PORT0_PPS_PPS12_Pos) /*!< PORT0 PPS: PPS12 Mask */
\r
6310 #define PORT0_PPS_PPS13_Pos 13 /*!< PORT0 PPS: PPS13 Position */
\r
6311 #define PORT0_PPS_PPS13_Msk (0x01UL << PORT0_PPS_PPS13_Pos) /*!< PORT0 PPS: PPS13 Mask */
\r
6312 #define PORT0_PPS_PPS14_Pos 14 /*!< PORT0 PPS: PPS14 Position */
\r
6313 #define PORT0_PPS_PPS14_Msk (0x01UL << PORT0_PPS_PPS14_Pos) /*!< PORT0 PPS: PPS14 Mask */
\r
6314 #define PORT0_PPS_PPS15_Pos 15 /*!< PORT0 PPS: PPS15 Position */
\r
6315 #define PORT0_PPS_PPS15_Msk (0x01UL << PORT0_PPS_PPS15_Pos) /*!< PORT0 PPS: PPS15 Mask */
\r
6317 /* --------------------------------- PORT0_HWSEL -------------------------------- */
\r
6318 #define PORT0_HWSEL_HW0_Pos 0 /*!< PORT0 HWSEL: HW0 Position */
\r
6319 #define PORT0_HWSEL_HW0_Msk (0x03UL << PORT0_HWSEL_HW0_Pos) /*!< PORT0 HWSEL: HW0 Mask */
\r
6320 #define PORT0_HWSEL_HW1_Pos 2 /*!< PORT0 HWSEL: HW1 Position */
\r
6321 #define PORT0_HWSEL_HW1_Msk (0x03UL << PORT0_HWSEL_HW1_Pos) /*!< PORT0 HWSEL: HW1 Mask */
\r
6322 #define PORT0_HWSEL_HW2_Pos 4 /*!< PORT0 HWSEL: HW2 Position */
\r
6323 #define PORT0_HWSEL_HW2_Msk (0x03UL << PORT0_HWSEL_HW2_Pos) /*!< PORT0 HWSEL: HW2 Mask */
\r
6324 #define PORT0_HWSEL_HW3_Pos 6 /*!< PORT0 HWSEL: HW3 Position */
\r
6325 #define PORT0_HWSEL_HW3_Msk (0x03UL << PORT0_HWSEL_HW3_Pos) /*!< PORT0 HWSEL: HW3 Mask */
\r
6326 #define PORT0_HWSEL_HW4_Pos 8 /*!< PORT0 HWSEL: HW4 Position */
\r
6327 #define PORT0_HWSEL_HW4_Msk (0x03UL << PORT0_HWSEL_HW4_Pos) /*!< PORT0 HWSEL: HW4 Mask */
\r
6328 #define PORT0_HWSEL_HW5_Pos 10 /*!< PORT0 HWSEL: HW5 Position */
\r
6329 #define PORT0_HWSEL_HW5_Msk (0x03UL << PORT0_HWSEL_HW5_Pos) /*!< PORT0 HWSEL: HW5 Mask */
\r
6330 #define PORT0_HWSEL_HW6_Pos 12 /*!< PORT0 HWSEL: HW6 Position */
\r
6331 #define PORT0_HWSEL_HW6_Msk (0x03UL << PORT0_HWSEL_HW6_Pos) /*!< PORT0 HWSEL: HW6 Mask */
\r
6332 #define PORT0_HWSEL_HW7_Pos 14 /*!< PORT0 HWSEL: HW7 Position */
\r
6333 #define PORT0_HWSEL_HW7_Msk (0x03UL << PORT0_HWSEL_HW7_Pos) /*!< PORT0 HWSEL: HW7 Mask */
\r
6334 #define PORT0_HWSEL_HW8_Pos 16 /*!< PORT0 HWSEL: HW8 Position */
\r
6335 #define PORT0_HWSEL_HW8_Msk (0x03UL << PORT0_HWSEL_HW8_Pos) /*!< PORT0 HWSEL: HW8 Mask */
\r
6336 #define PORT0_HWSEL_HW9_Pos 18 /*!< PORT0 HWSEL: HW9 Position */
\r
6337 #define PORT0_HWSEL_HW9_Msk (0x03UL << PORT0_HWSEL_HW9_Pos) /*!< PORT0 HWSEL: HW9 Mask */
\r
6338 #define PORT0_HWSEL_HW10_Pos 20 /*!< PORT0 HWSEL: HW10 Position */
\r
6339 #define PORT0_HWSEL_HW10_Msk (0x03UL << PORT0_HWSEL_HW10_Pos) /*!< PORT0 HWSEL: HW10 Mask */
\r
6340 #define PORT0_HWSEL_HW11_Pos 22 /*!< PORT0 HWSEL: HW11 Position */
\r
6341 #define PORT0_HWSEL_HW11_Msk (0x03UL << PORT0_HWSEL_HW11_Pos) /*!< PORT0 HWSEL: HW11 Mask */
\r
6342 #define PORT0_HWSEL_HW12_Pos 24 /*!< PORT0 HWSEL: HW12 Position */
\r
6343 #define PORT0_HWSEL_HW12_Msk (0x03UL << PORT0_HWSEL_HW12_Pos) /*!< PORT0 HWSEL: HW12 Mask */
\r
6344 #define PORT0_HWSEL_HW13_Pos 26 /*!< PORT0 HWSEL: HW13 Position */
\r
6345 #define PORT0_HWSEL_HW13_Msk (0x03UL << PORT0_HWSEL_HW13_Pos) /*!< PORT0 HWSEL: HW13 Mask */
\r
6346 #define PORT0_HWSEL_HW14_Pos 28 /*!< PORT0 HWSEL: HW14 Position */
\r
6347 #define PORT0_HWSEL_HW14_Msk (0x03UL << PORT0_HWSEL_HW14_Pos) /*!< PORT0 HWSEL: HW14 Mask */
\r
6348 #define PORT0_HWSEL_HW15_Pos 30 /*!< PORT0 HWSEL: HW15 Position */
\r
6349 #define PORT0_HWSEL_HW15_Msk (0x03UL << PORT0_HWSEL_HW15_Pos) /*!< PORT0 HWSEL: HW15 Mask */
\r
6352 /* ================================================================================ */
\r
6353 /* ================ struct 'PORT1' Position & Mask ================ */
\r
6354 /* ================================================================================ */
\r
6357 /* ---------------------------------- PORT1_OUT --------------------------------- */
\r
6358 #define PORT1_OUT_P0_Pos 0 /*!< PORT1 OUT: P0 Position */
\r
6359 #define PORT1_OUT_P0_Msk (0x01UL << PORT1_OUT_P0_Pos) /*!< PORT1 OUT: P0 Mask */
\r
6360 #define PORT1_OUT_P1_Pos 1 /*!< PORT1 OUT: P1 Position */
\r
6361 #define PORT1_OUT_P1_Msk (0x01UL << PORT1_OUT_P1_Pos) /*!< PORT1 OUT: P1 Mask */
\r
6362 #define PORT1_OUT_P2_Pos 2 /*!< PORT1 OUT: P2 Position */
\r
6363 #define PORT1_OUT_P2_Msk (0x01UL << PORT1_OUT_P2_Pos) /*!< PORT1 OUT: P2 Mask */
\r
6364 #define PORT1_OUT_P3_Pos 3 /*!< PORT1 OUT: P3 Position */
\r
6365 #define PORT1_OUT_P3_Msk (0x01UL << PORT1_OUT_P3_Pos) /*!< PORT1 OUT: P3 Mask */
\r
6366 #define PORT1_OUT_P4_Pos 4 /*!< PORT1 OUT: P4 Position */
\r
6367 #define PORT1_OUT_P4_Msk (0x01UL << PORT1_OUT_P4_Pos) /*!< PORT1 OUT: P4 Mask */
\r
6368 #define PORT1_OUT_P5_Pos 5 /*!< PORT1 OUT: P5 Position */
\r
6369 #define PORT1_OUT_P5_Msk (0x01UL << PORT1_OUT_P5_Pos) /*!< PORT1 OUT: P5 Mask */
\r
6371 /* ---------------------------------- PORT1_OMR --------------------------------- */
\r
6372 #define PORT1_OMR_PS0_Pos 0 /*!< PORT1 OMR: PS0 Position */
\r
6373 #define PORT1_OMR_PS0_Msk (0x01UL << PORT1_OMR_PS0_Pos) /*!< PORT1 OMR: PS0 Mask */
\r
6374 #define PORT1_OMR_PS1_Pos 1 /*!< PORT1 OMR: PS1 Position */
\r
6375 #define PORT1_OMR_PS1_Msk (0x01UL << PORT1_OMR_PS1_Pos) /*!< PORT1 OMR: PS1 Mask */
\r
6376 #define PORT1_OMR_PS2_Pos 2 /*!< PORT1 OMR: PS2 Position */
\r
6377 #define PORT1_OMR_PS2_Msk (0x01UL << PORT1_OMR_PS2_Pos) /*!< PORT1 OMR: PS2 Mask */
\r
6378 #define PORT1_OMR_PS3_Pos 3 /*!< PORT1 OMR: PS3 Position */
\r
6379 #define PORT1_OMR_PS3_Msk (0x01UL << PORT1_OMR_PS3_Pos) /*!< PORT1 OMR: PS3 Mask */
\r
6380 #define PORT1_OMR_PS4_Pos 4 /*!< PORT1 OMR: PS4 Position */
\r
6381 #define PORT1_OMR_PS4_Msk (0x01UL << PORT1_OMR_PS4_Pos) /*!< PORT1 OMR: PS4 Mask */
\r
6382 #define PORT1_OMR_PS5_Pos 5 /*!< PORT1 OMR: PS5 Position */
\r
6383 #define PORT1_OMR_PS5_Msk (0x01UL << PORT1_OMR_PS5_Pos) /*!< PORT1 OMR: PS5 Mask */
\r
6384 #define PORT1_OMR_PR0_Pos 16 /*!< PORT1 OMR: PR0 Position */
\r
6385 #define PORT1_OMR_PR0_Msk (0x01UL << PORT1_OMR_PR0_Pos) /*!< PORT1 OMR: PR0 Mask */
\r
6386 #define PORT1_OMR_PR1_Pos 17 /*!< PORT1 OMR: PR1 Position */
\r
6387 #define PORT1_OMR_PR1_Msk (0x01UL << PORT1_OMR_PR1_Pos) /*!< PORT1 OMR: PR1 Mask */
\r
6388 #define PORT1_OMR_PR2_Pos 18 /*!< PORT1 OMR: PR2 Position */
\r
6389 #define PORT1_OMR_PR2_Msk (0x01UL << PORT1_OMR_PR2_Pos) /*!< PORT1 OMR: PR2 Mask */
\r
6390 #define PORT1_OMR_PR3_Pos 19 /*!< PORT1 OMR: PR3 Position */
\r
6391 #define PORT1_OMR_PR3_Msk (0x01UL << PORT1_OMR_PR3_Pos) /*!< PORT1 OMR: PR3 Mask */
\r
6392 #define PORT1_OMR_PR4_Pos 20 /*!< PORT1 OMR: PR4 Position */
\r
6393 #define PORT1_OMR_PR4_Msk (0x01UL << PORT1_OMR_PR4_Pos) /*!< PORT1 OMR: PR4 Mask */
\r
6394 #define PORT1_OMR_PR5_Pos 21 /*!< PORT1 OMR: PR5 Position */
\r
6395 #define PORT1_OMR_PR5_Msk (0x01UL << PORT1_OMR_PR5_Pos) /*!< PORT1 OMR: PR5 Mask */
\r
6397 /* --------------------------------- PORT1_IOCR0 -------------------------------- */
\r
6398 #define PORT1_IOCR0_PC0_Pos 3 /*!< PORT1 IOCR0: PC0 Position */
\r
6399 #define PORT1_IOCR0_PC0_Msk (0x1fUL << PORT1_IOCR0_PC0_Pos) /*!< PORT1 IOCR0: PC0 Mask */
\r
6400 #define PORT1_IOCR0_PC1_Pos 11 /*!< PORT1 IOCR0: PC1 Position */
\r
6401 #define PORT1_IOCR0_PC1_Msk (0x1fUL << PORT1_IOCR0_PC1_Pos) /*!< PORT1 IOCR0: PC1 Mask */
\r
6402 #define PORT1_IOCR0_PC2_Pos 19 /*!< PORT1 IOCR0: PC2 Position */
\r
6403 #define PORT1_IOCR0_PC2_Msk (0x1fUL << PORT1_IOCR0_PC2_Pos) /*!< PORT1 IOCR0: PC2 Mask */
\r
6404 #define PORT1_IOCR0_PC3_Pos 27 /*!< PORT1 IOCR0: PC3 Position */
\r
6405 #define PORT1_IOCR0_PC3_Msk (0x1fUL << PORT1_IOCR0_PC3_Pos) /*!< PORT1 IOCR0: PC3 Mask */
\r
6407 /* --------------------------------- PORT1_IOCR4 -------------------------------- */
\r
6408 #define PORT1_IOCR4_PC4_Pos 3 /*!< PORT1 IOCR4: PC4 Position */
\r
6409 #define PORT1_IOCR4_PC4_Msk (0x1fUL << PORT1_IOCR4_PC4_Pos) /*!< PORT1 IOCR4: PC4 Mask */
\r
6410 #define PORT1_IOCR4_PC5_Pos 11 /*!< PORT1 IOCR4: PC5 Position */
\r
6411 #define PORT1_IOCR4_PC5_Msk (0x1fUL << PORT1_IOCR4_PC5_Pos) /*!< PORT1 IOCR4: PC5 Mask */
\r
6413 /* ---------------------------------- PORT1_IN ---------------------------------- */
\r
6414 #define PORT1_IN_P0_Pos 0 /*!< PORT1 IN: P0 Position */
\r
6415 #define PORT1_IN_P0_Msk (0x01UL << PORT1_IN_P0_Pos) /*!< PORT1 IN: P0 Mask */
\r
6416 #define PORT1_IN_P1_Pos 1 /*!< PORT1 IN: P1 Position */
\r
6417 #define PORT1_IN_P1_Msk (0x01UL << PORT1_IN_P1_Pos) /*!< PORT1 IN: P1 Mask */
\r
6418 #define PORT1_IN_P2_Pos 2 /*!< PORT1 IN: P2 Position */
\r
6419 #define PORT1_IN_P2_Msk (0x01UL << PORT1_IN_P2_Pos) /*!< PORT1 IN: P2 Mask */
\r
6420 #define PORT1_IN_P3_Pos 3 /*!< PORT1 IN: P3 Position */
\r
6421 #define PORT1_IN_P3_Msk (0x01UL << PORT1_IN_P3_Pos) /*!< PORT1 IN: P3 Mask */
\r
6422 #define PORT1_IN_P4_Pos 4 /*!< PORT1 IN: P4 Position */
\r
6423 #define PORT1_IN_P4_Msk (0x01UL << PORT1_IN_P4_Pos) /*!< PORT1 IN: P4 Mask */
\r
6424 #define PORT1_IN_P5_Pos 5 /*!< PORT1 IN: P5 Position */
\r
6425 #define PORT1_IN_P5_Msk (0x01UL << PORT1_IN_P5_Pos) /*!< PORT1 IN: P5 Mask */
\r
6427 /* --------------------------------- PORT1_PHCR0 -------------------------------- */
\r
6428 #define PORT1_PHCR0_PH0_Pos 2 /*!< PORT1 PHCR0: PH0 Position */
\r
6429 #define PORT1_PHCR0_PH0_Msk (0x01UL << PORT1_PHCR0_PH0_Pos) /*!< PORT1 PHCR0: PH0 Mask */
\r
6430 #define PORT1_PHCR0_PH1_Pos 6 /*!< PORT1 PHCR0: PH1 Position */
\r
6431 #define PORT1_PHCR0_PH1_Msk (0x01UL << PORT1_PHCR0_PH1_Pos) /*!< PORT1 PHCR0: PH1 Mask */
\r
6432 #define PORT1_PHCR0_PH2_Pos 10 /*!< PORT1 PHCR0: PH2 Position */
\r
6433 #define PORT1_PHCR0_PH2_Msk (0x01UL << PORT1_PHCR0_PH2_Pos) /*!< PORT1 PHCR0: PH2 Mask */
\r
6434 #define PORT1_PHCR0_PH3_Pos 14 /*!< PORT1 PHCR0: PH3 Position */
\r
6435 #define PORT1_PHCR0_PH3_Msk (0x01UL << PORT1_PHCR0_PH3_Pos) /*!< PORT1 PHCR0: PH3 Mask */
\r
6436 #define PORT1_PHCR0_PH4_Pos 18 /*!< PORT1 PHCR0: PH4 Position */
\r
6437 #define PORT1_PHCR0_PH4_Msk (0x01UL << PORT1_PHCR0_PH4_Pos) /*!< PORT1 PHCR0: PH4 Mask */
\r
6438 #define PORT1_PHCR0_PH5_Pos 22 /*!< PORT1 PHCR0: PH5 Position */
\r
6439 #define PORT1_PHCR0_PH5_Msk (0x01UL << PORT1_PHCR0_PH5_Pos) /*!< PORT1 PHCR0: PH5 Mask */
\r
6441 /* --------------------------------- PORT1_PDISC -------------------------------- */
\r
6442 #define PORT1_PDISC_PDIS0_Pos 0 /*!< PORT1 PDISC: PDIS0 Position */
\r
6443 #define PORT1_PDISC_PDIS0_Msk (0x01UL << PORT1_PDISC_PDIS0_Pos) /*!< PORT1 PDISC: PDIS0 Mask */
\r
6444 #define PORT1_PDISC_PDIS1_Pos 1 /*!< PORT1 PDISC: PDIS1 Position */
\r
6445 #define PORT1_PDISC_PDIS1_Msk (0x01UL << PORT1_PDISC_PDIS1_Pos) /*!< PORT1 PDISC: PDIS1 Mask */
\r
6446 #define PORT1_PDISC_PDIS2_Pos 2 /*!< PORT1 PDISC: PDIS2 Position */
\r
6447 #define PORT1_PDISC_PDIS2_Msk (0x01UL << PORT1_PDISC_PDIS2_Pos) /*!< PORT1 PDISC: PDIS2 Mask */
\r
6448 #define PORT1_PDISC_PDIS3_Pos 3 /*!< PORT1 PDISC: PDIS3 Position */
\r
6449 #define PORT1_PDISC_PDIS3_Msk (0x01UL << PORT1_PDISC_PDIS3_Pos) /*!< PORT1 PDISC: PDIS3 Mask */
\r
6450 #define PORT1_PDISC_PDIS4_Pos 4 /*!< PORT1 PDISC: PDIS4 Position */
\r
6451 #define PORT1_PDISC_PDIS4_Msk (0x01UL << PORT1_PDISC_PDIS4_Pos) /*!< PORT1 PDISC: PDIS4 Mask */
\r
6452 #define PORT1_PDISC_PDIS5_Pos 5 /*!< PORT1 PDISC: PDIS5 Position */
\r
6453 #define PORT1_PDISC_PDIS5_Msk (0x01UL << PORT1_PDISC_PDIS5_Pos) /*!< PORT1 PDISC: PDIS5 Mask */
\r
6455 /* ---------------------------------- PORT1_PPS --------------------------------- */
\r
6456 #define PORT1_PPS_PPS0_Pos 0 /*!< PORT1 PPS: PPS0 Position */
\r
6457 #define PORT1_PPS_PPS0_Msk (0x01UL << PORT1_PPS_PPS0_Pos) /*!< PORT1 PPS: PPS0 Mask */
\r
6458 #define PORT1_PPS_PPS1_Pos 1 /*!< PORT1 PPS: PPS1 Position */
\r
6459 #define PORT1_PPS_PPS1_Msk (0x01UL << PORT1_PPS_PPS1_Pos) /*!< PORT1 PPS: PPS1 Mask */
\r
6460 #define PORT1_PPS_PPS2_Pos 2 /*!< PORT1 PPS: PPS2 Position */
\r
6461 #define PORT1_PPS_PPS2_Msk (0x01UL << PORT1_PPS_PPS2_Pos) /*!< PORT1 PPS: PPS2 Mask */
\r
6462 #define PORT1_PPS_PPS3_Pos 3 /*!< PORT1 PPS: PPS3 Position */
\r
6463 #define PORT1_PPS_PPS3_Msk (0x01UL << PORT1_PPS_PPS3_Pos) /*!< PORT1 PPS: PPS3 Mask */
\r
6464 #define PORT1_PPS_PPS4_Pos 4 /*!< PORT1 PPS: PPS4 Position */
\r
6465 #define PORT1_PPS_PPS4_Msk (0x01UL << PORT1_PPS_PPS4_Pos) /*!< PORT1 PPS: PPS4 Mask */
\r
6466 #define PORT1_PPS_PPS5_Pos 5 /*!< PORT1 PPS: PPS5 Position */
\r
6467 #define PORT1_PPS_PPS5_Msk (0x01UL << PORT1_PPS_PPS5_Pos) /*!< PORT1 PPS: PPS5 Mask */
\r
6469 /* --------------------------------- PORT1_HWSEL -------------------------------- */
\r
6470 #define PORT1_HWSEL_HW0_Pos 0 /*!< PORT1 HWSEL: HW0 Position */
\r
6471 #define PORT1_HWSEL_HW0_Msk (0x03UL << PORT1_HWSEL_HW0_Pos) /*!< PORT1 HWSEL: HW0 Mask */
\r
6472 #define PORT1_HWSEL_HW1_Pos 2 /*!< PORT1 HWSEL: HW1 Position */
\r
6473 #define PORT1_HWSEL_HW1_Msk (0x03UL << PORT1_HWSEL_HW1_Pos) /*!< PORT1 HWSEL: HW1 Mask */
\r
6474 #define PORT1_HWSEL_HW2_Pos 4 /*!< PORT1 HWSEL: HW2 Position */
\r
6475 #define PORT1_HWSEL_HW2_Msk (0x03UL << PORT1_HWSEL_HW2_Pos) /*!< PORT1 HWSEL: HW2 Mask */
\r
6476 #define PORT1_HWSEL_HW3_Pos 6 /*!< PORT1 HWSEL: HW3 Position */
\r
6477 #define PORT1_HWSEL_HW3_Msk (0x03UL << PORT1_HWSEL_HW3_Pos) /*!< PORT1 HWSEL: HW3 Mask */
\r
6478 #define PORT1_HWSEL_HW4_Pos 8 /*!< PORT1 HWSEL: HW4 Position */
\r
6479 #define PORT1_HWSEL_HW4_Msk (0x03UL << PORT1_HWSEL_HW4_Pos) /*!< PORT1 HWSEL: HW4 Mask */
\r
6480 #define PORT1_HWSEL_HW5_Pos 10 /*!< PORT1 HWSEL: HW5 Position */
\r
6481 #define PORT1_HWSEL_HW5_Msk (0x03UL << PORT1_HWSEL_HW5_Pos) /*!< PORT1 HWSEL: HW5 Mask */
\r
6484 /* ================================================================================ */
\r
6485 /* ================ struct 'PORT2' Position & Mask ================ */
\r
6486 /* ================================================================================ */
\r
6489 /* ---------------------------------- PORT2_OUT --------------------------------- */
\r
6490 #define PORT2_OUT_P0_Pos 0 /*!< PORT2 OUT: P0 Position */
\r
6491 #define PORT2_OUT_P0_Msk (0x01UL << PORT2_OUT_P0_Pos) /*!< PORT2 OUT: P0 Mask */
\r
6492 #define PORT2_OUT_P1_Pos 1 /*!< PORT2 OUT: P1 Position */
\r
6493 #define PORT2_OUT_P1_Msk (0x01UL << PORT2_OUT_P1_Pos) /*!< PORT2 OUT: P1 Mask */
\r
6494 #define PORT2_OUT_P2_Pos 2 /*!< PORT2 OUT: P2 Position */
\r
6495 #define PORT2_OUT_P2_Msk (0x01UL << PORT2_OUT_P2_Pos) /*!< PORT2 OUT: P2 Mask */
\r
6496 #define PORT2_OUT_P3_Pos 3 /*!< PORT2 OUT: P3 Position */
\r
6497 #define PORT2_OUT_P3_Msk (0x01UL << PORT2_OUT_P3_Pos) /*!< PORT2 OUT: P3 Mask */
\r
6498 #define PORT2_OUT_P4_Pos 4 /*!< PORT2 OUT: P4 Position */
\r
6499 #define PORT2_OUT_P4_Msk (0x01UL << PORT2_OUT_P4_Pos) /*!< PORT2 OUT: P4 Mask */
\r
6500 #define PORT2_OUT_P5_Pos 5 /*!< PORT2 OUT: P5 Position */
\r
6501 #define PORT2_OUT_P5_Msk (0x01UL << PORT2_OUT_P5_Pos) /*!< PORT2 OUT: P5 Mask */
\r
6502 #define PORT2_OUT_P6_Pos 6 /*!< PORT2 OUT: P6 Position */
\r
6503 #define PORT2_OUT_P6_Msk (0x01UL << PORT2_OUT_P6_Pos) /*!< PORT2 OUT: P6 Mask */
\r
6504 #define PORT2_OUT_P7_Pos 7 /*!< PORT2 OUT: P7 Position */
\r
6505 #define PORT2_OUT_P7_Msk (0x01UL << PORT2_OUT_P7_Pos) /*!< PORT2 OUT: P7 Mask */
\r
6506 #define PORT2_OUT_P8_Pos 8 /*!< PORT2 OUT: P8 Position */
\r
6507 #define PORT2_OUT_P8_Msk (0x01UL << PORT2_OUT_P8_Pos) /*!< PORT2 OUT: P8 Mask */
\r
6508 #define PORT2_OUT_P9_Pos 9 /*!< PORT2 OUT: P9 Position */
\r
6509 #define PORT2_OUT_P9_Msk (0x01UL << PORT2_OUT_P9_Pos) /*!< PORT2 OUT: P9 Mask */
\r
6510 #define PORT2_OUT_P10_Pos 10 /*!< PORT2 OUT: P10 Position */
\r
6511 #define PORT2_OUT_P10_Msk (0x01UL << PORT2_OUT_P10_Pos) /*!< PORT2 OUT: P10 Mask */
\r
6512 #define PORT2_OUT_P11_Pos 11 /*!< PORT2 OUT: P11 Position */
\r
6513 #define PORT2_OUT_P11_Msk (0x01UL << PORT2_OUT_P11_Pos) /*!< PORT2 OUT: P11 Mask */
\r
6515 /* ---------------------------------- PORT2_OMR --------------------------------- */
\r
6516 #define PORT2_OMR_PS0_Pos 0 /*!< PORT2 OMR: PS0 Position */
\r
6517 #define PORT2_OMR_PS0_Msk (0x01UL << PORT2_OMR_PS0_Pos) /*!< PORT2 OMR: PS0 Mask */
\r
6518 #define PORT2_OMR_PS1_Pos 1 /*!< PORT2 OMR: PS1 Position */
\r
6519 #define PORT2_OMR_PS1_Msk (0x01UL << PORT2_OMR_PS1_Pos) /*!< PORT2 OMR: PS1 Mask */
\r
6520 #define PORT2_OMR_PS2_Pos 2 /*!< PORT2 OMR: PS2 Position */
\r
6521 #define PORT2_OMR_PS2_Msk (0x01UL << PORT2_OMR_PS2_Pos) /*!< PORT2 OMR: PS2 Mask */
\r
6522 #define PORT2_OMR_PS3_Pos 3 /*!< PORT2 OMR: PS3 Position */
\r
6523 #define PORT2_OMR_PS3_Msk (0x01UL << PORT2_OMR_PS3_Pos) /*!< PORT2 OMR: PS3 Mask */
\r
6524 #define PORT2_OMR_PS4_Pos 4 /*!< PORT2 OMR: PS4 Position */
\r
6525 #define PORT2_OMR_PS4_Msk (0x01UL << PORT2_OMR_PS4_Pos) /*!< PORT2 OMR: PS4 Mask */
\r
6526 #define PORT2_OMR_PS5_Pos 5 /*!< PORT2 OMR: PS5 Position */
\r
6527 #define PORT2_OMR_PS5_Msk (0x01UL << PORT2_OMR_PS5_Pos) /*!< PORT2 OMR: PS5 Mask */
\r
6528 #define PORT2_OMR_PS6_Pos 6 /*!< PORT2 OMR: PS6 Position */
\r
6529 #define PORT2_OMR_PS6_Msk (0x01UL << PORT2_OMR_PS6_Pos) /*!< PORT2 OMR: PS6 Mask */
\r
6530 #define PORT2_OMR_PS7_Pos 7 /*!< PORT2 OMR: PS7 Position */
\r
6531 #define PORT2_OMR_PS7_Msk (0x01UL << PORT2_OMR_PS7_Pos) /*!< PORT2 OMR: PS7 Mask */
\r
6532 #define PORT2_OMR_PS8_Pos 8 /*!< PORT2 OMR: PS8 Position */
\r
6533 #define PORT2_OMR_PS8_Msk (0x01UL << PORT2_OMR_PS8_Pos) /*!< PORT2 OMR: PS8 Mask */
\r
6534 #define PORT2_OMR_PS9_Pos 9 /*!< PORT2 OMR: PS9 Position */
\r
6535 #define PORT2_OMR_PS9_Msk (0x01UL << PORT2_OMR_PS9_Pos) /*!< PORT2 OMR: PS9 Mask */
\r
6536 #define PORT2_OMR_PS10_Pos 10 /*!< PORT2 OMR: PS10 Position */
\r
6537 #define PORT2_OMR_PS10_Msk (0x01UL << PORT2_OMR_PS10_Pos) /*!< PORT2 OMR: PS10 Mask */
\r
6538 #define PORT2_OMR_PS11_Pos 11 /*!< PORT2 OMR: PS11 Position */
\r
6539 #define PORT2_OMR_PS11_Msk (0x01UL << PORT2_OMR_PS11_Pos) /*!< PORT2 OMR: PS11 Mask */
\r
6540 #define PORT2_OMR_PR0_Pos 16 /*!< PORT2 OMR: PR0 Position */
\r
6541 #define PORT2_OMR_PR0_Msk (0x01UL << PORT2_OMR_PR0_Pos) /*!< PORT2 OMR: PR0 Mask */
\r
6542 #define PORT2_OMR_PR1_Pos 17 /*!< PORT2 OMR: PR1 Position */
\r
6543 #define PORT2_OMR_PR1_Msk (0x01UL << PORT2_OMR_PR1_Pos) /*!< PORT2 OMR: PR1 Mask */
\r
6544 #define PORT2_OMR_PR2_Pos 18 /*!< PORT2 OMR: PR2 Position */
\r
6545 #define PORT2_OMR_PR2_Msk (0x01UL << PORT2_OMR_PR2_Pos) /*!< PORT2 OMR: PR2 Mask */
\r
6546 #define PORT2_OMR_PR3_Pos 19 /*!< PORT2 OMR: PR3 Position */
\r
6547 #define PORT2_OMR_PR3_Msk (0x01UL << PORT2_OMR_PR3_Pos) /*!< PORT2 OMR: PR3 Mask */
\r
6548 #define PORT2_OMR_PR4_Pos 20 /*!< PORT2 OMR: PR4 Position */
\r
6549 #define PORT2_OMR_PR4_Msk (0x01UL << PORT2_OMR_PR4_Pos) /*!< PORT2 OMR: PR4 Mask */
\r
6550 #define PORT2_OMR_PR5_Pos 21 /*!< PORT2 OMR: PR5 Position */
\r
6551 #define PORT2_OMR_PR5_Msk (0x01UL << PORT2_OMR_PR5_Pos) /*!< PORT2 OMR: PR5 Mask */
\r
6552 #define PORT2_OMR_PR6_Pos 22 /*!< PORT2 OMR: PR6 Position */
\r
6553 #define PORT2_OMR_PR6_Msk (0x01UL << PORT2_OMR_PR6_Pos) /*!< PORT2 OMR: PR6 Mask */
\r
6554 #define PORT2_OMR_PR7_Pos 23 /*!< PORT2 OMR: PR7 Position */
\r
6555 #define PORT2_OMR_PR7_Msk (0x01UL << PORT2_OMR_PR7_Pos) /*!< PORT2 OMR: PR7 Mask */
\r
6556 #define PORT2_OMR_PR8_Pos 24 /*!< PORT2 OMR: PR8 Position */
\r
6557 #define PORT2_OMR_PR8_Msk (0x01UL << PORT2_OMR_PR8_Pos) /*!< PORT2 OMR: PR8 Mask */
\r
6558 #define PORT2_OMR_PR9_Pos 25 /*!< PORT2 OMR: PR9 Position */
\r
6559 #define PORT2_OMR_PR9_Msk (0x01UL << PORT2_OMR_PR9_Pos) /*!< PORT2 OMR: PR9 Mask */
\r
6560 #define PORT2_OMR_PR10_Pos 26 /*!< PORT2 OMR: PR10 Position */
\r
6561 #define PORT2_OMR_PR10_Msk (0x01UL << PORT2_OMR_PR10_Pos) /*!< PORT2 OMR: PR10 Mask */
\r
6562 #define PORT2_OMR_PR11_Pos 27 /*!< PORT2 OMR: PR11 Position */
\r
6563 #define PORT2_OMR_PR11_Msk (0x01UL << PORT2_OMR_PR11_Pos) /*!< PORT2 OMR: PR11 Mask */
\r
6565 /* --------------------------------- PORT2_IOCR0 -------------------------------- */
\r
6566 #define PORT2_IOCR0_PC0_Pos 3 /*!< PORT2 IOCR0: PC0 Position */
\r
6567 #define PORT2_IOCR0_PC0_Msk (0x1fUL << PORT2_IOCR0_PC0_Pos) /*!< PORT2 IOCR0: PC0 Mask */
\r
6568 #define PORT2_IOCR0_PC1_Pos 11 /*!< PORT2 IOCR0: PC1 Position */
\r
6569 #define PORT2_IOCR0_PC1_Msk (0x1fUL << PORT2_IOCR0_PC1_Pos) /*!< PORT2 IOCR0: PC1 Mask */
\r
6570 #define PORT2_IOCR0_PC2_Pos 19 /*!< PORT2 IOCR0: PC2 Position */
\r
6571 #define PORT2_IOCR0_PC2_Msk (0x1fUL << PORT2_IOCR0_PC2_Pos) /*!< PORT2 IOCR0: PC2 Mask */
\r
6572 #define PORT2_IOCR0_PC3_Pos 27 /*!< PORT2 IOCR0: PC3 Position */
\r
6573 #define PORT2_IOCR0_PC3_Msk (0x1fUL << PORT2_IOCR0_PC3_Pos) /*!< PORT2 IOCR0: PC3 Mask */
\r
6575 /* --------------------------------- PORT2_IOCR4 -------------------------------- */
\r
6576 #define PORT2_IOCR4_PC4_Pos 3 /*!< PORT2 IOCR4: PC4 Position */
\r
6577 #define PORT2_IOCR4_PC4_Msk (0x1fUL << PORT2_IOCR4_PC4_Pos) /*!< PORT2 IOCR4: PC4 Mask */
\r
6578 #define PORT2_IOCR4_PC5_Pos 11 /*!< PORT2 IOCR4: PC5 Position */
\r
6579 #define PORT2_IOCR4_PC5_Msk (0x1fUL << PORT2_IOCR4_PC5_Pos) /*!< PORT2 IOCR4: PC5 Mask */
\r
6580 #define PORT2_IOCR4_PC6_Pos 19 /*!< PORT2 IOCR4: PC6 Position */
\r
6581 #define PORT2_IOCR4_PC6_Msk (0x1fUL << PORT2_IOCR4_PC6_Pos) /*!< PORT2 IOCR4: PC6 Mask */
\r
6582 #define PORT2_IOCR4_PC7_Pos 27 /*!< PORT2 IOCR4: PC7 Position */
\r
6583 #define PORT2_IOCR4_PC7_Msk (0x1fUL << PORT2_IOCR4_PC7_Pos) /*!< PORT2 IOCR4: PC7 Mask */
\r
6585 /* --------------------------------- PORT2_IOCR8 -------------------------------- */
\r
6586 #define PORT2_IOCR8_PC8_Pos 3 /*!< PORT2 IOCR8: PC8 Position */
\r
6587 #define PORT2_IOCR8_PC8_Msk (0x1fUL << PORT2_IOCR8_PC8_Pos) /*!< PORT2 IOCR8: PC8 Mask */
\r
6588 #define PORT2_IOCR8_PC9_Pos 11 /*!< PORT2 IOCR8: PC9 Position */
\r
6589 #define PORT2_IOCR8_PC9_Msk (0x1fUL << PORT2_IOCR8_PC9_Pos) /*!< PORT2 IOCR8: PC9 Mask */
\r
6590 #define PORT2_IOCR8_PC10_Pos 19 /*!< PORT2 IOCR8: PC10 Position */
\r
6591 #define PORT2_IOCR8_PC10_Msk (0x1fUL << PORT2_IOCR8_PC10_Pos) /*!< PORT2 IOCR8: PC10 Mask */
\r
6592 #define PORT2_IOCR8_PC11_Pos 27 /*!< PORT2 IOCR8: PC11 Position */
\r
6593 #define PORT2_IOCR8_PC11_Msk (0x1fUL << PORT2_IOCR8_PC11_Pos) /*!< PORT2 IOCR8: PC11 Mask */
\r
6595 /* ---------------------------------- PORT2_IN ---------------------------------- */
\r
6596 #define PORT2_IN_P0_Pos 0 /*!< PORT2 IN: P0 Position */
\r
6597 #define PORT2_IN_P0_Msk (0x01UL << PORT2_IN_P0_Pos) /*!< PORT2 IN: P0 Mask */
\r
6598 #define PORT2_IN_P1_Pos 1 /*!< PORT2 IN: P1 Position */
\r
6599 #define PORT2_IN_P1_Msk (0x01UL << PORT2_IN_P1_Pos) /*!< PORT2 IN: P1 Mask */
\r
6600 #define PORT2_IN_P2_Pos 2 /*!< PORT2 IN: P2 Position */
\r
6601 #define PORT2_IN_P2_Msk (0x01UL << PORT2_IN_P2_Pos) /*!< PORT2 IN: P2 Mask */
\r
6602 #define PORT2_IN_P3_Pos 3 /*!< PORT2 IN: P3 Position */
\r
6603 #define PORT2_IN_P3_Msk (0x01UL << PORT2_IN_P3_Pos) /*!< PORT2 IN: P3 Mask */
\r
6604 #define PORT2_IN_P4_Pos 4 /*!< PORT2 IN: P4 Position */
\r
6605 #define PORT2_IN_P4_Msk (0x01UL << PORT2_IN_P4_Pos) /*!< PORT2 IN: P4 Mask */
\r
6606 #define PORT2_IN_P5_Pos 5 /*!< PORT2 IN: P5 Position */
\r
6607 #define PORT2_IN_P5_Msk (0x01UL << PORT2_IN_P5_Pos) /*!< PORT2 IN: P5 Mask */
\r
6608 #define PORT2_IN_P6_Pos 6 /*!< PORT2 IN: P6 Position */
\r
6609 #define PORT2_IN_P6_Msk (0x01UL << PORT2_IN_P6_Pos) /*!< PORT2 IN: P6 Mask */
\r
6610 #define PORT2_IN_P7_Pos 7 /*!< PORT2 IN: P7 Position */
\r
6611 #define PORT2_IN_P7_Msk (0x01UL << PORT2_IN_P7_Pos) /*!< PORT2 IN: P7 Mask */
\r
6612 #define PORT2_IN_P8_Pos 8 /*!< PORT2 IN: P8 Position */
\r
6613 #define PORT2_IN_P8_Msk (0x01UL << PORT2_IN_P8_Pos) /*!< PORT2 IN: P8 Mask */
\r
6614 #define PORT2_IN_P9_Pos 9 /*!< PORT2 IN: P9 Position */
\r
6615 #define PORT2_IN_P9_Msk (0x01UL << PORT2_IN_P9_Pos) /*!< PORT2 IN: P9 Mask */
\r
6616 #define PORT2_IN_P10_Pos 10 /*!< PORT2 IN: P10 Position */
\r
6617 #define PORT2_IN_P10_Msk (0x01UL << PORT2_IN_P10_Pos) /*!< PORT2 IN: P10 Mask */
\r
6618 #define PORT2_IN_P11_Pos 11 /*!< PORT2 IN: P11 Position */
\r
6619 #define PORT2_IN_P11_Msk (0x01UL << PORT2_IN_P11_Pos) /*!< PORT2 IN: P11 Mask */
\r
6621 /* --------------------------------- PORT2_PHCR0 -------------------------------- */
\r
6622 #define PORT2_PHCR0_PH0_Pos 2 /*!< PORT2 PHCR0: PH0 Position */
\r
6623 #define PORT2_PHCR0_PH0_Msk (0x01UL << PORT2_PHCR0_PH0_Pos) /*!< PORT2 PHCR0: PH0 Mask */
\r
6624 #define PORT2_PHCR0_PH1_Pos 6 /*!< PORT2 PHCR0: PH1 Position */
\r
6625 #define PORT2_PHCR0_PH1_Msk (0x01UL << PORT2_PHCR0_PH1_Pos) /*!< PORT2 PHCR0: PH1 Mask */
\r
6626 #define PORT2_PHCR0_PH2_Pos 10 /*!< PORT2 PHCR0: PH2 Position */
\r
6627 #define PORT2_PHCR0_PH2_Msk (0x01UL << PORT2_PHCR0_PH2_Pos) /*!< PORT2 PHCR0: PH2 Mask */
\r
6628 #define PORT2_PHCR0_PH3_Pos 14 /*!< PORT2 PHCR0: PH3 Position */
\r
6629 #define PORT2_PHCR0_PH3_Msk (0x01UL << PORT2_PHCR0_PH3_Pos) /*!< PORT2 PHCR0: PH3 Mask */
\r
6630 #define PORT2_PHCR0_PH4_Pos 18 /*!< PORT2 PHCR0: PH4 Position */
\r
6631 #define PORT2_PHCR0_PH4_Msk (0x01UL << PORT2_PHCR0_PH4_Pos) /*!< PORT2 PHCR0: PH4 Mask */
\r
6632 #define PORT2_PHCR0_PH5_Pos 22 /*!< PORT2 PHCR0: PH5 Position */
\r
6633 #define PORT2_PHCR0_PH5_Msk (0x01UL << PORT2_PHCR0_PH5_Pos) /*!< PORT2 PHCR0: PH5 Mask */
\r
6634 #define PORT2_PHCR0_PH6_Pos 26 /*!< PORT2 PHCR0: PH6 Position */
\r
6635 #define PORT2_PHCR0_PH6_Msk (0x01UL << PORT2_PHCR0_PH6_Pos) /*!< PORT2 PHCR0: PH6 Mask */
\r
6636 #define PORT2_PHCR0_PH7_Pos 30 /*!< PORT2 PHCR0: PH7 Position */
\r
6637 #define PORT2_PHCR0_PH7_Msk (0x01UL << PORT2_PHCR0_PH7_Pos) /*!< PORT2 PHCR0: PH7 Mask */
\r
6639 /* --------------------------------- PORT2_PHCR1 -------------------------------- */
\r
6640 #define PORT2_PHCR1_PH8_Pos 2 /*!< PORT2 PHCR1: PH8 Position */
\r
6641 #define PORT2_PHCR1_PH8_Msk (0x01UL << PORT2_PHCR1_PH8_Pos) /*!< PORT2 PHCR1: PH8 Mask */
\r
6642 #define PORT2_PHCR1_PH9_Pos 6 /*!< PORT2 PHCR1: PH9 Position */
\r
6643 #define PORT2_PHCR1_PH9_Msk (0x01UL << PORT2_PHCR1_PH9_Pos) /*!< PORT2 PHCR1: PH9 Mask */
\r
6644 #define PORT2_PHCR1_PH10_Pos 10 /*!< PORT2 PHCR1: PH10 Position */
\r
6645 #define PORT2_PHCR1_PH10_Msk (0x01UL << PORT2_PHCR1_PH10_Pos) /*!< PORT2 PHCR1: PH10 Mask */
\r
6646 #define PORT2_PHCR1_PH11_Pos 14 /*!< PORT2 PHCR1: PH11 Position */
\r
6647 #define PORT2_PHCR1_PH11_Msk (0x01UL << PORT2_PHCR1_PH11_Pos) /*!< PORT2 PHCR1: PH11 Mask */
\r
6649 /* --------------------------------- PORT2_PDISC -------------------------------- */
\r
6650 #define PORT2_PDISC_PDIS0_Pos 0 /*!< PORT2 PDISC: PDIS0 Position */
\r
6651 #define PORT2_PDISC_PDIS0_Msk (0x01UL << PORT2_PDISC_PDIS0_Pos) /*!< PORT2 PDISC: PDIS0 Mask */
\r
6652 #define PORT2_PDISC_PDIS1_Pos 1 /*!< PORT2 PDISC: PDIS1 Position */
\r
6653 #define PORT2_PDISC_PDIS1_Msk (0x01UL << PORT2_PDISC_PDIS1_Pos) /*!< PORT2 PDISC: PDIS1 Mask */
\r
6654 #define PORT2_PDISC_PDIS2_Pos 2 /*!< PORT2 PDISC: PDIS2 Position */
\r
6655 #define PORT2_PDISC_PDIS2_Msk (0x01UL << PORT2_PDISC_PDIS2_Pos) /*!< PORT2 PDISC: PDIS2 Mask */
\r
6656 #define PORT2_PDISC_PDIS3_Pos 3 /*!< PORT2 PDISC: PDIS3 Position */
\r
6657 #define PORT2_PDISC_PDIS3_Msk (0x01UL << PORT2_PDISC_PDIS3_Pos) /*!< PORT2 PDISC: PDIS3 Mask */
\r
6658 #define PORT2_PDISC_PDIS4_Pos 4 /*!< PORT2 PDISC: PDIS4 Position */
\r
6659 #define PORT2_PDISC_PDIS4_Msk (0x01UL << PORT2_PDISC_PDIS4_Pos) /*!< PORT2 PDISC: PDIS4 Mask */
\r
6660 #define PORT2_PDISC_PDIS5_Pos 5 /*!< PORT2 PDISC: PDIS5 Position */
\r
6661 #define PORT2_PDISC_PDIS5_Msk (0x01UL << PORT2_PDISC_PDIS5_Pos) /*!< PORT2 PDISC: PDIS5 Mask */
\r
6662 #define PORT2_PDISC_PDIS6_Pos 6 /*!< PORT2 PDISC: PDIS6 Position */
\r
6663 #define PORT2_PDISC_PDIS6_Msk (0x01UL << PORT2_PDISC_PDIS6_Pos) /*!< PORT2 PDISC: PDIS6 Mask */
\r
6664 #define PORT2_PDISC_PDIS7_Pos 7 /*!< PORT2 PDISC: PDIS7 Position */
\r
6665 #define PORT2_PDISC_PDIS7_Msk (0x01UL << PORT2_PDISC_PDIS7_Pos) /*!< PORT2 PDISC: PDIS7 Mask */
\r
6666 #define PORT2_PDISC_PDIS8_Pos 8 /*!< PORT2 PDISC: PDIS8 Position */
\r
6667 #define PORT2_PDISC_PDIS8_Msk (0x01UL << PORT2_PDISC_PDIS8_Pos) /*!< PORT2 PDISC: PDIS8 Mask */
\r
6668 #define PORT2_PDISC_PDIS9_Pos 9 /*!< PORT2 PDISC: PDIS9 Position */
\r
6669 #define PORT2_PDISC_PDIS9_Msk (0x01UL << PORT2_PDISC_PDIS9_Pos) /*!< PORT2 PDISC: PDIS9 Mask */
\r
6670 #define PORT2_PDISC_PDIS10_Pos 10 /*!< PORT2 PDISC: PDIS10 Position */
\r
6671 #define PORT2_PDISC_PDIS10_Msk (0x01UL << PORT2_PDISC_PDIS10_Pos) /*!< PORT2 PDISC: PDIS10 Mask */
\r
6672 #define PORT2_PDISC_PDIS11_Pos 11 /*!< PORT2 PDISC: PDIS11 Position */
\r
6673 #define PORT2_PDISC_PDIS11_Msk (0x01UL << PORT2_PDISC_PDIS11_Pos) /*!< PORT2 PDISC: PDIS11 Mask */
\r
6675 /* ---------------------------------- PORT2_PPS --------------------------------- */
\r
6676 #define PORT2_PPS_PPS0_Pos 0 /*!< PORT2 PPS: PPS0 Position */
\r
6677 #define PORT2_PPS_PPS0_Msk (0x01UL << PORT2_PPS_PPS0_Pos) /*!< PORT2 PPS: PPS0 Mask */
\r
6678 #define PORT2_PPS_PPS1_Pos 1 /*!< PORT2 PPS: PPS1 Position */
\r
6679 #define PORT2_PPS_PPS1_Msk (0x01UL << PORT2_PPS_PPS1_Pos) /*!< PORT2 PPS: PPS1 Mask */
\r
6680 #define PORT2_PPS_PPS2_Pos 2 /*!< PORT2 PPS: PPS2 Position */
\r
6681 #define PORT2_PPS_PPS2_Msk (0x01UL << PORT2_PPS_PPS2_Pos) /*!< PORT2 PPS: PPS2 Mask */
\r
6682 #define PORT2_PPS_PPS3_Pos 3 /*!< PORT2 PPS: PPS3 Position */
\r
6683 #define PORT2_PPS_PPS3_Msk (0x01UL << PORT2_PPS_PPS3_Pos) /*!< PORT2 PPS: PPS3 Mask */
\r
6684 #define PORT2_PPS_PPS4_Pos 4 /*!< PORT2 PPS: PPS4 Position */
\r
6685 #define PORT2_PPS_PPS4_Msk (0x01UL << PORT2_PPS_PPS4_Pos) /*!< PORT2 PPS: PPS4 Mask */
\r
6686 #define PORT2_PPS_PPS5_Pos 5 /*!< PORT2 PPS: PPS5 Position */
\r
6687 #define PORT2_PPS_PPS5_Msk (0x01UL << PORT2_PPS_PPS5_Pos) /*!< PORT2 PPS: PPS5 Mask */
\r
6688 #define PORT2_PPS_PPS6_Pos 6 /*!< PORT2 PPS: PPS6 Position */
\r
6689 #define PORT2_PPS_PPS6_Msk (0x01UL << PORT2_PPS_PPS6_Pos) /*!< PORT2 PPS: PPS6 Mask */
\r
6690 #define PORT2_PPS_PPS7_Pos 7 /*!< PORT2 PPS: PPS7 Position */
\r
6691 #define PORT2_PPS_PPS7_Msk (0x01UL << PORT2_PPS_PPS7_Pos) /*!< PORT2 PPS: PPS7 Mask */
\r
6692 #define PORT2_PPS_PPS8_Pos 8 /*!< PORT2 PPS: PPS8 Position */
\r
6693 #define PORT2_PPS_PPS8_Msk (0x01UL << PORT2_PPS_PPS8_Pos) /*!< PORT2 PPS: PPS8 Mask */
\r
6694 #define PORT2_PPS_PPS9_Pos 9 /*!< PORT2 PPS: PPS9 Position */
\r
6695 #define PORT2_PPS_PPS9_Msk (0x01UL << PORT2_PPS_PPS9_Pos) /*!< PORT2 PPS: PPS9 Mask */
\r
6696 #define PORT2_PPS_PPS10_Pos 10 /*!< PORT2 PPS: PPS10 Position */
\r
6697 #define PORT2_PPS_PPS10_Msk (0x01UL << PORT2_PPS_PPS10_Pos) /*!< PORT2 PPS: PPS10 Mask */
\r
6698 #define PORT2_PPS_PPS11_Pos 11 /*!< PORT2 PPS: PPS11 Position */
\r
6699 #define PORT2_PPS_PPS11_Msk (0x01UL << PORT2_PPS_PPS11_Pos) /*!< PORT2 PPS: PPS11 Mask */
\r
6701 /* --------------------------------- PORT2_HWSEL -------------------------------- */
\r
6702 #define PORT2_HWSEL_HW0_Pos 0 /*!< PORT2 HWSEL: HW0 Position */
\r
6703 #define PORT2_HWSEL_HW0_Msk (0x03UL << PORT2_HWSEL_HW0_Pos) /*!< PORT2 HWSEL: HW0 Mask */
\r
6704 #define PORT2_HWSEL_HW1_Pos 2 /*!< PORT2 HWSEL: HW1 Position */
\r
6705 #define PORT2_HWSEL_HW1_Msk (0x03UL << PORT2_HWSEL_HW1_Pos) /*!< PORT2 HWSEL: HW1 Mask */
\r
6706 #define PORT2_HWSEL_HW2_Pos 4 /*!< PORT2 HWSEL: HW2 Position */
\r
6707 #define PORT2_HWSEL_HW2_Msk (0x03UL << PORT2_HWSEL_HW2_Pos) /*!< PORT2 HWSEL: HW2 Mask */
\r
6708 #define PORT2_HWSEL_HW3_Pos 6 /*!< PORT2 HWSEL: HW3 Position */
\r
6709 #define PORT2_HWSEL_HW3_Msk (0x03UL << PORT2_HWSEL_HW3_Pos) /*!< PORT2 HWSEL: HW3 Mask */
\r
6710 #define PORT2_HWSEL_HW4_Pos 8 /*!< PORT2 HWSEL: HW4 Position */
\r
6711 #define PORT2_HWSEL_HW4_Msk (0x03UL << PORT2_HWSEL_HW4_Pos) /*!< PORT2 HWSEL: HW4 Mask */
\r
6712 #define PORT2_HWSEL_HW5_Pos 10 /*!< PORT2 HWSEL: HW5 Position */
\r
6713 #define PORT2_HWSEL_HW5_Msk (0x03UL << PORT2_HWSEL_HW5_Pos) /*!< PORT2 HWSEL: HW5 Mask */
\r
6714 #define PORT2_HWSEL_HW6_Pos 12 /*!< PORT2 HWSEL: HW6 Position */
\r
6715 #define PORT2_HWSEL_HW6_Msk (0x03UL << PORT2_HWSEL_HW6_Pos) /*!< PORT2 HWSEL: HW6 Mask */
\r
6716 #define PORT2_HWSEL_HW7_Pos 14 /*!< PORT2 HWSEL: HW7 Position */
\r
6717 #define PORT2_HWSEL_HW7_Msk (0x03UL << PORT2_HWSEL_HW7_Pos) /*!< PORT2 HWSEL: HW7 Mask */
\r
6718 #define PORT2_HWSEL_HW8_Pos 16 /*!< PORT2 HWSEL: HW8 Position */
\r
6719 #define PORT2_HWSEL_HW8_Msk (0x03UL << PORT2_HWSEL_HW8_Pos) /*!< PORT2 HWSEL: HW8 Mask */
\r
6720 #define PORT2_HWSEL_HW9_Pos 18 /*!< PORT2 HWSEL: HW9 Position */
\r
6721 #define PORT2_HWSEL_HW9_Msk (0x03UL << PORT2_HWSEL_HW9_Pos) /*!< PORT2 HWSEL: HW9 Mask */
\r
6722 #define PORT2_HWSEL_HW10_Pos 20 /*!< PORT2 HWSEL: HW10 Position */
\r
6723 #define PORT2_HWSEL_HW10_Msk (0x03UL << PORT2_HWSEL_HW10_Pos) /*!< PORT2 HWSEL: HW10 Mask */
\r
6724 #define PORT2_HWSEL_HW11_Pos 22 /*!< PORT2 HWSEL: HW11 Position */
\r
6725 #define PORT2_HWSEL_HW11_Msk (0x03UL << PORT2_HWSEL_HW11_Pos) /*!< PORT2 HWSEL: HW11 Mask */
\r
6729 /* ================================================================================ */
\r
6730 /* ================ Peripheral memory map ================ */
\r
6731 /* ================================================================================ */
\r
6733 #define PPB_BASE 0xE000E000UL
\r
6734 #define ERU0_BASE 0x40010600UL
\r
6735 #define MATH_BASE 0x40030000UL
\r
6736 #define PAU_BASE 0x40000000UL
\r
6737 #define NVM_BASE 0x40050000UL
\r
6738 #define WDT_BASE 0x40020000UL
\r
6739 #define RTC_BASE 0x40010A00UL
\r
6740 #define PRNG_BASE 0x48020000UL
\r
6741 #define USIC0_BASE 0x48000008UL
\r
6742 #define USIC0_CH0_BASE 0x48000000UL
\r
6743 #define USIC0_CH1_BASE 0x48000200UL
\r
6744 #define SCU_GENERAL_BASE 0x40010000UL
\r
6745 #define SCU_INTERRUPT_BASE 0x40010038UL
\r
6746 #define SCU_POWER_BASE 0x40010200UL
\r
6747 #define SCU_CLK_BASE 0x40010300UL
\r
6748 #define SCU_RESET_BASE 0x40010400UL
\r
6749 #define COMPARATOR_BASE 0x40010500UL
\r
6750 #define SCU_ANALOG_BASE 0x40011000UL
\r
6751 #define CCU40_BASE 0x48040000UL
\r
6752 #define CCU40_CC40_BASE 0x48040100UL
\r
6753 #define CCU40_CC41_BASE 0x48040200UL
\r
6754 #define CCU40_CC42_BASE 0x48040300UL
\r
6755 #define CCU40_CC43_BASE 0x48040400UL
\r
6756 #define CCU80_BASE 0x50000000UL
\r
6757 #define CCU80_CC80_BASE 0x50000100UL
\r
6758 #define CCU80_CC81_BASE 0x50000200UL
\r
6759 #define CCU80_CC82_BASE 0x50000300UL
\r
6760 #define CCU80_CC83_BASE 0x50000400UL
\r
6761 #define POSIF0_BASE 0x50010000UL
\r
6762 #define VADC_BASE 0x48030000UL
\r
6763 #define VADC_G0_BASE 0x48030400UL
\r
6764 #define VADC_G1_BASE 0x48030800UL
\r
6765 #define SHS0_BASE 0x48034000UL
\r
6766 #define BCCU0_BASE 0x50030000UL
\r
6767 #define BCCU0_CH0_BASE 0x5003003CUL
\r
6768 #define BCCU0_CH1_BASE 0x50030050UL
\r
6769 #define BCCU0_CH2_BASE 0x50030064UL
\r
6770 #define BCCU0_CH3_BASE 0x50030078UL
\r
6771 #define BCCU0_CH4_BASE 0x5003008CUL
\r
6772 #define BCCU0_CH5_BASE 0x500300A0UL
\r
6773 #define BCCU0_CH6_BASE 0x500300B4UL
\r
6774 #define BCCU0_CH7_BASE 0x500300C8UL
\r
6775 #define BCCU0_CH8_BASE 0x500300DCUL
\r
6776 #define BCCU0_DE0_BASE 0x5003017CUL
\r
6777 #define BCCU0_DE1_BASE 0x50030188UL
\r
6778 #define BCCU0_DE2_BASE 0x50030194UL
\r
6779 #define PORT0_BASE 0x40040000UL
\r
6780 #define PORT1_BASE 0x40040100UL
\r
6781 #define PORT2_BASE 0x40040200UL
\r
6784 /* ================================================================================ */
\r
6785 /* ================ Peripheral declaration ================ */
\r
6786 /* ================================================================================ */
\r
6788 #define PPB ((PPB_Type *) PPB_BASE)
\r
6789 #define ERU0 ((ERU_GLOBAL_TypeDef *) ERU0_BASE)
\r
6790 #define MATH ((MATH_Type *) MATH_BASE)
\r
6791 #define PAU ((PAU_Type *) PAU_BASE)
\r
6792 #define NVM ((NVM_Type *) NVM_BASE)
\r
6793 #define WDT ((WDT_GLOBAL_TypeDef *) WDT_BASE)
\r
6794 #define RTC ((RTC_GLOBAL_TypeDef *) RTC_BASE)
\r
6795 #define PRNG ((PRNG_Type *) PRNG_BASE)
\r
6796 #define USIC0 ((USIC_GLOBAL_TypeDef *) USIC0_BASE)
\r
6797 #define USIC0_CH0 ((USIC_CH_TypeDef *) USIC0_CH0_BASE)
\r
6798 #define USIC0_CH1 ((USIC_CH_TypeDef *) USIC0_CH1_BASE)
\r
6799 #define SCU_GENERAL ((SCU_GENERAL_Type *) SCU_GENERAL_BASE)
\r
6800 #define SCU_INTERRUPT ((SCU_INTERRUPT_TypeDef *) SCU_INTERRUPT_BASE)
\r
6801 #define SCU_POWER ((SCU_POWER_Type *) SCU_POWER_BASE)
\r
6802 #define SCU_CLK ((SCU_CLK_TypeDef *) SCU_CLK_BASE)
\r
6803 #define SCU_RESET ((SCU_RESET_Type *) SCU_RESET_BASE)
\r
6804 #define COMPARATOR ((COMPARATOR_Type *) COMPARATOR_BASE)
\r
6805 #define SCU_ANALOG ((SCU_ANALOG_Type *) SCU_ANALOG_BASE)
\r
6806 #define CCU40 ((CCU4_GLOBAL_TypeDef *) CCU40_BASE)
\r
6807 #define CCU40_CC40 ((CCU4_CC4_TypeDef *) CCU40_CC40_BASE)
\r
6808 #define CCU40_CC41 ((CCU4_CC4_TypeDef *) CCU40_CC41_BASE)
\r
6809 #define CCU40_CC42 ((CCU4_CC4_TypeDef *) CCU40_CC42_BASE)
\r
6810 #define CCU40_CC43 ((CCU4_CC4_TypeDef *) CCU40_CC43_BASE)
\r
6811 #define CCU80 ((CCU8_GLOBAL_TypeDef *) CCU80_BASE)
\r
6812 #define CCU80_CC80 ((CCU8_CC8_TypeDef *) CCU80_CC80_BASE)
\r
6813 #define CCU80_CC81 ((CCU8_CC8_TypeDef *) CCU80_CC81_BASE)
\r
6814 #define CCU80_CC82 ((CCU8_CC8_TypeDef *) CCU80_CC82_BASE)
\r
6815 #define CCU80_CC83 ((CCU8_CC8_TypeDef *) CCU80_CC83_BASE)
\r
6816 #define POSIF0 ((POSIF_GLOBAL_TypeDef *) POSIF0_BASE)
\r
6817 #define VADC ((VADC_GLOBAL_TypeDef *) VADC_BASE)
\r
6818 #define VADC_G0 ((VADC_G_TypeDef *) VADC_G0_BASE)
\r
6819 #define VADC_G1 ((VADC_G_TypeDef *) VADC_G1_BASE)
\r
6820 #define SHS0 ((SHS_Type *) SHS0_BASE)
\r
6821 #define BCCU0 ((BCCU_Type *) BCCU0_BASE)
\r
6822 #define BCCU0_CH0 ((BCCU_CH_Type *) BCCU0_CH0_BASE)
\r
6823 #define BCCU0_CH1 ((BCCU_CH_Type *) BCCU0_CH1_BASE)
\r
6824 #define BCCU0_CH2 ((BCCU_CH_Type *) BCCU0_CH2_BASE)
\r
6825 #define BCCU0_CH3 ((BCCU_CH_Type *) BCCU0_CH3_BASE)
\r
6826 #define BCCU0_CH4 ((BCCU_CH_Type *) BCCU0_CH4_BASE)
\r
6827 #define BCCU0_CH5 ((BCCU_CH_Type *) BCCU0_CH5_BASE)
\r
6828 #define BCCU0_CH6 ((BCCU_CH_Type *) BCCU0_CH6_BASE)
\r
6829 #define BCCU0_CH7 ((BCCU_CH_Type *) BCCU0_CH7_BASE)
\r
6830 #define BCCU0_CH8 ((BCCU_CH_Type *) BCCU0_CH8_BASE)
\r
6831 #define BCCU0_DE0 ((BCCU_DE_Type *) BCCU0_DE0_BASE)
\r
6832 #define BCCU0_DE1 ((BCCU_DE_Type *) BCCU0_DE1_BASE)
\r
6833 #define BCCU0_DE2 ((BCCU_DE_Type *) BCCU0_DE2_BASE)
\r
6834 #define PORT0 ((PORT0_Type *) PORT0_BASE)
\r
6835 #define PORT1 ((PORT1_Type *) PORT1_BASE)
\r
6836 #define PORT2 ((PORT2_Type *) PORT2_BASE)
\r
6839 /** @} */ /* End of group Device_Peripheral_Registers */
\r
6840 /** @} */ /* End of group XMC1300 */
\r
6841 /** @} */ /* End of group Infineon */
\r
6843 #ifdef __cplusplus
\r
6848 #endif /* XMC1300_H */
\r
projects / freertos / blob