git.sur5r.net Git - freertos/blob - FreeRTOS/Demo/CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC/Keil_Specific/startup_XMC1300.s

   1 ;*****************************************************************************/\r
   2 ; * @file     startup_XMC1300.s\r
   3 ; * @brief    CMSIS Cortex-M4 Core Device Startup File for\r
   4 ; *           Infineon XMC1300 Device Series\r
   5 ; * @version  V1.00\r
   6 ; * @date     21. Jan. 2013\r
   7 ; *\r
   8 ; * @note\r
   9 ; * Copyright (C) 2009-2013 ARM Limited. All rights reserved.\r
  10 ; *\r
  11 ; * @par\r
  12 ; * ARM Limited (ARM) is supplying this software for use with Cortex-M\r
  13 ; * processor based microcontrollers.  This file can be freely distributed\r
  14 ; * within development tools that are supporting such ARM based processors.\r
  15 ; *\r
  16 ; * @par\r
  17 ; * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
  18 ; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
  19 ; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
  20 ; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
  21 ; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
  22 ; *\r
  23 ; ******************************************************************************/\r
  24 \r
  25 \r
  26 ;*  <<< Use Configuration Wizard in Context Menu >>>\r
  27 \r
  28 ; Amount of memory (in bytes) allocated for Stack\r
  29 ; Tailor this value to your application needs\r
  30 ; <h> Stack Configuration\r
  31 ;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\r
  32 ; </h>\r
  33 \r
  34 Stack_Size      EQU     0x00000400\r
  35 \r
  36                 AREA    STACK, NOINIT, READWRITE, ALIGN=3\r
  37 Stack_Mem       SPACE   Stack_Size\r
  38 __initial_sp\r
  39 \r
  40 \r
  41 ; <h> Heap Configuration\r
  42 ;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\r
  43 ; </h>\r
  44 \r
  45 Heap_Size       EQU     0x00000000\r
  46 \r
  47                 AREA    HEAP, NOINIT, READWRITE, ALIGN=3\r
  48 __heap_base\r
  49 Heap_Mem        SPACE   Heap_Size\r
  50 __heap_limit\r
  51 \r
  52 ; <h> Clock system handling by SSW\r
  53 ;   <h> CLK_VAL1 Configuration\r
  54 ;     <o0.0..7>    FDIV Fractional Divider Selection\r
  55 ;     <o0.8..15>   IDIV Divider Selection\r
  56 ;                     <0=> Divider is bypassed\r
  57 ;                     <1=> MCLK = 32 MHz\r
  58 ;                     <2=> MCLK = 16 MHz\r
  59 ;                     <3=> MCLK = 10.67 MHz\r
  60 ;                     <4=> MCLK = 8 MHz\r
  61 ;                     <254=> MCLK = 126 kHz\r
  62 ;                     <255=> MCLK = 125.5 kHz\r
  63 ;     <o0.16>      PCLKSEL PCLK Clock Select\r
  64 ;                     <0=> PCLK = MCLK\r
  65 ;                     <1=> PCLK = 2 x MCLK\r
  66 ;     <o0.17..19>  RTCCLKSEL RTC Clock Select\r
  67 ;                     <0=> 32.768kHz standby clock\r
  68 ;                     <1=> 32.768kHz external clock from ERU0.IOUT0\r
  69 ;                     <2=> 32.768kHz external clock from ACMP0.OUT\r
  70 ;                     <3=> 32.768kHz external clock from ACMP1.OUT\r
  71 ;                     <4=> 32.768kHz external clock from ACMP2.OUT\r
  72 ;                     <5=> Reserved\r
  73 ;                     <6=> Reserved\r
  74 ;                     <7=> Reserved\r
  75 ;     <o0.31>      do not move CLK_VAL1 to SCU_CLKCR[0..19]\r
  76 ;   </h>\r
  77 CLK_VAL1_Val    EQU     0x00000100      ; 0xF0000000\r
  78 \r
  79 ;   <h> CLK_VAL2 Configuration\r
  80 ;     <o0.0>    disable VADC and SHS Gating\r
  81 ;     <o0.1>    disable CCU80 Gating\r
  82 ;     <o0.2>    disable CCU40 Gating\r
  83 ;     <o0.3>    disable USIC0 Gating\r
  84 ;     <o0.4>    disable BCCU0 Gating\r
  85 ;     <o0.5>    disable LEDTS0 Gating\r
  86 ;     <o0.6>    disable LEDTS1 Gating\r
  87 ;     <o0.7>    disable POSIF0 Gating\r
  88 ;     <o0.8>    disable MATH Gating\r
  89 ;     <o0.9>    disable WDT Gating\r
  90 ;     <o0.10>   disable RTC Gating\r
  91 ;     <o0.31>   do not move CLK_VAL2 to SCU_CGATCLR0[0..10]\r
  92 ;   </h>\r
  93 CLK_VAL2_Val    EQU     0x00000000      ; 0xF0000000\r
  94 ; </h>\r
  95 \r
  96                 PRESERVE8\r
  97                 THUMB\r
  98 \r
  99 ;* ================== START OF VECTOR TABLE DEFINITION ====================== */\r
 100 ;* Vector Table Mapped to Address 0 at Reset\r
 101                 AREA    RESET, DATA, READONLY\r
 102                 EXPORT  __Vectors\r
 103                 EXPORT  __Vectors_End\r
 104                 EXPORT  __Vectors_Size\r
 105 \r
 106 \r
 107 \r
 108 __Vectors\r
 109     DCD   __initial_sp                ;* Top of Stack\r
 110     DCD   Reset_Handler               ;* Reset Handler\r
 111     DCD   0                           ;* Not used\r
 112     DCD   0                           ;* Not Used\r
 113     DCD   CLK_VAL1_Val                ;* CLK_VAL1\r
 114     DCD   CLK_VAL2_Val                ;* CLK_VAL2\r
 115 __Vectors_End\r
 116 \r
 117 __Vectors_Size  EQU  __Vectors_End - __Vectors\r
 118 \r
 119 ;* ================== END OF VECTOR TABLE DEFINITION ======================== */\r
 120 \r
 121 \r
 122 ;* ================== START OF VECTOR ROUTINES ============================== */\r
 123                 AREA    |.text|, CODE, READONLY\r
 124 \r
 125 ;* Reset Handler\r
 126 Reset_Handler    PROC\r
 127                  EXPORT  Reset_Handler             [WEAK]\r
 128         IMPORT  __main\r
 129         IMPORT  SystemInit\r
 130 \r
 131         ;* C routines are likely to be called. Setup the stack now\r
 132         LDR     R0, =__initial_sp\r
 133         MOV     SP, R0\r
 134 \r
 135        ; Following code initializes the Veneers at address 0x20000000 with a "branch to itself"\r
 136        ; The real veneers will be copied later from the scatter loader before reaching main.\r
 137        ; This init code should handle an exception before the real veneers are copied.\r
 138 SRAM_BASE            EQU     0x20000000\r
 139 VENEER_INIT_CODE     EQU     0xE7FEBF00             ; NOP, B .\r
 140 \r
 141         LDR     R1, =SRAM_BASE\r
 142         LDR     R2, =VENEER_INIT_CODE                \r
 143         MOVS    R0, #48                     ; Veneer 0..47\r
 144 Init_Veneers\r
 145         STR     R2, [R1]\r
 146         ADDS    R1, #4\r
 147         SUBS    R0, R0, #1\r
 148         BNE     Init_Veneers\r
 149 \r
 150 \r
 151         LDR     R0, =SystemInit\r
 152         BLX     R0\r
 153 \r
 154 \r
 155         ; SystemInit_DAVE3() is provided by DAVE3 code generation engine. It is\r
 156         ; weakly defined here though for a potential override.\r
 157 \r
 158         LDR     R0, = SystemInit_DAVE3\r
 159         BLX     R0\r
 160 \r
 161 \r
 162         LDR     R0, =__main\r
 163         BX      R0\r
 164 \r
 165 \r
 166         ALIGN\r
 167         ENDP\r
 168 \r
 169 ;* ========================================================================== */\r
 170 \r
 171 \r
 172 \r
 173 ;* ========== START OF EXCEPTION HANDLER DEFINITION ========================= */\r
 174 ;* Default exception Handlers - Users may override this default functionality\r
 175 \r
 176 NMI_Handler     PROC\r
 177                 EXPORT  NMI_Handler                   [WEAK]\r
 178                 B       .\r
 179                 ENDP\r
 180 HardFault_Handler\\r
 181                 PROC\r
 182                 EXPORT  HardFault_Handler             [WEAK]\r
 183                 B       .\r
 184                 ENDP\r
 185 SVC_Handler\\r
 186                 PROC\r
 187                 EXPORT  SVC_Handler                   [WEAK]\r
 188                 B       .\r
 189                 ENDP\r
 190 PendSV_Handler\\r
 191                 PROC\r
 192                 EXPORT  PendSV_Handler                [WEAK]\r
 193                 B       .\r
 194                 ENDP\r
 195 SysTick_Handler\\r
 196                 PROC\r
 197                 EXPORT  SysTick_Handler               [WEAK]\r
 198                 B       .\r
 199                 ENDP\r
 200 \r
 201 ;* ============= END OF EXCEPTION HANDLER DEFINITION ======================== */\r
 202 \r
 203 \r
 204 ;* ============= START OF INTERRUPT HANDLER DEFINITION ====================== */\r
 205 ;* IRQ Handlers\r
 206 \r
 207 Default_Handler PROC\r
 208                EXPORT     SCU_0_IRQHandler            [WEAK]\r
 209                EXPORT     SCU_1_IRQHandler            [WEAK]\r
 210                EXPORT     SCU_2_IRQHandler            [WEAK]\r
 211                EXPORT     ERU0_0_IRQHandler           [WEAK]\r
 212                EXPORT     ERU0_1_IRQHandler           [WEAK]\r
 213                EXPORT     ERU0_2_IRQHandler           [WEAK]\r
 214                EXPORT     ERU0_3_IRQHandler           [WEAK]\r
 215                EXPORT     MATH0_0_IRQHandler          [WEAK]\r
 216                EXPORT     USIC0_0_IRQHandler          [WEAK]\r
 217                EXPORT     USIC0_1_IRQHandler          [WEAK]\r
 218                EXPORT     USIC0_2_IRQHandler          [WEAK]\r
 219                EXPORT     USIC0_3_IRQHandler          [WEAK]\r
 220                EXPORT     USIC0_4_IRQHandler          [WEAK]\r
 221                EXPORT     USIC0_5_IRQHandler          [WEAK]\r
 222                EXPORT     VADC0_C0_0_IRQHandler       [WEAK]\r
 223                EXPORT     VADC0_C0_1_IRQHandler       [WEAK]\r
 224                EXPORT     VADC0_G0_0_IRQHandler       [WEAK]\r
 225                EXPORT     VADC0_G0_1_IRQHandler       [WEAK]\r
 226                EXPORT     VADC0_G1_0_IRQHandler       [WEAK]\r
 227                EXPORT     VADC0_G1_1_IRQHandler       [WEAK]\r
 228                EXPORT     CCU40_0_IRQHandler          [WEAK]\r
 229                EXPORT     CCU40_1_IRQHandler          [WEAK]\r
 230                EXPORT     CCU40_2_IRQHandler          [WEAK]\r
 231                EXPORT     CCU40_3_IRQHandler          [WEAK]\r
 232                EXPORT     CCU80_0_IRQHandler          [WEAK]\r
 233                EXPORT     CCU80_1_IRQHandler          [WEAK]\r
 234                EXPORT     POSIF0_0_IRQHandler         [WEAK]\r
 235                EXPORT     POSIF0_1_IRQHandler         [WEAK]\r
 236                EXPORT     LEDTS0_0_IRQHandler         [WEAK]\r
 237                EXPORT     LEDTS1_0_IRQHandler         [WEAK]\r
 238                EXPORT     BCCU0_0_IRQHandler          [WEAK]\r
 239 \r
 240 SCU_0_IRQHandler\r
 241 SCU_1_IRQHandler\r
 242 SCU_2_IRQHandler\r
 243 ERU0_0_IRQHandler\r
 244 ERU0_1_IRQHandler\r
 245 ERU0_2_IRQHandler\r
 246 ERU0_3_IRQHandler\r
 247 MATH0_0_IRQHandler\r
 248 USIC0_0_IRQHandler\r
 249 USIC0_1_IRQHandler\r
 250 USIC0_2_IRQHandler\r
 251 USIC0_3_IRQHandler\r
 252 USIC0_4_IRQHandler\r
 253 USIC0_5_IRQHandler\r
 254 VADC0_C0_0_IRQHandler\r
 255 VADC0_C0_1_IRQHandler\r
 256 VADC0_G0_0_IRQHandler\r
 257 VADC0_G0_1_IRQHandler\r
 258 VADC0_G1_0_IRQHandler\r
 259 VADC0_G1_1_IRQHandler\r
 260 CCU40_0_IRQHandler\r
 261 CCU40_1_IRQHandler\r
 262 CCU40_2_IRQHandler\r
 263 CCU40_3_IRQHandler\r
 264 CCU80_0_IRQHandler\r
 265 CCU80_1_IRQHandler\r
 266 POSIF0_0_IRQHandler\r
 267 POSIF0_1_IRQHandler\r
 268 LEDTS0_0_IRQHandler\r
 269 LEDTS1_0_IRQHandler\r
 270 BCCU0_0_IRQHandler\r
 271 \r
 272                 B       .\r
 273 \r
 274                 ENDP\r
 275 \r
 276                 ALIGN\r
 277 \r
 278 ;* ============= END OF INTERRUPT HANDLER DEFINITION ======================== */\r
 279 \r
 280 ;*  Definition of the default weak SystemInit_DAVE3 function.\r
 281 ;*  This function will be called by the CMSIS SystemInit function.\r
 282 ;*  If DAVE3 requires an extended SystemInit it will create its own SystemInit_DAVE3\r
 283 ;*  which will overule this weak definition\r
 284 SystemInit_DAVE3    PROC\r
 285                   EXPORT  SystemInit_DAVE3             [WEAK]\r
 286                   NOP\r
 287                   BX LR\r
 288         ENDP\r
 289 \r
 290 ;*  Definition of the default weak DAVE3 function for clock App usage.\r
 291 ;*  AllowClkInitByStartup Handler */\r
 292 AllowClkInitByStartup    PROC\r
 293                   EXPORT  AllowClkInitByStartup        [WEAK]\r
 294                   MOVS R0,#1\r
 295                   BX LR\r
 296         ENDP\r
 297 \r
 298 \r
 299 ;*******************************************************************************\r
 300 ; User Stack and Heap initialization\r
 301 ;*******************************************************************************\r
 302                  IF      :DEF:__MICROLIB\r
 303 \r
 304                  EXPORT  __initial_sp\r
 305                  EXPORT  __heap_base\r
 306                  EXPORT  __heap_limit\r
 307 \r
 308                  ELSE\r
 309 \r
 310                  IMPORT  __use_two_region_memory\r
 311                  EXPORT  __user_initial_stackheap\r
 312 \r
 313 __user_initial_stackheap\r
 314 \r
 315                  LDR     R0, =  Heap_Mem\r
 316                  LDR     R1, =(Stack_Mem + Stack_Size)\r
 317                  LDR     R2, = (Heap_Mem +  Heap_Size)\r
 318                  LDR     R3, = Stack_Mem\r
 319                  BX      LR\r
 320 \r
 321                  ALIGN\r
 322 \r
 323                  ENDIF\r
 324 \r
 325 \r
 326 ;* ================== START OF INTERRUPT HANDLER VENEERS ==================== */\r
 327 ; Veneers are located to fix SRAM Address 0x2000'0000\r
 328                 AREA    |.ARM.__at_0x20000000|, CODE, READWRITE\r
 329 \r
 330 ; Each Veneer has exactly a lengs of 4 Byte\r
 331 \r
 332                 MACRO\r
 333                 STAYHERE $IrqNumber\r
 334                 LDR  R0, =$IrqNumber\r
 335                 B    .\r
 336                 MEND\r
 337 \r
 338                 MACRO\r
 339                 JUMPTO $Handler\r
 340                 LDR  R0, =$Handler\r
 341                 BX   R0\r
 342                 MEND\r
 343 \r
 344                 STAYHERE 0x0                          ;* Reserved\r
 345                 STAYHERE 0x1                          ;* Reserved \r
 346                 STAYHERE 0x2                          ;* Reserved \r
 347                 JUMPTO   HardFault_Handler            ;* HardFault Veneer  \r
 348                 STAYHERE 0x4                          ;* Reserved \r
 349                 STAYHERE 0x5                          ;* Reserved \r
 350                 STAYHERE 0x6                          ;* Reserved \r
 351                 STAYHERE 0x7                          ;* Reserved \r
 352                 STAYHERE 0x8                          ;* Reserved \r
 353                 STAYHERE 0x9                          ;* Reserved \r
 354                 STAYHERE 0xA                          ;* Reserved\r
 355                 JUMPTO   SVC_Handler                  ;* SVC Veneer        \r
 356                 STAYHERE 0xC                          ;* Reserved\r
 357                 STAYHERE 0xD                          ;* Reserved\r
 358                 JUMPTO   PendSV_Handler               ;* PendSV Veneer     \r
 359                 JUMPTO   SysTick_Handler              ;* SysTick Veneer    \r
 360                 JUMPTO   SCU_0_IRQHandler             ;* SCU_0 Veneer      \r
 361                 JUMPTO   SCU_1_IRQHandler             ;* SCU_1 Veneer      \r
 362                 JUMPTO   SCU_2_IRQHandler             ;* SCU_2 Veneer      \r
 363                 JUMPTO   ERU0_0_IRQHandler            ;* SCU_3 Veneer      \r
 364                 JUMPTO   ERU0_1_IRQHandler            ;* SCU_4 Veneer      \r
 365                 JUMPTO   ERU0_2_IRQHandler            ;* SCU_5 Veneer      \r
 366                 JUMPTO   ERU0_3_IRQHandler            ;* SCU_6 Veneer      \r
 367                 JUMPTO   MATH0_0_IRQHandler           ;* SCU_7 Veneer      \r
 368                 STAYHERE 0x18                         ;* Reserved\r
 369                 JUMPTO   USIC0_0_IRQHandler           ;* USIC0_0 Veneer    \r
 370                 JUMPTO   USIC0_1_IRQHandler           ;* USIC0_1 Veneer    \r
 371                 JUMPTO   USIC0_2_IRQHandler           ;* USIC0_2 Veneer    \r
 372                 JUMPTO   USIC0_3_IRQHandler           ;* USIC0_3 Veneer    \r
 373                 JUMPTO   USIC0_4_IRQHandler           ;* USIC0_4 Veneer    \r
 374                 JUMPTO   LEDTS0_0_IRQHandler          ;* USIC0_5 Veneer    \r
 375                 JUMPTO   VADC0_C0_0_IRQHandler        ;* VADC0_C0_0 Veneer \r
 376                 JUMPTO   VADC0_C0_1_IRQHandler        ;* VADC0_C0_1 Veneer \r
 377                 JUMPTO   VADC0_G0_0_IRQHandler        ;* VADC0_G0_0 Veneer \r
 378                 JUMPTO   VADC0_G0_1_IRQHandler        ;* VADC0_G0_1 Veneer \r
 379                 JUMPTO   VADC0_G1_0_IRQHandler        ;* VADC0_G1_0 Veneer \r
 380                 JUMPTO   VADC0_G1_1_IRQHandler        ;* VADC0_G1_1 Veneer \r
 381                 JUMPTO   CCU40_0_IRQHandler           ;* CCU40_0 Veneer    \r
 382                 JUMPTO   CCU40_1_IRQHandler           ;* CCU40_1 Veneer    \r
 383                 JUMPTO   CCU40_2_IRQHandler           ;* CCU40_2 Veneer    \r
 384                 JUMPTO   CCU40_3_IRQHandler           ;* CCU40_3 Veneer    \r
 385                 JUMPTO   CCU80_0_IRQHandler           ;* CCU80_0 Veneer    \r
 386                 JUMPTO   CCU80_1_IRQHandler           ;* CCU80_1 Veneer    \r
 387                 JUMPTO   POSIF0_0_IRQHandler          ;* POSIF0_0 Veneer   \r
 388                 JUMPTO   POSIF0_1_IRQHandler          ;* POSIF0_1 Veneer   \r
 389                 JUMPTO   LEDTS0_0_IRQHandler          ;* LEDTS0_0 Veneer   \r
 390                 JUMPTO   LEDTS1_0_IRQHandler          ;* LEDTS1_0 Veneer   \r
 391                 JUMPTO   BCCU0_0_IRQHandler           ;* BCCU0_0 Veneer    \r
 392 \r
 393                 ALIGN\r
 394 \r
 395 ;* ================== END OF INTERRUPT HANDLER VENEERS ====================== */\r
 396 \r
 397                 END\r