2 /****************************************************************************************************//**
\r
5 * @brief CMSIS Cortex-M0 Peripheral Access Layer Header File for
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6 * XMC1100 from Infineon.
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8 * @version V1.0.6 (Reference Manual v1.0)
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9 * @date 26. March 2013
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11 * @note Generated with SVDConv V2.78b
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12 * from CMSIS SVD File 'XMC1100_Processed_SVD.xml' Version 1.0.6 (Reference Manual v1.0),
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13 *******************************************************************************************************/
\r
17 /** @addtogroup Infineon
\r
21 /** @addtogroup XMC1100
\r
33 /* ------------------------- Interrupt Number Definition ------------------------ */
\r
36 /* ------------------- Cortex-M0 Processor Exceptions Numbers ------------------- */
\r
37 Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */
\r
38 NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */
\r
39 HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */
\r
40 SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */
\r
41 DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */
\r
42 PendSV_IRQn = -2, /*!< 14 Pendable request for system service */
\r
43 SysTick_IRQn = -1, /*!< 15 System Tick Timer */
\r
44 /* --------------------- XMC1100 Specific Interrupt Numbers --------------------- */
\r
45 SCU_0_IRQn = 0, /*!< SCU SR0 Interrupt */
\r
46 SCU_1_IRQn = 1, /*!< SCU SR1 Interrupt */
\r
47 SCU_2_IRQn = 2, /*!< SCU SR2 Interrupt */
\r
48 ERU0_0_IRQn = 3, /*!< ERU0 SR0 Interrupt */
\r
49 ERU0_1_IRQn = 4, /*!< ERU0 SR1 Interrupt */
\r
50 ERU0_2_IRQn = 5, /*!< ERU0 SR2 Interrupt */
\r
51 ERU0_3_IRQn = 6, /*!< ERU0 SR3 Interrupt */
\r
53 USIC0_0_IRQn = 9, /*!< USIC SR0 Interrupt */
\r
54 USIC0_1_IRQn = 10, /*!< USIC SR1 Interrupt */
\r
55 USIC0_2_IRQn = 11, /*!< USIC SR2 Interrupt */
\r
56 USIC0_3_IRQn = 12, /*!< USIC SR3 Interrupt */
\r
57 USIC0_4_IRQn = 13, /*!< USIC SR4 Interrupt */
\r
58 USIC0_5_IRQn = 14, /*!< USIC SR5 Interrupt */
\r
60 VADC0_C0_0_IRQn = 15, /*!< VADC SR0 Interrupt */
\r
61 VADC0_C0_1_IRQn = 16, /*!< VADC SR1 Interrupt */
\r
63 CCU40_0_IRQn = 21, /*!< CCU40 SR0 Interrupt */
\r
64 CCU40_1_IRQn = 22, /*!< CCU40 SR1 Interrupt */
\r
65 CCU40_2_IRQn = 23, /*!< CCU40 SR2 Interrupt */
\r
66 CCU40_3_IRQn = 24, /*!< CCU40 SR3 Interrupt */
\r
71 /** @addtogroup Configuration_of_CMSIS
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76 /* ================================================================================ */
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77 /* ================ Processor and Core Peripheral Section ================ */
\r
78 /* ================================================================================ */
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80 /* ----------------Configuration of the Cortex-M0 Processor and Core Peripherals---------------- */
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81 #define __CM0_REV 0x0000 /*!< Cortex-M0 Core Revision */
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82 #define __MPU_PRESENT 0 /*!< MPU present or not */
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83 #define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */
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84 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
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85 /** @} */ /* End of group Configuration_of_CMSIS */
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87 #include <core_cm0.h> /*!< Cortex-M0 processor and core peripherals */
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88 #include "system_XMC1100.h" /*!< XMC1100 System */
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91 /* ================================================================================ */
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92 /* ================ Device Specific Peripheral Section ================ */
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93 /* ================================================================================ */
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94 /* Macro to modify desired bitfields of a register */
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95 #define WR_REG(reg, mask, pos, val) reg = (((uint32_t)val << pos) & \
\r
96 ((uint32_t)mask)) | \
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97 (reg & ((uint32_t)~((uint32_t)mask)))
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99 /* Macro to modify desired bitfields of a register */
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100 #define WR_REG_SIZE(reg, mask, pos, val, size) { \
\r
101 uint##size##_t VAL1 = (uint##size##_t)((uint##size##_t)val << pos); \
\r
102 uint##size##_t VAL2 = (uint##size##_t) (VAL1 & (uint##size##_t)mask); \
\r
103 uint##size##_t VAL3 = (uint##size##_t)~((uint##size##_t)mask); \
\r
104 uint##size##_t VAL4 = (uint##size##_t) ((uint##size##_t)reg & VAL3); \
\r
105 reg = (uint##size##_t) (VAL2 | VAL4);\
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108 /** Macro to read bitfields from a register */
\r
109 #define RD_REG(reg, mask, pos) (((uint32_t)reg & (uint32_t)mask) >> pos)
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111 /** Macro to read bitfields from a register */
\r
112 #define RD_REG_SIZE(reg, mask, pos,size) ((uint##size##_t)(((uint32_t)reg & \
\r
113 (uint32_t)mask) >> pos) )
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115 /** Macro to set a bit in register */
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116 #define SET_BIT(reg, pos) (reg |= ((uint32_t)1<<pos))
\r
118 /** Macro to clear a bit in register */
\r
119 #define CLR_BIT(reg, pos) (reg = reg & (uint32_t)(~((uint32_t)1<<pos)) )
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121 * ==========================================================================
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122 * ---------- Interrupt Handler Definition ----------------------------------
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123 * ==========================================================================
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125 #define IRQ_Hdlr_0 SCU_0_IRQHandler
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126 #define IRQ_Hdlr_1 SCU_1_IRQHandler
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127 #define IRQ_Hdlr_2 SCU_2_IRQHandler
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128 #define IRQ_Hdlr_3 ERU0_0_IRQHandler
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129 #define IRQ_Hdlr_4 ERU0_1_IRQHandler
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130 #define IRQ_Hdlr_5 ERU0_2_IRQHandler
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131 #define IRQ_Hdlr_6 ERU0_3_IRQHandler
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133 #define IRQ_Hdlr_9 USIC0_0_IRQHandler
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134 #define IRQ_Hdlr_10 USIC0_1_IRQHandler
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135 #define IRQ_Hdlr_11 USIC0_2_IRQHandler
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136 #define IRQ_Hdlr_12 USIC0_3_IRQHandler
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137 #define IRQ_Hdlr_13 USIC0_4_IRQHandler
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138 #define IRQ_Hdlr_14 USIC0_5_IRQHandler
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139 #define IRQ_Hdlr_15 VADC0_C0_0_IRQHandler
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140 #define IRQ_Hdlr_16 VADC0_C0_1_IRQHandler
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141 #define IRQ_Hdlr_21 CCU40_0_IRQHandler
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142 #define IRQ_Hdlr_22 CCU40_1_IRQHandler
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143 #define IRQ_Hdlr_23 CCU40_2_IRQHandler
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144 #define IRQ_Hdlr_24 CCU40_3_IRQHandler
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147 * ==========================================================================
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148 * ---------- Interrupt Handler retrieval macro -----------------------------
\r
149 * ==========================================================================
\r
151 #define GET_IRQ_HANDLER(N) IRQ_Hdlr_##N
\r
154 /** @addtogroup Device_Peripheral_Registers
\r
159 /* ------------------- Start of section using anonymous unions ------------------ */
\r
160 #if defined(__CC_ARM)
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162 #pragma anon_unions
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163 #elif defined(__ICCARM__)
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164 #pragma language=extended
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165 #elif defined(__GNUC__)
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166 /* anonymous unions are enabled by default */
\r
167 #elif defined(__TMS470__)
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168 /* anonymous unions are enabled by default */
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169 #elif defined(__TASKING__)
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170 #pragma warning 586
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172 #warning Not supported compiler type
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177 /* ================================================================================ */
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178 /* ================ PPB ================ */
\r
179 /* ================================================================================ */
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183 * @brief Cortex-M0 Private Peripheral Block (PPB)
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186 typedef struct { /*!< (@ 0xE000E000) PPB Structure */
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187 __I uint32_t RESERVED0[4];
\r
188 __IO uint32_t SYST_CSR; /*!< (@ 0xE000E010) SysTick Control and Status Register */
\r
189 __IO uint32_t SYST_RVR; /*!< (@ 0xE000E014) SysTick Reload Value Register */
\r
190 __IO uint32_t SYST_CVR; /*!< (@ 0xE000E018) SysTick Current Value Register */
\r
191 __I uint32_t SYST_CALIB; /*!< (@ 0xE000E01C) SysTick Calibration Value Register */
\r
192 __I uint32_t RESERVED1[56];
\r
193 __IO uint32_t NVIC_ISER; /*!< (@ 0xE000E100) Interrupt Set-enable Register */
\r
194 __I uint32_t RESERVED2[31];
\r
195 __IO uint32_t NVIC_ICER; /*!< (@ 0xE000E180) IInterrupt Clear-enable Register */
\r
196 __I uint32_t RESERVED3[31];
\r
197 __IO uint32_t NVIC_ISPR; /*!< (@ 0xE000E200) Interrupt Set-pending Register */
\r
198 __I uint32_t RESERVED4[31];
\r
199 __IO uint32_t NVIC_ICPR; /*!< (@ 0xE000E280) Interrupt Clear-pending Register */
\r
200 __I uint32_t RESERVED5[95];
\r
201 __IO uint32_t NVIC_IPR0; /*!< (@ 0xE000E400) Interrupt Priority Register 0 */
\r
202 __IO uint32_t NVIC_IPR1; /*!< (@ 0xE000E404) Interrupt Priority Register 1 */
\r
203 __IO uint32_t NVIC_IPR2; /*!< (@ 0xE000E408) Interrupt Priority Register 2 */
\r
204 __IO uint32_t NVIC_IPR3; /*!< (@ 0xE000E40C) Interrupt Priority Register 3 */
\r
205 __IO uint32_t NVIC_IPR4; /*!< (@ 0xE000E410) Interrupt Priority Register 4 */
\r
206 __IO uint32_t NVIC_IPR5; /*!< (@ 0xE000E414) Interrupt Priority Register 5 */
\r
207 __IO uint32_t NVIC_IPR6; /*!< (@ 0xE000E418) Interrupt Priority Register 6 */
\r
208 __IO uint32_t NVIC_IPR7; /*!< (@ 0xE000E41C) Interrupt Priority Register 7 */
\r
209 __I uint32_t RESERVED6[568];
\r
210 __I uint32_t CPUID; /*!< (@ 0xE000ED00) CPUID Base Register */
\r
211 __IO uint32_t ICSR; /*!< (@ 0xE000ED04) Interrupt Control and State Register */
\r
212 __I uint32_t RESERVED7;
\r
213 __IO uint32_t AIRCR; /*!< (@ 0xE000ED0C) Application Interrupt and Reset Control Register */
\r
214 __IO uint32_t SCR; /*!< (@ 0xE000ED10) System Control Register */
\r
215 __I uint32_t CCR; /*!< (@ 0xE000ED14) Configuration and Control Register */
\r
216 __I uint32_t RESERVED8;
\r
217 __IO uint32_t SHPR2; /*!< (@ 0xE000ED1C) System Handler Priority Register 2 */
\r
218 __IO uint32_t SHPR3; /*!< (@ 0xE000ED20) System Handler Priority Register 3 */
\r
219 __IO uint32_t SHCSR; /*!< (@ 0xE000ED24) System Handler Control and State Register */
\r
223 /* ================================================================================ */
\r
224 /* ================ ERU [ERU0] ================ */
\r
225 /* ================================================================================ */
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229 * @brief Event Request Unit 0 (ERU)
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232 typedef struct { /*!< (@ 0x40010600) ERU Structure */
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233 __IO uint32_t EXISEL; /*!< (@ 0x40010600) Event Input Select */
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234 __I uint32_t RESERVED0[3];
\r
235 __IO uint32_t EXICON[4]; /*!< (@ 0x40010610) Event Input Control */
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236 __IO uint32_t EXOCON[4]; /*!< (@ 0x40010620) Event Output Trigger Control */
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237 } ERU_GLOBAL_TypeDef;
\r
240 /* ================================================================================ */
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241 /* ================ PAU ================ */
\r
242 /* ================================================================================ */
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246 * @brief PAU Unit (PAU)
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249 typedef struct { /*!< (@ 0x40000000) PAU Structure */
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250 __I uint32_t RESERVED0[16];
\r
251 __I uint32_t AVAIL0; /*!< (@ 0x40000040) Peripheral Availability Register 0 */
\r
252 __I uint32_t AVAIL1; /*!< (@ 0x40000044) Peripheral Availability Register 1 */
\r
253 __I uint32_t AVAIL2; /*!< (@ 0x40000048) Peripheral Availability Register 2 */
\r
254 __I uint32_t RESERVED1[13];
\r
255 __IO uint32_t PRIVDIS0; /*!< (@ 0x40000080) Peripheral Privilege Access Register 0 */
\r
256 __IO uint32_t PRIVDIS1; /*!< (@ 0x40000084) Peripheral Privilege Access Register 1 */
\r
257 __I uint32_t RESERVED2[222];
\r
258 __I uint32_t ROMSIZE; /*!< (@ 0x40000400) ROM Size Register */
\r
259 __I uint32_t FLSIZE; /*!< (@ 0x40000404) Flash Size Register */
\r
260 __I uint32_t RESERVED3[2];
\r
261 __I uint32_t RAM0SIZE; /*!< (@ 0x40000410) RAM0 Size Register */
\r
265 /* ================================================================================ */
\r
266 /* ================ NVM ================ */
\r
267 /* ================================================================================ */
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271 * @brief NVM Unit (NVM)
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274 typedef struct { /*!< (@ 0x40050000) NVM Structure */
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275 __I uint16_t NVMSTATUS; /*!< (@ 0x40050000) NVM Status Register */
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276 __I uint16_t RESERVED0;
\r
277 __IO uint16_t NVMPROG; /*!< (@ 0x40050004) NVM Programming Control Register */
\r
278 __I uint16_t RESERVED1;
\r
279 __IO uint16_t NVMCONF; /*!< (@ 0x40050008) NVM Configuration Register */
\r
283 /* ================================================================================ */
\r
284 /* ================ WDT ================ */
\r
285 /* ================================================================================ */
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289 * @brief Watch Dog Timer (WDT)
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292 typedef struct { /*!< (@ 0x40020000) WDT Structure */
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293 __I uint32_t ID; /*!< (@ 0x40020000) WDT Module ID Register */
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294 __IO uint32_t CTR; /*!< (@ 0x40020004) WDT Control Register */
\r
295 __O uint32_t SRV; /*!< (@ 0x40020008) WDT Service Register */
\r
296 __I uint32_t TIM; /*!< (@ 0x4002000C) WDT Timer Register */
\r
297 __IO uint32_t WLB; /*!< (@ 0x40020010) WDT Window Lower Bound Register */
\r
298 __IO uint32_t WUB; /*!< (@ 0x40020014) WDT Window Upper Bound Register */
\r
299 __I uint32_t WDTSTS; /*!< (@ 0x40020018) WDT Status Register */
\r
300 __O uint32_t WDTCLR; /*!< (@ 0x4002001C) WDT Clear Register */
\r
301 } WDT_GLOBAL_TypeDef;
\r
304 /* ================================================================================ */
\r
305 /* ================ RTC ================ */
\r
306 /* ================================================================================ */
\r
310 * @brief Real Time Clock (RTC)
\r
313 typedef struct { /*!< (@ 0x40010A00) RTC Structure */
\r
314 __I uint32_t ID; /*!< (@ 0x40010A00) RTC Module ID Register */
\r
315 __IO uint32_t CTR; /*!< (@ 0x40010A04) RTC Control Register */
\r
316 __I uint32_t RAWSTAT; /*!< (@ 0x40010A08) RTC Raw Service Request Register */
\r
317 __I uint32_t STSSR; /*!< (@ 0x40010A0C) RTC Service Request Status Register */
\r
318 __IO uint32_t MSKSR; /*!< (@ 0x40010A10) RTC Service Request Mask Register */
\r
319 __O uint32_t CLRSR; /*!< (@ 0x40010A14) RTC Clear Service Request Register */
\r
320 __IO uint32_t ATIM0; /*!< (@ 0x40010A18) RTC Alarm Time Register 0 */
\r
321 __IO uint32_t ATIM1; /*!< (@ 0x40010A1C) RTC Alarm Time Register 1 */
\r
322 __IO uint32_t TIM0; /*!< (@ 0x40010A20) RTC Time Register 0 */
\r
323 __IO uint32_t TIM1; /*!< (@ 0x40010A24) RTC Time Register 1 */
\r
324 } RTC_GLOBAL_TypeDef;
\r
327 /* ================================================================================ */
\r
328 /* ================ PRNG ================ */
\r
329 /* ================================================================================ */
\r
333 * @brief PRNG Unit (PRNG)
\r
336 typedef struct { /*!< (@ 0x48020000) PRNG Structure */
\r
337 __IO uint16_t WORD; /*!< (@ 0x48020000) Pseudo RNG Word Register */
\r
338 __I uint16_t RESERVED0;
\r
339 __I uint16_t CHK; /*!< (@ 0x48020004) Pseudo RNG Status Check Register */
\r
340 __I uint16_t RESERVED1[3];
\r
341 __IO uint16_t CTRL; /*!< (@ 0x4802000C) Pseudo RNG Control Register */
\r
345 /* ================================================================================ */
\r
346 /* ================ USIC [USIC0] ================ */
\r
347 /* ================================================================================ */
\r
351 * @brief Universal Serial Interface Controller 0 (USIC)
\r
354 typedef struct { /*!< (@ 0x48000008) USIC Structure */
\r
355 __I uint32_t ID; /*!< (@ 0x48000008) Module Identification Register */
\r
356 } USIC_GLOBAL_TypeDef;
\r
359 /* ================================================================================ */
\r
360 /* ================ USIC_CH [USIC0_CH0] ================ */
\r
361 /* ================================================================================ */
\r
365 * @brief Universal Serial Interface Controller 0 (USIC_CH)
\r
368 typedef struct { /*!< (@ 0x48000000) USIC_CH Structure */
\r
369 __I uint32_t RESERVED0;
\r
370 __I uint32_t CCFG; /*!< (@ 0x48000004) Channel Configuration Register */
\r
371 __I uint32_t RESERVED1;
\r
372 __IO uint32_t KSCFG; /*!< (@ 0x4800000C) Kernel State Configuration Register */
\r
373 __IO uint32_t FDR; /*!< (@ 0x48000010) Fractional Divider Register */
\r
374 __IO uint32_t BRG; /*!< (@ 0x48000014) Baud Rate Generator Register */
\r
375 __IO uint32_t INPR; /*!< (@ 0x48000018) Interrupt Node Pointer Register */
\r
376 __IO uint32_t DX0CR; /*!< (@ 0x4800001C) Input Control Register 0 */
\r
377 __IO uint32_t DX1CR; /*!< (@ 0x48000020) Input Control Register 1 */
\r
378 __IO uint32_t DX2CR; /*!< (@ 0x48000024) Input Control Register 2 */
\r
379 __IO uint32_t DX3CR; /*!< (@ 0x48000028) Input Control Register 3 */
\r
380 __IO uint32_t DX4CR; /*!< (@ 0x4800002C) Input Control Register 4 */
\r
381 __IO uint32_t DX5CR; /*!< (@ 0x48000030) Input Control Register 5 */
\r
382 __IO uint32_t SCTR; /*!< (@ 0x48000034) Shift Control Register */
\r
383 __IO uint32_t TCSR; /*!< (@ 0x48000038) Transmit Control/Status Register */
\r
386 __IO uint32_t PCR_IICMode; /*!< (@ 0x4800003C) Protocol Control Register [IIC Mode] */
\r
387 __IO uint32_t PCR_IISMode; /*!< (@ 0x4800003C) Protocol Control Register [IIS Mode] */
\r
388 __IO uint32_t PCR_SSCMode; /*!< (@ 0x4800003C) Protocol Control Register [SSC Mode] */
\r
389 __IO uint32_t PCR; /*!< (@ 0x4800003C) Protocol Control Register */
\r
390 __IO uint32_t PCR_ASCMode; /*!< (@ 0x4800003C) Protocol Control Register [ASC Mode] */
\r
392 __IO uint32_t CCR; /*!< (@ 0x48000040) Channel Control Register */
\r
393 __IO uint32_t CMTR; /*!< (@ 0x48000044) Capture Mode Timer Register */
\r
396 __IO uint32_t PSR_IICMode; /*!< (@ 0x48000048) Protocol Status Register [IIC Mode] */
\r
397 __IO uint32_t PSR_IISMode; /*!< (@ 0x48000048) Protocol Status Register [IIS Mode] */
\r
398 __IO uint32_t PSR_SSCMode; /*!< (@ 0x48000048) Protocol Status Register [SSC Mode] */
\r
399 __IO uint32_t PSR; /*!< (@ 0x48000048) Protocol Status Register */
\r
400 __IO uint32_t PSR_ASCMode; /*!< (@ 0x48000048) Protocol Status Register [ASC Mode] */
\r
402 __O uint32_t PSCR; /*!< (@ 0x4800004C) Protocol Status Clear Register */
\r
403 __I uint32_t RBUFSR; /*!< (@ 0x48000050) Receiver Buffer Status Register */
\r
404 __I uint32_t RBUF; /*!< (@ 0x48000054) Receiver Buffer Register */
\r
405 __I uint32_t RBUFD; /*!< (@ 0x48000058) Receiver Buffer Register for Debugger */
\r
406 __I uint32_t RBUF0; /*!< (@ 0x4800005C) Receiver Buffer Register 0 */
\r
407 __I uint32_t RBUF1; /*!< (@ 0x48000060) Receiver Buffer Register 1 */
\r
408 __I uint32_t RBUF01SR; /*!< (@ 0x48000064) Receiver Buffer 01 Status Register */
\r
409 __O uint32_t FMR; /*!< (@ 0x48000068) Flag Modification Register */
\r
410 __I uint32_t RESERVED2[5];
\r
411 __IO uint32_t TBUF[32]; /*!< (@ 0x48000080) Transmit Buffer */
\r
412 __IO uint32_t BYP; /*!< (@ 0x48000100) Bypass Data Register */
\r
413 __IO uint32_t BYPCR; /*!< (@ 0x48000104) Bypass Control Register */
\r
414 __IO uint32_t TBCTR; /*!< (@ 0x48000108) Transmitter Buffer Control Register */
\r
415 __IO uint32_t RBCTR; /*!< (@ 0x4800010C) Receiver Buffer Control Register */
\r
416 __I uint32_t TRBPTR; /*!< (@ 0x48000110) Transmit/Receive Buffer Pointer Register */
\r
417 __IO uint32_t TRBSR; /*!< (@ 0x48000114) Transmit/Receive Buffer Status Register */
\r
418 __O uint32_t TRBSCR; /*!< (@ 0x48000118) Transmit/Receive Buffer Status Clear Register */
\r
419 __I uint32_t OUTR; /*!< (@ 0x4800011C) Receiver Buffer Output Register */
\r
420 __I uint32_t OUTDR; /*!< (@ 0x48000120) Receiver Buffer Output Register L for Debugger */
\r
421 __I uint32_t RESERVED3[23];
\r
422 __O uint32_t IN[32]; /*!< (@ 0x48000180) Transmit FIFO Buffer */
\r
426 /* ================================================================================ */
\r
427 /* ================ SCU_GENERAL ================ */
\r
428 /* ================================================================================ */
\r
432 * @brief System Control Unit (SCU_GENERAL)
\r
435 typedef struct { /*!< (@ 0x40010000) SCU_GENERAL Structure */
\r
436 __I uint32_t DBGROMID; /*!< (@ 0x40010000) Debug System ROM ID Register */
\r
437 __I uint32_t IDCHIP; /*!< (@ 0x40010004) Chip ID Register */
\r
438 __I uint32_t ID; /*!< (@ 0x40010008) SCU Module ID Register */
\r
439 __I uint32_t RESERVED0[2];
\r
440 __IO uint32_t SSW0; /*!< (@ 0x40010014) SSW Register 0 */
\r
441 __I uint32_t RESERVED1[3];
\r
442 __IO uint32_t PASSWD; /*!< (@ 0x40010024) Password Register */
\r
443 __I uint32_t RESERVED2[2];
\r
444 __IO uint32_t CCUCON; /*!< (@ 0x40010030) CCU Control Register */
\r
445 __I uint32_t RESERVED3[5];
\r
446 __I uint32_t MIRRSTS; /*!< (@ 0x40010048) Mirror Update Status Register */
\r
447 __I uint32_t RESERVED4[2];
\r
448 __IO uint32_t PMTSR; /*!< (@ 0x40010054) Parity Memory Test Select Register */
\r
449 } SCU_GENERAL_Type;
\r
452 /* ================================================================================ */
\r
453 /* ================ SCU_INTERRUPT ================ */
\r
454 /* ================================================================================ */
\r
458 * @brief System Control Unit (SCU_INTERRUPT)
\r
461 typedef struct { /*!< (@ 0x40010038) SCU_INTERRUPT Structure */
\r
462 __I uint32_t SRRAW; /*!< (@ 0x40010038) SCU Raw Service Request Status */
\r
463 __IO uint32_t SRMSK; /*!< (@ 0x4001003C) SCU Service Request Mask */
\r
464 __O uint32_t SRCLR; /*!< (@ 0x40010040) SCU Service Request Clear */
\r
465 __O uint32_t SRSET; /*!< (@ 0x40010044) SCU Service Request Set */
\r
466 } SCU_INTERRUPT_TypeDef;
\r
469 /* ================================================================================ */
\r
470 /* ================ SCU_POWER ================ */
\r
471 /* ================================================================================ */
\r
475 * @brief System Control Unit (SCU_POWER)
\r
478 typedef struct { /*!< (@ 0x40010200) SCU_POWER Structure */
\r
479 __I uint32_t VDESR; /*!< (@ 0x40010200) Voltage Detector Status Register */
\r
483 /* ================================================================================ */
\r
484 /* ================ SCU_CLK ================ */
\r
485 /* ================================================================================ */
\r
489 * @brief System Control Unit (SCU_CLK)
\r
492 typedef struct { /*!< (@ 0x40010300) SCU_CLK Structure */
\r
493 __IO uint32_t CLKCR; /*!< (@ 0x40010300) Clock Control Register */
\r
494 __IO uint32_t PWRSVCR; /*!< (@ 0x40010304) Power Save Control Register */
\r
495 __I uint32_t CGATSTAT0; /*!< (@ 0x40010308) Peripheral 0 Clock Gating Status */
\r
496 __O uint32_t CGATSET0; /*!< (@ 0x4001030C) Peripheral 0 Clock Gating Set */
\r
497 __O uint32_t CGATCLR0; /*!< (@ 0x40010310) Peripheral 0 Clock Gating Clear */
\r
498 __IO uint32_t OSCCSR; /*!< (@ 0x40010314) Oscillator Control and Status Register */
\r
502 /* ================================================================================ */
\r
503 /* ================ SCU_RESET ================ */
\r
504 /* ================================================================================ */
\r
508 * @brief System Control Unit (SCU_RESET)
\r
511 typedef struct { /*!< (@ 0x40010400) SCU_RESET Structure */
\r
512 __I uint32_t RSTSTAT; /*!< (@ 0x40010400) RCU Reset Status */
\r
513 __O uint32_t RSTSET; /*!< (@ 0x40010404) RCU Reset Set Register */
\r
514 __O uint32_t RSTCLR; /*!< (@ 0x40010408) RCU Reset Clear Register */
\r
515 __IO uint32_t RSTCON; /*!< (@ 0x4001040C) RCU Reset Control Register */
\r
519 /* ================================================================================ */
\r
520 /* ================ SCU_ANALOG ================ */
\r
521 /* ================================================================================ */
\r
525 * @brief System Control Unit (SCU_ANALOG)
\r
528 typedef struct { /*!< (@ 0x40011000) SCU_ANALOG Structure */
\r
529 __I uint32_t RESERVED0[20];
\r
530 __IO uint16_t ANAVDEL; /*!< (@ 0x40011050) Voltage Detector Control Register */
\r
534 /* ================================================================================ */
\r
535 /* ================ CCU4 [CCU40] ================ */
\r
536 /* ================================================================================ */
\r
540 * @brief Capture Compare Unit 4 - Unit 0 (CCU4)
\r
543 typedef struct { /*!< (@ 0x48040000) CCU4 Structure */
\r
544 __IO uint32_t GCTRL; /*!< (@ 0x48040000) Global Control Register */
\r
545 __I uint32_t GSTAT; /*!< (@ 0x48040004) Global Status Register */
\r
546 __O uint32_t GIDLS; /*!< (@ 0x48040008) Global Idle Set */
\r
547 __O uint32_t GIDLC; /*!< (@ 0x4804000C) Global Idle Clear */
\r
548 __O uint32_t GCSS; /*!< (@ 0x48040010) Global Channel Set */
\r
549 __O uint32_t GCSC; /*!< (@ 0x48040014) Global Channel Clear */
\r
550 __I uint32_t GCST; /*!< (@ 0x48040018) Global Channel Status */
\r
551 __I uint32_t RESERVED0[25];
\r
552 __I uint32_t MIDR; /*!< (@ 0x48040080) Module Identification */
\r
553 } CCU4_GLOBAL_TypeDef;
\r
556 /* ================================================================================ */
\r
557 /* ================ CCU4_CC4 [CCU40_CC40] ================ */
\r
558 /* ================================================================================ */
\r
562 * @brief Capture Compare Unit 4 - Unit 0 (CCU4_CC4)
\r
565 typedef struct { /*!< (@ 0x48040100) CCU4_CC4 Structure */
\r
566 __IO uint32_t INS; /*!< (@ 0x48040100) Input Selector Configuration */
\r
567 __IO uint32_t CMC; /*!< (@ 0x48040104) Connection Matrix Control */
\r
568 __I uint32_t TCST; /*!< (@ 0x48040108) Slice Timer Status */
\r
569 __O uint32_t TCSET; /*!< (@ 0x4804010C) Slice Timer Run Set */
\r
570 __O uint32_t TCCLR; /*!< (@ 0x48040110) Slice Timer Clear */
\r
571 __IO uint32_t TC; /*!< (@ 0x48040114) Slice Timer Control */
\r
572 __IO uint32_t PSL; /*!< (@ 0x48040118) Passive Level Config */
\r
573 __I uint32_t DIT; /*!< (@ 0x4804011C) Dither Config */
\r
574 __IO uint32_t DITS; /*!< (@ 0x48040120) Dither Shadow Register */
\r
575 __IO uint32_t PSC; /*!< (@ 0x48040124) Prescaler Control */
\r
576 __IO uint32_t FPC; /*!< (@ 0x48040128) Floating Prescaler Control */
\r
577 __IO uint32_t FPCS; /*!< (@ 0x4804012C) Floating Prescaler Shadow */
\r
578 __I uint32_t PR; /*!< (@ 0x48040130) Timer Period Value */
\r
579 __IO uint32_t PRS; /*!< (@ 0x48040134) Timer Shadow Period Value */
\r
580 __I uint32_t CR; /*!< (@ 0x48040138) Timer Compare Value */
\r
581 __IO uint32_t CRS; /*!< (@ 0x4804013C) Timer Shadow Compare Value */
\r
582 __I uint32_t RESERVED0[12];
\r
583 __IO uint32_t TIMER; /*!< (@ 0x48040170) Timer Value */
\r
584 __I uint32_t CV[4]; /*!< (@ 0x48040174) Capture Register 0 */
\r
585 __I uint32_t RESERVED1[7];
\r
586 __I uint32_t INTS; /*!< (@ 0x480401A0) Interrupt Status */
\r
587 __IO uint32_t INTE; /*!< (@ 0x480401A4) Interrupt Enable Control */
\r
588 __IO uint32_t SRS; /*!< (@ 0x480401A8) Service Request Selector */
\r
589 __O uint32_t SWS; /*!< (@ 0x480401AC) Interrupt Status Set */
\r
590 __O uint32_t SWR; /*!< (@ 0x480401B0) Interrupt Status Clear */
\r
591 __I uint32_t RESERVED2;
\r
592 __I uint32_t ECRD0; /*!< (@ 0x480401B8) Extended Read Back 0 */
\r
593 __I uint32_t ECRD1; /*!< (@ 0x480401BC) Extended Read Back 1 */
\r
594 } CCU4_CC4_TypeDef;
\r
597 /* ================================================================================ */
\r
598 /* ================ VADC [VADC] ================ */
\r
599 /* ================================================================================ */
\r
603 * @brief Analog to Digital Converter (VADC)
\r
606 typedef struct { /*!< (@ 0x48030000) VADC Structure */
\r
607 __IO uint32_t CLC; /*!< (@ 0x48030000) Clock Control Register */
\r
608 __I uint32_t RESERVED0;
\r
609 __I uint32_t ID; /*!< (@ 0x48030008) Module Identification Register */
\r
610 __I uint32_t RESERVED1[7];
\r
611 __IO uint32_t OCS; /*!< (@ 0x48030028) OCDS Control and Status Register */
\r
612 __I uint32_t RESERVED2[21];
\r
613 __IO uint32_t GLOBCFG; /*!< (@ 0x48030080) Global Configuration Register */
\r
614 __I uint32_t RESERVED3[7];
\r
615 __IO uint32_t GLOBICLASS[2]; /*!< (@ 0x480300A0) Input Class Register, Global */
\r
616 __I uint32_t RESERVED4[14];
\r
617 __IO uint32_t GLOBEFLAG; /*!< (@ 0x480300E0) Global Event Flag Register */
\r
618 __I uint32_t RESERVED5[23];
\r
619 __IO uint32_t GLOBEVNP; /*!< (@ 0x48030140) Global Event Node Pointer Register */
\r
620 __I uint32_t RESERVED6[15];
\r
621 __IO uint32_t BRSSEL[2]; /*!< (@ 0x48030180) Background Request Source Channel Select Register */
\r
622 __I uint32_t RESERVED7[14];
\r
623 __IO uint32_t BRSPND[2]; /*!< (@ 0x480301C0) Background Request Source Pending Register */
\r
624 __I uint32_t RESERVED8[14];
\r
625 __IO uint32_t BRSCTRL; /*!< (@ 0x48030200) Background Request Source Control Register */
\r
626 __IO uint32_t BRSMR; /*!< (@ 0x48030204) Background Request Source Mode Register */
\r
627 __I uint32_t RESERVED9[30];
\r
628 __IO uint32_t GLOBRCR; /*!< (@ 0x48030280) Global Result Control Register */
\r
629 __I uint32_t RESERVED10[31];
\r
630 __IO uint32_t GLOBRES; /*!< (@ 0x48030300) Global Result Register */
\r
631 __I uint32_t RESERVED11[31];
\r
632 __IO uint32_t GLOBRESD; /*!< (@ 0x48030380) Global Result Register, Debug */
\r
633 } VADC_GLOBAL_TypeDef;
\r
636 /* ================================================================================ */
\r
637 /* ================ SHS [SHS0] ================ */
\r
638 /* ================================================================================ */
\r
642 * @brief Sample and Hold ADC Sequencer (SHS)
\r
645 typedef struct { /*!< (@ 0x48034000) SHS Structure */
\r
646 __I uint32_t RESERVED0[2];
\r
647 __I uint32_t ID; /*!< (@ 0x48034008) Module Identification Register */
\r
648 __I uint32_t RESERVED1[13];
\r
649 __IO uint32_t SHSCFG; /*!< (@ 0x48034040) SHS Configuration Register */
\r
650 __IO uint32_t STEPCFG; /*!< (@ 0x48034044) Stepper Configuration Register */
\r
651 __I uint32_t RESERVED2[2];
\r
652 __IO uint32_t LOOP; /*!< (@ 0x48034050) Loop Control Register */
\r
653 __I uint32_t RESERVED3[11];
\r
654 __IO uint32_t TIMCFG0; /*!< (@ 0x48034080) Timing Configuration Register 0 */
\r
655 __IO uint32_t TIMCFG1; /*!< (@ 0x48034084) Timing Configuration Register 1 */
\r
656 __I uint32_t RESERVED4[13];
\r
657 __IO uint32_t CALCTR; /*!< (@ 0x480340BC) Calibration Control Register */
\r
658 __IO uint32_t CALGC0; /*!< (@ 0x480340C0) Gain Calibration Control Register 0 */
\r
659 __IO uint32_t CALGC1; /*!< (@ 0x480340C4) Gain Calibration Control Register 1 */
\r
660 __I uint32_t RESERVED5[46];
\r
661 __IO uint32_t GNCTR00; /*!< (@ 0x48034180) Gain Control Register 00 */
\r
662 __I uint32_t RESERVED6[3];
\r
663 __IO uint32_t GNCTR10; /*!< (@ 0x48034190) Gain Control Register 10 */
\r
667 /* ================================================================================ */
\r
668 /* ================ PORT0 ================ */
\r
669 /* ================================================================================ */
\r
673 * @brief Port 0 (PORT0)
\r
676 typedef struct { /*!< (@ 0x40040000) PORT0 Structure */
\r
677 __IO uint32_t OUT; /*!< (@ 0x40040000) Port 0 Output Register */
\r
678 __O uint32_t OMR; /*!< (@ 0x40040004) Port 0 Output Modification Register */
\r
679 __I uint32_t RESERVED0[2];
\r
680 __IO uint32_t IOCR0; /*!< (@ 0x40040010) Port 0 Input/Output Control Register 0 */
\r
681 __IO uint32_t IOCR4; /*!< (@ 0x40040014) Port 0 Input/Output Control Register 4 */
\r
682 __IO uint32_t IOCR8; /*!< (@ 0x40040018) Port 0 Input/Output Control Register 8 */
\r
683 __IO uint32_t IOCR12; /*!< (@ 0x4004001C) Port 0 Input/Output Control Register 12 */
\r
684 __I uint32_t RESERVED1;
\r
685 __I uint32_t IN; /*!< (@ 0x40040024) Port 0 Input Register */
\r
686 __I uint32_t RESERVED2[6];
\r
687 __IO uint32_t PHCR0; /*!< (@ 0x40040040) Port 0 Pad Hysteresis Control Register 0 */
\r
688 __IO uint32_t PHCR1; /*!< (@ 0x40040044) Port 0 Pad Hysteresis Control Register 1 */
\r
689 __I uint32_t RESERVED3[6];
\r
690 __I uint32_t PDISC; /*!< (@ 0x40040060) Port 0 Pin Function Decision Control Register */
\r
691 __I uint32_t RESERVED4[3];
\r
692 __IO uint32_t PPS; /*!< (@ 0x40040070) Port 0 Pin Power Save Register */
\r
693 __IO uint32_t HWSEL; /*!< (@ 0x40040074) Port 0 Pin Hardware Select Register */
\r
697 /* ================================================================================ */
\r
698 /* ================ PORT1 ================ */
\r
699 /* ================================================================================ */
\r
703 * @brief Port 1 (PORT1)
\r
706 typedef struct { /*!< (@ 0x40040100) PORT1 Structure */
\r
707 __IO uint32_t OUT; /*!< (@ 0x40040100) Port 1 Output Register */
\r
708 __O uint32_t OMR; /*!< (@ 0x40040104) Port 1 Output Modification Register */
\r
709 __I uint32_t RESERVED0[2];
\r
710 __IO uint32_t IOCR0; /*!< (@ 0x40040110) Port 1 Input/Output Control Register 0 */
\r
711 __IO uint32_t IOCR4; /*!< (@ 0x40040114) Port 1 Input/Output Control Register 4 */
\r
712 __I uint32_t RESERVED1[3];
\r
713 __I uint32_t IN; /*!< (@ 0x40040124) Port 1 Input Register */
\r
714 __I uint32_t RESERVED2[6];
\r
715 __IO uint32_t PHCR0; /*!< (@ 0x40040140) Port 1 Pad Hysteresis Control Register 0 */
\r
716 __I uint32_t RESERVED3[7];
\r
717 __I uint32_t PDISC; /*!< (@ 0x40040160) Port 1 Pin Function Decision Control Register */
\r
718 __I uint32_t RESERVED4[3];
\r
719 __IO uint32_t PPS; /*!< (@ 0x40040170) Port 1 Pin Power Save Register */
\r
720 __IO uint32_t HWSEL; /*!< (@ 0x40040174) Port 1 Pin Hardware Select Register */
\r
724 /* ================================================================================ */
\r
725 /* ================ PORT2 ================ */
\r
726 /* ================================================================================ */
\r
730 * @brief Port 2 (PORT2)
\r
733 typedef struct { /*!< (@ 0x40040200) PORT2 Structure */
\r
734 __IO uint32_t OUT; /*!< (@ 0x40040200) Port 2 Output Register */
\r
735 __O uint32_t OMR; /*!< (@ 0x40040204) Port 2 Output Modification Register */
\r
736 __I uint32_t RESERVED0[2];
\r
737 __IO uint32_t IOCR0; /*!< (@ 0x40040210) Port 2 Input/Output Control Register 0 */
\r
738 __IO uint32_t IOCR4; /*!< (@ 0x40040214) Port 2 Input/Output Control Register 4 */
\r
739 __IO uint32_t IOCR8; /*!< (@ 0x40040218) Port 2 Input/Output Control Register 8 */
\r
740 __I uint32_t RESERVED1[2];
\r
741 __I uint32_t IN; /*!< (@ 0x40040224) Port 2 Input Register */
\r
742 __I uint32_t RESERVED2[6];
\r
743 __IO uint32_t PHCR0; /*!< (@ 0x40040240) Port 2 Pad Hysteresis Control Register 0 */
\r
744 __IO uint32_t PHCR1; /*!< (@ 0x40040244) Port 2 Pad Hysteresis Control Register 1 */
\r
745 __I uint32_t RESERVED3[6];
\r
746 __IO uint32_t PDISC; /*!< (@ 0x40040260) Port 2 Pin Function Decision Control Register */
\r
747 __I uint32_t RESERVED4[3];
\r
748 __IO uint32_t PPS; /*!< (@ 0x40040270) Port 2 Pin Power Save Register */
\r
749 __IO uint32_t HWSEL; /*!< (@ 0x40040274) Port 2 Pin Hardware Select Register */
\r
753 /* -------------------- End of section using anonymous unions ------------------- */
\r
754 #if defined(__CC_ARM)
\r
756 #elif defined(__ICCARM__)
\r
757 /* leave anonymous unions enabled */
\r
758 #elif defined(__GNUC__)
\r
759 /* anonymous unions are enabled by default */
\r
760 #elif defined(__TMS470__)
\r
761 /* anonymous unions are enabled by default */
\r
762 #elif defined(__TASKING__)
\r
763 #pragma warning restore
\r
765 #warning Not supported compiler type
\r
770 /* ================================================================================ */
\r
771 /* ================ struct 'PPB' Position & Mask ================ */
\r
772 /* ================================================================================ */
\r
775 /* -------------------------------- PPB_SYST_CSR -------------------------------- */
\r
776 #define PPB_SYST_CSR_ENABLE_Pos 0 /*!< PPB SYST_CSR: ENABLE Position */
\r
777 #define PPB_SYST_CSR_ENABLE_Msk (0x01UL << PPB_SYST_CSR_ENABLE_Pos) /*!< PPB SYST_CSR: ENABLE Mask */
\r
778 #define PPB_SYST_CSR_TICKINT_Pos 1 /*!< PPB SYST_CSR: TICKINT Position */
\r
779 #define PPB_SYST_CSR_TICKINT_Msk (0x01UL << PPB_SYST_CSR_TICKINT_Pos) /*!< PPB SYST_CSR: TICKINT Mask */
\r
780 #define PPB_SYST_CSR_CLKSOURCE_Pos 2 /*!< PPB SYST_CSR: CLKSOURCE Position */
\r
781 #define PPB_SYST_CSR_CLKSOURCE_Msk (0x01UL << PPB_SYST_CSR_CLKSOURCE_Pos) /*!< PPB SYST_CSR: CLKSOURCE Mask */
\r
782 #define PPB_SYST_CSR_COUNTFLAG_Pos 16 /*!< PPB SYST_CSR: COUNTFLAG Position */
\r
783 #define PPB_SYST_CSR_COUNTFLAG_Msk (0x01UL << PPB_SYST_CSR_COUNTFLAG_Pos) /*!< PPB SYST_CSR: COUNTFLAG Mask */
\r
785 /* -------------------------------- PPB_SYST_RVR -------------------------------- */
\r
786 #define PPB_SYST_RVR_RELOAD_Pos 0 /*!< PPB SYST_RVR: RELOAD Position */
\r
787 #define PPB_SYST_RVR_RELOAD_Msk (0x00ffffffUL << PPB_SYST_RVR_RELOAD_Pos) /*!< PPB SYST_RVR: RELOAD Mask */
\r
789 /* -------------------------------- PPB_SYST_CVR -------------------------------- */
\r
790 #define PPB_SYST_CVR_CURRENT_Pos 0 /*!< PPB SYST_CVR: CURRENT Position */
\r
791 #define PPB_SYST_CVR_CURRENT_Msk (0x00ffffffUL << PPB_SYST_CVR_CURRENT_Pos) /*!< PPB SYST_CVR: CURRENT Mask */
\r
793 /* ------------------------------- PPB_SYST_CALIB ------------------------------- */
\r
794 #define PPB_SYST_CALIB_TENMS_Pos 0 /*!< PPB SYST_CALIB: TENMS Position */
\r
795 #define PPB_SYST_CALIB_TENMS_Msk (0x00ffffffUL << PPB_SYST_CALIB_TENMS_Pos) /*!< PPB SYST_CALIB: TENMS Mask */
\r
796 #define PPB_SYST_CALIB_SKEW_Pos 30 /*!< PPB SYST_CALIB: SKEW Position */
\r
797 #define PPB_SYST_CALIB_SKEW_Msk (0x01UL << PPB_SYST_CALIB_SKEW_Pos) /*!< PPB SYST_CALIB: SKEW Mask */
\r
798 #define PPB_SYST_CALIB_NOREF_Pos 31 /*!< PPB SYST_CALIB: NOREF Position */
\r
799 #define PPB_SYST_CALIB_NOREF_Msk (0x01UL << PPB_SYST_CALIB_NOREF_Pos) /*!< PPB SYST_CALIB: NOREF Mask */
\r
801 /* -------------------------------- PPB_NVIC_ISER ------------------------------- */
\r
802 #define PPB_NVIC_ISER_SETENA_Pos 0 /*!< PPB NVIC_ISER: SETENA Position */
\r
803 #define PPB_NVIC_ISER_SETENA_Msk (0xffffffffUL << PPB_NVIC_ISER_SETENA_Pos) /*!< PPB NVIC_ISER: SETENA Mask */
\r
805 /* -------------------------------- PPB_NVIC_ICER ------------------------------- */
\r
806 #define PPB_NVIC_ICER_CLRENA_Pos 0 /*!< PPB NVIC_ICER: CLRENA Position */
\r
807 #define PPB_NVIC_ICER_CLRENA_Msk (0xffffffffUL << PPB_NVIC_ICER_CLRENA_Pos) /*!< PPB NVIC_ICER: CLRENA Mask */
\r
809 /* -------------------------------- PPB_NVIC_ISPR ------------------------------- */
\r
810 #define PPB_NVIC_ISPR_SETPEND_Pos 0 /*!< PPB NVIC_ISPR: SETPEND Position */
\r
811 #define PPB_NVIC_ISPR_SETPEND_Msk (0xffffffffUL << PPB_NVIC_ISPR_SETPEND_Pos) /*!< PPB NVIC_ISPR: SETPEND Mask */
\r
813 /* -------------------------------- PPB_NVIC_ICPR ------------------------------- */
\r
814 #define PPB_NVIC_ICPR_CLRPEND_Pos 0 /*!< PPB NVIC_ICPR: CLRPEND Position */
\r
815 #define PPB_NVIC_ICPR_CLRPEND_Msk (0xffffffffUL << PPB_NVIC_ICPR_CLRPEND_Pos) /*!< PPB NVIC_ICPR: CLRPEND Mask */
\r
817 /* -------------------------------- PPB_NVIC_IPR0 ------------------------------- */
\r
818 #define PPB_NVIC_IPR0_PRI_0_Pos 0 /*!< PPB NVIC_IPR0: PRI_0 Position */
\r
819 #define PPB_NVIC_IPR0_PRI_0_Msk (0x000000ffUL << PPB_NVIC_IPR0_PRI_0_Pos) /*!< PPB NVIC_IPR0: PRI_0 Mask */
\r
820 #define PPB_NVIC_IPR0_PRI_1_Pos 8 /*!< PPB NVIC_IPR0: PRI_1 Position */
\r
821 #define PPB_NVIC_IPR0_PRI_1_Msk (0x000000ffUL << PPB_NVIC_IPR0_PRI_1_Pos) /*!< PPB NVIC_IPR0: PRI_1 Mask */
\r
822 #define PPB_NVIC_IPR0_PRI_2_Pos 16 /*!< PPB NVIC_IPR0: PRI_2 Position */
\r
823 #define PPB_NVIC_IPR0_PRI_2_Msk (0x000000ffUL << PPB_NVIC_IPR0_PRI_2_Pos) /*!< PPB NVIC_IPR0: PRI_2 Mask */
\r
824 #define PPB_NVIC_IPR0_PRI_3_Pos 24 /*!< PPB NVIC_IPR0: PRI_3 Position */
\r
825 #define PPB_NVIC_IPR0_PRI_3_Msk (0x000000ffUL << PPB_NVIC_IPR0_PRI_3_Pos) /*!< PPB NVIC_IPR0: PRI_3 Mask */
\r
827 /* -------------------------------- PPB_NVIC_IPR1 ------------------------------- */
\r
828 #define PPB_NVIC_IPR1_PRI_0_Pos 0 /*!< PPB NVIC_IPR1: PRI_0 Position */
\r
829 #define PPB_NVIC_IPR1_PRI_0_Msk (0x000000ffUL << PPB_NVIC_IPR1_PRI_0_Pos) /*!< PPB NVIC_IPR1: PRI_0 Mask */
\r
830 #define PPB_NVIC_IPR1_PRI_1_Pos 8 /*!< PPB NVIC_IPR1: PRI_1 Position */
\r
831 #define PPB_NVIC_IPR1_PRI_1_Msk (0x000000ffUL << PPB_NVIC_IPR1_PRI_1_Pos) /*!< PPB NVIC_IPR1: PRI_1 Mask */
\r
832 #define PPB_NVIC_IPR1_PRI_2_Pos 16 /*!< PPB NVIC_IPR1: PRI_2 Position */
\r
833 #define PPB_NVIC_IPR1_PRI_2_Msk (0x000000ffUL << PPB_NVIC_IPR1_PRI_2_Pos) /*!< PPB NVIC_IPR1: PRI_2 Mask */
\r
834 #define PPB_NVIC_IPR1_PRI_3_Pos 24 /*!< PPB NVIC_IPR1: PRI_3 Position */
\r
835 #define PPB_NVIC_IPR1_PRI_3_Msk (0x000000ffUL << PPB_NVIC_IPR1_PRI_3_Pos) /*!< PPB NVIC_IPR1: PRI_3 Mask */
\r
837 /* -------------------------------- PPB_NVIC_IPR2 ------------------------------- */
\r
838 #define PPB_NVIC_IPR2_PRI_0_Pos 0 /*!< PPB NVIC_IPR2: PRI_0 Position */
\r
839 #define PPB_NVIC_IPR2_PRI_0_Msk (0x000000ffUL << PPB_NVIC_IPR2_PRI_0_Pos) /*!< PPB NVIC_IPR2: PRI_0 Mask */
\r
840 #define PPB_NVIC_IPR2_PRI_1_Pos 8 /*!< PPB NVIC_IPR2: PRI_1 Position */
\r
841 #define PPB_NVIC_IPR2_PRI_1_Msk (0x000000ffUL << PPB_NVIC_IPR2_PRI_1_Pos) /*!< PPB NVIC_IPR2: PRI_1 Mask */
\r
842 #define PPB_NVIC_IPR2_PRI_2_Pos 16 /*!< PPB NVIC_IPR2: PRI_2 Position */
\r
843 #define PPB_NVIC_IPR2_PRI_2_Msk (0x000000ffUL << PPB_NVIC_IPR2_PRI_2_Pos) /*!< PPB NVIC_IPR2: PRI_2 Mask */
\r
844 #define PPB_NVIC_IPR2_PRI_3_Pos 24 /*!< PPB NVIC_IPR2: PRI_3 Position */
\r
845 #define PPB_NVIC_IPR2_PRI_3_Msk (0x000000ffUL << PPB_NVIC_IPR2_PRI_3_Pos) /*!< PPB NVIC_IPR2: PRI_3 Mask */
\r
847 /* -------------------------------- PPB_NVIC_IPR3 ------------------------------- */
\r
848 #define PPB_NVIC_IPR3_PRI_0_Pos 0 /*!< PPB NVIC_IPR3: PRI_0 Position */
\r
849 #define PPB_NVIC_IPR3_PRI_0_Msk (0x000000ffUL << PPB_NVIC_IPR3_PRI_0_Pos) /*!< PPB NVIC_IPR3: PRI_0 Mask */
\r
850 #define PPB_NVIC_IPR3_PRI_1_Pos 8 /*!< PPB NVIC_IPR3: PRI_1 Position */
\r
851 #define PPB_NVIC_IPR3_PRI_1_Msk (0x000000ffUL << PPB_NVIC_IPR3_PRI_1_Pos) /*!< PPB NVIC_IPR3: PRI_1 Mask */
\r
852 #define PPB_NVIC_IPR3_PRI_2_Pos 16 /*!< PPB NVIC_IPR3: PRI_2 Position */
\r
853 #define PPB_NVIC_IPR3_PRI_2_Msk (0x000000ffUL << PPB_NVIC_IPR3_PRI_2_Pos) /*!< PPB NVIC_IPR3: PRI_2 Mask */
\r
854 #define PPB_NVIC_IPR3_PRI_3_Pos 24 /*!< PPB NVIC_IPR3: PRI_3 Position */
\r
855 #define PPB_NVIC_IPR3_PRI_3_Msk (0x000000ffUL << PPB_NVIC_IPR3_PRI_3_Pos) /*!< PPB NVIC_IPR3: PRI_3 Mask */
\r
857 /* -------------------------------- PPB_NVIC_IPR4 ------------------------------- */
\r
858 #define PPB_NVIC_IPR4_PRI_0_Pos 0 /*!< PPB NVIC_IPR4: PRI_0 Position */
\r
859 #define PPB_NVIC_IPR4_PRI_0_Msk (0x000000ffUL << PPB_NVIC_IPR4_PRI_0_Pos) /*!< PPB NVIC_IPR4: PRI_0 Mask */
\r
860 #define PPB_NVIC_IPR4_PRI_1_Pos 8 /*!< PPB NVIC_IPR4: PRI_1 Position */
\r
861 #define PPB_NVIC_IPR4_PRI_1_Msk (0x000000ffUL << PPB_NVIC_IPR4_PRI_1_Pos) /*!< PPB NVIC_IPR4: PRI_1 Mask */
\r
862 #define PPB_NVIC_IPR4_PRI_2_Pos 16 /*!< PPB NVIC_IPR4: PRI_2 Position */
\r
863 #define PPB_NVIC_IPR4_PRI_2_Msk (0x000000ffUL << PPB_NVIC_IPR4_PRI_2_Pos) /*!< PPB NVIC_IPR4: PRI_2 Mask */
\r
864 #define PPB_NVIC_IPR4_PRI_3_Pos 24 /*!< PPB NVIC_IPR4: PRI_3 Position */
\r
865 #define PPB_NVIC_IPR4_PRI_3_Msk (0x000000ffUL << PPB_NVIC_IPR4_PRI_3_Pos) /*!< PPB NVIC_IPR4: PRI_3 Mask */
\r
867 /* -------------------------------- PPB_NVIC_IPR5 ------------------------------- */
\r
868 #define PPB_NVIC_IPR5_PRI_0_Pos 0 /*!< PPB NVIC_IPR5: PRI_0 Position */
\r
869 #define PPB_NVIC_IPR5_PRI_0_Msk (0x000000ffUL << PPB_NVIC_IPR5_PRI_0_Pos) /*!< PPB NVIC_IPR5: PRI_0 Mask */
\r
870 #define PPB_NVIC_IPR5_PRI_1_Pos 8 /*!< PPB NVIC_IPR5: PRI_1 Position */
\r
871 #define PPB_NVIC_IPR5_PRI_1_Msk (0x000000ffUL << PPB_NVIC_IPR5_PRI_1_Pos) /*!< PPB NVIC_IPR5: PRI_1 Mask */
\r
872 #define PPB_NVIC_IPR5_PRI_2_Pos 16 /*!< PPB NVIC_IPR5: PRI_2 Position */
\r
873 #define PPB_NVIC_IPR5_PRI_2_Msk (0x000000ffUL << PPB_NVIC_IPR5_PRI_2_Pos) /*!< PPB NVIC_IPR5: PRI_2 Mask */
\r
874 #define PPB_NVIC_IPR5_PRI_3_Pos 24 /*!< PPB NVIC_IPR5: PRI_3 Position */
\r
875 #define PPB_NVIC_IPR5_PRI_3_Msk (0x000000ffUL << PPB_NVIC_IPR5_PRI_3_Pos) /*!< PPB NVIC_IPR5: PRI_3 Mask */
\r
877 /* -------------------------------- PPB_NVIC_IPR6 ------------------------------- */
\r
878 #define PPB_NVIC_IPR6_PRI_0_Pos 0 /*!< PPB NVIC_IPR6: PRI_0 Position */
\r
879 #define PPB_NVIC_IPR6_PRI_0_Msk (0x000000ffUL << PPB_NVIC_IPR6_PRI_0_Pos) /*!< PPB NVIC_IPR6: PRI_0 Mask */
\r
880 #define PPB_NVIC_IPR6_PRI_1_Pos 8 /*!< PPB NVIC_IPR6: PRI_1 Position */
\r
881 #define PPB_NVIC_IPR6_PRI_1_Msk (0x000000ffUL << PPB_NVIC_IPR6_PRI_1_Pos) /*!< PPB NVIC_IPR6: PRI_1 Mask */
\r
882 #define PPB_NVIC_IPR6_PRI_2_Pos 16 /*!< PPB NVIC_IPR6: PRI_2 Position */
\r
883 #define PPB_NVIC_IPR6_PRI_2_Msk (0x000000ffUL << PPB_NVIC_IPR6_PRI_2_Pos) /*!< PPB NVIC_IPR6: PRI_2 Mask */
\r
884 #define PPB_NVIC_IPR6_PRI_3_Pos 24 /*!< PPB NVIC_IPR6: PRI_3 Position */
\r
885 #define PPB_NVIC_IPR6_PRI_3_Msk (0x000000ffUL << PPB_NVIC_IPR6_PRI_3_Pos) /*!< PPB NVIC_IPR6: PRI_3 Mask */
\r
887 /* -------------------------------- PPB_NVIC_IPR7 ------------------------------- */
\r
888 #define PPB_NVIC_IPR7_PRI_0_Pos 0 /*!< PPB NVIC_IPR7: PRI_0 Position */
\r
889 #define PPB_NVIC_IPR7_PRI_0_Msk (0x000000ffUL << PPB_NVIC_IPR7_PRI_0_Pos) /*!< PPB NVIC_IPR7: PRI_0 Mask */
\r
890 #define PPB_NVIC_IPR7_PRI_1_Pos 8 /*!< PPB NVIC_IPR7: PRI_1 Position */
\r
891 #define PPB_NVIC_IPR7_PRI_1_Msk (0x000000ffUL << PPB_NVIC_IPR7_PRI_1_Pos) /*!< PPB NVIC_IPR7: PRI_1 Mask */
\r
892 #define PPB_NVIC_IPR7_PRI_2_Pos 16 /*!< PPB NVIC_IPR7: PRI_2 Position */
\r
893 #define PPB_NVIC_IPR7_PRI_2_Msk (0x000000ffUL << PPB_NVIC_IPR7_PRI_2_Pos) /*!< PPB NVIC_IPR7: PRI_2 Mask */
\r
894 #define PPB_NVIC_IPR7_PRI_3_Pos 24 /*!< PPB NVIC_IPR7: PRI_3 Position */
\r
895 #define PPB_NVIC_IPR7_PRI_3_Msk (0x000000ffUL << PPB_NVIC_IPR7_PRI_3_Pos) /*!< PPB NVIC_IPR7: PRI_3 Mask */
\r
897 /* ---------------------------------- PPB_CPUID --------------------------------- */
\r
898 #define PPB_CPUID_Revision_Pos 0 /*!< PPB CPUID: Revision Position */
\r
899 #define PPB_CPUID_Revision_Msk (0x0fUL << PPB_CPUID_Revision_Pos) /*!< PPB CPUID: Revision Mask */
\r
900 #define PPB_CPUID_PartNo_Pos 4 /*!< PPB CPUID: PartNo Position */
\r
901 #define PPB_CPUID_PartNo_Msk (0x00000fffUL << PPB_CPUID_PartNo_Pos) /*!< PPB CPUID: PartNo Mask */
\r
902 #define PPB_CPUID_Architecture_Pos 16 /*!< PPB CPUID: Architecture Position */
\r
903 #define PPB_CPUID_Architecture_Msk (0x0fUL << PPB_CPUID_Architecture_Pos) /*!< PPB CPUID: Architecture Mask */
\r
904 #define PPB_CPUID_Variant_Pos 20 /*!< PPB CPUID: Variant Position */
\r
905 #define PPB_CPUID_Variant_Msk (0x0fUL << PPB_CPUID_Variant_Pos) /*!< PPB CPUID: Variant Mask */
\r
906 #define PPB_CPUID_Implementer_Pos 24 /*!< PPB CPUID: Implementer Position */
\r
907 #define PPB_CPUID_Implementer_Msk (0x000000ffUL << PPB_CPUID_Implementer_Pos) /*!< PPB CPUID: Implementer Mask */
\r
909 /* ---------------------------------- PPB_ICSR ---------------------------------- */
\r
910 #define PPB_ICSR_VECTACTIVE_Pos 0 /*!< PPB ICSR: VECTACTIVE Position */
\r
911 #define PPB_ICSR_VECTACTIVE_Msk (0x3fUL << PPB_ICSR_VECTACTIVE_Pos) /*!< PPB ICSR: VECTACTIVE Mask */
\r
912 #define PPB_ICSR_VECTPENDING_Pos 12 /*!< PPB ICSR: VECTPENDING Position */
\r
913 #define PPB_ICSR_VECTPENDING_Msk (0x3fUL << PPB_ICSR_VECTPENDING_Pos) /*!< PPB ICSR: VECTPENDING Mask */
\r
914 #define PPB_ICSR_ISRPENDING_Pos 22 /*!< PPB ICSR: ISRPENDING Position */
\r
915 #define PPB_ICSR_ISRPENDING_Msk (0x01UL << PPB_ICSR_ISRPENDING_Pos) /*!< PPB ICSR: ISRPENDING Mask */
\r
916 #define PPB_ICSR_PENDSTCLR_Pos 25 /*!< PPB ICSR: PENDSTCLR Position */
\r
917 #define PPB_ICSR_PENDSTCLR_Msk (0x01UL << PPB_ICSR_PENDSTCLR_Pos) /*!< PPB ICSR: PENDSTCLR Mask */
\r
918 #define PPB_ICSR_PENDSTSET_Pos 26 /*!< PPB ICSR: PENDSTSET Position */
\r
919 #define PPB_ICSR_PENDSTSET_Msk (0x01UL << PPB_ICSR_PENDSTSET_Pos) /*!< PPB ICSR: PENDSTSET Mask */
\r
920 #define PPB_ICSR_PENDSVCLR_Pos 27 /*!< PPB ICSR: PENDSVCLR Position */
\r
921 #define PPB_ICSR_PENDSVCLR_Msk (0x01UL << PPB_ICSR_PENDSVCLR_Pos) /*!< PPB ICSR: PENDSVCLR Mask */
\r
922 #define PPB_ICSR_PENDSVSET_Pos 28 /*!< PPB ICSR: PENDSVSET Position */
\r
923 #define PPB_ICSR_PENDSVSET_Msk (0x01UL << PPB_ICSR_PENDSVSET_Pos) /*!< PPB ICSR: PENDSVSET Mask */
\r
925 /* ---------------------------------- PPB_AIRCR --------------------------------- */
\r
926 #define PPB_AIRCR_SYSRESETREQ_Pos 2 /*!< PPB AIRCR: SYSRESETREQ Position */
\r
927 #define PPB_AIRCR_SYSRESETREQ_Msk (0x01UL << PPB_AIRCR_SYSRESETREQ_Pos) /*!< PPB AIRCR: SYSRESETREQ Mask */
\r
928 #define PPB_AIRCR_ENDIANNESS_Pos 15 /*!< PPB AIRCR: ENDIANNESS Position */
\r
929 #define PPB_AIRCR_ENDIANNESS_Msk (0x01UL << PPB_AIRCR_ENDIANNESS_Pos) /*!< PPB AIRCR: ENDIANNESS Mask */
\r
930 #define PPB_AIRCR_VECTKEY_Pos 16 /*!< PPB AIRCR: VECTKEY Position */
\r
931 #define PPB_AIRCR_VECTKEY_Msk (0x0000ffffUL << PPB_AIRCR_VECTKEY_Pos) /*!< PPB AIRCR: VECTKEY Mask */
\r
933 /* ----------------------------------- PPB_SCR ---------------------------------- */
\r
934 #define PPB_SCR_SLEEPONEXIT_Pos 1 /*!< PPB SCR: SLEEPONEXIT Position */
\r
935 #define PPB_SCR_SLEEPONEXIT_Msk (0x01UL << PPB_SCR_SLEEPONEXIT_Pos) /*!< PPB SCR: SLEEPONEXIT Mask */
\r
936 #define PPB_SCR_SLEEPDEEP_Pos 2 /*!< PPB SCR: SLEEPDEEP Position */
\r
937 #define PPB_SCR_SLEEPDEEP_Msk (0x01UL << PPB_SCR_SLEEPDEEP_Pos) /*!< PPB SCR: SLEEPDEEP Mask */
\r
938 #define PPB_SCR_SEVONPEND_Pos 4 /*!< PPB SCR: SEVONPEND Position */
\r
939 #define PPB_SCR_SEVONPEND_Msk (0x01UL << PPB_SCR_SEVONPEND_Pos) /*!< PPB SCR: SEVONPEND Mask */
\r
941 /* ----------------------------------- PPB_CCR ---------------------------------- */
\r
942 #define PPB_CCR_UNALIGN_TRP_Pos 3 /*!< PPB CCR: UNALIGN_TRP Position */
\r
943 #define PPB_CCR_UNALIGN_TRP_Msk (0x01UL << PPB_CCR_UNALIGN_TRP_Pos) /*!< PPB CCR: UNALIGN_TRP Mask */
\r
944 #define PPB_CCR_STKALIGN_Pos 9 /*!< PPB CCR: STKALIGN Position */
\r
945 #define PPB_CCR_STKALIGN_Msk (0x01UL << PPB_CCR_STKALIGN_Pos) /*!< PPB CCR: STKALIGN Mask */
\r
947 /* ---------------------------------- PPB_SHPR2 --------------------------------- */
\r
948 #define PPB_SHPR2_PRI_11_Pos 24 /*!< PPB SHPR2: PRI_11 Position */
\r
949 #define PPB_SHPR2_PRI_11_Msk (0x000000ffUL << PPB_SHPR2_PRI_11_Pos) /*!< PPB SHPR2: PRI_11 Mask */
\r
951 /* ---------------------------------- PPB_SHPR3 --------------------------------- */
\r
952 #define PPB_SHPR3_PRI_14_Pos 16 /*!< PPB SHPR3: PRI_14 Position */
\r
953 #define PPB_SHPR3_PRI_14_Msk (0x000000ffUL << PPB_SHPR3_PRI_14_Pos) /*!< PPB SHPR3: PRI_14 Mask */
\r
954 #define PPB_SHPR3_PRI_15_Pos 24 /*!< PPB SHPR3: PRI_15 Position */
\r
955 #define PPB_SHPR3_PRI_15_Msk (0x000000ffUL << PPB_SHPR3_PRI_15_Pos) /*!< PPB SHPR3: PRI_15 Mask */
\r
957 /* ---------------------------------- PPB_SHCSR --------------------------------- */
\r
958 #define PPB_SHCSR_SVCALLPENDED_Pos 15 /*!< PPB SHCSR: SVCALLPENDED Position */
\r
959 #define PPB_SHCSR_SVCALLPENDED_Msk (0x01UL << PPB_SHCSR_SVCALLPENDED_Pos) /*!< PPB SHCSR: SVCALLPENDED Mask */
\r
962 /* ================================================================================ */
\r
963 /* ================ Group 'ERU' Position & Mask ================ */
\r
964 /* ================================================================================ */
\r
967 /* --------------------------------- ERU_EXISEL --------------------------------- */
\r
968 #define ERU_EXISEL_EXS0A_Pos 0 /*!< ERU EXISEL: EXS0A Position */
\r
969 #define ERU_EXISEL_EXS0A_Msk (0x03UL << ERU_EXISEL_EXS0A_Pos) /*!< ERU EXISEL: EXS0A Mask */
\r
970 #define ERU_EXISEL_EXS0B_Pos 2 /*!< ERU EXISEL: EXS0B Position */
\r
971 #define ERU_EXISEL_EXS0B_Msk (0x03UL << ERU_EXISEL_EXS0B_Pos) /*!< ERU EXISEL: EXS0B Mask */
\r
972 #define ERU_EXISEL_EXS1A_Pos 4 /*!< ERU EXISEL: EXS1A Position */
\r
973 #define ERU_EXISEL_EXS1A_Msk (0x03UL << ERU_EXISEL_EXS1A_Pos) /*!< ERU EXISEL: EXS1A Mask */
\r
974 #define ERU_EXISEL_EXS1B_Pos 6 /*!< ERU EXISEL: EXS1B Position */
\r
975 #define ERU_EXISEL_EXS1B_Msk (0x03UL << ERU_EXISEL_EXS1B_Pos) /*!< ERU EXISEL: EXS1B Mask */
\r
976 #define ERU_EXISEL_EXS2A_Pos 8 /*!< ERU EXISEL: EXS2A Position */
\r
977 #define ERU_EXISEL_EXS2A_Msk (0x03UL << ERU_EXISEL_EXS2A_Pos) /*!< ERU EXISEL: EXS2A Mask */
\r
978 #define ERU_EXISEL_EXS2B_Pos 10 /*!< ERU EXISEL: EXS2B Position */
\r
979 #define ERU_EXISEL_EXS2B_Msk (0x03UL << ERU_EXISEL_EXS2B_Pos) /*!< ERU EXISEL: EXS2B Mask */
\r
980 #define ERU_EXISEL_EXS3A_Pos 12 /*!< ERU EXISEL: EXS3A Position */
\r
981 #define ERU_EXISEL_EXS3A_Msk (0x03UL << ERU_EXISEL_EXS3A_Pos) /*!< ERU EXISEL: EXS3A Mask */
\r
982 #define ERU_EXISEL_EXS3B_Pos 14 /*!< ERU EXISEL: EXS3B Position */
\r
983 #define ERU_EXISEL_EXS3B_Msk (0x03UL << ERU_EXISEL_EXS3B_Pos) /*!< ERU EXISEL: EXS3B Mask */
\r
985 /* --------------------------------- ERU_EXICON --------------------------------- */
\r
986 #define ERU_EXICON_PE_Pos 0 /*!< ERU EXICON: PE Position */
\r
987 #define ERU_EXICON_PE_Msk (0x01UL << ERU_EXICON_PE_Pos) /*!< ERU EXICON: PE Mask */
\r
988 #define ERU_EXICON_LD_Pos 1 /*!< ERU EXICON: LD Position */
\r
989 #define ERU_EXICON_LD_Msk (0x01UL << ERU_EXICON_LD_Pos) /*!< ERU EXICON: LD Mask */
\r
990 #define ERU_EXICON_RE_Pos 2 /*!< ERU EXICON: RE Position */
\r
991 #define ERU_EXICON_RE_Msk (0x01UL << ERU_EXICON_RE_Pos) /*!< ERU EXICON: RE Mask */
\r
992 #define ERU_EXICON_FE_Pos 3 /*!< ERU EXICON: FE Position */
\r
993 #define ERU_EXICON_FE_Msk (0x01UL << ERU_EXICON_FE_Pos) /*!< ERU EXICON: FE Mask */
\r
994 #define ERU_EXICON_OCS_Pos 4 /*!< ERU EXICON: OCS Position */
\r
995 #define ERU_EXICON_OCS_Msk (0x07UL << ERU_EXICON_OCS_Pos) /*!< ERU EXICON: OCS Mask */
\r
996 #define ERU_EXICON_FL_Pos 7 /*!< ERU EXICON: FL Position */
\r
997 #define ERU_EXICON_FL_Msk (0x01UL << ERU_EXICON_FL_Pos) /*!< ERU EXICON: FL Mask */
\r
998 #define ERU_EXICON_SS_Pos 8 /*!< ERU EXICON: SS Position */
\r
999 #define ERU_EXICON_SS_Msk (0x03UL << ERU_EXICON_SS_Pos) /*!< ERU EXICON: SS Mask */
\r
1000 #define ERU_EXICON_NA_Pos 10 /*!< ERU EXICON: NA Position */
\r
1001 #define ERU_EXICON_NA_Msk (0x01UL << ERU_EXICON_NA_Pos) /*!< ERU EXICON: NA Mask */
\r
1002 #define ERU_EXICON_NB_Pos 11 /*!< ERU EXICON: NB Position */
\r
1003 #define ERU_EXICON_NB_Msk (0x01UL << ERU_EXICON_NB_Pos) /*!< ERU EXICON: NB Mask */
\r
1005 /* --------------------------------- ERU_EXOCON --------------------------------- */
\r
1006 #define ERU_EXOCON_ISS_Pos 0 /*!< ERU EXOCON: ISS Position */
\r
1007 #define ERU_EXOCON_ISS_Msk (0x03UL << ERU_EXOCON_ISS_Pos) /*!< ERU EXOCON: ISS Mask */
\r
1008 #define ERU_EXOCON_GEEN_Pos 2 /*!< ERU EXOCON: GEEN Position */
\r
1009 #define ERU_EXOCON_GEEN_Msk (0x01UL << ERU_EXOCON_GEEN_Pos) /*!< ERU EXOCON: GEEN Mask */
\r
1010 #define ERU_EXOCON_PDR_Pos 3 /*!< ERU EXOCON: PDR Position */
\r
1011 #define ERU_EXOCON_PDR_Msk (0x01UL << ERU_EXOCON_PDR_Pos) /*!< ERU EXOCON: PDR Mask */
\r
1012 #define ERU_EXOCON_GP_Pos 4 /*!< ERU EXOCON: GP Position */
\r
1013 #define ERU_EXOCON_GP_Msk (0x03UL << ERU_EXOCON_GP_Pos) /*!< ERU EXOCON: GP Mask */
\r
1014 #define ERU_EXOCON_IPEN0_Pos 12 /*!< ERU EXOCON: IPEN0 Position */
\r
1015 #define ERU_EXOCON_IPEN0_Msk (0x01UL << ERU_EXOCON_IPEN0_Pos) /*!< ERU EXOCON: IPEN0 Mask */
\r
1016 #define ERU_EXOCON_IPEN1_Pos 13 /*!< ERU EXOCON: IPEN1 Position */
\r
1017 #define ERU_EXOCON_IPEN1_Msk (0x01UL << ERU_EXOCON_IPEN1_Pos) /*!< ERU EXOCON: IPEN1 Mask */
\r
1018 #define ERU_EXOCON_IPEN2_Pos 14 /*!< ERU EXOCON: IPEN2 Position */
\r
1019 #define ERU_EXOCON_IPEN2_Msk (0x01UL << ERU_EXOCON_IPEN2_Pos) /*!< ERU EXOCON: IPEN2 Mask */
\r
1020 #define ERU_EXOCON_IPEN3_Pos 15 /*!< ERU EXOCON: IPEN3 Position */
\r
1021 #define ERU_EXOCON_IPEN3_Msk (0x01UL << ERU_EXOCON_IPEN3_Pos) /*!< ERU EXOCON: IPEN3 Mask */
\r
1024 /* ================================================================================ */
\r
1025 /* ================ struct 'PAU' Position & Mask ================ */
\r
1026 /* ================================================================================ */
\r
1029 /* --------------------------------- PAU_AVAIL0 --------------------------------- */
\r
1030 #define PAU_AVAIL0_AVAIL22_Pos 22 /*!< PAU AVAIL0: AVAIL22 Position */
\r
1031 #define PAU_AVAIL0_AVAIL22_Msk (0x01UL << PAU_AVAIL0_AVAIL22_Pos) /*!< PAU AVAIL0: AVAIL22 Mask */
\r
1032 #define PAU_AVAIL0_AVAIL23_Pos 23 /*!< PAU AVAIL0: AVAIL23 Position */
\r
1033 #define PAU_AVAIL0_AVAIL23_Msk (0x01UL << PAU_AVAIL0_AVAIL23_Pos) /*!< PAU AVAIL0: AVAIL23 Mask */
\r
1034 #define PAU_AVAIL0_AVAIL24_Pos 24 /*!< PAU AVAIL0: AVAIL24 Position */
\r
1035 #define PAU_AVAIL0_AVAIL24_Msk (0x01UL << PAU_AVAIL0_AVAIL24_Pos) /*!< PAU AVAIL0: AVAIL24 Mask */
\r
1037 /* --------------------------------- PAU_AVAIL1 --------------------------------- */
\r
1038 #define PAU_AVAIL1_AVAIL0_Pos 0 /*!< PAU AVAIL1: AVAIL0 Position */
\r
1039 #define PAU_AVAIL1_AVAIL0_Msk (0x01UL << PAU_AVAIL1_AVAIL0_Pos) /*!< PAU AVAIL1: AVAIL0 Mask */
\r
1040 #define PAU_AVAIL1_AVAIL1_Pos 1 /*!< PAU AVAIL1: AVAIL1 Position */
\r
1041 #define PAU_AVAIL1_AVAIL1_Msk (0x01UL << PAU_AVAIL1_AVAIL1_Pos) /*!< PAU AVAIL1: AVAIL1 Mask */
\r
1042 #define PAU_AVAIL1_AVAIL4_Pos 4 /*!< PAU AVAIL1: AVAIL4 Position */
\r
1043 #define PAU_AVAIL1_AVAIL4_Msk (0x01UL << PAU_AVAIL1_AVAIL4_Pos) /*!< PAU AVAIL1: AVAIL4 Mask */
\r
1044 #define PAU_AVAIL1_AVAIL5_Pos 5 /*!< PAU AVAIL1: AVAIL5 Position */
\r
1045 #define PAU_AVAIL1_AVAIL5_Msk (0x01UL << PAU_AVAIL1_AVAIL5_Pos) /*!< PAU AVAIL1: AVAIL5 Mask */
\r
1046 #define PAU_AVAIL1_AVAIL8_Pos 8 /*!< PAU AVAIL1: AVAIL8 Position */
\r
1047 #define PAU_AVAIL1_AVAIL8_Msk (0x01UL << PAU_AVAIL1_AVAIL8_Pos) /*!< PAU AVAIL1: AVAIL8 Mask */
\r
1048 #define PAU_AVAIL1_AVAIL9_Pos 9 /*!< PAU AVAIL1: AVAIL9 Position */
\r
1049 #define PAU_AVAIL1_AVAIL9_Msk (0x01UL << PAU_AVAIL1_AVAIL9_Pos) /*!< PAU AVAIL1: AVAIL9 Mask */
\r
1050 #define PAU_AVAIL1_AVAIL10_Pos 10 /*!< PAU AVAIL1: AVAIL10 Position */
\r
1051 #define PAU_AVAIL1_AVAIL10_Msk (0x01UL << PAU_AVAIL1_AVAIL10_Pos) /*!< PAU AVAIL1: AVAIL10 Mask */
\r
1052 #define PAU_AVAIL1_AVAIL11_Pos 11 /*!< PAU AVAIL1: AVAIL11 Position */
\r
1053 #define PAU_AVAIL1_AVAIL11_Msk (0x01UL << PAU_AVAIL1_AVAIL11_Pos) /*!< PAU AVAIL1: AVAIL11 Mask */
\r
1054 #define PAU_AVAIL1_AVAIL12_Pos 12 /*!< PAU AVAIL1: AVAIL12 Position */
\r
1055 #define PAU_AVAIL1_AVAIL12_Msk (0x01UL << PAU_AVAIL1_AVAIL12_Pos) /*!< PAU AVAIL1: AVAIL12 Mask */
\r
1057 /* -------------------------------- PAU_PRIVDIS0 -------------------------------- */
\r
1058 #define PAU_PRIVDIS0_PDIS2_Pos 2 /*!< PAU PRIVDIS0: PDIS2 Position */
\r
1059 #define PAU_PRIVDIS0_PDIS2_Msk (0x01UL << PAU_PRIVDIS0_PDIS2_Pos) /*!< PAU PRIVDIS0: PDIS2 Mask */
\r
1060 #define PAU_PRIVDIS0_PDIS5_Pos 5 /*!< PAU PRIVDIS0: PDIS5 Position */
\r
1061 #define PAU_PRIVDIS0_PDIS5_Msk (0x01UL << PAU_PRIVDIS0_PDIS5_Pos) /*!< PAU PRIVDIS0: PDIS5 Mask */
\r
1062 #define PAU_PRIVDIS0_PDIS6_Pos 6 /*!< PAU PRIVDIS0: PDIS6 Position */
\r
1063 #define PAU_PRIVDIS0_PDIS6_Msk (0x01UL << PAU_PRIVDIS0_PDIS6_Pos) /*!< PAU PRIVDIS0: PDIS6 Mask */
\r
1064 #define PAU_PRIVDIS0_PDIS7_Pos 7 /*!< PAU PRIVDIS0: PDIS7 Position */
\r
1065 #define PAU_PRIVDIS0_PDIS7_Msk (0x01UL << PAU_PRIVDIS0_PDIS7_Pos) /*!< PAU PRIVDIS0: PDIS7 Mask */
\r
1066 #define PAU_PRIVDIS0_PDIS19_Pos 19 /*!< PAU PRIVDIS0: PDIS19 Position */
\r
1067 #define PAU_PRIVDIS0_PDIS19_Msk (0x01UL << PAU_PRIVDIS0_PDIS19_Pos) /*!< PAU PRIVDIS0: PDIS19 Mask */
\r
1068 #define PAU_PRIVDIS0_PDIS22_Pos 22 /*!< PAU PRIVDIS0: PDIS22 Position */
\r
1069 #define PAU_PRIVDIS0_PDIS22_Msk (0x01UL << PAU_PRIVDIS0_PDIS22_Pos) /*!< PAU PRIVDIS0: PDIS22 Mask */
\r
1070 #define PAU_PRIVDIS0_PDIS23_Pos 23 /*!< PAU PRIVDIS0: PDIS23 Position */
\r
1071 #define PAU_PRIVDIS0_PDIS23_Msk (0x01UL << PAU_PRIVDIS0_PDIS23_Pos) /*!< PAU PRIVDIS0: PDIS23 Mask */
\r
1072 #define PAU_PRIVDIS0_PDIS24_Pos 24 /*!< PAU PRIVDIS0: PDIS24 Position */
\r
1073 #define PAU_PRIVDIS0_PDIS24_Msk (0x01UL << PAU_PRIVDIS0_PDIS24_Pos) /*!< PAU PRIVDIS0: PDIS24 Mask */
\r
1075 /* -------------------------------- PAU_PRIVDIS1 -------------------------------- */
\r
1076 #define PAU_PRIVDIS1_PDIS0_Pos 0 /*!< PAU PRIVDIS1: PDIS0 Position */
\r
1077 #define PAU_PRIVDIS1_PDIS0_Msk (0x01UL << PAU_PRIVDIS1_PDIS0_Pos) /*!< PAU PRIVDIS1: PDIS0 Mask */
\r
1078 #define PAU_PRIVDIS1_PDIS1_Pos 1 /*!< PAU PRIVDIS1: PDIS1 Position */
\r
1079 #define PAU_PRIVDIS1_PDIS1_Msk (0x01UL << PAU_PRIVDIS1_PDIS1_Pos) /*!< PAU PRIVDIS1: PDIS1 Mask */
\r
1080 #define PAU_PRIVDIS1_PDIS5_Pos 5 /*!< PAU PRIVDIS1: PDIS5 Position */
\r
1081 #define PAU_PRIVDIS1_PDIS5_Msk (0x01UL << PAU_PRIVDIS1_PDIS5_Pos) /*!< PAU PRIVDIS1: PDIS5 Mask */
\r
1082 #define PAU_PRIVDIS1_PDIS8_Pos 8 /*!< PAU PRIVDIS1: PDIS8 Position */
\r
1083 #define PAU_PRIVDIS1_PDIS8_Msk (0x01UL << PAU_PRIVDIS1_PDIS8_Pos) /*!< PAU PRIVDIS1: PDIS8 Mask */
\r
1084 #define PAU_PRIVDIS1_PDIS9_Pos 9 /*!< PAU PRIVDIS1: PDIS9 Position */
\r
1085 #define PAU_PRIVDIS1_PDIS9_Msk (0x01UL << PAU_PRIVDIS1_PDIS9_Pos) /*!< PAU PRIVDIS1: PDIS9 Mask */
\r
1086 #define PAU_PRIVDIS1_PDIS10_Pos 10 /*!< PAU PRIVDIS1: PDIS10 Position */
\r
1087 #define PAU_PRIVDIS1_PDIS10_Msk (0x01UL << PAU_PRIVDIS1_PDIS10_Pos) /*!< PAU PRIVDIS1: PDIS10 Mask */
\r
1088 #define PAU_PRIVDIS1_PDIS11_Pos 11 /*!< PAU PRIVDIS1: PDIS11 Position */
\r
1089 #define PAU_PRIVDIS1_PDIS11_Msk (0x01UL << PAU_PRIVDIS1_PDIS11_Pos) /*!< PAU PRIVDIS1: PDIS11 Mask */
\r
1090 #define PAU_PRIVDIS1_PDIS12_Pos 12 /*!< PAU PRIVDIS1: PDIS12 Position */
\r
1091 #define PAU_PRIVDIS1_PDIS12_Msk (0x01UL << PAU_PRIVDIS1_PDIS12_Pos) /*!< PAU PRIVDIS1: PDIS12 Mask */
\r
1093 /* --------------------------------- PAU_ROMSIZE -------------------------------- */
\r
1094 #define PAU_ROMSIZE_ADDR_Pos 8 /*!< PAU ROMSIZE: ADDR Position */
\r
1095 #define PAU_ROMSIZE_ADDR_Msk (0x3fUL << PAU_ROMSIZE_ADDR_Pos) /*!< PAU ROMSIZE: ADDR Mask */
\r
1097 /* --------------------------------- PAU_FLSIZE --------------------------------- */
\r
1098 #define PAU_FLSIZE_ADDR_Pos 12 /*!< PAU FLSIZE: ADDR Position */
\r
1099 #define PAU_FLSIZE_ADDR_Msk (0x3fUL << PAU_FLSIZE_ADDR_Pos) /*!< PAU FLSIZE: ADDR Mask */
\r
1101 /* -------------------------------- PAU_RAM0SIZE -------------------------------- */
\r
1102 #define PAU_RAM0SIZE_ADDR_Pos 8 /*!< PAU RAM0SIZE: ADDR Position */
\r
1103 #define PAU_RAM0SIZE_ADDR_Msk (0x1fUL << PAU_RAM0SIZE_ADDR_Pos) /*!< PAU RAM0SIZE: ADDR Mask */
\r
1106 /* ================================================================================ */
\r
1107 /* ================ struct 'NVM' Position & Mask ================ */
\r
1108 /* ================================================================================ */
\r
1111 /* -------------------------------- NVM_NVMSTATUS ------------------------------- */
\r
1112 #define NVM_NVMSTATUS_BUSY_Pos 0 /*!< NVM NVMSTATUS: BUSY Position */
\r
1113 #define NVM_NVMSTATUS_BUSY_Msk (0x01UL << NVM_NVMSTATUS_BUSY_Pos) /*!< NVM NVMSTATUS: BUSY Mask */
\r
1114 #define NVM_NVMSTATUS_SLEEP_Pos 1 /*!< NVM NVMSTATUS: SLEEP Position */
\r
1115 #define NVM_NVMSTATUS_SLEEP_Msk (0x01UL << NVM_NVMSTATUS_SLEEP_Pos) /*!< NVM NVMSTATUS: SLEEP Mask */
\r
1116 #define NVM_NVMSTATUS_VERR_Pos 2 /*!< NVM NVMSTATUS: VERR Position */
\r
1117 #define NVM_NVMSTATUS_VERR_Msk (0x03UL << NVM_NVMSTATUS_VERR_Pos) /*!< NVM NVMSTATUS: VERR Mask */
\r
1118 #define NVM_NVMSTATUS_ECC1READ_Pos 4 /*!< NVM NVMSTATUS: ECC1READ Position */
\r
1119 #define NVM_NVMSTATUS_ECC1READ_Msk (0x01UL << NVM_NVMSTATUS_ECC1READ_Pos) /*!< NVM NVMSTATUS: ECC1READ Mask */
\r
1120 #define NVM_NVMSTATUS_ECC2READ_Pos 5 /*!< NVM NVMSTATUS: ECC2READ Position */
\r
1121 #define NVM_NVMSTATUS_ECC2READ_Msk (0x01UL << NVM_NVMSTATUS_ECC2READ_Pos) /*!< NVM NVMSTATUS: ECC2READ Mask */
\r
1122 #define NVM_NVMSTATUS_WRPERR_Pos 6 /*!< NVM NVMSTATUS: WRPERR Position */
\r
1123 #define NVM_NVMSTATUS_WRPERR_Msk (0x01UL << NVM_NVMSTATUS_WRPERR_Pos) /*!< NVM NVMSTATUS: WRPERR Mask */
\r
1125 /* --------------------------------- NVM_NVMPROG -------------------------------- */
\r
1126 #define NVM_NVMPROG_ACTION_Pos 0 /*!< NVM NVMPROG: ACTION Position */
\r
1127 #define NVM_NVMPROG_ACTION_Msk (0x000000ffUL << NVM_NVMPROG_ACTION_Pos) /*!< NVM NVMPROG: ACTION Mask */
\r
1128 #define NVM_NVMPROG_RSTVERR_Pos 12 /*!< NVM NVMPROG: RSTVERR Position */
\r
1129 #define NVM_NVMPROG_RSTVERR_Msk (0x01UL << NVM_NVMPROG_RSTVERR_Pos) /*!< NVM NVMPROG: RSTVERR Mask */
\r
1130 #define NVM_NVMPROG_RSTECC_Pos 13 /*!< NVM NVMPROG: RSTECC Position */
\r
1131 #define NVM_NVMPROG_RSTECC_Msk (0x01UL << NVM_NVMPROG_RSTECC_Pos) /*!< NVM NVMPROG: RSTECC Mask */
\r
1133 /* --------------------------------- NVM_NVMCONF -------------------------------- */
\r
1134 #define NVM_NVMCONF_HRLEV_Pos 1 /*!< NVM NVMCONF: HRLEV Position */
\r
1135 #define NVM_NVMCONF_HRLEV_Msk (0x03UL << NVM_NVMCONF_HRLEV_Pos) /*!< NVM NVMCONF: HRLEV Mask */
\r
1136 #define NVM_NVMCONF_SECPROT_Pos 4 /*!< NVM NVMCONF: SECPROT Position */
\r
1137 #define NVM_NVMCONF_SECPROT_Msk (0x000000ffUL << NVM_NVMCONF_SECPROT_Pos) /*!< NVM NVMCONF: SECPROT Mask */
\r
1138 #define NVM_NVMCONF_INT_ON_Pos 14 /*!< NVM NVMCONF: INT_ON Position */
\r
1139 #define NVM_NVMCONF_INT_ON_Msk (0x01UL << NVM_NVMCONF_INT_ON_Pos) /*!< NVM NVMCONF: INT_ON Mask */
\r
1140 #define NVM_NVMCONF_NVM_ON_Pos 15 /*!< NVM NVMCONF: NVM_ON Position */
\r
1141 #define NVM_NVMCONF_NVM_ON_Msk (0x01UL << NVM_NVMCONF_NVM_ON_Pos) /*!< NVM NVMCONF: NVM_ON Mask */
\r
1144 /* ================================================================================ */
\r
1145 /* ================ struct 'WDT' Position & Mask ================ */
\r
1146 /* ================================================================================ */
\r
1149 /* ----------------------------------- WDT_ID ----------------------------------- */
\r
1150 #define WDT_ID_MOD_REV_Pos 0 /*!< WDT ID: MOD_REV Position */
\r
1151 #define WDT_ID_MOD_REV_Msk (0x000000ffUL << WDT_ID_MOD_REV_Pos) /*!< WDT ID: MOD_REV Mask */
\r
1152 #define WDT_ID_MOD_TYPE_Pos 8 /*!< WDT ID: MOD_TYPE Position */
\r
1153 #define WDT_ID_MOD_TYPE_Msk (0x000000ffUL << WDT_ID_MOD_TYPE_Pos) /*!< WDT ID: MOD_TYPE Mask */
\r
1154 #define WDT_ID_MOD_NUMBER_Pos 16 /*!< WDT ID: MOD_NUMBER Position */
\r
1155 #define WDT_ID_MOD_NUMBER_Msk (0x0000ffffUL << WDT_ID_MOD_NUMBER_Pos) /*!< WDT ID: MOD_NUMBER Mask */
\r
1157 /* ----------------------------------- WDT_CTR ---------------------------------- */
\r
1158 #define WDT_CTR_ENB_Pos 0 /*!< WDT CTR: ENB Position */
\r
1159 #define WDT_CTR_ENB_Msk (0x01UL << WDT_CTR_ENB_Pos) /*!< WDT CTR: ENB Mask */
\r
1160 #define WDT_CTR_PRE_Pos 1 /*!< WDT CTR: PRE Position */
\r
1161 #define WDT_CTR_PRE_Msk (0x01UL << WDT_CTR_PRE_Pos) /*!< WDT CTR: PRE Mask */
\r
1162 #define WDT_CTR_DSP_Pos 4 /*!< WDT CTR: DSP Position */
\r
1163 #define WDT_CTR_DSP_Msk (0x01UL << WDT_CTR_DSP_Pos) /*!< WDT CTR: DSP Mask */
\r
1164 #define WDT_CTR_SPW_Pos 8 /*!< WDT CTR: SPW Position */
\r
1165 #define WDT_CTR_SPW_Msk (0x000000ffUL << WDT_CTR_SPW_Pos) /*!< WDT CTR: SPW Mask */
\r
1167 /* ----------------------------------- WDT_SRV ---------------------------------- */
\r
1168 #define WDT_SRV_SRV_Pos 0 /*!< WDT SRV: SRV Position */
\r
1169 #define WDT_SRV_SRV_Msk (0xffffffffUL << WDT_SRV_SRV_Pos) /*!< WDT SRV: SRV Mask */
\r
1171 /* ----------------------------------- WDT_TIM ---------------------------------- */
\r
1172 #define WDT_TIM_TIM_Pos 0 /*!< WDT TIM: TIM Position */
\r
1173 #define WDT_TIM_TIM_Msk (0xffffffffUL << WDT_TIM_TIM_Pos) /*!< WDT TIM: TIM Mask */
\r
1175 /* ----------------------------------- WDT_WLB ---------------------------------- */
\r
1176 #define WDT_WLB_WLB_Pos 0 /*!< WDT WLB: WLB Position */
\r
1177 #define WDT_WLB_WLB_Msk (0xffffffffUL << WDT_WLB_WLB_Pos) /*!< WDT WLB: WLB Mask */
\r
1179 /* ----------------------------------- WDT_WUB ---------------------------------- */
\r
1180 #define WDT_WUB_WUB_Pos 0 /*!< WDT WUB: WUB Position */
\r
1181 #define WDT_WUB_WUB_Msk (0xffffffffUL << WDT_WUB_WUB_Pos) /*!< WDT WUB: WUB Mask */
\r
1183 /* --------------------------------- WDT_WDTSTS --------------------------------- */
\r
1184 #define WDT_WDTSTS_ALMS_Pos 0 /*!< WDT WDTSTS: ALMS Position */
\r
1185 #define WDT_WDTSTS_ALMS_Msk (0x01UL << WDT_WDTSTS_ALMS_Pos) /*!< WDT WDTSTS: ALMS Mask */
\r
1187 /* --------------------------------- WDT_WDTCLR --------------------------------- */
\r
1188 #define WDT_WDTCLR_ALMC_Pos 0 /*!< WDT WDTCLR: ALMC Position */
\r
1189 #define WDT_WDTCLR_ALMC_Msk (0x01UL << WDT_WDTCLR_ALMC_Pos) /*!< WDT WDTCLR: ALMC Mask */
\r
1192 /* ================================================================================ */
\r
1193 /* ================ struct 'RTC' Position & Mask ================ */
\r
1194 /* ================================================================================ */
\r
1197 /* ----------------------------------- RTC_ID ----------------------------------- */
\r
1198 #define RTC_ID_MOD_REV_Pos 0 /*!< RTC ID: MOD_REV Position */
\r
1199 #define RTC_ID_MOD_REV_Msk (0x000000ffUL << RTC_ID_MOD_REV_Pos) /*!< RTC ID: MOD_REV Mask */
\r
1200 #define RTC_ID_MOD_TYPE_Pos 8 /*!< RTC ID: MOD_TYPE Position */
\r
1201 #define RTC_ID_MOD_TYPE_Msk (0x000000ffUL << RTC_ID_MOD_TYPE_Pos) /*!< RTC ID: MOD_TYPE Mask */
\r
1202 #define RTC_ID_MOD_NUMBER_Pos 16 /*!< RTC ID: MOD_NUMBER Position */
\r
1203 #define RTC_ID_MOD_NUMBER_Msk (0x0000ffffUL << RTC_ID_MOD_NUMBER_Pos) /*!< RTC ID: MOD_NUMBER Mask */
\r
1205 /* ----------------------------------- RTC_CTR ---------------------------------- */
\r
1206 #define RTC_CTR_ENB_Pos 0 /*!< RTC CTR: ENB Position */
\r
1207 #define RTC_CTR_ENB_Msk (0x01UL << RTC_CTR_ENB_Pos) /*!< RTC CTR: ENB Mask */
\r
1208 #define RTC_CTR_SUS_Pos 1 /*!< RTC CTR: SUS Position */
\r
1209 #define RTC_CTR_SUS_Msk (0x01UL << RTC_CTR_SUS_Pos) /*!< RTC CTR: SUS Mask */
\r
1210 #define RTC_CTR_DIV_Pos 16 /*!< RTC CTR: DIV Position */
\r
1211 #define RTC_CTR_DIV_Msk (0x0000ffffUL << RTC_CTR_DIV_Pos) /*!< RTC CTR: DIV Mask */
\r
1213 /* --------------------------------- RTC_RAWSTAT -------------------------------- */
\r
1214 #define RTC_RAWSTAT_RPSE_Pos 0 /*!< RTC RAWSTAT: RPSE Position */
\r
1215 #define RTC_RAWSTAT_RPSE_Msk (0x01UL << RTC_RAWSTAT_RPSE_Pos) /*!< RTC RAWSTAT: RPSE Mask */
\r
1216 #define RTC_RAWSTAT_RPMI_Pos 1 /*!< RTC RAWSTAT: RPMI Position */
\r
1217 #define RTC_RAWSTAT_RPMI_Msk (0x01UL << RTC_RAWSTAT_RPMI_Pos) /*!< RTC RAWSTAT: RPMI Mask */
\r
1218 #define RTC_RAWSTAT_RPHO_Pos 2 /*!< RTC RAWSTAT: RPHO Position */
\r
1219 #define RTC_RAWSTAT_RPHO_Msk (0x01UL << RTC_RAWSTAT_RPHO_Pos) /*!< RTC RAWSTAT: RPHO Mask */
\r
1220 #define RTC_RAWSTAT_RPDA_Pos 3 /*!< RTC RAWSTAT: RPDA Position */
\r
1221 #define RTC_RAWSTAT_RPDA_Msk (0x01UL << RTC_RAWSTAT_RPDA_Pos) /*!< RTC RAWSTAT: RPDA Mask */
\r
1222 #define RTC_RAWSTAT_RPMO_Pos 5 /*!< RTC RAWSTAT: RPMO Position */
\r
1223 #define RTC_RAWSTAT_RPMO_Msk (0x01UL << RTC_RAWSTAT_RPMO_Pos) /*!< RTC RAWSTAT: RPMO Mask */
\r
1224 #define RTC_RAWSTAT_RPYE_Pos 6 /*!< RTC RAWSTAT: RPYE Position */
\r
1225 #define RTC_RAWSTAT_RPYE_Msk (0x01UL << RTC_RAWSTAT_RPYE_Pos) /*!< RTC RAWSTAT: RPYE Mask */
\r
1226 #define RTC_RAWSTAT_RAI_Pos 8 /*!< RTC RAWSTAT: RAI Position */
\r
1227 #define RTC_RAWSTAT_RAI_Msk (0x01UL << RTC_RAWSTAT_RAI_Pos) /*!< RTC RAWSTAT: RAI Mask */
\r
1229 /* ---------------------------------- RTC_STSSR --------------------------------- */
\r
1230 #define RTC_STSSR_SPSE_Pos 0 /*!< RTC STSSR: SPSE Position */
\r
1231 #define RTC_STSSR_SPSE_Msk (0x01UL << RTC_STSSR_SPSE_Pos) /*!< RTC STSSR: SPSE Mask */
\r
1232 #define RTC_STSSR_SPMI_Pos 1 /*!< RTC STSSR: SPMI Position */
\r
1233 #define RTC_STSSR_SPMI_Msk (0x01UL << RTC_STSSR_SPMI_Pos) /*!< RTC STSSR: SPMI Mask */
\r
1234 #define RTC_STSSR_SPHO_Pos 2 /*!< RTC STSSR: SPHO Position */
\r
1235 #define RTC_STSSR_SPHO_Msk (0x01UL << RTC_STSSR_SPHO_Pos) /*!< RTC STSSR: SPHO Mask */
\r
1236 #define RTC_STSSR_SPDA_Pos 3 /*!< RTC STSSR: SPDA Position */
\r
1237 #define RTC_STSSR_SPDA_Msk (0x01UL << RTC_STSSR_SPDA_Pos) /*!< RTC STSSR: SPDA Mask */
\r
1238 #define RTC_STSSR_SPMO_Pos 5 /*!< RTC STSSR: SPMO Position */
\r
1239 #define RTC_STSSR_SPMO_Msk (0x01UL << RTC_STSSR_SPMO_Pos) /*!< RTC STSSR: SPMO Mask */
\r
1240 #define RTC_STSSR_SPYE_Pos 6 /*!< RTC STSSR: SPYE Position */
\r
1241 #define RTC_STSSR_SPYE_Msk (0x01UL << RTC_STSSR_SPYE_Pos) /*!< RTC STSSR: SPYE Mask */
\r
1242 #define RTC_STSSR_SAI_Pos 8 /*!< RTC STSSR: SAI Position */
\r
1243 #define RTC_STSSR_SAI_Msk (0x01UL << RTC_STSSR_SAI_Pos) /*!< RTC STSSR: SAI Mask */
\r
1245 /* ---------------------------------- RTC_MSKSR --------------------------------- */
\r
1246 #define RTC_MSKSR_MPSE_Pos 0 /*!< RTC MSKSR: MPSE Position */
\r
1247 #define RTC_MSKSR_MPSE_Msk (0x01UL << RTC_MSKSR_MPSE_Pos) /*!< RTC MSKSR: MPSE Mask */
\r
1248 #define RTC_MSKSR_MPMI_Pos 1 /*!< RTC MSKSR: MPMI Position */
\r
1249 #define RTC_MSKSR_MPMI_Msk (0x01UL << RTC_MSKSR_MPMI_Pos) /*!< RTC MSKSR: MPMI Mask */
\r
1250 #define RTC_MSKSR_MPHO_Pos 2 /*!< RTC MSKSR: MPHO Position */
\r
1251 #define RTC_MSKSR_MPHO_Msk (0x01UL << RTC_MSKSR_MPHO_Pos) /*!< RTC MSKSR: MPHO Mask */
\r
1252 #define RTC_MSKSR_MPDA_Pos 3 /*!< RTC MSKSR: MPDA Position */
\r
1253 #define RTC_MSKSR_MPDA_Msk (0x01UL << RTC_MSKSR_MPDA_Pos) /*!< RTC MSKSR: MPDA Mask */
\r
1254 #define RTC_MSKSR_MPMO_Pos 5 /*!< RTC MSKSR: MPMO Position */
\r
1255 #define RTC_MSKSR_MPMO_Msk (0x01UL << RTC_MSKSR_MPMO_Pos) /*!< RTC MSKSR: MPMO Mask */
\r
1256 #define RTC_MSKSR_MPYE_Pos 6 /*!< RTC MSKSR: MPYE Position */
\r
1257 #define RTC_MSKSR_MPYE_Msk (0x01UL << RTC_MSKSR_MPYE_Pos) /*!< RTC MSKSR: MPYE Mask */
\r
1258 #define RTC_MSKSR_MAI_Pos 8 /*!< RTC MSKSR: MAI Position */
\r
1259 #define RTC_MSKSR_MAI_Msk (0x01UL << RTC_MSKSR_MAI_Pos) /*!< RTC MSKSR: MAI Mask */
\r
1261 /* ---------------------------------- RTC_CLRSR --------------------------------- */
\r
1262 #define RTC_CLRSR_RPSE_Pos 0 /*!< RTC CLRSR: RPSE Position */
\r
1263 #define RTC_CLRSR_RPSE_Msk (0x01UL << RTC_CLRSR_RPSE_Pos) /*!< RTC CLRSR: RPSE Mask */
\r
1264 #define RTC_CLRSR_RPMI_Pos 1 /*!< RTC CLRSR: RPMI Position */
\r
1265 #define RTC_CLRSR_RPMI_Msk (0x01UL << RTC_CLRSR_RPMI_Pos) /*!< RTC CLRSR: RPMI Mask */
\r
1266 #define RTC_CLRSR_RPHO_Pos 2 /*!< RTC CLRSR: RPHO Position */
\r
1267 #define RTC_CLRSR_RPHO_Msk (0x01UL << RTC_CLRSR_RPHO_Pos) /*!< RTC CLRSR: RPHO Mask */
\r
1268 #define RTC_CLRSR_RPDA_Pos 3 /*!< RTC CLRSR: RPDA Position */
\r
1269 #define RTC_CLRSR_RPDA_Msk (0x01UL << RTC_CLRSR_RPDA_Pos) /*!< RTC CLRSR: RPDA Mask */
\r
1270 #define RTC_CLRSR_RPMO_Pos 5 /*!< RTC CLRSR: RPMO Position */
\r
1271 #define RTC_CLRSR_RPMO_Msk (0x01UL << RTC_CLRSR_RPMO_Pos) /*!< RTC CLRSR: RPMO Mask */
\r
1272 #define RTC_CLRSR_RPYE_Pos 6 /*!< RTC CLRSR: RPYE Position */
\r
1273 #define RTC_CLRSR_RPYE_Msk (0x01UL << RTC_CLRSR_RPYE_Pos) /*!< RTC CLRSR: RPYE Mask */
\r
1274 #define RTC_CLRSR_RAI_Pos 8 /*!< RTC CLRSR: RAI Position */
\r
1275 #define RTC_CLRSR_RAI_Msk (0x01UL << RTC_CLRSR_RAI_Pos) /*!< RTC CLRSR: RAI Mask */
\r
1277 /* ---------------------------------- RTC_ATIM0 --------------------------------- */
\r
1278 #define RTC_ATIM0_ASE_Pos 0 /*!< RTC ATIM0: ASE Position */
\r
1279 #define RTC_ATIM0_ASE_Msk (0x3fUL << RTC_ATIM0_ASE_Pos) /*!< RTC ATIM0: ASE Mask */
\r
1280 #define RTC_ATIM0_AMI_Pos 8 /*!< RTC ATIM0: AMI Position */
\r
1281 #define RTC_ATIM0_AMI_Msk (0x3fUL << RTC_ATIM0_AMI_Pos) /*!< RTC ATIM0: AMI Mask */
\r
1282 #define RTC_ATIM0_AHO_Pos 16 /*!< RTC ATIM0: AHO Position */
\r
1283 #define RTC_ATIM0_AHO_Msk (0x1fUL << RTC_ATIM0_AHO_Pos) /*!< RTC ATIM0: AHO Mask */
\r
1284 #define RTC_ATIM0_ADA_Pos 24 /*!< RTC ATIM0: ADA Position */
\r
1285 #define RTC_ATIM0_ADA_Msk (0x1fUL << RTC_ATIM0_ADA_Pos) /*!< RTC ATIM0: ADA Mask */
\r
1287 /* ---------------------------------- RTC_ATIM1 --------------------------------- */
\r
1288 #define RTC_ATIM1_AMO_Pos 8 /*!< RTC ATIM1: AMO Position */
\r
1289 #define RTC_ATIM1_AMO_Msk (0x0fUL << RTC_ATIM1_AMO_Pos) /*!< RTC ATIM1: AMO Mask */
\r
1290 #define RTC_ATIM1_AYE_Pos 16 /*!< RTC ATIM1: AYE Position */
\r
1291 #define RTC_ATIM1_AYE_Msk (0x0000ffffUL << RTC_ATIM1_AYE_Pos) /*!< RTC ATIM1: AYE Mask */
\r
1293 /* ---------------------------------- RTC_TIM0 ---------------------------------- */
\r
1294 #define RTC_TIM0_SE_Pos 0 /*!< RTC TIM0: SE Position */
\r
1295 #define RTC_TIM0_SE_Msk (0x3fUL << RTC_TIM0_SE_Pos) /*!< RTC TIM0: SE Mask */
\r
1296 #define RTC_TIM0_MI_Pos 8 /*!< RTC TIM0: MI Position */
\r
1297 #define RTC_TIM0_MI_Msk (0x3fUL << RTC_TIM0_MI_Pos) /*!< RTC TIM0: MI Mask */
\r
1298 #define RTC_TIM0_HO_Pos 16 /*!< RTC TIM0: HO Position */
\r
1299 #define RTC_TIM0_HO_Msk (0x1fUL << RTC_TIM0_HO_Pos) /*!< RTC TIM0: HO Mask */
\r
1300 #define RTC_TIM0_DA_Pos 24 /*!< RTC TIM0: DA Position */
\r
1301 #define RTC_TIM0_DA_Msk (0x1fUL << RTC_TIM0_DA_Pos) /*!< RTC TIM0: DA Mask */
\r
1303 /* ---------------------------------- RTC_TIM1 ---------------------------------- */
\r
1304 #define RTC_TIM1_DAWE_Pos 0 /*!< RTC TIM1: DAWE Position */
\r
1305 #define RTC_TIM1_DAWE_Msk (0x07UL << RTC_TIM1_DAWE_Pos) /*!< RTC TIM1: DAWE Mask */
\r
1306 #define RTC_TIM1_MO_Pos 8 /*!< RTC TIM1: MO Position */
\r
1307 #define RTC_TIM1_MO_Msk (0x0fUL << RTC_TIM1_MO_Pos) /*!< RTC TIM1: MO Mask */
\r
1308 #define RTC_TIM1_YE_Pos 16 /*!< RTC TIM1: YE Position */
\r
1309 #define RTC_TIM1_YE_Msk (0x0000ffffUL << RTC_TIM1_YE_Pos) /*!< RTC TIM1: YE Mask */
\r
1312 /* ================================================================================ */
\r
1313 /* ================ struct 'PRNG' Position & Mask ================ */
\r
1314 /* ================================================================================ */
\r
1317 /* ---------------------------------- PRNG_WORD --------------------------------- */
\r
1318 #define PRNG_WORD_RDATA_Pos 0 /*!< PRNG WORD: RDATA Position */
\r
1319 #define PRNG_WORD_RDATA_Msk (0x0000ffffUL << PRNG_WORD_RDATA_Pos) /*!< PRNG WORD: RDATA Mask */
\r
1321 /* ---------------------------------- PRNG_CHK ---------------------------------- */
\r
1322 #define PRNG_CHK_RDV_Pos 0 /*!< PRNG CHK: RDV Position */
\r
1323 #define PRNG_CHK_RDV_Msk (0x01UL << PRNG_CHK_RDV_Pos) /*!< PRNG CHK: RDV Mask */
\r
1325 /* ---------------------------------- PRNG_CTRL --------------------------------- */
\r
1326 #define PRNG_CTRL_RDBS_Pos 1 /*!< PRNG CTRL: RDBS Position */
\r
1327 #define PRNG_CTRL_RDBS_Msk (0x03UL << PRNG_CTRL_RDBS_Pos) /*!< PRNG CTRL: RDBS Mask */
\r
1328 #define PRNG_CTRL_KLD_Pos 3 /*!< PRNG CTRL: KLD Position */
\r
1329 #define PRNG_CTRL_KLD_Msk (0x01UL << PRNG_CTRL_KLD_Pos) /*!< PRNG CTRL: KLD Mask */
\r
1332 /* ================================================================================ */
\r
1333 /* ================ Group 'USIC' Position & Mask ================ */
\r
1334 /* ================================================================================ */
\r
1337 /* ----------------------------------- USIC_ID ---------------------------------- */
\r
1338 #define USIC_ID_MOD_REV_Pos 0 /*!< USIC ID: MOD_REV Position */
\r
1339 #define USIC_ID_MOD_REV_Msk (0x000000ffUL << USIC_ID_MOD_REV_Pos) /*!< USIC ID: MOD_REV Mask */
\r
1340 #define USIC_ID_MOD_TYPE_Pos 8 /*!< USIC ID: MOD_TYPE Position */
\r
1341 #define USIC_ID_MOD_TYPE_Msk (0x000000ffUL << USIC_ID_MOD_TYPE_Pos) /*!< USIC ID: MOD_TYPE Mask */
\r
1342 #define USIC_ID_MOD_NUMBER_Pos 16 /*!< USIC ID: MOD_NUMBER Position */
\r
1343 #define USIC_ID_MOD_NUMBER_Msk (0x0000ffffUL << USIC_ID_MOD_NUMBER_Pos) /*!< USIC ID: MOD_NUMBER Mask */
\r
1346 /* ================================================================================ */
\r
1347 /* ================ Group 'USIC_CH' Position & Mask ================ */
\r
1348 /* ================================================================================ */
\r
1351 /* -------------------------------- USIC_CH_CCFG -------------------------------- */
\r
1352 #define USIC_CH_CCFG_SSC_Pos 0 /*!< USIC_CH CCFG: SSC Position */
\r
1353 #define USIC_CH_CCFG_SSC_Msk (0x01UL << USIC_CH_CCFG_SSC_Pos) /*!< USIC_CH CCFG: SSC Mask */
\r
1354 #define USIC_CH_CCFG_ASC_Pos 1 /*!< USIC_CH CCFG: ASC Position */
\r
1355 #define USIC_CH_CCFG_ASC_Msk (0x01UL << USIC_CH_CCFG_ASC_Pos) /*!< USIC_CH CCFG: ASC Mask */
\r
1356 #define USIC_CH_CCFG_IIC_Pos 2 /*!< USIC_CH CCFG: IIC Position */
\r
1357 #define USIC_CH_CCFG_IIC_Msk (0x01UL << USIC_CH_CCFG_IIC_Pos) /*!< USIC_CH CCFG: IIC Mask */
\r
1358 #define USIC_CH_CCFG_IIS_Pos 3 /*!< USIC_CH CCFG: IIS Position */
\r
1359 #define USIC_CH_CCFG_IIS_Msk (0x01UL << USIC_CH_CCFG_IIS_Pos) /*!< USIC_CH CCFG: IIS Mask */
\r
1360 #define USIC_CH_CCFG_RB_Pos 6 /*!< USIC_CH CCFG: RB Position */
\r
1361 #define USIC_CH_CCFG_RB_Msk (0x01UL << USIC_CH_CCFG_RB_Pos) /*!< USIC_CH CCFG: RB Mask */
\r
1362 #define USIC_CH_CCFG_TB_Pos 7 /*!< USIC_CH CCFG: TB Position */
\r
1363 #define USIC_CH_CCFG_TB_Msk (0x01UL << USIC_CH_CCFG_TB_Pos) /*!< USIC_CH CCFG: TB Mask */
\r
1365 /* -------------------------------- USIC_CH_KSCFG ------------------------------- */
\r
1366 #define USIC_CH_KSCFG_MODEN_Pos 0 /*!< USIC_CH KSCFG: MODEN Position */
\r
1367 #define USIC_CH_KSCFG_MODEN_Msk (0x01UL << USIC_CH_KSCFG_MODEN_Pos) /*!< USIC_CH KSCFG: MODEN Mask */
\r
1368 #define USIC_CH_KSCFG_BPMODEN_Pos 1 /*!< USIC_CH KSCFG: BPMODEN Position */
\r
1369 #define USIC_CH_KSCFG_BPMODEN_Msk (0x01UL << USIC_CH_KSCFG_BPMODEN_Pos) /*!< USIC_CH KSCFG: BPMODEN Mask */
\r
1370 #define USIC_CH_KSCFG_NOMCFG_Pos 4 /*!< USIC_CH KSCFG: NOMCFG Position */
\r
1371 #define USIC_CH_KSCFG_NOMCFG_Msk (0x03UL << USIC_CH_KSCFG_NOMCFG_Pos) /*!< USIC_CH KSCFG: NOMCFG Mask */
\r
1372 #define USIC_CH_KSCFG_BPNOM_Pos 7 /*!< USIC_CH KSCFG: BPNOM Position */
\r
1373 #define USIC_CH_KSCFG_BPNOM_Msk (0x01UL << USIC_CH_KSCFG_BPNOM_Pos) /*!< USIC_CH KSCFG: BPNOM Mask */
\r
1374 #define USIC_CH_KSCFG_SUMCFG_Pos 8 /*!< USIC_CH KSCFG: SUMCFG Position */
\r
1375 #define USIC_CH_KSCFG_SUMCFG_Msk (0x03UL << USIC_CH_KSCFG_SUMCFG_Pos) /*!< USIC_CH KSCFG: SUMCFG Mask */
\r
1376 #define USIC_CH_KSCFG_BPSUM_Pos 11 /*!< USIC_CH KSCFG: BPSUM Position */
\r
1377 #define USIC_CH_KSCFG_BPSUM_Msk (0x01UL << USIC_CH_KSCFG_BPSUM_Pos) /*!< USIC_CH KSCFG: BPSUM Mask */
\r
1379 /* --------------------------------- USIC_CH_FDR -------------------------------- */
\r
1380 #define USIC_CH_FDR_STEP_Pos 0 /*!< USIC_CH FDR: STEP Position */
\r
1381 #define USIC_CH_FDR_STEP_Msk (0x000003ffUL << USIC_CH_FDR_STEP_Pos) /*!< USIC_CH FDR: STEP Mask */
\r
1382 #define USIC_CH_FDR_DM_Pos 14 /*!< USIC_CH FDR: DM Position */
\r
1383 #define USIC_CH_FDR_DM_Msk (0x03UL << USIC_CH_FDR_DM_Pos) /*!< USIC_CH FDR: DM Mask */
\r
1384 #define USIC_CH_FDR_RESULT_Pos 16 /*!< USIC_CH FDR: RESULT Position */
\r
1385 #define USIC_CH_FDR_RESULT_Msk (0x000003ffUL << USIC_CH_FDR_RESULT_Pos) /*!< USIC_CH FDR: RESULT Mask */
\r
1387 /* --------------------------------- USIC_CH_BRG -------------------------------- */
\r
1388 #define USIC_CH_BRG_CLKSEL_Pos 0 /*!< USIC_CH BRG: CLKSEL Position */
\r
1389 #define USIC_CH_BRG_CLKSEL_Msk (0x03UL << USIC_CH_BRG_CLKSEL_Pos) /*!< USIC_CH BRG: CLKSEL Mask */
\r
1390 #define USIC_CH_BRG_TMEN_Pos 3 /*!< USIC_CH BRG: TMEN Position */
\r
1391 #define USIC_CH_BRG_TMEN_Msk (0x01UL << USIC_CH_BRG_TMEN_Pos) /*!< USIC_CH BRG: TMEN Mask */
\r
1392 #define USIC_CH_BRG_PPPEN_Pos 4 /*!< USIC_CH BRG: PPPEN Position */
\r
1393 #define USIC_CH_BRG_PPPEN_Msk (0x01UL << USIC_CH_BRG_PPPEN_Pos) /*!< USIC_CH BRG: PPPEN Mask */
\r
1394 #define USIC_CH_BRG_CTQSEL_Pos 6 /*!< USIC_CH BRG: CTQSEL Position */
\r
1395 #define USIC_CH_BRG_CTQSEL_Msk (0x03UL << USIC_CH_BRG_CTQSEL_Pos) /*!< USIC_CH BRG: CTQSEL Mask */
\r
1396 #define USIC_CH_BRG_PCTQ_Pos 8 /*!< USIC_CH BRG: PCTQ Position */
\r
1397 #define USIC_CH_BRG_PCTQ_Msk (0x03UL << USIC_CH_BRG_PCTQ_Pos) /*!< USIC_CH BRG: PCTQ Mask */
\r
1398 #define USIC_CH_BRG_DCTQ_Pos 10 /*!< USIC_CH BRG: DCTQ Position */
\r
1399 #define USIC_CH_BRG_DCTQ_Msk (0x1fUL << USIC_CH_BRG_DCTQ_Pos) /*!< USIC_CH BRG: DCTQ Mask */
\r
1400 #define USIC_CH_BRG_PDIV_Pos 16 /*!< USIC_CH BRG: PDIV Position */
\r
1401 #define USIC_CH_BRG_PDIV_Msk (0x000003ffUL << USIC_CH_BRG_PDIV_Pos) /*!< USIC_CH BRG: PDIV Mask */
\r
1402 #define USIC_CH_BRG_SCLKOSEL_Pos 28 /*!< USIC_CH BRG: SCLKOSEL Position */
\r
1403 #define USIC_CH_BRG_SCLKOSEL_Msk (0x01UL << USIC_CH_BRG_SCLKOSEL_Pos) /*!< USIC_CH BRG: SCLKOSEL Mask */
\r
1404 #define USIC_CH_BRG_MCLKCFG_Pos 29 /*!< USIC_CH BRG: MCLKCFG Position */
\r
1405 #define USIC_CH_BRG_MCLKCFG_Msk (0x01UL << USIC_CH_BRG_MCLKCFG_Pos) /*!< USIC_CH BRG: MCLKCFG Mask */
\r
1406 #define USIC_CH_BRG_SCLKCFG_Pos 30 /*!< USIC_CH BRG: SCLKCFG Position */
\r
1407 #define USIC_CH_BRG_SCLKCFG_Msk (0x03UL << USIC_CH_BRG_SCLKCFG_Pos) /*!< USIC_CH BRG: SCLKCFG Mask */
\r
1409 /* -------------------------------- USIC_CH_INPR -------------------------------- */
\r
1410 #define USIC_CH_INPR_TSINP_Pos 0 /*!< USIC_CH INPR: TSINP Position */
\r
1411 #define USIC_CH_INPR_TSINP_Msk (0x07UL << USIC_CH_INPR_TSINP_Pos) /*!< USIC_CH INPR: TSINP Mask */
\r
1412 #define USIC_CH_INPR_TBINP_Pos 4 /*!< USIC_CH INPR: TBINP Position */
\r
1413 #define USIC_CH_INPR_TBINP_Msk (0x07UL << USIC_CH_INPR_TBINP_Pos) /*!< USIC_CH INPR: TBINP Mask */
\r
1414 #define USIC_CH_INPR_RINP_Pos 8 /*!< USIC_CH INPR: RINP Position */
\r
1415 #define USIC_CH_INPR_RINP_Msk (0x07UL << USIC_CH_INPR_RINP_Pos) /*!< USIC_CH INPR: RINP Mask */
\r
1416 #define USIC_CH_INPR_AINP_Pos 12 /*!< USIC_CH INPR: AINP Position */
\r
1417 #define USIC_CH_INPR_AINP_Msk (0x07UL << USIC_CH_INPR_AINP_Pos) /*!< USIC_CH INPR: AINP Mask */
\r
1418 #define USIC_CH_INPR_PINP_Pos 16 /*!< USIC_CH INPR: PINP Position */
\r
1419 #define USIC_CH_INPR_PINP_Msk (0x07UL << USIC_CH_INPR_PINP_Pos) /*!< USIC_CH INPR: PINP Mask */
\r
1421 /* -------------------------------- USIC_CH_DX0CR ------------------------------- */
\r
1422 #define USIC_CH_DX0CR_DSEL_Pos 0 /*!< USIC_CH DX0CR: DSEL Position */
\r
1423 #define USIC_CH_DX0CR_DSEL_Msk (0x07UL << USIC_CH_DX0CR_DSEL_Pos) /*!< USIC_CH DX0CR: DSEL Mask */
\r
1424 #define USIC_CH_DX0CR_INSW_Pos 4 /*!< USIC_CH DX0CR: INSW Position */
\r
1425 #define USIC_CH_DX0CR_INSW_Msk (0x01UL << USIC_CH_DX0CR_INSW_Pos) /*!< USIC_CH DX0CR: INSW Mask */
\r
1426 #define USIC_CH_DX0CR_DFEN_Pos 5 /*!< USIC_CH DX0CR: DFEN Position */
\r
1427 #define USIC_CH_DX0CR_DFEN_Msk (0x01UL << USIC_CH_DX0CR_DFEN_Pos) /*!< USIC_CH DX0CR: DFEN Mask */
\r
1428 #define USIC_CH_DX0CR_DSEN_Pos 6 /*!< USIC_CH DX0CR: DSEN Position */
\r
1429 #define USIC_CH_DX0CR_DSEN_Msk (0x01UL << USIC_CH_DX0CR_DSEN_Pos) /*!< USIC_CH DX0CR: DSEN Mask */
\r
1430 #define USIC_CH_DX0CR_DPOL_Pos 8 /*!< USIC_CH DX0CR: DPOL Position */
\r
1431 #define USIC_CH_DX0CR_DPOL_Msk (0x01UL << USIC_CH_DX0CR_DPOL_Pos) /*!< USIC_CH DX0CR: DPOL Mask */
\r
1432 #define USIC_CH_DX0CR_SFSEL_Pos 9 /*!< USIC_CH DX0CR: SFSEL Position */
\r
1433 #define USIC_CH_DX0CR_SFSEL_Msk (0x01UL << USIC_CH_DX0CR_SFSEL_Pos) /*!< USIC_CH DX0CR: SFSEL Mask */
\r
1434 #define USIC_CH_DX0CR_CM_Pos 10 /*!< USIC_CH DX0CR: CM Position */
\r
1435 #define USIC_CH_DX0CR_CM_Msk (0x03UL << USIC_CH_DX0CR_CM_Pos) /*!< USIC_CH DX0CR: CM Mask */
\r
1436 #define USIC_CH_DX0CR_DXS_Pos 15 /*!< USIC_CH DX0CR: DXS Position */
\r
1437 #define USIC_CH_DX0CR_DXS_Msk (0x01UL << USIC_CH_DX0CR_DXS_Pos) /*!< USIC_CH DX0CR: DXS Mask */
\r
1439 /* -------------------------------- USIC_CH_DX1CR ------------------------------- */
\r
1440 #define USIC_CH_DX1CR_DSEL_Pos 0 /*!< USIC_CH DX1CR: DSEL Position */
\r
1441 #define USIC_CH_DX1CR_DSEL_Msk (0x07UL << USIC_CH_DX1CR_DSEL_Pos) /*!< USIC_CH DX1CR: DSEL Mask */
\r
1442 #define USIC_CH_DX1CR_DCEN_Pos 3 /*!< USIC_CH DX1CR: DCEN Position */
\r
1443 #define USIC_CH_DX1CR_DCEN_Msk (0x01UL << USIC_CH_DX1CR_DCEN_Pos) /*!< USIC_CH DX1CR: DCEN Mask */
\r
1444 #define USIC_CH_DX1CR_INSW_Pos 4 /*!< USIC_CH DX1CR: INSW Position */
\r
1445 #define USIC_CH_DX1CR_INSW_Msk (0x01UL << USIC_CH_DX1CR_INSW_Pos) /*!< USIC_CH DX1CR: INSW Mask */
\r
1446 #define USIC_CH_DX1CR_DFEN_Pos 5 /*!< USIC_CH DX1CR: DFEN Position */
\r
1447 #define USIC_CH_DX1CR_DFEN_Msk (0x01UL << USIC_CH_DX1CR_DFEN_Pos) /*!< USIC_CH DX1CR: DFEN Mask */
\r
1448 #define USIC_CH_DX1CR_DSEN_Pos 6 /*!< USIC_CH DX1CR: DSEN Position */
\r
1449 #define USIC_CH_DX1CR_DSEN_Msk (0x01UL << USIC_CH_DX1CR_DSEN_Pos) /*!< USIC_CH DX1CR: DSEN Mask */
\r
1450 #define USIC_CH_DX1CR_DPOL_Pos 8 /*!< USIC_CH DX1CR: DPOL Position */
\r
1451 #define USIC_CH_DX1CR_DPOL_Msk (0x01UL << USIC_CH_DX1CR_DPOL_Pos) /*!< USIC_CH DX1CR: DPOL Mask */
\r
1452 #define USIC_CH_DX1CR_SFSEL_Pos 9 /*!< USIC_CH DX1CR: SFSEL Position */
\r
1453 #define USIC_CH_DX1CR_SFSEL_Msk (0x01UL << USIC_CH_DX1CR_SFSEL_Pos) /*!< USIC_CH DX1CR: SFSEL Mask */
\r
1454 #define USIC_CH_DX1CR_CM_Pos 10 /*!< USIC_CH DX1CR: CM Position */
\r
1455 #define USIC_CH_DX1CR_CM_Msk (0x03UL << USIC_CH_DX1CR_CM_Pos) /*!< USIC_CH DX1CR: CM Mask */
\r
1456 #define USIC_CH_DX1CR_DXS_Pos 15 /*!< USIC_CH DX1CR: DXS Position */
\r
1457 #define USIC_CH_DX1CR_DXS_Msk (0x01UL << USIC_CH_DX1CR_DXS_Pos) /*!< USIC_CH DX1CR: DXS Mask */
\r
1459 /* -------------------------------- USIC_CH_DX2CR ------------------------------- */
\r
1460 #define USIC_CH_DX2CR_DSEL_Pos 0 /*!< USIC_CH DX2CR: DSEL Position */
\r
1461 #define USIC_CH_DX2CR_DSEL_Msk (0x07UL << USIC_CH_DX2CR_DSEL_Pos) /*!< USIC_CH DX2CR: DSEL Mask */
\r
1462 #define USIC_CH_DX2CR_INSW_Pos 4 /*!< USIC_CH DX2CR: INSW Position */
\r
1463 #define USIC_CH_DX2CR_INSW_Msk (0x01UL << USIC_CH_DX2CR_INSW_Pos) /*!< USIC_CH DX2CR: INSW Mask */
\r
1464 #define USIC_CH_DX2CR_DFEN_Pos 5 /*!< USIC_CH DX2CR: DFEN Position */
\r
1465 #define USIC_CH_DX2CR_DFEN_Msk (0x01UL << USIC_CH_DX2CR_DFEN_Pos) /*!< USIC_CH DX2CR: DFEN Mask */
\r
1466 #define USIC_CH_DX2CR_DSEN_Pos 6 /*!< USIC_CH DX2CR: DSEN Position */
\r
1467 #define USIC_CH_DX2CR_DSEN_Msk (0x01UL << USIC_CH_DX2CR_DSEN_Pos) /*!< USIC_CH DX2CR: DSEN Mask */
\r
1468 #define USIC_CH_DX2CR_DPOL_Pos 8 /*!< USIC_CH DX2CR: DPOL Position */
\r
1469 #define USIC_CH_DX2CR_DPOL_Msk (0x01UL << USIC_CH_DX2CR_DPOL_Pos) /*!< USIC_CH DX2CR: DPOL Mask */
\r
1470 #define USIC_CH_DX2CR_SFSEL_Pos 9 /*!< USIC_CH DX2CR: SFSEL Position */
\r
1471 #define USIC_CH_DX2CR_SFSEL_Msk (0x01UL << USIC_CH_DX2CR_SFSEL_Pos) /*!< USIC_CH DX2CR: SFSEL Mask */
\r
1472 #define USIC_CH_DX2CR_CM_Pos 10 /*!< USIC_CH DX2CR: CM Position */
\r
1473 #define USIC_CH_DX2CR_CM_Msk (0x03UL << USIC_CH_DX2CR_CM_Pos) /*!< USIC_CH DX2CR: CM Mask */
\r
1474 #define USIC_CH_DX2CR_DXS_Pos 15 /*!< USIC_CH DX2CR: DXS Position */
\r
1475 #define USIC_CH_DX2CR_DXS_Msk (0x01UL << USIC_CH_DX2CR_DXS_Pos) /*!< USIC_CH DX2CR: DXS Mask */
\r
1477 /* -------------------------------- USIC_CH_DX3CR ------------------------------- */
\r
1478 #define USIC_CH_DX3CR_DSEL_Pos 0 /*!< USIC_CH DX3CR: DSEL Position */
\r
1479 #define USIC_CH_DX3CR_DSEL_Msk (0x07UL << USIC_CH_DX3CR_DSEL_Pos) /*!< USIC_CH DX3CR: DSEL Mask */
\r
1480 #define USIC_CH_DX3CR_INSW_Pos 4 /*!< USIC_CH DX3CR: INSW Position */
\r
1481 #define USIC_CH_DX3CR_INSW_Msk (0x01UL << USIC_CH_DX3CR_INSW_Pos) /*!< USIC_CH DX3CR: INSW Mask */
\r
1482 #define USIC_CH_DX3CR_DFEN_Pos 5 /*!< USIC_CH DX3CR: DFEN Position */
\r
1483 #define USIC_CH_DX3CR_DFEN_Msk (0x01UL << USIC_CH_DX3CR_DFEN_Pos) /*!< USIC_CH DX3CR: DFEN Mask */
\r
1484 #define USIC_CH_DX3CR_DSEN_Pos 6 /*!< USIC_CH DX3CR: DSEN Position */
\r
1485 #define USIC_CH_DX3CR_DSEN_Msk (0x01UL << USIC_CH_DX3CR_DSEN_Pos) /*!< USIC_CH DX3CR: DSEN Mask */
\r
1486 #define USIC_CH_DX3CR_DPOL_Pos 8 /*!< USIC_CH DX3CR: DPOL Position */
\r
1487 #define USIC_CH_DX3CR_DPOL_Msk (0x01UL << USIC_CH_DX3CR_DPOL_Pos) /*!< USIC_CH DX3CR: DPOL Mask */
\r
1488 #define USIC_CH_DX3CR_SFSEL_Pos 9 /*!< USIC_CH DX3CR: SFSEL Position */
\r
1489 #define USIC_CH_DX3CR_SFSEL_Msk (0x01UL << USIC_CH_DX3CR_SFSEL_Pos) /*!< USIC_CH DX3CR: SFSEL Mask */
\r
1490 #define USIC_CH_DX3CR_CM_Pos 10 /*!< USIC_CH DX3CR: CM Position */
\r
1491 #define USIC_CH_DX3CR_CM_Msk (0x03UL << USIC_CH_DX3CR_CM_Pos) /*!< USIC_CH DX3CR: CM Mask */
\r
1492 #define USIC_CH_DX3CR_DXS_Pos 15 /*!< USIC_CH DX3CR: DXS Position */
\r
1493 #define USIC_CH_DX3CR_DXS_Msk (0x01UL << USIC_CH_DX3CR_DXS_Pos) /*!< USIC_CH DX3CR: DXS Mask */
\r
1495 /* -------------------------------- USIC_CH_DX4CR ------------------------------- */
\r
1496 #define USIC_CH_DX4CR_DSEL_Pos 0 /*!< USIC_CH DX4CR: DSEL Position */
\r
1497 #define USIC_CH_DX4CR_DSEL_Msk (0x07UL << USIC_CH_DX4CR_DSEL_Pos) /*!< USIC_CH DX4CR: DSEL Mask */
\r
1498 #define USIC_CH_DX4CR_INSW_Pos 4 /*!< USIC_CH DX4CR: INSW Position */
\r
1499 #define USIC_CH_DX4CR_INSW_Msk (0x01UL << USIC_CH_DX4CR_INSW_Pos) /*!< USIC_CH DX4CR: INSW Mask */
\r
1500 #define USIC_CH_DX4CR_DFEN_Pos 5 /*!< USIC_CH DX4CR: DFEN Position */
\r
1501 #define USIC_CH_DX4CR_DFEN_Msk (0x01UL << USIC_CH_DX4CR_DFEN_Pos) /*!< USIC_CH DX4CR: DFEN Mask */
\r
1502 #define USIC_CH_DX4CR_DSEN_Pos 6 /*!< USIC_CH DX4CR: DSEN Position */
\r
1503 #define USIC_CH_DX4CR_DSEN_Msk (0x01UL << USIC_CH_DX4CR_DSEN_Pos) /*!< USIC_CH DX4CR: DSEN Mask */
\r
1504 #define USIC_CH_DX4CR_DPOL_Pos 8 /*!< USIC_CH DX4CR: DPOL Position */
\r
1505 #define USIC_CH_DX4CR_DPOL_Msk (0x01UL << USIC_CH_DX4CR_DPOL_Pos) /*!< USIC_CH DX4CR: DPOL Mask */
\r
1506 #define USIC_CH_DX4CR_SFSEL_Pos 9 /*!< USIC_CH DX4CR: SFSEL Position */
\r
1507 #define USIC_CH_DX4CR_SFSEL_Msk (0x01UL << USIC_CH_DX4CR_SFSEL_Pos) /*!< USIC_CH DX4CR: SFSEL Mask */
\r
1508 #define USIC_CH_DX4CR_CM_Pos 10 /*!< USIC_CH DX4CR: CM Position */
\r
1509 #define USIC_CH_DX4CR_CM_Msk (0x03UL << USIC_CH_DX4CR_CM_Pos) /*!< USIC_CH DX4CR: CM Mask */
\r
1510 #define USIC_CH_DX4CR_DXS_Pos 15 /*!< USIC_CH DX4CR: DXS Position */
\r
1511 #define USIC_CH_DX4CR_DXS_Msk (0x01UL << USIC_CH_DX4CR_DXS_Pos) /*!< USIC_CH DX4CR: DXS Mask */
\r
1513 /* -------------------------------- USIC_CH_DX5CR ------------------------------- */
\r
1514 #define USIC_CH_DX5CR_DSEL_Pos 0 /*!< USIC_CH DX5CR: DSEL Position */
\r
1515 #define USIC_CH_DX5CR_DSEL_Msk (0x07UL << USIC_CH_DX5CR_DSEL_Pos) /*!< USIC_CH DX5CR: DSEL Mask */
\r
1516 #define USIC_CH_DX5CR_INSW_Pos 4 /*!< USIC_CH DX5CR: INSW Position */
\r
1517 #define USIC_CH_DX5CR_INSW_Msk (0x01UL << USIC_CH_DX5CR_INSW_Pos) /*!< USIC_CH DX5CR: INSW Mask */
\r
1518 #define USIC_CH_DX5CR_DFEN_Pos 5 /*!< USIC_CH DX5CR: DFEN Position */
\r
1519 #define USIC_CH_DX5CR_DFEN_Msk (0x01UL << USIC_CH_DX5CR_DFEN_Pos) /*!< USIC_CH DX5CR: DFEN Mask */
\r
1520 #define USIC_CH_DX5CR_DSEN_Pos 6 /*!< USIC_CH DX5CR: DSEN Position */
\r
1521 #define USIC_CH_DX5CR_DSEN_Msk (0x01UL << USIC_CH_DX5CR_DSEN_Pos) /*!< USIC_CH DX5CR: DSEN Mask */
\r
1522 #define USIC_CH_DX5CR_DPOL_Pos 8 /*!< USIC_CH DX5CR: DPOL Position */
\r
1523 #define USIC_CH_DX5CR_DPOL_Msk (0x01UL << USIC_CH_DX5CR_DPOL_Pos) /*!< USIC_CH DX5CR: DPOL Mask */
\r
1524 #define USIC_CH_DX5CR_SFSEL_Pos 9 /*!< USIC_CH DX5CR: SFSEL Position */
\r
1525 #define USIC_CH_DX5CR_SFSEL_Msk (0x01UL << USIC_CH_DX5CR_SFSEL_Pos) /*!< USIC_CH DX5CR: SFSEL Mask */
\r
1526 #define USIC_CH_DX5CR_CM_Pos 10 /*!< USIC_CH DX5CR: CM Position */
\r
1527 #define USIC_CH_DX5CR_CM_Msk (0x03UL << USIC_CH_DX5CR_CM_Pos) /*!< USIC_CH DX5CR: CM Mask */
\r
1528 #define USIC_CH_DX5CR_DXS_Pos 15 /*!< USIC_CH DX5CR: DXS Position */
\r
1529 #define USIC_CH_DX5CR_DXS_Msk (0x01UL << USIC_CH_DX5CR_DXS_Pos) /*!< USIC_CH DX5CR: DXS Mask */
\r
1531 /* -------------------------------- USIC_CH_SCTR -------------------------------- */
\r
1532 #define USIC_CH_SCTR_SDIR_Pos 0 /*!< USIC_CH SCTR: SDIR Position */
\r
1533 #define USIC_CH_SCTR_SDIR_Msk (0x01UL << USIC_CH_SCTR_SDIR_Pos) /*!< USIC_CH SCTR: SDIR Mask */
\r
1534 #define USIC_CH_SCTR_PDL_Pos 1 /*!< USIC_CH SCTR: PDL Position */
\r
1535 #define USIC_CH_SCTR_PDL_Msk (0x01UL << USIC_CH_SCTR_PDL_Pos) /*!< USIC_CH SCTR: PDL Mask */
\r
1536 #define USIC_CH_SCTR_DSM_Pos 2 /*!< USIC_CH SCTR: DSM Position */
\r
1537 #define USIC_CH_SCTR_DSM_Msk (0x03UL << USIC_CH_SCTR_DSM_Pos) /*!< USIC_CH SCTR: DSM Mask */
\r
1538 #define USIC_CH_SCTR_HPCDIR_Pos 4 /*!< USIC_CH SCTR: HPCDIR Position */
\r
1539 #define USIC_CH_SCTR_HPCDIR_Msk (0x01UL << USIC_CH_SCTR_HPCDIR_Pos) /*!< USIC_CH SCTR: HPCDIR Mask */
\r
1540 #define USIC_CH_SCTR_DOCFG_Pos 6 /*!< USIC_CH SCTR: DOCFG Position */
\r
1541 #define USIC_CH_SCTR_DOCFG_Msk (0x03UL << USIC_CH_SCTR_DOCFG_Pos) /*!< USIC_CH SCTR: DOCFG Mask */
\r
1542 #define USIC_CH_SCTR_TRM_Pos 8 /*!< USIC_CH SCTR: TRM Position */
\r
1543 #define USIC_CH_SCTR_TRM_Msk (0x03UL << USIC_CH_SCTR_TRM_Pos) /*!< USIC_CH SCTR: TRM Mask */
\r
1544 #define USIC_CH_SCTR_FLE_Pos 16 /*!< USIC_CH SCTR: FLE Position */
\r
1545 #define USIC_CH_SCTR_FLE_Msk (0x3fUL << USIC_CH_SCTR_FLE_Pos) /*!< USIC_CH SCTR: FLE Mask */
\r
1546 #define USIC_CH_SCTR_WLE_Pos 24 /*!< USIC_CH SCTR: WLE Position */
\r
1547 #define USIC_CH_SCTR_WLE_Msk (0x0fUL << USIC_CH_SCTR_WLE_Pos) /*!< USIC_CH SCTR: WLE Mask */
\r
1549 /* -------------------------------- USIC_CH_TCSR -------------------------------- */
\r
1550 #define USIC_CH_TCSR_WLEMD_Pos 0 /*!< USIC_CH TCSR: WLEMD Position */
\r
1551 #define USIC_CH_TCSR_WLEMD_Msk (0x01UL << USIC_CH_TCSR_WLEMD_Pos) /*!< USIC_CH TCSR: WLEMD Mask */
\r
1552 #define USIC_CH_TCSR_SELMD_Pos 1 /*!< USIC_CH TCSR: SELMD Position */
\r
1553 #define USIC_CH_TCSR_SELMD_Msk (0x01UL << USIC_CH_TCSR_SELMD_Pos) /*!< USIC_CH TCSR: SELMD Mask */
\r
1554 #define USIC_CH_TCSR_FLEMD_Pos 2 /*!< USIC_CH TCSR: FLEMD Position */
\r
1555 #define USIC_CH_TCSR_FLEMD_Msk (0x01UL << USIC_CH_TCSR_FLEMD_Pos) /*!< USIC_CH TCSR: FLEMD Mask */
\r
1556 #define USIC_CH_TCSR_WAMD_Pos 3 /*!< USIC_CH TCSR: WAMD Position */
\r
1557 #define USIC_CH_TCSR_WAMD_Msk (0x01UL << USIC_CH_TCSR_WAMD_Pos) /*!< USIC_CH TCSR: WAMD Mask */
\r
1558 #define USIC_CH_TCSR_HPCMD_Pos 4 /*!< USIC_CH TCSR: HPCMD Position */
\r
1559 #define USIC_CH_TCSR_HPCMD_Msk (0x01UL << USIC_CH_TCSR_HPCMD_Pos) /*!< USIC_CH TCSR: HPCMD Mask */
\r
1560 #define USIC_CH_TCSR_SOF_Pos 5 /*!< USIC_CH TCSR: SOF Position */
\r
1561 #define USIC_CH_TCSR_SOF_Msk (0x01UL << USIC_CH_TCSR_SOF_Pos) /*!< USIC_CH TCSR: SOF Mask */
\r
1562 #define USIC_CH_TCSR_EOF_Pos 6 /*!< USIC_CH TCSR: EOF Position */
\r
1563 #define USIC_CH_TCSR_EOF_Msk (0x01UL << USIC_CH_TCSR_EOF_Pos) /*!< USIC_CH TCSR: EOF Mask */
\r
1564 #define USIC_CH_TCSR_TDV_Pos 7 /*!< USIC_CH TCSR: TDV Position */
\r
1565 #define USIC_CH_TCSR_TDV_Msk (0x01UL << USIC_CH_TCSR_TDV_Pos) /*!< USIC_CH TCSR: TDV Mask */
\r
1566 #define USIC_CH_TCSR_TDSSM_Pos 8 /*!< USIC_CH TCSR: TDSSM Position */
\r
1567 #define USIC_CH_TCSR_TDSSM_Msk (0x01UL << USIC_CH_TCSR_TDSSM_Pos) /*!< USIC_CH TCSR: TDSSM Mask */
\r
1568 #define USIC_CH_TCSR_TDEN_Pos 10 /*!< USIC_CH TCSR: TDEN Position */
\r
1569 #define USIC_CH_TCSR_TDEN_Msk (0x03UL << USIC_CH_TCSR_TDEN_Pos) /*!< USIC_CH TCSR: TDEN Mask */
\r
1570 #define USIC_CH_TCSR_TDVTR_Pos 12 /*!< USIC_CH TCSR: TDVTR Position */
\r
1571 #define USIC_CH_TCSR_TDVTR_Msk (0x01UL << USIC_CH_TCSR_TDVTR_Pos) /*!< USIC_CH TCSR: TDVTR Mask */
\r
1572 #define USIC_CH_TCSR_WA_Pos 13 /*!< USIC_CH TCSR: WA Position */
\r
1573 #define USIC_CH_TCSR_WA_Msk (0x01UL << USIC_CH_TCSR_WA_Pos) /*!< USIC_CH TCSR: WA Mask */
\r
1574 #define USIC_CH_TCSR_TSOF_Pos 24 /*!< USIC_CH TCSR: TSOF Position */
\r
1575 #define USIC_CH_TCSR_TSOF_Msk (0x01UL << USIC_CH_TCSR_TSOF_Pos) /*!< USIC_CH TCSR: TSOF Mask */
\r
1576 #define USIC_CH_TCSR_TV_Pos 26 /*!< USIC_CH TCSR: TV Position */
\r
1577 #define USIC_CH_TCSR_TV_Msk (0x01UL << USIC_CH_TCSR_TV_Pos) /*!< USIC_CH TCSR: TV Mask */
\r
1578 #define USIC_CH_TCSR_TVC_Pos 27 /*!< USIC_CH TCSR: TVC Position */
\r
1579 #define USIC_CH_TCSR_TVC_Msk (0x01UL << USIC_CH_TCSR_TVC_Pos) /*!< USIC_CH TCSR: TVC Mask */
\r
1580 #define USIC_CH_TCSR_TE_Pos 28 /*!< USIC_CH TCSR: TE Position */
\r
1581 #define USIC_CH_TCSR_TE_Msk (0x01UL << USIC_CH_TCSR_TE_Pos) /*!< USIC_CH TCSR: TE Mask */
\r
1583 /* --------------------------------- USIC_CH_PCR -------------------------------- */
\r
1584 #define USIC_CH_PCR_CTR0_Pos 0 /*!< USIC_CH PCR: CTR0 Position */
\r
1585 #define USIC_CH_PCR_CTR0_Msk (0x01UL << USIC_CH_PCR_CTR0_Pos) /*!< USIC_CH PCR: CTR0 Mask */
\r
1586 #define USIC_CH_PCR_CTR1_Pos 1 /*!< USIC_CH PCR: CTR1 Position */
\r
1587 #define USIC_CH_PCR_CTR1_Msk (0x01UL << USIC_CH_PCR_CTR1_Pos) /*!< USIC_CH PCR: CTR1 Mask */
\r
1588 #define USIC_CH_PCR_CTR2_Pos 2 /*!< USIC_CH PCR: CTR2 Position */
\r
1589 #define USIC_CH_PCR_CTR2_Msk (0x01UL << USIC_CH_PCR_CTR2_Pos) /*!< USIC_CH PCR: CTR2 Mask */
\r
1590 #define USIC_CH_PCR_CTR3_Pos 3 /*!< USIC_CH PCR: CTR3 Position */
\r
1591 #define USIC_CH_PCR_CTR3_Msk (0x01UL << USIC_CH_PCR_CTR3_Pos) /*!< USIC_CH PCR: CTR3 Mask */
\r
1592 #define USIC_CH_PCR_CTR4_Pos 4 /*!< USIC_CH PCR: CTR4 Position */
\r
1593 #define USIC_CH_PCR_CTR4_Msk (0x01UL << USIC_CH_PCR_CTR4_Pos) /*!< USIC_CH PCR: CTR4 Mask */
\r
1594 #define USIC_CH_PCR_CTR5_Pos 5 /*!< USIC_CH PCR: CTR5 Position */
\r
1595 #define USIC_CH_PCR_CTR5_Msk (0x01UL << USIC_CH_PCR_CTR5_Pos) /*!< USIC_CH PCR: CTR5 Mask */
\r
1596 #define USIC_CH_PCR_CTR6_Pos 6 /*!< USIC_CH PCR: CTR6 Position */
\r
1597 #define USIC_CH_PCR_CTR6_Msk (0x01UL << USIC_CH_PCR_CTR6_Pos) /*!< USIC_CH PCR: CTR6 Mask */
\r
1598 #define USIC_CH_PCR_CTR7_Pos 7 /*!< USIC_CH PCR: CTR7 Position */
\r
1599 #define USIC_CH_PCR_CTR7_Msk (0x01UL << USIC_CH_PCR_CTR7_Pos) /*!< USIC_CH PCR: CTR7 Mask */
\r
1600 #define USIC_CH_PCR_CTR8_Pos 8 /*!< USIC_CH PCR: CTR8 Position */
\r
1601 #define USIC_CH_PCR_CTR8_Msk (0x01UL << USIC_CH_PCR_CTR8_Pos) /*!< USIC_CH PCR: CTR8 Mask */
\r
1602 #define USIC_CH_PCR_CTR9_Pos 9 /*!< USIC_CH PCR: CTR9 Position */
\r
1603 #define USIC_CH_PCR_CTR9_Msk (0x01UL << USIC_CH_PCR_CTR9_Pos) /*!< USIC_CH PCR: CTR9 Mask */
\r
1604 #define USIC_CH_PCR_CTR10_Pos 10 /*!< USIC_CH PCR: CTR10 Position */
\r
1605 #define USIC_CH_PCR_CTR10_Msk (0x01UL << USIC_CH_PCR_CTR10_Pos) /*!< USIC_CH PCR: CTR10 Mask */
\r
1606 #define USIC_CH_PCR_CTR11_Pos 11 /*!< USIC_CH PCR: CTR11 Position */
\r
1607 #define USIC_CH_PCR_CTR11_Msk (0x01UL << USIC_CH_PCR_CTR11_Pos) /*!< USIC_CH PCR: CTR11 Mask */
\r
1608 #define USIC_CH_PCR_CTR12_Pos 12 /*!< USIC_CH PCR: CTR12 Position */
\r
1609 #define USIC_CH_PCR_CTR12_Msk (0x01UL << USIC_CH_PCR_CTR12_Pos) /*!< USIC_CH PCR: CTR12 Mask */
\r
1610 #define USIC_CH_PCR_CTR13_Pos 13 /*!< USIC_CH PCR: CTR13 Position */
\r
1611 #define USIC_CH_PCR_CTR13_Msk (0x01UL << USIC_CH_PCR_CTR13_Pos) /*!< USIC_CH PCR: CTR13 Mask */
\r
1612 #define USIC_CH_PCR_CTR14_Pos 14 /*!< USIC_CH PCR: CTR14 Position */
\r
1613 #define USIC_CH_PCR_CTR14_Msk (0x01UL << USIC_CH_PCR_CTR14_Pos) /*!< USIC_CH PCR: CTR14 Mask */
\r
1614 #define USIC_CH_PCR_CTR15_Pos 15 /*!< USIC_CH PCR: CTR15 Position */
\r
1615 #define USIC_CH_PCR_CTR15_Msk (0x01UL << USIC_CH_PCR_CTR15_Pos) /*!< USIC_CH PCR: CTR15 Mask */
\r
1616 #define USIC_CH_PCR_CTR16_Pos 16 /*!< USIC_CH PCR: CTR16 Position */
\r
1617 #define USIC_CH_PCR_CTR16_Msk (0x01UL << USIC_CH_PCR_CTR16_Pos) /*!< USIC_CH PCR: CTR16 Mask */
\r
1618 #define USIC_CH_PCR_CTR17_Pos 17 /*!< USIC_CH PCR: CTR17 Position */
\r
1619 #define USIC_CH_PCR_CTR17_Msk (0x01UL << USIC_CH_PCR_CTR17_Pos) /*!< USIC_CH PCR: CTR17 Mask */
\r
1620 #define USIC_CH_PCR_CTR18_Pos 18 /*!< USIC_CH PCR: CTR18 Position */
\r
1621 #define USIC_CH_PCR_CTR18_Msk (0x01UL << USIC_CH_PCR_CTR18_Pos) /*!< USIC_CH PCR: CTR18 Mask */
\r
1622 #define USIC_CH_PCR_CTR19_Pos 19 /*!< USIC_CH PCR: CTR19 Position */
\r
1623 #define USIC_CH_PCR_CTR19_Msk (0x01UL << USIC_CH_PCR_CTR19_Pos) /*!< USIC_CH PCR: CTR19 Mask */
\r
1624 #define USIC_CH_PCR_CTR20_Pos 20 /*!< USIC_CH PCR: CTR20 Position */
\r
1625 #define USIC_CH_PCR_CTR20_Msk (0x01UL << USIC_CH_PCR_CTR20_Pos) /*!< USIC_CH PCR: CTR20 Mask */
\r
1626 #define USIC_CH_PCR_CTR21_Pos 21 /*!< USIC_CH PCR: CTR21 Position */
\r
1627 #define USIC_CH_PCR_CTR21_Msk (0x01UL << USIC_CH_PCR_CTR21_Pos) /*!< USIC_CH PCR: CTR21 Mask */
\r
1628 #define USIC_CH_PCR_CTR22_Pos 22 /*!< USIC_CH PCR: CTR22 Position */
\r
1629 #define USIC_CH_PCR_CTR22_Msk (0x01UL << USIC_CH_PCR_CTR22_Pos) /*!< USIC_CH PCR: CTR22 Mask */
\r
1630 #define USIC_CH_PCR_CTR23_Pos 23 /*!< USIC_CH PCR: CTR23 Position */
\r
1631 #define USIC_CH_PCR_CTR23_Msk (0x01UL << USIC_CH_PCR_CTR23_Pos) /*!< USIC_CH PCR: CTR23 Mask */
\r
1632 #define USIC_CH_PCR_CTR24_Pos 24 /*!< USIC_CH PCR: CTR24 Position */
\r
1633 #define USIC_CH_PCR_CTR24_Msk (0x01UL << USIC_CH_PCR_CTR24_Pos) /*!< USIC_CH PCR: CTR24 Mask */
\r
1634 #define USIC_CH_PCR_CTR25_Pos 25 /*!< USIC_CH PCR: CTR25 Position */
\r
1635 #define USIC_CH_PCR_CTR25_Msk (0x01UL << USIC_CH_PCR_CTR25_Pos) /*!< USIC_CH PCR: CTR25 Mask */
\r
1636 #define USIC_CH_PCR_CTR26_Pos 26 /*!< USIC_CH PCR: CTR26 Position */
\r
1637 #define USIC_CH_PCR_CTR26_Msk (0x01UL << USIC_CH_PCR_CTR26_Pos) /*!< USIC_CH PCR: CTR26 Mask */
\r
1638 #define USIC_CH_PCR_CTR27_Pos 27 /*!< USIC_CH PCR: CTR27 Position */
\r
1639 #define USIC_CH_PCR_CTR27_Msk (0x01UL << USIC_CH_PCR_CTR27_Pos) /*!< USIC_CH PCR: CTR27 Mask */
\r
1640 #define USIC_CH_PCR_CTR28_Pos 28 /*!< USIC_CH PCR: CTR28 Position */
\r
1641 #define USIC_CH_PCR_CTR28_Msk (0x01UL << USIC_CH_PCR_CTR28_Pos) /*!< USIC_CH PCR: CTR28 Mask */
\r
1642 #define USIC_CH_PCR_CTR29_Pos 29 /*!< USIC_CH PCR: CTR29 Position */
\r
1643 #define USIC_CH_PCR_CTR29_Msk (0x01UL << USIC_CH_PCR_CTR29_Pos) /*!< USIC_CH PCR: CTR29 Mask */
\r
1644 #define USIC_CH_PCR_CTR30_Pos 30 /*!< USIC_CH PCR: CTR30 Position */
\r
1645 #define USIC_CH_PCR_CTR30_Msk (0x01UL << USIC_CH_PCR_CTR30_Pos) /*!< USIC_CH PCR: CTR30 Mask */
\r
1646 #define USIC_CH_PCR_CTR31_Pos 31 /*!< USIC_CH PCR: CTR31 Position */
\r
1647 #define USIC_CH_PCR_CTR31_Msk (0x01UL << USIC_CH_PCR_CTR31_Pos) /*!< USIC_CH PCR: CTR31 Mask */
\r
1649 /* ----------------------------- USIC_CH_PCR_ASCMode ---------------------------- */
\r
1650 #define USIC_CH_PCR_ASCMode_SMD_Pos 0 /*!< USIC_CH PCR_ASCMode: SMD Position */
\r
1651 #define USIC_CH_PCR_ASCMode_SMD_Msk (0x01UL << USIC_CH_PCR_ASCMode_SMD_Pos) /*!< USIC_CH PCR_ASCMode: SMD Mask */
\r
1652 #define USIC_CH_PCR_ASCMode_STPB_Pos 1 /*!< USIC_CH PCR_ASCMode: STPB Position */
\r
1653 #define USIC_CH_PCR_ASCMode_STPB_Msk (0x01UL << USIC_CH_PCR_ASCMode_STPB_Pos) /*!< USIC_CH PCR_ASCMode: STPB Mask */
\r
1654 #define USIC_CH_PCR_ASCMode_IDM_Pos 2 /*!< USIC_CH PCR_ASCMode: IDM Position */
\r
1655 #define USIC_CH_PCR_ASCMode_IDM_Msk (0x01UL << USIC_CH_PCR_ASCMode_IDM_Pos) /*!< USIC_CH PCR_ASCMode: IDM Mask */
\r
1656 #define USIC_CH_PCR_ASCMode_SBIEN_Pos 3 /*!< USIC_CH PCR_ASCMode: SBIEN Position */
\r
1657 #define USIC_CH_PCR_ASCMode_SBIEN_Msk (0x01UL << USIC_CH_PCR_ASCMode_SBIEN_Pos) /*!< USIC_CH PCR_ASCMode: SBIEN Mask */
\r
1658 #define USIC_CH_PCR_ASCMode_CDEN_Pos 4 /*!< USIC_CH PCR_ASCMode: CDEN Position */
\r
1659 #define USIC_CH_PCR_ASCMode_CDEN_Msk (0x01UL << USIC_CH_PCR_ASCMode_CDEN_Pos) /*!< USIC_CH PCR_ASCMode: CDEN Mask */
\r
1660 #define USIC_CH_PCR_ASCMode_RNIEN_Pos 5 /*!< USIC_CH PCR_ASCMode: RNIEN Position */
\r
1661 #define USIC_CH_PCR_ASCMode_RNIEN_Msk (0x01UL << USIC_CH_PCR_ASCMode_RNIEN_Pos) /*!< USIC_CH PCR_ASCMode: RNIEN Mask */
\r
1662 #define USIC_CH_PCR_ASCMode_FEIEN_Pos 6 /*!< USIC_CH PCR_ASCMode: FEIEN Position */
\r
1663 #define USIC_CH_PCR_ASCMode_FEIEN_Msk (0x01UL << USIC_CH_PCR_ASCMode_FEIEN_Pos) /*!< USIC_CH PCR_ASCMode: FEIEN Mask */
\r
1664 #define USIC_CH_PCR_ASCMode_FFIEN_Pos 7 /*!< USIC_CH PCR_ASCMode: FFIEN Position */
\r
1665 #define USIC_CH_PCR_ASCMode_FFIEN_Msk (0x01UL << USIC_CH_PCR_ASCMode_FFIEN_Pos) /*!< USIC_CH PCR_ASCMode: FFIEN Mask */
\r
1666 #define USIC_CH_PCR_ASCMode_SP_Pos 8 /*!< USIC_CH PCR_ASCMode: SP Position */
\r
1667 #define USIC_CH_PCR_ASCMode_SP_Msk (0x1fUL << USIC_CH_PCR_ASCMode_SP_Pos) /*!< USIC_CH PCR_ASCMode: SP Mask */
\r
1668 #define USIC_CH_PCR_ASCMode_PL_Pos 13 /*!< USIC_CH PCR_ASCMode: PL Position */
\r
1669 #define USIC_CH_PCR_ASCMode_PL_Msk (0x07UL << USIC_CH_PCR_ASCMode_PL_Pos) /*!< USIC_CH PCR_ASCMode: PL Mask */
\r
1670 #define USIC_CH_PCR_ASCMode_RSTEN_Pos 16 /*!< USIC_CH PCR_ASCMode: RSTEN Position */
\r
1671 #define USIC_CH_PCR_ASCMode_RSTEN_Msk (0x01UL << USIC_CH_PCR_ASCMode_RSTEN_Pos) /*!< USIC_CH PCR_ASCMode: RSTEN Mask */
\r
1672 #define USIC_CH_PCR_ASCMode_TSTEN_Pos 17 /*!< USIC_CH PCR_ASCMode: TSTEN Position */
\r
1673 #define USIC_CH_PCR_ASCMode_TSTEN_Msk (0x01UL << USIC_CH_PCR_ASCMode_TSTEN_Pos) /*!< USIC_CH PCR_ASCMode: TSTEN Mask */
\r
1674 #define USIC_CH_PCR_ASCMode_MCLK_Pos 31 /*!< USIC_CH PCR_ASCMode: MCLK Position */
\r
1675 #define USIC_CH_PCR_ASCMode_MCLK_Msk (0x01UL << USIC_CH_PCR_ASCMode_MCLK_Pos) /*!< USIC_CH PCR_ASCMode: MCLK Mask */
\r
1677 /* ----------------------------- USIC_CH_PCR_SSCMode ---------------------------- */
\r
1678 #define USIC_CH_PCR_SSCMode_MSLSEN_Pos 0 /*!< USIC_CH PCR_SSCMode: MSLSEN Position */
\r
1679 #define USIC_CH_PCR_SSCMode_MSLSEN_Msk (0x01UL << USIC_CH_PCR_SSCMode_MSLSEN_Pos) /*!< USIC_CH PCR_SSCMode: MSLSEN Mask */
\r
1680 #define USIC_CH_PCR_SSCMode_SELCTR_Pos 1 /*!< USIC_CH PCR_SSCMode: SELCTR Position */
\r
1681 #define USIC_CH_PCR_SSCMode_SELCTR_Msk (0x01UL << USIC_CH_PCR_SSCMode_SELCTR_Pos) /*!< USIC_CH PCR_SSCMode: SELCTR Mask */
\r
1682 #define USIC_CH_PCR_SSCMode_SELINV_Pos 2 /*!< USIC_CH PCR_SSCMode: SELINV Position */
\r
1683 #define USIC_CH_PCR_SSCMode_SELINV_Msk (0x01UL << USIC_CH_PCR_SSCMode_SELINV_Pos) /*!< USIC_CH PCR_SSCMode: SELINV Mask */
\r
1684 #define USIC_CH_PCR_SSCMode_FEM_Pos 3 /*!< USIC_CH PCR_SSCMode: FEM Position */
\r
1685 #define USIC_CH_PCR_SSCMode_FEM_Msk (0x01UL << USIC_CH_PCR_SSCMode_FEM_Pos) /*!< USIC_CH PCR_SSCMode: FEM Mask */
\r
1686 #define USIC_CH_PCR_SSCMode_CTQSEL1_Pos 4 /*!< USIC_CH PCR_SSCMode: CTQSEL1 Position */
\r
1687 #define USIC_CH_PCR_SSCMode_CTQSEL1_Msk (0x03UL << USIC_CH_PCR_SSCMode_CTQSEL1_Pos) /*!< USIC_CH PCR_SSCMode: CTQSEL1 Mask */
\r
1688 #define USIC_CH_PCR_SSCMode_PCTQ1_Pos 6 /*!< USIC_CH PCR_SSCMode: PCTQ1 Position */
\r
1689 #define USIC_CH_PCR_SSCMode_PCTQ1_Msk (0x03UL << USIC_CH_PCR_SSCMode_PCTQ1_Pos) /*!< USIC_CH PCR_SSCMode: PCTQ1 Mask */
\r
1690 #define USIC_CH_PCR_SSCMode_DCTQ1_Pos 8 /*!< USIC_CH PCR_SSCMode: DCTQ1 Position */
\r
1691 #define USIC_CH_PCR_SSCMode_DCTQ1_Msk (0x1fUL << USIC_CH_PCR_SSCMode_DCTQ1_Pos) /*!< USIC_CH PCR_SSCMode: DCTQ1 Mask */
\r
1692 #define USIC_CH_PCR_SSCMode_PARIEN_Pos 13 /*!< USIC_CH PCR_SSCMode: PARIEN Position */
\r
1693 #define USIC_CH_PCR_SSCMode_PARIEN_Msk (0x01UL << USIC_CH_PCR_SSCMode_PARIEN_Pos) /*!< USIC_CH PCR_SSCMode: PARIEN Mask */
\r
1694 #define USIC_CH_PCR_SSCMode_MSLSIEN_Pos 14 /*!< USIC_CH PCR_SSCMode: MSLSIEN Position */
\r
1695 #define USIC_CH_PCR_SSCMode_MSLSIEN_Msk (0x01UL << USIC_CH_PCR_SSCMode_MSLSIEN_Pos) /*!< USIC_CH PCR_SSCMode: MSLSIEN Mask */
\r
1696 #define USIC_CH_PCR_SSCMode_DX2TIEN_Pos 15 /*!< USIC_CH PCR_SSCMode: DX2TIEN Position */
\r
1697 #define USIC_CH_PCR_SSCMode_DX2TIEN_Msk (0x01UL << USIC_CH_PCR_SSCMode_DX2TIEN_Pos) /*!< USIC_CH PCR_SSCMode: DX2TIEN Mask */
\r
1698 #define USIC_CH_PCR_SSCMode_SELO_Pos 16 /*!< USIC_CH PCR_SSCMode: SELO Position */
\r
1699 #define USIC_CH_PCR_SSCMode_SELO_Msk (0x000000ffUL << USIC_CH_PCR_SSCMode_SELO_Pos) /*!< USIC_CH PCR_SSCMode: SELO Mask */
\r
1700 #define USIC_CH_PCR_SSCMode_TIWEN_Pos 24 /*!< USIC_CH PCR_SSCMode: TIWEN Position */
\r
1701 #define USIC_CH_PCR_SSCMode_TIWEN_Msk (0x01UL << USIC_CH_PCR_SSCMode_TIWEN_Pos) /*!< USIC_CH PCR_SSCMode: TIWEN Mask */
\r
1702 #define USIC_CH_PCR_SSCMode_MCLK_Pos 31 /*!< USIC_CH PCR_SSCMode: MCLK Position */
\r
1703 #define USIC_CH_PCR_SSCMode_MCLK_Msk (0x01UL << USIC_CH_PCR_SSCMode_MCLK_Pos) /*!< USIC_CH PCR_SSCMode: MCLK Mask */
\r
1705 /* ----------------------------- USIC_CH_PCR_IICMode ---------------------------- */
\r
1706 #define USIC_CH_PCR_IICMode_SLAD_Pos 0 /*!< USIC_CH PCR_IICMode: SLAD Position */
\r
1707 #define USIC_CH_PCR_IICMode_SLAD_Msk (0x0000ffffUL << USIC_CH_PCR_IICMode_SLAD_Pos) /*!< USIC_CH PCR_IICMode: SLAD Mask */
\r
1708 #define USIC_CH_PCR_IICMode_ACK00_Pos 16 /*!< USIC_CH PCR_IICMode: ACK00 Position */
\r
1709 #define USIC_CH_PCR_IICMode_ACK00_Msk (0x01UL << USIC_CH_PCR_IICMode_ACK00_Pos) /*!< USIC_CH PCR_IICMode: ACK00 Mask */
\r
1710 #define USIC_CH_PCR_IICMode_STIM_Pos 17 /*!< USIC_CH PCR_IICMode: STIM Position */
\r
1711 #define USIC_CH_PCR_IICMode_STIM_Msk (0x01UL << USIC_CH_PCR_IICMode_STIM_Pos) /*!< USIC_CH PCR_IICMode: STIM Mask */
\r
1712 #define USIC_CH_PCR_IICMode_SCRIEN_Pos 18 /*!< USIC_CH PCR_IICMode: SCRIEN Position */
\r
1713 #define USIC_CH_PCR_IICMode_SCRIEN_Msk (0x01UL << USIC_CH_PCR_IICMode_SCRIEN_Pos) /*!< USIC_CH PCR_IICMode: SCRIEN Mask */
\r
1714 #define USIC_CH_PCR_IICMode_RSCRIEN_Pos 19 /*!< USIC_CH PCR_IICMode: RSCRIEN Position */
\r
1715 #define USIC_CH_PCR_IICMode_RSCRIEN_Msk (0x01UL << USIC_CH_PCR_IICMode_RSCRIEN_Pos) /*!< USIC_CH PCR_IICMode: RSCRIEN Mask */
\r
1716 #define USIC_CH_PCR_IICMode_PCRIEN_Pos 20 /*!< USIC_CH PCR_IICMode: PCRIEN Position */
\r
1717 #define USIC_CH_PCR_IICMode_PCRIEN_Msk (0x01UL << USIC_CH_PCR_IICMode_PCRIEN_Pos) /*!< USIC_CH PCR_IICMode: PCRIEN Mask */
\r
1718 #define USIC_CH_PCR_IICMode_NACKIEN_Pos 21 /*!< USIC_CH PCR_IICMode: NACKIEN Position */
\r
1719 #define USIC_CH_PCR_IICMode_NACKIEN_Msk (0x01UL << USIC_CH_PCR_IICMode_NACKIEN_Pos) /*!< USIC_CH PCR_IICMode: NACKIEN Mask */
\r
1720 #define USIC_CH_PCR_IICMode_ARLIEN_Pos 22 /*!< USIC_CH PCR_IICMode: ARLIEN Position */
\r
1721 #define USIC_CH_PCR_IICMode_ARLIEN_Msk (0x01UL << USIC_CH_PCR_IICMode_ARLIEN_Pos) /*!< USIC_CH PCR_IICMode: ARLIEN Mask */
\r
1722 #define USIC_CH_PCR_IICMode_SRRIEN_Pos 23 /*!< USIC_CH PCR_IICMode: SRRIEN Position */
\r
1723 #define USIC_CH_PCR_IICMode_SRRIEN_Msk (0x01UL << USIC_CH_PCR_IICMode_SRRIEN_Pos) /*!< USIC_CH PCR_IICMode: SRRIEN Mask */
\r
1724 #define USIC_CH_PCR_IICMode_ERRIEN_Pos 24 /*!< USIC_CH PCR_IICMode: ERRIEN Position */
\r
1725 #define USIC_CH_PCR_IICMode_ERRIEN_Msk (0x01UL << USIC_CH_PCR_IICMode_ERRIEN_Pos) /*!< USIC_CH PCR_IICMode: ERRIEN Mask */
\r
1726 #define USIC_CH_PCR_IICMode_SACKDIS_Pos 25 /*!< USIC_CH PCR_IICMode: SACKDIS Position */
\r
1727 #define USIC_CH_PCR_IICMode_SACKDIS_Msk (0x01UL << USIC_CH_PCR_IICMode_SACKDIS_Pos) /*!< USIC_CH PCR_IICMode: SACKDIS Mask */
\r
1728 #define USIC_CH_PCR_IICMode_HDEL_Pos 26 /*!< USIC_CH PCR_IICMode: HDEL Position */
\r
1729 #define USIC_CH_PCR_IICMode_HDEL_Msk (0x0fUL << USIC_CH_PCR_IICMode_HDEL_Pos) /*!< USIC_CH PCR_IICMode: HDEL Mask */
\r
1730 #define USIC_CH_PCR_IICMode_ACKIEN_Pos 30 /*!< USIC_CH PCR_IICMode: ACKIEN Position */
\r
1731 #define USIC_CH_PCR_IICMode_ACKIEN_Msk (0x01UL << USIC_CH_PCR_IICMode_ACKIEN_Pos) /*!< USIC_CH PCR_IICMode: ACKIEN Mask */
\r
1732 #define USIC_CH_PCR_IICMode_MCLK_Pos 31 /*!< USIC_CH PCR_IICMode: MCLK Position */
\r
1733 #define USIC_CH_PCR_IICMode_MCLK_Msk (0x01UL << USIC_CH_PCR_IICMode_MCLK_Pos) /*!< USIC_CH PCR_IICMode: MCLK Mask */
\r
1735 /* ----------------------------- USIC_CH_PCR_IISMode ---------------------------- */
\r
1736 #define USIC_CH_PCR_IISMode_WAGEN_Pos 0 /*!< USIC_CH PCR_IISMode: WAGEN Position */
\r
1737 #define USIC_CH_PCR_IISMode_WAGEN_Msk (0x01UL << USIC_CH_PCR_IISMode_WAGEN_Pos) /*!< USIC_CH PCR_IISMode: WAGEN Mask */
\r
1738 #define USIC_CH_PCR_IISMode_DTEN_Pos 1 /*!< USIC_CH PCR_IISMode: DTEN Position */
\r
1739 #define USIC_CH_PCR_IISMode_DTEN_Msk (0x01UL << USIC_CH_PCR_IISMode_DTEN_Pos) /*!< USIC_CH PCR_IISMode: DTEN Mask */
\r
1740 #define USIC_CH_PCR_IISMode_SELINV_Pos 2 /*!< USIC_CH PCR_IISMode: SELINV Position */
\r
1741 #define USIC_CH_PCR_IISMode_SELINV_Msk (0x01UL << USIC_CH_PCR_IISMode_SELINV_Pos) /*!< USIC_CH PCR_IISMode: SELINV Mask */
\r
1742 #define USIC_CH_PCR_IISMode_WAFEIEN_Pos 4 /*!< USIC_CH PCR_IISMode: WAFEIEN Position */
\r
1743 #define USIC_CH_PCR_IISMode_WAFEIEN_Msk (0x01UL << USIC_CH_PCR_IISMode_WAFEIEN_Pos) /*!< USIC_CH PCR_IISMode: WAFEIEN Mask */
\r
1744 #define USIC_CH_PCR_IISMode_WAREIEN_Pos 5 /*!< USIC_CH PCR_IISMode: WAREIEN Position */
\r
1745 #define USIC_CH_PCR_IISMode_WAREIEN_Msk (0x01UL << USIC_CH_PCR_IISMode_WAREIEN_Pos) /*!< USIC_CH PCR_IISMode: WAREIEN Mask */
\r
1746 #define USIC_CH_PCR_IISMode_ENDIEN_Pos 6 /*!< USIC_CH PCR_IISMode: ENDIEN Position */
\r
1747 #define USIC_CH_PCR_IISMode_ENDIEN_Msk (0x01UL << USIC_CH_PCR_IISMode_ENDIEN_Pos) /*!< USIC_CH PCR_IISMode: ENDIEN Mask */
\r
1748 #define USIC_CH_PCR_IISMode_DX2TIEN_Pos 15 /*!< USIC_CH PCR_IISMode: DX2TIEN Position */
\r
1749 #define USIC_CH_PCR_IISMode_DX2TIEN_Msk (0x01UL << USIC_CH_PCR_IISMode_DX2TIEN_Pos) /*!< USIC_CH PCR_IISMode: DX2TIEN Mask */
\r
1750 #define USIC_CH_PCR_IISMode_TDEL_Pos 16 /*!< USIC_CH PCR_IISMode: TDEL Position */
\r
1751 #define USIC_CH_PCR_IISMode_TDEL_Msk (0x3fUL << USIC_CH_PCR_IISMode_TDEL_Pos) /*!< USIC_CH PCR_IISMode: TDEL Mask */
\r
1752 #define USIC_CH_PCR_IISMode_MCLK_Pos 31 /*!< USIC_CH PCR_IISMode: MCLK Position */
\r
1753 #define USIC_CH_PCR_IISMode_MCLK_Msk (0x01UL << USIC_CH_PCR_IISMode_MCLK_Pos) /*!< USIC_CH PCR_IISMode: MCLK Mask */
\r
1755 /* --------------------------------- USIC_CH_CCR -------------------------------- */
\r
1756 #define USIC_CH_CCR_MODE_Pos 0 /*!< USIC_CH CCR: MODE Position */
\r
1757 #define USIC_CH_CCR_MODE_Msk (0x0fUL << USIC_CH_CCR_MODE_Pos) /*!< USIC_CH CCR: MODE Mask */
\r
1758 #define USIC_CH_CCR_HPCEN_Pos 6 /*!< USIC_CH CCR: HPCEN Position */
\r
1759 #define USIC_CH_CCR_HPCEN_Msk (0x03UL << USIC_CH_CCR_HPCEN_Pos) /*!< USIC_CH CCR: HPCEN Mask */
\r
1760 #define USIC_CH_CCR_PM_Pos 8 /*!< USIC_CH CCR: PM Position */
\r
1761 #define USIC_CH_CCR_PM_Msk (0x03UL << USIC_CH_CCR_PM_Pos) /*!< USIC_CH CCR: PM Mask */
\r
1762 #define USIC_CH_CCR_RSIEN_Pos 10 /*!< USIC_CH CCR: RSIEN Position */
\r
1763 #define USIC_CH_CCR_RSIEN_Msk (0x01UL << USIC_CH_CCR_RSIEN_Pos) /*!< USIC_CH CCR: RSIEN Mask */
\r
1764 #define USIC_CH_CCR_DLIEN_Pos 11 /*!< USIC_CH CCR: DLIEN Position */
\r
1765 #define USIC_CH_CCR_DLIEN_Msk (0x01UL << USIC_CH_CCR_DLIEN_Pos) /*!< USIC_CH CCR: DLIEN Mask */
\r
1766 #define USIC_CH_CCR_TSIEN_Pos 12 /*!< USIC_CH CCR: TSIEN Position */
\r
1767 #define USIC_CH_CCR_TSIEN_Msk (0x01UL << USIC_CH_CCR_TSIEN_Pos) /*!< USIC_CH CCR: TSIEN Mask */
\r
1768 #define USIC_CH_CCR_TBIEN_Pos 13 /*!< USIC_CH CCR: TBIEN Position */
\r
1769 #define USIC_CH_CCR_TBIEN_Msk (0x01UL << USIC_CH_CCR_TBIEN_Pos) /*!< USIC_CH CCR: TBIEN Mask */
\r
1770 #define USIC_CH_CCR_RIEN_Pos 14 /*!< USIC_CH CCR: RIEN Position */
\r
1771 #define USIC_CH_CCR_RIEN_Msk (0x01UL << USIC_CH_CCR_RIEN_Pos) /*!< USIC_CH CCR: RIEN Mask */
\r
1772 #define USIC_CH_CCR_AIEN_Pos 15 /*!< USIC_CH CCR: AIEN Position */
\r
1773 #define USIC_CH_CCR_AIEN_Msk (0x01UL << USIC_CH_CCR_AIEN_Pos) /*!< USIC_CH CCR: AIEN Mask */
\r
1774 #define USIC_CH_CCR_BRGIEN_Pos 16 /*!< USIC_CH CCR: BRGIEN Position */
\r
1775 #define USIC_CH_CCR_BRGIEN_Msk (0x01UL << USIC_CH_CCR_BRGIEN_Pos) /*!< USIC_CH CCR: BRGIEN Mask */
\r
1777 /* -------------------------------- USIC_CH_CMTR -------------------------------- */
\r
1778 #define USIC_CH_CMTR_CTV_Pos 0 /*!< USIC_CH CMTR: CTV Position */
\r
1779 #define USIC_CH_CMTR_CTV_Msk (0x000003ffUL << USIC_CH_CMTR_CTV_Pos) /*!< USIC_CH CMTR: CTV Mask */
\r
1781 /* --------------------------------- USIC_CH_PSR -------------------------------- */
\r
1782 #define USIC_CH_PSR_ST0_Pos 0 /*!< USIC_CH PSR: ST0 Position */
\r
1783 #define USIC_CH_PSR_ST0_Msk (0x01UL << USIC_CH_PSR_ST0_Pos) /*!< USIC_CH PSR: ST0 Mask */
\r
1784 #define USIC_CH_PSR_ST1_Pos 1 /*!< USIC_CH PSR: ST1 Position */
\r
1785 #define USIC_CH_PSR_ST1_Msk (0x01UL << USIC_CH_PSR_ST1_Pos) /*!< USIC_CH PSR: ST1 Mask */
\r
1786 #define USIC_CH_PSR_ST2_Pos 2 /*!< USIC_CH PSR: ST2 Position */
\r
1787 #define USIC_CH_PSR_ST2_Msk (0x01UL << USIC_CH_PSR_ST2_Pos) /*!< USIC_CH PSR: ST2 Mask */
\r
1788 #define USIC_CH_PSR_ST3_Pos 3 /*!< USIC_CH PSR: ST3 Position */
\r
1789 #define USIC_CH_PSR_ST3_Msk (0x01UL << USIC_CH_PSR_ST3_Pos) /*!< USIC_CH PSR: ST3 Mask */
\r
1790 #define USIC_CH_PSR_ST4_Pos 4 /*!< USIC_CH PSR: ST4 Position */
\r
1791 #define USIC_CH_PSR_ST4_Msk (0x01UL << USIC_CH_PSR_ST4_Pos) /*!< USIC_CH PSR: ST4 Mask */
\r
1792 #define USIC_CH_PSR_ST5_Pos 5 /*!< USIC_CH PSR: ST5 Position */
\r
1793 #define USIC_CH_PSR_ST5_Msk (0x01UL << USIC_CH_PSR_ST5_Pos) /*!< USIC_CH PSR: ST5 Mask */
\r
1794 #define USIC_CH_PSR_ST6_Pos 6 /*!< USIC_CH PSR: ST6 Position */
\r
1795 #define USIC_CH_PSR_ST6_Msk (0x01UL << USIC_CH_PSR_ST6_Pos) /*!< USIC_CH PSR: ST6 Mask */
\r
1796 #define USIC_CH_PSR_ST7_Pos 7 /*!< USIC_CH PSR: ST7 Position */
\r
1797 #define USIC_CH_PSR_ST7_Msk (0x01UL << USIC_CH_PSR_ST7_Pos) /*!< USIC_CH PSR: ST7 Mask */
\r
1798 #define USIC_CH_PSR_ST8_Pos 8 /*!< USIC_CH PSR: ST8 Position */
\r
1799 #define USIC_CH_PSR_ST8_Msk (0x01UL << USIC_CH_PSR_ST8_Pos) /*!< USIC_CH PSR: ST8 Mask */
\r
1800 #define USIC_CH_PSR_ST9_Pos 9 /*!< USIC_CH PSR: ST9 Position */
\r
1801 #define USIC_CH_PSR_ST9_Msk (0x01UL << USIC_CH_PSR_ST9_Pos) /*!< USIC_CH PSR: ST9 Mask */
\r
1802 #define USIC_CH_PSR_RSIF_Pos 10 /*!< USIC_CH PSR: RSIF Position */
\r
1803 #define USIC_CH_PSR_RSIF_Msk (0x01UL << USIC_CH_PSR_RSIF_Pos) /*!< USIC_CH PSR: RSIF Mask */
\r
1804 #define USIC_CH_PSR_DLIF_Pos 11 /*!< USIC_CH PSR: DLIF Position */
\r
1805 #define USIC_CH_PSR_DLIF_Msk (0x01UL << USIC_CH_PSR_DLIF_Pos) /*!< USIC_CH PSR: DLIF Mask */
\r
1806 #define USIC_CH_PSR_TSIF_Pos 12 /*!< USIC_CH PSR: TSIF Position */
\r
1807 #define USIC_CH_PSR_TSIF_Msk (0x01UL << USIC_CH_PSR_TSIF_Pos) /*!< USIC_CH PSR: TSIF Mask */
\r
1808 #define USIC_CH_PSR_TBIF_Pos 13 /*!< USIC_CH PSR: TBIF Position */
\r
1809 #define USIC_CH_PSR_TBIF_Msk (0x01UL << USIC_CH_PSR_TBIF_Pos) /*!< USIC_CH PSR: TBIF Mask */
\r
1810 #define USIC_CH_PSR_RIF_Pos 14 /*!< USIC_CH PSR: RIF Position */
\r
1811 #define USIC_CH_PSR_RIF_Msk (0x01UL << USIC_CH_PSR_RIF_Pos) /*!< USIC_CH PSR: RIF Mask */
\r
1812 #define USIC_CH_PSR_AIF_Pos 15 /*!< USIC_CH PSR: AIF Position */
\r
1813 #define USIC_CH_PSR_AIF_Msk (0x01UL << USIC_CH_PSR_AIF_Pos) /*!< USIC_CH PSR: AIF Mask */
\r
1814 #define USIC_CH_PSR_BRGIF_Pos 16 /*!< USIC_CH PSR: BRGIF Position */
\r
1815 #define USIC_CH_PSR_BRGIF_Msk (0x01UL << USIC_CH_PSR_BRGIF_Pos) /*!< USIC_CH PSR: BRGIF Mask */
\r
1817 /* ----------------------------- USIC_CH_PSR_ASCMode ---------------------------- */
\r
1818 #define USIC_CH_PSR_ASCMode_TXIDLE_Pos 0 /*!< USIC_CH PSR_ASCMode: TXIDLE Position */
\r
1819 #define USIC_CH_PSR_ASCMode_TXIDLE_Msk (0x01UL << USIC_CH_PSR_ASCMode_TXIDLE_Pos) /*!< USIC_CH PSR_ASCMode: TXIDLE Mask */
\r
1820 #define USIC_CH_PSR_ASCMode_RXIDLE_Pos 1 /*!< USIC_CH PSR_ASCMode: RXIDLE Position */
\r
1821 #define USIC_CH_PSR_ASCMode_RXIDLE_Msk (0x01UL << USIC_CH_PSR_ASCMode_RXIDLE_Pos) /*!< USIC_CH PSR_ASCMode: RXIDLE Mask */
\r
1822 #define USIC_CH_PSR_ASCMode_SBD_Pos 2 /*!< USIC_CH PSR_ASCMode: SBD Position */
\r
1823 #define USIC_CH_PSR_ASCMode_SBD_Msk (0x01UL << USIC_CH_PSR_ASCMode_SBD_Pos) /*!< USIC_CH PSR_ASCMode: SBD Mask */
\r
1824 #define USIC_CH_PSR_ASCMode_COL_Pos 3 /*!< USIC_CH PSR_ASCMode: COL Position */
\r
1825 #define USIC_CH_PSR_ASCMode_COL_Msk (0x01UL << USIC_CH_PSR_ASCMode_COL_Pos) /*!< USIC_CH PSR_ASCMode: COL Mask */
\r
1826 #define USIC_CH_PSR_ASCMode_RNS_Pos 4 /*!< USIC_CH PSR_ASCMode: RNS Position */
\r
1827 #define USIC_CH_PSR_ASCMode_RNS_Msk (0x01UL << USIC_CH_PSR_ASCMode_RNS_Pos) /*!< USIC_CH PSR_ASCMode: RNS Mask */
\r
1828 #define USIC_CH_PSR_ASCMode_FER0_Pos 5 /*!< USIC_CH PSR_ASCMode: FER0 Position */
\r
1829 #define USIC_CH_PSR_ASCMode_FER0_Msk (0x01UL << USIC_CH_PSR_ASCMode_FER0_Pos) /*!< USIC_CH PSR_ASCMode: FER0 Mask */
\r
1830 #define USIC_CH_PSR_ASCMode_FER1_Pos 6 /*!< USIC_CH PSR_ASCMode: FER1 Position */
\r
1831 #define USIC_CH_PSR_ASCMode_FER1_Msk (0x01UL << USIC_CH_PSR_ASCMode_FER1_Pos) /*!< USIC_CH PSR_ASCMode: FER1 Mask */
\r
1832 #define USIC_CH_PSR_ASCMode_RFF_Pos 7 /*!< USIC_CH PSR_ASCMode: RFF Position */
\r
1833 #define USIC_CH_PSR_ASCMode_RFF_Msk (0x01UL << USIC_CH_PSR_ASCMode_RFF_Pos) /*!< USIC_CH PSR_ASCMode: RFF Mask */
\r
1834 #define USIC_CH_PSR_ASCMode_TFF_Pos 8 /*!< USIC_CH PSR_ASCMode: TFF Position */
\r
1835 #define USIC_CH_PSR_ASCMode_TFF_Msk (0x01UL << USIC_CH_PSR_ASCMode_TFF_Pos) /*!< USIC_CH PSR_ASCMode: TFF Mask */
\r
1836 #define USIC_CH_PSR_ASCMode_BUSY_Pos 9 /*!< USIC_CH PSR_ASCMode: BUSY Position */
\r
1837 #define USIC_CH_PSR_ASCMode_BUSY_Msk (0x01UL << USIC_CH_PSR_ASCMode_BUSY_Pos) /*!< USIC_CH PSR_ASCMode: BUSY Mask */
\r
1838 #define USIC_CH_PSR_ASCMode_RSIF_Pos 10 /*!< USIC_CH PSR_ASCMode: RSIF Position */
\r
1839 #define USIC_CH_PSR_ASCMode_RSIF_Msk (0x01UL << USIC_CH_PSR_ASCMode_RSIF_Pos) /*!< USIC_CH PSR_ASCMode: RSIF Mask */
\r
1840 #define USIC_CH_PSR_ASCMode_DLIF_Pos 11 /*!< USIC_CH PSR_ASCMode: DLIF Position */
\r
1841 #define USIC_CH_PSR_ASCMode_DLIF_Msk (0x01UL << USIC_CH_PSR_ASCMode_DLIF_Pos) /*!< USIC_CH PSR_ASCMode: DLIF Mask */
\r
1842 #define USIC_CH_PSR_ASCMode_TSIF_Pos 12 /*!< USIC_CH PSR_ASCMode: TSIF Position */
\r
1843 #define USIC_CH_PSR_ASCMode_TSIF_Msk (0x01UL << USIC_CH_PSR_ASCMode_TSIF_Pos) /*!< USIC_CH PSR_ASCMode: TSIF Mask */
\r
1844 #define USIC_CH_PSR_ASCMode_TBIF_Pos 13 /*!< USIC_CH PSR_ASCMode: TBIF Position */
\r
1845 #define USIC_CH_PSR_ASCMode_TBIF_Msk (0x01UL << USIC_CH_PSR_ASCMode_TBIF_Pos) /*!< USIC_CH PSR_ASCMode: TBIF Mask */
\r
1846 #define USIC_CH_PSR_ASCMode_RIF_Pos 14 /*!< USIC_CH PSR_ASCMode: RIF Position */
\r
1847 #define USIC_CH_PSR_ASCMode_RIF_Msk (0x01UL << USIC_CH_PSR_ASCMode_RIF_Pos) /*!< USIC_CH PSR_ASCMode: RIF Mask */
\r
1848 #define USIC_CH_PSR_ASCMode_AIF_Pos 15 /*!< USIC_CH PSR_ASCMode: AIF Position */
\r
1849 #define USIC_CH_PSR_ASCMode_AIF_Msk (0x01UL << USIC_CH_PSR_ASCMode_AIF_Pos) /*!< USIC_CH PSR_ASCMode: AIF Mask */
\r
1850 #define USIC_CH_PSR_ASCMode_BRGIF_Pos 16 /*!< USIC_CH PSR_ASCMode: BRGIF Position */
\r
1851 #define USIC_CH_PSR_ASCMode_BRGIF_Msk (0x01UL << USIC_CH_PSR_ASCMode_BRGIF_Pos) /*!< USIC_CH PSR_ASCMode: BRGIF Mask */
\r
1853 /* ----------------------------- USIC_CH_PSR_SSCMode ---------------------------- */
\r
1854 #define USIC_CH_PSR_SSCMode_MSLS_Pos 0 /*!< USIC_CH PSR_SSCMode: MSLS Position */
\r
1855 #define USIC_CH_PSR_SSCMode_MSLS_Msk (0x01UL << USIC_CH_PSR_SSCMode_MSLS_Pos) /*!< USIC_CH PSR_SSCMode: MSLS Mask */
\r
1856 #define USIC_CH_PSR_SSCMode_DX2S_Pos 1 /*!< USIC_CH PSR_SSCMode: DX2S Position */
\r
1857 #define USIC_CH_PSR_SSCMode_DX2S_Msk (0x01UL << USIC_CH_PSR_SSCMode_DX2S_Pos) /*!< USIC_CH PSR_SSCMode: DX2S Mask */
\r
1858 #define USIC_CH_PSR_SSCMode_MSLSEV_Pos 2 /*!< USIC_CH PSR_SSCMode: MSLSEV Position */
\r
1859 #define USIC_CH_PSR_SSCMode_MSLSEV_Msk (0x01UL << USIC_CH_PSR_SSCMode_MSLSEV_Pos) /*!< USIC_CH PSR_SSCMode: MSLSEV Mask */
\r
1860 #define USIC_CH_PSR_SSCMode_DX2TEV_Pos 3 /*!< USIC_CH PSR_SSCMode: DX2TEV Position */
\r
1861 #define USIC_CH_PSR_SSCMode_DX2TEV_Msk (0x01UL << USIC_CH_PSR_SSCMode_DX2TEV_Pos) /*!< USIC_CH PSR_SSCMode: DX2TEV Mask */
\r
1862 #define USIC_CH_PSR_SSCMode_PARERR_Pos 4 /*!< USIC_CH PSR_SSCMode: PARERR Position */
\r
1863 #define USIC_CH_PSR_SSCMode_PARERR_Msk (0x01UL << USIC_CH_PSR_SSCMode_PARERR_Pos) /*!< USIC_CH PSR_SSCMode: PARERR Mask */
\r
1864 #define USIC_CH_PSR_SSCMode_RSIF_Pos 10 /*!< USIC_CH PSR_SSCMode: RSIF Position */
\r
1865 #define USIC_CH_PSR_SSCMode_RSIF_Msk (0x01UL << USIC_CH_PSR_SSCMode_RSIF_Pos) /*!< USIC_CH PSR_SSCMode: RSIF Mask */
\r
1866 #define USIC_CH_PSR_SSCMode_DLIF_Pos 11 /*!< USIC_CH PSR_SSCMode: DLIF Position */
\r
1867 #define USIC_CH_PSR_SSCMode_DLIF_Msk (0x01UL << USIC_CH_PSR_SSCMode_DLIF_Pos) /*!< USIC_CH PSR_SSCMode: DLIF Mask */
\r
1868 #define USIC_CH_PSR_SSCMode_TSIF_Pos 12 /*!< USIC_CH PSR_SSCMode: TSIF Position */
\r
1869 #define USIC_CH_PSR_SSCMode_TSIF_Msk (0x01UL << USIC_CH_PSR_SSCMode_TSIF_Pos) /*!< USIC_CH PSR_SSCMode: TSIF Mask */
\r
1870 #define USIC_CH_PSR_SSCMode_TBIF_Pos 13 /*!< USIC_CH PSR_SSCMode: TBIF Position */
\r
1871 #define USIC_CH_PSR_SSCMode_TBIF_Msk (0x01UL << USIC_CH_PSR_SSCMode_TBIF_Pos) /*!< USIC_CH PSR_SSCMode: TBIF Mask */
\r
1872 #define USIC_CH_PSR_SSCMode_RIF_Pos 14 /*!< USIC_CH PSR_SSCMode: RIF Position */
\r
1873 #define USIC_CH_PSR_SSCMode_RIF_Msk (0x01UL << USIC_CH_PSR_SSCMode_RIF_Pos) /*!< USIC_CH PSR_SSCMode: RIF Mask */
\r
1874 #define USIC_CH_PSR_SSCMode_AIF_Pos 15 /*!< USIC_CH PSR_SSCMode: AIF Position */
\r
1875 #define USIC_CH_PSR_SSCMode_AIF_Msk (0x01UL << USIC_CH_PSR_SSCMode_AIF_Pos) /*!< USIC_CH PSR_SSCMode: AIF Mask */
\r
1876 #define USIC_CH_PSR_SSCMode_BRGIF_Pos 16 /*!< USIC_CH PSR_SSCMode: BRGIF Position */
\r
1877 #define USIC_CH_PSR_SSCMode_BRGIF_Msk (0x01UL << USIC_CH_PSR_SSCMode_BRGIF_Pos) /*!< USIC_CH PSR_SSCMode: BRGIF Mask */
\r
1879 /* ----------------------------- USIC_CH_PSR_IICMode ---------------------------- */
\r
1880 #define USIC_CH_PSR_IICMode_SLSEL_Pos 0 /*!< USIC_CH PSR_IICMode: SLSEL Position */
\r
1881 #define USIC_CH_PSR_IICMode_SLSEL_Msk (0x01UL << USIC_CH_PSR_IICMode_SLSEL_Pos) /*!< USIC_CH PSR_IICMode: SLSEL Mask */
\r
1882 #define USIC_CH_PSR_IICMode_WTDF_Pos 1 /*!< USIC_CH PSR_IICMode: WTDF Position */
\r
1883 #define USIC_CH_PSR_IICMode_WTDF_Msk (0x01UL << USIC_CH_PSR_IICMode_WTDF_Pos) /*!< USIC_CH PSR_IICMode: WTDF Mask */
\r
1884 #define USIC_CH_PSR_IICMode_SCR_Pos 2 /*!< USIC_CH PSR_IICMode: SCR Position */
\r
1885 #define USIC_CH_PSR_IICMode_SCR_Msk (0x01UL << USIC_CH_PSR_IICMode_SCR_Pos) /*!< USIC_CH PSR_IICMode: SCR Mask */
\r
1886 #define USIC_CH_PSR_IICMode_RSCR_Pos 3 /*!< USIC_CH PSR_IICMode: RSCR Position */
\r
1887 #define USIC_CH_PSR_IICMode_RSCR_Msk (0x01UL << USIC_CH_PSR_IICMode_RSCR_Pos) /*!< USIC_CH PSR_IICMode: RSCR Mask */
\r
1888 #define USIC_CH_PSR_IICMode_PCR_Pos 4 /*!< USIC_CH PSR_IICMode: PCR Position */
\r
1889 #define USIC_CH_PSR_IICMode_PCR_Msk (0x01UL << USIC_CH_PSR_IICMode_PCR_Pos) /*!< USIC_CH PSR_IICMode: PCR Mask */
\r
1890 #define USIC_CH_PSR_IICMode_NACK_Pos 5 /*!< USIC_CH PSR_IICMode: NACK Position */
\r
1891 #define USIC_CH_PSR_IICMode_NACK_Msk (0x01UL << USIC_CH_PSR_IICMode_NACK_Pos) /*!< USIC_CH PSR_IICMode: NACK Mask */
\r
1892 #define USIC_CH_PSR_IICMode_ARL_Pos 6 /*!< USIC_CH PSR_IICMode: ARL Position */
\r
1893 #define USIC_CH_PSR_IICMode_ARL_Msk (0x01UL << USIC_CH_PSR_IICMode_ARL_Pos) /*!< USIC_CH PSR_IICMode: ARL Mask */
\r
1894 #define USIC_CH_PSR_IICMode_SRR_Pos 7 /*!< USIC_CH PSR_IICMode: SRR Position */
\r
1895 #define USIC_CH_PSR_IICMode_SRR_Msk (0x01UL << USIC_CH_PSR_IICMode_SRR_Pos) /*!< USIC_CH PSR_IICMode: SRR Mask */
\r
1896 #define USIC_CH_PSR_IICMode_ERR_Pos 8 /*!< USIC_CH PSR_IICMode: ERR Position */
\r
1897 #define USIC_CH_PSR_IICMode_ERR_Msk (0x01UL << USIC_CH_PSR_IICMode_ERR_Pos) /*!< USIC_CH PSR_IICMode: ERR Mask */
\r
1898 #define USIC_CH_PSR_IICMode_ACK_Pos 9 /*!< USIC_CH PSR_IICMode: ACK Position */
\r
1899 #define USIC_CH_PSR_IICMode_ACK_Msk (0x01UL << USIC_CH_PSR_IICMode_ACK_Pos) /*!< USIC_CH PSR_IICMode: ACK Mask */
\r
1900 #define USIC_CH_PSR_IICMode_RSIF_Pos 10 /*!< USIC_CH PSR_IICMode: RSIF Position */
\r
1901 #define USIC_CH_PSR_IICMode_RSIF_Msk (0x01UL << USIC_CH_PSR_IICMode_RSIF_Pos) /*!< USIC_CH PSR_IICMode: RSIF Mask */
\r
1902 #define USIC_CH_PSR_IICMode_DLIF_Pos 11 /*!< USIC_CH PSR_IICMode: DLIF Position */
\r
1903 #define USIC_CH_PSR_IICMode_DLIF_Msk (0x01UL << USIC_CH_PSR_IICMode_DLIF_Pos) /*!< USIC_CH PSR_IICMode: DLIF Mask */
\r
1904 #define USIC_CH_PSR_IICMode_TSIF_Pos 12 /*!< USIC_CH PSR_IICMode: TSIF Position */
\r
1905 #define USIC_CH_PSR_IICMode_TSIF_Msk (0x01UL << USIC_CH_PSR_IICMode_TSIF_Pos) /*!< USIC_CH PSR_IICMode: TSIF Mask */
\r
1906 #define USIC_CH_PSR_IICMode_TBIF_Pos 13 /*!< USIC_CH PSR_IICMode: TBIF Position */
\r
1907 #define USIC_CH_PSR_IICMode_TBIF_Msk (0x01UL << USIC_CH_PSR_IICMode_TBIF_Pos) /*!< USIC_CH PSR_IICMode: TBIF Mask */
\r
1908 #define USIC_CH_PSR_IICMode_RIF_Pos 14 /*!< USIC_CH PSR_IICMode: RIF Position */
\r
1909 #define USIC_CH_PSR_IICMode_RIF_Msk (0x01UL << USIC_CH_PSR_IICMode_RIF_Pos) /*!< USIC_CH PSR_IICMode: RIF Mask */
\r
1910 #define USIC_CH_PSR_IICMode_AIF_Pos 15 /*!< USIC_CH PSR_IICMode: AIF Position */
\r
1911 #define USIC_CH_PSR_IICMode_AIF_Msk (0x01UL << USIC_CH_PSR_IICMode_AIF_Pos) /*!< USIC_CH PSR_IICMode: AIF Mask */
\r
1912 #define USIC_CH_PSR_IICMode_BRGIF_Pos 16 /*!< USIC_CH PSR_IICMode: BRGIF Position */
\r
1913 #define USIC_CH_PSR_IICMode_BRGIF_Msk (0x01UL << USIC_CH_PSR_IICMode_BRGIF_Pos) /*!< USIC_CH PSR_IICMode: BRGIF Mask */
\r
1915 /* ----------------------------- USIC_CH_PSR_IISMode ---------------------------- */
\r
1916 #define USIC_CH_PSR_IISMode_WA_Pos 0 /*!< USIC_CH PSR_IISMode: WA Position */
\r
1917 #define USIC_CH_PSR_IISMode_WA_Msk (0x01UL << USIC_CH_PSR_IISMode_WA_Pos) /*!< USIC_CH PSR_IISMode: WA Mask */
\r
1918 #define USIC_CH_PSR_IISMode_DX2S_Pos 1 /*!< USIC_CH PSR_IISMode: DX2S Position */
\r
1919 #define USIC_CH_PSR_IISMode_DX2S_Msk (0x01UL << USIC_CH_PSR_IISMode_DX2S_Pos) /*!< USIC_CH PSR_IISMode: DX2S Mask */
\r
1920 #define USIC_CH_PSR_IISMode_DX2TEV_Pos 3 /*!< USIC_CH PSR_IISMode: DX2TEV Position */
\r
1921 #define USIC_CH_PSR_IISMode_DX2TEV_Msk (0x01UL << USIC_CH_PSR_IISMode_DX2TEV_Pos) /*!< USIC_CH PSR_IISMode: DX2TEV Mask */
\r
1922 #define USIC_CH_PSR_IISMode_WAFE_Pos 4 /*!< USIC_CH PSR_IISMode: WAFE Position */
\r
1923 #define USIC_CH_PSR_IISMode_WAFE_Msk (0x01UL << USIC_CH_PSR_IISMode_WAFE_Pos) /*!< USIC_CH PSR_IISMode: WAFE Mask */
\r
1924 #define USIC_CH_PSR_IISMode_WARE_Pos 5 /*!< USIC_CH PSR_IISMode: WARE Position */
\r
1925 #define USIC_CH_PSR_IISMode_WARE_Msk (0x01UL << USIC_CH_PSR_IISMode_WARE_Pos) /*!< USIC_CH PSR_IISMode: WARE Mask */
\r
1926 #define USIC_CH_PSR_IISMode_END_Pos 6 /*!< USIC_CH PSR_IISMode: END Position */
\r
1927 #define USIC_CH_PSR_IISMode_END_Msk (0x01UL << USIC_CH_PSR_IISMode_END_Pos) /*!< USIC_CH PSR_IISMode: END Mask */
\r
1928 #define USIC_CH_PSR_IISMode_RSIF_Pos 10 /*!< USIC_CH PSR_IISMode: RSIF Position */
\r
1929 #define USIC_CH_PSR_IISMode_RSIF_Msk (0x01UL << USIC_CH_PSR_IISMode_RSIF_Pos) /*!< USIC_CH PSR_IISMode: RSIF Mask */
\r
1930 #define USIC_CH_PSR_IISMode_DLIF_Pos 11 /*!< USIC_CH PSR_IISMode: DLIF Position */
\r
1931 #define USIC_CH_PSR_IISMode_DLIF_Msk (0x01UL << USIC_CH_PSR_IISMode_DLIF_Pos) /*!< USIC_CH PSR_IISMode: DLIF Mask */
\r
1932 #define USIC_CH_PSR_IISMode_TSIF_Pos 12 /*!< USIC_CH PSR_IISMode: TSIF Position */
\r
1933 #define USIC_CH_PSR_IISMode_TSIF_Msk (0x01UL << USIC_CH_PSR_IISMode_TSIF_Pos) /*!< USIC_CH PSR_IISMode: TSIF Mask */
\r
1934 #define USIC_CH_PSR_IISMode_TBIF_Pos 13 /*!< USIC_CH PSR_IISMode: TBIF Position */
\r
1935 #define USIC_CH_PSR_IISMode_TBIF_Msk (0x01UL << USIC_CH_PSR_IISMode_TBIF_Pos) /*!< USIC_CH PSR_IISMode: TBIF Mask */
\r
1936 #define USIC_CH_PSR_IISMode_RIF_Pos 14 /*!< USIC_CH PSR_IISMode: RIF Position */
\r
1937 #define USIC_CH_PSR_IISMode_RIF_Msk (0x01UL << USIC_CH_PSR_IISMode_RIF_Pos) /*!< USIC_CH PSR_IISMode: RIF Mask */
\r
1938 #define USIC_CH_PSR_IISMode_AIF_Pos 15 /*!< USIC_CH PSR_IISMode: AIF Position */
\r
1939 #define USIC_CH_PSR_IISMode_AIF_Msk (0x01UL << USIC_CH_PSR_IISMode_AIF_Pos) /*!< USIC_CH PSR_IISMode: AIF Mask */
\r
1940 #define USIC_CH_PSR_IISMode_BRGIF_Pos 16 /*!< USIC_CH PSR_IISMode: BRGIF Position */
\r
1941 #define USIC_CH_PSR_IISMode_BRGIF_Msk (0x01UL << USIC_CH_PSR_IISMode_BRGIF_Pos) /*!< USIC_CH PSR_IISMode: BRGIF Mask */
\r
1943 /* -------------------------------- USIC_CH_PSCR -------------------------------- */
\r
1944 #define USIC_CH_PSCR_CST0_Pos 0 /*!< USIC_CH PSCR: CST0 Position */
\r
1945 #define USIC_CH_PSCR_CST0_Msk (0x01UL << USIC_CH_PSCR_CST0_Pos) /*!< USIC_CH PSCR: CST0 Mask */
\r
1946 #define USIC_CH_PSCR_CST1_Pos 1 /*!< USIC_CH PSCR: CST1 Position */
\r
1947 #define USIC_CH_PSCR_CST1_Msk (0x01UL << USIC_CH_PSCR_CST1_Pos) /*!< USIC_CH PSCR: CST1 Mask */
\r
1948 #define USIC_CH_PSCR_CST2_Pos 2 /*!< USIC_CH PSCR: CST2 Position */
\r
1949 #define USIC_CH_PSCR_CST2_Msk (0x01UL << USIC_CH_PSCR_CST2_Pos) /*!< USIC_CH PSCR: CST2 Mask */
\r
1950 #define USIC_CH_PSCR_CST3_Pos 3 /*!< USIC_CH PSCR: CST3 Position */
\r
1951 #define USIC_CH_PSCR_CST3_Msk (0x01UL << USIC_CH_PSCR_CST3_Pos) /*!< USIC_CH PSCR: CST3 Mask */
\r
1952 #define USIC_CH_PSCR_CST4_Pos 4 /*!< USIC_CH PSCR: CST4 Position */
\r
1953 #define USIC_CH_PSCR_CST4_Msk (0x01UL << USIC_CH_PSCR_CST4_Pos) /*!< USIC_CH PSCR: CST4 Mask */
\r
1954 #define USIC_CH_PSCR_CST5_Pos 5 /*!< USIC_CH PSCR: CST5 Position */
\r
1955 #define USIC_CH_PSCR_CST5_Msk (0x01UL << USIC_CH_PSCR_CST5_Pos) /*!< USIC_CH PSCR: CST5 Mask */
\r
1956 #define USIC_CH_PSCR_CST6_Pos 6 /*!< USIC_CH PSCR: CST6 Position */
\r
1957 #define USIC_CH_PSCR_CST6_Msk (0x01UL << USIC_CH_PSCR_CST6_Pos) /*!< USIC_CH PSCR: CST6 Mask */
\r
1958 #define USIC_CH_PSCR_CST7_Pos 7 /*!< USIC_CH PSCR: CST7 Position */
\r
1959 #define USIC_CH_PSCR_CST7_Msk (0x01UL << USIC_CH_PSCR_CST7_Pos) /*!< USIC_CH PSCR: CST7 Mask */
\r
1960 #define USIC_CH_PSCR_CST8_Pos 8 /*!< USIC_CH PSCR: CST8 Position */
\r
1961 #define USIC_CH_PSCR_CST8_Msk (0x01UL << USIC_CH_PSCR_CST8_Pos) /*!< USIC_CH PSCR: CST8 Mask */
\r
1962 #define USIC_CH_PSCR_CST9_Pos 9 /*!< USIC_CH PSCR: CST9 Position */
\r
1963 #define USIC_CH_PSCR_CST9_Msk (0x01UL << USIC_CH_PSCR_CST9_Pos) /*!< USIC_CH PSCR: CST9 Mask */
\r
1964 #define USIC_CH_PSCR_CRSIF_Pos 10 /*!< USIC_CH PSCR: CRSIF Position */
\r
1965 #define USIC_CH_PSCR_CRSIF_Msk (0x01UL << USIC_CH_PSCR_CRSIF_Pos) /*!< USIC_CH PSCR: CRSIF Mask */
\r
1966 #define USIC_CH_PSCR_CDLIF_Pos 11 /*!< USIC_CH PSCR: CDLIF Position */
\r
1967 #define USIC_CH_PSCR_CDLIF_Msk (0x01UL << USIC_CH_PSCR_CDLIF_Pos) /*!< USIC_CH PSCR: CDLIF Mask */
\r
1968 #define USIC_CH_PSCR_CTSIF_Pos 12 /*!< USIC_CH PSCR: CTSIF Position */
\r
1969 #define USIC_CH_PSCR_CTSIF_Msk (0x01UL << USIC_CH_PSCR_CTSIF_Pos) /*!< USIC_CH PSCR: CTSIF Mask */
\r
1970 #define USIC_CH_PSCR_CTBIF_Pos 13 /*!< USIC_CH PSCR: CTBIF Position */
\r
1971 #define USIC_CH_PSCR_CTBIF_Msk (0x01UL << USIC_CH_PSCR_CTBIF_Pos) /*!< USIC_CH PSCR: CTBIF Mask */
\r
1972 #define USIC_CH_PSCR_CRIF_Pos 14 /*!< USIC_CH PSCR: CRIF Position */
\r
1973 #define USIC_CH_PSCR_CRIF_Msk (0x01UL << USIC_CH_PSCR_CRIF_Pos) /*!< USIC_CH PSCR: CRIF Mask */
\r
1974 #define USIC_CH_PSCR_CAIF_Pos 15 /*!< USIC_CH PSCR: CAIF Position */
\r
1975 #define USIC_CH_PSCR_CAIF_Msk (0x01UL << USIC_CH_PSCR_CAIF_Pos) /*!< USIC_CH PSCR: CAIF Mask */
\r
1976 #define USIC_CH_PSCR_CBRGIF_Pos 16 /*!< USIC_CH PSCR: CBRGIF Position */
\r
1977 #define USIC_CH_PSCR_CBRGIF_Msk (0x01UL << USIC_CH_PSCR_CBRGIF_Pos) /*!< USIC_CH PSCR: CBRGIF Mask */
\r
1979 /* ------------------------------- USIC_CH_RBUFSR ------------------------------- */
\r
1980 #define USIC_CH_RBUFSR_WLEN_Pos 0 /*!< USIC_CH RBUFSR: WLEN Position */
\r
1981 #define USIC_CH_RBUFSR_WLEN_Msk (0x0fUL << USIC_CH_RBUFSR_WLEN_Pos) /*!< USIC_CH RBUFSR: WLEN Mask */
\r
1982 #define USIC_CH_RBUFSR_SOF_Pos 6 /*!< USIC_CH RBUFSR: SOF Position */
\r
1983 #define USIC_CH_RBUFSR_SOF_Msk (0x01UL << USIC_CH_RBUFSR_SOF_Pos) /*!< USIC_CH RBUFSR: SOF Mask */
\r
1984 #define USIC_CH_RBUFSR_PAR_Pos 8 /*!< USIC_CH RBUFSR: PAR Position */
\r
1985 #define USIC_CH_RBUFSR_PAR_Msk (0x01UL << USIC_CH_RBUFSR_PAR_Pos) /*!< USIC_CH RBUFSR: PAR Mask */
\r
1986 #define USIC_CH_RBUFSR_PERR_Pos 9 /*!< USIC_CH RBUFSR: PERR Position */
\r
1987 #define USIC_CH_RBUFSR_PERR_Msk (0x01UL << USIC_CH_RBUFSR_PERR_Pos) /*!< USIC_CH RBUFSR: PERR Mask */
\r
1988 #define USIC_CH_RBUFSR_RDV0_Pos 13 /*!< USIC_CH RBUFSR: RDV0 Position */
\r
1989 #define USIC_CH_RBUFSR_RDV0_Msk (0x01UL << USIC_CH_RBUFSR_RDV0_Pos) /*!< USIC_CH RBUFSR: RDV0 Mask */
\r
1990 #define USIC_CH_RBUFSR_RDV1_Pos 14 /*!< USIC_CH RBUFSR: RDV1 Position */
\r
1991 #define USIC_CH_RBUFSR_RDV1_Msk (0x01UL << USIC_CH_RBUFSR_RDV1_Pos) /*!< USIC_CH RBUFSR: RDV1 Mask */
\r
1992 #define USIC_CH_RBUFSR_DS_Pos 15 /*!< USIC_CH RBUFSR: DS Position */
\r
1993 #define USIC_CH_RBUFSR_DS_Msk (0x01UL << USIC_CH_RBUFSR_DS_Pos) /*!< USIC_CH RBUFSR: DS Mask */
\r
1995 /* -------------------------------- USIC_CH_RBUF -------------------------------- */
\r
1996 #define USIC_CH_RBUF_DSR_Pos 0 /*!< USIC_CH RBUF: DSR Position */
\r
1997 #define USIC_CH_RBUF_DSR_Msk (0x0000ffffUL << USIC_CH_RBUF_DSR_Pos) /*!< USIC_CH RBUF: DSR Mask */
\r
1999 /* -------------------------------- USIC_CH_RBUFD ------------------------------- */
\r
2000 #define USIC_CH_RBUFD_DSR_Pos 0 /*!< USIC_CH RBUFD: DSR Position */
\r
2001 #define USIC_CH_RBUFD_DSR_Msk (0x0000ffffUL << USIC_CH_RBUFD_DSR_Pos) /*!< USIC_CH RBUFD: DSR Mask */
\r
2003 /* -------------------------------- USIC_CH_RBUF0 ------------------------------- */
\r
2004 #define USIC_CH_RBUF0_DSR0_Pos 0 /*!< USIC_CH RBUF0: DSR0 Position */
\r
2005 #define USIC_CH_RBUF0_DSR0_Msk (0x0000ffffUL << USIC_CH_RBUF0_DSR0_Pos) /*!< USIC_CH RBUF0: DSR0 Mask */
\r
2007 /* -------------------------------- USIC_CH_RBUF1 ------------------------------- */
\r
2008 #define USIC_CH_RBUF1_DSR1_Pos 0 /*!< USIC_CH RBUF1: DSR1 Position */
\r
2009 #define USIC_CH_RBUF1_DSR1_Msk (0x0000ffffUL << USIC_CH_RBUF1_DSR1_Pos) /*!< USIC_CH RBUF1: DSR1 Mask */
\r
2011 /* ------------------------------ USIC_CH_RBUF01SR ------------------------------ */
\r
2012 #define USIC_CH_RBUF01SR_WLEN0_Pos 0 /*!< USIC_CH RBUF01SR: WLEN0 Position */
\r
2013 #define USIC_CH_RBUF01SR_WLEN0_Msk (0x0fUL << USIC_CH_RBUF01SR_WLEN0_Pos) /*!< USIC_CH RBUF01SR: WLEN0 Mask */
\r
2014 #define USIC_CH_RBUF01SR_SOF0_Pos 6 /*!< USIC_CH RBUF01SR: SOF0 Position */
\r
2015 #define USIC_CH_RBUF01SR_SOF0_Msk (0x01UL << USIC_CH_RBUF01SR_SOF0_Pos) /*!< USIC_CH RBUF01SR: SOF0 Mask */
\r
2016 #define USIC_CH_RBUF01SR_PAR0_Pos 8 /*!< USIC_CH RBUF01SR: PAR0 Position */
\r
2017 #define USIC_CH_RBUF01SR_PAR0_Msk (0x01UL << USIC_CH_RBUF01SR_PAR0_Pos) /*!< USIC_CH RBUF01SR: PAR0 Mask */
\r
2018 #define USIC_CH_RBUF01SR_PERR0_Pos 9 /*!< USIC_CH RBUF01SR: PERR0 Position */
\r
2019 #define USIC_CH_RBUF01SR_PERR0_Msk (0x01UL << USIC_CH_RBUF01SR_PERR0_Pos) /*!< USIC_CH RBUF01SR: PERR0 Mask */
\r
2020 #define USIC_CH_RBUF01SR_RDV00_Pos 13 /*!< USIC_CH RBUF01SR: RDV00 Position */
\r
2021 #define USIC_CH_RBUF01SR_RDV00_Msk (0x01UL << USIC_CH_RBUF01SR_RDV00_Pos) /*!< USIC_CH RBUF01SR: RDV00 Mask */
\r
2022 #define USIC_CH_RBUF01SR_RDV01_Pos 14 /*!< USIC_CH RBUF01SR: RDV01 Position */
\r
2023 #define USIC_CH_RBUF01SR_RDV01_Msk (0x01UL << USIC_CH_RBUF01SR_RDV01_Pos) /*!< USIC_CH RBUF01SR: RDV01 Mask */
\r
2024 #define USIC_CH_RBUF01SR_DS0_Pos 15 /*!< USIC_CH RBUF01SR: DS0 Position */
\r
2025 #define USIC_CH_RBUF01SR_DS0_Msk (0x01UL << USIC_CH_RBUF01SR_DS0_Pos) /*!< USIC_CH RBUF01SR: DS0 Mask */
\r
2026 #define USIC_CH_RBUF01SR_WLEN1_Pos 16 /*!< USIC_CH RBUF01SR: WLEN1 Position */
\r
2027 #define USIC_CH_RBUF01SR_WLEN1_Msk (0x0fUL << USIC_CH_RBUF01SR_WLEN1_Pos) /*!< USIC_CH RBUF01SR: WLEN1 Mask */
\r
2028 #define USIC_CH_RBUF01SR_SOF1_Pos 22 /*!< USIC_CH RBUF01SR: SOF1 Position */
\r
2029 #define USIC_CH_RBUF01SR_SOF1_Msk (0x01UL << USIC_CH_RBUF01SR_SOF1_Pos) /*!< USIC_CH RBUF01SR: SOF1 Mask */
\r
2030 #define USIC_CH_RBUF01SR_PAR1_Pos 24 /*!< USIC_CH RBUF01SR: PAR1 Position */
\r
2031 #define USIC_CH_RBUF01SR_PAR1_Msk (0x01UL << USIC_CH_RBUF01SR_PAR1_Pos) /*!< USIC_CH RBUF01SR: PAR1 Mask */
\r
2032 #define USIC_CH_RBUF01SR_PERR1_Pos 25 /*!< USIC_CH RBUF01SR: PERR1 Position */
\r
2033 #define USIC_CH_RBUF01SR_PERR1_Msk (0x01UL << USIC_CH_RBUF01SR_PERR1_Pos) /*!< USIC_CH RBUF01SR: PERR1 Mask */
\r
2034 #define USIC_CH_RBUF01SR_RDV10_Pos 29 /*!< USIC_CH RBUF01SR: RDV10 Position */
\r
2035 #define USIC_CH_RBUF01SR_RDV10_Msk (0x01UL << USIC_CH_RBUF01SR_RDV10_Pos) /*!< USIC_CH RBUF01SR: RDV10 Mask */
\r
2036 #define USIC_CH_RBUF01SR_RDV11_Pos 30 /*!< USIC_CH RBUF01SR: RDV11 Position */
\r
2037 #define USIC_CH_RBUF01SR_RDV11_Msk (0x01UL << USIC_CH_RBUF01SR_RDV11_Pos) /*!< USIC_CH RBUF01SR: RDV11 Mask */
\r
2038 #define USIC_CH_RBUF01SR_DS1_Pos 31 /*!< USIC_CH RBUF01SR: DS1 Position */
\r
2039 #define USIC_CH_RBUF01SR_DS1_Msk (0x01UL << USIC_CH_RBUF01SR_DS1_Pos) /*!< USIC_CH RBUF01SR: DS1 Mask */
\r
2041 /* --------------------------------- USIC_CH_FMR -------------------------------- */
\r
2042 #define USIC_CH_FMR_MTDV_Pos 0 /*!< USIC_CH FMR: MTDV Position */
\r
2043 #define USIC_CH_FMR_MTDV_Msk (0x03UL << USIC_CH_FMR_MTDV_Pos) /*!< USIC_CH FMR: MTDV Mask */
\r
2044 #define USIC_CH_FMR_ATVC_Pos 4 /*!< USIC_CH FMR: ATVC Position */
\r
2045 #define USIC_CH_FMR_ATVC_Msk (0x01UL << USIC_CH_FMR_ATVC_Pos) /*!< USIC_CH FMR: ATVC Mask */
\r
2046 #define USIC_CH_FMR_CRDV0_Pos 14 /*!< USIC_CH FMR: CRDV0 Position */
\r
2047 #define USIC_CH_FMR_CRDV0_Msk (0x01UL << USIC_CH_FMR_CRDV0_Pos) /*!< USIC_CH FMR: CRDV0 Mask */
\r
2048 #define USIC_CH_FMR_CRDV1_Pos 15 /*!< USIC_CH FMR: CRDV1 Position */
\r
2049 #define USIC_CH_FMR_CRDV1_Msk (0x01UL << USIC_CH_FMR_CRDV1_Pos) /*!< USIC_CH FMR: CRDV1 Mask */
\r
2050 #define USIC_CH_FMR_SIO0_Pos 16 /*!< USIC_CH FMR: SIO0 Position */
\r
2051 #define USIC_CH_FMR_SIO0_Msk (0x01UL << USIC_CH_FMR_SIO0_Pos) /*!< USIC_CH FMR: SIO0 Mask */
\r
2052 #define USIC_CH_FMR_SIO1_Pos 17 /*!< USIC_CH FMR: SIO1 Position */
\r
2053 #define USIC_CH_FMR_SIO1_Msk (0x01UL << USIC_CH_FMR_SIO1_Pos) /*!< USIC_CH FMR: SIO1 Mask */
\r
2054 #define USIC_CH_FMR_SIO2_Pos 18 /*!< USIC_CH FMR: SIO2 Position */
\r
2055 #define USIC_CH_FMR_SIO2_Msk (0x01UL << USIC_CH_FMR_SIO2_Pos) /*!< USIC_CH FMR: SIO2 Mask */
\r
2056 #define USIC_CH_FMR_SIO3_Pos 19 /*!< USIC_CH FMR: SIO3 Position */
\r
2057 #define USIC_CH_FMR_SIO3_Msk (0x01UL << USIC_CH_FMR_SIO3_Pos) /*!< USIC_CH FMR: SIO3 Mask */
\r
2058 #define USIC_CH_FMR_SIO4_Pos 20 /*!< USIC_CH FMR: SIO4 Position */
\r
2059 #define USIC_CH_FMR_SIO4_Msk (0x01UL << USIC_CH_FMR_SIO4_Pos) /*!< USIC_CH FMR: SIO4 Mask */
\r
2060 #define USIC_CH_FMR_SIO5_Pos 21 /*!< USIC_CH FMR: SIO5 Position */
\r
2061 #define USIC_CH_FMR_SIO5_Msk (0x01UL << USIC_CH_FMR_SIO5_Pos) /*!< USIC_CH FMR: SIO5 Mask */
\r
2063 /* -------------------------------- USIC_CH_TBUF -------------------------------- */
\r
2064 #define USIC_CH_TBUF_TDATA_Pos 0 /*!< USIC_CH TBUF: TDATA Position */
\r
2065 #define USIC_CH_TBUF_TDATA_Msk (0x0000ffffUL << USIC_CH_TBUF_TDATA_Pos) /*!< USIC_CH TBUF: TDATA Mask */
\r
2067 /* --------------------------------- USIC_CH_BYP -------------------------------- */
\r
2068 #define USIC_CH_BYP_BDATA_Pos 0 /*!< USIC_CH BYP: BDATA Position */
\r
2069 #define USIC_CH_BYP_BDATA_Msk (0x0000ffffUL << USIC_CH_BYP_BDATA_Pos) /*!< USIC_CH BYP: BDATA Mask */
\r
2071 /* -------------------------------- USIC_CH_BYPCR ------------------------------- */
\r
2072 #define USIC_CH_BYPCR_BWLE_Pos 0 /*!< USIC_CH BYPCR: BWLE Position */
\r
2073 #define USIC_CH_BYPCR_BWLE_Msk (0x0fUL << USIC_CH_BYPCR_BWLE_Pos) /*!< USIC_CH BYPCR: BWLE Mask */
\r
2074 #define USIC_CH_BYPCR_BDSSM_Pos 8 /*!< USIC_CH BYPCR: BDSSM Position */
\r
2075 #define USIC_CH_BYPCR_BDSSM_Msk (0x01UL << USIC_CH_BYPCR_BDSSM_Pos) /*!< USIC_CH BYPCR: BDSSM Mask */
\r
2076 #define USIC_CH_BYPCR_BDEN_Pos 10 /*!< USIC_CH BYPCR: BDEN Position */
\r
2077 #define USIC_CH_BYPCR_BDEN_Msk (0x03UL << USIC_CH_BYPCR_BDEN_Pos) /*!< USIC_CH BYPCR: BDEN Mask */
\r
2078 #define USIC_CH_BYPCR_BDVTR_Pos 12 /*!< USIC_CH BYPCR: BDVTR Position */
\r
2079 #define USIC_CH_BYPCR_BDVTR_Msk (0x01UL << USIC_CH_BYPCR_BDVTR_Pos) /*!< USIC_CH BYPCR: BDVTR Mask */
\r
2080 #define USIC_CH_BYPCR_BPRIO_Pos 13 /*!< USIC_CH BYPCR: BPRIO Position */
\r
2081 #define USIC_CH_BYPCR_BPRIO_Msk (0x01UL << USIC_CH_BYPCR_BPRIO_Pos) /*!< USIC_CH BYPCR: BPRIO Mask */
\r
2082 #define USIC_CH_BYPCR_BDV_Pos 15 /*!< USIC_CH BYPCR: BDV Position */
\r
2083 #define USIC_CH_BYPCR_BDV_Msk (0x01UL << USIC_CH_BYPCR_BDV_Pos) /*!< USIC_CH BYPCR: BDV Mask */
\r
2084 #define USIC_CH_BYPCR_BSELO_Pos 16 /*!< USIC_CH BYPCR: BSELO Position */
\r
2085 #define USIC_CH_BYPCR_BSELO_Msk (0x1fUL << USIC_CH_BYPCR_BSELO_Pos) /*!< USIC_CH BYPCR: BSELO Mask */
\r
2086 #define USIC_CH_BYPCR_BHPC_Pos 21 /*!< USIC_CH BYPCR: BHPC Position */
\r
2087 #define USIC_CH_BYPCR_BHPC_Msk (0x07UL << USIC_CH_BYPCR_BHPC_Pos) /*!< USIC_CH BYPCR: BHPC Mask */
\r
2089 /* -------------------------------- USIC_CH_TBCTR ------------------------------- */
\r
2090 #define USIC_CH_TBCTR_DPTR_Pos 0 /*!< USIC_CH TBCTR: DPTR Position */
\r
2091 #define USIC_CH_TBCTR_DPTR_Msk (0x3fUL << USIC_CH_TBCTR_DPTR_Pos) /*!< USIC_CH TBCTR: DPTR Mask */
\r
2092 #define USIC_CH_TBCTR_LIMIT_Pos 8 /*!< USIC_CH TBCTR: LIMIT Position */
\r
2093 #define USIC_CH_TBCTR_LIMIT_Msk (0x3fUL << USIC_CH_TBCTR_LIMIT_Pos) /*!< USIC_CH TBCTR: LIMIT Mask */
\r
2094 #define USIC_CH_TBCTR_STBTM_Pos 14 /*!< USIC_CH TBCTR: STBTM Position */
\r
2095 #define USIC_CH_TBCTR_STBTM_Msk (0x01UL << USIC_CH_TBCTR_STBTM_Pos) /*!< USIC_CH TBCTR: STBTM Mask */
\r
2096 #define USIC_CH_TBCTR_STBTEN_Pos 15 /*!< USIC_CH TBCTR: STBTEN Position */
\r
2097 #define USIC_CH_TBCTR_STBTEN_Msk (0x01UL << USIC_CH_TBCTR_STBTEN_Pos) /*!< USIC_CH TBCTR: STBTEN Mask */
\r
2098 #define USIC_CH_TBCTR_STBINP_Pos 16 /*!< USIC_CH TBCTR: STBINP Position */
\r
2099 #define USIC_CH_TBCTR_STBINP_Msk (0x07UL << USIC_CH_TBCTR_STBINP_Pos) /*!< USIC_CH TBCTR: STBINP Mask */
\r
2100 #define USIC_CH_TBCTR_ATBINP_Pos 19 /*!< USIC_CH TBCTR: ATBINP Position */
\r
2101 #define USIC_CH_TBCTR_ATBINP_Msk (0x07UL << USIC_CH_TBCTR_ATBINP_Pos) /*!< USIC_CH TBCTR: ATBINP Mask */
\r
2102 #define USIC_CH_TBCTR_SIZE_Pos 24 /*!< USIC_CH TBCTR: SIZE Position */
\r
2103 #define USIC_CH_TBCTR_SIZE_Msk (0x07UL << USIC_CH_TBCTR_SIZE_Pos) /*!< USIC_CH TBCTR: SIZE Mask */
\r
2104 #define USIC_CH_TBCTR_LOF_Pos 28 /*!< USIC_CH TBCTR: LOF Position */
\r
2105 #define USIC_CH_TBCTR_LOF_Msk (0x01UL << USIC_CH_TBCTR_LOF_Pos) /*!< USIC_CH TBCTR: LOF Mask */
\r
2106 #define USIC_CH_TBCTR_STBIEN_Pos 30 /*!< USIC_CH TBCTR: STBIEN Position */
\r
2107 #define USIC_CH_TBCTR_STBIEN_Msk (0x01UL << USIC_CH_TBCTR_STBIEN_Pos) /*!< USIC_CH TBCTR: STBIEN Mask */
\r
2108 #define USIC_CH_TBCTR_TBERIEN_Pos 31 /*!< USIC_CH TBCTR: TBERIEN Position */
\r
2109 #define USIC_CH_TBCTR_TBERIEN_Msk (0x01UL << USIC_CH_TBCTR_TBERIEN_Pos) /*!< USIC_CH TBCTR: TBERIEN Mask */
\r
2111 /* -------------------------------- USIC_CH_RBCTR ------------------------------- */
\r
2112 #define USIC_CH_RBCTR_DPTR_Pos 0 /*!< USIC_CH RBCTR: DPTR Position */
\r
2113 #define USIC_CH_RBCTR_DPTR_Msk (0x3fUL << USIC_CH_RBCTR_DPTR_Pos) /*!< USIC_CH RBCTR: DPTR Mask */
\r
2114 #define USIC_CH_RBCTR_LIMIT_Pos 8 /*!< USIC_CH RBCTR: LIMIT Position */
\r
2115 #define USIC_CH_RBCTR_LIMIT_Msk (0x3fUL << USIC_CH_RBCTR_LIMIT_Pos) /*!< USIC_CH RBCTR: LIMIT Mask */
\r
2116 #define USIC_CH_RBCTR_SRBTM_Pos 14 /*!< USIC_CH RBCTR: SRBTM Position */
\r
2117 #define USIC_CH_RBCTR_SRBTM_Msk (0x01UL << USIC_CH_RBCTR_SRBTM_Pos) /*!< USIC_CH RBCTR: SRBTM Mask */
\r
2118 #define USIC_CH_RBCTR_SRBTEN_Pos 15 /*!< USIC_CH RBCTR: SRBTEN Position */
\r
2119 #define USIC_CH_RBCTR_SRBTEN_Msk (0x01UL << USIC_CH_RBCTR_SRBTEN_Pos) /*!< USIC_CH RBCTR: SRBTEN Mask */
\r
2120 #define USIC_CH_RBCTR_SRBINP_Pos 16 /*!< USIC_CH RBCTR: SRBINP Position */
\r
2121 #define USIC_CH_RBCTR_SRBINP_Msk (0x07UL << USIC_CH_RBCTR_SRBINP_Pos) /*!< USIC_CH RBCTR: SRBINP Mask */
\r
2122 #define USIC_CH_RBCTR_ARBINP_Pos 19 /*!< USIC_CH RBCTR: ARBINP Position */
\r
2123 #define USIC_CH_RBCTR_ARBINP_Msk (0x07UL << USIC_CH_RBCTR_ARBINP_Pos) /*!< USIC_CH RBCTR: ARBINP Mask */
\r
2124 #define USIC_CH_RBCTR_RCIM_Pos 22 /*!< USIC_CH RBCTR: RCIM Position */
\r
2125 #define USIC_CH_RBCTR_RCIM_Msk (0x03UL << USIC_CH_RBCTR_RCIM_Pos) /*!< USIC_CH RBCTR: RCIM Mask */
\r
2126 #define USIC_CH_RBCTR_SIZE_Pos 24 /*!< USIC_CH RBCTR: SIZE Position */
\r
2127 #define USIC_CH_RBCTR_SIZE_Msk (0x07UL << USIC_CH_RBCTR_SIZE_Pos) /*!< USIC_CH RBCTR: SIZE Mask */
\r
2128 #define USIC_CH_RBCTR_RNM_Pos 27 /*!< USIC_CH RBCTR: RNM Position */
\r
2129 #define USIC_CH_RBCTR_RNM_Msk (0x01UL << USIC_CH_RBCTR_RNM_Pos) /*!< USIC_CH RBCTR: RNM Mask */
\r
2130 #define USIC_CH_RBCTR_LOF_Pos 28 /*!< USIC_CH RBCTR: LOF Position */
\r
2131 #define USIC_CH_RBCTR_LOF_Msk (0x01UL << USIC_CH_RBCTR_LOF_Pos) /*!< USIC_CH RBCTR: LOF Mask */
\r
2132 #define USIC_CH_RBCTR_ARBIEN_Pos 29 /*!< USIC_CH RBCTR: ARBIEN Position */
\r
2133 #define USIC_CH_RBCTR_ARBIEN_Msk (0x01UL << USIC_CH_RBCTR_ARBIEN_Pos) /*!< USIC_CH RBCTR: ARBIEN Mask */
\r
2134 #define USIC_CH_RBCTR_SRBIEN_Pos 30 /*!< USIC_CH RBCTR: SRBIEN Position */
\r
2135 #define USIC_CH_RBCTR_SRBIEN_Msk (0x01UL << USIC_CH_RBCTR_SRBIEN_Pos) /*!< USIC_CH RBCTR: SRBIEN Mask */
\r
2136 #define USIC_CH_RBCTR_RBERIEN_Pos 31 /*!< USIC_CH RBCTR: RBERIEN Position */
\r
2137 #define USIC_CH_RBCTR_RBERIEN_Msk (0x01UL << USIC_CH_RBCTR_RBERIEN_Pos) /*!< USIC_CH RBCTR: RBERIEN Mask */
\r
2139 /* ------------------------------- USIC_CH_TRBPTR ------------------------------- */
\r
2140 #define USIC_CH_TRBPTR_TDIPTR_Pos 0 /*!< USIC_CH TRBPTR: TDIPTR Position */
\r
2141 #define USIC_CH_TRBPTR_TDIPTR_Msk (0x3fUL << USIC_CH_TRBPTR_TDIPTR_Pos) /*!< USIC_CH TRBPTR: TDIPTR Mask */
\r
2142 #define USIC_CH_TRBPTR_TDOPTR_Pos 8 /*!< USIC_CH TRBPTR: TDOPTR Position */
\r
2143 #define USIC_CH_TRBPTR_TDOPTR_Msk (0x3fUL << USIC_CH_TRBPTR_TDOPTR_Pos) /*!< USIC_CH TRBPTR: TDOPTR Mask */
\r
2144 #define USIC_CH_TRBPTR_RDIPTR_Pos 16 /*!< USIC_CH TRBPTR: RDIPTR Position */
\r
2145 #define USIC_CH_TRBPTR_RDIPTR_Msk (0x3fUL << USIC_CH_TRBPTR_RDIPTR_Pos) /*!< USIC_CH TRBPTR: RDIPTR Mask */
\r
2146 #define USIC_CH_TRBPTR_RDOPTR_Pos 24 /*!< USIC_CH TRBPTR: RDOPTR Position */
\r
2147 #define USIC_CH_TRBPTR_RDOPTR_Msk (0x3fUL << USIC_CH_TRBPTR_RDOPTR_Pos) /*!< USIC_CH TRBPTR: RDOPTR Mask */
\r
2149 /* -------------------------------- USIC_CH_TRBSR ------------------------------- */
\r
2150 #define USIC_CH_TRBSR_SRBI_Pos 0 /*!< USIC_CH TRBSR: SRBI Position */
\r
2151 #define USIC_CH_TRBSR_SRBI_Msk (0x01UL << USIC_CH_TRBSR_SRBI_Pos) /*!< USIC_CH TRBSR: SRBI Mask */
\r
2152 #define USIC_CH_TRBSR_RBERI_Pos 1 /*!< USIC_CH TRBSR: RBERI Position */
\r
2153 #define USIC_CH_TRBSR_RBERI_Msk (0x01UL << USIC_CH_TRBSR_RBERI_Pos) /*!< USIC_CH TRBSR: RBERI Mask */
\r
2154 #define USIC_CH_TRBSR_ARBI_Pos 2 /*!< USIC_CH TRBSR: ARBI Position */
\r
2155 #define USIC_CH_TRBSR_ARBI_Msk (0x01UL << USIC_CH_TRBSR_ARBI_Pos) /*!< USIC_CH TRBSR: ARBI Mask */
\r
2156 #define USIC_CH_TRBSR_REMPTY_Pos 3 /*!< USIC_CH TRBSR: REMPTY Position */
\r
2157 #define USIC_CH_TRBSR_REMPTY_Msk (0x01UL << USIC_CH_TRBSR_REMPTY_Pos) /*!< USIC_CH TRBSR: REMPTY Mask */
\r
2158 #define USIC_CH_TRBSR_RFULL_Pos 4 /*!< USIC_CH TRBSR: RFULL Position */
\r
2159 #define USIC_CH_TRBSR_RFULL_Msk (0x01UL << USIC_CH_TRBSR_RFULL_Pos) /*!< USIC_CH TRBSR: RFULL Mask */
\r
2160 #define USIC_CH_TRBSR_RBUS_Pos 5 /*!< USIC_CH TRBSR: RBUS Position */
\r
2161 #define USIC_CH_TRBSR_RBUS_Msk (0x01UL << USIC_CH_TRBSR_RBUS_Pos) /*!< USIC_CH TRBSR: RBUS Mask */
\r
2162 #define USIC_CH_TRBSR_SRBT_Pos 6 /*!< USIC_CH TRBSR: SRBT Position */
\r
2163 #define USIC_CH_TRBSR_SRBT_Msk (0x01UL << USIC_CH_TRBSR_SRBT_Pos) /*!< USIC_CH TRBSR: SRBT Mask */
\r
2164 #define USIC_CH_TRBSR_STBI_Pos 8 /*!< USIC_CH TRBSR: STBI Position */
\r
2165 #define USIC_CH_TRBSR_STBI_Msk (0x01UL << USIC_CH_TRBSR_STBI_Pos) /*!< USIC_CH TRBSR: STBI Mask */
\r
2166 #define USIC_CH_TRBSR_TBERI_Pos 9 /*!< USIC_CH TRBSR: TBERI Position */
\r
2167 #define USIC_CH_TRBSR_TBERI_Msk (0x01UL << USIC_CH_TRBSR_TBERI_Pos) /*!< USIC_CH TRBSR: TBERI Mask */
\r
2168 #define USIC_CH_TRBSR_TEMPTY_Pos 11 /*!< USIC_CH TRBSR: TEMPTY Position */
\r
2169 #define USIC_CH_TRBSR_TEMPTY_Msk (0x01UL << USIC_CH_TRBSR_TEMPTY_Pos) /*!< USIC_CH TRBSR: TEMPTY Mask */
\r
2170 #define USIC_CH_TRBSR_TFULL_Pos 12 /*!< USIC_CH TRBSR: TFULL Position */
\r
2171 #define USIC_CH_TRBSR_TFULL_Msk (0x01UL << USIC_CH_TRBSR_TFULL_Pos) /*!< USIC_CH TRBSR: TFULL Mask */
\r
2172 #define USIC_CH_TRBSR_TBUS_Pos 13 /*!< USIC_CH TRBSR: TBUS Position */
\r
2173 #define USIC_CH_TRBSR_TBUS_Msk (0x01UL << USIC_CH_TRBSR_TBUS_Pos) /*!< USIC_CH TRBSR: TBUS Mask */
\r
2174 #define USIC_CH_TRBSR_STBT_Pos 14 /*!< USIC_CH TRBSR: STBT Position */
\r
2175 #define USIC_CH_TRBSR_STBT_Msk (0x01UL << USIC_CH_TRBSR_STBT_Pos) /*!< USIC_CH TRBSR: STBT Mask */
\r
2176 #define USIC_CH_TRBSR_RBFLVL_Pos 16 /*!< USIC_CH TRBSR: RBFLVL Position */
\r
2177 #define USIC_CH_TRBSR_RBFLVL_Msk (0x7fUL << USIC_CH_TRBSR_RBFLVL_Pos) /*!< USIC_CH TRBSR: RBFLVL Mask */
\r
2178 #define USIC_CH_TRBSR_TBFLVL_Pos 24 /*!< USIC_CH TRBSR: TBFLVL Position */
\r
2179 #define USIC_CH_TRBSR_TBFLVL_Msk (0x7fUL << USIC_CH_TRBSR_TBFLVL_Pos) /*!< USIC_CH TRBSR: TBFLVL Mask */
\r
2181 /* ------------------------------- USIC_CH_TRBSCR ------------------------------- */
\r
2182 #define USIC_CH_TRBSCR_CSRBI_Pos 0 /*!< USIC_CH TRBSCR: CSRBI Position */
\r
2183 #define USIC_CH_TRBSCR_CSRBI_Msk (0x01UL << USIC_CH_TRBSCR_CSRBI_Pos) /*!< USIC_CH TRBSCR: CSRBI Mask */
\r
2184 #define USIC_CH_TRBSCR_CRBERI_Pos 1 /*!< USIC_CH TRBSCR: CRBERI Position */
\r
2185 #define USIC_CH_TRBSCR_CRBERI_Msk (0x01UL << USIC_CH_TRBSCR_CRBERI_Pos) /*!< USIC_CH TRBSCR: CRBERI Mask */
\r
2186 #define USIC_CH_TRBSCR_CARBI_Pos 2 /*!< USIC_CH TRBSCR: CARBI Position */
\r
2187 #define USIC_CH_TRBSCR_CARBI_Msk (0x01UL << USIC_CH_TRBSCR_CARBI_Pos) /*!< USIC_CH TRBSCR: CARBI Mask */
\r
2188 #define USIC_CH_TRBSCR_CSTBI_Pos 8 /*!< USIC_CH TRBSCR: CSTBI Position */
\r
2189 #define USIC_CH_TRBSCR_CSTBI_Msk (0x01UL << USIC_CH_TRBSCR_CSTBI_Pos) /*!< USIC_CH TRBSCR: CSTBI Mask */
\r
2190 #define USIC_CH_TRBSCR_CTBERI_Pos 9 /*!< USIC_CH TRBSCR: CTBERI Position */
\r
2191 #define USIC_CH_TRBSCR_CTBERI_Msk (0x01UL << USIC_CH_TRBSCR_CTBERI_Pos) /*!< USIC_CH TRBSCR: CTBERI Mask */
\r
2192 #define USIC_CH_TRBSCR_CBDV_Pos 10 /*!< USIC_CH TRBSCR: CBDV Position */
\r
2193 #define USIC_CH_TRBSCR_CBDV_Msk (0x01UL << USIC_CH_TRBSCR_CBDV_Pos) /*!< USIC_CH TRBSCR: CBDV Mask */
\r
2194 #define USIC_CH_TRBSCR_FLUSHRB_Pos 14 /*!< USIC_CH TRBSCR: FLUSHRB Position */
\r
2195 #define USIC_CH_TRBSCR_FLUSHRB_Msk (0x01UL << USIC_CH_TRBSCR_FLUSHRB_Pos) /*!< USIC_CH TRBSCR: FLUSHRB Mask */
\r
2196 #define USIC_CH_TRBSCR_FLUSHTB_Pos 15 /*!< USIC_CH TRBSCR: FLUSHTB Position */
\r
2197 #define USIC_CH_TRBSCR_FLUSHTB_Msk (0x01UL << USIC_CH_TRBSCR_FLUSHTB_Pos) /*!< USIC_CH TRBSCR: FLUSHTB Mask */
\r
2199 /* -------------------------------- USIC_CH_OUTR -------------------------------- */
\r
2200 #define USIC_CH_OUTR_DSR_Pos 0 /*!< USIC_CH OUTR: DSR Position */
\r
2201 #define USIC_CH_OUTR_DSR_Msk (0x0000ffffUL << USIC_CH_OUTR_DSR_Pos) /*!< USIC_CH OUTR: DSR Mask */
\r
2202 #define USIC_CH_OUTR_RCI_Pos 16 /*!< USIC_CH OUTR: RCI Position */
\r
2203 #define USIC_CH_OUTR_RCI_Msk (0x1fUL << USIC_CH_OUTR_RCI_Pos) /*!< USIC_CH OUTR: RCI Mask */
\r
2205 /* -------------------------------- USIC_CH_OUTDR ------------------------------- */
\r
2206 #define USIC_CH_OUTDR_DSR_Pos 0 /*!< USIC_CH OUTDR: DSR Position */
\r
2207 #define USIC_CH_OUTDR_DSR_Msk (0x0000ffffUL << USIC_CH_OUTDR_DSR_Pos) /*!< USIC_CH OUTDR: DSR Mask */
\r
2208 #define USIC_CH_OUTDR_RCI_Pos 16 /*!< USIC_CH OUTDR: RCI Position */
\r
2209 #define USIC_CH_OUTDR_RCI_Msk (0x1fUL << USIC_CH_OUTDR_RCI_Pos) /*!< USIC_CH OUTDR: RCI Mask */
\r
2211 /* --------------------------------- USIC_CH_IN --------------------------------- */
\r
2212 #define USIC_CH_IN_TDATA_Pos 0 /*!< USIC_CH IN: TDATA Position */
\r
2213 #define USIC_CH_IN_TDATA_Msk (0x0000ffffUL << USIC_CH_IN_TDATA_Pos) /*!< USIC_CH IN: TDATA Mask */
\r
2216 /* ================================================================================ */
\r
2217 /* ================ struct 'SCU_GENERAL' Position & Mask ================ */
\r
2218 /* ================================================================================ */
\r
2221 /* ---------------------------- SCU_GENERAL_DBGROMID ---------------------------- */
\r
2222 #define SCU_GENERAL_DBGROMID_MANUFID_Pos 1 /*!< SCU_GENERAL DBGROMID: MANUFID Position */
\r
2223 #define SCU_GENERAL_DBGROMID_MANUFID_Msk (0x000007ffUL << SCU_GENERAL_DBGROMID_MANUFID_Pos) /*!< SCU_GENERAL DBGROMID: MANUFID Mask */
\r
2224 #define SCU_GENERAL_DBGROMID_PARTNO_Pos 12 /*!< SCU_GENERAL DBGROMID: PARTNO Position */
\r
2225 #define SCU_GENERAL_DBGROMID_PARTNO_Msk (0x0000ffffUL << SCU_GENERAL_DBGROMID_PARTNO_Pos) /*!< SCU_GENERAL DBGROMID: PARTNO Mask */
\r
2226 #define SCU_GENERAL_DBGROMID_VERSION_Pos 28 /*!< SCU_GENERAL DBGROMID: VERSION Position */
\r
2227 #define SCU_GENERAL_DBGROMID_VERSION_Msk (0x0fUL << SCU_GENERAL_DBGROMID_VERSION_Pos) /*!< SCU_GENERAL DBGROMID: VERSION Mask */
\r
2229 /* ----------------------------- SCU_GENERAL_IDCHIP ----------------------------- */
\r
2230 #define SCU_GENERAL_IDCHIP_IDCHIP_Pos 0 /*!< SCU_GENERAL IDCHIP: IDCHIP Position */
\r
2231 #define SCU_GENERAL_IDCHIP_IDCHIP_Msk (0xffffffffUL << SCU_GENERAL_IDCHIP_IDCHIP_Pos) /*!< SCU_GENERAL IDCHIP: IDCHIP Mask */
\r
2233 /* ------------------------------- SCU_GENERAL_ID ------------------------------- */
\r
2234 #define SCU_GENERAL_ID_MOD_REV_Pos 0 /*!< SCU_GENERAL ID: MOD_REV Position */
\r
2235 #define SCU_GENERAL_ID_MOD_REV_Msk (0x000000ffUL << SCU_GENERAL_ID_MOD_REV_Pos) /*!< SCU_GENERAL ID: MOD_REV Mask */
\r
2236 #define SCU_GENERAL_ID_MOD_TYPE_Pos 8 /*!< SCU_GENERAL ID: MOD_TYPE Position */
\r
2237 #define SCU_GENERAL_ID_MOD_TYPE_Msk (0x000000ffUL << SCU_GENERAL_ID_MOD_TYPE_Pos) /*!< SCU_GENERAL ID: MOD_TYPE Mask */
\r
2238 #define SCU_GENERAL_ID_MOD_NUMBER_Pos 16 /*!< SCU_GENERAL ID: MOD_NUMBER Position */
\r
2239 #define SCU_GENERAL_ID_MOD_NUMBER_Msk (0x0000ffffUL << SCU_GENERAL_ID_MOD_NUMBER_Pos) /*!< SCU_GENERAL ID: MOD_NUMBER Mask */
\r
2241 /* ------------------------------ SCU_GENERAL_SSW0 ------------------------------ */
\r
2242 #define SCU_GENERAL_SSW0_DAT_Pos 0 /*!< SCU_GENERAL SSW0: DAT Position */
\r
2243 #define SCU_GENERAL_SSW0_DAT_Msk (0xffffffffUL << SCU_GENERAL_SSW0_DAT_Pos) /*!< SCU_GENERAL SSW0: DAT Mask */
\r
2245 /* ----------------------------- SCU_GENERAL_PASSWD ----------------------------- */
\r
2246 #define SCU_GENERAL_PASSWD_MODE_Pos 0 /*!< SCU_GENERAL PASSWD: MODE Position */
\r
2247 #define SCU_GENERAL_PASSWD_MODE_Msk (0x03UL << SCU_GENERAL_PASSWD_MODE_Pos) /*!< SCU_GENERAL PASSWD: MODE Mask */
\r
2248 #define SCU_GENERAL_PASSWD_PROTS_Pos 2 /*!< SCU_GENERAL PASSWD: PROTS Position */
\r
2249 #define SCU_GENERAL_PASSWD_PROTS_Msk (0x01UL << SCU_GENERAL_PASSWD_PROTS_Pos) /*!< SCU_GENERAL PASSWD: PROTS Mask */
\r
2250 #define SCU_GENERAL_PASSWD_PASS_Pos 3 /*!< SCU_GENERAL PASSWD: PASS Position */
\r
2251 #define SCU_GENERAL_PASSWD_PASS_Msk (0x1fUL << SCU_GENERAL_PASSWD_PASS_Pos) /*!< SCU_GENERAL PASSWD: PASS Mask */
\r
2253 /* ----------------------------- SCU_GENERAL_CCUCON ----------------------------- */
\r
2254 #define SCU_GENERAL_CCUCON_GSC40_Pos 0 /*!< SCU_GENERAL CCUCON: GSC40 Position */
\r
2255 #define SCU_GENERAL_CCUCON_GSC40_Msk (0x01UL << SCU_GENERAL_CCUCON_GSC40_Pos) /*!< SCU_GENERAL CCUCON: GSC40 Mask */
\r
2257 /* ----------------------------- SCU_GENERAL_MIRRSTS ---------------------------- */
\r
2258 #define SCU_GENERAL_MIRRSTS_RTC_CTR_Pos 0 /*!< SCU_GENERAL MIRRSTS: RTC_CTR Position */
\r
2259 #define SCU_GENERAL_MIRRSTS_RTC_CTR_Msk (0x01UL << SCU_GENERAL_MIRRSTS_RTC_CTR_Pos) /*!< SCU_GENERAL MIRRSTS: RTC_CTR Mask */
\r
2260 #define SCU_GENERAL_MIRRSTS_RTC_ATIM0_Pos 1 /*!< SCU_GENERAL MIRRSTS: RTC_ATIM0 Position */
\r
2261 #define SCU_GENERAL_MIRRSTS_RTC_ATIM0_Msk (0x01UL << SCU_GENERAL_MIRRSTS_RTC_ATIM0_Pos) /*!< SCU_GENERAL MIRRSTS: RTC_ATIM0 Mask */
\r
2262 #define SCU_GENERAL_MIRRSTS_RTC_ATIM1_Pos 2 /*!< SCU_GENERAL MIRRSTS: RTC_ATIM1 Position */
\r
2263 #define SCU_GENERAL_MIRRSTS_RTC_ATIM1_Msk (0x01UL << SCU_GENERAL_MIRRSTS_RTC_ATIM1_Pos) /*!< SCU_GENERAL MIRRSTS: RTC_ATIM1 Mask */
\r
2264 #define SCU_GENERAL_MIRRSTS_RTC_TIM0_Pos 3 /*!< SCU_GENERAL MIRRSTS: RTC_TIM0 Position */
\r
2265 #define SCU_GENERAL_MIRRSTS_RTC_TIM0_Msk (0x01UL << SCU_GENERAL_MIRRSTS_RTC_TIM0_Pos) /*!< SCU_GENERAL MIRRSTS: RTC_TIM0 Mask */
\r
2266 #define SCU_GENERAL_MIRRSTS_RTC_TIM1_Pos 4 /*!< SCU_GENERAL MIRRSTS: RTC_TIM1 Position */
\r
2267 #define SCU_GENERAL_MIRRSTS_RTC_TIM1_Msk (0x01UL << SCU_GENERAL_MIRRSTS_RTC_TIM1_Pos) /*!< SCU_GENERAL MIRRSTS: RTC_TIM1 Mask */
\r
2269 /* ------------------------------ SCU_GENERAL_PMTSR ----------------------------- */
\r
2270 #define SCU_GENERAL_PMTSR_MTENS_Pos 0 /*!< SCU_GENERAL PMTSR: MTENS Position */
\r
2271 #define SCU_GENERAL_PMTSR_MTENS_Msk (0x01UL << SCU_GENERAL_PMTSR_MTENS_Pos) /*!< SCU_GENERAL PMTSR: MTENS Mask */
\r
2274 /* ================================================================================ */
\r
2275 /* ================ struct 'SCU_INTERRUPT' Position & Mask ================ */
\r
2276 /* ================================================================================ */
\r
2279 /* ----------------------------- SCU_INTERRUPT_SRRAW ---------------------------- */
\r
2280 #define SCU_INTERRUPT_SRRAW_PRWARN_Pos 0 /*!< SCU_INTERRUPT SRRAW: PRWARN Position */
\r
2281 #define SCU_INTERRUPT_SRRAW_PRWARN_Msk (0x01UL << SCU_INTERRUPT_SRRAW_PRWARN_Pos) /*!< SCU_INTERRUPT SRRAW: PRWARN Mask */
\r
2282 #define SCU_INTERRUPT_SRRAW_PI_Pos 1 /*!< SCU_INTERRUPT SRRAW: PI Position */
\r
2283 #define SCU_INTERRUPT_SRRAW_PI_Msk (0x01UL << SCU_INTERRUPT_SRRAW_PI_Pos) /*!< SCU_INTERRUPT SRRAW: PI Mask */
\r
2284 #define SCU_INTERRUPT_SRRAW_AI_Pos 2 /*!< SCU_INTERRUPT SRRAW: AI Position */
\r
2285 #define SCU_INTERRUPT_SRRAW_AI_Msk (0x01UL << SCU_INTERRUPT_SRRAW_AI_Pos) /*!< SCU_INTERRUPT SRRAW: AI Mask */
\r
2286 #define SCU_INTERRUPT_SRRAW_VDDPI_Pos 3 /*!< SCU_INTERRUPT SRRAW: VDDPI Position */
\r
2287 #define SCU_INTERRUPT_SRRAW_VDDPI_Msk (0x01UL << SCU_INTERRUPT_SRRAW_VDDPI_Pos) /*!< SCU_INTERRUPT SRRAW: VDDPI Mask */
\r
2288 #define SCU_INTERRUPT_SRRAW_ACMP0I_Pos 4 /*!< SCU_INTERRUPT SRRAW: ACMP0I Position */
\r
2289 #define SCU_INTERRUPT_SRRAW_ACMP0I_Msk (0x01UL << SCU_INTERRUPT_SRRAW_ACMP0I_Pos) /*!< SCU_INTERRUPT SRRAW: ACMP0I Mask */
\r
2290 #define SCU_INTERRUPT_SRRAW_ACMP1I_Pos 5 /*!< SCU_INTERRUPT SRRAW: ACMP1I Position */
\r
2291 #define SCU_INTERRUPT_SRRAW_ACMP1I_Msk (0x01UL << SCU_INTERRUPT_SRRAW_ACMP1I_Pos) /*!< SCU_INTERRUPT SRRAW: ACMP1I Mask */
\r
2292 #define SCU_INTERRUPT_SRRAW_ACMP2I_Pos 6 /*!< SCU_INTERRUPT SRRAW: ACMP2I Position */
\r
2293 #define SCU_INTERRUPT_SRRAW_ACMP2I_Msk (0x01UL << SCU_INTERRUPT_SRRAW_ACMP2I_Pos) /*!< SCU_INTERRUPT SRRAW: ACMP2I Mask */
\r
2294 #define SCU_INTERRUPT_SRRAW_VDROPI_Pos 7 /*!< SCU_INTERRUPT SRRAW: VDROPI Position */
\r
2295 #define SCU_INTERRUPT_SRRAW_VDROPI_Msk (0x01UL << SCU_INTERRUPT_SRRAW_VDROPI_Pos) /*!< SCU_INTERRUPT SRRAW: VDROPI Mask */
\r
2296 #define SCU_INTERRUPT_SRRAW_ORC0I_Pos 8 /*!< SCU_INTERRUPT SRRAW: ORC0I Position */
\r
2297 #define SCU_INTERRUPT_SRRAW_ORC0I_Msk (0x01UL << SCU_INTERRUPT_SRRAW_ORC0I_Pos) /*!< SCU_INTERRUPT SRRAW: ORC0I Mask */
\r
2298 #define SCU_INTERRUPT_SRRAW_ORC1I_Pos 9 /*!< SCU_INTERRUPT SRRAW: ORC1I Position */
\r
2299 #define SCU_INTERRUPT_SRRAW_ORC1I_Msk (0x01UL << SCU_INTERRUPT_SRRAW_ORC1I_Pos) /*!< SCU_INTERRUPT SRRAW: ORC1I Mask */
\r
2300 #define SCU_INTERRUPT_SRRAW_ORC2I_Pos 10 /*!< SCU_INTERRUPT SRRAW: ORC2I Position */
\r
2301 #define SCU_INTERRUPT_SRRAW_ORC2I_Msk (0x01UL << SCU_INTERRUPT_SRRAW_ORC2I_Pos) /*!< SCU_INTERRUPT SRRAW: ORC2I Mask */
\r
2302 #define SCU_INTERRUPT_SRRAW_ORC3I_Pos 11 /*!< SCU_INTERRUPT SRRAW: ORC3I Position */
\r
2303 #define SCU_INTERRUPT_SRRAW_ORC3I_Msk (0x01UL << SCU_INTERRUPT_SRRAW_ORC3I_Pos) /*!< SCU_INTERRUPT SRRAW: ORC3I Mask */
\r
2304 #define SCU_INTERRUPT_SRRAW_ORC4I_Pos 12 /*!< SCU_INTERRUPT SRRAW: ORC4I Position */
\r
2305 #define SCU_INTERRUPT_SRRAW_ORC4I_Msk (0x01UL << SCU_INTERRUPT_SRRAW_ORC4I_Pos) /*!< SCU_INTERRUPT SRRAW: ORC4I Mask */
\r
2306 #define SCU_INTERRUPT_SRRAW_ORC5I_Pos 13 /*!< SCU_INTERRUPT SRRAW: ORC5I Position */
\r
2307 #define SCU_INTERRUPT_SRRAW_ORC5I_Msk (0x01UL << SCU_INTERRUPT_SRRAW_ORC5I_Pos) /*!< SCU_INTERRUPT SRRAW: ORC5I Mask */
\r
2308 #define SCU_INTERRUPT_SRRAW_ORC6I_Pos 14 /*!< SCU_INTERRUPT SRRAW: ORC6I Position */
\r
2309 #define SCU_INTERRUPT_SRRAW_ORC6I_Msk (0x01UL << SCU_INTERRUPT_SRRAW_ORC6I_Pos) /*!< SCU_INTERRUPT SRRAW: ORC6I Mask */
\r
2310 #define SCU_INTERRUPT_SRRAW_ORC7I_Pos 15 /*!< SCU_INTERRUPT SRRAW: ORC7I Position */
\r
2311 #define SCU_INTERRUPT_SRRAW_ORC7I_Msk (0x01UL << SCU_INTERRUPT_SRRAW_ORC7I_Pos) /*!< SCU_INTERRUPT SRRAW: ORC7I Mask */
\r
2312 #define SCU_INTERRUPT_SRRAW_LOCI_Pos 16 /*!< SCU_INTERRUPT SRRAW: LOCI Position */
\r
2313 #define SCU_INTERRUPT_SRRAW_LOCI_Msk (0x01UL << SCU_INTERRUPT_SRRAW_LOCI_Pos) /*!< SCU_INTERRUPT SRRAW: LOCI Mask */
\r
2314 #define SCU_INTERRUPT_SRRAW_PESRAMI_Pos 17 /*!< SCU_INTERRUPT SRRAW: PESRAMI Position */
\r
2315 #define SCU_INTERRUPT_SRRAW_PESRAMI_Msk (0x01UL << SCU_INTERRUPT_SRRAW_PESRAMI_Pos) /*!< SCU_INTERRUPT SRRAW: PESRAMI Mask */
\r
2316 #define SCU_INTERRUPT_SRRAW_PEU0I_Pos 18 /*!< SCU_INTERRUPT SRRAW: PEU0I Position */
\r
2317 #define SCU_INTERRUPT_SRRAW_PEU0I_Msk (0x01UL << SCU_INTERRUPT_SRRAW_PEU0I_Pos) /*!< SCU_INTERRUPT SRRAW: PEU0I Mask */
\r
2318 #define SCU_INTERRUPT_SRRAW_FLECC2I_Pos 19 /*!< SCU_INTERRUPT SRRAW: FLECC2I Position */
\r
2319 #define SCU_INTERRUPT_SRRAW_FLECC2I_Msk (0x01UL << SCU_INTERRUPT_SRRAW_FLECC2I_Pos) /*!< SCU_INTERRUPT SRRAW: FLECC2I Mask */
\r
2320 #define SCU_INTERRUPT_SRRAW_FLCMPLTI_Pos 20 /*!< SCU_INTERRUPT SRRAW: FLCMPLTI Position */
\r
2321 #define SCU_INTERRUPT_SRRAW_FLCMPLTI_Msk (0x01UL << SCU_INTERRUPT_SRRAW_FLCMPLTI_Pos) /*!< SCU_INTERRUPT SRRAW: FLCMPLTI Mask */
\r
2322 #define SCU_INTERRUPT_SRRAW_VCLIPI_Pos 21 /*!< SCU_INTERRUPT SRRAW: VCLIPI Position */
\r
2323 #define SCU_INTERRUPT_SRRAW_VCLIPI_Msk (0x01UL << SCU_INTERRUPT_SRRAW_VCLIPI_Pos) /*!< SCU_INTERRUPT SRRAW: VCLIPI Mask */
\r
2324 #define SCU_INTERRUPT_SRRAW_SBYCLKFI_Pos 22 /*!< SCU_INTERRUPT SRRAW: SBYCLKFI Position */
\r
2325 #define SCU_INTERRUPT_SRRAW_SBYCLKFI_Msk (0x01UL << SCU_INTERRUPT_SRRAW_SBYCLKFI_Pos) /*!< SCU_INTERRUPT SRRAW: SBYCLKFI Mask */
\r
2326 #define SCU_INTERRUPT_SRRAW_RTC_CTR_Pos 24 /*!< SCU_INTERRUPT SRRAW: RTC_CTR Position */
\r
2327 #define SCU_INTERRUPT_SRRAW_RTC_CTR_Msk (0x01UL << SCU_INTERRUPT_SRRAW_RTC_CTR_Pos) /*!< SCU_INTERRUPT SRRAW: RTC_CTR Mask */
\r
2328 #define SCU_INTERRUPT_SRRAW_RTC_ATIM0_Pos 25 /*!< SCU_INTERRUPT SRRAW: RTC_ATIM0 Position */
\r
2329 #define SCU_INTERRUPT_SRRAW_RTC_ATIM0_Msk (0x01UL << SCU_INTERRUPT_SRRAW_RTC_ATIM0_Pos) /*!< SCU_INTERRUPT SRRAW: RTC_ATIM0 Mask */
\r
2330 #define SCU_INTERRUPT_SRRAW_RTC_ATIM1_Pos 26 /*!< SCU_INTERRUPT SRRAW: RTC_ATIM1 Position */
\r
2331 #define SCU_INTERRUPT_SRRAW_RTC_ATIM1_Msk (0x01UL << SCU_INTERRUPT_SRRAW_RTC_ATIM1_Pos) /*!< SCU_INTERRUPT SRRAW: RTC_ATIM1 Mask */
\r
2332 #define SCU_INTERRUPT_SRRAW_RTC_TIM0_Pos 27 /*!< SCU_INTERRUPT SRRAW: RTC_TIM0 Position */
\r
2333 #define SCU_INTERRUPT_SRRAW_RTC_TIM0_Msk (0x01UL << SCU_INTERRUPT_SRRAW_RTC_TIM0_Pos) /*!< SCU_INTERRUPT SRRAW: RTC_TIM0 Mask */
\r
2334 #define SCU_INTERRUPT_SRRAW_RTC_TIM1_Pos 28 /*!< SCU_INTERRUPT SRRAW: RTC_TIM1 Position */
\r
2335 #define SCU_INTERRUPT_SRRAW_RTC_TIM1_Msk (0x01UL << SCU_INTERRUPT_SRRAW_RTC_TIM1_Pos) /*!< SCU_INTERRUPT SRRAW: RTC_TIM1 Mask */
\r
2336 #define SCU_INTERRUPT_SRRAW_TSE_DONE_Pos 29 /*!< SCU_INTERRUPT SRRAW: TSE_DONE Position */
\r
2337 #define SCU_INTERRUPT_SRRAW_TSE_DONE_Msk (0x01UL << SCU_INTERRUPT_SRRAW_TSE_DONE_Pos) /*!< SCU_INTERRUPT SRRAW: TSE_DONE Mask */
\r
2338 #define SCU_INTERRUPT_SRRAW_TSE_HIGH_Pos 30 /*!< SCU_INTERRUPT SRRAW: TSE_HIGH Position */
\r
2339 #define SCU_INTERRUPT_SRRAW_TSE_HIGH_Msk (0x01UL << SCU_INTERRUPT_SRRAW_TSE_HIGH_Pos) /*!< SCU_INTERRUPT SRRAW: TSE_HIGH Mask */
\r
2340 #define SCU_INTERRUPT_SRRAW_TSE_LOW_Pos 31 /*!< SCU_INTERRUPT SRRAW: TSE_LOW Position */
\r
2341 #define SCU_INTERRUPT_SRRAW_TSE_LOW_Msk (0x01UL << SCU_INTERRUPT_SRRAW_TSE_LOW_Pos) /*!< SCU_INTERRUPT SRRAW: TSE_LOW Mask */
\r
2343 /* ----------------------------- SCU_INTERRUPT_SRMSK ---------------------------- */
\r
2344 #define SCU_INTERRUPT_SRMSK_PRWARN_Pos 0 /*!< SCU_INTERRUPT SRMSK: PRWARN Position */
\r
2345 #define SCU_INTERRUPT_SRMSK_PRWARN_Msk (0x01UL << SCU_INTERRUPT_SRMSK_PRWARN_Pos) /*!< SCU_INTERRUPT SRMSK: PRWARN Mask */
\r
2346 #define SCU_INTERRUPT_SRMSK_VDDPI_Pos 3 /*!< SCU_INTERRUPT SRMSK: VDDPI Position */
\r
2347 #define SCU_INTERRUPT_SRMSK_VDDPI_Msk (0x01UL << SCU_INTERRUPT_SRMSK_VDDPI_Pos) /*!< SCU_INTERRUPT SRMSK: VDDPI Mask */
\r
2348 #define SCU_INTERRUPT_SRMSK_ACMP0I_Pos 4 /*!< SCU_INTERRUPT SRMSK: ACMP0I Position */
\r
2349 #define SCU_INTERRUPT_SRMSK_ACMP0I_Msk (0x01UL << SCU_INTERRUPT_SRMSK_ACMP0I_Pos) /*!< SCU_INTERRUPT SRMSK: ACMP0I Mask */
\r
2350 #define SCU_INTERRUPT_SRMSK_ACMP1I_Pos 5 /*!< SCU_INTERRUPT SRMSK: ACMP1I Position */
\r
2351 #define SCU_INTERRUPT_SRMSK_ACMP1I_Msk (0x01UL << SCU_INTERRUPT_SRMSK_ACMP1I_Pos) /*!< SCU_INTERRUPT SRMSK: ACMP1I Mask */
\r
2352 #define SCU_INTERRUPT_SRMSK_ACMP2I_Pos 6 /*!< SCU_INTERRUPT SRMSK: ACMP2I Position */
\r
2353 #define SCU_INTERRUPT_SRMSK_ACMP2I_Msk (0x01UL << SCU_INTERRUPT_SRMSK_ACMP2I_Pos) /*!< SCU_INTERRUPT SRMSK: ACMP2I Mask */
\r
2354 #define SCU_INTERRUPT_SRMSK_VDROPI_Pos 7 /*!< SCU_INTERRUPT SRMSK: VDROPI Position */
\r
2355 #define SCU_INTERRUPT_SRMSK_VDROPI_Msk (0x01UL << SCU_INTERRUPT_SRMSK_VDROPI_Pos) /*!< SCU_INTERRUPT SRMSK: VDROPI Mask */
\r
2356 #define SCU_INTERRUPT_SRMSK_ORC0I_Pos 8 /*!< SCU_INTERRUPT SRMSK: ORC0I Position */
\r
2357 #define SCU_INTERRUPT_SRMSK_ORC0I_Msk (0x01UL << SCU_INTERRUPT_SRMSK_ORC0I_Pos) /*!< SCU_INTERRUPT SRMSK: ORC0I Mask */
\r
2358 #define SCU_INTERRUPT_SRMSK_ORC1I_Pos 9 /*!< SCU_INTERRUPT SRMSK: ORC1I Position */
\r
2359 #define SCU_INTERRUPT_SRMSK_ORC1I_Msk (0x01UL << SCU_INTERRUPT_SRMSK_ORC1I_Pos) /*!< SCU_INTERRUPT SRMSK: ORC1I Mask */
\r
2360 #define SCU_INTERRUPT_SRMSK_ORC2I_Pos 10 /*!< SCU_INTERRUPT SRMSK: ORC2I Position */
\r
2361 #define SCU_INTERRUPT_SRMSK_ORC2I_Msk (0x01UL << SCU_INTERRUPT_SRMSK_ORC2I_Pos) /*!< SCU_INTERRUPT SRMSK: ORC2I Mask */
\r
2362 #define SCU_INTERRUPT_SRMSK_ORC3I_Pos 11 /*!< SCU_INTERRUPT SRMSK: ORC3I Position */
\r
2363 #define SCU_INTERRUPT_SRMSK_ORC3I_Msk (0x01UL << SCU_INTERRUPT_SRMSK_ORC3I_Pos) /*!< SCU_INTERRUPT SRMSK: ORC3I Mask */
\r
2364 #define SCU_INTERRUPT_SRMSK_ORC4I_Pos 12 /*!< SCU_INTERRUPT SRMSK: ORC4I Position */
\r
2365 #define SCU_INTERRUPT_SRMSK_ORC4I_Msk (0x01UL << SCU_INTERRUPT_SRMSK_ORC4I_Pos) /*!< SCU_INTERRUPT SRMSK: ORC4I Mask */
\r
2366 #define SCU_INTERRUPT_SRMSK_ORC5I_Pos 13 /*!< SCU_INTERRUPT SRMSK: ORC5I Position */
\r
2367 #define SCU_INTERRUPT_SRMSK_ORC5I_Msk (0x01UL << SCU_INTERRUPT_SRMSK_ORC5I_Pos) /*!< SCU_INTERRUPT SRMSK: ORC5I Mask */
\r
2368 #define SCU_INTERRUPT_SRMSK_ORC6I_Pos 14 /*!< SCU_INTERRUPT SRMSK: ORC6I Position */
\r
2369 #define SCU_INTERRUPT_SRMSK_ORC6I_Msk (0x01UL << SCU_INTERRUPT_SRMSK_ORC6I_Pos) /*!< SCU_INTERRUPT SRMSK: ORC6I Mask */
\r
2370 #define SCU_INTERRUPT_SRMSK_ORC7I_Pos 15 /*!< SCU_INTERRUPT SRMSK: ORC7I Position */
\r
2371 #define SCU_INTERRUPT_SRMSK_ORC7I_Msk (0x01UL << SCU_INTERRUPT_SRMSK_ORC7I_Pos) /*!< SCU_INTERRUPT SRMSK: ORC7I Mask */
\r
2372 #define SCU_INTERRUPT_SRMSK_LOCI_Pos 16 /*!< SCU_INTERRUPT SRMSK: LOCI Position */
\r
2373 #define SCU_INTERRUPT_SRMSK_LOCI_Msk (0x01UL << SCU_INTERRUPT_SRMSK_LOCI_Pos) /*!< SCU_INTERRUPT SRMSK: LOCI Mask */
\r
2374 #define SCU_INTERRUPT_SRMSK_PESRAMI_Pos 17 /*!< SCU_INTERRUPT SRMSK: PESRAMI Position */
\r
2375 #define SCU_INTERRUPT_SRMSK_PESRAMI_Msk (0x01UL << SCU_INTERRUPT_SRMSK_PESRAMI_Pos) /*!< SCU_INTERRUPT SRMSK: PESRAMI Mask */
\r
2376 #define SCU_INTERRUPT_SRMSK_PEU0I_Pos 18 /*!< SCU_INTERRUPT SRMSK: PEU0I Position */
\r
2377 #define SCU_INTERRUPT_SRMSK_PEU0I_Msk (0x01UL << SCU_INTERRUPT_SRMSK_PEU0I_Pos) /*!< SCU_INTERRUPT SRMSK: PEU0I Mask */
\r
2378 #define SCU_INTERRUPT_SRMSK_FLECC2I_Pos 19 /*!< SCU_INTERRUPT SRMSK: FLECC2I Position */
\r
2379 #define SCU_INTERRUPT_SRMSK_FLECC2I_Msk (0x01UL << SCU_INTERRUPT_SRMSK_FLECC2I_Pos) /*!< SCU_INTERRUPT SRMSK: FLECC2I Mask */
\r
2380 #define SCU_INTERRUPT_SRMSK_VCLIPI_Pos 21 /*!< SCU_INTERRUPT SRMSK: VCLIPI Position */
\r
2381 #define SCU_INTERRUPT_SRMSK_VCLIPI_Msk (0x01UL << SCU_INTERRUPT_SRMSK_VCLIPI_Pos) /*!< SCU_INTERRUPT SRMSK: VCLIPI Mask */
\r
2382 #define SCU_INTERRUPT_SRMSK_SBYCLKFI_Pos 22 /*!< SCU_INTERRUPT SRMSK: SBYCLKFI Position */
\r
2383 #define SCU_INTERRUPT_SRMSK_SBYCLKFI_Msk (0x01UL << SCU_INTERRUPT_SRMSK_SBYCLKFI_Pos) /*!< SCU_INTERRUPT SRMSK: SBYCLKFI Mask */
\r
2384 #define SCU_INTERRUPT_SRMSK_RTC_CTR_Pos 24 /*!< SCU_INTERRUPT SRMSK: RTC_CTR Position */
\r
2385 #define SCU_INTERRUPT_SRMSK_RTC_CTR_Msk (0x01UL << SCU_INTERRUPT_SRMSK_RTC_CTR_Pos) /*!< SCU_INTERRUPT SRMSK: RTC_CTR Mask */
\r
2386 #define SCU_INTERRUPT_SRMSK_RTC_ATIM0_Pos 25 /*!< SCU_INTERRUPT SRMSK: RTC_ATIM0 Position */
\r
2387 #define SCU_INTERRUPT_SRMSK_RTC_ATIM0_Msk (0x01UL << SCU_INTERRUPT_SRMSK_RTC_ATIM0_Pos) /*!< SCU_INTERRUPT SRMSK: RTC_ATIM0 Mask */
\r
2388 #define SCU_INTERRUPT_SRMSK_RTC_ATIM1_Pos 26 /*!< SCU_INTERRUPT SRMSK: RTC_ATIM1 Position */
\r
2389 #define SCU_INTERRUPT_SRMSK_RTC_ATIM1_Msk (0x01UL << SCU_INTERRUPT_SRMSK_RTC_ATIM1_Pos) /*!< SCU_INTERRUPT SRMSK: RTC_ATIM1 Mask */
\r
2390 #define SCU_INTERRUPT_SRMSK_RTC_TIM0_Pos 27 /*!< SCU_INTERRUPT SRMSK: RTC_TIM0 Position */
\r
2391 #define SCU_INTERRUPT_SRMSK_RTC_TIM0_Msk (0x01UL << SCU_INTERRUPT_SRMSK_RTC_TIM0_Pos) /*!< SCU_INTERRUPT SRMSK: RTC_TIM0 Mask */
\r
2392 #define SCU_INTERRUPT_SRMSK_RTC_TIM1_Pos 28 /*!< SCU_INTERRUPT SRMSK: RTC_TIM1 Position */
\r
2393 #define SCU_INTERRUPT_SRMSK_RTC_TIM1_Msk (0x01UL << SCU_INTERRUPT_SRMSK_RTC_TIM1_Pos) /*!< SCU_INTERRUPT SRMSK: RTC_TIM1 Mask */
\r
2394 #define SCU_INTERRUPT_SRMSK_TSE_DONE_Pos 29 /*!< SCU_INTERRUPT SRMSK: TSE_DONE Position */
\r
2395 #define SCU_INTERRUPT_SRMSK_TSE_DONE_Msk (0x01UL << SCU_INTERRUPT_SRMSK_TSE_DONE_Pos) /*!< SCU_INTERRUPT SRMSK: TSE_DONE Mask */
\r
2396 #define SCU_INTERRUPT_SRMSK_TSE_HIGH_Pos 30 /*!< SCU_INTERRUPT SRMSK: TSE_HIGH Position */
\r
2397 #define SCU_INTERRUPT_SRMSK_TSE_HIGH_Msk (0x01UL << SCU_INTERRUPT_SRMSK_TSE_HIGH_Pos) /*!< SCU_INTERRUPT SRMSK: TSE_HIGH Mask */
\r
2398 #define SCU_INTERRUPT_SRMSK_TSE_LOW_Pos 31 /*!< SCU_INTERRUPT SRMSK: TSE_LOW Position */
\r
2399 #define SCU_INTERRUPT_SRMSK_TSE_LOW_Msk (0x01UL << SCU_INTERRUPT_SRMSK_TSE_LOW_Pos) /*!< SCU_INTERRUPT SRMSK: TSE_LOW Mask */
\r
2401 /* ----------------------------- SCU_INTERRUPT_SRCLR ---------------------------- */
\r
2402 #define SCU_INTERRUPT_SRCLR_PRWARN_Pos 0 /*!< SCU_INTERRUPT SRCLR: PRWARN Position */
\r
2403 #define SCU_INTERRUPT_SRCLR_PRWARN_Msk (0x01UL << SCU_INTERRUPT_SRCLR_PRWARN_Pos) /*!< SCU_INTERRUPT SRCLR: PRWARN Mask */
\r
2404 #define SCU_INTERRUPT_SRCLR_PI_Pos 1 /*!< SCU_INTERRUPT SRCLR: PI Position */
\r
2405 #define SCU_INTERRUPT_SRCLR_PI_Msk (0x01UL << SCU_INTERRUPT_SRCLR_PI_Pos) /*!< SCU_INTERRUPT SRCLR: PI Mask */
\r
2406 #define SCU_INTERRUPT_SRCLR_AI_Pos 2 /*!< SCU_INTERRUPT SRCLR: AI Position */
\r
2407 #define SCU_INTERRUPT_SRCLR_AI_Msk (0x01UL << SCU_INTERRUPT_SRCLR_AI_Pos) /*!< SCU_INTERRUPT SRCLR: AI Mask */
\r
2408 #define SCU_INTERRUPT_SRCLR_VDDPI_Pos 3 /*!< SCU_INTERRUPT SRCLR: VDDPI Position */
\r
2409 #define SCU_INTERRUPT_SRCLR_VDDPI_Msk (0x01UL << SCU_INTERRUPT_SRCLR_VDDPI_Pos) /*!< SCU_INTERRUPT SRCLR: VDDPI Mask */
\r
2410 #define SCU_INTERRUPT_SRCLR_ACMP0I_Pos 4 /*!< SCU_INTERRUPT SRCLR: ACMP0I Position */
\r
2411 #define SCU_INTERRUPT_SRCLR_ACMP0I_Msk (0x01UL << SCU_INTERRUPT_SRCLR_ACMP0I_Pos) /*!< SCU_INTERRUPT SRCLR: ACMP0I Mask */
\r
2412 #define SCU_INTERRUPT_SRCLR_ACMP1I_Pos 5 /*!< SCU_INTERRUPT SRCLR: ACMP1I Position */
\r
2413 #define SCU_INTERRUPT_SRCLR_ACMP1I_Msk (0x01UL << SCU_INTERRUPT_SRCLR_ACMP1I_Pos) /*!< SCU_INTERRUPT SRCLR: ACMP1I Mask */
\r
2414 #define SCU_INTERRUPT_SRCLR_ACMP2I_Pos 6 /*!< SCU_INTERRUPT SRCLR: ACMP2I Position */
\r
2415 #define SCU_INTERRUPT_SRCLR_ACMP2I_Msk (0x01UL << SCU_INTERRUPT_SRCLR_ACMP2I_Pos) /*!< SCU_INTERRUPT SRCLR: ACMP2I Mask */
\r
2416 #define SCU_INTERRUPT_SRCLR_VDROPI_Pos 7 /*!< SCU_INTERRUPT SRCLR: VDROPI Position */
\r
2417 #define SCU_INTERRUPT_SRCLR_VDROPI_Msk (0x01UL << SCU_INTERRUPT_SRCLR_VDROPI_Pos) /*!< SCU_INTERRUPT SRCLR: VDROPI Mask */
\r
2418 #define SCU_INTERRUPT_SRCLR_ORC0I_Pos 8 /*!< SCU_INTERRUPT SRCLR: ORC0I Position */
\r
2419 #define SCU_INTERRUPT_SRCLR_ORC0I_Msk (0x01UL << SCU_INTERRUPT_SRCLR_ORC0I_Pos) /*!< SCU_INTERRUPT SRCLR: ORC0I Mask */
\r
2420 #define SCU_INTERRUPT_SRCLR_ORC1I_Pos 9 /*!< SCU_INTERRUPT SRCLR: ORC1I Position */
\r
2421 #define SCU_INTERRUPT_SRCLR_ORC1I_Msk (0x01UL << SCU_INTERRUPT_SRCLR_ORC1I_Pos) /*!< SCU_INTERRUPT SRCLR: ORC1I Mask */
\r
2422 #define SCU_INTERRUPT_SRCLR_ORC2I_Pos 10 /*!< SCU_INTERRUPT SRCLR: ORC2I Position */
\r
2423 #define SCU_INTERRUPT_SRCLR_ORC2I_Msk (0x01UL << SCU_INTERRUPT_SRCLR_ORC2I_Pos) /*!< SCU_INTERRUPT SRCLR: ORC2I Mask */
\r
2424 #define SCU_INTERRUPT_SRCLR_ORC3I_Pos 11 /*!< SCU_INTERRUPT SRCLR: ORC3I Position */
\r
2425 #define SCU_INTERRUPT_SRCLR_ORC3I_Msk (0x01UL << SCU_INTERRUPT_SRCLR_ORC3I_Pos) /*!< SCU_INTERRUPT SRCLR: ORC3I Mask */
\r
2426 #define SCU_INTERRUPT_SRCLR_ORC4I_Pos 12 /*!< SCU_INTERRUPT SRCLR: ORC4I Position */
\r
2427 #define SCU_INTERRUPT_SRCLR_ORC4I_Msk (0x01UL << SCU_INTERRUPT_SRCLR_ORC4I_Pos) /*!< SCU_INTERRUPT SRCLR: ORC4I Mask */
\r
2428 #define SCU_INTERRUPT_SRCLR_ORC5I_Pos 13 /*!< SCU_INTERRUPT SRCLR: ORC5I Position */
\r
2429 #define SCU_INTERRUPT_SRCLR_ORC5I_Msk (0x01UL << SCU_INTERRUPT_SRCLR_ORC5I_Pos) /*!< SCU_INTERRUPT SRCLR: ORC5I Mask */
\r
2430 #define SCU_INTERRUPT_SRCLR_ORC6I_Pos 14 /*!< SCU_INTERRUPT SRCLR: ORC6I Position */
\r
2431 #define SCU_INTERRUPT_SRCLR_ORC6I_Msk (0x01UL << SCU_INTERRUPT_SRCLR_ORC6I_Pos) /*!< SCU_INTERRUPT SRCLR: ORC6I Mask */
\r
2432 #define SCU_INTERRUPT_SRCLR_ORC7I_Pos 15 /*!< SCU_INTERRUPT SRCLR: ORC7I Position */
\r
2433 #define SCU_INTERRUPT_SRCLR_ORC7I_Msk (0x01UL << SCU_INTERRUPT_SRCLR_ORC7I_Pos) /*!< SCU_INTERRUPT SRCLR: ORC7I Mask */
\r
2434 #define SCU_INTERRUPT_SRCLR_LOCI_Pos 16 /*!< SCU_INTERRUPT SRCLR: LOCI Position */
\r
2435 #define SCU_INTERRUPT_SRCLR_LOCI_Msk (0x01UL << SCU_INTERRUPT_SRCLR_LOCI_Pos) /*!< SCU_INTERRUPT SRCLR: LOCI Mask */
\r
2436 #define SCU_INTERRUPT_SRCLR_PESRAMI_Pos 17 /*!< SCU_INTERRUPT SRCLR: PESRAMI Position */
\r
2437 #define SCU_INTERRUPT_SRCLR_PESRAMI_Msk (0x01UL << SCU_INTERRUPT_SRCLR_PESRAMI_Pos) /*!< SCU_INTERRUPT SRCLR: PESRAMI Mask */
\r
2438 #define SCU_INTERRUPT_SRCLR_PEU0I_Pos 18 /*!< SCU_INTERRUPT SRCLR: PEU0I Position */
\r
2439 #define SCU_INTERRUPT_SRCLR_PEU0I_Msk (0x01UL << SCU_INTERRUPT_SRCLR_PEU0I_Pos) /*!< SCU_INTERRUPT SRCLR: PEU0I Mask */
\r
2440 #define SCU_INTERRUPT_SRCLR_FLECC2I_Pos 19 /*!< SCU_INTERRUPT SRCLR: FLECC2I Position */
\r
2441 #define SCU_INTERRUPT_SRCLR_FLECC2I_Msk (0x01UL << SCU_INTERRUPT_SRCLR_FLECC2I_Pos) /*!< SCU_INTERRUPT SRCLR: FLECC2I Mask */
\r
2442 #define SCU_INTERRUPT_SRCLR_FLCMPLTI_Pos 20 /*!< SCU_INTERRUPT SRCLR: FLCMPLTI Position */
\r
2443 #define SCU_INTERRUPT_SRCLR_FLCMPLTI_Msk (0x01UL << SCU_INTERRUPT_SRCLR_FLCMPLTI_Pos) /*!< SCU_INTERRUPT SRCLR: FLCMPLTI Mask */
\r
2444 #define SCU_INTERRUPT_SRCLR_VCLIPI_Pos 21 /*!< SCU_INTERRUPT SRCLR: VCLIPI Position */
\r
2445 #define SCU_INTERRUPT_SRCLR_VCLIPI_Msk (0x01UL << SCU_INTERRUPT_SRCLR_VCLIPI_Pos) /*!< SCU_INTERRUPT SRCLR: VCLIPI Mask */
\r
2446 #define SCU_INTERRUPT_SRCLR_SBYCLKFI_Pos 22 /*!< SCU_INTERRUPT SRCLR: SBYCLKFI Position */
\r
2447 #define SCU_INTERRUPT_SRCLR_SBYCLKFI_Msk (0x01UL << SCU_INTERRUPT_SRCLR_SBYCLKFI_Pos) /*!< SCU_INTERRUPT SRCLR: SBYCLKFI Mask */
\r
2448 #define SCU_INTERRUPT_SRCLR_RTC_CTR_Pos 24 /*!< SCU_INTERRUPT SRCLR: RTC_CTR Position */
\r
2449 #define SCU_INTERRUPT_SRCLR_RTC_CTR_Msk (0x01UL << SCU_INTERRUPT_SRCLR_RTC_CTR_Pos) /*!< SCU_INTERRUPT SRCLR: RTC_CTR Mask */
\r
2450 #define SCU_INTERRUPT_SRCLR_RTC_ATIM0_Pos 25 /*!< SCU_INTERRUPT SRCLR: RTC_ATIM0 Position */
\r
2451 #define SCU_INTERRUPT_SRCLR_RTC_ATIM0_Msk (0x01UL << SCU_INTERRUPT_SRCLR_RTC_ATIM0_Pos) /*!< SCU_INTERRUPT SRCLR: RTC_ATIM0 Mask */
\r
2452 #define SCU_INTERRUPT_SRCLR_RTC_ATIM1_Pos 26 /*!< SCU_INTERRUPT SRCLR: RTC_ATIM1 Position */
\r
2453 #define SCU_INTERRUPT_SRCLR_RTC_ATIM1_Msk (0x01UL << SCU_INTERRUPT_SRCLR_RTC_ATIM1_Pos) /*!< SCU_INTERRUPT SRCLR: RTC_ATIM1 Mask */
\r
2454 #define SCU_INTERRUPT_SRCLR_RTC_TIM0_Pos 27 /*!< SCU_INTERRUPT SRCLR: RTC_TIM0 Position */
\r
2455 #define SCU_INTERRUPT_SRCLR_RTC_TIM0_Msk (0x01UL << SCU_INTERRUPT_SRCLR_RTC_TIM0_Pos) /*!< SCU_INTERRUPT SRCLR: RTC_TIM0 Mask */
\r
2456 #define SCU_INTERRUPT_SRCLR_RTC_TIM1_Pos 28 /*!< SCU_INTERRUPT SRCLR: RTC_TIM1 Position */
\r
2457 #define SCU_INTERRUPT_SRCLR_RTC_TIM1_Msk (0x01UL << SCU_INTERRUPT_SRCLR_RTC_TIM1_Pos) /*!< SCU_INTERRUPT SRCLR: RTC_TIM1 Mask */
\r
2458 #define SCU_INTERRUPT_SRCLR_TSE_DONE_Pos 29 /*!< SCU_INTERRUPT SRCLR: TSE_DONE Position */
\r
2459 #define SCU_INTERRUPT_SRCLR_TSE_DONE_Msk (0x01UL << SCU_INTERRUPT_SRCLR_TSE_DONE_Pos) /*!< SCU_INTERRUPT SRCLR: TSE_DONE Mask */
\r
2460 #define SCU_INTERRUPT_SRCLR_TSE_HIGH_Pos 30 /*!< SCU_INTERRUPT SRCLR: TSE_HIGH Position */
\r
2461 #define SCU_INTERRUPT_SRCLR_TSE_HIGH_Msk (0x01UL << SCU_INTERRUPT_SRCLR_TSE_HIGH_Pos) /*!< SCU_INTERRUPT SRCLR: TSE_HIGH Mask */
\r
2462 #define SCU_INTERRUPT_SRCLR_TSE_LOW_Pos 31 /*!< SCU_INTERRUPT SRCLR: TSE_LOW Position */
\r
2463 #define SCU_INTERRUPT_SRCLR_TSE_LOW_Msk (0x01UL << SCU_INTERRUPT_SRCLR_TSE_LOW_Pos) /*!< SCU_INTERRUPT SRCLR: TSE_LOW Mask */
\r
2465 /* ----------------------------- SCU_INTERRUPT_SRSET ---------------------------- */
\r
2466 #define SCU_INTERRUPT_SRSET_PRWARN_Pos 0 /*!< SCU_INTERRUPT SRSET: PRWARN Position */
\r
2467 #define SCU_INTERRUPT_SRSET_PRWARN_Msk (0x01UL << SCU_INTERRUPT_SRSET_PRWARN_Pos) /*!< SCU_INTERRUPT SRSET: PRWARN Mask */
\r
2468 #define SCU_INTERRUPT_SRSET_PI_Pos 1 /*!< SCU_INTERRUPT SRSET: PI Position */
\r
2469 #define SCU_INTERRUPT_SRSET_PI_Msk (0x01UL << SCU_INTERRUPT_SRSET_PI_Pos) /*!< SCU_INTERRUPT SRSET: PI Mask */
\r
2470 #define SCU_INTERRUPT_SRSET_AI_Pos 2 /*!< SCU_INTERRUPT SRSET: AI Position */
\r
2471 #define SCU_INTERRUPT_SRSET_AI_Msk (0x01UL << SCU_INTERRUPT_SRSET_AI_Pos) /*!< SCU_INTERRUPT SRSET: AI Mask */
\r
2472 #define SCU_INTERRUPT_SRSET_VDDPI_Pos 3 /*!< SCU_INTERRUPT SRSET: VDDPI Position */
\r
2473 #define SCU_INTERRUPT_SRSET_VDDPI_Msk (0x01UL << SCU_INTERRUPT_SRSET_VDDPI_Pos) /*!< SCU_INTERRUPT SRSET: VDDPI Mask */
\r
2474 #define SCU_INTERRUPT_SRSET_ACMP0I_Pos 4 /*!< SCU_INTERRUPT SRSET: ACMP0I Position */
\r
2475 #define SCU_INTERRUPT_SRSET_ACMP0I_Msk (0x01UL << SCU_INTERRUPT_SRSET_ACMP0I_Pos) /*!< SCU_INTERRUPT SRSET: ACMP0I Mask */
\r
2476 #define SCU_INTERRUPT_SRSET_ACMP1I_Pos 5 /*!< SCU_INTERRUPT SRSET: ACMP1I Position */
\r
2477 #define SCU_INTERRUPT_SRSET_ACMP1I_Msk (0x01UL << SCU_INTERRUPT_SRSET_ACMP1I_Pos) /*!< SCU_INTERRUPT SRSET: ACMP1I Mask */
\r
2478 #define SCU_INTERRUPT_SRSET_ACMP2I_Pos 6 /*!< SCU_INTERRUPT SRSET: ACMP2I Position */
\r
2479 #define SCU_INTERRUPT_SRSET_ACMP2I_Msk (0x01UL << SCU_INTERRUPT_SRSET_ACMP2I_Pos) /*!< SCU_INTERRUPT SRSET: ACMP2I Mask */
\r
2480 #define SCU_INTERRUPT_SRSET_VDROPI_Pos 7 /*!< SCU_INTERRUPT SRSET: VDROPI Position */
\r
2481 #define SCU_INTERRUPT_SRSET_VDROPI_Msk (0x01UL << SCU_INTERRUPT_SRSET_VDROPI_Pos) /*!< SCU_INTERRUPT SRSET: VDROPI Mask */
\r
2482 #define SCU_INTERRUPT_SRSET_ORC0I_Pos 8 /*!< SCU_INTERRUPT SRSET: ORC0I Position */
\r
2483 #define SCU_INTERRUPT_SRSET_ORC0I_Msk (0x01UL << SCU_INTERRUPT_SRSET_ORC0I_Pos) /*!< SCU_INTERRUPT SRSET: ORC0I Mask */
\r
2484 #define SCU_INTERRUPT_SRSET_ORC1I_Pos 9 /*!< SCU_INTERRUPT SRSET: ORC1I Position */
\r
2485 #define SCU_INTERRUPT_SRSET_ORC1I_Msk (0x01UL << SCU_INTERRUPT_SRSET_ORC1I_Pos) /*!< SCU_INTERRUPT SRSET: ORC1I Mask */
\r
2486 #define SCU_INTERRUPT_SRSET_ORC2I_Pos 10 /*!< SCU_INTERRUPT SRSET: ORC2I Position */
\r
2487 #define SCU_INTERRUPT_SRSET_ORC2I_Msk (0x01UL << SCU_INTERRUPT_SRSET_ORC2I_Pos) /*!< SCU_INTERRUPT SRSET: ORC2I Mask */
\r
2488 #define SCU_INTERRUPT_SRSET_ORC3I_Pos 11 /*!< SCU_INTERRUPT SRSET: ORC3I Position */
\r
2489 #define SCU_INTERRUPT_SRSET_ORC3I_Msk (0x01UL << SCU_INTERRUPT_SRSET_ORC3I_Pos) /*!< SCU_INTERRUPT SRSET: ORC3I Mask */
\r
2490 #define SCU_INTERRUPT_SRSET_ORC4I_Pos 12 /*!< SCU_INTERRUPT SRSET: ORC4I Position */
\r
2491 #define SCU_INTERRUPT_SRSET_ORC4I_Msk (0x01UL << SCU_INTERRUPT_SRSET_ORC4I_Pos) /*!< SCU_INTERRUPT SRSET: ORC4I Mask */
\r
2492 #define SCU_INTERRUPT_SRSET_ORC5I_Pos 13 /*!< SCU_INTERRUPT SRSET: ORC5I Position */
\r
2493 #define SCU_INTERRUPT_SRSET_ORC5I_Msk (0x01UL << SCU_INTERRUPT_SRSET_ORC5I_Pos) /*!< SCU_INTERRUPT SRSET: ORC5I Mask */
\r
2494 #define SCU_INTERRUPT_SRSET_ORC6I_Pos 14 /*!< SCU_INTERRUPT SRSET: ORC6I Position */
\r
2495 #define SCU_INTERRUPT_SRSET_ORC6I_Msk (0x01UL << SCU_INTERRUPT_SRSET_ORC6I_Pos) /*!< SCU_INTERRUPT SRSET: ORC6I Mask */
\r
2496 #define SCU_INTERRUPT_SRSET_ORC7I_Pos 15 /*!< SCU_INTERRUPT SRSET: ORC7I Position */
\r
2497 #define SCU_INTERRUPT_SRSET_ORC7I_Msk (0x01UL << SCU_INTERRUPT_SRSET_ORC7I_Pos) /*!< SCU_INTERRUPT SRSET: ORC7I Mask */
\r
2498 #define SCU_INTERRUPT_SRSET_LOCI_Pos 16 /*!< SCU_INTERRUPT SRSET: LOCI Position */
\r
2499 #define SCU_INTERRUPT_SRSET_LOCI_Msk (0x01UL << SCU_INTERRUPT_SRSET_LOCI_Pos) /*!< SCU_INTERRUPT SRSET: LOCI Mask */
\r
2500 #define SCU_INTERRUPT_SRSET_PESRAMI_Pos 17 /*!< SCU_INTERRUPT SRSET: PESRAMI Position */
\r
2501 #define SCU_INTERRUPT_SRSET_PESRAMI_Msk (0x01UL << SCU_INTERRUPT_SRSET_PESRAMI_Pos) /*!< SCU_INTERRUPT SRSET: PESRAMI Mask */
\r
2502 #define SCU_INTERRUPT_SRSET_PEU0I_Pos 18 /*!< SCU_INTERRUPT SRSET: PEU0I Position */
\r
2503 #define SCU_INTERRUPT_SRSET_PEU0I_Msk (0x01UL << SCU_INTERRUPT_SRSET_PEU0I_Pos) /*!< SCU_INTERRUPT SRSET: PEU0I Mask */
\r
2504 #define SCU_INTERRUPT_SRSET_FLECC2I_Pos 19 /*!< SCU_INTERRUPT SRSET: FLECC2I Position */
\r
2505 #define SCU_INTERRUPT_SRSET_FLECC2I_Msk (0x01UL << SCU_INTERRUPT_SRSET_FLECC2I_Pos) /*!< SCU_INTERRUPT SRSET: FLECC2I Mask */
\r
2506 #define SCU_INTERRUPT_SRSET_FLCMPLTI_Pos 20 /*!< SCU_INTERRUPT SRSET: FLCMPLTI Position */
\r
2507 #define SCU_INTERRUPT_SRSET_FLCMPLTI_Msk (0x01UL << SCU_INTERRUPT_SRSET_FLCMPLTI_Pos) /*!< SCU_INTERRUPT SRSET: FLCMPLTI Mask */
\r
2508 #define SCU_INTERRUPT_SRSET_VCLIPI_Pos 21 /*!< SCU_INTERRUPT SRSET: VCLIPI Position */
\r
2509 #define SCU_INTERRUPT_SRSET_VCLIPI_Msk (0x01UL << SCU_INTERRUPT_SRSET_VCLIPI_Pos) /*!< SCU_INTERRUPT SRSET: VCLIPI Mask */
\r
2510 #define SCU_INTERRUPT_SRSET_SBYCLKFI_Pos 22 /*!< SCU_INTERRUPT SRSET: SBYCLKFI Position */
\r
2511 #define SCU_INTERRUPT_SRSET_SBYCLKFI_Msk (0x01UL << SCU_INTERRUPT_SRSET_SBYCLKFI_Pos) /*!< SCU_INTERRUPT SRSET: SBYCLKFI Mask */
\r
2512 #define SCU_INTERRUPT_SRSET_RTC_CTR_Pos 24 /*!< SCU_INTERRUPT SRSET: RTC_CTR Position */
\r
2513 #define SCU_INTERRUPT_SRSET_RTC_CTR_Msk (0x01UL << SCU_INTERRUPT_SRSET_RTC_CTR_Pos) /*!< SCU_INTERRUPT SRSET: RTC_CTR Mask */
\r
2514 #define SCU_INTERRUPT_SRSET_RTC_ATIM0_Pos 25 /*!< SCU_INTERRUPT SRSET: RTC_ATIM0 Position */
\r
2515 #define SCU_INTERRUPT_SRSET_RTC_ATIM0_Msk (0x01UL << SCU_INTERRUPT_SRSET_RTC_ATIM0_Pos) /*!< SCU_INTERRUPT SRSET: RTC_ATIM0 Mask */
\r
2516 #define SCU_INTERRUPT_SRSET_RTC_ATIM1_Pos 26 /*!< SCU_INTERRUPT SRSET: RTC_ATIM1 Position */
\r
2517 #define SCU_INTERRUPT_SRSET_RTC_ATIM1_Msk (0x01UL << SCU_INTERRUPT_SRSET_RTC_ATIM1_Pos) /*!< SCU_INTERRUPT SRSET: RTC_ATIM1 Mask */
\r
2518 #define SCU_INTERRUPT_SRSET_RTC_TIM0_Pos 27 /*!< SCU_INTERRUPT SRSET: RTC_TIM0 Position */
\r
2519 #define SCU_INTERRUPT_SRSET_RTC_TIM0_Msk (0x01UL << SCU_INTERRUPT_SRSET_RTC_TIM0_Pos) /*!< SCU_INTERRUPT SRSET: RTC_TIM0 Mask */
\r
2520 #define SCU_INTERRUPT_SRSET_RTC_TIM1_Pos 28 /*!< SCU_INTERRUPT SRSET: RTC_TIM1 Position */
\r
2521 #define SCU_INTERRUPT_SRSET_RTC_TIM1_Msk (0x01UL << SCU_INTERRUPT_SRSET_RTC_TIM1_Pos) /*!< SCU_INTERRUPT SRSET: RTC_TIM1 Mask */
\r
2522 #define SCU_INTERRUPT_SRSET_TSE_DONE_Pos 29 /*!< SCU_INTERRUPT SRSET: TSE_DONE Position */
\r
2523 #define SCU_INTERRUPT_SRSET_TSE_DONE_Msk (0x01UL << SCU_INTERRUPT_SRSET_TSE_DONE_Pos) /*!< SCU_INTERRUPT SRSET: TSE_DONE Mask */
\r
2524 #define SCU_INTERRUPT_SRSET_TSE_HIGH_Pos 30 /*!< SCU_INTERRUPT SRSET: TSE_HIGH Position */
\r
2525 #define SCU_INTERRUPT_SRSET_TSE_HIGH_Msk (0x01UL << SCU_INTERRUPT_SRSET_TSE_HIGH_Pos) /*!< SCU_INTERRUPT SRSET: TSE_HIGH Mask */
\r
2526 #define SCU_INTERRUPT_SRSET_TSE_LOW_Pos 31 /*!< SCU_INTERRUPT SRSET: TSE_LOW Position */
\r
2527 #define SCU_INTERRUPT_SRSET_TSE_LOW_Msk (0x01UL << SCU_INTERRUPT_SRSET_TSE_LOW_Pos) /*!< SCU_INTERRUPT SRSET: TSE_LOW Mask */
\r
2530 /* ================================================================================ */
\r
2531 /* ================ struct 'SCU_POWER' Position & Mask ================ */
\r
2532 /* ================================================================================ */
\r
2535 /* ------------------------------- SCU_POWER_VDESR ------------------------------ */
\r
2536 #define SCU_POWER_VDESR_VCLIP_Pos 0 /*!< SCU_POWER VDESR: VCLIP Position */
\r
2537 #define SCU_POWER_VDESR_VCLIP_Msk (0x01UL << SCU_POWER_VDESR_VCLIP_Pos) /*!< SCU_POWER VDESR: VCLIP Mask */
\r
2538 #define SCU_POWER_VDESR_VDDPPW_Pos 1 /*!< SCU_POWER VDESR: VDDPPW Position */
\r
2539 #define SCU_POWER_VDESR_VDDPPW_Msk (0x01UL << SCU_POWER_VDESR_VDDPPW_Pos) /*!< SCU_POWER VDESR: VDDPPW Mask */
\r
2542 /* ================================================================================ */
\r
2543 /* ================ struct 'SCU_CLK' Position & Mask ================ */
\r
2544 /* ================================================================================ */
\r
2547 /* -------------------------------- SCU_CLK_CLKCR ------------------------------- */
\r
2548 #define SCU_CLK_CLKCR_FDIV_Pos 0 /*!< SCU_CLK CLKCR: FDIV Position */
\r
2549 #define SCU_CLK_CLKCR_FDIV_Msk (0x000000ffUL << SCU_CLK_CLKCR_FDIV_Pos) /*!< SCU_CLK CLKCR: FDIV Mask */
\r
2550 #define SCU_CLK_CLKCR_IDIV_Pos 8 /*!< SCU_CLK CLKCR: IDIV Position */
\r
2551 #define SCU_CLK_CLKCR_IDIV_Msk (0x000000ffUL << SCU_CLK_CLKCR_IDIV_Pos) /*!< SCU_CLK CLKCR: IDIV Mask */
\r
2552 #define SCU_CLK_CLKCR_PCLKSEL_Pos 16 /*!< SCU_CLK CLKCR: PCLKSEL Position */
\r
2553 #define SCU_CLK_CLKCR_PCLKSEL_Msk (0x01UL << SCU_CLK_CLKCR_PCLKSEL_Pos) /*!< SCU_CLK CLKCR: PCLKSEL Mask */
\r
2554 #define SCU_CLK_CLKCR_RTCCLKSEL_Pos 17 /*!< SCU_CLK CLKCR: RTCCLKSEL Position */
\r
2555 #define SCU_CLK_CLKCR_RTCCLKSEL_Msk (0x07UL << SCU_CLK_CLKCR_RTCCLKSEL_Pos) /*!< SCU_CLK CLKCR: RTCCLKSEL Mask */
\r
2556 #define SCU_CLK_CLKCR_CNTADJ_Pos 20 /*!< SCU_CLK CLKCR: CNTADJ Position */
\r
2557 #define SCU_CLK_CLKCR_CNTADJ_Msk (0x000003ffUL << SCU_CLK_CLKCR_CNTADJ_Pos) /*!< SCU_CLK CLKCR: CNTADJ Mask */
\r
2558 #define SCU_CLK_CLKCR_VDDC2LOW_Pos 30 /*!< SCU_CLK CLKCR: VDDC2LOW Position */
\r
2559 #define SCU_CLK_CLKCR_VDDC2LOW_Msk (0x01UL << SCU_CLK_CLKCR_VDDC2LOW_Pos) /*!< SCU_CLK CLKCR: VDDC2LOW Mask */
\r
2560 #define SCU_CLK_CLKCR_VDDC2HIGH_Pos 31 /*!< SCU_CLK CLKCR: VDDC2HIGH Position */
\r
2561 #define SCU_CLK_CLKCR_VDDC2HIGH_Msk (0x01UL << SCU_CLK_CLKCR_VDDC2HIGH_Pos) /*!< SCU_CLK CLKCR: VDDC2HIGH Mask */
\r
2563 /* ------------------------------- SCU_CLK_PWRSVCR ------------------------------ */
\r
2564 #define SCU_CLK_PWRSVCR_FPD_Pos 0 /*!< SCU_CLK PWRSVCR: FPD Position */
\r
2565 #define SCU_CLK_PWRSVCR_FPD_Msk (0x01UL << SCU_CLK_PWRSVCR_FPD_Pos) /*!< SCU_CLK PWRSVCR: FPD Mask */
\r
2567 /* ------------------------------ SCU_CLK_CGATSTAT0 ----------------------------- */
\r
2568 #define SCU_CLK_CGATSTAT0_VADC_Pos 0 /*!< SCU_CLK CGATSTAT0: VADC Position */
\r
2569 #define SCU_CLK_CGATSTAT0_VADC_Msk (0x01UL << SCU_CLK_CGATSTAT0_VADC_Pos) /*!< SCU_CLK CGATSTAT0: VADC Mask */
\r
2570 #define SCU_CLK_CGATSTAT0_CCU40_Pos 2 /*!< SCU_CLK CGATSTAT0: CCU40 Position */
\r
2571 #define SCU_CLK_CGATSTAT0_CCU40_Msk (0x01UL << SCU_CLK_CGATSTAT0_CCU40_Pos) /*!< SCU_CLK CGATSTAT0: CCU40 Mask */
\r
2572 #define SCU_CLK_CGATSTAT0_USIC0_Pos 3 /*!< SCU_CLK CGATSTAT0: USIC0 Position */
\r
2573 #define SCU_CLK_CGATSTAT0_USIC0_Msk (0x01UL << SCU_CLK_CGATSTAT0_USIC0_Pos) /*!< SCU_CLK CGATSTAT0: USIC0 Mask */
\r
2574 #define SCU_CLK_CGATSTAT0_WDT_Pos 9 /*!< SCU_CLK CGATSTAT0: WDT Position */
\r
2575 #define SCU_CLK_CGATSTAT0_WDT_Msk (0x01UL << SCU_CLK_CGATSTAT0_WDT_Pos) /*!< SCU_CLK CGATSTAT0: WDT Mask */
\r
2576 #define SCU_CLK_CGATSTAT0_RTC_Pos 10 /*!< SCU_CLK CGATSTAT0: RTC Position */
\r
2577 #define SCU_CLK_CGATSTAT0_RTC_Msk (0x01UL << SCU_CLK_CGATSTAT0_RTC_Pos) /*!< SCU_CLK CGATSTAT0: RTC Mask */
\r
2579 /* ------------------------------ SCU_CLK_CGATSET0 ------------------------------ */
\r
2580 #define SCU_CLK_CGATSET0_VADC_Pos 0 /*!< SCU_CLK CGATSET0: VADC Position */
\r
2581 #define SCU_CLK_CGATSET0_VADC_Msk (0x01UL << SCU_CLK_CGATSET0_VADC_Pos) /*!< SCU_CLK CGATSET0: VADC Mask */
\r
2582 #define SCU_CLK_CGATSET0_CCU40_Pos 2 /*!< SCU_CLK CGATSET0: CCU40 Position */
\r
2583 #define SCU_CLK_CGATSET0_CCU40_Msk (0x01UL << SCU_CLK_CGATSET0_CCU40_Pos) /*!< SCU_CLK CGATSET0: CCU40 Mask */
\r
2584 #define SCU_CLK_CGATSET0_USIC0_Pos 3 /*!< SCU_CLK CGATSET0: USIC0 Position */
\r
2585 #define SCU_CLK_CGATSET0_USIC0_Msk (0x01UL << SCU_CLK_CGATSET0_USIC0_Pos) /*!< SCU_CLK CGATSET0: USIC0 Mask */
\r
2586 #define SCU_CLK_CGATSET0_WDT_Pos 9 /*!< SCU_CLK CGATSET0: WDT Position */
\r
2587 #define SCU_CLK_CGATSET0_WDT_Msk (0x01UL << SCU_CLK_CGATSET0_WDT_Pos) /*!< SCU_CLK CGATSET0: WDT Mask */
\r
2588 #define SCU_CLK_CGATSET0_RTC_Pos 10 /*!< SCU_CLK CGATSET0: RTC Position */
\r
2589 #define SCU_CLK_CGATSET0_RTC_Msk (0x01UL << SCU_CLK_CGATSET0_RTC_Pos) /*!< SCU_CLK CGATSET0: RTC Mask */
\r
2591 /* ------------------------------ SCU_CLK_CGATCLR0 ------------------------------ */
\r
2592 #define SCU_CLK_CGATCLR0_VADC_Pos 0 /*!< SCU_CLK CGATCLR0: VADC Position */
\r
2593 #define SCU_CLK_CGATCLR0_VADC_Msk (0x01UL << SCU_CLK_CGATCLR0_VADC_Pos) /*!< SCU_CLK CGATCLR0: VADC Mask */
\r
2594 #define SCU_CLK_CGATCLR0_CCU40_Pos 2 /*!< SCU_CLK CGATCLR0: CCU40 Position */
\r
2595 #define SCU_CLK_CGATCLR0_CCU40_Msk (0x01UL << SCU_CLK_CGATCLR0_CCU40_Pos) /*!< SCU_CLK CGATCLR0: CCU40 Mask */
\r
2596 #define SCU_CLK_CGATCLR0_USIC0_Pos 3 /*!< SCU_CLK CGATCLR0: USIC0 Position */
\r
2597 #define SCU_CLK_CGATCLR0_USIC0_Msk (0x01UL << SCU_CLK_CGATCLR0_USIC0_Pos) /*!< SCU_CLK CGATCLR0: USIC0 Mask */
\r
2598 #define SCU_CLK_CGATCLR0_WDT_Pos 9 /*!< SCU_CLK CGATCLR0: WDT Position */
\r
2599 #define SCU_CLK_CGATCLR0_WDT_Msk (0x01UL << SCU_CLK_CGATCLR0_WDT_Pos) /*!< SCU_CLK CGATCLR0: WDT Mask */
\r
2600 #define SCU_CLK_CGATCLR0_RTC_Pos 10 /*!< SCU_CLK CGATCLR0: RTC Position */
\r
2601 #define SCU_CLK_CGATCLR0_RTC_Msk (0x01UL << SCU_CLK_CGATCLR0_RTC_Pos) /*!< SCU_CLK CGATCLR0: RTC Mask */
\r
2603 /* ------------------------------- SCU_CLK_OSCCSR ------------------------------- */
\r
2604 #define SCU_CLK_OSCCSR_OSC2L_Pos 0 /*!< SCU_CLK OSCCSR: OSC2L Position */
\r
2605 #define SCU_CLK_OSCCSR_OSC2L_Msk (0x01UL << SCU_CLK_OSCCSR_OSC2L_Pos) /*!< SCU_CLK OSCCSR: OSC2L Mask */
\r
2606 #define SCU_CLK_OSCCSR_OSC2H_Pos 1 /*!< SCU_CLK OSCCSR: OSC2H Position */
\r
2607 #define SCU_CLK_OSCCSR_OSC2H_Msk (0x01UL << SCU_CLK_OSCCSR_OSC2H_Pos) /*!< SCU_CLK OSCCSR: OSC2H Mask */
\r
2608 #define SCU_CLK_OSCCSR_OWDRES_Pos 16 /*!< SCU_CLK OSCCSR: OWDRES Position */
\r
2609 #define SCU_CLK_OSCCSR_OWDRES_Msk (0x01UL << SCU_CLK_OSCCSR_OWDRES_Pos) /*!< SCU_CLK OSCCSR: OWDRES Mask */
\r
2610 #define SCU_CLK_OSCCSR_OWDEN_Pos 17 /*!< SCU_CLK OSCCSR: OWDEN Position */
\r
2611 #define SCU_CLK_OSCCSR_OWDEN_Msk (0x01UL << SCU_CLK_OSCCSR_OWDEN_Pos) /*!< SCU_CLK OSCCSR: OWDEN Mask */
\r
2614 /* ================================================================================ */
\r
2615 /* ================ struct 'SCU_RESET' Position & Mask ================ */
\r
2616 /* ================================================================================ */
\r
2619 /* ------------------------------ SCU_RESET_RSTSTAT ----------------------------- */
\r
2620 #define SCU_RESET_RSTSTAT_RSTSTAT_Pos 0 /*!< SCU_RESET RSTSTAT: RSTSTAT Position */
\r
2621 #define SCU_RESET_RSTSTAT_RSTSTAT_Msk (0x000003ffUL << SCU_RESET_RSTSTAT_RSTSTAT_Pos) /*!< SCU_RESET RSTSTAT: RSTSTAT Mask */
\r
2622 #define SCU_RESET_RSTSTAT_LCKEN_Pos 10 /*!< SCU_RESET RSTSTAT: LCKEN Position */
\r
2623 #define SCU_RESET_RSTSTAT_LCKEN_Msk (0x01UL << SCU_RESET_RSTSTAT_LCKEN_Pos) /*!< SCU_RESET RSTSTAT: LCKEN Mask */
\r
2625 /* ------------------------------ SCU_RESET_RSTSET ------------------------------ */
\r
2626 #define SCU_RESET_RSTSET_LCKEN_Pos 10 /*!< SCU_RESET RSTSET: LCKEN Position */
\r
2627 #define SCU_RESET_RSTSET_LCKEN_Msk (0x01UL << SCU_RESET_RSTSET_LCKEN_Pos) /*!< SCU_RESET RSTSET: LCKEN Mask */
\r
2629 /* ------------------------------ SCU_RESET_RSTCLR ------------------------------ */
\r
2630 #define SCU_RESET_RSTCLR_RSCLR_Pos 0 /*!< SCU_RESET RSTCLR: RSCLR Position */
\r
2631 #define SCU_RESET_RSTCLR_RSCLR_Msk (0x01UL << SCU_RESET_RSTCLR_RSCLR_Pos) /*!< SCU_RESET RSTCLR: RSCLR Mask */
\r
2632 #define SCU_RESET_RSTCLR_LCKEN_Pos 10 /*!< SCU_RESET RSTCLR: LCKEN Position */
\r
2633 #define SCU_RESET_RSTCLR_LCKEN_Msk (0x01UL << SCU_RESET_RSTCLR_LCKEN_Pos) /*!< SCU_RESET RSTCLR: LCKEN Mask */
\r
2635 /* ------------------------------ SCU_RESET_RSTCON ------------------------------ */
\r
2636 #define SCU_RESET_RSTCON_ECCRSTEN_Pos 0 /*!< SCU_RESET RSTCON: ECCRSTEN Position */
\r
2637 #define SCU_RESET_RSTCON_ECCRSTEN_Msk (0x01UL << SCU_RESET_RSTCON_ECCRSTEN_Pos) /*!< SCU_RESET RSTCON: ECCRSTEN Mask */
\r
2638 #define SCU_RESET_RSTCON_LOCRSTEN_Pos 1 /*!< SCU_RESET RSTCON: LOCRSTEN Position */
\r
2639 #define SCU_RESET_RSTCON_LOCRSTEN_Msk (0x01UL << SCU_RESET_RSTCON_LOCRSTEN_Pos) /*!< SCU_RESET RSTCON: LOCRSTEN Mask */
\r
2640 #define SCU_RESET_RSTCON_SPERSTEN_Pos 2 /*!< SCU_RESET RSTCON: SPERSTEN Position */
\r
2641 #define SCU_RESET_RSTCON_SPERSTEN_Msk (0x01UL << SCU_RESET_RSTCON_SPERSTEN_Pos) /*!< SCU_RESET RSTCON: SPERSTEN Mask */
\r
2642 #define SCU_RESET_RSTCON_U0PERSTEN_Pos 3 /*!< SCU_RESET RSTCON: U0PERSTEN Position */
\r
2643 #define SCU_RESET_RSTCON_U0PERSTEN_Msk (0x01UL << SCU_RESET_RSTCON_U0PERSTEN_Pos) /*!< SCU_RESET RSTCON: U0PERSTEN Mask */
\r
2644 #define SCU_RESET_RSTCON_MRSTEN_Pos 16 /*!< SCU_RESET RSTCON: MRSTEN Position */
\r
2645 #define SCU_RESET_RSTCON_MRSTEN_Msk (0x01UL << SCU_RESET_RSTCON_MRSTEN_Pos) /*!< SCU_RESET RSTCON: MRSTEN Mask */
\r
2648 /* ================================================================================ */
\r
2649 /* ================ struct 'SCU_ANALOG' Position & Mask ================ */
\r
2650 /* ================================================================================ */
\r
2653 /* ----------------------------- SCU_ANALOG_ANAVDEL ----------------------------- */
\r
2654 #define SCU_ANALOG_ANAVDEL_VDEL_SELECT_Pos 0 /*!< SCU_ANALOG ANAVDEL: VDEL_SELECT Position */
\r
2655 #define SCU_ANALOG_ANAVDEL_VDEL_SELECT_Msk (0x03UL << SCU_ANALOG_ANAVDEL_VDEL_SELECT_Pos) /*!< SCU_ANALOG ANAVDEL: VDEL_SELECT Mask */
\r
2656 #define SCU_ANALOG_ANAVDEL_VDEL_TIM_ADJ_Pos 2 /*!< SCU_ANALOG ANAVDEL: VDEL_TIM_ADJ Position */
\r
2657 #define SCU_ANALOG_ANAVDEL_VDEL_TIM_ADJ_Msk (0x03UL << SCU_ANALOG_ANAVDEL_VDEL_TIM_ADJ_Pos) /*!< SCU_ANALOG ANAVDEL: VDEL_TIM_ADJ Mask */
\r
2658 #define SCU_ANALOG_ANAVDEL_VDEL_EN_Pos 4 /*!< SCU_ANALOG ANAVDEL: VDEL_EN Position */
\r
2659 #define SCU_ANALOG_ANAVDEL_VDEL_EN_Msk (0x01UL << SCU_ANALOG_ANAVDEL_VDEL_EN_Pos) /*!< SCU_ANALOG ANAVDEL: VDEL_EN Mask */
\r
2662 /* ================================================================================ */
\r
2663 /* ================ Group 'CCU4' Position & Mask ================ */
\r
2664 /* ================================================================================ */
\r
2667 /* --------------------------------- CCU4_GCTRL --------------------------------- */
\r
2668 #define CCU4_GCTRL_PRBC_Pos 0 /*!< CCU4 GCTRL: PRBC Position */
\r
2669 #define CCU4_GCTRL_PRBC_Msk (0x07UL << CCU4_GCTRL_PRBC_Pos) /*!< CCU4 GCTRL: PRBC Mask */
\r
2670 #define CCU4_GCTRL_PCIS_Pos 4 /*!< CCU4 GCTRL: PCIS Position */
\r
2671 #define CCU4_GCTRL_PCIS_Msk (0x03UL << CCU4_GCTRL_PCIS_Pos) /*!< CCU4 GCTRL: PCIS Mask */
\r
2672 #define CCU4_GCTRL_SUSCFG_Pos 8 /*!< CCU4 GCTRL: SUSCFG Position */
\r
2673 #define CCU4_GCTRL_SUSCFG_Msk (0x03UL << CCU4_GCTRL_SUSCFG_Pos) /*!< CCU4 GCTRL: SUSCFG Mask */
\r
2674 #define CCU4_GCTRL_MSE0_Pos 10 /*!< CCU4 GCTRL: MSE0 Position */
\r
2675 #define CCU4_GCTRL_MSE0_Msk (0x01UL << CCU4_GCTRL_MSE0_Pos) /*!< CCU4 GCTRL: MSE0 Mask */
\r
2676 #define CCU4_GCTRL_MSE1_Pos 11 /*!< CCU4 GCTRL: MSE1 Position */
\r
2677 #define CCU4_GCTRL_MSE1_Msk (0x01UL << CCU4_GCTRL_MSE1_Pos) /*!< CCU4 GCTRL: MSE1 Mask */
\r
2678 #define CCU4_GCTRL_MSE2_Pos 12 /*!< CCU4 GCTRL: MSE2 Position */
\r
2679 #define CCU4_GCTRL_MSE2_Msk (0x01UL << CCU4_GCTRL_MSE2_Pos) /*!< CCU4 GCTRL: MSE2 Mask */
\r
2680 #define CCU4_GCTRL_MSE3_Pos 13 /*!< CCU4 GCTRL: MSE3 Position */
\r
2681 #define CCU4_GCTRL_MSE3_Msk (0x01UL << CCU4_GCTRL_MSE3_Pos) /*!< CCU4 GCTRL: MSE3 Mask */
\r
2682 #define CCU4_GCTRL_MSDE_Pos 14 /*!< CCU4 GCTRL: MSDE Position */
\r
2683 #define CCU4_GCTRL_MSDE_Msk (0x03UL << CCU4_GCTRL_MSDE_Pos) /*!< CCU4 GCTRL: MSDE Mask */
\r
2685 /* --------------------------------- CCU4_GSTAT --------------------------------- */
\r
2686 #define CCU4_GSTAT_S0I_Pos 0 /*!< CCU4 GSTAT: S0I Position */
\r
2687 #define CCU4_GSTAT_S0I_Msk (0x01UL << CCU4_GSTAT_S0I_Pos) /*!< CCU4 GSTAT: S0I Mask */
\r
2688 #define CCU4_GSTAT_S1I_Pos 1 /*!< CCU4 GSTAT: S1I Position */
\r
2689 #define CCU4_GSTAT_S1I_Msk (0x01UL << CCU4_GSTAT_S1I_Pos) /*!< CCU4 GSTAT: S1I Mask */
\r
2690 #define CCU4_GSTAT_S2I_Pos 2 /*!< CCU4 GSTAT: S2I Position */
\r
2691 #define CCU4_GSTAT_S2I_Msk (0x01UL << CCU4_GSTAT_S2I_Pos) /*!< CCU4 GSTAT: S2I Mask */
\r
2692 #define CCU4_GSTAT_S3I_Pos 3 /*!< CCU4 GSTAT: S3I Position */
\r
2693 #define CCU4_GSTAT_S3I_Msk (0x01UL << CCU4_GSTAT_S3I_Pos) /*!< CCU4 GSTAT: S3I Mask */
\r
2694 #define CCU4_GSTAT_PRB_Pos 8 /*!< CCU4 GSTAT: PRB Position */
\r
2695 #define CCU4_GSTAT_PRB_Msk (0x01UL << CCU4_GSTAT_PRB_Pos) /*!< CCU4 GSTAT: PRB Mask */
\r
2697 /* --------------------------------- CCU4_GIDLS --------------------------------- */
\r
2698 #define CCU4_GIDLS_SS0I_Pos 0 /*!< CCU4 GIDLS: SS0I Position */
\r
2699 #define CCU4_GIDLS_SS0I_Msk (0x01UL << CCU4_GIDLS_SS0I_Pos) /*!< CCU4 GIDLS: SS0I Mask */
\r
2700 #define CCU4_GIDLS_SS1I_Pos 1 /*!< CCU4 GIDLS: SS1I Position */
\r
2701 #define CCU4_GIDLS_SS1I_Msk (0x01UL << CCU4_GIDLS_SS1I_Pos) /*!< CCU4 GIDLS: SS1I Mask */
\r
2702 #define CCU4_GIDLS_SS2I_Pos 2 /*!< CCU4 GIDLS: SS2I Position */
\r
2703 #define CCU4_GIDLS_SS2I_Msk (0x01UL << CCU4_GIDLS_SS2I_Pos) /*!< CCU4 GIDLS: SS2I Mask */
\r
2704 #define CCU4_GIDLS_SS3I_Pos 3 /*!< CCU4 GIDLS: SS3I Position */
\r
2705 #define CCU4_GIDLS_SS3I_Msk (0x01UL << CCU4_GIDLS_SS3I_Pos) /*!< CCU4 GIDLS: SS3I Mask */
\r
2706 #define CCU4_GIDLS_CPRB_Pos 8 /*!< CCU4 GIDLS: CPRB Position */
\r
2707 #define CCU4_GIDLS_CPRB_Msk (0x01UL << CCU4_GIDLS_CPRB_Pos) /*!< CCU4 GIDLS: CPRB Mask */
\r
2708 #define CCU4_GIDLS_PSIC_Pos 9 /*!< CCU4 GIDLS: PSIC Position */
\r
2709 #define CCU4_GIDLS_PSIC_Msk (0x01UL << CCU4_GIDLS_PSIC_Pos) /*!< CCU4 GIDLS: PSIC Mask */
\r
2711 /* --------------------------------- CCU4_GIDLC --------------------------------- */
\r
2712 #define CCU4_GIDLC_CS0I_Pos 0 /*!< CCU4 GIDLC: CS0I Position */
\r
2713 #define CCU4_GIDLC_CS0I_Msk (0x01UL << CCU4_GIDLC_CS0I_Pos) /*!< CCU4 GIDLC: CS0I Mask */
\r
2714 #define CCU4_GIDLC_CS1I_Pos 1 /*!< CCU4 GIDLC: CS1I Position */
\r
2715 #define CCU4_GIDLC_CS1I_Msk (0x01UL << CCU4_GIDLC_CS1I_Pos) /*!< CCU4 GIDLC: CS1I Mask */
\r
2716 #define CCU4_GIDLC_CS2I_Pos 2 /*!< CCU4 GIDLC: CS2I Position */
\r
2717 #define CCU4_GIDLC_CS2I_Msk (0x01UL << CCU4_GIDLC_CS2I_Pos) /*!< CCU4 GIDLC: CS2I Mask */
\r
2718 #define CCU4_GIDLC_CS3I_Pos 3 /*!< CCU4 GIDLC: CS3I Position */
\r
2719 #define CCU4_GIDLC_CS3I_Msk (0x01UL << CCU4_GIDLC_CS3I_Pos) /*!< CCU4 GIDLC: CS3I Mask */
\r
2720 #define CCU4_GIDLC_SPRB_Pos 8 /*!< CCU4 GIDLC: SPRB Position */
\r
2721 #define CCU4_GIDLC_SPRB_Msk (0x01UL << CCU4_GIDLC_SPRB_Pos) /*!< CCU4 GIDLC: SPRB Mask */
\r
2723 /* ---------------------------------- CCU4_GCSS --------------------------------- */
\r
2724 #define CCU4_GCSS_S0SE_Pos 0 /*!< CCU4 GCSS: S0SE Position */
\r
2725 #define CCU4_GCSS_S0SE_Msk (0x01UL << CCU4_GCSS_S0SE_Pos) /*!< CCU4 GCSS: S0SE Mask */
\r
2726 #define CCU4_GCSS_S0DSE_Pos 1 /*!< CCU4 GCSS: S0DSE Position */
\r
2727 #define CCU4_GCSS_S0DSE_Msk (0x01UL << CCU4_GCSS_S0DSE_Pos) /*!< CCU4 GCSS: S0DSE Mask */
\r
2728 #define CCU4_GCSS_S0PSE_Pos 2 /*!< CCU4 GCSS: S0PSE Position */
\r
2729 #define CCU4_GCSS_S0PSE_Msk (0x01UL << CCU4_GCSS_S0PSE_Pos) /*!< CCU4 GCSS: S0PSE Mask */
\r
2730 #define CCU4_GCSS_S1SE_Pos 4 /*!< CCU4 GCSS: S1SE Position */
\r
2731 #define CCU4_GCSS_S1SE_Msk (0x01UL << CCU4_GCSS_S1SE_Pos) /*!< CCU4 GCSS: S1SE Mask */
\r
2732 #define CCU4_GCSS_S1DSE_Pos 5 /*!< CCU4 GCSS: S1DSE Position */
\r
2733 #define CCU4_GCSS_S1DSE_Msk (0x01UL << CCU4_GCSS_S1DSE_Pos) /*!< CCU4 GCSS: S1DSE Mask */
\r
2734 #define CCU4_GCSS_S1PSE_Pos 6 /*!< CCU4 GCSS: S1PSE Position */
\r
2735 #define CCU4_GCSS_S1PSE_Msk (0x01UL << CCU4_GCSS_S1PSE_Pos) /*!< CCU4 GCSS: S1PSE Mask */
\r
2736 #define CCU4_GCSS_S2SE_Pos 8 /*!< CCU4 GCSS: S2SE Position */
\r
2737 #define CCU4_GCSS_S2SE_Msk (0x01UL << CCU4_GCSS_S2SE_Pos) /*!< CCU4 GCSS: S2SE Mask */
\r
2738 #define CCU4_GCSS_S2DSE_Pos 9 /*!< CCU4 GCSS: S2DSE Position */
\r
2739 #define CCU4_GCSS_S2DSE_Msk (0x01UL << CCU4_GCSS_S2DSE_Pos) /*!< CCU4 GCSS: S2DSE Mask */
\r
2740 #define CCU4_GCSS_S2PSE_Pos 10 /*!< CCU4 GCSS: S2PSE Position */
\r
2741 #define CCU4_GCSS_S2PSE_Msk (0x01UL << CCU4_GCSS_S2PSE_Pos) /*!< CCU4 GCSS: S2PSE Mask */
\r
2742 #define CCU4_GCSS_S3SE_Pos 12 /*!< CCU4 GCSS: S3SE Position */
\r
2743 #define CCU4_GCSS_S3SE_Msk (0x01UL << CCU4_GCSS_S3SE_Pos) /*!< CCU4 GCSS: S3SE Mask */
\r
2744 #define CCU4_GCSS_S3DSE_Pos 13 /*!< CCU4 GCSS: S3DSE Position */
\r
2745 #define CCU4_GCSS_S3DSE_Msk (0x01UL << CCU4_GCSS_S3DSE_Pos) /*!< CCU4 GCSS: S3DSE Mask */
\r
2746 #define CCU4_GCSS_S3PSE_Pos 14 /*!< CCU4 GCSS: S3PSE Position */
\r
2747 #define CCU4_GCSS_S3PSE_Msk (0x01UL << CCU4_GCSS_S3PSE_Pos) /*!< CCU4 GCSS: S3PSE Mask */
\r
2748 #define CCU4_GCSS_S0STS_Pos 16 /*!< CCU4 GCSS: S0STS Position */
\r
2749 #define CCU4_GCSS_S0STS_Msk (0x01UL << CCU4_GCSS_S0STS_Pos) /*!< CCU4 GCSS: S0STS Mask */
\r
2750 #define CCU4_GCSS_S1STS_Pos 17 /*!< CCU4 GCSS: S1STS Position */
\r
2751 #define CCU4_GCSS_S1STS_Msk (0x01UL << CCU4_GCSS_S1STS_Pos) /*!< CCU4 GCSS: S1STS Mask */
\r
2752 #define CCU4_GCSS_S2STS_Pos 18 /*!< CCU4 GCSS: S2STS Position */
\r
2753 #define CCU4_GCSS_S2STS_Msk (0x01UL << CCU4_GCSS_S2STS_Pos) /*!< CCU4 GCSS: S2STS Mask */
\r
2754 #define CCU4_GCSS_S3STS_Pos 19 /*!< CCU4 GCSS: S3STS Position */
\r
2755 #define CCU4_GCSS_S3STS_Msk (0x01UL << CCU4_GCSS_S3STS_Pos) /*!< CCU4 GCSS: S3STS Mask */
\r
2757 /* ---------------------------------- CCU4_GCSC --------------------------------- */
\r
2758 #define CCU4_GCSC_S0SC_Pos 0 /*!< CCU4 GCSC: S0SC Position */
\r
2759 #define CCU4_GCSC_S0SC_Msk (0x01UL << CCU4_GCSC_S0SC_Pos) /*!< CCU4 GCSC: S0SC Mask */
\r
2760 #define CCU4_GCSC_S0DSC_Pos 1 /*!< CCU4 GCSC: S0DSC Position */
\r
2761 #define CCU4_GCSC_S0DSC_Msk (0x01UL << CCU4_GCSC_S0DSC_Pos) /*!< CCU4 GCSC: S0DSC Mask */
\r
2762 #define CCU4_GCSC_S0PSC_Pos 2 /*!< CCU4 GCSC: S0PSC Position */
\r
2763 #define CCU4_GCSC_S0PSC_Msk (0x01UL << CCU4_GCSC_S0PSC_Pos) /*!< CCU4 GCSC: S0PSC Mask */
\r
2764 #define CCU4_GCSC_S1SC_Pos 4 /*!< CCU4 GCSC: S1SC Position */
\r
2765 #define CCU4_GCSC_S1SC_Msk (0x01UL << CCU4_GCSC_S1SC_Pos) /*!< CCU4 GCSC: S1SC Mask */
\r
2766 #define CCU4_GCSC_S1DSC_Pos 5 /*!< CCU4 GCSC: S1DSC Position */
\r
2767 #define CCU4_GCSC_S1DSC_Msk (0x01UL << CCU4_GCSC_S1DSC_Pos) /*!< CCU4 GCSC: S1DSC Mask */
\r
2768 #define CCU4_GCSC_S1PSC_Pos 6 /*!< CCU4 GCSC: S1PSC Position */
\r
2769 #define CCU4_GCSC_S1PSC_Msk (0x01UL << CCU4_GCSC_S1PSC_Pos) /*!< CCU4 GCSC: S1PSC Mask */
\r
2770 #define CCU4_GCSC_S2SC_Pos 8 /*!< CCU4 GCSC: S2SC Position */
\r
2771 #define CCU4_GCSC_S2SC_Msk (0x01UL << CCU4_GCSC_S2SC_Pos) /*!< CCU4 GCSC: S2SC Mask */
\r
2772 #define CCU4_GCSC_S2DSC_Pos 9 /*!< CCU4 GCSC: S2DSC Position */
\r
2773 #define CCU4_GCSC_S2DSC_Msk (0x01UL << CCU4_GCSC_S2DSC_Pos) /*!< CCU4 GCSC: S2DSC Mask */
\r
2774 #define CCU4_GCSC_S2PSC_Pos 10 /*!< CCU4 GCSC: S2PSC Position */
\r
2775 #define CCU4_GCSC_S2PSC_Msk (0x01UL << CCU4_GCSC_S2PSC_Pos) /*!< CCU4 GCSC: S2PSC Mask */
\r
2776 #define CCU4_GCSC_S3SC_Pos 12 /*!< CCU4 GCSC: S3SC Position */
\r
2777 #define CCU4_GCSC_S3SC_Msk (0x01UL << CCU4_GCSC_S3SC_Pos) /*!< CCU4 GCSC: S3SC Mask */
\r
2778 #define CCU4_GCSC_S3DSC_Pos 13 /*!< CCU4 GCSC: S3DSC Position */
\r
2779 #define CCU4_GCSC_S3DSC_Msk (0x01UL << CCU4_GCSC_S3DSC_Pos) /*!< CCU4 GCSC: S3DSC Mask */
\r
2780 #define CCU4_GCSC_S3PSC_Pos 14 /*!< CCU4 GCSC: S3PSC Position */
\r
2781 #define CCU4_GCSC_S3PSC_Msk (0x01UL << CCU4_GCSC_S3PSC_Pos) /*!< CCU4 GCSC: S3PSC Mask */
\r
2782 #define CCU4_GCSC_S0STC_Pos 16 /*!< CCU4 GCSC: S0STC Position */
\r
2783 #define CCU4_GCSC_S0STC_Msk (0x01UL << CCU4_GCSC_S0STC_Pos) /*!< CCU4 GCSC: S0STC Mask */
\r
2784 #define CCU4_GCSC_S1STC_Pos 17 /*!< CCU4 GCSC: S1STC Position */
\r
2785 #define CCU4_GCSC_S1STC_Msk (0x01UL << CCU4_GCSC_S1STC_Pos) /*!< CCU4 GCSC: S1STC Mask */
\r
2786 #define CCU4_GCSC_S2STC_Pos 18 /*!< CCU4 GCSC: S2STC Position */
\r
2787 #define CCU4_GCSC_S2STC_Msk (0x01UL << CCU4_GCSC_S2STC_Pos) /*!< CCU4 GCSC: S2STC Mask */
\r
2788 #define CCU4_GCSC_S3STC_Pos 19 /*!< CCU4 GCSC: S3STC Position */
\r
2789 #define CCU4_GCSC_S3STC_Msk (0x01UL << CCU4_GCSC_S3STC_Pos) /*!< CCU4 GCSC: S3STC Mask */
\r
2791 /* ---------------------------------- CCU4_GCST --------------------------------- */
\r
2792 #define CCU4_GCST_S0SS_Pos 0 /*!< CCU4 GCST: S0SS Position */
\r
2793 #define CCU4_GCST_S0SS_Msk (0x01UL << CCU4_GCST_S0SS_Pos) /*!< CCU4 GCST: S0SS Mask */
\r
2794 #define CCU4_GCST_S0DSS_Pos 1 /*!< CCU4 GCST: S0DSS Position */
\r
2795 #define CCU4_GCST_S0DSS_Msk (0x01UL << CCU4_GCST_S0DSS_Pos) /*!< CCU4 GCST: S0DSS Mask */
\r
2796 #define CCU4_GCST_S0PSS_Pos 2 /*!< CCU4 GCST: S0PSS Position */
\r
2797 #define CCU4_GCST_S0PSS_Msk (0x01UL << CCU4_GCST_S0PSS_Pos) /*!< CCU4 GCST: S0PSS Mask */
\r
2798 #define CCU4_GCST_S1SS_Pos 4 /*!< CCU4 GCST: S1SS Position */
\r
2799 #define CCU4_GCST_S1SS_Msk (0x01UL << CCU4_GCST_S1SS_Pos) /*!< CCU4 GCST: S1SS Mask */
\r
2800 #define CCU4_GCST_S1DSS_Pos 5 /*!< CCU4 GCST: S1DSS Position */
\r
2801 #define CCU4_GCST_S1DSS_Msk (0x01UL << CCU4_GCST_S1DSS_Pos) /*!< CCU4 GCST: S1DSS Mask */
\r
2802 #define CCU4_GCST_S1PSS_Pos 6 /*!< CCU4 GCST: S1PSS Position */
\r
2803 #define CCU4_GCST_S1PSS_Msk (0x01UL << CCU4_GCST_S1PSS_Pos) /*!< CCU4 GCST: S1PSS Mask */
\r
2804 #define CCU4_GCST_S2SS_Pos 8 /*!< CCU4 GCST: S2SS Position */
\r
2805 #define CCU4_GCST_S2SS_Msk (0x01UL << CCU4_GCST_S2SS_Pos) /*!< CCU4 GCST: S2SS Mask */
\r
2806 #define CCU4_GCST_S2DSS_Pos 9 /*!< CCU4 GCST: S2DSS Position */
\r
2807 #define CCU4_GCST_S2DSS_Msk (0x01UL << CCU4_GCST_S2DSS_Pos) /*!< CCU4 GCST: S2DSS Mask */
\r
2808 #define CCU4_GCST_S2PSS_Pos 10 /*!< CCU4 GCST: S2PSS Position */
\r
2809 #define CCU4_GCST_S2PSS_Msk (0x01UL << CCU4_GCST_S2PSS_Pos) /*!< CCU4 GCST: S2PSS Mask */
\r
2810 #define CCU4_GCST_S3SS_Pos 12 /*!< CCU4 GCST: S3SS Position */
\r
2811 #define CCU4_GCST_S3SS_Msk (0x01UL << CCU4_GCST_S3SS_Pos) /*!< CCU4 GCST: S3SS Mask */
\r
2812 #define CCU4_GCST_S3DSS_Pos 13 /*!< CCU4 GCST: S3DSS Position */
\r
2813 #define CCU4_GCST_S3DSS_Msk (0x01UL << CCU4_GCST_S3DSS_Pos) /*!< CCU4 GCST: S3DSS Mask */
\r
2814 #define CCU4_GCST_S3PSS_Pos 14 /*!< CCU4 GCST: S3PSS Position */
\r
2815 #define CCU4_GCST_S3PSS_Msk (0x01UL << CCU4_GCST_S3PSS_Pos) /*!< CCU4 GCST: S3PSS Mask */
\r
2816 #define CCU4_GCST_CC40ST_Pos 16 /*!< CCU4 GCST: CC40ST Position */
\r
2817 #define CCU4_GCST_CC40ST_Msk (0x01UL << CCU4_GCST_CC40ST_Pos) /*!< CCU4 GCST: CC40ST Mask */
\r
2818 #define CCU4_GCST_CC41ST_Pos 17 /*!< CCU4 GCST: CC41ST Position */
\r
2819 #define CCU4_GCST_CC41ST_Msk (0x01UL << CCU4_GCST_CC41ST_Pos) /*!< CCU4 GCST: CC41ST Mask */
\r
2820 #define CCU4_GCST_CC42ST_Pos 18 /*!< CCU4 GCST: CC42ST Position */
\r
2821 #define CCU4_GCST_CC42ST_Msk (0x01UL << CCU4_GCST_CC42ST_Pos) /*!< CCU4 GCST: CC42ST Mask */
\r
2822 #define CCU4_GCST_CC43ST_Pos 19 /*!< CCU4 GCST: CC43ST Position */
\r
2823 #define CCU4_GCST_CC43ST_Msk (0x01UL << CCU4_GCST_CC43ST_Pos) /*!< CCU4 GCST: CC43ST Mask */
\r
2825 /* ---------------------------------- CCU4_MIDR --------------------------------- */
\r
2826 #define CCU4_MIDR_MODR_Pos 0 /*!< CCU4 MIDR: MODR Position */
\r
2827 #define CCU4_MIDR_MODR_Msk (0x000000ffUL << CCU4_MIDR_MODR_Pos) /*!< CCU4 MIDR: MODR Mask */
\r
2828 #define CCU4_MIDR_MODT_Pos 8 /*!< CCU4 MIDR: MODT Position */
\r
2829 #define CCU4_MIDR_MODT_Msk (0x000000ffUL << CCU4_MIDR_MODT_Pos) /*!< CCU4 MIDR: MODT Mask */
\r
2830 #define CCU4_MIDR_MODN_Pos 16 /*!< CCU4 MIDR: MODN Position */
\r
2831 #define CCU4_MIDR_MODN_Msk (0x0000ffffUL << CCU4_MIDR_MODN_Pos) /*!< CCU4 MIDR: MODN Mask */
\r
2834 /* ================================================================================ */
\r
2835 /* ================ Group 'CCU4_CC4' Position & Mask ================ */
\r
2836 /* ================================================================================ */
\r
2839 /* -------------------------------- CCU4_CC4_INS -------------------------------- */
\r
2840 #define CCU4_CC4_INS_EV0IS_Pos 0 /*!< CCU4_CC4 INS: EV0IS Position */
\r
2841 #define CCU4_CC4_INS_EV0IS_Msk (0x0fUL << CCU4_CC4_INS_EV0IS_Pos) /*!< CCU4_CC4 INS: EV0IS Mask */
\r
2842 #define CCU4_CC4_INS_EV1IS_Pos 4 /*!< CCU4_CC4 INS: EV1IS Position */
\r
2843 #define CCU4_CC4_INS_EV1IS_Msk (0x0fUL << CCU4_CC4_INS_EV1IS_Pos) /*!< CCU4_CC4 INS: EV1IS Mask */
\r
2844 #define CCU4_CC4_INS_EV2IS_Pos 8 /*!< CCU4_CC4 INS: EV2IS Position */
\r
2845 #define CCU4_CC4_INS_EV2IS_Msk (0x0fUL << CCU4_CC4_INS_EV2IS_Pos) /*!< CCU4_CC4 INS: EV2IS Mask */
\r
2846 #define CCU4_CC4_INS_EV0EM_Pos 16 /*!< CCU4_CC4 INS: EV0EM Position */
\r
2847 #define CCU4_CC4_INS_EV0EM_Msk (0x03UL << CCU4_CC4_INS_EV0EM_Pos) /*!< CCU4_CC4 INS: EV0EM Mask */
\r
2848 #define CCU4_CC4_INS_EV1EM_Pos 18 /*!< CCU4_CC4 INS: EV1EM Position */
\r
2849 #define CCU4_CC4_INS_EV1EM_Msk (0x03UL << CCU4_CC4_INS_EV1EM_Pos) /*!< CCU4_CC4 INS: EV1EM Mask */
\r
2850 #define CCU4_CC4_INS_EV2EM_Pos 20 /*!< CCU4_CC4 INS: EV2EM Position */
\r
2851 #define CCU4_CC4_INS_EV2EM_Msk (0x03UL << CCU4_CC4_INS_EV2EM_Pos) /*!< CCU4_CC4 INS: EV2EM Mask */
\r
2852 #define CCU4_CC4_INS_EV0LM_Pos 22 /*!< CCU4_CC4 INS: EV0LM Position */
\r
2853 #define CCU4_CC4_INS_EV0LM_Msk (0x01UL << CCU4_CC4_INS_EV0LM_Pos) /*!< CCU4_CC4 INS: EV0LM Mask */
\r
2854 #define CCU4_CC4_INS_EV1LM_Pos 23 /*!< CCU4_CC4 INS: EV1LM Position */
\r
2855 #define CCU4_CC4_INS_EV1LM_Msk (0x01UL << CCU4_CC4_INS_EV1LM_Pos) /*!< CCU4_CC4 INS: EV1LM Mask */
\r
2856 #define CCU4_CC4_INS_EV2LM_Pos 24 /*!< CCU4_CC4 INS: EV2LM Position */
\r
2857 #define CCU4_CC4_INS_EV2LM_Msk (0x01UL << CCU4_CC4_INS_EV2LM_Pos) /*!< CCU4_CC4 INS: EV2LM Mask */
\r
2858 #define CCU4_CC4_INS_LPF0M_Pos 25 /*!< CCU4_CC4 INS: LPF0M Position */
\r
2859 #define CCU4_CC4_INS_LPF0M_Msk (0x03UL << CCU4_CC4_INS_LPF0M_Pos) /*!< CCU4_CC4 INS: LPF0M Mask */
\r
2860 #define CCU4_CC4_INS_LPF1M_Pos 27 /*!< CCU4_CC4 INS: LPF1M Position */
\r
2861 #define CCU4_CC4_INS_LPF1M_Msk (0x03UL << CCU4_CC4_INS_LPF1M_Pos) /*!< CCU4_CC4 INS: LPF1M Mask */
\r
2862 #define CCU4_CC4_INS_LPF2M_Pos 29 /*!< CCU4_CC4 INS: LPF2M Position */
\r
2863 #define CCU4_CC4_INS_LPF2M_Msk (0x03UL << CCU4_CC4_INS_LPF2M_Pos) /*!< CCU4_CC4 INS: LPF2M Mask */
\r
2865 /* -------------------------------- CCU4_CC4_CMC -------------------------------- */
\r
2866 #define CCU4_CC4_CMC_STRTS_Pos 0 /*!< CCU4_CC4 CMC: STRTS Position */
\r
2867 #define CCU4_CC4_CMC_STRTS_Msk (0x03UL << CCU4_CC4_CMC_STRTS_Pos) /*!< CCU4_CC4 CMC: STRTS Mask */
\r
2868 #define CCU4_CC4_CMC_ENDS_Pos 2 /*!< CCU4_CC4 CMC: ENDS Position */
\r
2869 #define CCU4_CC4_CMC_ENDS_Msk (0x03UL << CCU4_CC4_CMC_ENDS_Pos) /*!< CCU4_CC4 CMC: ENDS Mask */
\r
2870 #define CCU4_CC4_CMC_CAP0S_Pos 4 /*!< CCU4_CC4 CMC: CAP0S Position */
\r
2871 #define CCU4_CC4_CMC_CAP0S_Msk (0x03UL << CCU4_CC4_CMC_CAP0S_Pos) /*!< CCU4_CC4 CMC: CAP0S Mask */
\r
2872 #define CCU4_CC4_CMC_CAP1S_Pos 6 /*!< CCU4_CC4 CMC: CAP1S Position */
\r
2873 #define CCU4_CC4_CMC_CAP1S_Msk (0x03UL << CCU4_CC4_CMC_CAP1S_Pos) /*!< CCU4_CC4 CMC: CAP1S Mask */
\r
2874 #define CCU4_CC4_CMC_GATES_Pos 8 /*!< CCU4_CC4 CMC: GATES Position */
\r
2875 #define CCU4_CC4_CMC_GATES_Msk (0x03UL << CCU4_CC4_CMC_GATES_Pos) /*!< CCU4_CC4 CMC: GATES Mask */
\r
2876 #define CCU4_CC4_CMC_UDS_Pos 10 /*!< CCU4_CC4 CMC: UDS Position */
\r
2877 #define CCU4_CC4_CMC_UDS_Msk (0x03UL << CCU4_CC4_CMC_UDS_Pos) /*!< CCU4_CC4 CMC: UDS Mask */
\r
2878 #define CCU4_CC4_CMC_LDS_Pos 12 /*!< CCU4_CC4 CMC: LDS Position */
\r
2879 #define CCU4_CC4_CMC_LDS_Msk (0x03UL << CCU4_CC4_CMC_LDS_Pos) /*!< CCU4_CC4 CMC: LDS Mask */
\r
2880 #define CCU4_CC4_CMC_CNTS_Pos 14 /*!< CCU4_CC4 CMC: CNTS Position */
\r
2881 #define CCU4_CC4_CMC_CNTS_Msk (0x03UL << CCU4_CC4_CMC_CNTS_Pos) /*!< CCU4_CC4 CMC: CNTS Mask */
\r
2882 #define CCU4_CC4_CMC_OFS_Pos 16 /*!< CCU4_CC4 CMC: OFS Position */
\r
2883 #define CCU4_CC4_CMC_OFS_Msk (0x01UL << CCU4_CC4_CMC_OFS_Pos) /*!< CCU4_CC4 CMC: OFS Mask */
\r
2884 #define CCU4_CC4_CMC_TS_Pos 17 /*!< CCU4_CC4 CMC: TS Position */
\r
2885 #define CCU4_CC4_CMC_TS_Msk (0x01UL << CCU4_CC4_CMC_TS_Pos) /*!< CCU4_CC4 CMC: TS Mask */
\r
2886 #define CCU4_CC4_CMC_MOS_Pos 18 /*!< CCU4_CC4 CMC: MOS Position */
\r
2887 #define CCU4_CC4_CMC_MOS_Msk (0x03UL << CCU4_CC4_CMC_MOS_Pos) /*!< CCU4_CC4 CMC: MOS Mask */
\r
2888 #define CCU4_CC4_CMC_TCE_Pos 20 /*!< CCU4_CC4 CMC: TCE Position */
\r
2889 #define CCU4_CC4_CMC_TCE_Msk (0x01UL << CCU4_CC4_CMC_TCE_Pos) /*!< CCU4_CC4 CMC: TCE Mask */
\r
2891 /* -------------------------------- CCU4_CC4_TCST ------------------------------- */
\r
2892 #define CCU4_CC4_TCST_TRB_Pos 0 /*!< CCU4_CC4 TCST: TRB Position */
\r
2893 #define CCU4_CC4_TCST_TRB_Msk (0x01UL << CCU4_CC4_TCST_TRB_Pos) /*!< CCU4_CC4 TCST: TRB Mask */
\r
2894 #define CCU4_CC4_TCST_CDIR_Pos 1 /*!< CCU4_CC4 TCST: CDIR Position */
\r
2895 #define CCU4_CC4_TCST_CDIR_Msk (0x01UL << CCU4_CC4_TCST_CDIR_Pos) /*!< CCU4_CC4 TCST: CDIR Mask */
\r
2897 /* ------------------------------- CCU4_CC4_TCSET ------------------------------- */
\r
2898 #define CCU4_CC4_TCSET_TRBS_Pos 0 /*!< CCU4_CC4 TCSET: TRBS Position */
\r
2899 #define CCU4_CC4_TCSET_TRBS_Msk (0x01UL << CCU4_CC4_TCSET_TRBS_Pos) /*!< CCU4_CC4 TCSET: TRBS Mask */
\r
2901 /* ------------------------------- CCU4_CC4_TCCLR ------------------------------- */
\r
2902 #define CCU4_CC4_TCCLR_TRBC_Pos 0 /*!< CCU4_CC4 TCCLR: TRBC Position */
\r
2903 #define CCU4_CC4_TCCLR_TRBC_Msk (0x01UL << CCU4_CC4_TCCLR_TRBC_Pos) /*!< CCU4_CC4 TCCLR: TRBC Mask */
\r
2904 #define CCU4_CC4_TCCLR_TCC_Pos 1 /*!< CCU4_CC4 TCCLR: TCC Position */
\r
2905 #define CCU4_CC4_TCCLR_TCC_Msk (0x01UL << CCU4_CC4_TCCLR_TCC_Pos) /*!< CCU4_CC4 TCCLR: TCC Mask */
\r
2906 #define CCU4_CC4_TCCLR_DITC_Pos 2 /*!< CCU4_CC4 TCCLR: DITC Position */
\r
2907 #define CCU4_CC4_TCCLR_DITC_Msk (0x01UL << CCU4_CC4_TCCLR_DITC_Pos) /*!< CCU4_CC4 TCCLR: DITC Mask */
\r
2909 /* --------------------------------- CCU4_CC4_TC -------------------------------- */
\r
2910 #define CCU4_CC4_TC_TCM_Pos 0 /*!< CCU4_CC4 TC: TCM Position */
\r
2911 #define CCU4_CC4_TC_TCM_Msk (0x01UL << CCU4_CC4_TC_TCM_Pos) /*!< CCU4_CC4 TC: TCM Mask */
\r
2912 #define CCU4_CC4_TC_TSSM_Pos 1 /*!< CCU4_CC4 TC: TSSM Position */
\r
2913 #define CCU4_CC4_TC_TSSM_Msk (0x01UL << CCU4_CC4_TC_TSSM_Pos) /*!< CCU4_CC4 TC: TSSM Mask */
\r
2914 #define CCU4_CC4_TC_CLST_Pos 2 /*!< CCU4_CC4 TC: CLST Position */
\r
2915 #define CCU4_CC4_TC_CLST_Msk (0x01UL << CCU4_CC4_TC_CLST_Pos) /*!< CCU4_CC4 TC: CLST Mask */
\r
2916 #define CCU4_CC4_TC_CMOD_Pos 3 /*!< CCU4_CC4 TC: CMOD Position */
\r
2917 #define CCU4_CC4_TC_CMOD_Msk (0x01UL << CCU4_CC4_TC_CMOD_Pos) /*!< CCU4_CC4 TC: CMOD Mask */
\r
2918 #define CCU4_CC4_TC_ECM_Pos 4 /*!< CCU4_CC4 TC: ECM Position */
\r
2919 #define CCU4_CC4_TC_ECM_Msk (0x01UL << CCU4_CC4_TC_ECM_Pos) /*!< CCU4_CC4 TC: ECM Mask */
\r
2920 #define CCU4_CC4_TC_CAPC_Pos 5 /*!< CCU4_CC4 TC: CAPC Position */
\r
2921 #define CCU4_CC4_TC_CAPC_Msk (0x03UL << CCU4_CC4_TC_CAPC_Pos) /*!< CCU4_CC4 TC: CAPC Mask */
\r
2922 #define CCU4_CC4_TC_ENDM_Pos 8 /*!< CCU4_CC4 TC: ENDM Position */
\r
2923 #define CCU4_CC4_TC_ENDM_Msk (0x03UL << CCU4_CC4_TC_ENDM_Pos) /*!< CCU4_CC4 TC: ENDM Mask */
\r
2924 #define CCU4_CC4_TC_STRM_Pos 10 /*!< CCU4_CC4 TC: STRM Position */
\r
2925 #define CCU4_CC4_TC_STRM_Msk (0x01UL << CCU4_CC4_TC_STRM_Pos) /*!< CCU4_CC4 TC: STRM Mask */
\r
2926 #define CCU4_CC4_TC_SCE_Pos 11 /*!< CCU4_CC4 TC: SCE Position */
\r
2927 #define CCU4_CC4_TC_SCE_Msk (0x01UL << CCU4_CC4_TC_SCE_Pos) /*!< CCU4_CC4 TC: SCE Mask */
\r
2928 #define CCU4_CC4_TC_CCS_Pos 12 /*!< CCU4_CC4 TC: CCS Position */
\r
2929 #define CCU4_CC4_TC_CCS_Msk (0x01UL << CCU4_CC4_TC_CCS_Pos) /*!< CCU4_CC4 TC: CCS Mask */
\r
2930 #define CCU4_CC4_TC_DITHE_Pos 13 /*!< CCU4_CC4 TC: DITHE Position */
\r
2931 #define CCU4_CC4_TC_DITHE_Msk (0x03UL << CCU4_CC4_TC_DITHE_Pos) /*!< CCU4_CC4 TC: DITHE Mask */
\r
2932 #define CCU4_CC4_TC_DIM_Pos 15 /*!< CCU4_CC4 TC: DIM Position */
\r
2933 #define CCU4_CC4_TC_DIM_Msk (0x01UL << CCU4_CC4_TC_DIM_Pos) /*!< CCU4_CC4 TC: DIM Mask */
\r
2934 #define CCU4_CC4_TC_FPE_Pos 16 /*!< CCU4_CC4 TC: FPE Position */
\r
2935 #define CCU4_CC4_TC_FPE_Msk (0x01UL << CCU4_CC4_TC_FPE_Pos) /*!< CCU4_CC4 TC: FPE Mask */
\r
2936 #define CCU4_CC4_TC_TRAPE_Pos 17 /*!< CCU4_CC4 TC: TRAPE Position */
\r
2937 #define CCU4_CC4_TC_TRAPE_Msk (0x01UL << CCU4_CC4_TC_TRAPE_Pos) /*!< CCU4_CC4 TC: TRAPE Mask */
\r
2938 #define CCU4_CC4_TC_TRPSE_Pos 21 /*!< CCU4_CC4 TC: TRPSE Position */
\r
2939 #define CCU4_CC4_TC_TRPSE_Msk (0x01UL << CCU4_CC4_TC_TRPSE_Pos) /*!< CCU4_CC4 TC: TRPSE Mask */
\r
2940 #define CCU4_CC4_TC_TRPSW_Pos 22 /*!< CCU4_CC4 TC: TRPSW Position */
\r
2941 #define CCU4_CC4_TC_TRPSW_Msk (0x01UL << CCU4_CC4_TC_TRPSW_Pos) /*!< CCU4_CC4 TC: TRPSW Mask */
\r
2942 #define CCU4_CC4_TC_EMS_Pos 23 /*!< CCU4_CC4 TC: EMS Position */
\r
2943 #define CCU4_CC4_TC_EMS_Msk (0x01UL << CCU4_CC4_TC_EMS_Pos) /*!< CCU4_CC4 TC: EMS Mask */
\r
2944 #define CCU4_CC4_TC_EMT_Pos 24 /*!< CCU4_CC4 TC: EMT Position */
\r
2945 #define CCU4_CC4_TC_EMT_Msk (0x01UL << CCU4_CC4_TC_EMT_Pos) /*!< CCU4_CC4 TC: EMT Mask */
\r
2946 #define CCU4_CC4_TC_MCME_Pos 25 /*!< CCU4_CC4 TC: MCME Position */
\r
2947 #define CCU4_CC4_TC_MCME_Msk (0x01UL << CCU4_CC4_TC_MCME_Pos) /*!< CCU4_CC4 TC: MCME Mask */
\r
2949 /* -------------------------------- CCU4_CC4_PSL -------------------------------- */
\r
2950 #define CCU4_CC4_PSL_PSL_Pos 0 /*!< CCU4_CC4 PSL: PSL Position */
\r
2951 #define CCU4_CC4_PSL_PSL_Msk (0x01UL << CCU4_CC4_PSL_PSL_Pos) /*!< CCU4_CC4 PSL: PSL Mask */
\r
2953 /* -------------------------------- CCU4_CC4_DIT -------------------------------- */
\r
2954 #define CCU4_CC4_DIT_DCV_Pos 0 /*!< CCU4_CC4 DIT: DCV Position */
\r
2955 #define CCU4_CC4_DIT_DCV_Msk (0x0fUL << CCU4_CC4_DIT_DCV_Pos) /*!< CCU4_CC4 DIT: DCV Mask */
\r
2956 #define CCU4_CC4_DIT_DCNT_Pos 8 /*!< CCU4_CC4 DIT: DCNT Position */
\r
2957 #define CCU4_CC4_DIT_DCNT_Msk (0x0fUL << CCU4_CC4_DIT_DCNT_Pos) /*!< CCU4_CC4 DIT: DCNT Mask */
\r
2959 /* -------------------------------- CCU4_CC4_DITS ------------------------------- */
\r
2960 #define CCU4_CC4_DITS_DCVS_Pos 0 /*!< CCU4_CC4 DITS: DCVS Position */
\r
2961 #define CCU4_CC4_DITS_DCVS_Msk (0x0fUL << CCU4_CC4_DITS_DCVS_Pos) /*!< CCU4_CC4 DITS: DCVS Mask */
\r
2963 /* -------------------------------- CCU4_CC4_PSC -------------------------------- */
\r
2964 #define CCU4_CC4_PSC_PSIV_Pos 0 /*!< CCU4_CC4 PSC: PSIV Position */
\r
2965 #define CCU4_CC4_PSC_PSIV_Msk (0x0fUL << CCU4_CC4_PSC_PSIV_Pos) /*!< CCU4_CC4 PSC: PSIV Mask */
\r
2967 /* -------------------------------- CCU4_CC4_FPC -------------------------------- */
\r
2968 #define CCU4_CC4_FPC_PCMP_Pos 0 /*!< CCU4_CC4 FPC: PCMP Position */
\r
2969 #define CCU4_CC4_FPC_PCMP_Msk (0x0fUL << CCU4_CC4_FPC_PCMP_Pos) /*!< CCU4_CC4 FPC: PCMP Mask */
\r
2970 #define CCU4_CC4_FPC_PVAL_Pos 8 /*!< CCU4_CC4 FPC: PVAL Position */
\r
2971 #define CCU4_CC4_FPC_PVAL_Msk (0x0fUL << CCU4_CC4_FPC_PVAL_Pos) /*!< CCU4_CC4 FPC: PVAL Mask */
\r
2973 /* -------------------------------- CCU4_CC4_FPCS ------------------------------- */
\r
2974 #define CCU4_CC4_FPCS_PCMP_Pos 0 /*!< CCU4_CC4 FPCS: PCMP Position */
\r
2975 #define CCU4_CC4_FPCS_PCMP_Msk (0x0fUL << CCU4_CC4_FPCS_PCMP_Pos) /*!< CCU4_CC4 FPCS: PCMP Mask */
\r
2977 /* --------------------------------- CCU4_CC4_PR -------------------------------- */
\r
2978 #define CCU4_CC4_PR_PR_Pos 0 /*!< CCU4_CC4 PR: PR Position */
\r
2979 #define CCU4_CC4_PR_PR_Msk (0x0000ffffUL << CCU4_CC4_PR_PR_Pos) /*!< CCU4_CC4 PR: PR Mask */
\r
2981 /* -------------------------------- CCU4_CC4_PRS -------------------------------- */
\r
2982 #define CCU4_CC4_PRS_PRS_Pos 0 /*!< CCU4_CC4 PRS: PRS Position */
\r
2983 #define CCU4_CC4_PRS_PRS_Msk (0x0000ffffUL << CCU4_CC4_PRS_PRS_Pos) /*!< CCU4_CC4 PRS: PRS Mask */
\r
2985 /* --------------------------------- CCU4_CC4_CR -------------------------------- */
\r
2986 #define CCU4_CC4_CR_CR_Pos 0 /*!< CCU4_CC4 CR: CR Position */
\r
2987 #define CCU4_CC4_CR_CR_Msk (0x0000ffffUL << CCU4_CC4_CR_CR_Pos) /*!< CCU4_CC4 CR: CR Mask */
\r
2989 /* -------------------------------- CCU4_CC4_CRS -------------------------------- */
\r
2990 #define CCU4_CC4_CRS_CRS_Pos 0 /*!< CCU4_CC4 CRS: CRS Position */
\r
2991 #define CCU4_CC4_CRS_CRS_Msk (0x0000ffffUL << CCU4_CC4_CRS_CRS_Pos) /*!< CCU4_CC4 CRS: CRS Mask */
\r
2993 /* ------------------------------- CCU4_CC4_TIMER ------------------------------- */
\r
2994 #define CCU4_CC4_TIMER_TVAL_Pos 0 /*!< CCU4_CC4 TIMER: TVAL Position */
\r
2995 #define CCU4_CC4_TIMER_TVAL_Msk (0x0000ffffUL << CCU4_CC4_TIMER_TVAL_Pos) /*!< CCU4_CC4 TIMER: TVAL Mask */
\r
2997 /* --------------------------------- CCU4_CC4_CV -------------------------------- */
\r
2998 #define CCU4_CC4_CV_CAPTV_Pos 0 /*!< CCU4_CC4 CV: CAPTV Position */
\r
2999 #define CCU4_CC4_CV_CAPTV_Msk (0x0000ffffUL << CCU4_CC4_CV_CAPTV_Pos) /*!< CCU4_CC4 CV: CAPTV Mask */
\r
3000 #define CCU4_CC4_CV_FPCV_Pos 16 /*!< CCU4_CC4 CV: FPCV Position */
\r
3001 #define CCU4_CC4_CV_FPCV_Msk (0x0fUL << CCU4_CC4_CV_FPCV_Pos) /*!< CCU4_CC4 CV: FPCV Mask */
\r
3002 #define CCU4_CC4_CV_FFL_Pos 20 /*!< CCU4_CC4 CV: FFL Position */
\r
3003 #define CCU4_CC4_CV_FFL_Msk (0x01UL << CCU4_CC4_CV_FFL_Pos) /*!< CCU4_CC4 CV: FFL Mask */
\r
3005 /* -------------------------------- CCU4_CC4_INTS ------------------------------- */
\r
3006 #define CCU4_CC4_INTS_PMUS_Pos 0 /*!< CCU4_CC4 INTS: PMUS Position */
\r
3007 #define CCU4_CC4_INTS_PMUS_Msk (0x01UL << CCU4_CC4_INTS_PMUS_Pos) /*!< CCU4_CC4 INTS: PMUS Mask */
\r
3008 #define CCU4_CC4_INTS_OMDS_Pos 1 /*!< CCU4_CC4 INTS: OMDS Position */
\r
3009 #define CCU4_CC4_INTS_OMDS_Msk (0x01UL << CCU4_CC4_INTS_OMDS_Pos) /*!< CCU4_CC4 INTS: OMDS Mask */
\r
3010 #define CCU4_CC4_INTS_CMUS_Pos 2 /*!< CCU4_CC4 INTS: CMUS Position */
\r
3011 #define CCU4_CC4_INTS_CMUS_Msk (0x01UL << CCU4_CC4_INTS_CMUS_Pos) /*!< CCU4_CC4 INTS: CMUS Mask */
\r
3012 #define CCU4_CC4_INTS_CMDS_Pos 3 /*!< CCU4_CC4 INTS: CMDS Position */
\r
3013 #define CCU4_CC4_INTS_CMDS_Msk (0x01UL << CCU4_CC4_INTS_CMDS_Pos) /*!< CCU4_CC4 INTS: CMDS Mask */
\r
3014 #define CCU4_CC4_INTS_E0AS_Pos 8 /*!< CCU4_CC4 INTS: E0AS Position */
\r
3015 #define CCU4_CC4_INTS_E0AS_Msk (0x01UL << CCU4_CC4_INTS_E0AS_Pos) /*!< CCU4_CC4 INTS: E0AS Mask */
\r
3016 #define CCU4_CC4_INTS_E1AS_Pos 9 /*!< CCU4_CC4 INTS: E1AS Position */
\r
3017 #define CCU4_CC4_INTS_E1AS_Msk (0x01UL << CCU4_CC4_INTS_E1AS_Pos) /*!< CCU4_CC4 INTS: E1AS Mask */
\r
3018 #define CCU4_CC4_INTS_E2AS_Pos 10 /*!< CCU4_CC4 INTS: E2AS Position */
\r
3019 #define CCU4_CC4_INTS_E2AS_Msk (0x01UL << CCU4_CC4_INTS_E2AS_Pos) /*!< CCU4_CC4 INTS: E2AS Mask */
\r
3020 #define CCU4_CC4_INTS_TRPF_Pos 11 /*!< CCU4_CC4 INTS: TRPF Position */
\r
3021 #define CCU4_CC4_INTS_TRPF_Msk (0x01UL << CCU4_CC4_INTS_TRPF_Pos) /*!< CCU4_CC4 INTS: TRPF Mask */
\r
3023 /* -------------------------------- CCU4_CC4_INTE ------------------------------- */
\r
3024 #define CCU4_CC4_INTE_PME_Pos 0 /*!< CCU4_CC4 INTE: PME Position */
\r
3025 #define CCU4_CC4_INTE_PME_Msk (0x01UL << CCU4_CC4_INTE_PME_Pos) /*!< CCU4_CC4 INTE: PME Mask */
\r
3026 #define CCU4_CC4_INTE_OME_Pos 1 /*!< CCU4_CC4 INTE: OME Position */
\r
3027 #define CCU4_CC4_INTE_OME_Msk (0x01UL << CCU4_CC4_INTE_OME_Pos) /*!< CCU4_CC4 INTE: OME Mask */
\r
3028 #define CCU4_CC4_INTE_CMUE_Pos 2 /*!< CCU4_CC4 INTE: CMUE Position */
\r
3029 #define CCU4_CC4_INTE_CMUE_Msk (0x01UL << CCU4_CC4_INTE_CMUE_Pos) /*!< CCU4_CC4 INTE: CMUE Mask */
\r
3030 #define CCU4_CC4_INTE_CMDE_Pos 3 /*!< CCU4_CC4 INTE: CMDE Position */
\r
3031 #define CCU4_CC4_INTE_CMDE_Msk (0x01UL << CCU4_CC4_INTE_CMDE_Pos) /*!< CCU4_CC4 INTE: CMDE Mask */
\r
3032 #define CCU4_CC4_INTE_E0AE_Pos 8 /*!< CCU4_CC4 INTE: E0AE Position */
\r
3033 #define CCU4_CC4_INTE_E0AE_Msk (0x01UL << CCU4_CC4_INTE_E0AE_Pos) /*!< CCU4_CC4 INTE: E0AE Mask */
\r
3034 #define CCU4_CC4_INTE_E1AE_Pos 9 /*!< CCU4_CC4 INTE: E1AE Position */
\r
3035 #define CCU4_CC4_INTE_E1AE_Msk (0x01UL << CCU4_CC4_INTE_E1AE_Pos) /*!< CCU4_CC4 INTE: E1AE Mask */
\r
3036 #define CCU4_CC4_INTE_E2AE_Pos 10 /*!< CCU4_CC4 INTE: E2AE Position */
\r
3037 #define CCU4_CC4_INTE_E2AE_Msk (0x01UL << CCU4_CC4_INTE_E2AE_Pos) /*!< CCU4_CC4 INTE: E2AE Mask */
\r
3039 /* -------------------------------- CCU4_CC4_SRS -------------------------------- */
\r
3040 #define CCU4_CC4_SRS_POSR_Pos 0 /*!< CCU4_CC4 SRS: POSR Position */
\r
3041 #define CCU4_CC4_SRS_POSR_Msk (0x03UL << CCU4_CC4_SRS_POSR_Pos) /*!< CCU4_CC4 SRS: POSR Mask */
\r
3042 #define CCU4_CC4_SRS_CMSR_Pos 2 /*!< CCU4_CC4 SRS: CMSR Position */
\r
3043 #define CCU4_CC4_SRS_CMSR_Msk (0x03UL << CCU4_CC4_SRS_CMSR_Pos) /*!< CCU4_CC4 SRS: CMSR Mask */
\r
3044 #define CCU4_CC4_SRS_E0SR_Pos 8 /*!< CCU4_CC4 SRS: E0SR Position */
\r
3045 #define CCU4_CC4_SRS_E0SR_Msk (0x03UL << CCU4_CC4_SRS_E0SR_Pos) /*!< CCU4_CC4 SRS: E0SR Mask */
\r
3046 #define CCU4_CC4_SRS_E1SR_Pos 10 /*!< CCU4_CC4 SRS: E1SR Position */
\r
3047 #define CCU4_CC4_SRS_E1SR_Msk (0x03UL << CCU4_CC4_SRS_E1SR_Pos) /*!< CCU4_CC4 SRS: E1SR Mask */
\r
3048 #define CCU4_CC4_SRS_E2SR_Pos 12 /*!< CCU4_CC4 SRS: E2SR Position */
\r
3049 #define CCU4_CC4_SRS_E2SR_Msk (0x03UL << CCU4_CC4_SRS_E2SR_Pos) /*!< CCU4_CC4 SRS: E2SR Mask */
\r
3051 /* -------------------------------- CCU4_CC4_SWS -------------------------------- */
\r
3052 #define CCU4_CC4_SWS_SPM_Pos 0 /*!< CCU4_CC4 SWS: SPM Position */
\r
3053 #define CCU4_CC4_SWS_SPM_Msk (0x01UL << CCU4_CC4_SWS_SPM_Pos) /*!< CCU4_CC4 SWS: SPM Mask */
\r
3054 #define CCU4_CC4_SWS_SOM_Pos 1 /*!< CCU4_CC4 SWS: SOM Position */
\r
3055 #define CCU4_CC4_SWS_SOM_Msk (0x01UL << CCU4_CC4_SWS_SOM_Pos) /*!< CCU4_CC4 SWS: SOM Mask */
\r
3056 #define CCU4_CC4_SWS_SCMU_Pos 2 /*!< CCU4_CC4 SWS: SCMU Position */
\r
3057 #define CCU4_CC4_SWS_SCMU_Msk (0x01UL << CCU4_CC4_SWS_SCMU_Pos) /*!< CCU4_CC4 SWS: SCMU Mask */
\r
3058 #define CCU4_CC4_SWS_SCMD_Pos 3 /*!< CCU4_CC4 SWS: SCMD Position */
\r
3059 #define CCU4_CC4_SWS_SCMD_Msk (0x01UL << CCU4_CC4_SWS_SCMD_Pos) /*!< CCU4_CC4 SWS: SCMD Mask */
\r
3060 #define CCU4_CC4_SWS_SE0A_Pos 8 /*!< CCU4_CC4 SWS: SE0A Position */
\r
3061 #define CCU4_CC4_SWS_SE0A_Msk (0x01UL << CCU4_CC4_SWS_SE0A_Pos) /*!< CCU4_CC4 SWS: SE0A Mask */
\r
3062 #define CCU4_CC4_SWS_SE1A_Pos 9 /*!< CCU4_CC4 SWS: SE1A Position */
\r
3063 #define CCU4_CC4_SWS_SE1A_Msk (0x01UL << CCU4_CC4_SWS_SE1A_Pos) /*!< CCU4_CC4 SWS: SE1A Mask */
\r
3064 #define CCU4_CC4_SWS_SE2A_Pos 10 /*!< CCU4_CC4 SWS: SE2A Position */
\r
3065 #define CCU4_CC4_SWS_SE2A_Msk (0x01UL << CCU4_CC4_SWS_SE2A_Pos) /*!< CCU4_CC4 SWS: SE2A Mask */
\r
3066 #define CCU4_CC4_SWS_STRPF_Pos 11 /*!< CCU4_CC4 SWS: STRPF Position */
\r
3067 #define CCU4_CC4_SWS_STRPF_Msk (0x01UL << CCU4_CC4_SWS_STRPF_Pos) /*!< CCU4_CC4 SWS: STRPF Mask */
\r
3069 /* -------------------------------- CCU4_CC4_SWR -------------------------------- */
\r
3070 #define CCU4_CC4_SWR_RPM_Pos 0 /*!< CCU4_CC4 SWR: RPM Position */
\r
3071 #define CCU4_CC4_SWR_RPM_Msk (0x01UL << CCU4_CC4_SWR_RPM_Pos) /*!< CCU4_CC4 SWR: RPM Mask */
\r
3072 #define CCU4_CC4_SWR_ROM_Pos 1 /*!< CCU4_CC4 SWR: ROM Position */
\r
3073 #define CCU4_CC4_SWR_ROM_Msk (0x01UL << CCU4_CC4_SWR_ROM_Pos) /*!< CCU4_CC4 SWR: ROM Mask */
\r
3074 #define CCU4_CC4_SWR_RCMU_Pos 2 /*!< CCU4_CC4 SWR: RCMU Position */
\r
3075 #define CCU4_CC4_SWR_RCMU_Msk (0x01UL << CCU4_CC4_SWR_RCMU_Pos) /*!< CCU4_CC4 SWR: RCMU Mask */
\r
3076 #define CCU4_CC4_SWR_RCMD_Pos 3 /*!< CCU4_CC4 SWR: RCMD Position */
\r
3077 #define CCU4_CC4_SWR_RCMD_Msk (0x01UL << CCU4_CC4_SWR_RCMD_Pos) /*!< CCU4_CC4 SWR: RCMD Mask */
\r
3078 #define CCU4_CC4_SWR_RE0A_Pos 8 /*!< CCU4_CC4 SWR: RE0A Position */
\r
3079 #define CCU4_CC4_SWR_RE0A_Msk (0x01UL << CCU4_CC4_SWR_RE0A_Pos) /*!< CCU4_CC4 SWR: RE0A Mask */
\r
3080 #define CCU4_CC4_SWR_RE1A_Pos 9 /*!< CCU4_CC4 SWR: RE1A Position */
\r
3081 #define CCU4_CC4_SWR_RE1A_Msk (0x01UL << CCU4_CC4_SWR_RE1A_Pos) /*!< CCU4_CC4 SWR: RE1A Mask */
\r
3082 #define CCU4_CC4_SWR_RE2A_Pos 10 /*!< CCU4_CC4 SWR: RE2A Position */
\r
3083 #define CCU4_CC4_SWR_RE2A_Msk (0x01UL << CCU4_CC4_SWR_RE2A_Pos) /*!< CCU4_CC4 SWR: RE2A Mask */
\r
3084 #define CCU4_CC4_SWR_RTRPF_Pos 11 /*!< CCU4_CC4 SWR: RTRPF Position */
\r
3085 #define CCU4_CC4_SWR_RTRPF_Msk (0x01UL << CCU4_CC4_SWR_RTRPF_Pos) /*!< CCU4_CC4 SWR: RTRPF Mask */
\r
3087 /* ------------------------------- CCU4_CC4_ECRD0 ------------------------------- */
\r
3088 #define CCU4_CC4_ECRD0_CAPV_Pos 0 /*!< CCU4_CC4 ECRD0: CAPV Position */
\r
3089 #define CCU4_CC4_ECRD0_CAPV_Msk (0x0000ffffUL << CCU4_CC4_ECRD0_CAPV_Pos) /*!< CCU4_CC4 ECRD0: CAPV Mask */
\r
3090 #define CCU4_CC4_ECRD0_FPCV_Pos 16 /*!< CCU4_CC4 ECRD0: FPCV Position */
\r
3091 #define CCU4_CC4_ECRD0_FPCV_Msk (0x0fUL << CCU4_CC4_ECRD0_FPCV_Pos) /*!< CCU4_CC4 ECRD0: FPCV Mask */
\r
3092 #define CCU4_CC4_ECRD0_SPTR_Pos 20 /*!< CCU4_CC4 ECRD0: SPTR Position */
\r
3093 #define CCU4_CC4_ECRD0_SPTR_Msk (0x03UL << CCU4_CC4_ECRD0_SPTR_Pos) /*!< CCU4_CC4 ECRD0: SPTR Mask */
\r
3094 #define CCU4_CC4_ECRD0_VPTR_Pos 22 /*!< CCU4_CC4 ECRD0: VPTR Position */
\r
3095 #define CCU4_CC4_ECRD0_VPTR_Msk (0x03UL << CCU4_CC4_ECRD0_VPTR_Pos) /*!< CCU4_CC4 ECRD0: VPTR Mask */
\r
3096 #define CCU4_CC4_ECRD0_FFL_Pos 24 /*!< CCU4_CC4 ECRD0: FFL Position */
\r
3097 #define CCU4_CC4_ECRD0_FFL_Msk (0x01UL << CCU4_CC4_ECRD0_FFL_Pos) /*!< CCU4_CC4 ECRD0: FFL Mask */
\r
3098 #define CCU4_CC4_ECRD0_LCV_Pos 25 /*!< CCU4_CC4 ECRD0: LCV Position */
\r
3099 #define CCU4_CC4_ECRD0_LCV_Msk (0x01UL << CCU4_CC4_ECRD0_LCV_Pos) /*!< CCU4_CC4 ECRD0: LCV Mask */
\r
3101 /* ------------------------------- CCU4_CC4_ECRD1 ------------------------------- */
\r
3102 #define CCU4_CC4_ECRD1_CAPV_Pos 0 /*!< CCU4_CC4 ECRD1: CAPV Position */
\r
3103 #define CCU4_CC4_ECRD1_CAPV_Msk (0x0000ffffUL << CCU4_CC4_ECRD1_CAPV_Pos) /*!< CCU4_CC4 ECRD1: CAPV Mask */
\r
3104 #define CCU4_CC4_ECRD1_FPCV_Pos 16 /*!< CCU4_CC4 ECRD1: FPCV Position */
\r
3105 #define CCU4_CC4_ECRD1_FPCV_Msk (0x0fUL << CCU4_CC4_ECRD1_FPCV_Pos) /*!< CCU4_CC4 ECRD1: FPCV Mask */
\r
3106 #define CCU4_CC4_ECRD1_SPTR_Pos 20 /*!< CCU4_CC4 ECRD1: SPTR Position */
\r
3107 #define CCU4_CC4_ECRD1_SPTR_Msk (0x03UL << CCU4_CC4_ECRD1_SPTR_Pos) /*!< CCU4_CC4 ECRD1: SPTR Mask */
\r
3108 #define CCU4_CC4_ECRD1_VPTR_Pos 22 /*!< CCU4_CC4 ECRD1: VPTR Position */
\r
3109 #define CCU4_CC4_ECRD1_VPTR_Msk (0x03UL << CCU4_CC4_ECRD1_VPTR_Pos) /*!< CCU4_CC4 ECRD1: VPTR Mask */
\r
3110 #define CCU4_CC4_ECRD1_FFL_Pos 24 /*!< CCU4_CC4 ECRD1: FFL Position */
\r
3111 #define CCU4_CC4_ECRD1_FFL_Msk (0x01UL << CCU4_CC4_ECRD1_FFL_Pos) /*!< CCU4_CC4 ECRD1: FFL Mask */
\r
3112 #define CCU4_CC4_ECRD1_LCV_Pos 25 /*!< CCU4_CC4 ECRD1: LCV Position */
\r
3113 #define CCU4_CC4_ECRD1_LCV_Msk (0x01UL << CCU4_CC4_ECRD1_LCV_Pos) /*!< CCU4_CC4 ECRD1: LCV Mask */
\r
3116 /* ================================================================================ */
\r
3117 /* ================ Group 'VADC' Position & Mask ================ */
\r
3118 /* ================================================================================ */
\r
3121 /* ---------------------------------- VADC_CLC ---------------------------------- */
\r
3122 #define VADC_CLC_DISR_Pos 0 /*!< VADC CLC: DISR Position */
\r
3123 #define VADC_CLC_DISR_Msk (0x01UL << VADC_CLC_DISR_Pos) /*!< VADC CLC: DISR Mask */
\r
3124 #define VADC_CLC_DISS_Pos 1 /*!< VADC CLC: DISS Position */
\r
3125 #define VADC_CLC_DISS_Msk (0x01UL << VADC_CLC_DISS_Pos) /*!< VADC CLC: DISS Mask */
\r
3126 #define VADC_CLC_EDIS_Pos 3 /*!< VADC CLC: EDIS Position */
\r
3127 #define VADC_CLC_EDIS_Msk (0x01UL << VADC_CLC_EDIS_Pos) /*!< VADC CLC: EDIS Mask */
\r
3129 /* ----------------------------------- VADC_ID ---------------------------------- */
\r
3130 #define VADC_ID_MOD_REV_Pos 0 /*!< VADC ID: MOD_REV Position */
\r
3131 #define VADC_ID_MOD_REV_Msk (0x000000ffUL << VADC_ID_MOD_REV_Pos) /*!< VADC ID: MOD_REV Mask */
\r
3132 #define VADC_ID_MOD_TYPE_Pos 8 /*!< VADC ID: MOD_TYPE Position */
\r
3133 #define VADC_ID_MOD_TYPE_Msk (0x000000ffUL << VADC_ID_MOD_TYPE_Pos) /*!< VADC ID: MOD_TYPE Mask */
\r
3134 #define VADC_ID_MOD_NUMBER_Pos 16 /*!< VADC ID: MOD_NUMBER Position */
\r
3135 #define VADC_ID_MOD_NUMBER_Msk (0x0000ffffUL << VADC_ID_MOD_NUMBER_Pos) /*!< VADC ID: MOD_NUMBER Mask */
\r
3137 /* ---------------------------------- VADC_OCS ---------------------------------- */
\r
3138 #define VADC_OCS_TGS_Pos 0 /*!< VADC OCS: TGS Position */
\r
3139 #define VADC_OCS_TGS_Msk (0x03UL << VADC_OCS_TGS_Pos) /*!< VADC OCS: TGS Mask */
\r
3140 #define VADC_OCS_TGB_Pos 2 /*!< VADC OCS: TGB Position */
\r
3141 #define VADC_OCS_TGB_Msk (0x01UL << VADC_OCS_TGB_Pos) /*!< VADC OCS: TGB Mask */
\r
3142 #define VADC_OCS_TG_P_Pos 3 /*!< VADC OCS: TG_P Position */
\r
3143 #define VADC_OCS_TG_P_Msk (0x01UL << VADC_OCS_TG_P_Pos) /*!< VADC OCS: TG_P Mask */
\r
3144 #define VADC_OCS_SUS_Pos 24 /*!< VADC OCS: SUS Position */
\r
3145 #define VADC_OCS_SUS_Msk (0x0fUL << VADC_OCS_SUS_Pos) /*!< VADC OCS: SUS Mask */
\r
3146 #define VADC_OCS_SUS_P_Pos 28 /*!< VADC OCS: SUS_P Position */
\r
3147 #define VADC_OCS_SUS_P_Msk (0x01UL << VADC_OCS_SUS_P_Pos) /*!< VADC OCS: SUS_P Mask */
\r
3148 #define VADC_OCS_SUSSTA_Pos 29 /*!< VADC OCS: SUSSTA Position */
\r
3149 #define VADC_OCS_SUSSTA_Msk (0x01UL << VADC_OCS_SUSSTA_Pos) /*!< VADC OCS: SUSSTA Mask */
\r
3151 /* -------------------------------- VADC_GLOBCFG -------------------------------- */
\r
3152 #define VADC_GLOBCFG_DIVA_Pos 0 /*!< VADC GLOBCFG: DIVA Position */
\r
3153 #define VADC_GLOBCFG_DIVA_Msk (0x1fUL << VADC_GLOBCFG_DIVA_Pos) /*!< VADC GLOBCFG: DIVA Mask */
\r
3154 #define VADC_GLOBCFG_DCMSB_Pos 7 /*!< VADC GLOBCFG: DCMSB Position */
\r
3155 #define VADC_GLOBCFG_DCMSB_Msk (0x01UL << VADC_GLOBCFG_DCMSB_Pos) /*!< VADC GLOBCFG: DCMSB Mask */
\r
3156 #define VADC_GLOBCFG_DIVD_Pos 8 /*!< VADC GLOBCFG: DIVD Position */
\r
3157 #define VADC_GLOBCFG_DIVD_Msk (0x03UL << VADC_GLOBCFG_DIVD_Pos) /*!< VADC GLOBCFG: DIVD Mask */
\r
3158 #define VADC_GLOBCFG_DIVWC_Pos 15 /*!< VADC GLOBCFG: DIVWC Position */
\r
3159 #define VADC_GLOBCFG_DIVWC_Msk (0x01UL << VADC_GLOBCFG_DIVWC_Pos) /*!< VADC GLOBCFG: DIVWC Mask */
\r
3160 #define VADC_GLOBCFG_DPCAL0_Pos 16 /*!< VADC GLOBCFG: DPCAL0 Position */
\r
3161 #define VADC_GLOBCFG_DPCAL0_Msk (0x01UL << VADC_GLOBCFG_DPCAL0_Pos) /*!< VADC GLOBCFG: DPCAL0 Mask */
\r
3162 #define VADC_GLOBCFG_DPCAL1_Pos 17 /*!< VADC GLOBCFG: DPCAL1 Position */
\r
3163 #define VADC_GLOBCFG_DPCAL1_Msk (0x01UL << VADC_GLOBCFG_DPCAL1_Pos) /*!< VADC GLOBCFG: DPCAL1 Mask */
\r
3164 #define VADC_GLOBCFG_SUCAL_Pos 31 /*!< VADC GLOBCFG: SUCAL Position */
\r
3165 #define VADC_GLOBCFG_SUCAL_Msk (0x01UL << VADC_GLOBCFG_SUCAL_Pos) /*!< VADC GLOBCFG: SUCAL Mask */
\r
3167 /* ------------------------------- VADC_GLOBICLASS ------------------------------ */
\r
3168 #define VADC_GLOBICLASS_STCS_Pos 0 /*!< VADC GLOBICLASS: STCS Position */
\r
3169 #define VADC_GLOBICLASS_STCS_Msk (0x1fUL << VADC_GLOBICLASS_STCS_Pos) /*!< VADC GLOBICLASS: STCS Mask */
\r
3170 #define VADC_GLOBICLASS_CMS_Pos 8 /*!< VADC GLOBICLASS: CMS Position */
\r
3171 #define VADC_GLOBICLASS_CMS_Msk (0x07UL << VADC_GLOBICLASS_CMS_Pos) /*!< VADC GLOBICLASS: CMS Mask */
\r
3173 /* ------------------------------- VADC_GLOBEFLAG ------------------------------- */
\r
3174 #define VADC_GLOBEFLAG_SEVGLB_Pos 0 /*!< VADC GLOBEFLAG: SEVGLB Position */
\r
3175 #define VADC_GLOBEFLAG_SEVGLB_Msk (0x01UL << VADC_GLOBEFLAG_SEVGLB_Pos) /*!< VADC GLOBEFLAG: SEVGLB Mask */
\r
3176 #define VADC_GLOBEFLAG_REVGLB_Pos 8 /*!< VADC GLOBEFLAG: REVGLB Position */
\r
3177 #define VADC_GLOBEFLAG_REVGLB_Msk (0x01UL << VADC_GLOBEFLAG_REVGLB_Pos) /*!< VADC GLOBEFLAG: REVGLB Mask */
\r
3178 #define VADC_GLOBEFLAG_SEVGLBCLR_Pos 16 /*!< VADC GLOBEFLAG: SEVGLBCLR Position */
\r
3179 #define VADC_GLOBEFLAG_SEVGLBCLR_Msk (0x01UL << VADC_GLOBEFLAG_SEVGLBCLR_Pos) /*!< VADC GLOBEFLAG: SEVGLBCLR Mask */
\r
3180 #define VADC_GLOBEFLAG_REVGLBCLR_Pos 24 /*!< VADC GLOBEFLAG: REVGLBCLR Position */
\r
3181 #define VADC_GLOBEFLAG_REVGLBCLR_Msk (0x01UL << VADC_GLOBEFLAG_REVGLBCLR_Pos) /*!< VADC GLOBEFLAG: REVGLBCLR Mask */
\r
3183 /* -------------------------------- VADC_GLOBEVNP ------------------------------- */
\r
3184 #define VADC_GLOBEVNP_SEV0NP_Pos 0 /*!< VADC GLOBEVNP: SEV0NP Position */
\r
3185 #define VADC_GLOBEVNP_SEV0NP_Msk (0x0fUL << VADC_GLOBEVNP_SEV0NP_Pos) /*!< VADC GLOBEVNP: SEV0NP Mask */
\r
3186 #define VADC_GLOBEVNP_REV0NP_Pos 16 /*!< VADC GLOBEVNP: REV0NP Position */
\r
3187 #define VADC_GLOBEVNP_REV0NP_Msk (0x0fUL << VADC_GLOBEVNP_REV0NP_Pos) /*!< VADC GLOBEVNP: REV0NP Mask */
\r
3189 /* --------------------------------- VADC_BRSSEL -------------------------------- */
\r
3190 #define VADC_BRSSEL_CHSELG0_Pos 0 /*!< VADC BRSSEL: CHSELG0 Position */
\r
3191 #define VADC_BRSSEL_CHSELG0_Msk (0x01UL << VADC_BRSSEL_CHSELG0_Pos) /*!< VADC BRSSEL: CHSELG0 Mask */
\r
3192 #define VADC_BRSSEL_CHSELG1_Pos 1 /*!< VADC BRSSEL: CHSELG1 Position */
\r
3193 #define VADC_BRSSEL_CHSELG1_Msk (0x01UL << VADC_BRSSEL_CHSELG1_Pos) /*!< VADC BRSSEL: CHSELG1 Mask */
\r
3194 #define VADC_BRSSEL_CHSELG2_Pos 2 /*!< VADC BRSSEL: CHSELG2 Position */
\r
3195 #define VADC_BRSSEL_CHSELG2_Msk (0x01UL << VADC_BRSSEL_CHSELG2_Pos) /*!< VADC BRSSEL: CHSELG2 Mask */
\r
3196 #define VADC_BRSSEL_CHSELG3_Pos 3 /*!< VADC BRSSEL: CHSELG3 Position */
\r
3197 #define VADC_BRSSEL_CHSELG3_Msk (0x01UL << VADC_BRSSEL_CHSELG3_Pos) /*!< VADC BRSSEL: CHSELG3 Mask */
\r
3198 #define VADC_BRSSEL_CHSELG4_Pos 4 /*!< VADC BRSSEL: CHSELG4 Position */
\r
3199 #define VADC_BRSSEL_CHSELG4_Msk (0x01UL << VADC_BRSSEL_CHSELG4_Pos) /*!< VADC BRSSEL: CHSELG4 Mask */
\r
3200 #define VADC_BRSSEL_CHSELG5_Pos 5 /*!< VADC BRSSEL: CHSELG5 Position */
\r
3201 #define VADC_BRSSEL_CHSELG5_Msk (0x01UL << VADC_BRSSEL_CHSELG5_Pos) /*!< VADC BRSSEL: CHSELG5 Mask */
\r
3202 #define VADC_BRSSEL_CHSELG6_Pos 6 /*!< VADC BRSSEL: CHSELG6 Position */
\r
3203 #define VADC_BRSSEL_CHSELG6_Msk (0x01UL << VADC_BRSSEL_CHSELG6_Pos) /*!< VADC BRSSEL: CHSELG6 Mask */
\r
3204 #define VADC_BRSSEL_CHSELG7_Pos 7 /*!< VADC BRSSEL: CHSELG7 Position */
\r
3205 #define VADC_BRSSEL_CHSELG7_Msk (0x01UL << VADC_BRSSEL_CHSELG7_Pos) /*!< VADC BRSSEL: CHSELG7 Mask */
\r
3207 /* --------------------------------- VADC_BRSPND -------------------------------- */
\r
3208 #define VADC_BRSPND_CHPNDG0_Pos 0 /*!< VADC BRSPND: CHPNDG0 Position */
\r
3209 #define VADC_BRSPND_CHPNDG0_Msk (0x01UL << VADC_BRSPND_CHPNDG0_Pos) /*!< VADC BRSPND: CHPNDG0 Mask */
\r
3210 #define VADC_BRSPND_CHPNDG1_Pos 1 /*!< VADC BRSPND: CHPNDG1 Position */
\r
3211 #define VADC_BRSPND_CHPNDG1_Msk (0x01UL << VADC_BRSPND_CHPNDG1_Pos) /*!< VADC BRSPND: CHPNDG1 Mask */
\r
3212 #define VADC_BRSPND_CHPNDG2_Pos 2 /*!< VADC BRSPND: CHPNDG2 Position */
\r
3213 #define VADC_BRSPND_CHPNDG2_Msk (0x01UL << VADC_BRSPND_CHPNDG2_Pos) /*!< VADC BRSPND: CHPNDG2 Mask */
\r
3214 #define VADC_BRSPND_CHPNDG3_Pos 3 /*!< VADC BRSPND: CHPNDG3 Position */
\r
3215 #define VADC_BRSPND_CHPNDG3_Msk (0x01UL << VADC_BRSPND_CHPNDG3_Pos) /*!< VADC BRSPND: CHPNDG3 Mask */
\r
3216 #define VADC_BRSPND_CHPNDG4_Pos 4 /*!< VADC BRSPND: CHPNDG4 Position */
\r
3217 #define VADC_BRSPND_CHPNDG4_Msk (0x01UL << VADC_BRSPND_CHPNDG4_Pos) /*!< VADC BRSPND: CHPNDG4 Mask */
\r
3218 #define VADC_BRSPND_CHPNDG5_Pos 5 /*!< VADC BRSPND: CHPNDG5 Position */
\r
3219 #define VADC_BRSPND_CHPNDG5_Msk (0x01UL << VADC_BRSPND_CHPNDG5_Pos) /*!< VADC BRSPND: CHPNDG5 Mask */
\r
3220 #define VADC_BRSPND_CHPNDG6_Pos 6 /*!< VADC BRSPND: CHPNDG6 Position */
\r
3221 #define VADC_BRSPND_CHPNDG6_Msk (0x01UL << VADC_BRSPND_CHPNDG6_Pos) /*!< VADC BRSPND: CHPNDG6 Mask */
\r
3222 #define VADC_BRSPND_CHPNDG7_Pos 7 /*!< VADC BRSPND: CHPNDG7 Position */
\r
3223 #define VADC_BRSPND_CHPNDG7_Msk (0x01UL << VADC_BRSPND_CHPNDG7_Pos) /*!< VADC BRSPND: CHPNDG7 Mask */
\r
3225 /* -------------------------------- VADC_BRSCTRL -------------------------------- */
\r
3226 #define VADC_BRSCTRL_SRCRESREG_Pos 0 /*!< VADC BRSCTRL: SRCRESREG Position */
\r
3227 #define VADC_BRSCTRL_SRCRESREG_Msk (0x0fUL << VADC_BRSCTRL_SRCRESREG_Pos) /*!< VADC BRSCTRL: SRCRESREG Mask */
\r
3228 #define VADC_BRSCTRL_XTSEL_Pos 8 /*!< VADC BRSCTRL: XTSEL Position */
\r
3229 #define VADC_BRSCTRL_XTSEL_Msk (0x0fUL << VADC_BRSCTRL_XTSEL_Pos) /*!< VADC BRSCTRL: XTSEL Mask */
\r
3230 #define VADC_BRSCTRL_XTLVL_Pos 12 /*!< VADC BRSCTRL: XTLVL Position */
\r
3231 #define VADC_BRSCTRL_XTLVL_Msk (0x01UL << VADC_BRSCTRL_XTLVL_Pos) /*!< VADC BRSCTRL: XTLVL Mask */
\r
3232 #define VADC_BRSCTRL_XTMODE_Pos 13 /*!< VADC BRSCTRL: XTMODE Position */
\r
3233 #define VADC_BRSCTRL_XTMODE_Msk (0x03UL << VADC_BRSCTRL_XTMODE_Pos) /*!< VADC BRSCTRL: XTMODE Mask */
\r
3234 #define VADC_BRSCTRL_XTWC_Pos 15 /*!< VADC BRSCTRL: XTWC Position */
\r
3235 #define VADC_BRSCTRL_XTWC_Msk (0x01UL << VADC_BRSCTRL_XTWC_Pos) /*!< VADC BRSCTRL: XTWC Mask */
\r
3236 #define VADC_BRSCTRL_GTSEL_Pos 16 /*!< VADC BRSCTRL: GTSEL Position */
\r
3237 #define VADC_BRSCTRL_GTSEL_Msk (0x0fUL << VADC_BRSCTRL_GTSEL_Pos) /*!< VADC BRSCTRL: GTSEL Mask */
\r
3238 #define VADC_BRSCTRL_GTLVL_Pos 20 /*!< VADC BRSCTRL: GTLVL Position */
\r
3239 #define VADC_BRSCTRL_GTLVL_Msk (0x01UL << VADC_BRSCTRL_GTLVL_Pos) /*!< VADC BRSCTRL: GTLVL Mask */
\r
3240 #define VADC_BRSCTRL_GTWC_Pos 23 /*!< VADC BRSCTRL: GTWC Position */
\r
3241 #define VADC_BRSCTRL_GTWC_Msk (0x01UL << VADC_BRSCTRL_GTWC_Pos) /*!< VADC BRSCTRL: GTWC Mask */
\r
3243 /* --------------------------------- VADC_BRSMR --------------------------------- */
\r
3244 #define VADC_BRSMR_ENGT_Pos 0 /*!< VADC BRSMR: ENGT Position */
\r
3245 #define VADC_BRSMR_ENGT_Msk (0x03UL << VADC_BRSMR_ENGT_Pos) /*!< VADC BRSMR: ENGT Mask */
\r
3246 #define VADC_BRSMR_ENTR_Pos 2 /*!< VADC BRSMR: ENTR Position */
\r
3247 #define VADC_BRSMR_ENTR_Msk (0x01UL << VADC_BRSMR_ENTR_Pos) /*!< VADC BRSMR: ENTR Mask */
\r
3248 #define VADC_BRSMR_ENSI_Pos 3 /*!< VADC BRSMR: ENSI Position */
\r
3249 #define VADC_BRSMR_ENSI_Msk (0x01UL << VADC_BRSMR_ENSI_Pos) /*!< VADC BRSMR: ENSI Mask */
\r
3250 #define VADC_BRSMR_SCAN_Pos 4 /*!< VADC BRSMR: SCAN Position */
\r
3251 #define VADC_BRSMR_SCAN_Msk (0x01UL << VADC_BRSMR_SCAN_Pos) /*!< VADC BRSMR: SCAN Mask */
\r
3252 #define VADC_BRSMR_LDM_Pos 5 /*!< VADC BRSMR: LDM Position */
\r
3253 #define VADC_BRSMR_LDM_Msk (0x01UL << VADC_BRSMR_LDM_Pos) /*!< VADC BRSMR: LDM Mask */
\r
3254 #define VADC_BRSMR_REQGT_Pos 7 /*!< VADC BRSMR: REQGT Position */
\r
3255 #define VADC_BRSMR_REQGT_Msk (0x01UL << VADC_BRSMR_REQGT_Pos) /*!< VADC BRSMR: REQGT Mask */
\r
3256 #define VADC_BRSMR_CLRPND_Pos 8 /*!< VADC BRSMR: CLRPND Position */
\r
3257 #define VADC_BRSMR_CLRPND_Msk (0x01UL << VADC_BRSMR_CLRPND_Pos) /*!< VADC BRSMR: CLRPND Mask */
\r
3258 #define VADC_BRSMR_LDEV_Pos 9 /*!< VADC BRSMR: LDEV Position */
\r
3259 #define VADC_BRSMR_LDEV_Msk (0x01UL << VADC_BRSMR_LDEV_Pos) /*!< VADC BRSMR: LDEV Mask */
\r
3260 #define VADC_BRSMR_RPTDIS_Pos 16 /*!< VADC BRSMR: RPTDIS Position */
\r
3261 #define VADC_BRSMR_RPTDIS_Msk (0x01UL << VADC_BRSMR_RPTDIS_Pos) /*!< VADC BRSMR: RPTDIS Mask */
\r
3263 /* -------------------------------- VADC_GLOBRCR -------------------------------- */
\r
3264 #define VADC_GLOBRCR_DRCTR_Pos 16 /*!< VADC GLOBRCR: DRCTR Position */
\r
3265 #define VADC_GLOBRCR_DRCTR_Msk (0x0fUL << VADC_GLOBRCR_DRCTR_Pos) /*!< VADC GLOBRCR: DRCTR Mask */
\r
3266 #define VADC_GLOBRCR_WFR_Pos 24 /*!< VADC GLOBRCR: WFR Position */
\r
3267 #define VADC_GLOBRCR_WFR_Msk (0x01UL << VADC_GLOBRCR_WFR_Pos) /*!< VADC GLOBRCR: WFR Mask */
\r
3268 #define VADC_GLOBRCR_SRGEN_Pos 31 /*!< VADC GLOBRCR: SRGEN Position */
\r
3269 #define VADC_GLOBRCR_SRGEN_Msk (0x01UL << VADC_GLOBRCR_SRGEN_Pos) /*!< VADC GLOBRCR: SRGEN Mask */
\r
3271 /* -------------------------------- VADC_GLOBRES -------------------------------- */
\r
3272 #define VADC_GLOBRES_RESULT_Pos 0 /*!< VADC GLOBRES: RESULT Position */
\r
3273 #define VADC_GLOBRES_RESULT_Msk (0x0000ffffUL << VADC_GLOBRES_RESULT_Pos) /*!< VADC GLOBRES: RESULT Mask */
\r
3274 #define VADC_GLOBRES_GNR_Pos 16 /*!< VADC GLOBRES: GNR Position */
\r
3275 #define VADC_GLOBRES_GNR_Msk (0x0fUL << VADC_GLOBRES_GNR_Pos) /*!< VADC GLOBRES: GNR Mask */
\r
3276 #define VADC_GLOBRES_CHNR_Pos 20 /*!< VADC GLOBRES: CHNR Position */
\r
3277 #define VADC_GLOBRES_CHNR_Msk (0x1fUL << VADC_GLOBRES_CHNR_Pos) /*!< VADC GLOBRES: CHNR Mask */
\r
3278 #define VADC_GLOBRES_EMUX_Pos 25 /*!< VADC GLOBRES: EMUX Position */
\r
3279 #define VADC_GLOBRES_EMUX_Msk (0x07UL << VADC_GLOBRES_EMUX_Pos) /*!< VADC GLOBRES: EMUX Mask */
\r
3280 #define VADC_GLOBRES_CRS_Pos 28 /*!< VADC GLOBRES: CRS Position */
\r
3281 #define VADC_GLOBRES_CRS_Msk (0x03UL << VADC_GLOBRES_CRS_Pos) /*!< VADC GLOBRES: CRS Mask */
\r
3282 #define VADC_GLOBRES_FCR_Pos 30 /*!< VADC GLOBRES: FCR Position */
\r
3283 #define VADC_GLOBRES_FCR_Msk (0x01UL << VADC_GLOBRES_FCR_Pos) /*!< VADC GLOBRES: FCR Mask */
\r
3284 #define VADC_GLOBRES_VF_Pos 31 /*!< VADC GLOBRES: VF Position */
\r
3285 #define VADC_GLOBRES_VF_Msk (0x01UL << VADC_GLOBRES_VF_Pos) /*!< VADC GLOBRES: VF Mask */
\r
3287 /* -------------------------------- VADC_GLOBRESD ------------------------------- */
\r
3288 #define VADC_GLOBRESD_RESULT_Pos 0 /*!< VADC GLOBRESD: RESULT Position */
\r
3289 #define VADC_GLOBRESD_RESULT_Msk (0x0000ffffUL << VADC_GLOBRESD_RESULT_Pos) /*!< VADC GLOBRESD: RESULT Mask */
\r
3290 #define VADC_GLOBRESD_GNR_Pos 16 /*!< VADC GLOBRESD: GNR Position */
\r
3291 #define VADC_GLOBRESD_GNR_Msk (0x0fUL << VADC_GLOBRESD_GNR_Pos) /*!< VADC GLOBRESD: GNR Mask */
\r
3292 #define VADC_GLOBRESD_CHNR_Pos 20 /*!< VADC GLOBRESD: CHNR Position */
\r
3293 #define VADC_GLOBRESD_CHNR_Msk (0x1fUL << VADC_GLOBRESD_CHNR_Pos) /*!< VADC GLOBRESD: CHNR Mask */
\r
3294 #define VADC_GLOBRESD_EMUX_Pos 25 /*!< VADC GLOBRESD: EMUX Position */
\r
3295 #define VADC_GLOBRESD_EMUX_Msk (0x07UL << VADC_GLOBRESD_EMUX_Pos) /*!< VADC GLOBRESD: EMUX Mask */
\r
3296 #define VADC_GLOBRESD_CRS_Pos 28 /*!< VADC GLOBRESD: CRS Position */
\r
3297 #define VADC_GLOBRESD_CRS_Msk (0x03UL << VADC_GLOBRESD_CRS_Pos) /*!< VADC GLOBRESD: CRS Mask */
\r
3298 #define VADC_GLOBRESD_FCR_Pos 30 /*!< VADC GLOBRESD: FCR Position */
\r
3299 #define VADC_GLOBRESD_FCR_Msk (0x01UL << VADC_GLOBRESD_FCR_Pos) /*!< VADC GLOBRESD: FCR Mask */
\r
3300 #define VADC_GLOBRESD_VF_Pos 31 /*!< VADC GLOBRESD: VF Position */
\r
3301 #define VADC_GLOBRESD_VF_Msk (0x01UL << VADC_GLOBRESD_VF_Pos) /*!< VADC GLOBRESD: VF Mask */
\r
3304 /* ================================================================================ */
\r
3305 /* ================ Group 'SHS' Position & Mask ================ */
\r
3306 /* ================================================================================ */
\r
3309 /* ----------------------------------- SHS_ID ----------------------------------- */
\r
3310 #define SHS_ID_MOD_REV_Pos 0 /*!< SHS ID: MOD_REV Position */
\r
3311 #define SHS_ID_MOD_REV_Msk (0x000000ffUL << SHS_ID_MOD_REV_Pos) /*!< SHS ID: MOD_REV Mask */
\r
3312 #define SHS_ID_MOD_TYPE_Pos 8 /*!< SHS ID: MOD_TYPE Position */
\r
3313 #define SHS_ID_MOD_TYPE_Msk (0x000000ffUL << SHS_ID_MOD_TYPE_Pos) /*!< SHS ID: MOD_TYPE Mask */
\r
3314 #define SHS_ID_MOD_NUMBER_Pos 16 /*!< SHS ID: MOD_NUMBER Position */
\r
3315 #define SHS_ID_MOD_NUMBER_Msk (0x0000ffffUL << SHS_ID_MOD_NUMBER_Pos) /*!< SHS ID: MOD_NUMBER Mask */
\r
3317 /* --------------------------------- SHS_SHSCFG --------------------------------- */
\r
3318 #define SHS_SHSCFG_DIVS_Pos 0 /*!< SHS SHSCFG: DIVS Position */
\r
3319 #define SHS_SHSCFG_DIVS_Msk (0x0fUL << SHS_SHSCFG_DIVS_Pos) /*!< SHS SHSCFG: DIVS Mask */
\r
3320 #define SHS_SHSCFG_AREF_Pos 10 /*!< SHS SHSCFG: AREF Position */
\r
3321 #define SHS_SHSCFG_AREF_Msk (0x03UL << SHS_SHSCFG_AREF_Pos) /*!< SHS SHSCFG: AREF Mask */
\r
3322 #define SHS_SHSCFG_ANOFF_Pos 12 /*!< SHS SHSCFG: ANOFF Position */
\r
3323 #define SHS_SHSCFG_ANOFF_Msk (0x01UL << SHS_SHSCFG_ANOFF_Pos) /*!< SHS SHSCFG: ANOFF Mask */
\r
3324 #define SHS_SHSCFG_ANRDY_Pos 14 /*!< SHS SHSCFG: ANRDY Position */
\r
3325 #define SHS_SHSCFG_ANRDY_Msk (0x01UL << SHS_SHSCFG_ANRDY_Pos) /*!< SHS SHSCFG: ANRDY Mask */
\r
3326 #define SHS_SHSCFG_SCWC_Pos 15 /*!< SHS SHSCFG: SCWC Position */
\r
3327 #define SHS_SHSCFG_SCWC_Msk (0x01UL << SHS_SHSCFG_SCWC_Pos) /*!< SHS SHSCFG: SCWC Mask */
\r
3328 #define SHS_SHSCFG_SP0_Pos 16 /*!< SHS SHSCFG: SP0 Position */
\r
3329 #define SHS_SHSCFG_SP0_Msk (0x01UL << SHS_SHSCFG_SP0_Pos) /*!< SHS SHSCFG: SP0 Mask */
\r
3330 #define SHS_SHSCFG_SP1_Pos 17 /*!< SHS SHSCFG: SP1 Position */
\r
3331 #define SHS_SHSCFG_SP1_Msk (0x01UL << SHS_SHSCFG_SP1_Pos) /*!< SHS SHSCFG: SP1 Mask */
\r
3332 #define SHS_SHSCFG_TC_Pos 24 /*!< SHS SHSCFG: TC Position */
\r
3333 #define SHS_SHSCFG_TC_Msk (0x0fUL << SHS_SHSCFG_TC_Pos) /*!< SHS SHSCFG: TC Mask */
\r
3334 #define SHS_SHSCFG_STATE_Pos 28 /*!< SHS SHSCFG: STATE Position */
\r
3335 #define SHS_SHSCFG_STATE_Msk (0x0fUL << SHS_SHSCFG_STATE_Pos) /*!< SHS SHSCFG: STATE Mask */
\r
3337 /* --------------------------------- SHS_STEPCFG -------------------------------- */
\r
3338 #define SHS_STEPCFG_KSEL0_Pos 0 /*!< SHS STEPCFG: KSEL0 Position */
\r
3339 #define SHS_STEPCFG_KSEL0_Msk (0x07UL << SHS_STEPCFG_KSEL0_Pos) /*!< SHS STEPCFG: KSEL0 Mask */
\r
3340 #define SHS_STEPCFG_SEN0_Pos 3 /*!< SHS STEPCFG: SEN0 Position */
\r
3341 #define SHS_STEPCFG_SEN0_Msk (0x01UL << SHS_STEPCFG_SEN0_Pos) /*!< SHS STEPCFG: SEN0 Mask */
\r
3342 #define SHS_STEPCFG_KSEL1_Pos 4 /*!< SHS STEPCFG: KSEL1 Position */
\r
3343 #define SHS_STEPCFG_KSEL1_Msk (0x07UL << SHS_STEPCFG_KSEL1_Pos) /*!< SHS STEPCFG: KSEL1 Mask */
\r
3344 #define SHS_STEPCFG_SEN1_Pos 7 /*!< SHS STEPCFG: SEN1 Position */
\r
3345 #define SHS_STEPCFG_SEN1_Msk (0x01UL << SHS_STEPCFG_SEN1_Pos) /*!< SHS STEPCFG: SEN1 Mask */
\r
3346 #define SHS_STEPCFG_KSEL2_Pos 8 /*!< SHS STEPCFG: KSEL2 Position */
\r
3347 #define SHS_STEPCFG_KSEL2_Msk (0x07UL << SHS_STEPCFG_KSEL2_Pos) /*!< SHS STEPCFG: KSEL2 Mask */
\r
3348 #define SHS_STEPCFG_SEN2_Pos 11 /*!< SHS STEPCFG: SEN2 Position */
\r
3349 #define SHS_STEPCFG_SEN2_Msk (0x01UL << SHS_STEPCFG_SEN2_Pos) /*!< SHS STEPCFG: SEN2 Mask */
\r
3350 #define SHS_STEPCFG_KSEL3_Pos 12 /*!< SHS STEPCFG: KSEL3 Position */
\r
3351 #define SHS_STEPCFG_KSEL3_Msk (0x07UL << SHS_STEPCFG_KSEL3_Pos) /*!< SHS STEPCFG: KSEL3 Mask */
\r
3352 #define SHS_STEPCFG_SEN3_Pos 15 /*!< SHS STEPCFG: SEN3 Position */
\r
3353 #define SHS_STEPCFG_SEN3_Msk (0x01UL << SHS_STEPCFG_SEN3_Pos) /*!< SHS STEPCFG: SEN3 Mask */
\r
3354 #define SHS_STEPCFG_KSEL4_Pos 16 /*!< SHS STEPCFG: KSEL4 Position */
\r
3355 #define SHS_STEPCFG_KSEL4_Msk (0x07UL << SHS_STEPCFG_KSEL4_Pos) /*!< SHS STEPCFG: KSEL4 Mask */
\r
3356 #define SHS_STEPCFG_SEN4_Pos 19 /*!< SHS STEPCFG: SEN4 Position */
\r
3357 #define SHS_STEPCFG_SEN4_Msk (0x01UL << SHS_STEPCFG_SEN4_Pos) /*!< SHS STEPCFG: SEN4 Mask */
\r
3358 #define SHS_STEPCFG_KSEL5_Pos 20 /*!< SHS STEPCFG: KSEL5 Position */
\r
3359 #define SHS_STEPCFG_KSEL5_Msk (0x07UL << SHS_STEPCFG_KSEL5_Pos) /*!< SHS STEPCFG: KSEL5 Mask */
\r
3360 #define SHS_STEPCFG_SEN5_Pos 23 /*!< SHS STEPCFG: SEN5 Position */
\r
3361 #define SHS_STEPCFG_SEN5_Msk (0x01UL << SHS_STEPCFG_SEN5_Pos) /*!< SHS STEPCFG: SEN5 Mask */
\r
3362 #define SHS_STEPCFG_KSEL6_Pos 24 /*!< SHS STEPCFG: KSEL6 Position */
\r
3363 #define SHS_STEPCFG_KSEL6_Msk (0x07UL << SHS_STEPCFG_KSEL6_Pos) /*!< SHS STEPCFG: KSEL6 Mask */
\r
3364 #define SHS_STEPCFG_SEN6_Pos 27 /*!< SHS STEPCFG: SEN6 Position */
\r
3365 #define SHS_STEPCFG_SEN6_Msk (0x01UL << SHS_STEPCFG_SEN6_Pos) /*!< SHS STEPCFG: SEN6 Mask */
\r
3366 #define SHS_STEPCFG_KSEL7_Pos 28 /*!< SHS STEPCFG: KSEL7 Position */
\r
3367 #define SHS_STEPCFG_KSEL7_Msk (0x07UL << SHS_STEPCFG_KSEL7_Pos) /*!< SHS STEPCFG: KSEL7 Mask */
\r
3368 #define SHS_STEPCFG_SEN7_Pos 31 /*!< SHS STEPCFG: SEN7 Position */
\r
3369 #define SHS_STEPCFG_SEN7_Msk (0x01UL << SHS_STEPCFG_SEN7_Pos) /*!< SHS STEPCFG: SEN7 Mask */
\r
3371 /* ---------------------------------- SHS_LOOP ---------------------------------- */
\r
3372 #define SHS_LOOP_LPCH0_Pos 0 /*!< SHS LOOP: LPCH0 Position */
\r
3373 #define SHS_LOOP_LPCH0_Msk (0x1fUL << SHS_LOOP_LPCH0_Pos) /*!< SHS LOOP: LPCH0 Mask */
\r
3374 #define SHS_LOOP_LPSH0_Pos 8 /*!< SHS LOOP: LPSH0 Position */
\r
3375 #define SHS_LOOP_LPSH0_Msk (0x01UL << SHS_LOOP_LPSH0_Pos) /*!< SHS LOOP: LPSH0 Mask */
\r
3376 #define SHS_LOOP_LPEN0_Pos 15 /*!< SHS LOOP: LPEN0 Position */
\r
3377 #define SHS_LOOP_LPEN0_Msk (0x01UL << SHS_LOOP_LPEN0_Pos) /*!< SHS LOOP: LPEN0 Mask */
\r
3378 #define SHS_LOOP_LPCH1_Pos 16 /*!< SHS LOOP: LPCH1 Position */
\r
3379 #define SHS_LOOP_LPCH1_Msk (0x1fUL << SHS_LOOP_LPCH1_Pos) /*!< SHS LOOP: LPCH1 Mask */
\r
3380 #define SHS_LOOP_LPSH1_Pos 24 /*!< SHS LOOP: LPSH1 Position */
\r
3381 #define SHS_LOOP_LPSH1_Msk (0x01UL << SHS_LOOP_LPSH1_Pos) /*!< SHS LOOP: LPSH1 Mask */
\r
3382 #define SHS_LOOP_LPEN1_Pos 31 /*!< SHS LOOP: LPEN1 Position */
\r
3383 #define SHS_LOOP_LPEN1_Msk (0x01UL << SHS_LOOP_LPEN1_Pos) /*!< SHS LOOP: LPEN1 Mask */
\r
3385 /* --------------------------------- SHS_TIMCFG0 -------------------------------- */
\r
3386 #define SHS_TIMCFG0_AT_Pos 0 /*!< SHS TIMCFG0: AT Position */
\r
3387 #define SHS_TIMCFG0_AT_Msk (0x01UL << SHS_TIMCFG0_AT_Pos) /*!< SHS TIMCFG0: AT Mask */
\r
3388 #define SHS_TIMCFG0_FCRT_Pos 4 /*!< SHS TIMCFG0: FCRT Position */
\r
3389 #define SHS_TIMCFG0_FCRT_Msk (0x0fUL << SHS_TIMCFG0_FCRT_Pos) /*!< SHS TIMCFG0: FCRT Mask */
\r
3390 #define SHS_TIMCFG0_SST_Pos 8 /*!< SHS TIMCFG0: SST Position */
\r
3391 #define SHS_TIMCFG0_SST_Msk (0x3fUL << SHS_TIMCFG0_SST_Pos) /*!< SHS TIMCFG0: SST Mask */
\r
3392 #define SHS_TIMCFG0_TGEN_Pos 16 /*!< SHS TIMCFG0: TGEN Position */
\r
3393 #define SHS_TIMCFG0_TGEN_Msk (0x00003fffUL << SHS_TIMCFG0_TGEN_Pos) /*!< SHS TIMCFG0: TGEN Mask */
\r
3395 /* --------------------------------- SHS_TIMCFG1 -------------------------------- */
\r
3396 #define SHS_TIMCFG1_AT_Pos 0 /*!< SHS TIMCFG1: AT Position */
\r
3397 #define SHS_TIMCFG1_AT_Msk (0x01UL << SHS_TIMCFG1_AT_Pos) /*!< SHS TIMCFG1: AT Mask */
\r
3398 #define SHS_TIMCFG1_FCRT_Pos 4 /*!< SHS TIMCFG1: FCRT Position */
\r
3399 #define SHS_TIMCFG1_FCRT_Msk (0x0fUL << SHS_TIMCFG1_FCRT_Pos) /*!< SHS TIMCFG1: FCRT Mask */
\r
3400 #define SHS_TIMCFG1_SST_Pos 8 /*!< SHS TIMCFG1: SST Position */
\r
3401 #define SHS_TIMCFG1_SST_Msk (0x3fUL << SHS_TIMCFG1_SST_Pos) /*!< SHS TIMCFG1: SST Mask */
\r
3402 #define SHS_TIMCFG1_TGEN_Pos 16 /*!< SHS TIMCFG1: TGEN Position */
\r
3403 #define SHS_TIMCFG1_TGEN_Msk (0x00003fffUL << SHS_TIMCFG1_TGEN_Pos) /*!< SHS TIMCFG1: TGEN Mask */
\r
3405 /* --------------------------------- SHS_CALCTR --------------------------------- */
\r
3406 #define SHS_CALCTR_CALORD_Pos 0 /*!< SHS CALCTR: CALORD Position */
\r
3407 #define SHS_CALCTR_CALORD_Msk (0x01UL << SHS_CALCTR_CALORD_Pos) /*!< SHS CALCTR: CALORD Mask */
\r
3408 #define SHS_CALCTR_CALGNSTC_Pos 8 /*!< SHS CALCTR: CALGNSTC Position */
\r
3409 #define SHS_CALCTR_CALGNSTC_Msk (0x3fUL << SHS_CALCTR_CALGNSTC_Pos) /*!< SHS CALCTR: CALGNSTC Mask */
\r
3410 #define SHS_CALCTR_SUCALVAL_Pos 16 /*!< SHS CALCTR: SUCALVAL Position */
\r
3411 #define SHS_CALCTR_SUCALVAL_Msk (0x7fUL << SHS_CALCTR_SUCALVAL_Pos) /*!< SHS CALCTR: SUCALVAL Mask */
\r
3412 #define SHS_CALCTR_CALMAX_Pos 24 /*!< SHS CALCTR: CALMAX Position */
\r
3413 #define SHS_CALCTR_CALMAX_Msk (0x3fUL << SHS_CALCTR_CALMAX_Pos) /*!< SHS CALCTR: CALMAX Mask */
\r
3414 #define SHS_CALCTR_SUCAL_Pos 31 /*!< SHS CALCTR: SUCAL Position */
\r
3415 #define SHS_CALCTR_SUCAL_Msk (0x01UL << SHS_CALCTR_SUCAL_Pos) /*!< SHS CALCTR: SUCAL Mask */
\r
3417 /* --------------------------------- SHS_CALGC0 --------------------------------- */
\r
3418 #define SHS_CALGC0_CALGNVALS_Pos 0 /*!< SHS CALGC0: CALGNVALS Position */
\r
3419 #define SHS_CALGC0_CALGNVALS_Msk (0x00003fffUL << SHS_CALGC0_CALGNVALS_Pos) /*!< SHS CALGC0: CALGNVALS Mask */
\r
3420 #define SHS_CALGC0_GNSWC_Pos 15 /*!< SHS CALGC0: GNSWC Position */
\r
3421 #define SHS_CALGC0_GNSWC_Msk (0x01UL << SHS_CALGC0_GNSWC_Pos) /*!< SHS CALGC0: GNSWC Mask */
\r
3422 #define SHS_CALGC0_CALGNVALA_Pos 16 /*!< SHS CALGC0: CALGNVALA Position */
\r
3423 #define SHS_CALGC0_CALGNVALA_Msk (0x00003fffUL << SHS_CALGC0_CALGNVALA_Pos) /*!< SHS CALGC0: CALGNVALA Mask */
\r
3424 #define SHS_CALGC0_GNAWC_Pos 31 /*!< SHS CALGC0: GNAWC Position */
\r
3425 #define SHS_CALGC0_GNAWC_Msk (0x01UL << SHS_CALGC0_GNAWC_Pos) /*!< SHS CALGC0: GNAWC Mask */
\r
3427 /* --------------------------------- SHS_CALGC1 --------------------------------- */
\r
3428 #define SHS_CALGC1_CALGNVALS_Pos 0 /*!< SHS CALGC1: CALGNVALS Position */
\r
3429 #define SHS_CALGC1_CALGNVALS_Msk (0x00003fffUL << SHS_CALGC1_CALGNVALS_Pos) /*!< SHS CALGC1: CALGNVALS Mask */
\r
3430 #define SHS_CALGC1_GNSWC_Pos 15 /*!< SHS CALGC1: GNSWC Position */
\r
3431 #define SHS_CALGC1_GNSWC_Msk (0x01UL << SHS_CALGC1_GNSWC_Pos) /*!< SHS CALGC1: GNSWC Mask */
\r
3432 #define SHS_CALGC1_CALGNVALA_Pos 16 /*!< SHS CALGC1: CALGNVALA Position */
\r
3433 #define SHS_CALGC1_CALGNVALA_Msk (0x00003fffUL << SHS_CALGC1_CALGNVALA_Pos) /*!< SHS CALGC1: CALGNVALA Mask */
\r
3434 #define SHS_CALGC1_GNAWC_Pos 31 /*!< SHS CALGC1: GNAWC Position */
\r
3435 #define SHS_CALGC1_GNAWC_Msk (0x01UL << SHS_CALGC1_GNAWC_Pos) /*!< SHS CALGC1: GNAWC Mask */
\r
3437 /* --------------------------------- SHS_GNCTR00 -------------------------------- */
\r
3438 #define SHS_GNCTR00_GAIN0_Pos 0 /*!< SHS GNCTR00: GAIN0 Position */
\r
3439 #define SHS_GNCTR00_GAIN0_Msk (0x0fUL << SHS_GNCTR00_GAIN0_Pos) /*!< SHS GNCTR00: GAIN0 Mask */
\r
3440 #define SHS_GNCTR00_GAIN1_Pos 4 /*!< SHS GNCTR00: GAIN1 Position */
\r
3441 #define SHS_GNCTR00_GAIN1_Msk (0x0fUL << SHS_GNCTR00_GAIN1_Pos) /*!< SHS GNCTR00: GAIN1 Mask */
\r
3442 #define SHS_GNCTR00_GAIN2_Pos 8 /*!< SHS GNCTR00: GAIN2 Position */
\r
3443 #define SHS_GNCTR00_GAIN2_Msk (0x0fUL << SHS_GNCTR00_GAIN2_Pos) /*!< SHS GNCTR00: GAIN2 Mask */
\r
3444 #define SHS_GNCTR00_GAIN3_Pos 12 /*!< SHS GNCTR00: GAIN3 Position */
\r
3445 #define SHS_GNCTR00_GAIN3_Msk (0x0fUL << SHS_GNCTR00_GAIN3_Pos) /*!< SHS GNCTR00: GAIN3 Mask */
\r
3446 #define SHS_GNCTR00_GAIN4_Pos 16 /*!< SHS GNCTR00: GAIN4 Position */
\r
3447 #define SHS_GNCTR00_GAIN4_Msk (0x0fUL << SHS_GNCTR00_GAIN4_Pos) /*!< SHS GNCTR00: GAIN4 Mask */
\r
3448 #define SHS_GNCTR00_GAIN5_Pos 20 /*!< SHS GNCTR00: GAIN5 Position */
\r
3449 #define SHS_GNCTR00_GAIN5_Msk (0x0fUL << SHS_GNCTR00_GAIN5_Pos) /*!< SHS GNCTR00: GAIN5 Mask */
\r
3450 #define SHS_GNCTR00_GAIN6_Pos 24 /*!< SHS GNCTR00: GAIN6 Position */
\r
3451 #define SHS_GNCTR00_GAIN6_Msk (0x0fUL << SHS_GNCTR00_GAIN6_Pos) /*!< SHS GNCTR00: GAIN6 Mask */
\r
3452 #define SHS_GNCTR00_GAIN7_Pos 28 /*!< SHS GNCTR00: GAIN7 Position */
\r
3453 #define SHS_GNCTR00_GAIN7_Msk (0x0fUL << SHS_GNCTR00_GAIN7_Pos) /*!< SHS GNCTR00: GAIN7 Mask */
\r
3455 /* --------------------------------- SHS_GNCTR10 -------------------------------- */
\r
3456 #define SHS_GNCTR10_GAIN0_Pos 0 /*!< SHS GNCTR10: GAIN0 Position */
\r
3457 #define SHS_GNCTR10_GAIN0_Msk (0x0fUL << SHS_GNCTR10_GAIN0_Pos) /*!< SHS GNCTR10: GAIN0 Mask */
\r
3458 #define SHS_GNCTR10_GAIN1_Pos 4 /*!< SHS GNCTR10: GAIN1 Position */
\r
3459 #define SHS_GNCTR10_GAIN1_Msk (0x0fUL << SHS_GNCTR10_GAIN1_Pos) /*!< SHS GNCTR10: GAIN1 Mask */
\r
3460 #define SHS_GNCTR10_GAIN2_Pos 8 /*!< SHS GNCTR10: GAIN2 Position */
\r
3461 #define SHS_GNCTR10_GAIN2_Msk (0x0fUL << SHS_GNCTR10_GAIN2_Pos) /*!< SHS GNCTR10: GAIN2 Mask */
\r
3462 #define SHS_GNCTR10_GAIN3_Pos 12 /*!< SHS GNCTR10: GAIN3 Position */
\r
3463 #define SHS_GNCTR10_GAIN3_Msk (0x0fUL << SHS_GNCTR10_GAIN3_Pos) /*!< SHS GNCTR10: GAIN3 Mask */
\r
3464 #define SHS_GNCTR10_GAIN4_Pos 16 /*!< SHS GNCTR10: GAIN4 Position */
\r
3465 #define SHS_GNCTR10_GAIN4_Msk (0x0fUL << SHS_GNCTR10_GAIN4_Pos) /*!< SHS GNCTR10: GAIN4 Mask */
\r
3466 #define SHS_GNCTR10_GAIN5_Pos 20 /*!< SHS GNCTR10: GAIN5 Position */
\r
3467 #define SHS_GNCTR10_GAIN5_Msk (0x0fUL << SHS_GNCTR10_GAIN5_Pos) /*!< SHS GNCTR10: GAIN5 Mask */
\r
3468 #define SHS_GNCTR10_GAIN6_Pos 24 /*!< SHS GNCTR10: GAIN6 Position */
\r
3469 #define SHS_GNCTR10_GAIN6_Msk (0x0fUL << SHS_GNCTR10_GAIN6_Pos) /*!< SHS GNCTR10: GAIN6 Mask */
\r
3470 #define SHS_GNCTR10_GAIN7_Pos 28 /*!< SHS GNCTR10: GAIN7 Position */
\r
3471 #define SHS_GNCTR10_GAIN7_Msk (0x0fUL << SHS_GNCTR10_GAIN7_Pos) /*!< SHS GNCTR10: GAIN7 Mask */
\r
3474 /* ================================================================================ */
\r
3475 /* ================ struct 'PORT0' Position & Mask ================ */
\r
3476 /* ================================================================================ */
\r
3479 /* ---------------------------------- PORT0_OUT --------------------------------- */
\r
3480 #define PORT0_OUT_P0_Pos 0 /*!< PORT0 OUT: P0 Position */
\r
3481 #define PORT0_OUT_P0_Msk (0x01UL << PORT0_OUT_P0_Pos) /*!< PORT0 OUT: P0 Mask */
\r
3482 #define PORT0_OUT_P1_Pos 1 /*!< PORT0 OUT: P1 Position */
\r
3483 #define PORT0_OUT_P1_Msk (0x01UL << PORT0_OUT_P1_Pos) /*!< PORT0 OUT: P1 Mask */
\r
3484 #define PORT0_OUT_P2_Pos 2 /*!< PORT0 OUT: P2 Position */
\r
3485 #define PORT0_OUT_P2_Msk (0x01UL << PORT0_OUT_P2_Pos) /*!< PORT0 OUT: P2 Mask */
\r
3486 #define PORT0_OUT_P3_Pos 3 /*!< PORT0 OUT: P3 Position */
\r
3487 #define PORT0_OUT_P3_Msk (0x01UL << PORT0_OUT_P3_Pos) /*!< PORT0 OUT: P3 Mask */
\r
3488 #define PORT0_OUT_P4_Pos 4 /*!< PORT0 OUT: P4 Position */
\r
3489 #define PORT0_OUT_P4_Msk (0x01UL << PORT0_OUT_P4_Pos) /*!< PORT0 OUT: P4 Mask */
\r
3490 #define PORT0_OUT_P5_Pos 5 /*!< PORT0 OUT: P5 Position */
\r
3491 #define PORT0_OUT_P5_Msk (0x01UL << PORT0_OUT_P5_Pos) /*!< PORT0 OUT: P5 Mask */
\r
3492 #define PORT0_OUT_P6_Pos 6 /*!< PORT0 OUT: P6 Position */
\r
3493 #define PORT0_OUT_P6_Msk (0x01UL << PORT0_OUT_P6_Pos) /*!< PORT0 OUT: P6 Mask */
\r
3494 #define PORT0_OUT_P7_Pos 7 /*!< PORT0 OUT: P7 Position */
\r
3495 #define PORT0_OUT_P7_Msk (0x01UL << PORT0_OUT_P7_Pos) /*!< PORT0 OUT: P7 Mask */
\r
3496 #define PORT0_OUT_P8_Pos 8 /*!< PORT0 OUT: P8 Position */
\r
3497 #define PORT0_OUT_P8_Msk (0x01UL << PORT0_OUT_P8_Pos) /*!< PORT0 OUT: P8 Mask */
\r
3498 #define PORT0_OUT_P9_Pos 9 /*!< PORT0 OUT: P9 Position */
\r
3499 #define PORT0_OUT_P9_Msk (0x01UL << PORT0_OUT_P9_Pos) /*!< PORT0 OUT: P9 Mask */
\r
3500 #define PORT0_OUT_P10_Pos 10 /*!< PORT0 OUT: P10 Position */
\r
3501 #define PORT0_OUT_P10_Msk (0x01UL << PORT0_OUT_P10_Pos) /*!< PORT0 OUT: P10 Mask */
\r
3502 #define PORT0_OUT_P11_Pos 11 /*!< PORT0 OUT: P11 Position */
\r
3503 #define PORT0_OUT_P11_Msk (0x01UL << PORT0_OUT_P11_Pos) /*!< PORT0 OUT: P11 Mask */
\r
3504 #define PORT0_OUT_P12_Pos 12 /*!< PORT0 OUT: P12 Position */
\r
3505 #define PORT0_OUT_P12_Msk (0x01UL << PORT0_OUT_P12_Pos) /*!< PORT0 OUT: P12 Mask */
\r
3506 #define PORT0_OUT_P13_Pos 13 /*!< PORT0 OUT: P13 Position */
\r
3507 #define PORT0_OUT_P13_Msk (0x01UL << PORT0_OUT_P13_Pos) /*!< PORT0 OUT: P13 Mask */
\r
3508 #define PORT0_OUT_P14_Pos 14 /*!< PORT0 OUT: P14 Position */
\r
3509 #define PORT0_OUT_P14_Msk (0x01UL << PORT0_OUT_P14_Pos) /*!< PORT0 OUT: P14 Mask */
\r
3510 #define PORT0_OUT_P15_Pos 15 /*!< PORT0 OUT: P15 Position */
\r
3511 #define PORT0_OUT_P15_Msk (0x01UL << PORT0_OUT_P15_Pos) /*!< PORT0 OUT: P15 Mask */
\r
3513 /* ---------------------------------- PORT0_OMR --------------------------------- */
\r
3514 #define PORT0_OMR_PS0_Pos 0 /*!< PORT0 OMR: PS0 Position */
\r
3515 #define PORT0_OMR_PS0_Msk (0x01UL << PORT0_OMR_PS0_Pos) /*!< PORT0 OMR: PS0 Mask */
\r
3516 #define PORT0_OMR_PS1_Pos 1 /*!< PORT0 OMR: PS1 Position */
\r
3517 #define PORT0_OMR_PS1_Msk (0x01UL << PORT0_OMR_PS1_Pos) /*!< PORT0 OMR: PS1 Mask */
\r
3518 #define PORT0_OMR_PS2_Pos 2 /*!< PORT0 OMR: PS2 Position */
\r
3519 #define PORT0_OMR_PS2_Msk (0x01UL << PORT0_OMR_PS2_Pos) /*!< PORT0 OMR: PS2 Mask */
\r
3520 #define PORT0_OMR_PS3_Pos 3 /*!< PORT0 OMR: PS3 Position */
\r
3521 #define PORT0_OMR_PS3_Msk (0x01UL << PORT0_OMR_PS3_Pos) /*!< PORT0 OMR: PS3 Mask */
\r
3522 #define PORT0_OMR_PS4_Pos 4 /*!< PORT0 OMR: PS4 Position */
\r
3523 #define PORT0_OMR_PS4_Msk (0x01UL << PORT0_OMR_PS4_Pos) /*!< PORT0 OMR: PS4 Mask */
\r
3524 #define PORT0_OMR_PS5_Pos 5 /*!< PORT0 OMR: PS5 Position */
\r
3525 #define PORT0_OMR_PS5_Msk (0x01UL << PORT0_OMR_PS5_Pos) /*!< PORT0 OMR: PS5 Mask */
\r
3526 #define PORT0_OMR_PS6_Pos 6 /*!< PORT0 OMR: PS6 Position */
\r
3527 #define PORT0_OMR_PS6_Msk (0x01UL << PORT0_OMR_PS6_Pos) /*!< PORT0 OMR: PS6 Mask */
\r
3528 #define PORT0_OMR_PS7_Pos 7 /*!< PORT0 OMR: PS7 Position */
\r
3529 #define PORT0_OMR_PS7_Msk (0x01UL << PORT0_OMR_PS7_Pos) /*!< PORT0 OMR: PS7 Mask */
\r
3530 #define PORT0_OMR_PS8_Pos 8 /*!< PORT0 OMR: PS8 Position */
\r
3531 #define PORT0_OMR_PS8_Msk (0x01UL << PORT0_OMR_PS8_Pos) /*!< PORT0 OMR: PS8 Mask */
\r
3532 #define PORT0_OMR_PS9_Pos 9 /*!< PORT0 OMR: PS9 Position */
\r
3533 #define PORT0_OMR_PS9_Msk (0x01UL << PORT0_OMR_PS9_Pos) /*!< PORT0 OMR: PS9 Mask */
\r
3534 #define PORT0_OMR_PS10_Pos 10 /*!< PORT0 OMR: PS10 Position */
\r
3535 #define PORT0_OMR_PS10_Msk (0x01UL << PORT0_OMR_PS10_Pos) /*!< PORT0 OMR: PS10 Mask */
\r
3536 #define PORT0_OMR_PS11_Pos 11 /*!< PORT0 OMR: PS11 Position */
\r
3537 #define PORT0_OMR_PS11_Msk (0x01UL << PORT0_OMR_PS11_Pos) /*!< PORT0 OMR: PS11 Mask */
\r
3538 #define PORT0_OMR_PS12_Pos 12 /*!< PORT0 OMR: PS12 Position */
\r
3539 #define PORT0_OMR_PS12_Msk (0x01UL << PORT0_OMR_PS12_Pos) /*!< PORT0 OMR: PS12 Mask */
\r
3540 #define PORT0_OMR_PS13_Pos 13 /*!< PORT0 OMR: PS13 Position */
\r
3541 #define PORT0_OMR_PS13_Msk (0x01UL << PORT0_OMR_PS13_Pos) /*!< PORT0 OMR: PS13 Mask */
\r
3542 #define PORT0_OMR_PS14_Pos 14 /*!< PORT0 OMR: PS14 Position */
\r
3543 #define PORT0_OMR_PS14_Msk (0x01UL << PORT0_OMR_PS14_Pos) /*!< PORT0 OMR: PS14 Mask */
\r
3544 #define PORT0_OMR_PS15_Pos 15 /*!< PORT0 OMR: PS15 Position */
\r
3545 #define PORT0_OMR_PS15_Msk (0x01UL << PORT0_OMR_PS15_Pos) /*!< PORT0 OMR: PS15 Mask */
\r
3546 #define PORT0_OMR_PR0_Pos 16 /*!< PORT0 OMR: PR0 Position */
\r
3547 #define PORT0_OMR_PR0_Msk (0x01UL << PORT0_OMR_PR0_Pos) /*!< PORT0 OMR: PR0 Mask */
\r
3548 #define PORT0_OMR_PR1_Pos 17 /*!< PORT0 OMR: PR1 Position */
\r
3549 #define PORT0_OMR_PR1_Msk (0x01UL << PORT0_OMR_PR1_Pos) /*!< PORT0 OMR: PR1 Mask */
\r
3550 #define PORT0_OMR_PR2_Pos 18 /*!< PORT0 OMR: PR2 Position */
\r
3551 #define PORT0_OMR_PR2_Msk (0x01UL << PORT0_OMR_PR2_Pos) /*!< PORT0 OMR: PR2 Mask */
\r
3552 #define PORT0_OMR_PR3_Pos 19 /*!< PORT0 OMR: PR3 Position */
\r
3553 #define PORT0_OMR_PR3_Msk (0x01UL << PORT0_OMR_PR3_Pos) /*!< PORT0 OMR: PR3 Mask */
\r
3554 #define PORT0_OMR_PR4_Pos 20 /*!< PORT0 OMR: PR4 Position */
\r
3555 #define PORT0_OMR_PR4_Msk (0x01UL << PORT0_OMR_PR4_Pos) /*!< PORT0 OMR: PR4 Mask */
\r
3556 #define PORT0_OMR_PR5_Pos 21 /*!< PORT0 OMR: PR5 Position */
\r
3557 #define PORT0_OMR_PR5_Msk (0x01UL << PORT0_OMR_PR5_Pos) /*!< PORT0 OMR: PR5 Mask */
\r
3558 #define PORT0_OMR_PR6_Pos 22 /*!< PORT0 OMR: PR6 Position */
\r
3559 #define PORT0_OMR_PR6_Msk (0x01UL << PORT0_OMR_PR6_Pos) /*!< PORT0 OMR: PR6 Mask */
\r
3560 #define PORT0_OMR_PR7_Pos 23 /*!< PORT0 OMR: PR7 Position */
\r
3561 #define PORT0_OMR_PR7_Msk (0x01UL << PORT0_OMR_PR7_Pos) /*!< PORT0 OMR: PR7 Mask */
\r
3562 #define PORT0_OMR_PR8_Pos 24 /*!< PORT0 OMR: PR8 Position */
\r
3563 #define PORT0_OMR_PR8_Msk (0x01UL << PORT0_OMR_PR8_Pos) /*!< PORT0 OMR: PR8 Mask */
\r
3564 #define PORT0_OMR_PR9_Pos 25 /*!< PORT0 OMR: PR9 Position */
\r
3565 #define PORT0_OMR_PR9_Msk (0x01UL << PORT0_OMR_PR9_Pos) /*!< PORT0 OMR: PR9 Mask */
\r
3566 #define PORT0_OMR_PR10_Pos 26 /*!< PORT0 OMR: PR10 Position */
\r
3567 #define PORT0_OMR_PR10_Msk (0x01UL << PORT0_OMR_PR10_Pos) /*!< PORT0 OMR: PR10 Mask */
\r
3568 #define PORT0_OMR_PR11_Pos 27 /*!< PORT0 OMR: PR11 Position */
\r
3569 #define PORT0_OMR_PR11_Msk (0x01UL << PORT0_OMR_PR11_Pos) /*!< PORT0 OMR: PR11 Mask */
\r
3570 #define PORT0_OMR_PR12_Pos 28 /*!< PORT0 OMR: PR12 Position */
\r
3571 #define PORT0_OMR_PR12_Msk (0x01UL << PORT0_OMR_PR12_Pos) /*!< PORT0 OMR: PR12 Mask */
\r
3572 #define PORT0_OMR_PR13_Pos 29 /*!< PORT0 OMR: PR13 Position */
\r
3573 #define PORT0_OMR_PR13_Msk (0x01UL << PORT0_OMR_PR13_Pos) /*!< PORT0 OMR: PR13 Mask */
\r
3574 #define PORT0_OMR_PR14_Pos 30 /*!< PORT0 OMR: PR14 Position */
\r
3575 #define PORT0_OMR_PR14_Msk (0x01UL << PORT0_OMR_PR14_Pos) /*!< PORT0 OMR: PR14 Mask */
\r
3576 #define PORT0_OMR_PR15_Pos 31 /*!< PORT0 OMR: PR15 Position */
\r
3577 #define PORT0_OMR_PR15_Msk (0x01UL << PORT0_OMR_PR15_Pos) /*!< PORT0 OMR: PR15 Mask */
\r
3579 /* --------------------------------- PORT0_IOCR0 -------------------------------- */
\r
3580 #define PORT0_IOCR0_PC0_Pos 3 /*!< PORT0 IOCR0: PC0 Position */
\r
3581 #define PORT0_IOCR0_PC0_Msk (0x1fUL << PORT0_IOCR0_PC0_Pos) /*!< PORT0 IOCR0: PC0 Mask */
\r
3582 #define PORT0_IOCR0_PC1_Pos 11 /*!< PORT0 IOCR0: PC1 Position */
\r
3583 #define PORT0_IOCR0_PC1_Msk (0x1fUL << PORT0_IOCR0_PC1_Pos) /*!< PORT0 IOCR0: PC1 Mask */
\r
3584 #define PORT0_IOCR0_PC2_Pos 19 /*!< PORT0 IOCR0: PC2 Position */
\r
3585 #define PORT0_IOCR0_PC2_Msk (0x1fUL << PORT0_IOCR0_PC2_Pos) /*!< PORT0 IOCR0: PC2 Mask */
\r
3586 #define PORT0_IOCR0_PC3_Pos 27 /*!< PORT0 IOCR0: PC3 Position */
\r
3587 #define PORT0_IOCR0_PC3_Msk (0x1fUL << PORT0_IOCR0_PC3_Pos) /*!< PORT0 IOCR0: PC3 Mask */
\r
3589 /* --------------------------------- PORT0_IOCR4 -------------------------------- */
\r
3590 #define PORT0_IOCR4_PC4_Pos 3 /*!< PORT0 IOCR4: PC4 Position */
\r
3591 #define PORT0_IOCR4_PC4_Msk (0x1fUL << PORT0_IOCR4_PC4_Pos) /*!< PORT0 IOCR4: PC4 Mask */
\r
3592 #define PORT0_IOCR4_PC5_Pos 11 /*!< PORT0 IOCR4: PC5 Position */
\r
3593 #define PORT0_IOCR4_PC5_Msk (0x1fUL << PORT0_IOCR4_PC5_Pos) /*!< PORT0 IOCR4: PC5 Mask */
\r
3594 #define PORT0_IOCR4_PC6_Pos 19 /*!< PORT0 IOCR4: PC6 Position */
\r
3595 #define PORT0_IOCR4_PC6_Msk (0x1fUL << PORT0_IOCR4_PC6_Pos) /*!< PORT0 IOCR4: PC6 Mask */
\r
3596 #define PORT0_IOCR4_PC7_Pos 27 /*!< PORT0 IOCR4: PC7 Position */
\r
3597 #define PORT0_IOCR4_PC7_Msk (0x1fUL << PORT0_IOCR4_PC7_Pos) /*!< PORT0 IOCR4: PC7 Mask */
\r
3599 /* --------------------------------- PORT0_IOCR8 -------------------------------- */
\r
3600 #define PORT0_IOCR8_PC8_Pos 3 /*!< PORT0 IOCR8: PC8 Position */
\r
3601 #define PORT0_IOCR8_PC8_Msk (0x1fUL << PORT0_IOCR8_PC8_Pos) /*!< PORT0 IOCR8: PC8 Mask */
\r
3602 #define PORT0_IOCR8_PC9_Pos 11 /*!< PORT0 IOCR8: PC9 Position */
\r
3603 #define PORT0_IOCR8_PC9_Msk (0x1fUL << PORT0_IOCR8_PC9_Pos) /*!< PORT0 IOCR8: PC9 Mask */
\r
3604 #define PORT0_IOCR8_PC10_Pos 19 /*!< PORT0 IOCR8: PC10 Position */
\r
3605 #define PORT0_IOCR8_PC10_Msk (0x1fUL << PORT0_IOCR8_PC10_Pos) /*!< PORT0 IOCR8: PC10 Mask */
\r
3606 #define PORT0_IOCR8_PC11_Pos 27 /*!< PORT0 IOCR8: PC11 Position */
\r
3607 #define PORT0_IOCR8_PC11_Msk (0x1fUL << PORT0_IOCR8_PC11_Pos) /*!< PORT0 IOCR8: PC11 Mask */
\r
3609 /* -------------------------------- PORT0_IOCR12 -------------------------------- */
\r
3610 #define PORT0_IOCR12_PC12_Pos 3 /*!< PORT0 IOCR12: PC12 Position */
\r
3611 #define PORT0_IOCR12_PC12_Msk (0x1fUL << PORT0_IOCR12_PC12_Pos) /*!< PORT0 IOCR12: PC12 Mask */
\r
3612 #define PORT0_IOCR12_PC13_Pos 11 /*!< PORT0 IOCR12: PC13 Position */
\r
3613 #define PORT0_IOCR12_PC13_Msk (0x1fUL << PORT0_IOCR12_PC13_Pos) /*!< PORT0 IOCR12: PC13 Mask */
\r
3614 #define PORT0_IOCR12_PC14_Pos 19 /*!< PORT0 IOCR12: PC14 Position */
\r
3615 #define PORT0_IOCR12_PC14_Msk (0x1fUL << PORT0_IOCR12_PC14_Pos) /*!< PORT0 IOCR12: PC14 Mask */
\r
3616 #define PORT0_IOCR12_PC15_Pos 27 /*!< PORT0 IOCR12: PC15 Position */
\r
3617 #define PORT0_IOCR12_PC15_Msk (0x1fUL << PORT0_IOCR12_PC15_Pos) /*!< PORT0 IOCR12: PC15 Mask */
\r
3619 /* ---------------------------------- PORT0_IN ---------------------------------- */
\r
3620 #define PORT0_IN_P0_Pos 0 /*!< PORT0 IN: P0 Position */
\r
3621 #define PORT0_IN_P0_Msk (0x01UL << PORT0_IN_P0_Pos) /*!< PORT0 IN: P0 Mask */
\r
3622 #define PORT0_IN_P1_Pos 1 /*!< PORT0 IN: P1 Position */
\r
3623 #define PORT0_IN_P1_Msk (0x01UL << PORT0_IN_P1_Pos) /*!< PORT0 IN: P1 Mask */
\r
3624 #define PORT0_IN_P2_Pos 2 /*!< PORT0 IN: P2 Position */
\r
3625 #define PORT0_IN_P2_Msk (0x01UL << PORT0_IN_P2_Pos) /*!< PORT0 IN: P2 Mask */
\r
3626 #define PORT0_IN_P3_Pos 3 /*!< PORT0 IN: P3 Position */
\r
3627 #define PORT0_IN_P3_Msk (0x01UL << PORT0_IN_P3_Pos) /*!< PORT0 IN: P3 Mask */
\r
3628 #define PORT0_IN_P4_Pos 4 /*!< PORT0 IN: P4 Position */
\r
3629 #define PORT0_IN_P4_Msk (0x01UL << PORT0_IN_P4_Pos) /*!< PORT0 IN: P4 Mask */
\r
3630 #define PORT0_IN_P5_Pos 5 /*!< PORT0 IN: P5 Position */
\r
3631 #define PORT0_IN_P5_Msk (0x01UL << PORT0_IN_P5_Pos) /*!< PORT0 IN: P5 Mask */
\r
3632 #define PORT0_IN_P6_Pos 6 /*!< PORT0 IN: P6 Position */
\r
3633 #define PORT0_IN_P6_Msk (0x01UL << PORT0_IN_P6_Pos) /*!< PORT0 IN: P6 Mask */
\r
3634 #define PORT0_IN_P7_Pos 7 /*!< PORT0 IN: P7 Position */
\r
3635 #define PORT0_IN_P7_Msk (0x01UL << PORT0_IN_P7_Pos) /*!< PORT0 IN: P7 Mask */
\r
3636 #define PORT0_IN_P8_Pos 8 /*!< PORT0 IN: P8 Position */
\r
3637 #define PORT0_IN_P8_Msk (0x01UL << PORT0_IN_P8_Pos) /*!< PORT0 IN: P8 Mask */
\r
3638 #define PORT0_IN_P9_Pos 9 /*!< PORT0 IN: P9 Position */
\r
3639 #define PORT0_IN_P9_Msk (0x01UL << PORT0_IN_P9_Pos) /*!< PORT0 IN: P9 Mask */
\r
3640 #define PORT0_IN_P10_Pos 10 /*!< PORT0 IN: P10 Position */
\r
3641 #define PORT0_IN_P10_Msk (0x01UL << PORT0_IN_P10_Pos) /*!< PORT0 IN: P10 Mask */
\r
3642 #define PORT0_IN_P11_Pos 11 /*!< PORT0 IN: P11 Position */
\r
3643 #define PORT0_IN_P11_Msk (0x01UL << PORT0_IN_P11_Pos) /*!< PORT0 IN: P11 Mask */
\r
3644 #define PORT0_IN_P12_Pos 12 /*!< PORT0 IN: P12 Position */
\r
3645 #define PORT0_IN_P12_Msk (0x01UL << PORT0_IN_P12_Pos) /*!< PORT0 IN: P12 Mask */
\r
3646 #define PORT0_IN_P13_Pos 13 /*!< PORT0 IN: P13 Position */
\r
3647 #define PORT0_IN_P13_Msk (0x01UL << PORT0_IN_P13_Pos) /*!< PORT0 IN: P13 Mask */
\r
3648 #define PORT0_IN_P14_Pos 14 /*!< PORT0 IN: P14 Position */
\r
3649 #define PORT0_IN_P14_Msk (0x01UL << PORT0_IN_P14_Pos) /*!< PORT0 IN: P14 Mask */
\r
3650 #define PORT0_IN_P15_Pos 15 /*!< PORT0 IN: P15 Position */
\r
3651 #define PORT0_IN_P15_Msk (0x01UL << PORT0_IN_P15_Pos) /*!< PORT0 IN: P15 Mask */
\r
3653 /* --------------------------------- PORT0_PHCR0 -------------------------------- */
\r
3654 #define PORT0_PHCR0_PH0_Pos 2 /*!< PORT0 PHCR0: PH0 Position */
\r
3655 #define PORT0_PHCR0_PH0_Msk (0x01UL << PORT0_PHCR0_PH0_Pos) /*!< PORT0 PHCR0: PH0 Mask */
\r
3656 #define PORT0_PHCR0_PH1_Pos 6 /*!< PORT0 PHCR0: PH1 Position */
\r
3657 #define PORT0_PHCR0_PH1_Msk (0x01UL << PORT0_PHCR0_PH1_Pos) /*!< PORT0 PHCR0: PH1 Mask */
\r
3658 #define PORT0_PHCR0_PH2_Pos 10 /*!< PORT0 PHCR0: PH2 Position */
\r
3659 #define PORT0_PHCR0_PH2_Msk (0x01UL << PORT0_PHCR0_PH2_Pos) /*!< PORT0 PHCR0: PH2 Mask */
\r
3660 #define PORT0_PHCR0_PH3_Pos 14 /*!< PORT0 PHCR0: PH3 Position */
\r
3661 #define PORT0_PHCR0_PH3_Msk (0x01UL << PORT0_PHCR0_PH3_Pos) /*!< PORT0 PHCR0: PH3 Mask */
\r
3662 #define PORT0_PHCR0_PH4_Pos 18 /*!< PORT0 PHCR0: PH4 Position */
\r
3663 #define PORT0_PHCR0_PH4_Msk (0x01UL << PORT0_PHCR0_PH4_Pos) /*!< PORT0 PHCR0: PH4 Mask */
\r
3664 #define PORT0_PHCR0_PH5_Pos 22 /*!< PORT0 PHCR0: PH5 Position */
\r
3665 #define PORT0_PHCR0_PH5_Msk (0x01UL << PORT0_PHCR0_PH5_Pos) /*!< PORT0 PHCR0: PH5 Mask */
\r
3666 #define PORT0_PHCR0_PH6_Pos 26 /*!< PORT0 PHCR0: PH6 Position */
\r
3667 #define PORT0_PHCR0_PH6_Msk (0x01UL << PORT0_PHCR0_PH6_Pos) /*!< PORT0 PHCR0: PH6 Mask */
\r
3668 #define PORT0_PHCR0_PH7_Pos 30 /*!< PORT0 PHCR0: PH7 Position */
\r
3669 #define PORT0_PHCR0_PH7_Msk (0x01UL << PORT0_PHCR0_PH7_Pos) /*!< PORT0 PHCR0: PH7 Mask */
\r
3671 /* --------------------------------- PORT0_PHCR1 -------------------------------- */
\r
3672 #define PORT0_PHCR1_PH8_Pos 2 /*!< PORT0 PHCR1: PH8 Position */
\r
3673 #define PORT0_PHCR1_PH8_Msk (0x01UL << PORT0_PHCR1_PH8_Pos) /*!< PORT0 PHCR1: PH8 Mask */
\r
3674 #define PORT0_PHCR1_PH9_Pos 6 /*!< PORT0 PHCR1: PH9 Position */
\r
3675 #define PORT0_PHCR1_PH9_Msk (0x01UL << PORT0_PHCR1_PH9_Pos) /*!< PORT0 PHCR1: PH9 Mask */
\r
3676 #define PORT0_PHCR1_PH10_Pos 10 /*!< PORT0 PHCR1: PH10 Position */
\r
3677 #define PORT0_PHCR1_PH10_Msk (0x01UL << PORT0_PHCR1_PH10_Pos) /*!< PORT0 PHCR1: PH10 Mask */
\r
3678 #define PORT0_PHCR1_PH11_Pos 14 /*!< PORT0 PHCR1: PH11 Position */
\r
3679 #define PORT0_PHCR1_PH11_Msk (0x01UL << PORT0_PHCR1_PH11_Pos) /*!< PORT0 PHCR1: PH11 Mask */
\r
3680 #define PORT0_PHCR1_PH12_Pos 18 /*!< PORT0 PHCR1: PH12 Position */
\r
3681 #define PORT0_PHCR1_PH12_Msk (0x01UL << PORT0_PHCR1_PH12_Pos) /*!< PORT0 PHCR1: PH12 Mask */
\r
3682 #define PORT0_PHCR1_PH13_Pos 22 /*!< PORT0 PHCR1: PH13 Position */
\r
3683 #define PORT0_PHCR1_PH13_Msk (0x01UL << PORT0_PHCR1_PH13_Pos) /*!< PORT0 PHCR1: PH13 Mask */
\r
3684 #define PORT0_PHCR1_PH14_Pos 26 /*!< PORT0 PHCR1: PH14 Position */
\r
3685 #define PORT0_PHCR1_PH14_Msk (0x01UL << PORT0_PHCR1_PH14_Pos) /*!< PORT0 PHCR1: PH14 Mask */
\r
3686 #define PORT0_PHCR1_PH15_Pos 30 /*!< PORT0 PHCR1: PH15 Position */
\r
3687 #define PORT0_PHCR1_PH15_Msk (0x01UL << PORT0_PHCR1_PH15_Pos) /*!< PORT0 PHCR1: PH15 Mask */
\r
3689 /* --------------------------------- PORT0_PDISC -------------------------------- */
\r
3690 #define PORT0_PDISC_PDIS0_Pos 0 /*!< PORT0 PDISC: PDIS0 Position */
\r
3691 #define PORT0_PDISC_PDIS0_Msk (0x01UL << PORT0_PDISC_PDIS0_Pos) /*!< PORT0 PDISC: PDIS0 Mask */
\r
3692 #define PORT0_PDISC_PDIS1_Pos 1 /*!< PORT0 PDISC: PDIS1 Position */
\r
3693 #define PORT0_PDISC_PDIS1_Msk (0x01UL << PORT0_PDISC_PDIS1_Pos) /*!< PORT0 PDISC: PDIS1 Mask */
\r
3694 #define PORT0_PDISC_PDIS2_Pos 2 /*!< PORT0 PDISC: PDIS2 Position */
\r
3695 #define PORT0_PDISC_PDIS2_Msk (0x01UL << PORT0_PDISC_PDIS2_Pos) /*!< PORT0 PDISC: PDIS2 Mask */
\r
3696 #define PORT0_PDISC_PDIS3_Pos 3 /*!< PORT0 PDISC: PDIS3 Position */
\r
3697 #define PORT0_PDISC_PDIS3_Msk (0x01UL << PORT0_PDISC_PDIS3_Pos) /*!< PORT0 PDISC: PDIS3 Mask */
\r
3698 #define PORT0_PDISC_PDIS4_Pos 4 /*!< PORT0 PDISC: PDIS4 Position */
\r
3699 #define PORT0_PDISC_PDIS4_Msk (0x01UL << PORT0_PDISC_PDIS4_Pos) /*!< PORT0 PDISC: PDIS4 Mask */
\r
3700 #define PORT0_PDISC_PDIS5_Pos 5 /*!< PORT0 PDISC: PDIS5 Position */
\r
3701 #define PORT0_PDISC_PDIS5_Msk (0x01UL << PORT0_PDISC_PDIS5_Pos) /*!< PORT0 PDISC: PDIS5 Mask */
\r
3702 #define PORT0_PDISC_PDIS6_Pos 6 /*!< PORT0 PDISC: PDIS6 Position */
\r
3703 #define PORT0_PDISC_PDIS6_Msk (0x01UL << PORT0_PDISC_PDIS6_Pos) /*!< PORT0 PDISC: PDIS6 Mask */
\r
3704 #define PORT0_PDISC_PDIS7_Pos 7 /*!< PORT0 PDISC: PDIS7 Position */
\r
3705 #define PORT0_PDISC_PDIS7_Msk (0x01UL << PORT0_PDISC_PDIS7_Pos) /*!< PORT0 PDISC: PDIS7 Mask */
\r
3706 #define PORT0_PDISC_PDIS8_Pos 8 /*!< PORT0 PDISC: PDIS8 Position */
\r
3707 #define PORT0_PDISC_PDIS8_Msk (0x01UL << PORT0_PDISC_PDIS8_Pos) /*!< PORT0 PDISC: PDIS8 Mask */
\r
3708 #define PORT0_PDISC_PDIS9_Pos 9 /*!< PORT0 PDISC: PDIS9 Position */
\r
3709 #define PORT0_PDISC_PDIS9_Msk (0x01UL << PORT0_PDISC_PDIS9_Pos) /*!< PORT0 PDISC: PDIS9 Mask */
\r
3710 #define PORT0_PDISC_PDIS10_Pos 10 /*!< PORT0 PDISC: PDIS10 Position */
\r
3711 #define PORT0_PDISC_PDIS10_Msk (0x01UL << PORT0_PDISC_PDIS10_Pos) /*!< PORT0 PDISC: PDIS10 Mask */
\r
3712 #define PORT0_PDISC_PDIS11_Pos 11 /*!< PORT0 PDISC: PDIS11 Position */
\r
3713 #define PORT0_PDISC_PDIS11_Msk (0x01UL << PORT0_PDISC_PDIS11_Pos) /*!< PORT0 PDISC: PDIS11 Mask */
\r
3714 #define PORT0_PDISC_PDIS12_Pos 12 /*!< PORT0 PDISC: PDIS12 Position */
\r
3715 #define PORT0_PDISC_PDIS12_Msk (0x01UL << PORT0_PDISC_PDIS12_Pos) /*!< PORT0 PDISC: PDIS12 Mask */
\r
3716 #define PORT0_PDISC_PDIS13_Pos 13 /*!< PORT0 PDISC: PDIS13 Position */
\r
3717 #define PORT0_PDISC_PDIS13_Msk (0x01UL << PORT0_PDISC_PDIS13_Pos) /*!< PORT0 PDISC: PDIS13 Mask */
\r
3718 #define PORT0_PDISC_PDIS14_Pos 14 /*!< PORT0 PDISC: PDIS14 Position */
\r
3719 #define PORT0_PDISC_PDIS14_Msk (0x01UL << PORT0_PDISC_PDIS14_Pos) /*!< PORT0 PDISC: PDIS14 Mask */
\r
3720 #define PORT0_PDISC_PDIS15_Pos 15 /*!< PORT0 PDISC: PDIS15 Position */
\r
3721 #define PORT0_PDISC_PDIS15_Msk (0x01UL << PORT0_PDISC_PDIS15_Pos) /*!< PORT0 PDISC: PDIS15 Mask */
\r
3723 /* ---------------------------------- PORT0_PPS --------------------------------- */
\r
3724 #define PORT0_PPS_PPS0_Pos 0 /*!< PORT0 PPS: PPS0 Position */
\r
3725 #define PORT0_PPS_PPS0_Msk (0x01UL << PORT0_PPS_PPS0_Pos) /*!< PORT0 PPS: PPS0 Mask */
\r
3726 #define PORT0_PPS_PPS1_Pos 1 /*!< PORT0 PPS: PPS1 Position */
\r
3727 #define PORT0_PPS_PPS1_Msk (0x01UL << PORT0_PPS_PPS1_Pos) /*!< PORT0 PPS: PPS1 Mask */
\r
3728 #define PORT0_PPS_PPS2_Pos 2 /*!< PORT0 PPS: PPS2 Position */
\r
3729 #define PORT0_PPS_PPS2_Msk (0x01UL << PORT0_PPS_PPS2_Pos) /*!< PORT0 PPS: PPS2 Mask */
\r
3730 #define PORT0_PPS_PPS3_Pos 3 /*!< PORT0 PPS: PPS3 Position */
\r
3731 #define PORT0_PPS_PPS3_Msk (0x01UL << PORT0_PPS_PPS3_Pos) /*!< PORT0 PPS: PPS3 Mask */
\r
3732 #define PORT0_PPS_PPS4_Pos 4 /*!< PORT0 PPS: PPS4 Position */
\r
3733 #define PORT0_PPS_PPS4_Msk (0x01UL << PORT0_PPS_PPS4_Pos) /*!< PORT0 PPS: PPS4 Mask */
\r
3734 #define PORT0_PPS_PPS5_Pos 5 /*!< PORT0 PPS: PPS5 Position */
\r
3735 #define PORT0_PPS_PPS5_Msk (0x01UL << PORT0_PPS_PPS5_Pos) /*!< PORT0 PPS: PPS5 Mask */
\r
3736 #define PORT0_PPS_PPS6_Pos 6 /*!< PORT0 PPS: PPS6 Position */
\r
3737 #define PORT0_PPS_PPS6_Msk (0x01UL << PORT0_PPS_PPS6_Pos) /*!< PORT0 PPS: PPS6 Mask */
\r
3738 #define PORT0_PPS_PPS7_Pos 7 /*!< PORT0 PPS: PPS7 Position */
\r
3739 #define PORT0_PPS_PPS7_Msk (0x01UL << PORT0_PPS_PPS7_Pos) /*!< PORT0 PPS: PPS7 Mask */
\r
3740 #define PORT0_PPS_PPS8_Pos 8 /*!< PORT0 PPS: PPS8 Position */
\r
3741 #define PORT0_PPS_PPS8_Msk (0x01UL << PORT0_PPS_PPS8_Pos) /*!< PORT0 PPS: PPS8 Mask */
\r
3742 #define PORT0_PPS_PPS9_Pos 9 /*!< PORT0 PPS: PPS9 Position */
\r
3743 #define PORT0_PPS_PPS9_Msk (0x01UL << PORT0_PPS_PPS9_Pos) /*!< PORT0 PPS: PPS9 Mask */
\r
3744 #define PORT0_PPS_PPS10_Pos 10 /*!< PORT0 PPS: PPS10 Position */
\r
3745 #define PORT0_PPS_PPS10_Msk (0x01UL << PORT0_PPS_PPS10_Pos) /*!< PORT0 PPS: PPS10 Mask */
\r
3746 #define PORT0_PPS_PPS11_Pos 11 /*!< PORT0 PPS: PPS11 Position */
\r
3747 #define PORT0_PPS_PPS11_Msk (0x01UL << PORT0_PPS_PPS11_Pos) /*!< PORT0 PPS: PPS11 Mask */
\r
3748 #define PORT0_PPS_PPS12_Pos 12 /*!< PORT0 PPS: PPS12 Position */
\r
3749 #define PORT0_PPS_PPS12_Msk (0x01UL << PORT0_PPS_PPS12_Pos) /*!< PORT0 PPS: PPS12 Mask */
\r
3750 #define PORT0_PPS_PPS13_Pos 13 /*!< PORT0 PPS: PPS13 Position */
\r
3751 #define PORT0_PPS_PPS13_Msk (0x01UL << PORT0_PPS_PPS13_Pos) /*!< PORT0 PPS: PPS13 Mask */
\r
3752 #define PORT0_PPS_PPS14_Pos 14 /*!< PORT0 PPS: PPS14 Position */
\r
3753 #define PORT0_PPS_PPS14_Msk (0x01UL << PORT0_PPS_PPS14_Pos) /*!< PORT0 PPS: PPS14 Mask */
\r
3754 #define PORT0_PPS_PPS15_Pos 15 /*!< PORT0 PPS: PPS15 Position */
\r
3755 #define PORT0_PPS_PPS15_Msk (0x01UL << PORT0_PPS_PPS15_Pos) /*!< PORT0 PPS: PPS15 Mask */
\r
3757 /* --------------------------------- PORT0_HWSEL -------------------------------- */
\r
3758 #define PORT0_HWSEL_HW0_Pos 0 /*!< PORT0 HWSEL: HW0 Position */
\r
3759 #define PORT0_HWSEL_HW0_Msk (0x03UL << PORT0_HWSEL_HW0_Pos) /*!< PORT0 HWSEL: HW0 Mask */
\r
3760 #define PORT0_HWSEL_HW1_Pos 2 /*!< PORT0 HWSEL: HW1 Position */
\r
3761 #define PORT0_HWSEL_HW1_Msk (0x03UL << PORT0_HWSEL_HW1_Pos) /*!< PORT0 HWSEL: HW1 Mask */
\r
3762 #define PORT0_HWSEL_HW2_Pos 4 /*!< PORT0 HWSEL: HW2 Position */
\r
3763 #define PORT0_HWSEL_HW2_Msk (0x03UL << PORT0_HWSEL_HW2_Pos) /*!< PORT0 HWSEL: HW2 Mask */
\r
3764 #define PORT0_HWSEL_HW3_Pos 6 /*!< PORT0 HWSEL: HW3 Position */
\r
3765 #define PORT0_HWSEL_HW3_Msk (0x03UL << PORT0_HWSEL_HW3_Pos) /*!< PORT0 HWSEL: HW3 Mask */
\r
3766 #define PORT0_HWSEL_HW4_Pos 8 /*!< PORT0 HWSEL: HW4 Position */
\r
3767 #define PORT0_HWSEL_HW4_Msk (0x03UL << PORT0_HWSEL_HW4_Pos) /*!< PORT0 HWSEL: HW4 Mask */
\r
3768 #define PORT0_HWSEL_HW5_Pos 10 /*!< PORT0 HWSEL: HW5 Position */
\r
3769 #define PORT0_HWSEL_HW5_Msk (0x03UL << PORT0_HWSEL_HW5_Pos) /*!< PORT0 HWSEL: HW5 Mask */
\r
3770 #define PORT0_HWSEL_HW6_Pos 12 /*!< PORT0 HWSEL: HW6 Position */
\r
3771 #define PORT0_HWSEL_HW6_Msk (0x03UL << PORT0_HWSEL_HW6_Pos) /*!< PORT0 HWSEL: HW6 Mask */
\r
3772 #define PORT0_HWSEL_HW7_Pos 14 /*!< PORT0 HWSEL: HW7 Position */
\r
3773 #define PORT0_HWSEL_HW7_Msk (0x03UL << PORT0_HWSEL_HW7_Pos) /*!< PORT0 HWSEL: HW7 Mask */
\r
3774 #define PORT0_HWSEL_HW8_Pos 16 /*!< PORT0 HWSEL: HW8 Position */
\r
3775 #define PORT0_HWSEL_HW8_Msk (0x03UL << PORT0_HWSEL_HW8_Pos) /*!< PORT0 HWSEL: HW8 Mask */
\r
3776 #define PORT0_HWSEL_HW9_Pos 18 /*!< PORT0 HWSEL: HW9 Position */
\r
3777 #define PORT0_HWSEL_HW9_Msk (0x03UL << PORT0_HWSEL_HW9_Pos) /*!< PORT0 HWSEL: HW9 Mask */
\r
3778 #define PORT0_HWSEL_HW10_Pos 20 /*!< PORT0 HWSEL: HW10 Position */
\r
3779 #define PORT0_HWSEL_HW10_Msk (0x03UL << PORT0_HWSEL_HW10_Pos) /*!< PORT0 HWSEL: HW10 Mask */
\r
3780 #define PORT0_HWSEL_HW11_Pos 22 /*!< PORT0 HWSEL: HW11 Position */
\r
3781 #define PORT0_HWSEL_HW11_Msk (0x03UL << PORT0_HWSEL_HW11_Pos) /*!< PORT0 HWSEL: HW11 Mask */
\r
3782 #define PORT0_HWSEL_HW12_Pos 24 /*!< PORT0 HWSEL: HW12 Position */
\r
3783 #define PORT0_HWSEL_HW12_Msk (0x03UL << PORT0_HWSEL_HW12_Pos) /*!< PORT0 HWSEL: HW12 Mask */
\r
3784 #define PORT0_HWSEL_HW13_Pos 26 /*!< PORT0 HWSEL: HW13 Position */
\r
3785 #define PORT0_HWSEL_HW13_Msk (0x03UL << PORT0_HWSEL_HW13_Pos) /*!< PORT0 HWSEL: HW13 Mask */
\r
3786 #define PORT0_HWSEL_HW14_Pos 28 /*!< PORT0 HWSEL: HW14 Position */
\r
3787 #define PORT0_HWSEL_HW14_Msk (0x03UL << PORT0_HWSEL_HW14_Pos) /*!< PORT0 HWSEL: HW14 Mask */
\r
3788 #define PORT0_HWSEL_HW15_Pos 30 /*!< PORT0 HWSEL: HW15 Position */
\r
3789 #define PORT0_HWSEL_HW15_Msk (0x03UL << PORT0_HWSEL_HW15_Pos) /*!< PORT0 HWSEL: HW15 Mask */
\r
3792 /* ================================================================================ */
\r
3793 /* ================ struct 'PORT1' Position & Mask ================ */
\r
3794 /* ================================================================================ */
\r
3797 /* ---------------------------------- PORT1_OUT --------------------------------- */
\r
3798 #define PORT1_OUT_P0_Pos 0 /*!< PORT1 OUT: P0 Position */
\r
3799 #define PORT1_OUT_P0_Msk (0x01UL << PORT1_OUT_P0_Pos) /*!< PORT1 OUT: P0 Mask */
\r
3800 #define PORT1_OUT_P1_Pos 1 /*!< PORT1 OUT: P1 Position */
\r
3801 #define PORT1_OUT_P1_Msk (0x01UL << PORT1_OUT_P1_Pos) /*!< PORT1 OUT: P1 Mask */
\r
3802 #define PORT1_OUT_P2_Pos 2 /*!< PORT1 OUT: P2 Position */
\r
3803 #define PORT1_OUT_P2_Msk (0x01UL << PORT1_OUT_P2_Pos) /*!< PORT1 OUT: P2 Mask */
\r
3804 #define PORT1_OUT_P3_Pos 3 /*!< PORT1 OUT: P3 Position */
\r
3805 #define PORT1_OUT_P3_Msk (0x01UL << PORT1_OUT_P3_Pos) /*!< PORT1 OUT: P3 Mask */
\r
3806 #define PORT1_OUT_P4_Pos 4 /*!< PORT1 OUT: P4 Position */
\r
3807 #define PORT1_OUT_P4_Msk (0x01UL << PORT1_OUT_P4_Pos) /*!< PORT1 OUT: P4 Mask */
\r
3808 #define PORT1_OUT_P5_Pos 5 /*!< PORT1 OUT: P5 Position */
\r
3809 #define PORT1_OUT_P5_Msk (0x01UL << PORT1_OUT_P5_Pos) /*!< PORT1 OUT: P5 Mask */
\r
3811 /* ---------------------------------- PORT1_OMR --------------------------------- */
\r
3812 #define PORT1_OMR_PS0_Pos 0 /*!< PORT1 OMR: PS0 Position */
\r
3813 #define PORT1_OMR_PS0_Msk (0x01UL << PORT1_OMR_PS0_Pos) /*!< PORT1 OMR: PS0 Mask */
\r
3814 #define PORT1_OMR_PS1_Pos 1 /*!< PORT1 OMR: PS1 Position */
\r
3815 #define PORT1_OMR_PS1_Msk (0x01UL << PORT1_OMR_PS1_Pos) /*!< PORT1 OMR: PS1 Mask */
\r
3816 #define PORT1_OMR_PS2_Pos 2 /*!< PORT1 OMR: PS2 Position */
\r
3817 #define PORT1_OMR_PS2_Msk (0x01UL << PORT1_OMR_PS2_Pos) /*!< PORT1 OMR: PS2 Mask */
\r
3818 #define PORT1_OMR_PS3_Pos 3 /*!< PORT1 OMR: PS3 Position */
\r
3819 #define PORT1_OMR_PS3_Msk (0x01UL << PORT1_OMR_PS3_Pos) /*!< PORT1 OMR: PS3 Mask */
\r
3820 #define PORT1_OMR_PS4_Pos 4 /*!< PORT1 OMR: PS4 Position */
\r
3821 #define PORT1_OMR_PS4_Msk (0x01UL << PORT1_OMR_PS4_Pos) /*!< PORT1 OMR: PS4 Mask */
\r
3822 #define PORT1_OMR_PS5_Pos 5 /*!< PORT1 OMR: PS5 Position */
\r
3823 #define PORT1_OMR_PS5_Msk (0x01UL << PORT1_OMR_PS5_Pos) /*!< PORT1 OMR: PS5 Mask */
\r
3824 #define PORT1_OMR_PR0_Pos 16 /*!< PORT1 OMR: PR0 Position */
\r
3825 #define PORT1_OMR_PR0_Msk (0x01UL << PORT1_OMR_PR0_Pos) /*!< PORT1 OMR: PR0 Mask */
\r
3826 #define PORT1_OMR_PR1_Pos 17 /*!< PORT1 OMR: PR1 Position */
\r
3827 #define PORT1_OMR_PR1_Msk (0x01UL << PORT1_OMR_PR1_Pos) /*!< PORT1 OMR: PR1 Mask */
\r
3828 #define PORT1_OMR_PR2_Pos 18 /*!< PORT1 OMR: PR2 Position */
\r
3829 #define PORT1_OMR_PR2_Msk (0x01UL << PORT1_OMR_PR2_Pos) /*!< PORT1 OMR: PR2 Mask */
\r
3830 #define PORT1_OMR_PR3_Pos 19 /*!< PORT1 OMR: PR3 Position */
\r
3831 #define PORT1_OMR_PR3_Msk (0x01UL << PORT1_OMR_PR3_Pos) /*!< PORT1 OMR: PR3 Mask */
\r
3832 #define PORT1_OMR_PR4_Pos 20 /*!< PORT1 OMR: PR4 Position */
\r
3833 #define PORT1_OMR_PR4_Msk (0x01UL << PORT1_OMR_PR4_Pos) /*!< PORT1 OMR: PR4 Mask */
\r
3834 #define PORT1_OMR_PR5_Pos 21 /*!< PORT1 OMR: PR5 Position */
\r
3835 #define PORT1_OMR_PR5_Msk (0x01UL << PORT1_OMR_PR5_Pos) /*!< PORT1 OMR: PR5 Mask */
\r
3837 /* --------------------------------- PORT1_IOCR0 -------------------------------- */
\r
3838 #define PORT1_IOCR0_PC0_Pos 3 /*!< PORT1 IOCR0: PC0 Position */
\r
3839 #define PORT1_IOCR0_PC0_Msk (0x1fUL << PORT1_IOCR0_PC0_Pos) /*!< PORT1 IOCR0: PC0 Mask */
\r
3840 #define PORT1_IOCR0_PC1_Pos 11 /*!< PORT1 IOCR0: PC1 Position */
\r
3841 #define PORT1_IOCR0_PC1_Msk (0x1fUL << PORT1_IOCR0_PC1_Pos) /*!< PORT1 IOCR0: PC1 Mask */
\r
3842 #define PORT1_IOCR0_PC2_Pos 19 /*!< PORT1 IOCR0: PC2 Position */
\r
3843 #define PORT1_IOCR0_PC2_Msk (0x1fUL << PORT1_IOCR0_PC2_Pos) /*!< PORT1 IOCR0: PC2 Mask */
\r
3844 #define PORT1_IOCR0_PC3_Pos 27 /*!< PORT1 IOCR0: PC3 Position */
\r
3845 #define PORT1_IOCR0_PC3_Msk (0x1fUL << PORT1_IOCR0_PC3_Pos) /*!< PORT1 IOCR0: PC3 Mask */
\r
3847 /* --------------------------------- PORT1_IOCR4 -------------------------------- */
\r
3848 #define PORT1_IOCR4_PC4_Pos 3 /*!< PORT1 IOCR4: PC4 Position */
\r
3849 #define PORT1_IOCR4_PC4_Msk (0x1fUL << PORT1_IOCR4_PC4_Pos) /*!< PORT1 IOCR4: PC4 Mask */
\r
3850 #define PORT1_IOCR4_PC5_Pos 11 /*!< PORT1 IOCR4: PC5 Position */
\r
3851 #define PORT1_IOCR4_PC5_Msk (0x1fUL << PORT1_IOCR4_PC5_Pos) /*!< PORT1 IOCR4: PC5 Mask */
\r
3853 /* ---------------------------------- PORT1_IN ---------------------------------- */
\r
3854 #define PORT1_IN_P0_Pos 0 /*!< PORT1 IN: P0 Position */
\r
3855 #define PORT1_IN_P0_Msk (0x01UL << PORT1_IN_P0_Pos) /*!< PORT1 IN: P0 Mask */
\r
3856 #define PORT1_IN_P1_Pos 1 /*!< PORT1 IN: P1 Position */
\r
3857 #define PORT1_IN_P1_Msk (0x01UL << PORT1_IN_P1_Pos) /*!< PORT1 IN: P1 Mask */
\r
3858 #define PORT1_IN_P2_Pos 2 /*!< PORT1 IN: P2 Position */
\r
3859 #define PORT1_IN_P2_Msk (0x01UL << PORT1_IN_P2_Pos) /*!< PORT1 IN: P2 Mask */
\r
3860 #define PORT1_IN_P3_Pos 3 /*!< PORT1 IN: P3 Position */
\r
3861 #define PORT1_IN_P3_Msk (0x01UL << PORT1_IN_P3_Pos) /*!< PORT1 IN: P3 Mask */
\r
3862 #define PORT1_IN_P4_Pos 4 /*!< PORT1 IN: P4 Position */
\r
3863 #define PORT1_IN_P4_Msk (0x01UL << PORT1_IN_P4_Pos) /*!< PORT1 IN: P4 Mask */
\r
3864 #define PORT1_IN_P5_Pos 5 /*!< PORT1 IN: P5 Position */
\r
3865 #define PORT1_IN_P5_Msk (0x01UL << PORT1_IN_P5_Pos) /*!< PORT1 IN: P5 Mask */
\r
3867 /* --------------------------------- PORT1_PHCR0 -------------------------------- */
\r
3868 #define PORT1_PHCR0_PH0_Pos 2 /*!< PORT1 PHCR0: PH0 Position */
\r
3869 #define PORT1_PHCR0_PH0_Msk (0x01UL << PORT1_PHCR0_PH0_Pos) /*!< PORT1 PHCR0: PH0 Mask */
\r
3870 #define PORT1_PHCR0_PH1_Pos 6 /*!< PORT1 PHCR0: PH1 Position */
\r
3871 #define PORT1_PHCR0_PH1_Msk (0x01UL << PORT1_PHCR0_PH1_Pos) /*!< PORT1 PHCR0: PH1 Mask */
\r
3872 #define PORT1_PHCR0_PH2_Pos 10 /*!< PORT1 PHCR0: PH2 Position */
\r
3873 #define PORT1_PHCR0_PH2_Msk (0x01UL << PORT1_PHCR0_PH2_Pos) /*!< PORT1 PHCR0: PH2 Mask */
\r
3874 #define PORT1_PHCR0_PH3_Pos 14 /*!< PORT1 PHCR0: PH3 Position */
\r
3875 #define PORT1_PHCR0_PH3_Msk (0x01UL << PORT1_PHCR0_PH3_Pos) /*!< PORT1 PHCR0: PH3 Mask */
\r
3876 #define PORT1_PHCR0_PH4_Pos 18 /*!< PORT1 PHCR0: PH4 Position */
\r
3877 #define PORT1_PHCR0_PH4_Msk (0x01UL << PORT1_PHCR0_PH4_Pos) /*!< PORT1 PHCR0: PH4 Mask */
\r
3878 #define PORT1_PHCR0_PH5_Pos 22 /*!< PORT1 PHCR0: PH5 Position */
\r
3879 #define PORT1_PHCR0_PH5_Msk (0x01UL << PORT1_PHCR0_PH5_Pos) /*!< PORT1 PHCR0: PH5 Mask */
\r
3881 /* --------------------------------- PORT1_PDISC -------------------------------- */
\r
3882 #define PORT1_PDISC_PDIS0_Pos 0 /*!< PORT1 PDISC: PDIS0 Position */
\r
3883 #define PORT1_PDISC_PDIS0_Msk (0x01UL << PORT1_PDISC_PDIS0_Pos) /*!< PORT1 PDISC: PDIS0 Mask */
\r
3884 #define PORT1_PDISC_PDIS1_Pos 1 /*!< PORT1 PDISC: PDIS1 Position */
\r
3885 #define PORT1_PDISC_PDIS1_Msk (0x01UL << PORT1_PDISC_PDIS1_Pos) /*!< PORT1 PDISC: PDIS1 Mask */
\r
3886 #define PORT1_PDISC_PDIS2_Pos 2 /*!< PORT1 PDISC: PDIS2 Position */
\r
3887 #define PORT1_PDISC_PDIS2_Msk (0x01UL << PORT1_PDISC_PDIS2_Pos) /*!< PORT1 PDISC: PDIS2 Mask */
\r
3888 #define PORT1_PDISC_PDIS3_Pos 3 /*!< PORT1 PDISC: PDIS3 Position */
\r
3889 #define PORT1_PDISC_PDIS3_Msk (0x01UL << PORT1_PDISC_PDIS3_Pos) /*!< PORT1 PDISC: PDIS3 Mask */
\r
3890 #define PORT1_PDISC_PDIS4_Pos 4 /*!< PORT1 PDISC: PDIS4 Position */
\r
3891 #define PORT1_PDISC_PDIS4_Msk (0x01UL << PORT1_PDISC_PDIS4_Pos) /*!< PORT1 PDISC: PDIS4 Mask */
\r
3892 #define PORT1_PDISC_PDIS5_Pos 5 /*!< PORT1 PDISC: PDIS5 Position */
\r
3893 #define PORT1_PDISC_PDIS5_Msk (0x01UL << PORT1_PDISC_PDIS5_Pos) /*!< PORT1 PDISC: PDIS5 Mask */
\r
3895 /* ---------------------------------- PORT1_PPS --------------------------------- */
\r
3896 #define PORT1_PPS_PPS0_Pos 0 /*!< PORT1 PPS: PPS0 Position */
\r
3897 #define PORT1_PPS_PPS0_Msk (0x01UL << PORT1_PPS_PPS0_Pos) /*!< PORT1 PPS: PPS0 Mask */
\r
3898 #define PORT1_PPS_PPS1_Pos 1 /*!< PORT1 PPS: PPS1 Position */
\r
3899 #define PORT1_PPS_PPS1_Msk (0x01UL << PORT1_PPS_PPS1_Pos) /*!< PORT1 PPS: PPS1 Mask */
\r
3900 #define PORT1_PPS_PPS2_Pos 2 /*!< PORT1 PPS: PPS2 Position */
\r
3901 #define PORT1_PPS_PPS2_Msk (0x01UL << PORT1_PPS_PPS2_Pos) /*!< PORT1 PPS: PPS2 Mask */
\r
3902 #define PORT1_PPS_PPS3_Pos 3 /*!< PORT1 PPS: PPS3 Position */
\r
3903 #define PORT1_PPS_PPS3_Msk (0x01UL << PORT1_PPS_PPS3_Pos) /*!< PORT1 PPS: PPS3 Mask */
\r
3904 #define PORT1_PPS_PPS4_Pos 4 /*!< PORT1 PPS: PPS4 Position */
\r
3905 #define PORT1_PPS_PPS4_Msk (0x01UL << PORT1_PPS_PPS4_Pos) /*!< PORT1 PPS: PPS4 Mask */
\r
3906 #define PORT1_PPS_PPS5_Pos 5 /*!< PORT1 PPS: PPS5 Position */
\r
3907 #define PORT1_PPS_PPS5_Msk (0x01UL << PORT1_PPS_PPS5_Pos) /*!< PORT1 PPS: PPS5 Mask */
\r
3909 /* --------------------------------- PORT1_HWSEL -------------------------------- */
\r
3910 #define PORT1_HWSEL_HW0_Pos 0 /*!< PORT1 HWSEL: HW0 Position */
\r
3911 #define PORT1_HWSEL_HW0_Msk (0x03UL << PORT1_HWSEL_HW0_Pos) /*!< PORT1 HWSEL: HW0 Mask */
\r
3912 #define PORT1_HWSEL_HW1_Pos 2 /*!< PORT1 HWSEL: HW1 Position */
\r
3913 #define PORT1_HWSEL_HW1_Msk (0x03UL << PORT1_HWSEL_HW1_Pos) /*!< PORT1 HWSEL: HW1 Mask */
\r
3914 #define PORT1_HWSEL_HW2_Pos 4 /*!< PORT1 HWSEL: HW2 Position */
\r
3915 #define PORT1_HWSEL_HW2_Msk (0x03UL << PORT1_HWSEL_HW2_Pos) /*!< PORT1 HWSEL: HW2 Mask */
\r
3916 #define PORT1_HWSEL_HW3_Pos 6 /*!< PORT1 HWSEL: HW3 Position */
\r
3917 #define PORT1_HWSEL_HW3_Msk (0x03UL << PORT1_HWSEL_HW3_Pos) /*!< PORT1 HWSEL: HW3 Mask */
\r
3918 #define PORT1_HWSEL_HW4_Pos 8 /*!< PORT1 HWSEL: HW4 Position */
\r
3919 #define PORT1_HWSEL_HW4_Msk (0x03UL << PORT1_HWSEL_HW4_Pos) /*!< PORT1 HWSEL: HW4 Mask */
\r
3920 #define PORT1_HWSEL_HW5_Pos 10 /*!< PORT1 HWSEL: HW5 Position */
\r
3921 #define PORT1_HWSEL_HW5_Msk (0x03UL << PORT1_HWSEL_HW5_Pos) /*!< PORT1 HWSEL: HW5 Mask */
\r
3924 /* ================================================================================ */
\r
3925 /* ================ struct 'PORT2' Position & Mask ================ */
\r
3926 /* ================================================================================ */
\r
3929 /* ---------------------------------- PORT2_OUT --------------------------------- */
\r
3930 #define PORT2_OUT_P0_Pos 0 /*!< PORT2 OUT: P0 Position */
\r
3931 #define PORT2_OUT_P0_Msk (0x01UL << PORT2_OUT_P0_Pos) /*!< PORT2 OUT: P0 Mask */
\r
3932 #define PORT2_OUT_P1_Pos 1 /*!< PORT2 OUT: P1 Position */
\r
3933 #define PORT2_OUT_P1_Msk (0x01UL << PORT2_OUT_P1_Pos) /*!< PORT2 OUT: P1 Mask */
\r
3934 #define PORT2_OUT_P2_Pos 2 /*!< PORT2 OUT: P2 Position */
\r
3935 #define PORT2_OUT_P2_Msk (0x01UL << PORT2_OUT_P2_Pos) /*!< PORT2 OUT: P2 Mask */
\r
3936 #define PORT2_OUT_P3_Pos 3 /*!< PORT2 OUT: P3 Position */
\r
3937 #define PORT2_OUT_P3_Msk (0x01UL << PORT2_OUT_P3_Pos) /*!< PORT2 OUT: P3 Mask */
\r
3938 #define PORT2_OUT_P4_Pos 4 /*!< PORT2 OUT: P4 Position */
\r
3939 #define PORT2_OUT_P4_Msk (0x01UL << PORT2_OUT_P4_Pos) /*!< PORT2 OUT: P4 Mask */
\r
3940 #define PORT2_OUT_P5_Pos 5 /*!< PORT2 OUT: P5 Position */
\r
3941 #define PORT2_OUT_P5_Msk (0x01UL << PORT2_OUT_P5_Pos) /*!< PORT2 OUT: P5 Mask */
\r
3942 #define PORT2_OUT_P6_Pos 6 /*!< PORT2 OUT: P6 Position */
\r
3943 #define PORT2_OUT_P6_Msk (0x01UL << PORT2_OUT_P6_Pos) /*!< PORT2 OUT: P6 Mask */
\r
3944 #define PORT2_OUT_P7_Pos 7 /*!< PORT2 OUT: P7 Position */
\r
3945 #define PORT2_OUT_P7_Msk (0x01UL << PORT2_OUT_P7_Pos) /*!< PORT2 OUT: P7 Mask */
\r
3946 #define PORT2_OUT_P8_Pos 8 /*!< PORT2 OUT: P8 Position */
\r
3947 #define PORT2_OUT_P8_Msk (0x01UL << PORT2_OUT_P8_Pos) /*!< PORT2 OUT: P8 Mask */
\r
3948 #define PORT2_OUT_P9_Pos 9 /*!< PORT2 OUT: P9 Position */
\r
3949 #define PORT2_OUT_P9_Msk (0x01UL << PORT2_OUT_P9_Pos) /*!< PORT2 OUT: P9 Mask */
\r
3950 #define PORT2_OUT_P10_Pos 10 /*!< PORT2 OUT: P10 Position */
\r
3951 #define PORT2_OUT_P10_Msk (0x01UL << PORT2_OUT_P10_Pos) /*!< PORT2 OUT: P10 Mask */
\r
3952 #define PORT2_OUT_P11_Pos 11 /*!< PORT2 OUT: P11 Position */
\r
3953 #define PORT2_OUT_P11_Msk (0x01UL << PORT2_OUT_P11_Pos) /*!< PORT2 OUT: P11 Mask */
\r
3955 /* ---------------------------------- PORT2_OMR --------------------------------- */
\r
3956 #define PORT2_OMR_PS0_Pos 0 /*!< PORT2 OMR: PS0 Position */
\r
3957 #define PORT2_OMR_PS0_Msk (0x01UL << PORT2_OMR_PS0_Pos) /*!< PORT2 OMR: PS0 Mask */
\r
3958 #define PORT2_OMR_PS1_Pos 1 /*!< PORT2 OMR: PS1 Position */
\r
3959 #define PORT2_OMR_PS1_Msk (0x01UL << PORT2_OMR_PS1_Pos) /*!< PORT2 OMR: PS1 Mask */
\r
3960 #define PORT2_OMR_PS2_Pos 2 /*!< PORT2 OMR: PS2 Position */
\r
3961 #define PORT2_OMR_PS2_Msk (0x01UL << PORT2_OMR_PS2_Pos) /*!< PORT2 OMR: PS2 Mask */
\r
3962 #define PORT2_OMR_PS3_Pos 3 /*!< PORT2 OMR: PS3 Position */
\r
3963 #define PORT2_OMR_PS3_Msk (0x01UL << PORT2_OMR_PS3_Pos) /*!< PORT2 OMR: PS3 Mask */
\r
3964 #define PORT2_OMR_PS4_Pos 4 /*!< PORT2 OMR: PS4 Position */
\r
3965 #define PORT2_OMR_PS4_Msk (0x01UL << PORT2_OMR_PS4_Pos) /*!< PORT2 OMR: PS4 Mask */
\r
3966 #define PORT2_OMR_PS5_Pos 5 /*!< PORT2 OMR: PS5 Position */
\r
3967 #define PORT2_OMR_PS5_Msk (0x01UL << PORT2_OMR_PS5_Pos) /*!< PORT2 OMR: PS5 Mask */
\r
3968 #define PORT2_OMR_PS6_Pos 6 /*!< PORT2 OMR: PS6 Position */
\r
3969 #define PORT2_OMR_PS6_Msk (0x01UL << PORT2_OMR_PS6_Pos) /*!< PORT2 OMR: PS6 Mask */
\r
3970 #define PORT2_OMR_PS7_Pos 7 /*!< PORT2 OMR: PS7 Position */
\r
3971 #define PORT2_OMR_PS7_Msk (0x01UL << PORT2_OMR_PS7_Pos) /*!< PORT2 OMR: PS7 Mask */
\r
3972 #define PORT2_OMR_PS8_Pos 8 /*!< PORT2 OMR: PS8 Position */
\r
3973 #define PORT2_OMR_PS8_Msk (0x01UL << PORT2_OMR_PS8_Pos) /*!< PORT2 OMR: PS8 Mask */
\r
3974 #define PORT2_OMR_PS9_Pos 9 /*!< PORT2 OMR: PS9 Position */
\r
3975 #define PORT2_OMR_PS9_Msk (0x01UL << PORT2_OMR_PS9_Pos) /*!< PORT2 OMR: PS9 Mask */
\r
3976 #define PORT2_OMR_PS10_Pos 10 /*!< PORT2 OMR: PS10 Position */
\r
3977 #define PORT2_OMR_PS10_Msk (0x01UL << PORT2_OMR_PS10_Pos) /*!< PORT2 OMR: PS10 Mask */
\r
3978 #define PORT2_OMR_PS11_Pos 11 /*!< PORT2 OMR: PS11 Position */
\r
3979 #define PORT2_OMR_PS11_Msk (0x01UL << PORT2_OMR_PS11_Pos) /*!< PORT2 OMR: PS11 Mask */
\r
3980 #define PORT2_OMR_PR0_Pos 16 /*!< PORT2 OMR: PR0 Position */
\r
3981 #define PORT2_OMR_PR0_Msk (0x01UL << PORT2_OMR_PR0_Pos) /*!< PORT2 OMR: PR0 Mask */
\r
3982 #define PORT2_OMR_PR1_Pos 17 /*!< PORT2 OMR: PR1 Position */
\r
3983 #define PORT2_OMR_PR1_Msk (0x01UL << PORT2_OMR_PR1_Pos) /*!< PORT2 OMR: PR1 Mask */
\r
3984 #define PORT2_OMR_PR2_Pos 18 /*!< PORT2 OMR: PR2 Position */
\r
3985 #define PORT2_OMR_PR2_Msk (0x01UL << PORT2_OMR_PR2_Pos) /*!< PORT2 OMR: PR2 Mask */
\r
3986 #define PORT2_OMR_PR3_Pos 19 /*!< PORT2 OMR: PR3 Position */
\r
3987 #define PORT2_OMR_PR3_Msk (0x01UL << PORT2_OMR_PR3_Pos) /*!< PORT2 OMR: PR3 Mask */
\r
3988 #define PORT2_OMR_PR4_Pos 20 /*!< PORT2 OMR: PR4 Position */
\r
3989 #define PORT2_OMR_PR4_Msk (0x01UL << PORT2_OMR_PR4_Pos) /*!< PORT2 OMR: PR4 Mask */
\r
3990 #define PORT2_OMR_PR5_Pos 21 /*!< PORT2 OMR: PR5 Position */
\r
3991 #define PORT2_OMR_PR5_Msk (0x01UL << PORT2_OMR_PR5_Pos) /*!< PORT2 OMR: PR5 Mask */
\r
3992 #define PORT2_OMR_PR6_Pos 22 /*!< PORT2 OMR: PR6 Position */
\r
3993 #define PORT2_OMR_PR6_Msk (0x01UL << PORT2_OMR_PR6_Pos) /*!< PORT2 OMR: PR6 Mask */
\r
3994 #define PORT2_OMR_PR7_Pos 23 /*!< PORT2 OMR: PR7 Position */
\r
3995 #define PORT2_OMR_PR7_Msk (0x01UL << PORT2_OMR_PR7_Pos) /*!< PORT2 OMR: PR7 Mask */
\r
3996 #define PORT2_OMR_PR8_Pos 24 /*!< PORT2 OMR: PR8 Position */
\r
3997 #define PORT2_OMR_PR8_Msk (0x01UL << PORT2_OMR_PR8_Pos) /*!< PORT2 OMR: PR8 Mask */
\r
3998 #define PORT2_OMR_PR9_Pos 25 /*!< PORT2 OMR: PR9 Position */
\r
3999 #define PORT2_OMR_PR9_Msk (0x01UL << PORT2_OMR_PR9_Pos) /*!< PORT2 OMR: PR9 Mask */
\r
4000 #define PORT2_OMR_PR10_Pos 26 /*!< PORT2 OMR: PR10 Position */
\r
4001 #define PORT2_OMR_PR10_Msk (0x01UL << PORT2_OMR_PR10_Pos) /*!< PORT2 OMR: PR10 Mask */
\r
4002 #define PORT2_OMR_PR11_Pos 27 /*!< PORT2 OMR: PR11 Position */
\r
4003 #define PORT2_OMR_PR11_Msk (0x01UL << PORT2_OMR_PR11_Pos) /*!< PORT2 OMR: PR11 Mask */
\r
4005 /* --------------------------------- PORT2_IOCR0 -------------------------------- */
\r
4006 #define PORT2_IOCR0_PC0_Pos 3 /*!< PORT2 IOCR0: PC0 Position */
\r
4007 #define PORT2_IOCR0_PC0_Msk (0x1fUL << PORT2_IOCR0_PC0_Pos) /*!< PORT2 IOCR0: PC0 Mask */
\r
4008 #define PORT2_IOCR0_PC1_Pos 11 /*!< PORT2 IOCR0: PC1 Position */
\r
4009 #define PORT2_IOCR0_PC1_Msk (0x1fUL << PORT2_IOCR0_PC1_Pos) /*!< PORT2 IOCR0: PC1 Mask */
\r
4010 #define PORT2_IOCR0_PC2_Pos 19 /*!< PORT2 IOCR0: PC2 Position */
\r
4011 #define PORT2_IOCR0_PC2_Msk (0x1fUL << PORT2_IOCR0_PC2_Pos) /*!< PORT2 IOCR0: PC2 Mask */
\r
4012 #define PORT2_IOCR0_PC3_Pos 27 /*!< PORT2 IOCR0: PC3 Position */
\r
4013 #define PORT2_IOCR0_PC3_Msk (0x1fUL << PORT2_IOCR0_PC3_Pos) /*!< PORT2 IOCR0: PC3 Mask */
\r
4015 /* --------------------------------- PORT2_IOCR4 -------------------------------- */
\r
4016 #define PORT2_IOCR4_PC4_Pos 3 /*!< PORT2 IOCR4: PC4 Position */
\r
4017 #define PORT2_IOCR4_PC4_Msk (0x1fUL << PORT2_IOCR4_PC4_Pos) /*!< PORT2 IOCR4: PC4 Mask */
\r
4018 #define PORT2_IOCR4_PC5_Pos 11 /*!< PORT2 IOCR4: PC5 Position */
\r
4019 #define PORT2_IOCR4_PC5_Msk (0x1fUL << PORT2_IOCR4_PC5_Pos) /*!< PORT2 IOCR4: PC5 Mask */
\r
4020 #define PORT2_IOCR4_PC6_Pos 19 /*!< PORT2 IOCR4: PC6 Position */
\r
4021 #define PORT2_IOCR4_PC6_Msk (0x1fUL << PORT2_IOCR4_PC6_Pos) /*!< PORT2 IOCR4: PC6 Mask */
\r
4022 #define PORT2_IOCR4_PC7_Pos 27 /*!< PORT2 IOCR4: PC7 Position */
\r
4023 #define PORT2_IOCR4_PC7_Msk (0x1fUL << PORT2_IOCR4_PC7_Pos) /*!< PORT2 IOCR4: PC7 Mask */
\r
4025 /* --------------------------------- PORT2_IOCR8 -------------------------------- */
\r
4026 #define PORT2_IOCR8_PC8_Pos 3 /*!< PORT2 IOCR8: PC8 Position */
\r
4027 #define PORT2_IOCR8_PC8_Msk (0x1fUL << PORT2_IOCR8_PC8_Pos) /*!< PORT2 IOCR8: PC8 Mask */
\r
4028 #define PORT2_IOCR8_PC9_Pos 11 /*!< PORT2 IOCR8: PC9 Position */
\r
4029 #define PORT2_IOCR8_PC9_Msk (0x1fUL << PORT2_IOCR8_PC9_Pos) /*!< PORT2 IOCR8: PC9 Mask */
\r
4030 #define PORT2_IOCR8_PC10_Pos 19 /*!< PORT2 IOCR8: PC10 Position */
\r
4031 #define PORT2_IOCR8_PC10_Msk (0x1fUL << PORT2_IOCR8_PC10_Pos) /*!< PORT2 IOCR8: PC10 Mask */
\r
4032 #define PORT2_IOCR8_PC11_Pos 27 /*!< PORT2 IOCR8: PC11 Position */
\r
4033 #define PORT2_IOCR8_PC11_Msk (0x1fUL << PORT2_IOCR8_PC11_Pos) /*!< PORT2 IOCR8: PC11 Mask */
\r
4035 /* ---------------------------------- PORT2_IN ---------------------------------- */
\r
4036 #define PORT2_IN_P0_Pos 0 /*!< PORT2 IN: P0 Position */
\r
4037 #define PORT2_IN_P0_Msk (0x01UL << PORT2_IN_P0_Pos) /*!< PORT2 IN: P0 Mask */
\r
4038 #define PORT2_IN_P1_Pos 1 /*!< PORT2 IN: P1 Position */
\r
4039 #define PORT2_IN_P1_Msk (0x01UL << PORT2_IN_P1_Pos) /*!< PORT2 IN: P1 Mask */
\r
4040 #define PORT2_IN_P2_Pos 2 /*!< PORT2 IN: P2 Position */
\r
4041 #define PORT2_IN_P2_Msk (0x01UL << PORT2_IN_P2_Pos) /*!< PORT2 IN: P2 Mask */
\r
4042 #define PORT2_IN_P3_Pos 3 /*!< PORT2 IN: P3 Position */
\r
4043 #define PORT2_IN_P3_Msk (0x01UL << PORT2_IN_P3_Pos) /*!< PORT2 IN: P3 Mask */
\r
4044 #define PORT2_IN_P4_Pos 4 /*!< PORT2 IN: P4 Position */
\r
4045 #define PORT2_IN_P4_Msk (0x01UL << PORT2_IN_P4_Pos) /*!< PORT2 IN: P4 Mask */
\r
4046 #define PORT2_IN_P5_Pos 5 /*!< PORT2 IN: P5 Position */
\r
4047 #define PORT2_IN_P5_Msk (0x01UL << PORT2_IN_P5_Pos) /*!< PORT2 IN: P5 Mask */
\r
4048 #define PORT2_IN_P6_Pos 6 /*!< PORT2 IN: P6 Position */
\r
4049 #define PORT2_IN_P6_Msk (0x01UL << PORT2_IN_P6_Pos) /*!< PORT2 IN: P6 Mask */
\r
4050 #define PORT2_IN_P7_Pos 7 /*!< PORT2 IN: P7 Position */
\r
4051 #define PORT2_IN_P7_Msk (0x01UL << PORT2_IN_P7_Pos) /*!< PORT2 IN: P7 Mask */
\r
4052 #define PORT2_IN_P8_Pos 8 /*!< PORT2 IN: P8 Position */
\r
4053 #define PORT2_IN_P8_Msk (0x01UL << PORT2_IN_P8_Pos) /*!< PORT2 IN: P8 Mask */
\r
4054 #define PORT2_IN_P9_Pos 9 /*!< PORT2 IN: P9 Position */
\r
4055 #define PORT2_IN_P9_Msk (0x01UL << PORT2_IN_P9_Pos) /*!< PORT2 IN: P9 Mask */
\r
4056 #define PORT2_IN_P10_Pos 10 /*!< PORT2 IN: P10 Position */
\r
4057 #define PORT2_IN_P10_Msk (0x01UL << PORT2_IN_P10_Pos) /*!< PORT2 IN: P10 Mask */
\r
4058 #define PORT2_IN_P11_Pos 11 /*!< PORT2 IN: P11 Position */
\r
4059 #define PORT2_IN_P11_Msk (0x01UL << PORT2_IN_P11_Pos) /*!< PORT2 IN: P11 Mask */
\r
4061 /* --------------------------------- PORT2_PHCR0 -------------------------------- */
\r
4062 #define PORT2_PHCR0_PH0_Pos 2 /*!< PORT2 PHCR0: PH0 Position */
\r
4063 #define PORT2_PHCR0_PH0_Msk (0x01UL << PORT2_PHCR0_PH0_Pos) /*!< PORT2 PHCR0: PH0 Mask */
\r
4064 #define PORT2_PHCR0_PH1_Pos 6 /*!< PORT2 PHCR0: PH1 Position */
\r
4065 #define PORT2_PHCR0_PH1_Msk (0x01UL << PORT2_PHCR0_PH1_Pos) /*!< PORT2 PHCR0: PH1 Mask */
\r
4066 #define PORT2_PHCR0_PH2_Pos 10 /*!< PORT2 PHCR0: PH2 Position */
\r
4067 #define PORT2_PHCR0_PH2_Msk (0x01UL << PORT2_PHCR0_PH2_Pos) /*!< PORT2 PHCR0: PH2 Mask */
\r
4068 #define PORT2_PHCR0_PH3_Pos 14 /*!< PORT2 PHCR0: PH3 Position */
\r
4069 #define PORT2_PHCR0_PH3_Msk (0x01UL << PORT2_PHCR0_PH3_Pos) /*!< PORT2 PHCR0: PH3 Mask */
\r
4070 #define PORT2_PHCR0_PH4_Pos 18 /*!< PORT2 PHCR0: PH4 Position */
\r
4071 #define PORT2_PHCR0_PH4_Msk (0x01UL << PORT2_PHCR0_PH4_Pos) /*!< PORT2 PHCR0: PH4 Mask */
\r
4072 #define PORT2_PHCR0_PH5_Pos 22 /*!< PORT2 PHCR0: PH5 Position */
\r
4073 #define PORT2_PHCR0_PH5_Msk (0x01UL << PORT2_PHCR0_PH5_Pos) /*!< PORT2 PHCR0: PH5 Mask */
\r
4074 #define PORT2_PHCR0_PH6_Pos 26 /*!< PORT2 PHCR0: PH6 Position */
\r
4075 #define PORT2_PHCR0_PH6_Msk (0x01UL << PORT2_PHCR0_PH6_Pos) /*!< PORT2 PHCR0: PH6 Mask */
\r
4076 #define PORT2_PHCR0_PH7_Pos 30 /*!< PORT2 PHCR0: PH7 Position */
\r
4077 #define PORT2_PHCR0_PH7_Msk (0x01UL << PORT2_PHCR0_PH7_Pos) /*!< PORT2 PHCR0: PH7 Mask */
\r
4079 /* --------------------------------- PORT2_PHCR1 -------------------------------- */
\r
4080 #define PORT2_PHCR1_PH8_Pos 2 /*!< PORT2 PHCR1: PH8 Position */
\r
4081 #define PORT2_PHCR1_PH8_Msk (0x01UL << PORT2_PHCR1_PH8_Pos) /*!< PORT2 PHCR1: PH8 Mask */
\r
4082 #define PORT2_PHCR1_PH9_Pos 6 /*!< PORT2 PHCR1: PH9 Position */
\r
4083 #define PORT2_PHCR1_PH9_Msk (0x01UL << PORT2_PHCR1_PH9_Pos) /*!< PORT2 PHCR1: PH9 Mask */
\r
4084 #define PORT2_PHCR1_PH10_Pos 10 /*!< PORT2 PHCR1: PH10 Position */
\r
4085 #define PORT2_PHCR1_PH10_Msk (0x01UL << PORT2_PHCR1_PH10_Pos) /*!< PORT2 PHCR1: PH10 Mask */
\r
4086 #define PORT2_PHCR1_PH11_Pos 14 /*!< PORT2 PHCR1: PH11 Position */
\r
4087 #define PORT2_PHCR1_PH11_Msk (0x01UL << PORT2_PHCR1_PH11_Pos) /*!< PORT2 PHCR1: PH11 Mask */
\r
4089 /* --------------------------------- PORT2_PDISC -------------------------------- */
\r
4090 #define PORT2_PDISC_PDIS0_Pos 0 /*!< PORT2 PDISC: PDIS0 Position */
\r
4091 #define PORT2_PDISC_PDIS0_Msk (0x01UL << PORT2_PDISC_PDIS0_Pos) /*!< PORT2 PDISC: PDIS0 Mask */
\r
4092 #define PORT2_PDISC_PDIS1_Pos 1 /*!< PORT2 PDISC: PDIS1 Position */
\r
4093 #define PORT2_PDISC_PDIS1_Msk (0x01UL << PORT2_PDISC_PDIS1_Pos) /*!< PORT2 PDISC: PDIS1 Mask */
\r
4094 #define PORT2_PDISC_PDIS2_Pos 2 /*!< PORT2 PDISC: PDIS2 Position */
\r
4095 #define PORT2_PDISC_PDIS2_Msk (0x01UL << PORT2_PDISC_PDIS2_Pos) /*!< PORT2 PDISC: PDIS2 Mask */
\r
4096 #define PORT2_PDISC_PDIS3_Pos 3 /*!< PORT2 PDISC: PDIS3 Position */
\r
4097 #define PORT2_PDISC_PDIS3_Msk (0x01UL << PORT2_PDISC_PDIS3_Pos) /*!< PORT2 PDISC: PDIS3 Mask */
\r
4098 #define PORT2_PDISC_PDIS4_Pos 4 /*!< PORT2 PDISC: PDIS4 Position */
\r
4099 #define PORT2_PDISC_PDIS4_Msk (0x01UL << PORT2_PDISC_PDIS4_Pos) /*!< PORT2 PDISC: PDIS4 Mask */
\r
4100 #define PORT2_PDISC_PDIS5_Pos 5 /*!< PORT2 PDISC: PDIS5 Position */
\r
4101 #define PORT2_PDISC_PDIS5_Msk (0x01UL << PORT2_PDISC_PDIS5_Pos) /*!< PORT2 PDISC: PDIS5 Mask */
\r
4102 #define PORT2_PDISC_PDIS6_Pos 6 /*!< PORT2 PDISC: PDIS6 Position */
\r
4103 #define PORT2_PDISC_PDIS6_Msk (0x01UL << PORT2_PDISC_PDIS6_Pos) /*!< PORT2 PDISC: PDIS6 Mask */
\r
4104 #define PORT2_PDISC_PDIS7_Pos 7 /*!< PORT2 PDISC: PDIS7 Position */
\r
4105 #define PORT2_PDISC_PDIS7_Msk (0x01UL << PORT2_PDISC_PDIS7_Pos) /*!< PORT2 PDISC: PDIS7 Mask */
\r
4106 #define PORT2_PDISC_PDIS8_Pos 8 /*!< PORT2 PDISC: PDIS8 Position */
\r
4107 #define PORT2_PDISC_PDIS8_Msk (0x01UL << PORT2_PDISC_PDIS8_Pos) /*!< PORT2 PDISC: PDIS8 Mask */
\r
4108 #define PORT2_PDISC_PDIS9_Pos 9 /*!< PORT2 PDISC: PDIS9 Position */
\r
4109 #define PORT2_PDISC_PDIS9_Msk (0x01UL << PORT2_PDISC_PDIS9_Pos) /*!< PORT2 PDISC: PDIS9 Mask */
\r
4110 #define PORT2_PDISC_PDIS10_Pos 10 /*!< PORT2 PDISC: PDIS10 Position */
\r
4111 #define PORT2_PDISC_PDIS10_Msk (0x01UL << PORT2_PDISC_PDIS10_Pos) /*!< PORT2 PDISC: PDIS10 Mask */
\r
4112 #define PORT2_PDISC_PDIS11_Pos 11 /*!< PORT2 PDISC: PDIS11 Position */
\r
4113 #define PORT2_PDISC_PDIS11_Msk (0x01UL << PORT2_PDISC_PDIS11_Pos) /*!< PORT2 PDISC: PDIS11 Mask */
\r
4115 /* ---------------------------------- PORT2_PPS --------------------------------- */
\r
4116 #define PORT2_PPS_PPS0_Pos 0 /*!< PORT2 PPS: PPS0 Position */
\r
4117 #define PORT2_PPS_PPS0_Msk (0x01UL << PORT2_PPS_PPS0_Pos) /*!< PORT2 PPS: PPS0 Mask */
\r
4118 #define PORT2_PPS_PPS1_Pos 1 /*!< PORT2 PPS: PPS1 Position */
\r
4119 #define PORT2_PPS_PPS1_Msk (0x01UL << PORT2_PPS_PPS1_Pos) /*!< PORT2 PPS: PPS1 Mask */
\r
4120 #define PORT2_PPS_PPS2_Pos 2 /*!< PORT2 PPS: PPS2 Position */
\r
4121 #define PORT2_PPS_PPS2_Msk (0x01UL << PORT2_PPS_PPS2_Pos) /*!< PORT2 PPS: PPS2 Mask */
\r
4122 #define PORT2_PPS_PPS3_Pos 3 /*!< PORT2 PPS: PPS3 Position */
\r
4123 #define PORT2_PPS_PPS3_Msk (0x01UL << PORT2_PPS_PPS3_Pos) /*!< PORT2 PPS: PPS3 Mask */
\r
4124 #define PORT2_PPS_PPS4_Pos 4 /*!< PORT2 PPS: PPS4 Position */
\r
4125 #define PORT2_PPS_PPS4_Msk (0x01UL << PORT2_PPS_PPS4_Pos) /*!< PORT2 PPS: PPS4 Mask */
\r
4126 #define PORT2_PPS_PPS5_Pos 5 /*!< PORT2 PPS: PPS5 Position */
\r
4127 #define PORT2_PPS_PPS5_Msk (0x01UL << PORT2_PPS_PPS5_Pos) /*!< PORT2 PPS: PPS5 Mask */
\r
4128 #define PORT2_PPS_PPS6_Pos 6 /*!< PORT2 PPS: PPS6 Position */
\r
4129 #define PORT2_PPS_PPS6_Msk (0x01UL << PORT2_PPS_PPS6_Pos) /*!< PORT2 PPS: PPS6 Mask */
\r
4130 #define PORT2_PPS_PPS7_Pos 7 /*!< PORT2 PPS: PPS7 Position */
\r
4131 #define PORT2_PPS_PPS7_Msk (0x01UL << PORT2_PPS_PPS7_Pos) /*!< PORT2 PPS: PPS7 Mask */
\r
4132 #define PORT2_PPS_PPS8_Pos 8 /*!< PORT2 PPS: PPS8 Position */
\r
4133 #define PORT2_PPS_PPS8_Msk (0x01UL << PORT2_PPS_PPS8_Pos) /*!< PORT2 PPS: PPS8 Mask */
\r
4134 #define PORT2_PPS_PPS9_Pos 9 /*!< PORT2 PPS: PPS9 Position */
\r
4135 #define PORT2_PPS_PPS9_Msk (0x01UL << PORT2_PPS_PPS9_Pos) /*!< PORT2 PPS: PPS9 Mask */
\r
4136 #define PORT2_PPS_PPS10_Pos 10 /*!< PORT2 PPS: PPS10 Position */
\r
4137 #define PORT2_PPS_PPS10_Msk (0x01UL << PORT2_PPS_PPS10_Pos) /*!< PORT2 PPS: PPS10 Mask */
\r
4138 #define PORT2_PPS_PPS11_Pos 11 /*!< PORT2 PPS: PPS11 Position */
\r
4139 #define PORT2_PPS_PPS11_Msk (0x01UL << PORT2_PPS_PPS11_Pos) /*!< PORT2 PPS: PPS11 Mask */
\r
4141 /* --------------------------------- PORT2_HWSEL -------------------------------- */
\r
4142 #define PORT2_HWSEL_HW0_Pos 0 /*!< PORT2 HWSEL: HW0 Position */
\r
4143 #define PORT2_HWSEL_HW0_Msk (0x03UL << PORT2_HWSEL_HW0_Pos) /*!< PORT2 HWSEL: HW0 Mask */
\r
4144 #define PORT2_HWSEL_HW1_Pos 2 /*!< PORT2 HWSEL: HW1 Position */
\r
4145 #define PORT2_HWSEL_HW1_Msk (0x03UL << PORT2_HWSEL_HW1_Pos) /*!< PORT2 HWSEL: HW1 Mask */
\r
4146 #define PORT2_HWSEL_HW2_Pos 4 /*!< PORT2 HWSEL: HW2 Position */
\r
4147 #define PORT2_HWSEL_HW2_Msk (0x03UL << PORT2_HWSEL_HW2_Pos) /*!< PORT2 HWSEL: HW2 Mask */
\r
4148 #define PORT2_HWSEL_HW3_Pos 6 /*!< PORT2 HWSEL: HW3 Position */
\r
4149 #define PORT2_HWSEL_HW3_Msk (0x03UL << PORT2_HWSEL_HW3_Pos) /*!< PORT2 HWSEL: HW3 Mask */
\r
4150 #define PORT2_HWSEL_HW4_Pos 8 /*!< PORT2 HWSEL: HW4 Position */
\r
4151 #define PORT2_HWSEL_HW4_Msk (0x03UL << PORT2_HWSEL_HW4_Pos) /*!< PORT2 HWSEL: HW4 Mask */
\r
4152 #define PORT2_HWSEL_HW5_Pos 10 /*!< PORT2 HWSEL: HW5 Position */
\r
4153 #define PORT2_HWSEL_HW5_Msk (0x03UL << PORT2_HWSEL_HW5_Pos) /*!< PORT2 HWSEL: HW5 Mask */
\r
4154 #define PORT2_HWSEL_HW6_Pos 12 /*!< PORT2 HWSEL: HW6 Position */
\r
4155 #define PORT2_HWSEL_HW6_Msk (0x03UL << PORT2_HWSEL_HW6_Pos) /*!< PORT2 HWSEL: HW6 Mask */
\r
4156 #define PORT2_HWSEL_HW7_Pos 14 /*!< PORT2 HWSEL: HW7 Position */
\r
4157 #define PORT2_HWSEL_HW7_Msk (0x03UL << PORT2_HWSEL_HW7_Pos) /*!< PORT2 HWSEL: HW7 Mask */
\r
4158 #define PORT2_HWSEL_HW8_Pos 16 /*!< PORT2 HWSEL: HW8 Position */
\r
4159 #define PORT2_HWSEL_HW8_Msk (0x03UL << PORT2_HWSEL_HW8_Pos) /*!< PORT2 HWSEL: HW8 Mask */
\r
4160 #define PORT2_HWSEL_HW9_Pos 18 /*!< PORT2 HWSEL: HW9 Position */
\r
4161 #define PORT2_HWSEL_HW9_Msk (0x03UL << PORT2_HWSEL_HW9_Pos) /*!< PORT2 HWSEL: HW9 Mask */
\r
4162 #define PORT2_HWSEL_HW10_Pos 20 /*!< PORT2 HWSEL: HW10 Position */
\r
4163 #define PORT2_HWSEL_HW10_Msk (0x03UL << PORT2_HWSEL_HW10_Pos) /*!< PORT2 HWSEL: HW10 Mask */
\r
4164 #define PORT2_HWSEL_HW11_Pos 22 /*!< PORT2 HWSEL: HW11 Position */
\r
4165 #define PORT2_HWSEL_HW11_Msk (0x03UL << PORT2_HWSEL_HW11_Pos) /*!< PORT2 HWSEL: HW11 Mask */
\r
4169 /* ================================================================================ */
\r
4170 /* ================ Peripheral memory map ================ */
\r
4171 /* ================================================================================ */
\r
4173 #define PPB_BASE 0xE000E000UL
\r
4174 #define ERU0_BASE 0x40010600UL
\r
4175 #define PAU_BASE 0x40000000UL
\r
4176 #define NVM_BASE 0x40050000UL
\r
4177 #define WDT_BASE 0x40020000UL
\r
4178 #define RTC_BASE 0x40010A00UL
\r
4179 #define PRNG_BASE 0x48020000UL
\r
4180 #define USIC0_BASE 0x48000008UL
\r
4181 #define USIC0_CH0_BASE 0x48000000UL
\r
4182 #define USIC0_CH1_BASE 0x48000200UL
\r
4183 #define SCU_GENERAL_BASE 0x40010000UL
\r
4184 #define SCU_INTERRUPT_BASE 0x40010038UL
\r
4185 #define SCU_POWER_BASE 0x40010200UL
\r
4186 #define SCU_CLK_BASE 0x40010300UL
\r
4187 #define SCU_RESET_BASE 0x40010400UL
\r
4188 #define SCU_ANALOG_BASE 0x40011000UL
\r
4189 #define CCU40_BASE 0x48040000UL
\r
4190 #define CCU40_CC40_BASE 0x48040100UL
\r
4191 #define CCU40_CC41_BASE 0x48040200UL
\r
4192 #define CCU40_CC42_BASE 0x48040300UL
\r
4193 #define CCU40_CC43_BASE 0x48040400UL
\r
4194 #define VADC_BASE 0x48030000UL
\r
4195 #define SHS0_BASE 0x48034000UL
\r
4196 #define PORT0_BASE 0x40040000UL
\r
4197 #define PORT1_BASE 0x40040100UL
\r
4198 #define PORT2_BASE 0x40040200UL
\r
4201 /* ================================================================================ */
\r
4202 /* ================ Peripheral declaration ================ */
\r
4203 /* ================================================================================ */
\r
4205 #define PPB ((PPB_Type *) PPB_BASE)
\r
4206 #define ERU0 ((ERU_GLOBAL_TypeDef *) ERU0_BASE)
\r
4207 #define PAU ((PAU_Type *) PAU_BASE)
\r
4208 #define NVM ((NVM_Type *) NVM_BASE)
\r
4209 #define WDT ((WDT_GLOBAL_TypeDef *) WDT_BASE)
\r
4210 #define RTC ((RTC_GLOBAL_TypeDef *) RTC_BASE)
\r
4211 #define PRNG ((PRNG_Type *) PRNG_BASE)
\r
4212 #define USIC0 ((USIC_GLOBAL_TypeDef *) USIC0_BASE)
\r
4213 #define USIC0_CH0 ((USIC_CH_TypeDef *) USIC0_CH0_BASE)
\r
4214 #define USIC0_CH1 ((USIC_CH_TypeDef *) USIC0_CH1_BASE)
\r
4215 #define SCU_GENERAL ((SCU_GENERAL_Type *) SCU_GENERAL_BASE)
\r
4216 #define SCU_INTERRUPT ((SCU_INTERRUPT_TypeDef *) SCU_INTERRUPT_BASE)
\r
4217 #define SCU_POWER ((SCU_POWER_Type *) SCU_POWER_BASE)
\r
4218 #define SCU_CLK ((SCU_CLK_TypeDef *) SCU_CLK_BASE)
\r
4219 #define SCU_RESET ((SCU_RESET_Type *) SCU_RESET_BASE)
\r
4220 #define SCU_ANALOG ((SCU_ANALOG_Type *) SCU_ANALOG_BASE)
\r
4221 #define CCU40 ((CCU4_GLOBAL_TypeDef *) CCU40_BASE)
\r
4222 #define CCU40_CC40 ((CCU4_CC4_TypeDef *) CCU40_CC40_BASE)
\r
4223 #define CCU40_CC41 ((CCU4_CC4_TypeDef *) CCU40_CC41_BASE)
\r
4224 #define CCU40_CC42 ((CCU4_CC4_TypeDef *) CCU40_CC42_BASE)
\r
4225 #define CCU40_CC43 ((CCU4_CC4_TypeDef *) CCU40_CC43_BASE)
\r
4226 #define VADC ((VADC_GLOBAL_TypeDef *) VADC_BASE)
\r
4227 #define SHS0 ((SHS_Type *) SHS0_BASE)
\r
4228 #define PORT0 ((PORT0_Type *) PORT0_BASE)
\r
4229 #define PORT1 ((PORT1_Type *) PORT1_BASE)
\r
4230 #define PORT2 ((PORT2_Type *) PORT2_BASE)
\r
4233 /** @} */ /* End of group Device_Peripheral_Registers */
\r
4234 /** @} */ /* End of group XMC1100 */
\r
4235 /** @} */ /* End of group Infineon */
\r
4237 #ifdef __cplusplus
\r
4242 #endif /* XMC1100_H */
\r
projects / freertos / blob