2 * FreeRTOS Kernel V10.0.0
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3 * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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5 * Permission is hereby granted, free of charge, to any person obtaining a copy of
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6 * this software and associated documentation files (the "Software"), to deal in
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7 * the Software without restriction, including without limitation the rights to
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8 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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9 * the Software, and to permit persons to whom the Software is furnished to do so,
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10 * subject to the following conditions:
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12 * The above copyright notice and this permission notice shall be included in all
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13 * copies or substantial portions of the Software. If you wish to use our Amazon
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14 * FreeRTOS name, please do so in a fair use way that does not cause confusion.
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16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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18 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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19 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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20 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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23 * http://www.FreeRTOS.org
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24 * http://aws.amazon.com/freertos
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26 * 1 tab == 4 spaces!
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29 /* Scheduler includes. */
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30 #include "FreeRTOS.h"
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33 /* Demo includes. */
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34 #include "IntQueueTimer.h"
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35 #include "IntQueue.h"
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37 /* Hardware includes. */
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38 #include "lpc11xx.h"
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40 /* The two timer frequencies. */
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41 #define tmrTIMER_2_FREQUENCY ( 2000UL )
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42 #define tmrTIMER_3_FREQUENCY ( 2001UL )
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44 /* The priorities for the two timers. Note that a priority of 0 is the highest
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45 possible on Cortex-M devices. */
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46 #define tmrMAX_PRIORITY ( 0UL )
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47 #define trmSECOND_HIGHEST_PRIORITY ( tmrMAX_PRIORITY + 1 )
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49 void vInitialiseTimerForIntQueueTest( void )
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51 /* Enable AHB clock for GPIO and 16-bit timers. */
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52 LPC_SYSCON->SYSAHBCLKCTRL |= ( 7 << 6 );
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54 /* Interrupt and reset on MR0 match. */
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55 LPC_TMR16B0->MCR = 0x03;
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56 LPC_TMR16B1->MCR = 0x03;
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58 /* Configure the frequency of the interrupt generated by MR0 matches. */
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59 LPC_TMR16B0->MR0 = SystemCoreClock / tmrTIMER_2_FREQUENCY;
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60 LPC_TMR16B1->MR0 = SystemCoreClock / tmrTIMER_3_FREQUENCY;
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62 /* Don't generate interrupts until the scheduler has been started.
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63 Interrupts will be automatically enabled when the first task starts
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65 taskDISABLE_INTERRUPTS();
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67 /* Set the timer interrupts to be above the kernel. The interrupts are
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68 assigned different priorities so they nest with each other. */
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69 NVIC_SetPriority( TIMER_16_0_IRQn, trmSECOND_HIGHEST_PRIORITY );
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70 NVIC_SetPriority( TIMER_16_1_IRQn, tmrMAX_PRIORITY );
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72 /* Enable the timer interrupts. */
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73 NVIC_EnableIRQ( TIMER_16_0_IRQn );
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74 NVIC_EnableIRQ( TIMER_16_1_IRQn );
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76 /* Start the timers. */
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77 LPC_TMR16B0->TCR = 0x01;
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78 LPC_TMR16B1->TCR = 0x01;
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80 /*-----------------------------------------------------------*/
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82 void TIMER16_0_IRQHandler(void)
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84 /* Clear the interrupt. */
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85 LPC_TMR16B0->IR = LPC_TMR16B0->IR;
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87 /* Call the standard demo int queue timer function for this first timer. */
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88 portEND_SWITCHING_ISR( xFirstTimerHandler() );
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90 /*-----------------------------------------------------------*/
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92 void TIMER16_1_IRQHandler(void)
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94 /* Clear the interrupt. */
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95 LPC_TMR16B1->IR = LPC_TMR16B1->IR;
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97 /* Call the standard demo int queue timer function for this second timer. */
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98 portEND_SWITCHING_ISR( xSecondTimerHandler() );
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100 /*-----------------------------------------------------------*/
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