2 ******************************************************************************
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3 * @file startup_stm32f0xx.s
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4 * @author MCD Application Team
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6 * @date 27-January-2012
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7 * @brief STM32F0xx Devices vector table for Atollic toolchain.
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8 * This module performs:
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9 * - Set the initial SP
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10 * - Set the initial PC == Reset_Handler,
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11 * - Set the vector table entries with the exceptions ISR address
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12 * - Configure the clock system
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13 * - Branches to main in the C library (which eventually
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15 * After Reset the Cortex-M0 processor is in Thread mode,
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16 * priority is Privileged, and the Stack is set to Main.
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17 *******************************************************************************
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20 * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
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21 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
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22 * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
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23 * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
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24 * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
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25 * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
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27 * FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE
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28 * LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.
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30 * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
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31 ******************************************************************************
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39 .global g_pfnVectors
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40 .global Default_Handler
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42 /* start address for the initialization values of the .data section.
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43 defined in linker script */
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45 /* start address for the .data section. defined in linker script */
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47 /* end address for the .data section. defined in linker script */
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49 /* start address for the .bss section. defined in linker script */
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51 /* end address for the .bss section. defined in linker script */
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54 .equ BootRAM, 0xF108F85F
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56 * @brief This is the code that gets called when the processor first
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57 * starts execution following a reset event. Only the absolutely
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58 * necessary set is performed, after which the application
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59 * supplied main() routine is called.
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64 .section .text.Reset_Handler
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66 .type Reset_Handler, %function
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69 /* Copy the data segment initializers from flash to SRAM */
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87 /* Zero fill the bss segment. */
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97 /* Call the clock system intitialization function.*/
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99 /* Call static constructors */
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100 bl __libc_init_array
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101 /* Call the application's entry point.*/
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104 .size Reset_Handler, .-Reset_Handler
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107 * @brief This is the code that gets called when the processor receives an
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108 * unexpected interrupt. This simply enters an infinite loop, preserving
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109 * the system state for examination by a debugger.
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114 .section .text.Default_Handler,"ax",%progbits
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118 .size Default_Handler, .-Default_Handler
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119 /******************************************************************************
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121 * The minimal vector table for a Cortex M0. Note that the proper constructs
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122 * must be placed on this to ensure that it ends up at physical address
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125 ******************************************************************************/
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126 .section .isr_vector,"a",%progbits
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127 .type g_pfnVectors, %object
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128 .size g_pfnVectors, .-g_pfnVectors
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133 .word Reset_Handler
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135 .word HardFault_Handler
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146 .word PendSV_Handler
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147 .word SysTick_Handler
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148 .word WWDG_IRQHandler
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149 .word PVD_IRQHandler
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150 .word RTC_IRQHandler
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151 .word FLASH_IRQHandler
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152 .word RCC_IRQHandler
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153 .word EXTI0_1_IRQHandler
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154 .word EXTI2_3_IRQHandler
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155 .word EXTI4_15_IRQHandler
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156 .word TS_IRQHandler
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157 .word DMA1_Channel1_IRQHandler
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158 .word DMA1_Channel2_3_IRQHandler
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159 .word DMA1_Channel4_5_IRQHandler
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160 .word ADC1_COMP_IRQHandler
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161 .word TIM1_BRK_UP_TRG_COM_IRQHandler
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162 .word TIM1_CC_IRQHandler
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163 .word TIM2_IRQHandler
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164 .word TIM3_IRQHandler
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165 .word TIM6_DAC_IRQHandler
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167 .word TIM14_IRQHandler
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168 .word TIM15_IRQHandler
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169 .word TIM16_IRQHandler
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170 .word TIM17_IRQHandler
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171 .word I2C1_IRQHandler
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172 .word I2C2_IRQHandler
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173 .word SPI1_IRQHandler
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174 .word SPI2_IRQHandler
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175 .word USART1_IRQHandler
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176 .word USART2_IRQHandler
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178 .word CEC_IRQHandler
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180 .word BootRAM /* @0x108. This is for boot in RAM mode for
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181 STM32F0xx devices. */
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183 /*******************************************************************************
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185 * Provide weak aliases for each Exception handler to the Default_Handler.
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186 * As they are weak aliases, any function with the same name will override
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189 *******************************************************************************/
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192 .thumb_set NMI_Handler,Default_Handler
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194 .weak HardFault_Handler
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195 .thumb_set HardFault_Handler,Default_Handler
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198 .thumb_set SVC_Handler,Default_Handler
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200 .weak PendSV_Handler
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201 .thumb_set PendSV_Handler,Default_Handler
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203 .weak SysTick_Handler
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204 .thumb_set SysTick_Handler,Default_Handler
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206 .weak WWDG_IRQHandler
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207 .thumb_set WWDG_IRQHandler,Default_Handler
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209 .weak PVD_IRQHandler
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210 .thumb_set PVD_IRQHandler,Default_Handler
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212 .weak RTC_IRQHandler
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213 .thumb_set RTC_IRQHandler,Default_Handler
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215 .weak FLASH_IRQHandler
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216 .thumb_set FLASH_IRQHandler,Default_Handler
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218 .weak RCC_IRQHandler
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219 .thumb_set RCC_IRQHandler,Default_Handler
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221 .weak EXTI0_1_IRQHandler
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222 .thumb_set EXTI0_1_IRQHandler,Default_Handler
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224 .weak EXTI2_3_IRQHandler
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225 .thumb_set EXTI2_3_IRQHandler,Default_Handler
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227 .weak EXTI4_15_IRQHandler
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228 .thumb_set EXTI4_15_IRQHandler,Default_Handler
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230 .weak TS_IRQHandler
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231 .thumb_set TS_IRQHandler,Default_Handler
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233 .weak DMA1_Channel1_IRQHandler
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234 .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
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236 .weak DMA1_Channel2_3_IRQHandler
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237 .thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler
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239 .weak DMA1_Channel4_5_IRQHandler
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240 .thumb_set DMA1_Channel4_5_IRQHandler,Default_Handler
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242 .weak ADC1_COMP_IRQHandler
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243 .thumb_set ADC1_COMP_IRQHandler,Default_Handler
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245 .weak TIM1_BRK_UP_TRG_COM_IRQHandler
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246 .thumb_set TIM1_BRK_UP_TRG_COM_IRQHandler,Default_Handler
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248 .weak TIM1_CC_IRQHandler
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249 .thumb_set TIM1_CC_IRQHandler,Default_Handler
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251 .weak TIM2_IRQHandler
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252 .thumb_set TIM2_IRQHandler,Default_Handler
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254 .weak TIM3_IRQHandler
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255 .thumb_set TIM3_IRQHandler,Default_Handler
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257 .weak TIM6_DAC_IRQHandler
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258 .thumb_set TIM6_DAC_IRQHandler,Default_Handler
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260 .weak TIM14_IRQHandler
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261 .thumb_set TIM14_IRQHandler,Default_Handler
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263 .weak TIM15_IRQHandler
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264 .thumb_set TIM15_IRQHandler,Default_Handler
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266 .weak TIM16_IRQHandler
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267 .thumb_set TIM16_IRQHandler,Default_Handler
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269 .weak TIM17_IRQHandler
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270 .thumb_set TIM17_IRQHandler,Default_Handler
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272 .weak I2C1_IRQHandler
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273 .thumb_set I2C1_IRQHandler,Default_Handler
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275 .weak I2C2_IRQHandler
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276 .thumb_set I2C2_IRQHandler,Default_Handler
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278 .weak SPI1_IRQHandler
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279 .thumb_set SPI1_IRQHandler,Default_Handler
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281 .weak SPI2_IRQHandler
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282 .thumb_set SPI2_IRQHandler,Default_Handler
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284 .weak USART1_IRQHandler
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285 .thumb_set USART1_IRQHandler,Default_Handler
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287 .weak USART2_IRQHandler
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288 .thumb_set USART2_IRQHandler,Default_Handler
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290 .weak CEC_IRQHandler
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291 .thumb_set CEC_IRQHandler,Default_Handler
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293 /******************* (C) COPYRIGHT 2012 STMicroelectronics *****END OF FILE****/
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