git.sur5r.net Git - freertos/blob - FreeRTOS/Demo/CORTEX_M0_STM32F0518_IAR/startup_stm32f0xx.s

   1 ;/******************** (C) COPYRIGHT 2012 STMicroelectronics ********************\r
   2 ;* File Name          : startup_stm32f0xx.s\r
   3 ;* Author             : MCD Application Team\r
   4 ;* Version            : V1.0.0RC1\r
   5 ;* Date               : 27-January-2012\r
   6 ;* Description        : STM32F0xx Devices vector table for EWARM toolchain.\r
   7 ;*                      This module performs:\r
   8 ;*                      - Set the initial SP\r
   9 ;*                      - Set the initial PC == __iar_program_start,\r
  10 ;*                      - Set the vector table entries with the exceptions ISR \r
  11 ;*                        address.\r
  12 ;*                      After Reset the Cortex-M0 processor is in Thread mode,\r
  13 ;*                      priority is Privileged, and the Stack is set to Main.\r
  14 ;********************************************************************************\r
  15 ;* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
  16 ;* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
  17 ;* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,\r
  18 ;* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE\r
  19 ;* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING\r
  20 ;* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
  21 ;* FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE\r
  22 ;* LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.\r
  23 ;*******************************************************************************/\r
  24 ;\r
  25 ;\r
  26 ; The modules in this file are included in the libraries, and may be replaced\r
  27 ; by any user-defined modules that define the PUBLIC symbol _program_start or\r
  28 ; a user defined start symbol.\r
  29 ; To override the cstartup defined in the library, simply add your modified\r
  30 ; version to the workbench project.\r
  31 ;\r
  32 ; The vector table is normally located at address 0.\r
  33 ; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.\r
  34 ; The name "__vector_table" has special meaning for C-SPY:\r
  35 ; it is where the SP start value is found, and the NVIC vector\r
  36 ; table register (VTOR) is initialized to this address if != 0.\r
  37 ;\r
  38 ; Cortex-M version\r
  39 ;\r
  40 \r
  41         MODULE  ?cstartup\r
  42 \r
  43         ;; Forward declaration of sections.\r
  44         SECTION CSTACK:DATA:NOROOT(3)\r
  45 \r
  46         SECTION .intvec:CODE:NOROOT(2)\r
  47 \r
  48         EXTERN  __iar_program_start\r
  49         EXTERN  SystemInit        \r
  50         PUBLIC  __vector_table\r
  51 \r
  52         DATA\r
  53 __vector_table\r
  54         DCD     sfe(CSTACK)\r
  55         DCD     Reset_Handler                  ; Reset Handler\r
  56 \r
  57         DCD     NMI_Handler                    ; NMI Handler\r
  58         DCD     HardFault_Handler              ; Hard Fault Handler\r
  59         DCD     0                              ; Reserved\r
  60         DCD     0                              ; Reserved\r
  61         DCD     0                              ; Reserved\r
  62         DCD     0                              ; Reserved\r
  63         DCD     0                              ; Reserved\r
  64         DCD     0                              ; Reserved\r
  65         DCD     0                              ; Reserved\r
  66         DCD     SVC_Handler                    ; SVCall Handler\r
  67         DCD     0                              ; Reserved\r
  68         DCD     0                              ; Reserved\r
  69         DCD     PendSV_Handler                 ; PendSV Handler\r
  70         DCD     SysTick_Handler                ; SysTick Handler\r
  71 \r
  72         ; External Interrupts\r
  73         DCD     WWDG_IRQHandler                ; Window Watchdog\r
  74         DCD     PVD_IRQHandler                 ; PVD through EXTI Line detect\r
  75         DCD     RTC_IRQHandler                 ; RTC through EXTI Line\r
  76         DCD     FLASH_IRQHandler               ; FLASH\r
  77         DCD     RCC_IRQHandler                 ; RCC\r
  78         DCD     EXTI0_1_IRQHandler             ; EXTI Line 0 and 1\r
  79         DCD     EXTI2_3_IRQHandler             ; EXTI Line 2 and 3\r
  80         DCD     EXTI4_15_IRQHandler            ; EXTI Line 4 to 15\r
  81         DCD     TS_IRQHandler                  ; TS\r
  82         DCD     DMA1_Channel1_IRQHandler       ; DMA1 Channel 1\r
  83         DCD     DMA1_Channel2_3_IRQHandler     ; DMA1 Channel 2 and Channel 3\r
  84         DCD     DMA1_Channel4_5_IRQHandler     ; DMA1 Channel 4 and Channel 5\r
  85         DCD     ADC1_COMP_IRQHandler           ; ADC1, COMP1 and COMP2 \r
  86         DCD     TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation\r
  87         DCD     TIM1_CC_IRQHandler             ; TIM1 Capture Compare\r
  88         DCD     TIM2_IRQHandler                ; TIM2\r
  89         DCD     TIM3_IRQHandler                ; TIM3\r
  90         DCD     TIM6_DAC_IRQHandler            ; TIM6 and DAC\r
  91         DCD     0                              ; Reserved\r
  92         DCD     TIM14_IRQHandler               ; TIM14\r
  93         DCD     TIM15_IRQHandler               ; TIM15\r
  94         DCD     TIM16_IRQHandler               ; TIM16\r
  95         DCD     TIM17_IRQHandler               ; TIM17\r
  96         DCD     I2C1_IRQHandler                ; I2C1\r
  97         DCD     I2C2_IRQHandler                ; I2C2\r
  98         DCD     SPI1_IRQHandler                ; SPI1\r
  99         DCD     SPI2_IRQHandler                ; SPI2\r
 100         DCD     USART1_IRQHandler              ; USART1\r
 101         DCD     USART2_IRQHandler              ; USART2\r
 102         DCD     0                              ; Reserved\r
 103         DCD     CEC_IRQHandler                 ; CEC\r
 104         DCD     0                              ; Reserved\r
 105         \r
 106 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\r
 107 ;;\r
 108 ;; Default interrupt handlers.\r
 109 ;;\r
 110         THUMB\r
 111 \r
 112         EXTERN  __ICFEDIT_region_RAM_start__\r
 113         EXTERN  __ICFEDIT_region_RAM_end__\r
 114         SECTION `.text`:CODE:NOROOT(2)\r
 115         DATA\r
 116 ??DataTable22:\r
 117         DC32     __ICFEDIT_region_RAM_start__\r
 118 ??DataTable22_1:\r
 119         DC32     __ICFEDIT_region_RAM_end__\r
 120 \r
 121         THUMB\r
 122 \r
 123         PUBWEAK Reset_Handler\r
 124         SECTION .text:CODE:REORDER(2)\r
 125 Reset_Handler\r
 126 \r
 127         LDR   R0,=??DataTable22\r
 128         LDR    R0,[R0, #+0]\r
 129         LDR   R1,=??DataTable22_1\r
 130 ??x_0:\r
 131         MOVS     R2,#+0\r
 132         STRB     R2,[R0]\r
 133         ADDS      R0,R0,#0x1\r
 134         LDR      R2,[R1, #+0]\r
 135         CMP      R2,R0\r
 136         BCS.N    ??x_0\r
 137 \r
 138         LDR     R0, =SystemInit\r
 139         BLX     R0\r
 140         LDR     R0, =__iar_program_start\r
 141         BX      R0\r
 142 \r
 143         \r
 144         PUBWEAK NMI_Handler\r
 145         SECTION .text:CODE:NOROOT:REORDER(1)\r
 146 NMI_Handler\r
 147         B NMI_Handler\r
 148         \r
 149         \r
 150         PUBWEAK HardFault_Handler\r
 151         SECTION .text:CODE:NOROOT:REORDER(1)\r
 152 HardFault_Handler\r
 153         B HardFault_Handler\r
 154        \r
 155         \r
 156         PUBWEAK SVC_Handler\r
 157         SECTION .text:CODE:NOROOT:REORDER(1)\r
 158 SVC_Handler\r
 159         B SVC_Handler\r
 160        \r
 161         \r
 162         PUBWEAK PendSV_Handler\r
 163         SECTION .text:CODE:NOROOT:REORDER(1)\r
 164 PendSV_Handler\r
 165         B PendSV_Handler\r
 166         \r
 167         \r
 168         PUBWEAK SysTick_Handler\r
 169         SECTION .text:CODE:NOROOT:REORDER(1)\r
 170 SysTick_Handler\r
 171         B SysTick_Handler\r
 172         \r
 173         \r
 174         PUBWEAK WWDG_IRQHandler\r
 175         SECTION .text:CODE:NOROOT:REORDER(1)\r
 176 WWDG_IRQHandler\r
 177         B WWDG_IRQHandler\r
 178         \r
 179                 \r
 180         PUBWEAK PVD_IRQHandler\r
 181         SECTION .text:CODE:NOROOT:REORDER(1)\r
 182 PVD_IRQHandler\r
 183         B PVD_IRQHandler\r
 184         \r
 185                 \r
 186         PUBWEAK RTC_IRQHandler\r
 187         SECTION .text:CODE:NOROOT:REORDER(1)\r
 188 RTC_IRQHandler\r
 189         B RTC_IRQHandler\r
 190         \r
 191                 \r
 192         PUBWEAK FLASH_IRQHandler\r
 193         SECTION .text:CODE:NOROOT:REORDER(1)\r
 194 FLASH_IRQHandler\r
 195         B FLASH_IRQHandler\r
 196         \r
 197                 \r
 198         PUBWEAK RCC_IRQHandler\r
 199         SECTION .text:CODE:NOROOT:REORDER(1)\r
 200 RCC_IRQHandler\r
 201         B RCC_IRQHandler\r
 202         \r
 203                 \r
 204         PUBWEAK EXTI0_1_IRQHandler\r
 205         SECTION .text:CODE:NOROOT:REORDER(1)\r
 206 EXTI0_1_IRQHandler\r
 207         B EXTI0_1_IRQHandler\r
 208         \r
 209                 \r
 210         PUBWEAK EXTI2_3_IRQHandler\r
 211         SECTION .text:CODE:NOROOT:REORDER(1)\r
 212 EXTI2_3_IRQHandler\r
 213         B EXTI2_3_IRQHandler\r
 214         \r
 215                 \r
 216         PUBWEAK EXTI4_15_IRQHandler\r
 217         SECTION .text:CODE:NOROOT:REORDER(1)\r
 218 EXTI4_15_IRQHandler\r
 219         B EXTI4_15_IRQHandler\r
 220         \r
 221                 \r
 222         PUBWEAK TS_IRQHandler\r
 223         SECTION .text:CODE:NOROOT:REORDER(1)\r
 224 TS_IRQHandler\r
 225         B TS_IRQHandler\r
 226         \r
 227                 \r
 228         PUBWEAK DMA1_Channel1_IRQHandler\r
 229         SECTION .text:CODE:NOROOT:REORDER(1)\r
 230 DMA1_Channel1_IRQHandler\r
 231         B DMA1_Channel1_IRQHandler\r
 232         \r
 233                 \r
 234         PUBWEAK DMA1_Channel2_3_IRQHandler\r
 235         SECTION .text:CODE:NOROOT:REORDER(1)\r
 236 DMA1_Channel2_3_IRQHandler\r
 237         B DMA1_Channel2_3_IRQHandler\r
 238         \r
 239                 \r
 240         PUBWEAK DMA1_Channel4_5_IRQHandler\r
 241         SECTION .text:CODE:NOROOT:REORDER(1)\r
 242 DMA1_Channel4_5_IRQHandler\r
 243         B DMA1_Channel4_5_IRQHandler\r
 244         \r
 245                 \r
 246         PUBWEAK ADC1_COMP_IRQHandler\r
 247         SECTION .text:CODE:NOROOT:REORDER(1)\r
 248 ADC1_COMP_IRQHandler\r
 249         B ADC1_COMP_IRQHandler\r
 250         \r
 251                  \r
 252         PUBWEAK TIM1_BRK_UP_TRG_COM_IRQHandler\r
 253         SECTION .text:CODE:NOROOT:REORDER(1)\r
 254 TIM1_BRK_UP_TRG_COM_IRQHandler\r
 255         B TIM1_BRK_UP_TRG_COM_IRQHandler\r
 256         \r
 257                 \r
 258         PUBWEAK TIM1_CC_IRQHandler\r
 259         SECTION .text:CODE:NOROOT:REORDER(1)\r
 260 TIM1_CC_IRQHandler\r
 261         B TIM1_CC_IRQHandler\r
 262         \r
 263                 \r
 264         PUBWEAK TIM2_IRQHandler\r
 265         SECTION .text:CODE:NOROOT:REORDER(1)\r
 266 TIM2_IRQHandler\r
 267         B TIM2_IRQHandler\r
 268         \r
 269                 \r
 270         PUBWEAK TIM3_IRQHandler\r
 271         SECTION .text:CODE:NOROOT:REORDER(1)\r
 272 TIM3_IRQHandler\r
 273         B TIM3_IRQHandler\r
 274         \r
 275                 \r
 276         PUBWEAK TIM6_DAC_IRQHandler\r
 277         SECTION .text:CODE:NOROOT:REORDER(1)\r
 278 TIM6_DAC_IRQHandler\r
 279         B TIM6_DAC_IRQHandler\r
 280         \r
 281                 \r
 282         PUBWEAK TIM14_IRQHandler\r
 283         SECTION .text:CODE:NOROOT:REORDER(1)\r
 284 TIM14_IRQHandler\r
 285         B TIM14_IRQHandler\r
 286         \r
 287                 \r
 288         PUBWEAK TIM15_IRQHandler\r
 289         SECTION .text:CODE:NOROOT:REORDER(1)\r
 290 TIM15_IRQHandler\r
 291         B TIM15_IRQHandler\r
 292         \r
 293                 \r
 294         PUBWEAK TIM16_IRQHandler\r
 295         SECTION .text:CODE:NOROOT:REORDER(1)\r
 296 TIM16_IRQHandler\r
 297         B TIM16_IRQHandler\r
 298         \r
 299                 \r
 300         PUBWEAK TIM17_IRQHandler\r
 301         SECTION .text:CODE:NOROOT:REORDER(1)\r
 302 TIM17_IRQHandler\r
 303         B TIM17_IRQHandler\r
 304         \r
 305                 \r
 306         PUBWEAK I2C1_IRQHandler\r
 307         SECTION .text:CODE:NOROOT:REORDER(1)\r
 308 I2C1_IRQHandler\r
 309         B I2C1_IRQHandler\r
 310         \r
 311                 \r
 312         PUBWEAK I2C2_IRQHandler\r
 313         SECTION .text:CODE:NOROOT:REORDER(1)\r
 314 I2C2_IRQHandler\r
 315         B I2C2_IRQHandler\r
 316         \r
 317                 \r
 318         PUBWEAK SPI1_IRQHandler\r
 319         SECTION .text:CODE:NOROOT:REORDER(1)\r
 320 SPI1_IRQHandler\r
 321         B SPI1_IRQHandler\r
 322         \r
 323                 \r
 324         PUBWEAK SPI2_IRQHandler\r
 325         SECTION .text:CODE:NOROOT:REORDER(1)\r
 326 SPI2_IRQHandler\r
 327         B SPI2_IRQHandler\r
 328         \r
 329                 \r
 330         PUBWEAK USART1_IRQHandler\r
 331         SECTION .text:CODE:NOROOT:REORDER(1)\r
 332 USART1_IRQHandler\r
 333         B USART1_IRQHandler\r
 334         \r
 335                 \r
 336         PUBWEAK USART2_IRQHandler\r
 337         SECTION .text:CODE:NOROOT:REORDER(1)\r
 338 USART2_IRQHandler\r
 339         B USART2_IRQHandler\r
 340         \r
 341                 \r
 342         PUBWEAK CEC_IRQHandler\r
 343         SECTION .text:CODE:NOROOT:REORDER(1)\r
 344 CEC_IRQHandler\r
 345         B CEC_IRQHandler                        \r
 346 \r
 347         END\r
 348 /******************* (C) COPYRIGHT 2012 STMicroelectronics *****END OF FILE****/\r