git.sur5r.net Git - freertos/blob - FreeRTOS/Demo/CORTEX_M4F_CEC1302_Keil_GCC/GCC_Specific/startup_ARMCM4.S

   1 /* File: startup_ARMCM4.S
   2  * Purpose: startup file for Cortex-M4 devices. Should use with
   3  *   GCC for ARM Embedded Processors
   4  * Version: V2.0
   5  * Date: 16 August 2013
   6  *
   7 /* Copyright (c) 2011 - 2013 ARM LIMITED
   8
   9    All rights reserved.
  10    Redistribution and use in source and binary forms, with or without
  11    modification, are permitted provided that the following conditions are met:
  12    - Redistributions of source code must retain the above copyright
  13      notice, this list of conditions and the following disclaimer.
  14    - Redistributions in binary form must reproduce the above copyright
  15      notice, this list of conditions and the following disclaimer in the
  16      documentation and/or other materials provided with the distribution.
  17    - Neither the name of ARM nor the names of its contributors may be used
  18      to endorse or promote products derived from this software without
  19      specific prior written permission.
  20    *
  21    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  22    AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23    IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24    ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
  25    LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  26    CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  27    SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  28    INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  29    CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  30    ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  31    POSSIBILITY OF SUCH DAMAGE.
  32    ---------------------------------------------------------------------------*/
  33         .syntax unified
  34         .arch   armv7e-m
  35
  36         .extern __SRAM_segment_end__
  37
  38         .section .isr_vector,"a",%progbits
  39         .align  4
  40         .globl  __isr_vector
  41         .global __Vectors
  42
  43 __Vectors:
  44 __isr_vector:
  45         .long   __SRAM_segment_end__ - 4  /* Top of Stack at top of RAM*/
  46         .long   Reset_Handler         /* Reset Handler */
  47         .long   NMI_Handler           /* NMI Handler */
  48         .long   HardFault_Handler     /* Hard Fault Handler */
  49         .long   MemManage_Handler     /* MPU Fault Handler */
  50         .long   BusFault_Handler      /* Bus Fault Handler */
  51         .long   UsageFault_Handler    /* Usage Fault Handler */
  52         .long   0                     /* Reserved */
  53         .long   0                     /* Reserved */
  54         .long   0                     /* Reserved */
  55         .long   0                     /* Reserved */
  56         .long   SVC_Handler           /* SVCall Handler */
  57         .long   DebugMon_Handler      /* Debug Monitor Handler */
  58         .long   0                     /* Reserved */
  59         .long   PendSV_Handler        /* PendSV Handler */
  60         .long   SysTick_Handler       /* SysTick Handler */
  61
  62         /* External interrupts */
  63         .long     NVIC_Handler_I2C0
  64         .long     NVIC_Handler_I2C1
  65         .long     NVIC_Handler_I2C2
  66         .long     NVIC_Handler_I2C3
  67         .long     NVIC_Handler_DMA0
  68         .long     NVIC_Handler_DMA1
  69         .long     NVIC_Handler_DMA2
  70         .long     NVIC_Handler_DMA3
  71         .long     NVIC_Handler_DMA4
  72         .long     NVIC_Handler_DMA5
  73         .long     NVIC_Handler_DMA6
  74         .long     NVIC_Handler_DMA7
  75         .long     NVIC_Handler_LPCBERR
  76         .long     NVIC_Handler_UART0
  77         .long     NVIC_Handler_IMAP0
  78         .long     NVIC_Handler_EC0_IBF
  79         .long     NVIC_Handler_EC0_OBF
  80         .long     NVIC_Handler_EC1_IBF
  81         .long     NVIC_Handler_EC1_OBF
  82         .long     NVIC_Handler_PM1_CTL
  83         .long     NVIC_Handler_PM1_EN
  84         .long     NVIC_Handler_PM1_STS
  85         .long     NVIC_Handler_MIF8042_OBF
  86         .long     NVIC_Handler_MIF8042_IBF
  87         .long     NVIC_Handler_MAILBOX
  88         .long     NVIC_Handler_PECI
  89         .long     NVIC_Handler_TACH0
  90         .long     NVIC_Handler_TACH1
  91         .long     NVIC_Handler_ADC_SNGL
  92         .long     NVIC_Handler_ADC_RPT
  93         .long     NVIC_Handler_V2P_INT0
  94         .long     NVIC_Handler_V2P_INT1
  95         .long     NVIC_Handler_PS2_CH0
  96         .long     NVIC_Handler_PS2_CH1
  97         .long     NVIC_Handler_PS2_CH2
  98         .long     NVIC_Handler_PS2_CH3
  99         .long     NVIC_Handler_SPI0_TX
 100         .long     NVIC_Handler_SPI0_RX
 101         .long     NVIC_Handler_HIB_TMR
 102         .long     NVIC_Handler_KEY_INT
 103         .long     NVIC_Handler_KEY_WAKE
 104         .long     NVIC_Handler_RPM_STALL
 105         .long     NVIC_Handler_RPM_SPIN
 106         .long     NVIC_Handler_VBAT
 107         .long     NVIC_Handler_LED0
 108         .long     NVIC_Handler_LED1
 109         .long     NVIC_Handler_LED2
 110         .long     NVIC_Handler_MBC_ERR
 111         .long     NVIC_Handler_MBC_BUSY
 112         .long     NVIC_Handler_TMR0
 113         .long     NVIC_Handler_TMR1
 114         .long     NVIC_Handler_TMR2
 115         .long     NVIC_Handler_TMR3
 116         .long     NVIC_Handler_TMR4
 117         .long     NVIC_Handler_TMR5
 118         .long     NVIC_Handler_SPI1_TX
 119         .long     NVIC_Handler_SPI1_RX
 120         .long     NVIC_Handler_GIRQ08
 121         .long     NVIC_Handler_GIRQ09
 122         .long     NVIC_Handler_GIRQ10
 123         .long     NVIC_Handler_GIRQ11
 124         .long     NVIC_Handler_GIRQ12
 125         .long     NVIC_Handler_GIRQ13
 126         .long     NVIC_Handler_GIRQ14
 127         .long     NVIC_Handler_GIRQ15
 128         .long     NVIC_Handler_GIRQ16
 129         .long     NVIC_Handler_GIRQ17
 130         .long     NVIC_Handler_GIRQ18
 131         .long     NVIC_Handler_GIRQ19
 132         .long     NVIC_Handler_GIRQ20
 133         .long     NVIC_Handler_GIRQ21
 134         .long     NVIC_Handler_GIRQ22
 135         .long     NVIC_Handler_GIRQ23
 136         .long     NVIC_Handler_073
 137         .long     NVIC_Handler_074
 138         .long     NVIC_Handler_075
 139         .long     NVIC_Handler_076
 140         .long     NVIC_Handler_077
 141         .long     NVIC_Handler_078
 142         .long     NVIC_Handler_079
 143         .long     NVIC_Handler_080
 144         .long     NVIC_Handler_DMA8
 145         .long     NVIC_Handler_DMA9
 146         .long     NVIC_Handler_DMA10
 147         .long     NVIC_Handler_DMA11
 148         .long     NVIC_Handler_LED3
 149         .long     NVIC_Handler_PKE_ERR
 150         .long     NVIC_Handler_PKE_END
 151         .long     NVIC_Handler_TRNG
 152         .long     NVIC_Handler_AES
 153         .long     NVIC_Handler_HASH
 154
 155
 156         .text
 157         .thumb
 158         .thumb_func
 159         .align  2
 160         .globl _start
 161         .extern main
 162         .globl  Reset_Handler
 163         .type   Reset_Handler, %function
 164 _start:
 165 Reset_Handler:
 166 /*  Firstly it copies data from read only memory to RAM. There are two schemes
 167  *  to copy. One can copy more than one sections. Another can only copy
 168  *  one section.  The former scheme needs more instructions and read-only
 169  *  data to implement than the latter.
 170  *  Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes.  */
 171
 172 /*  Single section scheme.
 173  *
 174  *  The ranges of copy from/to are specified by following symbols
 175  *    __etext: LMA of start of the section to copy from. Usually end of text
 176  *    __data_start__: VMA of start of the section to copy to
 177  *    __data_end__: VMA of end of the section to copy to
 178  *
 179  *  All addresses must be aligned to 4 bytes boundary.
 180  */
 181         ldr sp, =__SRAM_segment_end__
 182         sub sp, sp, #4
 183
 184         ldr     r1, =__etext
 185         ldr     r2, =__data_start__
 186         ldr     r3, =__data_end__
 187
 188 .L_loop1:
 189         cmp     r2, r3
 190         ittt    lt
 191         ldrlt   r0, [r1], #4
 192         strlt   r0, [r2], #4
 193         blt     .L_loop1
 194
 195 /*  This part of work usually is done in C library startup code. Otherwise,
 196  *  define this macro to enable it in this startup.
 197  *
 198  *  There are two schemes too. One can clear multiple BSS sections. Another
 199  *  can only clear one section. The former is more size expensive than the
 200  *  latter.
 201  *
 202  *  Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
 203  *  Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
 204  */
 205
 206  /*  Single BSS section scheme.
 207  *
 208  *  The BSS section is specified by following symbols
 209  *    __bss_start__: start of the BSS section.
 210  *    __bss_end__: end of the BSS section.
 211  *
 212  *  Both addresses must be aligned to 4 bytes boundary.
 213  */
 214         ldr     r1, =__bss_start__
 215         ldr     r2, =__bss_end__
 216
 217         movs    r0, 0
 218 .L_loop3:
 219         cmp     r1, r2
 220         itt     lt
 221         strlt   r0, [r1], #4
 222         blt     .L_loop3
 223
 224 #ifndef __NO_SYSTEM_INIT
 225 /*      bl      SystemInit */
 226 #endif
 227
 228         bl      main
 229
 230         .pool
 231         .size   Reset_Handler, . - Reset_Handler
 232
 233         .align  1
 234         .thumb_func
 235         .weak   Default_Handler
 236         .type   Default_Handler, %function
 237 Default_Handler:
 238         b       .
 239         .size   Default_Handler, . - Default_Handler
 240
 241 /*    Macro to define default handlers. Default handler
 242  *    will be weak symbol and just dead loops. They can be
 243  *    overwritten by other handlers */
 244         .macro  def_irq_handler handler_name
 245         .weak   \handler_name
 246         .set    \handler_name, Default_Handler
 247         .endm
 248
 249         def_irq_handler NMI_Handler
 250         def_irq_handler HardFault_Handler
 251         def_irq_handler MemManage_Handler
 252         def_irq_handler BusFault_Handler
 253         def_irq_handler UsageFault_Handler
 254 /*      def_irq_handler SVC_Handler */
 255         def_irq_handler DebugMon_Handler
 256 /*      def_irq_handler PendSV_Handler */
 257 /*      def_irq_handler SysTick_Handler */
 258         def_irq_handler DEF_IRQHandler
 259
 260         def_irq_handler     NVIC_Handler_I2C0
 261         def_irq_handler     NVIC_Handler_I2C1
 262         def_irq_handler     NVIC_Handler_I2C2
 263         def_irq_handler     NVIC_Handler_I2C3
 264         def_irq_handler     NVIC_Handler_DMA0
 265         def_irq_handler     NVIC_Handler_DMA1
 266         def_irq_handler     NVIC_Handler_DMA2
 267         def_irq_handler     NVIC_Handler_DMA3
 268         def_irq_handler     NVIC_Handler_DMA4
 269         def_irq_handler     NVIC_Handler_DMA5
 270         def_irq_handler     NVIC_Handler_DMA6
 271         def_irq_handler     NVIC_Handler_DMA7
 272         def_irq_handler     NVIC_Handler_LPCBERR
 273         def_irq_handler     NVIC_Handler_UART0
 274         def_irq_handler     NVIC_Handler_IMAP0
 275         def_irq_handler     NVIC_Handler_EC0_IBF
 276         def_irq_handler     NVIC_Handler_EC0_OBF
 277         def_irq_handler     NVIC_Handler_EC1_IBF
 278         def_irq_handler     NVIC_Handler_EC1_OBF
 279         def_irq_handler     NVIC_Handler_PM1_CTL
 280         def_irq_handler     NVIC_Handler_PM1_EN
 281         def_irq_handler     NVIC_Handler_PM1_STS
 282         def_irq_handler     NVIC_Handler_MIF8042_OBF
 283         def_irq_handler     NVIC_Handler_MIF8042_IBF
 284         def_irq_handler     NVIC_Handler_MAILBOX
 285         def_irq_handler     NVIC_Handler_PECI
 286         def_irq_handler     NVIC_Handler_TACH0
 287         def_irq_handler     NVIC_Handler_TACH1
 288         def_irq_handler     NVIC_Handler_ADC_SNGL
 289         def_irq_handler     NVIC_Handler_ADC_RPT
 290         def_irq_handler     NVIC_Handler_V2P_INT0
 291         def_irq_handler     NVIC_Handler_V2P_INT1
 292         def_irq_handler     NVIC_Handler_PS2_CH0
 293         def_irq_handler     NVIC_Handler_PS2_CH1
 294         def_irq_handler     NVIC_Handler_PS2_CH2
 295         def_irq_handler     NVIC_Handler_PS2_CH3
 296         def_irq_handler     NVIC_Handler_SPI0_TX
 297         def_irq_handler     NVIC_Handler_SPI0_RX
 298         def_irq_handler     NVIC_Handler_HIB_TMR
 299         def_irq_handler     NVIC_Handler_KEY_INT
 300         def_irq_handler     NVIC_Handler_KEY_WAKE
 301         def_irq_handler     NVIC_Handler_RPM_STALL
 302         def_irq_handler     NVIC_Handler_RPM_SPIN
 303         def_irq_handler     NVIC_Handler_VBAT
 304         def_irq_handler     NVIC_Handler_LED0
 305         def_irq_handler     NVIC_Handler_LED1
 306         def_irq_handler     NVIC_Handler_LED2
 307         def_irq_handler     NVIC_Handler_MBC_ERR
 308         def_irq_handler     NVIC_Handler_MBC_BUSY
 309         def_irq_handler     NVIC_Handler_TMR0
 310         def_irq_handler     NVIC_Handler_TMR1
 311         def_irq_handler     NVIC_Handler_TMR2
 312         def_irq_handler     NVIC_Handler_TMR3
 313         def_irq_handler     NVIC_Handler_TMR4
 314         def_irq_handler     NVIC_Handler_TMR5
 315         def_irq_handler     NVIC_Handler_SPI1_TX
 316         def_irq_handler     NVIC_Handler_SPI1_RX
 317         def_irq_handler     NVIC_Handler_GIRQ08
 318         def_irq_handler     NVIC_Handler_GIRQ09
 319         def_irq_handler     NVIC_Handler_GIRQ10
 320         def_irq_handler     NVIC_Handler_GIRQ11
 321         ;def_irq_handler     NVIC_Handler_GIRQ12
 322         def_irq_handler     interrupt_irq12
 323         ;def_irq_handler     NVIC_Handler_GIRQ13
 324         def_irq_handler     interrupt_irq13
 325         def_irq_handler     NVIC_Handler_GIRQ14
 326         def_irq_handler     NVIC_Handler_GIRQ15
 327         def_irq_handler     NVIC_Handler_GIRQ16
 328         def_irq_handler     NVIC_Handler_GIRQ17
 329         def_irq_handler     NVIC_Handler_GIRQ18
 330         def_irq_handler     NVIC_Handler_GIRQ19
 331         def_irq_handler     NVIC_Handler_GIRQ20
 332         def_irq_handler     NVIC_Handler_GIRQ21
 333         def_irq_handler     NVIC_Handler_GIRQ22
 334         def_irq_handler     NVIC_Handler_GIRQ23
 335         def_irq_handler     NVIC_Handler_073
 336         def_irq_handler     NVIC_Handler_074
 337         def_irq_handler     NVIC_Handler_075
 338         def_irq_handler     NVIC_Handler_076
 339         def_irq_handler     NVIC_Handler_077
 340         def_irq_handler     NVIC_Handler_078
 341         def_irq_handler     NVIC_Handler_079
 342         def_irq_handler     NVIC_Handler_080
 343         def_irq_handler     NVIC_Handler_DMA8
 344         def_irq_handler     NVIC_Handler_DMA9
 345         def_irq_handler     NVIC_Handler_DMA10
 346         def_irq_handler     NVIC_Handler_DMA11
 347         def_irq_handler     NVIC_Handler_LED3
 348         def_irq_handler     NVIC_Handler_PKE_ERR
 349         def_irq_handler     NVIC_Handler_PKE_END
 350         def_irq_handler     NVIC_Handler_TRNG
 351         def_irq_handler     NVIC_Handler_AES
 352         def_irq_handler     NVIC_Handler_HASH
 353
 354         .end