2 * FreeRTOS Kernel V10.0.0
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3 * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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5 * Permission is hereby granted, free of charge, to any person obtaining a copy of
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6 * this software and associated documentation files (the "Software"), to deal in
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7 * the Software without restriction, including without limitation the rights to
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8 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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9 * the Software, and to permit persons to whom the Software is furnished to do so,
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10 * subject to the following conditions:
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12 * The above copyright notice and this permission notice shall be included in all
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13 * copies or substantial portions of the Software. If you wish to use our Amazon
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14 * FreeRTOS name, please do so in a fair use way that does not cause confusion.
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16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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18 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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19 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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20 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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23 * http://www.FreeRTOS.org
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24 * http://aws.amazon.com/freertos
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26 * 1 tab == 4 spaces!
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30 * This file initialises three timers as follows:
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32 * Basic timer channels 0 and 1 provide the interrupts that are used with the
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33 * IntQ standard demo tasks, which test interrupt nesting and using queues from
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34 * interrupts. The interrupts use slightly different frequencies so will
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35 * occasionally nest.
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37 * Basic timer channel 2 provides a much higher frequency timer that tests the
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38 * nesting of interrupts that don't use the FreeRTOS API.
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40 * All the timers can nest with the tick interrupt - creating a maximum
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41 * interrupt nesting depth of 4 (which is shown as a max nest count of 3 as the
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42 * tick interrupt does not increment the nesting count variable).
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46 /* Scheduler includes. */
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47 #include "FreeRTOS.h"
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50 /* Demo includes. */
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51 #include "IntQueueTimer.h"
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52 #include "IntQueue.h"
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54 /* Library includes. */
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55 #include "common_lib.h"
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56 #include "peripheral_library/interrupt/interrupt.h"
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57 #include "peripheral_library/basic_timer/btimer.h"
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59 /* The frequencies at which the first two timers expire are slightly offset to
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60 ensure they don't remain synchronised. The frequency of the highest priority
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61 interrupt is 20 times faster so really hammers the interrupt entry and exit
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63 #define tmrTIMER_0_FREQUENCY ( 2000UL )
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64 #define tmrTIMER_1_FREQUENCY ( 2003UL )
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65 #define tmrTIMER_2_FREQUENCY ( 20000UL )
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67 /* The basic timer channels used for generating the three interrupts. */
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68 #define tmrTIMER_CHANNEL_0 0 /* At tmrTIMER_0_FREQUENCY */
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69 #define tmrTIMER_CHANNEL_1 1 /* At tmrTIMER_1_FREQUENCY */
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70 #define tmrTIMER_CHANNEL_2 2 /* At tmrTIMER_2_FREQUENCY */
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72 /* The high frequency interrupt is given a priority above the maximum at which
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73 interrupt safe FreeRTOS calls can be made. The priority of the lower frequency
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74 timers must still be above the tick interrupt priority. */
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75 #define tmrLOWER_PRIORITY ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY + 1 )
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76 #define tmrMEDIUM_PRIORITY ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY + 0 )
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77 #define tmrHIGHER_PRIORITY ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY - 1 )
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79 /* Hardware register locations and bit definitions to enable the btimer
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81 #define tmrGIRQ23_ENABLE_SET ( * ( volatile uint32_t * ) 0x4000C130 )
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82 #define tmrGIRQ23_BIT_TIMER0 ( 1UL << 0UL )
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83 #define tmrGIRQ23_BIT_TIMER1 ( 1UL << 1UL )
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84 #define tmrGIRQ23_BIT_TIMER2 ( 1UL << 2UL )
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85 #define tmrGIRQ23_TIMER_BITS ( tmrGIRQ23_BIT_TIMER0 | tmrGIRQ23_BIT_TIMER1 | tmrGIRQ23_BIT_TIMER2 )
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87 #define tmrRECORD_NESTING_DEPTH() \
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89 if( ulNestingDepth > ulMaxRecordedNestingDepth ) \
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91 ulMaxRecordedNestingDepth = ulNestingDepth; \
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94 /* Used to count the nesting depth, and record the maximum nesting depth. */
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95 volatile uint32_t ulNestingDepth = 0, ulMaxRecordedNestingDepth = 0;
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97 /*-----------------------------------------------------------*/
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99 void vInitialiseTimerForIntQueueTest( void )
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101 const uint32_t ulTimer0Count = configCPU_CLOCK_HZ / tmrTIMER_0_FREQUENCY;
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102 const uint32_t ulTimer1Count = configCPU_CLOCK_HZ / tmrTIMER_1_FREQUENCY;
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103 const uint32_t ulTimer2Count = configCPU_CLOCK_HZ / tmrTIMER_2_FREQUENCY;
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105 tmrGIRQ23_ENABLE_SET = tmrGIRQ23_TIMER_BITS;
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107 /* Initialise the three timers as described at the top of this file, and
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108 enable their interrupts in the NVIC. */
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109 btimer_init( tmrTIMER_CHANNEL_0, BTIMER_AUTO_RESTART | BTIMER_COUNT_DOWN | BTIMER_INT_EN, 0, ulTimer0Count, ulTimer0Count );
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110 btimer_interrupt_status_get_clr( tmrTIMER_CHANNEL_0 );
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111 NVIC_SetPriority( TIMER0_IRQn, tmrLOWER_PRIORITY ); //0xc0 into 0xe000e431
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112 NVIC_ClearPendingIRQ( TIMER0_IRQn );
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113 NVIC_EnableIRQ( TIMER0_IRQn );
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114 btimer_start( tmrTIMER_CHANNEL_0 );
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116 btimer_init( tmrTIMER_CHANNEL_1, BTIMER_AUTO_RESTART | BTIMER_COUNT_DOWN | BTIMER_INT_EN, 0, ulTimer1Count, ulTimer1Count );
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117 btimer_interrupt_status_get_clr( tmrTIMER_CHANNEL_1 );
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118 NVIC_SetPriority( TIMER1_IRQn, tmrMEDIUM_PRIORITY ); //0xa0 into 0xe000e432
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119 NVIC_ClearPendingIRQ( TIMER1_IRQn );
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120 NVIC_EnableIRQ( TIMER1_IRQn );
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121 btimer_start( tmrTIMER_CHANNEL_1 );
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123 btimer_init( tmrTIMER_CHANNEL_2, BTIMER_AUTO_RESTART | BTIMER_COUNT_DOWN | BTIMER_INT_EN, 0, ulTimer2Count, ulTimer2Count );
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124 btimer_interrupt_status_get_clr( tmrTIMER_CHANNEL_2 );
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125 NVIC_SetPriority( TIMER2_IRQn, tmrHIGHER_PRIORITY );
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126 NVIC_ClearPendingIRQ( TIMER2_IRQn );
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127 NVIC_EnableIRQ( TIMER2_IRQn );
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128 btimer_start( tmrTIMER_CHANNEL_2 );
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130 /*-----------------------------------------------------------*/
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132 /* The TMR0 interrupt is used for different purposes by the low power and full
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133 demos respectively. */
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134 #if( configCREATE_LOW_POWER_DEMO == 0 )
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136 void NVIC_Handler_TMR0( void )
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138 tmrRECORD_NESTING_DEPTH();
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140 /* Call the IntQ test function for this channel. */
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141 portYIELD_FROM_ISR( xFirstTimerHandler() );
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146 #endif /* configCREATE_LOW_POWER_DEMO */
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147 /*-----------------------------------------------------------*/
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149 void NVIC_Handler_TMR1( void )
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151 tmrRECORD_NESTING_DEPTH();
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153 /* Just testing the xPortIsInsideInterrupt() functionality. */
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154 configASSERT( xPortIsInsideInterrupt() == pdTRUE );
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156 /* Call the IntQ test function for this channel. */
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157 portYIELD_FROM_ISR( xSecondTimerHandler() );
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161 /*-----------------------------------------------------------*/
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163 void NVIC_Handler_TMR2( void )
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165 tmrRECORD_NESTING_DEPTH();
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168 /*-----------------------------------------------------------*/
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