2 **********************************************************************************
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3 * © 2013 Microchip Technology Inc. and its subsidiaries.
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4 * You may use this software and any derivatives exclusively with
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5 * Microchip products.
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6 * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
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7 * NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
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8 * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
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9 * AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
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10 * PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
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11 * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
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12 * INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
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13 * WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
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14 * BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
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15 * TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
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16 * CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
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17 * FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
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18 * MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
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20 **********************************************************************************
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22 * This is the header to define Cortex-M3 system control & status registers
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23 **********************************************************************************
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24 * SMSC version control information (Perforce):
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26 * FILE: $File: //depot_pcs/FWEng/projects/MEC2016/Playground/pramans/160623_FreeRTOS_Microchip_MEC170x/Demo/CORTEX_MPU_MEC1701_Keil_GCC/peripheral_library/ARM_REG.h $
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27 * REVISION: $Revision: #1 $
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28 * DATETIME: $DateTime: 2016/09/22 08:03:49 $
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29 * AUTHOR: $Author: pramans $
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31 * Revision history (latest first):
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33 ***********************************************************************************
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36 /******************************************************************************/
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37 /** @defgroup ARM_REG ARM_REG
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42 * \brief ARM Cortex-M3 registers header file
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43 * \author KBCEC Team
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45 * This file contains ARM Cortex-M3 system control & status registers.
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46 ******************************************************************************/
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50 #define REG8(x) (*((volatile unsigned char *)(x)))
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51 #define REG16(x) (*((volatile unsigned short *)(x)))
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52 #define REG32(x) (*((volatile unsigned long *)(x)))
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54 /* NVIC Registers */
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55 #define NVIC_INT_TYPE REG32(0xE000E004)
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56 #define NVIC_AUX_ACTLR REG32(0xE000E008)
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57 #define WR_BUF_DISABLE (1 << 1)
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58 #define NVIC_ST_CTRL REG32(0xE000E010)
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59 #define ST_ENABLE (1 << 0)
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60 #define ST_TICKINT (1 << 1)
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61 #define ST_CLKSOURCE (1 << 2)
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62 #define ST_COUNTFLAG (1 << 3)
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63 #define NVIC_ST_RELOAD REG32(0xE000E014)
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64 #define NVIC_ST_CURRENT REG32(0xE000E018)
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65 #define NVIC_ST_CALIB REG32(0xE000E01C)
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66 #define NVIC_ENABLE0 REG32(0xE000E100)
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67 #define NVIC_ENABLE1 REG32(0xE000E104)
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68 #define NVIC_ENABLE2 REG32(0xE000E108)
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69 #define NVIC_ENABLE3 REG32(0xE000E10C)
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70 #define NVIC_ENABLE4 REG32(0xE000E110)
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71 #define NVIC_ENABLE5 REG32(0xE000E114)
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72 #define NVIC_ENABLE6 REG32(0xE000E118)
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73 #define NVIC_ENABLE7 REG32(0xE000E11C)
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74 #define NVIC_DISABLE0 REG32(0xE000E180)
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75 #define NVIC_DISABLE1 REG32(0xE000E184)
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76 #define NVIC_DISABLE2 REG32(0xE000E188)
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77 #define NVIC_DISABLE3 REG32(0xE000E18C)
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78 #define NVIC_DISABLE4 REG32(0xE000E190)
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79 #define NVIC_DISABLE5 REG32(0xE000E194)
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80 #define NVIC_DISABLE6 REG32(0xE000E198)
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81 #define NVIC_DISABLE7 REG32(0xE000E19C)
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82 #define NVIC_PEND0 REG32(0xE000E200)
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83 #define NVIC_PEND1 REG32(0xE000E204)
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84 #define NVIC_PEND2 REG32(0xE000E208)
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85 #define NVIC_PEND3 REG32(0xE000E20C)
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86 #define NVIC_PEND4 REG32(0xE000E210)
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87 #define NVIC_PEND5 REG32(0xE000E214)
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88 #define NVIC_PEND6 REG32(0xE000E218)
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89 #define NVIC_PEND7 REG32(0xE000E21C)
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90 #define NVIC_UNPEND0 REG32(0xE000E280)
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91 #define NVIC_UNPEND1 REG32(0xE000E284)
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92 #define NVIC_UNPEND2 REG32(0xE000E288)
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93 #define NVIC_UNPEND3 REG32(0xE000E28C)
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94 #define NVIC_UNPEND4 REG32(0xE000E290)
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95 #define NVIC_UNPEND5 REG32(0xE000E294)
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96 #define NVIC_UNPEND6 REG32(0xE000E298)
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97 #define NVIC_UNPEND7 REG32(0xE000E29C)
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98 #define NVIC_ACTIVE0 REG32(0xE000E300)
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99 #define NVIC_ACTIVE1 REG32(0xE000E304)
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100 #define NVIC_ACTIVE2 REG32(0xE000E308)
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101 #define NVIC_ACTIVE3 REG32(0xE000E30C)
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102 #define NVIC_ACTIVE4 REG32(0xE000E310)
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103 #define NVIC_ACTIVE5 REG32(0xE000E314)
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104 #define NVIC_ACTIVE6 REG32(0xE000E318)
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105 #define NVIC_ACTIVE7 REG32(0xE000E31C)
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106 #define NVIC_PRI0 REG32(0xE000E400)
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107 #define NVIC_PRI1 REG32(0xE000E404)
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108 #define NVIC_PRI2 REG32(0xE000E408)
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109 #define NVIC_PRI3 REG32(0xE000E40C)
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110 #define NVIC_PRI4 REG32(0xE000E410)
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111 #define NVIC_PRI5 REG32(0xE000E414)
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112 #define NVIC_PRI6 REG32(0xE000E418)
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113 #define NVIC_PRI7 REG32(0xE000E41C)
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114 #define NVIC_PRI8 REG32(0xE000E420)
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115 #define NVIC_PRI9 REG32(0xE000E424)
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116 #define NVIC_PRI10 REG32(0xE000E428)
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117 #define NVIC_PRI11 REG32(0xE000E42C)
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118 #define NVIC_PRI12 REG32(0xE000E430)
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119 #define NVIC_PRI13 REG32(0xE000E434)
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120 #define NVIC_PRI14 REG32(0xE000E438)
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121 #define NVIC_PRI15 REG32(0xE000E43C)
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122 #define NVIC_PRI16 REG32(0xE000E440)
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123 #define NVIC_PRI17 REG32(0xE000E444)
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124 #define NVIC_PRI18 REG32(0xE000E448)
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125 #define NVIC_PRI19 REG32(0xE000E44C)
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126 #define NVIC_PRI20 REG32(0xE000E450)
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127 #define NVIC_PRI21 REG32(0xE000E454)
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128 #define NVIC_PRI22 REG32(0xE000E458)
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129 #define NVIC_PRI23 REG32(0xE000E45C)
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130 #define NVIC_PRI24 REG32(0xE000E460)
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131 #define NVIC_PRI25 REG32(0xE000E464)
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132 #define NVIC_PRI26 REG32(0xE000E468)
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133 #define NVIC_PRI27 REG32(0xE000E46C)
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134 #define NVIC_PRI28 REG32(0xE000E470)
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135 #define NVIC_PRI29 REG32(0xE000E474)
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136 #define NVIC_PRI30 REG32(0xE000E478)
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137 #define NVIC_PRI31 REG32(0xE000E47C)
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138 #define NVIC_PRI32 REG32(0xE000E480)
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139 #define NVIC_PRI33 REG32(0xE000E484)
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140 #define NVIC_PRI34 REG32(0xE000E488)
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141 #define NVIC_PRI35 REG32(0xE000E48C)
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142 #define NVIC_PRI36 REG32(0xE000E490)
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143 #define NVIC_PRI37 REG32(0xE000E494)
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144 #define NVIC_PRI38 REG32(0xE000E498)
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145 #define NVIC_PRI39 REG32(0xE000E49C)
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146 #define NVIC_PRI40 REG32(0xE000E4A0)
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147 #define NVIC_PRI41 REG32(0xE000E4A4)
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148 #define NVIC_PRI42 REG32(0xE000E4A8)
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149 #define NVIC_PRI43 REG32(0xE000E4AC)
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150 #define NVIC_PRI44 REG32(0xE000E4B0)
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151 #define NVIC_PRI45 REG32(0xE000E4B4)
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152 #define NVIC_PRI46 REG32(0xE000E4B8)
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153 #define NVIC_PRI47 REG32(0xE000E4BC)
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154 #define NVIC_PRI48 REG32(0xE000E4C0)
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155 #define NVIC_PRI49 REG32(0xE000E4C4)
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156 #define NVIC_PRI50 REG32(0xE000E4C8)
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157 #define NVIC_PRI51 REG32(0xE000E4CC)
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158 #define NVIC_PRI52 REG32(0xE000E4D0)
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159 #define NVIC_PRI53 REG32(0xE000E4D4)
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160 #define NVIC_PRI54 REG32(0xE000E4D8)
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161 #define NVIC_PRI55 REG32(0xE000E4DC)
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162 #define NVIC_PRI56 REG32(0xE000E4E0)
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163 #define NVIC_PRI57 REG32(0xE000E4E4)
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164 #define NVIC_PRI58 REG32(0xE000E4E8)
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165 #define NVIC_PRI59 REG32(0xE000E4EC)
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166 #define NVIC_CPUID REG32(0xE000ED00)
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167 #define NVIC_INT_CTRL REG32(0xE000ED04)
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168 #define NVIC_VECT_TABLE REG32(0xE000ED08)
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169 #define NVIC_AP_INT_RST REG32(0xE000ED0C)
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170 #define NVIC_SYS_CTRL REG32(0xE000ED10)
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171 #define NVIC_CFG_CTRL REG32(0xE000ED14)
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172 #define NVIC_SYS_H_PRI1 REG32(0xE000ED18)
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173 #define NVIC_SYS_H_PRI2 REG32(0xE000ED1C)
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174 #define NVIC_SYS_H_PRI3 REG32(0xE000ED20)
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175 #define NVIC_SYS_H_CTRL REG32(0xE000ED24)
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176 #define NVIC_FAULT_STA REG32(0xE000ED28)
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177 #define NVIC_HARD_F_STA REG32(0xE000ED2C)
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178 #define NVIC_DBG_F_STA REG32(0xE000ED30)
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179 #define NVIC_MM_F_ADR REG32(0xE000ED34)
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180 #define NVIC_BUS_F_ADR REG32(0xE000ED38)
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181 #define NVIC_SW_TRIG REG32(0xE000EF00)
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183 /* MPU Registers */
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184 #define MPU_TYPE REG32(0xE000ED90)
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185 #define MPU_CTRL REG32(0xE000ED94)
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186 #define MPU_RG_NUM REG32(0xE000ED98)
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187 #define MPU_RG_ADDR REG32(0xE000ED9C)
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188 #define MPU_RG_AT_SZ REG32(0xE000EDA0)
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191 #endif /* #ifndef ARM_REG_H_ */
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projects / freertos / blob