1 /*****************************************************************************
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2 * © 2015 Microchip Technology Inc. and its subsidiaries.
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3 * You may use this software and any derivatives exclusively with
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4 * Microchip products.
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5 * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
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6 * NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
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7 * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
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8 * AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
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9 * PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
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10 * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
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11 * INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
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12 * WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
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13 * BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
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14 * TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
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15 * CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
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16 * FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
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17 * MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
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19 ******************************************************************************
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21 Version Control Information (Perforce)
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22 ******************************************************************************
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24 $DateTime: 2016/09/22 08:03:49 $
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26 Last Change: Renamed ecia_init to interrupt_init
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27 ******************************************************************************/
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28 /** @file interrupt.h
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29 * \brief Interrupt Header File
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32 * This file implements the Interrupt Module Header file
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33 ******************************************************************************/
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35 /** @defgroup Interrupt
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39 #ifndef _INTERRUPT_H
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40 #define _INTERRUPT_H
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42 // GIRQ IDs for EC Interrupt Aggregator
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64 //Bitmask of GIRQ in ECIA Block Registers
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65 #define MEC_GIRQ08_BITMASK (1UL << (MEC_GIRQ08_ID + 8))
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66 #define MEC_GIRQ09_BITMASK (1UL << (MEC_GIRQ09_ID + 8))
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67 #define MEC_GIRQ10_BITMASK (1UL << (MEC_GIRQ10_ID + 8))
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68 #define MEC_GIRQ11_BITMASK (1UL << (MEC_GIRQ11_ID + 8))
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69 #define MEC_GIRQ12_BITMASK (1UL << (MEC_GIRQ12_ID + 8))
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70 #define MEC_GIRQ13_BITMASK (1UL << (MEC_GIRQ13_ID + 8))
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71 #define MEC_GIRQ14_BITMASK (1UL << (MEC_GIRQ14_ID + 8))
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72 #define MEC_GIRQ15_BITMASK (1UL << (MEC_GIRQ15_ID + 8))
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73 #define MEC_GIRQ16_BITMASK (1UL << (MEC_GIRQ16_ID + 8))
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74 #define MEC_GIRQ17_BITMASK (1UL << (MEC_GIRQ17_ID + 8))
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75 #define MEC_GIRQ18_BITMASK (1UL << (MEC_GIRQ18_ID + 8))
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76 #define MEC_GIRQ19_BITMASK (1UL << (MEC_GIRQ19_ID + 8))
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77 #define MEC_GIRQ20_BITMASK (1UL << (MEC_GIRQ20_ID + 8))
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78 #define MEC_GIRQ21_BITMASK (1UL << (MEC_GIRQ21_ID + 8))
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79 #define MEC_GIRQ22_BITMASK (1UL << (MEC_GIRQ22_ID + 8))
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80 #define MEC_GIRQ23_BITMASK (1UL << (MEC_GIRQ23_ID + 8))
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82 #define INTERRUPT_MODE_ALL_AGGREGATED (0u)
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83 #define INTERRUPT_MODE_DIRECT (1u)
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85 // Bit map of GIRQs whose sources can be directly connected to the NVIC
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86 // GIRQs 13 - 19, 21, 23, 24-26
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87 #define ECIA_GIRQ_DIRECT_BITMAP (0x07AFE000ul)
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90 * n = b[7:0] = zero-based direct mapped NVIC ID
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91 * m = b[15:8] = zero-based aggregated NVIC ID
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92 * a = b[23:16] = block Aggregator register block ID
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93 * b = b[31:24] = block bit position in Aggregator registers
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95 #define IROUTE(b,a,m,n) (((uint32_t)(n)&0xFFul) + \
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96 (((uint32_t)(m)&0xFFul)<<8u) + \
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97 ((((uint32_t)(a)-8ul)&0x0F)<<16u) + \
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98 (((uint32_t)(b)&0x1Ful)<<24))
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100 #define ECIA_NVIC_ID_BITPOS (0u)
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101 #define ECIA_IA_NVIC_ID_BITPOS (8u)
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102 #define ECIA_GIRQ_ID_BITPOS (16u)
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103 #define ECIA_GIRQ_BIT_BITPOS (24u)
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108 #define GPIO_0140_IROUTE IROUTE(0,8,0,0)
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109 #define GPIO_0141_IROUTE IROUTE(1,8,0,0)
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110 #define GPIO_0142_IROUTE IROUTE(2,8,0,0)
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111 #define GPIO_0143_IROUTE IROUTE(3,8,0,0)
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112 #define GPIO_0144_IROUTE IROUTE(4,8,0,0)
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113 #define GPIO_0145_IROUTE IROUTE(5,8,0,0)
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114 #define GPIO_0147_IROUTE IROUTE(7,8,0,0)
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116 #define GPIO_0150_IROUTE IROUTE(8,8,0,0)
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117 #define GPIO_0151_IROUTE IROUTE(9,8,0,0)
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118 #define GPIO_0152_IROUTE IROUTE(10,8,0,0)
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119 #define GPIO_0153_IROUTE IROUTE(11,8,0,0)
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120 #define GPIO_0154_IROUTE IROUTE(12,8,0,0)
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121 #define GPIO_0155_IROUTE IROUTE(13,8,0,0)
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122 #define GPIO_0156_IROUTE IROUTE(14,8,0,0)
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123 #define GPIO_0157_IROUTE IROUTE(15,8,0,0)
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125 #define GPIO_0160_IROUTE IROUTE(16,8,0,0)
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126 #define GPIO_0161_IROUTE IROUTE(17,8,0,0)
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127 #define GPIO_0162_IROUTE IROUTE(18,8,0,0)
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128 #define GPIO_0163_IROUTE IROUTE(19,8,0,0)
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129 #define GPIO_0164_IROUTE IROUTE(20,8,0,0)
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130 #define GPIO_0165_IROUTE IROUTE(21,8,0,0)
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131 #define GPIO_0166_IROUTE IROUTE(22,8,0,0)
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132 #define GPIO_0167_IROUTE IROUTE(23,8,0,0)
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134 #define GPIO_0170_IROUTE IROUTE(24,8,0,0)
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135 #define GPIO_0171_IROUTE IROUTE(25,8,0,0)
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136 #define GPIO_0172_IROUTE IROUTE(26,8,0,0)
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137 #define GPIO_0173_IROUTE IROUTE(27,8,0,0)
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138 #define GPIO_0174_IROUTE IROUTE(28,8,0,0)
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139 #define GPIO_0175_IROUTE IROUTE(29,8,0,0)
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140 #define GPIO_0176_IROUTE IROUTE(30,8,0,0)
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145 #define GPIO_0100_IROUTE IROUTE(0,9,1,1)
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146 #define GPIO_0101_IROUTE IROUTE(1,9,1,1)
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147 #define GPIO_0102_IROUTE IROUTE(2,9,1,1)
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148 #define GPIO_0103_IROUTE IROUTE(3,9,1,1)
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149 #define GPIO_0104_IROUTE IROUTE(4,9,1,1)
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150 #define GPIO_0105_IROUTE IROUTE(5,9,1,1)
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151 #define GPIO_0105_IROUTE IROUTE(5,9,1,1)
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152 #define GPIO_0107_IROUTE IROUTE(7,9,1,1)
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154 #define GPIO_0110_IROUTE IROUTE(8,9,1,1)
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155 #define GPIO_0111_IROUTE IROUTE(9,9,1,1)
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156 #define GPIO_0112_IROUTE IROUTE(10,9,1,1)
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157 #define GPIO_0113_IROUTE IROUTE(11,9,1,1)
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158 #define GPIO_0114_IROUTE IROUTE(12,9,1,1)
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159 #define GPIO_0115_IROUTE IROUTE(13,9,1,1)
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160 #define GPIO_0116_IROUTE IROUTE(14,9,1,1)
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161 #define GPIO_0117_IROUTE IROUTE(15,9,1,1)
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163 #define GPIO_0120_IROUTE IROUTE(16,9,1,1)
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164 #define GPIO_0121_IROUTE IROUTE(17,9,1,1)
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165 #define GPIO_0122_IROUTE IROUTE(18,9,1,1)
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166 #define GPIO_0124_IROUTE IROUTE(20,9,1,1)
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167 #define GPIO_0125_IROUTE IROUTE(21,9,1,1)
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168 #define GPIO_0126_IROUTE IROUTE(22,9,1,1)
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169 #define GPIO_0127_IROUTE IROUTE(23,9,1,1)
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171 #define GPIO_0130_IROUTE IROUTE(24,9,1,1)
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172 #define GPIO_0131_IROUTE IROUTE(25,9,1,1)
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173 #define GPIO_0132_IROUTE IROUTE(26,9,1,1)
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174 #define GPIO_0133_IROUTE IROUTE(27,9,1,1)
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175 #define GPIO_0134_IROUTE IROUTE(28,9,1,1)
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176 #define GPIO_0135_IROUTE IROUTE(29,9,1,1)
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177 #define GPIO_0136_IROUTE IROUTE(30,9,1,1)
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182 #define GPIO_0040_IROUTE IROUTE(0,10,2,2)
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183 #define GPIO_0041_IROUTE IROUTE(1,10,2,2)
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184 #define GPIO_0042_IROUTE IROUTE(2,10,2,2)
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185 #define GPIO_0043_IROUTE IROUTE(3,10,2,2)
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186 #define GPIO_0044_IROUTE IROUTE(4,10,2,2)
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187 #define GPIO_0045_IROUTE IROUTE(5,10,2,2)
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188 #define GPIO_0045_IROUTE IROUTE(5,10,2,2)
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189 #define GPIO_0047_IROUTE IROUTE(7,10,2,2)
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191 #define GPIO_0050_IROUTE IROUTE(8,10,2,2)
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192 #define GPIO_0051_IROUTE IROUTE(9,10,2,2)
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193 #define GPIO_0052_IROUTE IROUTE(10,10,2,2)
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194 #define GPIO_0053_IROUTE IROUTE(11,10,2,2)
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195 #define GPIO_0054_IROUTE IROUTE(12,10,2,2)
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196 #define GPIO_0055_IROUTE IROUTE(13,10,2,2)
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197 #define GPIO_0056_IROUTE IROUTE(14,10,2,2)
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198 #define GPIO_0057_IROUTE IROUTE(15,10,2,2)
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200 #define GPIO_0060_IROUTE IROUTE(16,10,2,2)
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201 #define GPIO_0061_IROUTE IROUTE(17,10,2,2)
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202 #define GPIO_0062_IROUTE IROUTE(18,10,2,2)
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203 #define GPIO_0063_IROUTE IROUTE(19,10,2,2)
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204 #define GPIO_0064_IROUTE IROUTE(20,10,2,2)
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205 #define GPIO_0065_IROUTE IROUTE(21,10,2,2)
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206 #define GPIO_0066_IROUTE IROUTE(22,10,2,2)
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207 #define GPIO_0067_IROUTE IROUTE(23,10,2,2)
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209 #define GPIO_0070_IROUTE IROUTE(24,10,2,2)
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210 #define GPIO_0071_IROUTE IROUTE(25,10,2,2)
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211 #define GPIO_0072_IROUTE IROUTE(26,10,2,2)
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212 #define GPIO_0073_IROUTE IROUTE(27,10,2,2)
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213 #define GPIO_0074_IROUTE IROUTE(28,10,2,2)
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214 #define GPIO_0075_IROUTE IROUTE(29,10,2,2)
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215 #define GPIO_0076_IROUTE IROUTE(30,10,2,2)
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220 #define GPIO_0000_IROUTE IROUTE(0,11,3,3)
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221 #define GPIO_0001_IROUTE IROUTE(1,11,3,3)
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222 #define GPIO_0002_IROUTE IROUTE(2,11,3,3)
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223 #define GPIO_0003_IROUTE IROUTE(3,11,3,3)
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224 #define GPIO_0004_IROUTE IROUTE(4,11,3,3)
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225 #define GPIO_0005_IROUTE IROUTE(5,11,3,3)
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226 #define GPIO_0006_IROUTE IROUTE(6,11,3,3)
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227 #define GPIO_0007_IROUTE IROUTE(7,11,3,3)
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229 #define GPIO_0010_IROUTE IROUTE(8,11,3,3)
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230 #define GPIO_0011_IROUTE IROUTE(9,11,3,3)
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231 #define GPIO_0012_IROUTE IROUTE(10,11,3,3)
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232 #define GPIO_0013_IROUTE IROUTE(11,11,3,3)
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233 #define GPIO_0014_IROUTE IROUTE(12,11,3,3)
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234 #define GPIO_0015_IROUTE IROUTE(13,11,3,3)
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235 #define GPIO_0016_IROUTE IROUTE(14,11,3,3)
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236 #define GPIO_0017_IROUTE IROUTE(15,11,3,3)
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238 #define GPIO_0020_IROUTE IROUTE(16,11,3,3)
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239 #define GPIO_0021_IROUTE IROUTE(17,11,3,3)
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240 #define GPIO_0022_IROUTE IROUTE(18,11,3,3)
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241 #define GPIO_0023_IROUTE IROUTE(19,11,3,3)
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242 #define GPIO_0024_IROUTE IROUTE(20,11,3,3)
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243 #define GPIO_0025_IROUTE IROUTE(21,11,3,3)
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244 #define GPIO_0026_IROUTE IROUTE(22,11,3,3)
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245 #define GPIO_0027_IROUTE IROUTE(23,11,3,3)
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247 #define GPIO_0030_IROUTE IROUTE(24,11,3,3)
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248 #define GPIO_0031_IROUTE IROUTE(25,11,3,3)
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249 #define GPIO_0032_IROUTE IROUTE(26,11,3,3)
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250 #define GPIO_0033_IROUTE IROUTE(27,11,3,3)
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251 #define GPIO_0034_IROUTE IROUTE(28,11,3,3)
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252 #define GPIO_0035_IROUTE IROUTE(29,11,3,3)
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253 #define GPIO_0036_IROUTE IROUTE(30,11,3,3)
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258 #define GPIO_0200_IROUTE IROUTE(0,12,4,4)
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259 #define GPIO_0201_IROUTE IROUTE(1,12,4,4)
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260 #define GPIO_0202_IROUTE IROUTE(2,12,4,4)
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261 #define GPIO_0203_IROUTE IROUTE(3,12,4,4)
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262 #define GPIO_0204_IROUTE IROUTE(4,12,4,4)
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263 #define GPIO_0205_IROUTE IROUTE(5,12,4,4)
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264 #define GPIO_0206_IROUTE IROUTE(6,12,4,4)
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265 #define GPIO_0207_IROUTE IROUTE(7,12,4,4)
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267 #define GPIO_0210_IROUTE IROUTE(8,12,4,4)
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268 #define GPIO_0211_IROUTE IROUTE(9,12,4,4)
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269 #define GPIO_0212_IROUTE IROUTE(10,12,4,4)
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270 #define GPIO_0213_IROUTE IROUTE(11,12,4,4)
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271 #define GPIO_0214_IROUTE IROUTE(12,12,4,4)
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272 #define GPIO_0215_IROUTE IROUTE(13,12,4,4)
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273 #define GPIO_0216_IROUTE IROUTE(14,12,4,4)
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274 #define GPIO_0217_IROUTE IROUTE(15,12,4,4)
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276 #define GPIO_0220_IROUTE IROUTE(16,12,4,4)
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277 #define GPIO_0221_IROUTE IROUTE(17,12,4,4)
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278 #define GPIO_0222_IROUTE IROUTE(18,12,4,4)
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279 #define GPIO_0223_IROUTE IROUTE(19,12,4,4)
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280 #define GPIO_0224_IROUTE IROUTE(20,12,4,4)
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281 #define GPIO_0225_IROUTE IROUTE(21,12,4,4)
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282 #define GPIO_0226_IROUTE IROUTE(22,12,4,4)
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283 #define GPIO_0227_IROUTE IROUTE(23,12,4,4)
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285 #define GPIO_0230_IROUTE IROUTE(24,12,4,4)
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286 #define GPIO_0231_IROUTE IROUTE(25,12,4,4)
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287 #define GPIO_0232_IROUTE IROUTE(26,12,4,4)
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288 #define GPIO_0233_IROUTE IROUTE(27,12,4,4)
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289 #define GPIO_0234_IROUTE IROUTE(28,12,4,4)
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290 #define GPIO_0235_IROUTE IROUTE(29,12,4,4)
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291 #define GPIO_0236_IROUTE IROUTE(30,12,4,4)
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298 #define SMB0_IROUTE IROUTE(0,13,5,20)
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299 #define SMB1_IROUTE IROUTE(1,13,5,21)
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300 #define SMB2_IROUTE IROUTE(2,13,5,22)
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301 #define SMB3_IROUTE IROUTE(3,13,5,23)
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306 #define DMA0_IROUTE IROUTE(0,14,6,24)
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307 #define DMA1_IROUTE IROUTE(1,14,6,25)
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308 #define DMA2_IROUTE IROUTE(2,14,6,26)
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309 #define DMA3_IROUTE IROUTE(3,14,6,27)
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310 #define DMA4_IROUTE IROUTE(4,14,6,28)
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311 #define DMA5_IROUTE IROUTE(5,14,6,29)
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312 #define DMA6_IROUTE IROUTE(6,14,6,30)
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313 #define DMA7_IROUTE IROUTE(7,14,6,31)
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314 #define DMA8_IROUTE IROUTE(8,14,6,33)
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315 #define DMA9_IROUTE IROUTE(9,14,6,33)
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316 #define DMA10_IROUTE IROUTE(10,14,6,34)
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317 #define DMA11_IROUTE IROUTE(11,14,6,35)
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318 #define DMA12_IROUTE IROUTE(12,14,6,36)
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319 #define DMA13_IROUTE IROUTE(13,14,6,37)
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325 #define UART0_IROUTE IROUTE(0,15,7,40)
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326 #define UART1_IROUTE IROUTE(1,15,7,41)
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327 #define EMI0_IROUTE IROUTE(2,15,7,42)
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328 #define EMI1_IROUTE IROUTE(3,15,7,43)
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329 #define EMI2_IROUTE IROUTE(4,15,7,44)
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330 #define ACPI_EC0_IBF_IROUTE IROUTE(5,15,7,45)
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331 #define ACPI_EC0_OBF_IROUTE IROUTE(6,15,7,46)
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332 #define ACPI_EC1_IBF_IROUTE IROUTE(7,15,7,47)
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333 #define ACPI_EC1_OBF_IROUTE IROUTE(8,15,7,48)
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334 #define ACPI_EC2_IBF_IROUTE IROUTE(9,15,7,49)
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335 #define ACPI_EC2_OBF_IROUTE IROUTE(10,15,7,50)
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336 #define ACPI_EC3_IBF_IROUTE IROUTE(11,15,7,51)
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337 #define ACPI_EC3_OBF_IROUTE IROUTE(12,15,7,52)
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338 #define ACPI_EC4_IBF_IROUTE IROUTE(13,15,7,53)
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339 #define ACPI_EC4_OBF_IROUTE IROUTE(14,15,7,54)
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340 #define ACPI_PM1_CTL_IROUTE IROUTE(15,15,7,55)
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341 #define ACPI_PM1_EN_IROUTE IROUTE(16,15,7,56)
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342 #define ACPI_PM1_STS_IROUTE IROUTE(17,15,7,57)
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343 #define EM8042_OBF_IROUTE IROUTE(18,15,7,58)
\r
344 #define EM8042_IBF_IROUTE IROUTE(19,15,7,59)
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345 #define MBOX_IROUTE IROUTE(20,15,7,60)
\r
346 #define PORT80_DBG0_BDPINT_IROUTE IROUTE(22,15,7,62)
\r
347 #define PORT80_DBG1_BDPINT_IROUTE IROUTE(23,15,7,63)
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348 #define TEST_IROUTE IROUTE(24,15,7,64)
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353 #define PKE_ERROR_IROUTE IROUTE(0,16,8,65)
\r
354 #define PKE_END_IROUTE IROUTE(1,16,8,66)
\r
355 #define RNG_IROUTE IROUTE(2,16,8,67)
\r
356 #define AES_IROUTE IROUTE(3,16,8,68)
\r
357 #define HASH_IROUTE IROUTE(4,16,8,69)
\r
362 #define PECI_IROUTE IROUTE(0,17,9,70)
\r
363 #define TACH0_IROUTE IROUTE(1,17,9,71)
\r
364 #define TACH1_IROUTE IROUTE(2,17,9,72)
\r
365 #define TACH2_IROUTE IROUTE(3,17,9,73)
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366 #define RPM2PWM0_FAIL_IROUTE IROUTE(4,17,9,74)
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367 #define RPM2PWM0_STALL_IROUTE IROUTE(5,17,9,75)
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368 #define RPM2PWM1_FAIL_IROUTE IROUTE(6,17,9,76)
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369 #define RPM2PWM1_STALL_IROUTE IROUTE(7,17,9,77)
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370 #define ADC_SNGL_IROUTE IROUTE(8,17,9,78)
\r
371 #define ADC_RPT_IROUTE IROUTE(9,17,9,79)
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372 #define RC_ID0_IROUTE IROUTE(10,17,9,80)
\r
373 #define RC_ID1_IROUTE IROUTE(11,17,9,81)
\r
374 #define RC_ID2_IROUTE IROUTE(12,17,9,82)
\r
375 #define LED0_IROUTE IROUTE(13,17,9,83)
\r
376 #define LED1_IROUTE IROUTE(14,17,9,84)
\r
377 #define LED2_IROUTE IROUTE(15,17,9,85)
\r
378 #define LED3_IROUTE IROUTE(16,17,9,86)
\r
379 #define PHOT_IROUTE IROUTE(17,17,9,87)
\r
380 #define POWER_GUARD0_IROUTE IROUTE(18,17,9,88)
\r
381 #define POWER_GUARD1_IROUTE IROUTE(19,17,9,89)
\r
382 #define RTOS_SWI0_IROUTE IROUTE(25,17,9,9)
\r
383 #define RTOS_SWI1_IROUTE IROUTE(26,17,9,9)
\r
384 #define RTOS_SWI2_IROUTE IROUTE(27,17,9,9)
\r
385 #define RTOS_SWI3_IROUTE IROUTE(28,17,9,9)
\r
390 #define LPC_INT_ERR_IROUTE IROUTE(0,18,10,90)
\r
391 #define QMSPI_INT_IROUTE IROUTE(1,18,10,91)
\r
392 #define GP_SPI0_TXBE_STS_IROUTE IROUTE(2,18,10,92)
\r
393 #define GP_SPI0_RXBF_STS_IROUTE IROUTE(3,18,10,93)
\r
394 #define GP_SPI1_TXBE_STS_IROUTE IROUTE(4,18,10,94)
\r
395 #define GP_SPI1_RXBF_STS_IROUTE IROUTE(5,18,10,95)
\r
396 #define BCLINK0_BCM_ERR_IROUTE IROUTE(6,18,10,96)
\r
397 #define BCLINK0_BUSY_CLR_IROUTE IROUTE(7,18,10,97)
\r
398 #define BCLINK1_BCM_ERR_IROUTE IROUTE(8,18,10,98)
\r
399 #define BCLINK1_BUSY_CLR_IROUTE IROUTE(9,18,10,99)
\r
400 #define PS2_IFACE0_ACT_IROUTE IROUTE(10,18,10,100)
\r
401 #define PS2_IFACE1_ACT_IROUTE IROUTE(11,18,10,101)
\r
402 #define PS2_IFACE2_ACT_IROUTE IROUTE(12,18,10,102)
\r
403 #define EEPROM_IROUTE IROUTE(13,18,10,155)
\r
409 #define ESPI_SLAVE_INTR_PC_IROUTE IROUTE(0,19,11,103)
\r
410 #define ESPI_SLAVE_INTR_BM1_IROUTE IROUTE(1,19,11,104)
\r
411 #define ESPI_SLAVE_INTR_BM2_IROUTE IROUTE(2,19,11,105)
\r
412 #define ESPI_SLAVE_INTR_LTR_IROUTE IROUTE(3,19,11,106)
\r
413 #define ESPI_SLAVE_INTR_OOB_UP_IROUTE IROUTE(4,19,11,107)
\r
414 #define ESPI_SLAVE_INTR_OOB_DN_IROUTE IROUTE(5,19,11,108)
\r
415 #define ESPI_SLAVE_INTR_FLASH_IROUTE IROUTE(6,19,11,109)
\r
416 #define ESPI_SLAVE_ESPI_RESET_IROUTE IROUTE(7,19,11,110)
\r
417 #define ESPI_SLAVE_VW_ENABLE_IROUTE IROUTE(8,19,11,156)
\r
427 #define RTOS_TIMER_IROUTE IROUTE(0,21,13,111)
\r
428 #define HTIMER0_IROUTE IROUTE(1,21,13,112)
\r
429 #define HTIMER1_IROUTE IROUTE(2,21,13,113)
\r
430 #define WEEK_ALARM_INT_IROUTE IROUTE(3,21,13,114)
\r
431 #define SUB_WEEK_ALARM_IN_IROUTE IROUTE(4,21,13,115)
\r
432 #define WEEK_ALARM_ONE_SECOND_IROUTE IROUTE(5,21,13,116)
\r
433 #define WEEK_ALARM_SUB_SECOND_IROUTE IROUTE(6,21,13,117)
\r
434 #define WEEK_ALARM_SYSPWR_PRES_IROUTE IROUTE(7,21,13,118)
\r
435 #define RTC_IROUTE IROUTE(8,21,13,119)
\r
436 #define RTC_ALARM_IROUTE IROUTE(9,21,13,120)
\r
437 #define VBAT_VCI_OVRD_IN_IROUTE IROUTE(10,21,13,121)
\r
438 #define VBAT_VCI_IN0_IROUTE IROUTE(11,21,13,122)
\r
439 #define VBAT_VCI_IN1_IROUTE IROUTE(12,21,13,123)
\r
440 #define VBAT_VCI_IN2_IROUTE IROUTE(13,21,13,124)
\r
441 #define VBAT_VCI_IN3_IROUTE IROUTE(14,21,13,125)
\r
442 #define VBAT_VCI_IN4_IROUTE IROUTE(15,21,13,126)
\r
443 #define VBAT_VCI_IN5_IROUTE IROUTE(16,21,13,127)
\r
444 #define VBAT_VCI_IN6_IROUTE IROUTE(17,21,13,128)
\r
445 #define PS2_0A_WK_IROUTE IROUTE(18,21,13,129)
\r
446 #define PS2_0B_WK_IROUTE IROUTE(19,21,13,130)
\r
447 #define PS2_1A_WK_IROUTE IROUTE(20,21,13,131)
\r
448 #define PS2_1B_WK_IROUTE IROUTE(21,21,13,132)
\r
449 #define PS2_2_WK_IROUTE IROUTE(22,21,13,133)
\r
450 #define ENVMON_IROUTE IROUTE(24,21,13,134)
\r
451 #define KSC_INT_IROUTE IROUTE(25,21,13,135)
\r
455 // GIRQ22 (No Aggregated & No direct source, WAKE ONLY EVENTS)
\r
457 #define LPC_WAKE_ONLY_IROUTE IROUTE(0,22,22,22)
\r
458 #define SMB0_WAKE_ONLY_IROUTE IROUTE(1,22,22,22)
\r
459 #define SMB1_WAKE_ONLY_IROUTE IROUTE(2,22,22,22)
\r
460 #define SMB2_WAKE_ONLY_IROUTE IROUTE(3,22,22,22)
\r
461 #define SMB3_WAKE_ONLY_IROUTE IROUTE(4,22,22,22)
\r
462 #define ESPI_WAKE_ONLY_IROUTE IROUTE(9,22,22,22)
\r
467 #define BTMR0_IROUTE IROUTE(0,23,14,136)
\r
468 #define BTMR1_IROUTE IROUTE(1,23,14,137)
\r
469 #define BTMR2_IROUTE IROUTE(2,23,14,138)
\r
470 #define BTMR3_IROUTE IROUTE(3,23,14,139)
\r
471 #define BTMR4_IROUTE IROUTE(4,23,14,140)
\r
472 #define BTMR5_IROUTE IROUTE(5,23,14,141)
\r
473 #define CTIMER0_IROUTE IROUTE(6,23,14,142)
\r
474 #define CTIMER1_IROUTE IROUTE(7,23,14,143)
\r
475 #define CTIMER2_IROUTE IROUTE(8,23,14,144)
\r
476 #define CTIMER3_IROUTE IROUTE(9,23,14,145)
\r
477 #define CAP_TIMER_IROUTE IROUTE(10,23,14,146)
\r
478 #define CC_TIMER0_IROUTE IROUTE(11,23,14,147)
\r
479 #define CC_TIMER1_IROUTE IROUTE(12,23,14,148)
\r
480 #define CC_TIMER2_IROUTE IROUTE(13,23,14,149)
\r
481 #define CC_TIMER3_IROUTE IROUTE(14,23,14,150)
\r
482 #define CC_TIMER4_IROUTE IROUTE(15,23,14,151)
\r
483 #define CC_TIMER5_IROUTE IROUTE(16,23,14,152)
\r
484 #define CC_TIMER_CMP0_IROUTE IROUTE(17,23,14,153)
\r
485 #define CC_TIMER_CMP1_IROUTE IROUTE(18,23,14,154)
\r
490 #define ESPI_SLAVE_VW00_SRC0_IROUTE IROUTE(0,24,15,15)
\r
491 #define ESPI_SLAVE_VW00_SRC1_IROUTE IROUTE(1,24,15,15)
\r
492 #define ESPI_SLAVE_VW00_SRC2_IROUTE IROUTE(2,24,15,15)
\r
493 #define ESPI_SLAVE_VW00_SRC3_IROUTE IROUTE(3,24,15,15)
\r
494 #define ESPI_SLAVE_VW01_SRC0_IROUTE IROUTE(4,24,15,15)
\r
495 #define ESPI_SLAVE_VW01_SRC1_IROUTE IROUTE(5,24,15,15)
\r
496 #define ESPI_SLAVE_VW01_SRC2_IROUTE IROUTE(6,24,15,15)
\r
497 #define ESPI_SLAVE_VW01_SRC3_IROUTE IROUTE(7,24,15,15)
\r
498 #define ESPI_SLAVE_VW02_SRC0_IROUTE IROUTE(8,24,15,15)
\r
499 #define ESPI_SLAVE_VW02_SRC1_IROUTE IROUTE(9,24,15,15)
\r
500 #define ESPI_SLAVE_VW02_SRC2_IROUTE IROUTE(10,24,15,15)
\r
501 #define ESPI_SLAVE_VW02_SRC3_IROUTE IROUTE(11,24,15,15)
\r
502 #define ESPI_SLAVE_VW03_SRC0_IROUTE IROUTE(12,24,15,15)
\r
503 #define ESPI_SLAVE_VW03_SRC1_IROUTE IROUTE(13,24,15,15)
\r
504 #define ESPI_SLAVE_VW03_SRC2_IROUTE IROUTE(14,24,15,15)
\r
505 #define ESPI_SLAVE_VW03_SRC3_IROUTE IROUTE(15,24,15,15)
\r
506 #define ESPI_SLAVE_VW04_SRC0_IROUTE IROUTE(16,24,15,15)
\r
507 #define ESPI_SLAVE_VW04_SRC1_IROUTE IROUTE(17,24,15,15)
\r
508 #define ESPI_SLAVE_VW04_SRC2_IROUTE IROUTE(18,24,15,15)
\r
509 #define ESPI_SLAVE_VW04_SRC3_IROUTE IROUTE(19,24,15,15)
\r
510 #define ESPI_SLAVE_VW05_SRC0_IROUTE IROUTE(20,24,15,15)
\r
511 #define ESPI_SLAVE_VW05_SRC1_IROUTE IROUTE(21,24,15,15)
\r
512 #define ESPI_SLAVE_VW05_SRC2_IROUTE IROUTE(22,24,15,15)
\r
513 #define ESPI_SLAVE_VW05_SRC3_IROUTE IROUTE(23,24,15,15)
\r
514 #define ESPI_SLAVE_VW06_SRC0_IROUTE IROUTE(24,24,15,15)
\r
515 #define ESPI_SLAVE_VW06_SRC1_IROUTE IROUTE(25,24,15,15)
\r
516 #define ESPI_SLAVE_VW06_SRC2_IROUTE IROUTE(26,24,15,15)
\r
517 #define ESPI_SLAVE_VW06_SRC3_IROUTE IROUTE(27,24,15,15)
\r
523 #define ESPI_SLAVE_VW07_SRC0_IROUTE IROUTE(0,25,15,15)
\r
524 #define ESPI_SLAVE_VW07_SRC1_IROUTE IROUTE(1,25,15,15)
\r
525 #define ESPI_SLAVE_VW07_SRC2_IROUTE IROUTE(2,25,15,15)
\r
526 #define ESPI_SLAVE_VW07_SRC3_IROUTE IROUTE(3,25,15,15)
\r
527 #define ESPI_SLAVE_VW08_SRC0_IROUTE IROUTE(4,25,15,15)
\r
528 #define ESPI_SLAVE_VW08_SRC1_IROUTE IROUTE(5,25,15,15)
\r
529 #define ESPI_SLAVE_VW08_SRC2_IROUTE IROUTE(6,25,15,15)
\r
530 #define ESPI_SLAVE_VW08_SRC3_IROUTE IROUTE(7,25,15,15)
\r
531 #define ESPI_SLAVE_VW09_SRC0_IROUTE IROUTE(8,25,15,15)
\r
532 #define ESPI_SLAVE_VW09_SRC1_IROUTE IROUTE(9,25,15,15)
\r
533 #define ESPI_SLAVE_VW09_SRC2_IROUTE IROUTE(10,25,15,15)
\r
534 #define ESPI_SLAVE_VW09_SRC3_IROUTE IROUTE(11,25,15,15)
\r
535 #define ESPI_SLAVE_VW10_SRC0_IROUTE IROUTE(12,25,15,15)
\r
536 #define ESPI_SLAVE_VW10_SRC1_IROUTE IROUTE(13,25,15,15)
\r
537 #define ESPI_SLAVE_VW10_SRC2_IROUTE IROUTE(14,25,15,15)
\r
538 #define ESPI_SLAVE_VW10_SRC3_IROUTE IROUTE(15,25,15,15)
\r
543 #define GPIO_0240_IROUTE IROUTE(0,26,17,17)
\r
544 #define GPIO_0241_IROUTE IROUTE(1,26,17,17)
\r
545 #define GPIO_0242_IROUTE IROUTE(2,26,17,17)
\r
546 #define GPIO_0243_IROUTE IROUTE(3,26,17,17)
\r
547 #define GPIO_0244_IROUTE IROUTE(4,26,17,17)
\r
548 #define GPIO_0245_IROUTE IROUTE(5,26,17,17)
\r
549 #define GPIO_0246_IROUTE IROUTE(6,26,17,17)
\r
550 #define GPIO_0247_IROUTE IROUTE(7,26,17,17)
\r
552 #define GPIO_0250_IROUTE IROUTE(8,26,17,17)
\r
553 #define GPIO_0251_IROUTE IROUTE(9,26,17,17)
\r
554 #define GPIO_0252_IROUTE IROUTE(10,26,17,17)
\r
555 #define GPIO_0253_IROUTE IROUTE(11,26,17,17)
\r
556 #define GPIO_0254_IROUTE IROUTE(12,26,17,17)
\r
557 #define GPIO_0255_IROUTE IROUTE(13,26,17,17)
\r
558 #define GPIO_0256_IROUTE IROUTE(14,26,17,17)
\r
559 #define GPIO_0257_IROUTE IROUTE(15,26,17,17)
\r
561 #define GPIO_0260_IROUTE IROUTE(16,26,17,17)
\r
562 #define GPIO_0261_IROUTE IROUTE(17,26,17,17)
\r
563 #define GPIO_0262_IROUTE IROUTE(18,26,17,17)
\r
564 #define GPIO_0263_IROUTE IROUTE(19,26,17,17)
\r
565 #define GPIO_0264_IROUTE IROUTE(20,26,17,17)
\r
566 #define GPIO_0265_IROUTE IROUTE(21,26,17,17)
\r
567 #define GPIO_0266_IROUTE IROUTE(22,26,17,17)
\r
568 #define GPIO_0267_IROUTE IROUTE(23,26,17,17)
\r
570 #define GPIO_0270_IROUTE IROUTE(24,26,17,17)
\r
571 #define GPIO_0271_IROUTE IROUTE(25,26,17,17)
\r
572 #define GPIO_0272_IROUTE IROUTE(26,26,17,17)
\r
573 #define GPIO_0273_IROUTE IROUTE(27,26,17,17)
\r
574 #define GPIO_0274_IROUTE IROUTE(28,26,17,17)
\r
575 #define GPIO_0275_IROUTE IROUTE(29,26,17,17)
\r
576 #define GPIO_0276_IROUTE IROUTE(30,26,17,17)
\r
579 // GIRQ08 Bit Positions
\r
580 #define GIRQ08_GPIO_0140_BITPOS (0)
\r
581 #define GIRQ08_GPIO_0141_BITPOS (1)
\r
582 #define GIRQ08_GPIO_0142_BITPOS (2)
\r
583 #define GIRQ08_GPIO_0143_BITPOS (3)
\r
584 #define GIRQ08_GPIO_0144_BITPOS (4)
\r
585 #define GIRQ08_GPIO_0145_BITPOS (5)
\r
586 #define GIRQ08_GPIO_0146_BITPOS (6)
\r
587 #define GIRQ08_GPIO_0147_BITPOS (7)
\r
589 #define GIRQ08_GPIO_0150_BITPOS (8)
\r
590 #define GIRQ08_GPIO_0151_BITPOS (9)
\r
591 #define GIRQ08_GPIO_0152_BITPOS (10)
\r
592 #define GIRQ08_GPIO_0153_BITPOS (11)
\r
593 #define GIRQ08_GPIO_0154_BITPOS (12)
\r
594 #define GIRQ08_GPIO_0155_BITPOS (13)
\r
595 #define GIRQ08_GPIO_0156_BITPOS (14)
\r
596 #define GIRQ08_GPIO_0157_BITPOS (15)
\r
598 #define GIRQ08_GPIO_0160_BITPOS (16)
\r
599 #define GIRQ08_GPIO_0161_BITPOS (17)
\r
600 #define GIRQ08_GPIO_0162_BITPOS (18)
\r
601 #define GIRQ08_GPIO_0163_BITPOS (19)
\r
602 #define GIRQ08_GPIO_0164_BITPOS (20)
\r
603 #define GIRQ08_GPIO_0165_BITPOS (21)
\r
604 #define GIRQ08_GPIO_0166_BITPOS (22)
\r
605 #define GIRQ08_GPIO_0167_BITPOS (23)
\r
607 #define GIRQ08_GPIO_0170_BITPOS (24)
\r
608 #define GIRQ08_GPIO_0171_BITPOS (25)
\r
609 #define GIRQ08_GPIO_0172_BITPOS (26)
\r
610 #define GIRQ08_GPIO_0173_BITPOS (27)
\r
611 #define GIRQ08_GPIO_0174_BITPOS (28)
\r
612 #define GIRQ08_GPIO_0175_BITPOS (29)
\r
613 #define GIRQ08_GPIO_0176_BITPOS (30)
\r
616 #define GIRQ08_MASK (0x7FFFFFFFul)
\r
617 #define GIRQ08_WAKE_CAPABLE_MASK (0x7FFFFFFFul)
\r
620 // GIRQ09 Bit Positions
\r
621 #define GIRQ09_GPIO_0100_BITPOS (0)
\r
622 #define GIRQ09_GPIO_0101_BITPOS (1)
\r
623 #define GIRQ09_GPIO_0102_BITPOS (2)
\r
624 #define GIRQ09_GPIO_0103_BITPOS (3)
\r
625 #define GIRQ09_GPIO_0104_BITPOS (4)
\r
626 #define GIRQ09_GPIO_0105_BITPOS (5)
\r
627 #define GIRQ09_GPIO_0106_BITPOS (6)
\r
628 #define GIRQ09_GPIO_0107_BITPOS (7)
\r
630 #define GIRQ09_GPIO_0110_BITPOS (8)
\r
631 #define GIRQ09_GPIO_0111_BITPOS (9)
\r
632 #define GIRQ09_GPIO_0112_BITPOS (10)
\r
633 #define GIRQ09_GPIO_0113_BITPOS (11)
\r
634 #define GIRQ09_GPIO_0114_BITPOS (12)
\r
635 #define GIRQ09_GPIO_0115_BITPOS (13)
\r
636 #define GIRQ09_GPIO_0116_BITPOS (14)
\r
637 #define GIRQ09_GPIO_0117_BITPOS (15)
\r
639 #define GIRQ09_GPIO_0120_BITPOS (16)
\r
640 #define GIRQ09_GPIO_0121_BITPOS (17)
\r
641 #define GIRQ09_GPIO_0122_BITPOS (18)
\r
642 #define GIRQ09_GPIO_0123_BITPOS (19)
\r
643 #define GIRQ09_GPIO_0124_BITPOS (20)
\r
644 #define GIRQ09_GPIO_0125_BITPOS (21)
\r
645 #define GIRQ09_GPIO_0126_BITPOS (22)
\r
646 #define GIRQ09_GPIO_0127_BITPOS (23)
\r
648 #define GIRQ09_GPIO_0130_BITPOS (24)
\r
649 #define GIRQ09_GPIO_0131_BITPOS (25)
\r
650 #define GIRQ09_GPIO_0132_BITPOS (26)
\r
651 #define GIRQ09_GPIO_0133_BITPOS (27)
\r
652 #define GIRQ09_GPIO_0134_BITPOS (28)
\r
653 #define GIRQ09_GPIO_0135_BITPOS (29)
\r
654 #define GIRQ09_GPIO_0136_BITPOS (30)
\r
657 #define GIRQ09_MASK (0x7FFFFFFFul)
\r
658 #define GIRQ09_WAKE_CAPABLE_MASK (0x7FFFFFFFul)
\r
661 // GIRQ10 Bit Positions
\r
662 #define GIRQ10_GPIO_0040_BITPOS (0)
\r
663 #define GIRQ10_GPIO_0041_BITPOS (1)
\r
664 #define GIRQ10_GPIO_0042_BITPOS (2)
\r
665 #define GIRQ10_GPIO_0043_BITPOS (3)
\r
666 #define GIRQ10_GPIO_0044_BITPOS (4)
\r
667 #define GIRQ10_GPIO_0045_BITPOS (5)
\r
668 #define GIRQ10_GPIO_0046_BITPOS (6)
\r
669 #define GIRQ10_GPIO_0047_BITPOS (7)
\r
671 #define GIRQ10_GPIO_0050_BITPOS (8)
\r
672 #define GIRQ10_GPIO_0051_BITPOS (9)
\r
673 #define GIRQ10_GPIO_0052_BITPOS (10)
\r
674 #define GIRQ10_GPIO_0053_BITPOS (11)
\r
675 #define GIRQ10_GPIO_0054_BITPOS (12)
\r
676 #define GIRQ10_GPIO_0055_BITPOS (13)
\r
677 #define GIRQ10_GPIO_0056_BITPOS (14)
\r
678 #define GIRQ10_GPIO_0057_BITPOS (15)
\r
680 #define GIRQ10_GPIO_0060_BITPOS (16)
\r
681 #define GIRQ10_GPIO_0061_BITPOS (17)
\r
682 #define GIRQ10_GPIO_0062_BITPOS (18)
\r
683 #define GIRQ10_GPIO_0063_BITPOS (19)
\r
684 #define GIRQ10_GPIO_0064_BITPOS (20)
\r
685 #define GIRQ10_GPIO_0065_BITPOS (21)
\r
686 #define GIRQ10_GPIO_0066_BITPOS (22)
\r
687 #define GIRQ10_GPIO_0067_BITPOS (23)
\r
689 #define GIRQ10_GPIO_0070_BITPOS (24)
\r
690 #define GIRQ10_GPIO_0071_BITPOS (25)
\r
691 #define GIRQ10_GPIO_0072_BITPOS (26)
\r
692 #define GIRQ10_GPIO_0073_BITPOS (27)
\r
693 #define GIRQ10_GPIO_0074_BITPOS (28)
\r
694 #define GIRQ10_GPIO_0075_BITPOS (29)
\r
695 #define GIRQ10_GPIO_0076_BITPOS (30)
\r
698 #define GIRQ10_MASK (0x7FFFFFFFul)
\r
699 #define GIRQ10_WAKE_CAPABLE_MASK (0x7FFFFFFFul)
\r
702 // GIRQ11 Bit Positions
\r
703 #define GIRQ11_GPIO_0000_BITPOS (0)
\r
704 #define GIRQ11_GPIO_0001_BITPOS (1)
\r
705 #define GIRQ11_GPIO_0002_BITPOS (2)
\r
706 #define GIRQ11_GPIO_0003_BITPOS (3)
\r
707 #define GIRQ11_GPIO_0004_BITPOS (4)
\r
708 #define GIRQ11_GPIO_0005_BITPOS (5)
\r
709 #define GIRQ11_GPIO_0006_BITPOS (6)
\r
710 #define GIRQ11_GPIO_0007_BITPOS (7)
\r
712 #define GIRQ11_GPIO_0010_BITPOS (8)
\r
713 #define GIRQ11_GPIO_0011_BITPOS (9)
\r
714 #define GIRQ11_GPIO_0012_BITPOS (10)
\r
715 #define GIRQ11_GPIO_0013_BITPOS (11)
\r
716 #define GIRQ11_GPIO_0014_BITPOS (12)
\r
717 #define GIRQ11_GPIO_0015_BITPOS (13)
\r
718 #define GIRQ11_GPIO_0016_BITPOS (14)
\r
719 #define GIRQ11_GPIO_0017_BITPOS (15)
\r
721 #define GIRQ11_GPIO_0020_BITPOS (16)
\r
722 #define GIRQ11_GPIO_0021_BITPOS (17)
\r
723 #define GIRQ11_GPIO_0022_BITPOS (18)
\r
724 #define GIRQ11_GPIO_0023_BITPOS (19)
\r
725 #define GIRQ11_GPIO_0024_BITPOS (20)
\r
726 #define GIRQ11_GPIO_0025_BITPOS (21)
\r
727 #define GIRQ11_GPIO_0026_BITPOS (22)
\r
728 #define GIRQ11_GPIO_0027_BITPOS (23)
\r
730 #define GIRQ11_GPIO_0030_BITPOS (24)
\r
731 #define GIRQ11_GPIO_0031_BITPOS (25)
\r
732 #define GIRQ11_GPIO_0032_BITPOS (26)
\r
733 #define GIRQ11_GPIO_0033_BITPOS (27)
\r
734 #define GIRQ11_GPIO_0034_BITPOS (28)
\r
735 #define GIRQ11_GPIO_0035_BITPOS (29)
\r
736 #define GIRQ11_GPIO_0036_BITPOS (30)
\r
739 #define GIRQ11_MASK (0x7FFFFFFFul)
\r
740 #define GIRQ11_WAKE_CAPABLE_MASK (0x7FFFFFFFul)
\r
743 // GIRQ12 Bit Positions
\r
744 #define GIRQ12_GPIO_0200_BITPOS (0)
\r
745 #define GIRQ12_GPIO_0201_BITPOS (1)
\r
746 #define GIRQ12_GPIO_0202_BITPOS (2)
\r
747 #define GIRQ12_GPIO_0203_BITPOS (3)
\r
748 #define GIRQ12_GPIO_0204_BITPOS (4)
\r
749 #define GIRQ12_GPIO_0205_BITPOS (5)
\r
750 #define GIRQ12_GPIO_0206_BITPOS (6)
\r
751 #define GIRQ12_GPIO_0207_BITPOS (7)
\r
753 #define GIRQ12_GPIO_0210_BITPOS (8)
\r
754 #define GIRQ12_GPIO_0211_BITPOS (9)
\r
755 #define GIRQ12_GPIO_0212_BITPOS (10)
\r
756 #define GIRQ12_GPIO_0213_BITPOS (11)
\r
757 #define GIRQ12_GPIO_0214_BITPOS (12)
\r
758 #define GIRQ12_GPIO_0215_BITPOS (13)
\r
759 #define GIRQ12_GPIO_0216_BITPOS (14)
\r
760 #define GIRQ12_GPIO_0217_BITPOS (15)
\r
762 #define GIRQ12_GPIO_0220_BITPOS (16)
\r
763 #define GIRQ12_GPIO_0221_BITPOS (17)
\r
764 #define GIRQ12_GPIO_0222_BITPOS (18)
\r
765 #define GIRQ12_GPIO_0223_BITPOS (19)
\r
766 #define GIRQ12_GPIO_0224_BITPOS (20)
\r
767 #define GIRQ12_GPIO_0225_BITPOS (21)
\r
768 #define GIRQ12_GPIO_0226_BITPOS (22)
\r
769 #define GIRQ12_GPIO_0227_BITPOS (23)
\r
771 #define GIRQ12_GPIO_0230_BITPOS (24)
\r
772 #define GIRQ12_GPIO_0231_BITPOS (25)
\r
773 #define GIRQ12_GPIO_0232_BITPOS (26)
\r
774 #define GIRQ12_GPIO_0233_BITPOS (27)
\r
775 #define GIRQ12_GPIO_0234_BITPOS (28)
\r
776 #define GIRQ12_GPIO_0235_BITPOS (29)
\r
777 #define GIRQ12_GPIO_0236_BITPOS (30)
\r
780 #define GIRQ12_MASK (0x7FFFFFFFul)
\r
781 #define GIRQ12_WAKE_CAPABLE_MASK (0x7FFFFFFFul)
\r
783 // GIRQ13 Bit Positions
\r
784 #define GIRQ13_SMBUS0_BITPOS (0)
\r
785 #define GIRQ13_SMBUS1_BITPOS (1)
\r
786 #define GIRQ13_SMBUS2_BITPOS (2)
\r
787 #define GIRQ13_SMBUS3_BITPOS (3)
\r
789 #define GIRQ13_MASK (0xFul)
\r
790 #define GIRQ13_WAKE_CAPABLE_MASK (0x0ul)
\r
793 // GIRQ14 Bit Positions
\r
794 #define GIRQ14_DMA0_BITPOS (0)
\r
795 #define GIRQ14_DMA1_BITPOS (1)
\r
796 #define GIRQ14_DMA2_BITPOS (2)
\r
797 #define GIRQ14_DMA3_BITPOS (3)
\r
798 #define GIRQ14_DMA4_BITPOS (4)
\r
799 #define GIRQ14_DMA5_BITPOS (5)
\r
800 #define GIRQ14_DMA6_BITPOS (6)
\r
801 #define GIRQ14_DMA7_BITPOS (7)
\r
802 #define GIRQ14_DMA8_BITPOS (8)
\r
803 #define GIRQ14_DMA9_BITPOS (9)
\r
804 #define GIRQ14_DMA10_BITPOS (10)
\r
805 #define GIRQ14_DMA11_BITPOS (11)
\r
806 #define GIRQ14_DMA12_BITPOS (12)
\r
807 #define GIRQ14_DMA13_BITPOS (13)
\r
809 #define GIRQ14_MASK (0x3FFFul)
\r
810 #define GIRQ14_WAKE_CAPABLE_MASK (0x00000000ul)
\r
814 // GIRQ15 Bit Positions
\r
815 #define GIRQ15_UART0_BITPOS (0)
\r
816 #define GIRQ15_UART1_BITPOS (1)
\r
817 #define GIRQ15_EMI0_BITPOS (2)
\r
818 #define GIRQ15_EMI1_BITPOS (3)
\r
819 #define GIRQ15_EMI2_BITPOS (4)
\r
820 #define GIRQ15_ACPI0_IBF_BITPOS (5)
\r
821 #define GIRQ15_ACPI0_OBF_BITPOS (6)
\r
822 #define GIRQ15_ACPI1_IBF_BITPOS (7)
\r
823 #define GIRQ15_ACPI1_OBF_BITPOS (8)
\r
824 #define GIRQ15_ACPI2_IBF_BITPOS (9)
\r
825 #define GIRQ15_ACPI2_OBF_BITPOS (10)
\r
826 #define GIRQ15_ACPI3_IBF_BITPOS (11)
\r
827 #define GIRQ15_ACPI3_OBF_BITPOS (12)
\r
828 #define GIRQ15_ACPI4_IBF_BITPOS (13)
\r
829 #define GIRQ15_ACPI4_OBF_BITPOS (14)
\r
830 #define GIRQ15_ACPI_PM1CTL_BITPOS (15)
\r
831 #define GIRQ15_ACPI_PM1EN_BITPOS (16)
\r
832 #define GIRQ15_ACPI_PM1STS_BITPOS (17)
\r
833 #define GIRQ15_MF8042_OBF_BITPOS (18)
\r
834 #define GIRQ15_MF8042_IBF_BITPOS (19)
\r
835 #define GIRQ15_MAILBOX_BITPOS (20)
\r
836 #define GIRQ15_PORT80_DBG0_BITPOS (22)
\r
837 #define GIRQ15_PORT80_DBG1_BITPOS (23)
\r
838 #define GIRQ15_TEST_BITPOS (24)
\r
841 #define GIRQ15_MASK (0x1FFFFFFul)
\r
842 #define GIRQ15_WAKE_CAPABLE_MASK (0x000000ul)
\r
845 // GIRQ16 Bit Positions
\r
846 #define PKE_ERROR_BITPOS (0)
\r
847 #define PKE_END_BITPOS (1)
\r
848 #define RNG_BITPOS (2)
\r
849 #define AES_BITPOS (3)
\r
850 #define HASH_BITPOS (4)
\r
853 #define GIRQ16_MASK (0x1Ful)
\r
854 #define GIRQ16_WAKE_CAPABLE_MASK (0x00ul)
\r
857 // GIRQ17 Bit Positions
\r
858 #define GIRQ17_PECI_BITPOS (0)
\r
859 #define GIRQ17_TACH0_BITPOS (1)
\r
860 #define GIRQ17_TACH1_BITPOS (2)
\r
861 #define GIRQ17_TACH2_BITPOS (3)
\r
862 #define GIRQ17_RPM2PWM0_FAIL_BITPOS (4)
\r
863 #define GIRQ17_RPM2PWM0_STALL_BITPOS (5)
\r
864 #define GIRQ17_RPM2PWM1_FAIL_BITPOS (6)
\r
865 #define GIRQ17_RPM2PWM1_STALL_BITPOS (7)
\r
866 #define GIRQ17_ADC_INT0_BITPOS (8)
\r
867 #define GIRQ17_ADC_INT1_BITPOS (9)
\r
868 #define GIRQ17_RC_ID0_BITPOS (10)
\r
869 #define GIRQ17_RC_ID1_BITPOS (11)
\r
870 #define GIRQ17_RC_ID2_BITPOS (12)
\r
871 #define GIRQ17_LED0_BITPOS (13)
\r
872 #define GIRQ17_LED1_BITPOS (14)
\r
873 #define GIRQ17_LED2_BITPOS (15)
\r
874 #define GIRQ17_LED3_BITPOS (16)
\r
875 #define GIRQ17_PHOT_BITPOS (17)
\r
876 #define GIRQ17_PWRGUARD0_BITPOS (18)
\r
877 #define GIRQ17_PWRGUARD1_BITPOS (19)
\r
878 #define GIRQ17_RTOS_SWI0_BITPOS (25)
\r
879 #define GIRQ17_RTOS_SWI1_BITPOS (26)
\r
880 #define GIRQ17_RTOS_SWI2_BITPOS (27)
\r
881 #define GIRQ17_RTOS_SWI3_BITPOS (28)
\r
884 #define GIRQ17_MASK (0x1E0FFFFFul)
\r
885 #define GIRQ17_WAKE_CAPABLE_MASK (0x0ul)
\r
888 // GIRQ18 Bit Positions
\r
889 #define GIRQ18_LPC_ERROR_BITPOS (0)
\r
890 #define GIRQ18_QMSPI_INT_BITPOS (1)
\r
891 #define GIRQ18_SPI0_TX_BITPOS (2)
\r
892 #define GIRQ18_SPI0_RX_BITPOS (3)
\r
893 #define GIRQ18_SPI1_TX_BITPOS (4)
\r
894 #define GIRQ18_SPI1_RX_BITPOS (5)
\r
895 #define GIRQ18_BCM0_BUSY_CLR_BITPOS (6)
\r
896 #define GIRQ18_BCM0_ERROR_BITPOS (7)
\r
897 #define GIRQ18_BCM1_BUSY_CLR_BITPOS (8)
\r
898 #define GIRQ18_BCM1_ERROR_BITPOS (9)
\r
899 #define GIRQ18_PS2_ACT0_BITPOS (10)
\r
900 #define GIRQ18_PS2_ACT1_BITPOS (11)
\r
901 #define GIRQ18_PS2_ACT2_BITPOS (12)
\r
902 #define GIRQ18_EEPROM_BITPOS (13)
\r
905 #define GIRQ18_MASK (0x3FFFul)
\r
906 #define GIRQ18_WAKE_CAPABLE_MASK (0x0ul)
\r
909 // GIRQ19 Bit Positions
\r
910 #define GIRQ19_ESPI_INTR_PC_BITPOS (0)
\r
911 #define GIRQ19_ESPI_INTR_BM1_BITPOS (1)
\r
912 #define GIRQ19_ESPI_INTR_BM2_BITPOS (2)
\r
913 #define GIRQ19_ESPI_INTR_LTR_BITPOS (3)
\r
914 #define GIRQ19_ESPI_INTR_OOB_UP_BITPOS (4)
\r
915 #define GIRQ19_ESPI_INTR_OOB_DN_BITPOS (5)
\r
916 #define GIRQ19_ESPI_INTR_FLASH_BITPOS (6)
\r
917 #define GIRQ19_ESPI_RESET_BITPOS (7)
\r
918 #define GIRQ19_ESPI_VW_ENABLE_BITPOS (8)
\r
921 #define GIRQ19_MASK (0x01FFul)
\r
922 #define GIRQ19_WAKE_CAPABLE_MASK (0x0ul)
\r
925 // GIRQ20 Bit Positions
\r
928 #define GIRQ20_MASK (0x0ul)
\r
929 #define GIRQ20_WAKE_CAPABLE_MASK (0x0ul)
\r
932 // GIRQ21 Bit Positions
\r
933 #define GIRQ21_RTOS_TIMER_BITPOS (0)
\r
934 #define GIRQ21_HTIMER0_BITPOS (1)
\r
935 #define GIRQ21_HTIMER1_BITPOS (2)
\r
936 #define GIRQ21_WEEK_ALRM_INT_BITPOS (3)
\r
937 #define GIRQ21_SUB_WEEK_ALRM_INT_BITPOS (4)
\r
938 #define GIRQ21_ONE_SECOND_BITPOS (5)
\r
939 #define GIRQ21_SUB_SECOND_BITPOS (6)
\r
940 #define GIRQ21_SYSPWR_PRES_BITPOS (7)
\r
941 #define GIRQ21_RTC_BITPOS (8)
\r
942 #define GIRQ21_RTC_ALARM_BITPOS (9)
\r
943 #define GIRQ21_VBAT_VCI_OVRD_IN_BITPOS (10)
\r
944 #define GIRQ21_VBAT_VCI_IN0_BITPOS (11)
\r
945 #define GIRQ21_VBAT_VCI_IN1_BITPOS (12)
\r
946 #define GIRQ21_VBAT_VCI_IN2_BITPOS (13)
\r
947 #define GIRQ21_VBAT_VCI_IN3_BITPOS (14)
\r
948 #define GIRQ21_VBAT_VCI_IN4_BITPOS (15)
\r
949 #define GIRQ21_VBAT_VCI_IN5_BITPOS (16)
\r
950 #define GIRQ21_VBAT_VCI_IN6_BITPOS (17)
\r
951 #define GIRQ21_PS2_0A_WK_BITPOS (18)
\r
952 #define GIRQ21_PS2_0B_WK_BITPOS (19)
\r
953 #define GIRQ21_PS2_1A_WK_BITPOS (20)
\r
954 #define GIRQ21_PS2_1B_WK_BITPOS (21)
\r
955 #define GIRQ21_PS2_2_WK_BITPOS (22)
\r
956 #define GIRQ21_ENVMON_BITPOS (24)
\r
957 #define GIRQ21_KSC_INT_BITPOS (25)
\r
960 #define GIRQ21_MASK (0x37FFFFFul)
\r
961 #define GIRQ21_WAKE_CAPABLE_MASK (0x37FFFFFul)
\r
964 // GIRQ22 Bit Positions
\r
965 #define GIRQ22_LPC_WAKE_ONLY_BITPOS (0)
\r
966 #define GIRQ22_SMB0_WAKE_ONLY_BITPOS (1)
\r
967 #define GIRQ22_SMB1_WAKE_ONLY_BITPOS (2)
\r
968 #define GIRQ22_SMB2_WAKE_ONLY_BITPOS (3)
\r
969 #define GIRQ22_SMB3_WAKE_ONLY_BITPOS (4)
\r
970 #define GIRQ22_ESPI_WAKE_ONLY_BITPOS (9)
\r
972 #define GIRQ22_MASK (0x021Ful)
\r
973 #define GIRQ22_WAKE_CAPABLE_MASK (0x021Ful)
\r
975 // GIRQ23 Bit Positions
\r
976 #define GIRQ23_TMR0_BITPOS (0)
\r
977 #define GIRQ23_TMR1_BITPOS (1)
\r
978 #define GIRQ23_TMR2_BITPOS (2)
\r
979 #define GIRQ23_TMR3_BITPOS (3)
\r
980 #define GIRQ23_TMR4_BITPOS (4)
\r
981 #define GIRQ23_TMR5_BITPOS (5)
\r
982 #define GIRQ23_CTIMER0_BITPOS (6)
\r
983 #define GIRQ23_CTIMER1_BITPOS (7)
\r
984 #define GIRQ23_CTIMER2_BITPOS (8)
\r
985 #define GIRQ23_CTIMER3_BITPOS (9)
\r
986 #define GIRQ23_CAP_TIMER_BITPOS (10)
\r
987 #define GIRQ23_CCTIMER0_BITPOS (11)
\r
988 #define GIRQ23_CCTIMER1_BITPOS (12)
\r
989 #define GIRQ23_CCTIMER2_BITPOS (13)
\r
990 #define GIRQ23_CCTIMER3_BITPOS (14)
\r
991 #define GIRQ23_CCTIMER4_BITPOS (15)
\r
992 #define GIRQ23_CCTIMER5_BITPOS (16)
\r
993 #define GIRQ23_CCTIMER6_BITPOS (17)
\r
994 #define GIRQ23_CCTIMER7_BITPOS (18)
\r
997 #define GIRQ23_MASK (0x07FFFFul)
\r
998 #define GIRQ23_WAKE_CAPABLE_MASK (0x0ul)
\r
1001 // GIRQ24 Bit Positions
\r
1002 #define GIRQ24_ESPI_VW00_SRC0_BITPOS (0)
\r
1003 #define GIRQ24_ESPI_VW00_SRC1_BITPOS (1)
\r
1004 #define GIRQ24_ESPI_VW00_SRC2_BITPOS (2)
\r
1005 #define GIRQ24_ESPI_VW00_SRC3_BITPOS (3)
\r
1006 #define GIRQ24_ESPI_VW01_SRC0_BITPOS (4)
\r
1007 #define GIRQ24_ESPI_VW01_SRC1_BITPOS (5)
\r
1008 #define GIRQ24_ESPI_VW01_SRC2_BITPOS (6)
\r
1009 #define GIRQ24_ESPI_VW01_SRC3_BITPOS (7)
\r
1010 #define GIRQ24_ESPI_VW02_SRC0_BITPOS (8)
\r
1011 #define GIRQ24_ESPI_VW02_SRC1_BITPOS (9)
\r
1012 #define GIRQ24_ESPI_VW02_SRC2_BITPOS (10)
\r
1013 #define GIRQ24_ESPI_VW02_SRC3_BITPOS (11)
\r
1014 #define GIRQ24_ESPI_VW03_SRC0_BITPOS (12)
\r
1015 #define GIRQ24_ESPI_VW03_SRC1_BITPOS (13)
\r
1016 #define GIRQ24_ESPI_VW03_SRC2_BITPOS (14)
\r
1017 #define GIRQ24_ESPI_VW03_SRC3_BITPOS (15)
\r
1018 #define GIRQ24_ESPI_VW04_SRC0_BITPOS (16)
\r
1019 #define GIRQ24_ESPI_VW04_SRC1_BITPOS (17)
\r
1020 #define GIRQ24_ESPI_VW04_SRC2_BITPOS (18)
\r
1021 #define GIRQ24_ESPI_VW04_SRC3_BITPOS (19)
\r
1022 #define GIRQ24_ESPI_VW05_SRC0_BITPOS (20)
\r
1023 #define GIRQ24_ESPI_VW05_SRC1_BITPOS (21)
\r
1024 #define GIRQ24_ESPI_VW05_SRC2_BITPOS (22)
\r
1025 #define GIRQ24_ESPI_VW05_SRC3_BITPOS (23)
\r
1026 #define GIRQ24_ESPI_VW06_SRC0_BITPOS (24)
\r
1027 #define GIRQ24_ESPI_VW06_SRC1_BITPOS (25)
\r
1028 #define GIRQ24_ESPI_VW06_SRC2_BITPOS (26)
\r
1029 #define GIRQ24_ESPI_VW06_SRC3_BITPOS (27)
\r
1032 #define GIRQ24_MASK (0x0FFFFFFFul)
\r
1033 #define GIRQ24_WAKE_CAPABLE_MASK (0x0FFFFFFFul)
\r
1036 // GIRQ25 Bit Positions
\r
1037 #define GIRQ25_ESPI_VW07_SRC0_BITPOS (0)
\r
1038 #define GIRQ25_ESPI_VW07_SRC1_BITPOS (1)
\r
1039 #define GIRQ25_ESPI_VW07_SRC2_BITPOS (2)
\r
1040 #define GIRQ25_ESPI_VW07_SRC3_BITPOS (3)
\r
1041 #define GIRQ25_ESPI_VW08_SRC0_BITPOS (4)
\r
1042 #define GIRQ25_ESPI_VW08_SRC1_BITPOS (5)
\r
1043 #define GIRQ25_ESPI_VW08_SRC2_BITPOS (6)
\r
1044 #define GIRQ25_ESPI_VW08_SRC3_BITPOS (7)
\r
1045 #define GIRQ25_ESPI_VW09_SRC0_BITPOS (8)
\r
1046 #define GIRQ25_ESPI_VW09_SRC1_BITPOS (9)
\r
1047 #define GIRQ25_ESPI_VW09_SRC2_BITPOS (10)
\r
1048 #define GIRQ25_ESPI_VW09_SRC3_BITPOS (11)
\r
1049 #define GIRQ25_ESPI_VW10_SRC0_BITPOS (12)
\r
1050 #define GIRQ25_ESPI_VW10_SRC1_BITPOS (13)
\r
1051 #define GIRQ25_ESPI_VW10_SRC2_BITPOS (14)
\r
1052 #define GIRQ25_ESPI_VW10_SRC3_BITPOS (15)
\r
1055 #define GIRQ25_MASK (0x0FFFFul)
\r
1056 #define GIRQ25_WAKE_CAPABLE_MASK (0x0FFFFul)
\r
1059 // GIRQ26 bit positions
\r
1060 #define GIRQ26_GPIO240_BITPOS (0)
\r
1061 #define GIRQ26_GPIO241_BITPOS (1)
\r
1062 #define GIRQ26_GPIO242_BITPOS (2)
\r
1063 #define GIRQ26_GPIO243_BITPOS (3)
\r
1064 #define GIRQ26_GPIO244_BITPOS (4)
\r
1065 #define GIRQ26_GPIO245_BITPOS (5)
\r
1066 #define GIRQ26_GPIO246_BITPOS (6)
\r
1067 #define GIRQ26_GPIO247_BITPOS (7)
\r
1069 #define GIRQ26_GPIO250_BITPOS (8)
\r
1070 #define GIRQ26_GPIO251_BITPOS (9)
\r
1071 #define GIRQ26_GPIO252_BITPOS (10)
\r
1072 #define GIRQ26_GPIO253_BITPOS (11)
\r
1073 #define GIRQ26_GPIO254_BITPOS (12)
\r
1074 #define GIRQ26_GPIO255_BITPOS (13)
\r
1075 #define GIRQ26_GPIO256_BITPOS (14)
\r
1076 #define GIRQ26_GPIO257_BITPOS (15)
\r
1078 #define GIRQ26_GPIO260_BITPOS (16)
\r
1079 #define GIRQ26_GPIO261_BITPOS (17)
\r
1080 #define GIRQ26_GPIO262_BITPOS (18)
\r
1081 #define GIRQ26_GPIO263_BITPOS (19)
\r
1082 #define GIRQ26_GPIO264_BITPOS (20)
\r
1083 #define GIRQ26_GPIO265_BITPOS (21)
\r
1084 #define GIRQ26_GPIO266_BITPOS (22)
\r
1085 #define GIRQ26_GPIO267_BITPOS (23)
\r
1087 #define GIRQ26_GPIO270_BITPOS (24)
\r
1088 #define GIRQ26_GPIO271_BITPOS (25)
\r
1089 #define GIRQ26_GPIO272_BITPOS (26)
\r
1090 #define GIRQ26_GPIO273_BITPOS (27)
\r
1091 #define GIRQ26_GPIO274_BITPOS (28)
\r
1092 #define GIRQ26_GPIO275_BITPOS (29)
\r
1093 #define GIRQ26_GPIO276_BITPOS (30)
\r
1095 #define GIRQ26_MASK (0x7FFFFFFFul)
\r
1096 #define GIRQ26_WAKE_CAPABLE_MASK (0x7FFFFFFFul)
\r
1098 /* ------------------------------------------------------------------------------- */
\r
1099 /* NVIC,ECIA Routing Policy for Direct Mode */
\r
1100 /* ------------------------------------------------------------------------------- */
\r
1101 /* In Direct Mode, some interrupts could be configured to be used as aggregated.
\r
1103 * 1. Always set ECS Interrupt Direct enable bit.
\r
1104 * 2. If GIRQn aggregated set Block Enable bit.
\r
1105 * 3. If GIRQn direct then clear Block Enable bit and enable individual NVIC inputs.
\r
1106 * Switching issues:
\r
1107 * Aggregate enable/disable requires set/clear single GIRQn bit in GIRQ Block En/Clr registers.
\r
1108 * Also requires set/clear of individual NVIC Enables.
\r
1110 * Note: interrupt_is_girq_direct() internal function uses this policy to detect
\r
1111 * if any interrupt is configured as direct or aggregated
\r
1114 /** Initialize EC Interrupt Aggregator
\r
1115 * @param mode 1 - Direct Map mode, 0 - Fully Aggregated Mode
\r
1116 * @param girq_bitmask - BitMask of GIRQ to be configured as aggregated
\r
1117 * This parameter is only applicable in direct mode.
\r
1118 * @note All GPIO's and wake capable sources are always
\r
1119 * aggregated! GPIO's interrupts will still work in direct mode.
\r
1120 * Block wakes are not be routed to the processor in direct
\r
1122 * Note2: This function disables and enables global interrupt
\r
1124 void interrupt_init(uint8_t mode, uint32_t girq_bitmask);
\r
1126 /** Set interrupt routing mode to aggregated or direct.
\r
1127 * @param mode 1 = Direct (except GPIO & wake), 0 = All Aggregated
\r
1128 * @note In direct mode, one could enable certain GIRQs as aggregated using
\r
1129 * p_interrupt_ecia_block_enable_set function
\r
1131 void interrupt_mode_set(uint8_t mode);
\r
1133 /** Clears all individual interrupts Enables and Source in ECIA,
\r
1134 * and Clears all NVIC external enables and pending bits
\r
1136 void interrupt_reset(void);
\r
1138 /** Enables interrupt for a device
\r
1139 * @param dev_iroute - source IROUTING information
\r
1140 * @note This function disables and enables global interrupt
\r
1142 void interrupt_device_enable(uint32_t dev_iroute);
\r
1144 /** Disables interrupt for a device
\r
1145 * @param dev_iroute - source IROUTING information
\r
1146 * @note This function disables and enables global interrupt
\r
1148 void interrupt_device_disable(uint32_t dev_iroute);
\r
1150 /* ------------------------------------------------------------------------------- */
\r
1151 /* ECIA APIs using device IROUTE() as input */
\r
1152 /* ------------------------------------------------------------------------------- */
\r
1154 /** Clear Source in the ECIA for the device
\r
1155 * @param devi - device IROUTING value
\r
1157 void interrupt_device_ecia_source_clear(const uint32_t dev_iroute);
\r
1159 /** Get the Source bit in the ECIA for the device
\r
1160 * @param devi - device IROUTING value
\r
1161 * @return 0 if source bit not set; else non-zero value
\r
1163 uint32_t interrupt_device_ecia_source_get(const uint32_t dev_iroute);
\r
1165 /** Get the Result bit in the ECIA for the device
\r
1166 * @param devi - device IROUTING value
\r
1167 * @return 0 if result bit not set; else non-zero value
\r
1169 uint32_t interrupt_device_ecia_result_get(const uint32_t dev_iroute);
\r
1171 /* ------------------------------------------------------------------------------- */
\r
1172 /* NVIC APIs using device IROUTE() as input */
\r
1173 /* ------------------------------------------------------------------------------- */
\r
1174 /* Note that if the device interrupt is aggregated, then these APIs would affect the
\r
1175 * NVIC corresponding to the aggregated GIRQ
\r
1178 /** Enable/Disable the NVIC (in the NVIC controller) for the device
\r
1179 * @param dev_iroute : source IROUTING information (encoded in a uint32_t)
\r
1180 * @param en_flag : 1 = Enable the NVIC IRQ, 0 = Disable the NVIC IRQ
\r
1181 * @note Recommended to use interrupt_device_enable, interrupt_device_disable
\r
1182 * to enable/disable interrupts for the device, since those APIs configure ECIA as well
\r
1184 void interrupt_device_nvic_enable(uint32_t dev_iroute, uint8_t en_flag);
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1186 /** Set NVIC priority for specified peripheral interrupt source
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1187 * @param dev_iroute - source IROUTING information (encoded in a uint32_t)
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1188 * @param nvic_pri - NVIC Priority
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1189 * @note 1. If ECIA is in aggregated mode, the priority affects all interrupt
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1190 * sources in the GIRQ.
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1191 * 2. This function disables and enables global interrupt
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1193 void interrupt_device_nvic_priority_set(const uint32_t dev_iroute, const uint8_t nvic_pri);
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1195 /** Return NVIC priority for interrupt source
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1196 * @param dev_iroute - source IROUTING information
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1197 * @return uint32_t NVIC priority
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1199 uint32_t interrupt_device_nvic_priority_get(const uint32_t dev_iroute);
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1201 /** Return NVIC pending for interrupt source
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1202 * @param dev_iroute - source IROUTING information
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1203 * @return uint8_t 0(not pending), 1 (pending in NVIC)
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1206 uint8_t interrupt_device_nvic_pending_get(const uint32_t dev_iroute);
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1208 /** Set NVIC pending for interrupt source
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1209 * @param dev_iroute - source IROUTING information
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1211 void interrupt_device_nvic_pending_set(const uint32_t dev_iroute);
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1213 /** Clears NVIC pending for interrupt source
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1214 * @param dev_iroute - source IROUTING information
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1215 * @return uint8_t 0(not pending), 1 (pending in NVIC) - before clear
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1216 * @note This function disables and enables global interrupt
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1218 uint8_t interrupt_device_nvic_pending_clear(const uint32_t dev_iroute);
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1220 /* ------------------------------------------------------------------------------- */
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1221 /* Peripheral Functions - Operations on GIRQ Block Enable Set, Enable Clear *
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1222 * and Status Register */
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1223 /* ------------------------------------------------------------------------------- */
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1225 /** Enable specified GIRQ in ECIA block
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1226 * @param girq_id - enum MEC_GIRQ_IDS
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1228 void p_interrupt_ecia_block_enable_set(uint8_t girq_id);
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1230 /** Enable GIRQs in ECIA Block
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1231 * @param girq_bitmask - Bitmask of GIRQs to be enabled in ECIA Block
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1233 void p_interrupt_ecia_block_enable_bitmask_set(uint32_t girq_bitmask);
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1235 /** Check if specified GIRQ block enabled or not
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1236 * @param girq_id - enum MEC_GIRQ_IDS
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1237 * @return retVal - 1 if the particular GIRQ block enabled, else 0
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1239 uint8_t p_interrupt_ecia_block_enable_get(uint8_t girq_id);
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1241 /** Set all GIRQ block enables */
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1242 void p_interrupt_ecia_block_enable_all_set(void);
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1244 /** Clear specified GIRQ in ECIA Block
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1245 * @param girq_id - enum MEC_GIRQ_IDS
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1247 void p_interrupt_ecia_block_enable_clr(uint8_t girq_id);
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1249 /** Clear GIRQs in ECIA Block
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1250 * @param girq_bitmask - Bitmask of GIRQs to be cleared in ECIA Block
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1252 void p_interrupt_ecia_block_enable_bitmask_clr(uint32_t girq_bitmask);
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1254 /** p_interrupt_ecia_block_enable_all_clr - Clears all GIRQ block enables */
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1255 void p_interrupt_ecia_block_enable_all_clr(void);
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1257 /** Get status of GIRQ in ECIA Block
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1258 * @param girq_id - enum MEC_GIRQ_IDS
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1259 * @return 0 if status bit not set; else non-zero value
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1261 uint32_t p_interrupt_ecia_block_irq_status_get(uint8_t girq_id);
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1263 /** Reads the Block IRQ Vector Register
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1264 * @return 32-bit value
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1266 uint32_t p_interrupt_ecia_block_irq_all_status_get(void);
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1268 /* ---------------------------------------------------------------------------- */
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1269 /* Peripheral Functions - Operations on GIRQx Source, Enable, Result *
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1270 * and Enable Registers */
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1271 /* ---------------------------------------------------------------------------- */
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1273 /** Clear specified interrupt source bit in GIRQx
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1274 * @param girq_id - enum MEC_GIRQ_IDS
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1275 * @param bitnum -[0, 31]
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1277 void p_interrupt_ecia_girq_source_clr(int16_t girq_id, uint8_t bitnum);
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1279 /** Read the specified interrupt source bit in GIRQx
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1280 * @param girq_id - enum MEC_GIRQ_IDS
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1281 * @param bitnum -[0, 31]
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1282 * @return 0 if source bit not set; else non-zero value
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1284 uint32_t p_interrupt_ecia_girq_source_get(int16_t girq_id, uint8_t bitnum);
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1286 /** Enable the specified interrupt in GIRQx
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1287 * girq_id - enum MEC_GIRQ_IDS
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1288 * bitnum = [0, 31]
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1290 void p_interrupt_ecia_girq_enable_set(uint16_t girq_id, uint8_t bitnum);
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1292 /** Disable the specified interrupt in GIRQx
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1293 * girq_id - enum MEC_GIRQ_IDS
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1294 * bitnum = [0, 31]
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1296 void p_interrupt_ecia_girq_enable_clr(uint16_t girq_id, uint8_t bitnum);
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1298 /** Read the status of the specified interrupt in GIRQx
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1299 * girq_id - enum MEC_GIRQ_IDS
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1300 * bitnum = [0, 31]
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1301 * @return 0 if enable bit not set; else non-zero value
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1303 uint32_t p_interrupt_ecia_girq_enable_get(uint16_t girq_id, uint8_t bitnum);
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1305 /** Read the result bit of the interrupt in GIRQx
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1306 * @param girq_id - enum MEC_GIRQ_IDS
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1307 * @param bitnum -[0, 31]
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1308 * @return 0 if enable bit not set; else non-zero value
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1310 uint32_t p_interrupt_ecia_girq_result_get(int16_t girq_id, uint8_t bitnum);
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1312 /* ------------------------------------------------------------------------------- */
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1313 /* Peripheral Function - Operations on all GIRQs */
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1314 /* ------------------------------------------------------------------------------- */
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1316 /** Clear all aggregator GIRQn status registers */
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1317 void p_interrupt_ecia_girqs_source_reset(void);
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1319 /** Clear all aggregator GIRQn enables */
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1320 void p_interrupt_ecia_girqs_enable_reset(void);
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1322 /* ------------------------------------------------------------------------------- */
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1323 /* Peripheral Function - Function to set interrupt control */
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1324 /* ------------------------------------------------------------------------------- */
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1326 /** Set interrupt control
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1327 * @param nvic_en_flag : 0 = Alternate NVIC disabled, 1 = Alternate NVIC enabled
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1329 void p_interrupt_control_set(uint8_t nvic_en_flag);
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1331 /** Read interrupt control
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1332 * @return uint8_t - 0 = Alternate NVIC disabled, 1 = Alternate NVIC enabled
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1334 uint8_t p_interrupt_control_get(void);
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1336 /* ------------------------------------------------------------------------------- */
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1337 /* Peripheral Functions - NVIC */
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1338 /* ------------------------------------------------------------------------------- */
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1340 /** Enable/Disable the NVIC IRQ in the NVIC interrupt controller
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1341 * @param nvic_num : NVIC number (see enum IRQn_Type)
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1342 * @param en_flag : 1 = Enable the NVIC IRQ, 0 = Disable the NVIC IRQ
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1343 * @note Application should perform this operation
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1345 void p_interrupt_nvic_enable(IRQn_Type nvic_num, uint8_t en_flag);
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1347 /** ecia_nvic_clr_en - Clear all NVIC external enables */
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1348 void p_interrupt_nvic_extEnables_clr(void);
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1350 /** Clear all NVIC external enables and pending bits */
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1351 void p_interrupt_nvic_enpend_clr(void);
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1353 /** Set NVIC external priorities to POR value */
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1354 void p_interrupt_nvic_priorities_default_set(void);
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1356 /** Set NVIC external priorities to specified priority (0 - 7)
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1357 * @param zero-based 3-bit priority value: 0=highest, 7=lowest.
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1358 * @note NVIC highest priority is the value 0, lowest is all 1's.
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1359 * Each external interrupt has an 8-bit register and the priority
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1360 * is left justified in the registers. MECxxx implements 8 priority
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1361 * levels or bits [7:5] in the register. Lowest priority = 0xE0
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1363 void p_interrupt_nvic_priorities_set(uint8_t new_pri);
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1365 #endif // #ifndef _INTERRUPT_H
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1366 /* end interrupt.h */
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projects / freertos / blob