git.sur5r.net Git - freertos/blob - FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_GCC_Dave/GPIO.h

   1 #ifndef __GPIO_H__\r
   2 #define __GPIO_H__\r
   3 \r
   4 /* Generated automatically for XMC4500_QFP144 on: Mon Jan 14 10:10:13 2013*/\r
   5 \r
   6 #include <XMC4500.h>\r
   7 \r
   8 #define INPUT           0x00U\r
   9 #define INPUT_PD        0x08U\r
  10 #define INPUT_PU        0x10U\r
  11 #define INPUT_PPS       0x18U\r
  12 #define INPUT_INV       0x20U\r
  13 #define INPUT_INV_PD    0x28U\r
  14 #define INPUT_INV_PU    0x30U\r
  15 #define INPUT_INV_PPS   0x38U\r
  16 #define OUTPUT_PP_GP    0x80U\r
  17 #define OUTPUT_PP_AF1   0x88U\r
  18 #define OUTPUT_PP_AF2   0x90U\r
  19 #define OUTPUT_PP_AF3   0x98U\r
  20 #define OUTPUT_PP_AF4   0xA0U\r
  21 #define OUTPUT_OD_GP    0xC0U\r
  22 #define OUTPUT_OD_AF1   0xC8U\r
  23 #define OUTPUT_OD_AF2   0xD0U\r
  24 #define OUTPUT_OD_AF3   0xD8U\r
  25 #define OUTPUT_OD_AF4   0XE0U\r
  26 \r
  27 #define WEAK            0x7UL\r
  28 #define MEDIUM          0x4UL\r
  29 #define STRONG          0x2UL\r
  30 #define VERYSTRONG      0x0UL\r
  31 \r
  32 #define SOFTWARE        0x0UL\r
  33 #define HW0             0x1UL\r
  34 #define HW1             0x2UL\r
  35 \r
  36 __STATIC_INLINE void P0_0_set_mode(uint8_t mode){\r
  37     PORT0->IOCR0 &= ~0x000000f8UL;\r
  38     PORT0->IOCR0 |= mode << 0;\r
  39 }\r
  40 \r
  41 __STATIC_INLINE void P0_0_set_driver_strength(uint8_t strength){\r
  42     PORT0->PDR0 &= ~0x00000007UL;\r
  43     PORT0->PDR0 |= strength << 0;\r
  44 }\r
  45 \r
  46 __STATIC_INLINE void P0_0_set_hwsel(uint32_t config){\r
  47     PORT0->HWSEL &= ~0x00000003UL;\r
  48     PORT0->HWSEL |= config << 0;\r
  49 }\r
  50 \r
  51 __STATIC_INLINE void P0_0_set(void){\r
  52     PORT0->OMR = 0x00000001UL;\r
  53 }\r
  54 \r
  55 __STATIC_INLINE void P0_0_reset(void){\r
  56     PORT0->OMR = 0x00010000UL;\r
  57 }\r
  58 \r
  59 __STATIC_INLINE void P0_0_toggle(void){\r
  60     PORT0->OMR = 0x00010001UL;\r
  61 }\r
  62 \r
  63 __STATIC_INLINE uint32_t P0_0_read(void){\r
  64     return(PORT0->IN & 0x00000001UL);\r
  65 }\r
  66 \r
  67 __STATIC_INLINE void P0_1_set_mode(uint8_t mode){\r
  68     PORT0->IOCR0 &= ~0x0000f800UL;\r
  69     PORT0->IOCR0 |= mode << 8;\r
  70 }\r
  71 \r
  72 __STATIC_INLINE void P0_1_set_driver_strength(uint8_t strength){\r
  73     PORT0->PDR0 &= ~0x00000070UL;\r
  74     PORT0->PDR0 |= strength << 4;\r
  75 }\r
  76 \r
  77 __STATIC_INLINE void P0_1_set_hwsel(uint32_t config){\r
  78     PORT0->HWSEL &= ~0x0000000cUL;\r
  79     PORT0->HWSEL |= config << 2;\r
  80 }\r
  81 \r
  82 __STATIC_INLINE void P0_1_set(void){\r
  83     PORT0->OMR = 0x00000002UL;\r
  84 }\r
  85 \r
  86 __STATIC_INLINE void P0_1_reset(void){\r
  87     PORT0->OMR = 0x00020000UL;\r
  88 }\r
  89 \r
  90 __STATIC_INLINE void P0_1_toggle(void){\r
  91     PORT0->OMR = 0x00020002UL;\r
  92 }\r
  93 \r
  94 __STATIC_INLINE uint32_t P0_1_read(void){\r
  95     return(PORT0->IN & 0x00000002UL);\r
  96 }\r
  97 \r
  98 __STATIC_INLINE void P0_2_set_mode(uint8_t mode){\r
  99     PORT0->IOCR0 &= ~0x00f80000UL;\r
 100     PORT0->IOCR0 |= mode << 16;\r
 101 }\r
 102 \r
 103 __STATIC_INLINE void P0_2_set_driver_strength(uint8_t strength){\r
 104     PORT0->PDR0 &= ~0x00000700UL;\r
 105     PORT0->PDR0 |= strength << 8;\r
 106 }\r
 107 \r
 108 __STATIC_INLINE void P0_2_set_hwsel(uint32_t config){\r
 109     PORT0->HWSEL &= ~0x00000030UL;\r
 110     PORT0->HWSEL |= config << 4;\r
 111 }\r
 112 \r
 113 __STATIC_INLINE void P0_2_set(void){\r
 114     PORT0->OMR = 0x00000004UL;\r
 115 }\r
 116 \r
 117 __STATIC_INLINE void P0_2_reset(void){\r
 118     PORT0->OMR = 0x00040000UL;\r
 119 }\r
 120 \r
 121 __STATIC_INLINE void P0_2_toggle(void){\r
 122     PORT0->OMR = 0x00040004UL;\r
 123 }\r
 124 \r
 125 __STATIC_INLINE uint32_t P0_2_read(void){\r
 126     return(PORT0->IN & 0x00000004UL);\r
 127 }\r
 128 \r
 129 __STATIC_INLINE void P0_3_set_mode(uint8_t mode){\r
 130     PORT0->IOCR0 &= ~0xf8000000UL;\r
 131     PORT0->IOCR0 |= mode << 24;\r
 132 }\r
 133 \r
 134 __STATIC_INLINE void P0_3_set_driver_strength(uint8_t strength){\r
 135     PORT0->PDR0 &= ~0x00007000UL;\r
 136     PORT0->PDR0 |= strength << 12;\r
 137 }\r
 138 \r
 139 __STATIC_INLINE void P0_3_set_hwsel(uint32_t config){\r
 140     PORT0->HWSEL &= ~0x000000c0UL;\r
 141     PORT0->HWSEL |= config << 6;\r
 142 }\r
 143 \r
 144 __STATIC_INLINE void P0_3_set(void){\r
 145     PORT0->OMR = 0x00000008UL;\r
 146 }\r
 147 \r
 148 __STATIC_INLINE void P0_3_reset(void){\r
 149     PORT0->OMR = 0x00080000UL;\r
 150 }\r
 151 \r
 152 __STATIC_INLINE void P0_3_toggle(void){\r
 153     PORT0->OMR = 0x00080008UL;\r
 154 }\r
 155 \r
 156 __STATIC_INLINE uint32_t P0_3_read(void){\r
 157     return(PORT0->IN & 0x00000008UL);\r
 158 }\r
 159 \r
 160 __STATIC_INLINE void P0_4_set_mode(uint8_t mode){\r
 161     PORT0->IOCR4 &= ~0x000000f8UL;\r
 162     PORT0->IOCR4 |= mode << 0;\r
 163 }\r
 164 \r
 165 __STATIC_INLINE void P0_4_set_driver_strength(uint8_t strength){\r
 166     PORT0->PDR0 &= ~0x00070000UL;\r
 167     PORT0->PDR0 |= strength << 16;\r
 168 }\r
 169 \r
 170 __STATIC_INLINE void P0_4_set_hwsel(uint32_t config){\r
 171     PORT0->HWSEL &= ~0x00000300UL;\r
 172     PORT0->HWSEL |= config << 8;\r
 173 }\r
 174 \r
 175 __STATIC_INLINE void P0_4_set(void){\r
 176     PORT0->OMR = 0x00000010UL;\r
 177 }\r
 178 \r
 179 __STATIC_INLINE void P0_4_reset(void){\r
 180     PORT0->OMR = 0x00100000UL;\r
 181 }\r
 182 \r
 183 __STATIC_INLINE void P0_4_toggle(void){\r
 184     PORT0->OMR = 0x00100010UL;\r
 185 }\r
 186 \r
 187 __STATIC_INLINE uint32_t P0_4_read(void){\r
 188     return(PORT0->IN & 0x00000010UL);\r
 189 }\r
 190 \r
 191 __STATIC_INLINE void P0_5_set_mode(uint8_t mode){\r
 192     PORT0->IOCR4 &= ~0x0000f800UL;\r
 193     PORT0->IOCR4 |= mode << 8;\r
 194 }\r
 195 \r
 196 __STATIC_INLINE void P0_5_set_driver_strength(uint8_t strength){\r
 197     PORT0->PDR0 &= ~0x00700000UL;\r
 198     PORT0->PDR0 |= strength << 20;\r
 199 }\r
 200 \r
 201 __STATIC_INLINE void P0_5_set_hwsel(uint32_t config){\r
 202     PORT0->HWSEL &= ~0x00000c00UL;\r
 203     PORT0->HWSEL |= config << 10;\r
 204 }\r
 205 \r
 206 __STATIC_INLINE void P0_5_set(void){\r
 207     PORT0->OMR = 0x00000020UL;\r
 208 }\r
 209 \r
 210 __STATIC_INLINE void P0_5_reset(void){\r
 211     PORT0->OMR = 0x00200000UL;\r
 212 }\r
 213 \r
 214 __STATIC_INLINE void P0_5_toggle(void){\r
 215     PORT0->OMR = 0x00200020UL;\r
 216 }\r
 217 \r
 218 __STATIC_INLINE uint32_t P0_5_read(void){\r
 219     return(PORT0->IN & 0x00000020UL);\r
 220 }\r
 221 \r
 222 __STATIC_INLINE void P0_6_set_mode(uint8_t mode){\r
 223     PORT0->IOCR4 &= ~0x00f80000UL;\r
 224     PORT0->IOCR4 |= mode << 16;\r
 225 }\r
 226 \r
 227 __STATIC_INLINE void P0_6_set_driver_strength(uint8_t strength){\r
 228     PORT0->PDR0 &= ~0x07000000UL;\r
 229     PORT0->PDR0 |= strength << 24;\r
 230 }\r
 231 \r
 232 __STATIC_INLINE void P0_6_set_hwsel(uint32_t config){\r
 233     PORT0->HWSEL &= ~0x00003000UL;\r
 234     PORT0->HWSEL |= config << 12;\r
 235 }\r
 236 \r
 237 __STATIC_INLINE void P0_6_set(void){\r
 238     PORT0->OMR = 0x00000040UL;\r
 239 }\r
 240 \r
 241 __STATIC_INLINE void P0_6_reset(void){\r
 242     PORT0->OMR = 0x00400000UL;\r
 243 }\r
 244 \r
 245 __STATIC_INLINE void P0_6_toggle(void){\r
 246     PORT0->OMR = 0x00400040UL;\r
 247 }\r
 248 \r
 249 __STATIC_INLINE uint32_t P0_6_read(void){\r
 250     return(PORT0->IN & 0x00000040UL);\r
 251 }\r
 252 \r
 253 __STATIC_INLINE void P0_7_set_mode(uint8_t mode){\r
 254     PORT0->IOCR4 &= ~0xf8000000UL;\r
 255     PORT0->IOCR4 |= mode << 24;\r
 256 }\r
 257 \r
 258 __STATIC_INLINE void P0_7_set_driver_strength(uint8_t strength){\r
 259     PORT0->PDR0 &= ~0x70000000UL;\r
 260     PORT0->PDR0 |= strength << 28;\r
 261 }\r
 262 \r
 263 __STATIC_INLINE void P0_7_set_hwsel(uint32_t config){\r
 264     PORT0->HWSEL &= ~0x0000c000UL;\r
 265     PORT0->HWSEL |= config << 14;\r
 266 }\r
 267 \r
 268 __STATIC_INLINE void P0_7_set(void){\r
 269     PORT0->OMR = 0x00000080UL;\r
 270 }\r
 271 \r
 272 __STATIC_INLINE void P0_7_reset(void){\r
 273     PORT0->OMR = 0x00800000UL;\r
 274 }\r
 275 \r
 276 __STATIC_INLINE void P0_7_toggle(void){\r
 277     PORT0->OMR = 0x00800080UL;\r
 278 }\r
 279 \r
 280 __STATIC_INLINE uint32_t P0_7_read(void){\r
 281     return(PORT0->IN & 0x00000080UL);\r
 282 }\r
 283 \r
 284 __STATIC_INLINE void P0_8_set_mode(uint8_t mode){\r
 285     PORT0->IOCR8 &= ~0x000000f8UL;\r
 286     PORT0->IOCR8 |= mode << 0;\r
 287 }\r
 288 \r
 289 __STATIC_INLINE void P0_8_set_driver_strength(uint8_t strength){\r
 290     PORT0->PDR1 &= ~0x00000007UL;\r
 291     PORT0->PDR1 |= strength << 0;\r
 292 }\r
 293 \r
 294 __STATIC_INLINE void P0_8_set_hwsel(uint32_t config){\r
 295     PORT0->HWSEL &= ~0x00030000UL;\r
 296     PORT0->HWSEL |= config << 16;\r
 297 }\r
 298 \r
 299 __STATIC_INLINE void P0_8_set(void){\r
 300     PORT0->OMR = 0x00000100UL;\r
 301 }\r
 302 \r
 303 __STATIC_INLINE void P0_8_reset(void){\r
 304     PORT0->OMR = 0x01000000UL;\r
 305 }\r
 306 \r
 307 __STATIC_INLINE void P0_8_toggle(void){\r
 308     PORT0->OMR = 0x01000100UL;\r
 309 }\r
 310 \r
 311 __STATIC_INLINE uint32_t P0_8_read(void){\r
 312     return(PORT0->IN & 0x00000100UL);\r
 313 }\r
 314 \r
 315 __STATIC_INLINE void P0_9_set_mode(uint8_t mode){\r
 316     PORT0->IOCR8 &= ~0x0000f800UL;\r
 317     PORT0->IOCR8 |= mode << 8;\r
 318 }\r
 319 \r
 320 __STATIC_INLINE void P0_9_set_driver_strength(uint8_t strength){\r
 321     PORT0->PDR1 &= ~0x00000070UL;\r
 322     PORT0->PDR1 |= strength << 4;\r
 323 }\r
 324 \r
 325 __STATIC_INLINE void P0_9_set_hwsel(uint32_t config){\r
 326     PORT0->HWSEL &= ~0x000c0000UL;\r
 327     PORT0->HWSEL |= config << 18;\r
 328 }\r
 329 \r
 330 __STATIC_INLINE void P0_9_set(void){\r
 331     PORT0->OMR = 0x00000200UL;\r
 332 }\r
 333 \r
 334 __STATIC_INLINE void P0_9_reset(void){\r
 335     PORT0->OMR = 0x02000000UL;\r
 336 }\r
 337 \r
 338 __STATIC_INLINE void P0_9_toggle(void){\r
 339     PORT0->OMR = 0x02000200UL;\r
 340 }\r
 341 \r
 342 __STATIC_INLINE uint32_t P0_9_read(void){\r
 343     return(PORT0->IN & 0x00000200UL);\r
 344 }\r
 345 \r
 346 __STATIC_INLINE void P0_10_set_mode(uint8_t mode){\r
 347     PORT0->IOCR8 &= ~0x00f80000UL;\r
 348     PORT0->IOCR8 |= mode << 16;\r
 349 }\r
 350 \r
 351 __STATIC_INLINE void P0_10_set_driver_strength(uint8_t strength){\r
 352     PORT0->PDR1 &= ~0x00000700UL;\r
 353     PORT0->PDR1 |= strength << 8;\r
 354 }\r
 355 \r
 356 __STATIC_INLINE void P0_10_set_hwsel(uint32_t config){\r
 357     PORT0->HWSEL &= ~0x00300000UL;\r
 358     PORT0->HWSEL |= config << 20;\r
 359 }\r
 360 \r
 361 __STATIC_INLINE void P0_10_set(void){\r
 362     PORT0->OMR = 0x00000400UL;\r
 363 }\r
 364 \r
 365 __STATIC_INLINE void P0_10_reset(void){\r
 366     PORT0->OMR = 0x04000000UL;\r
 367 }\r
 368 \r
 369 __STATIC_INLINE void P0_10_toggle(void){\r
 370     PORT0->OMR = 0x04000400UL;\r
 371 }\r
 372 \r
 373 __STATIC_INLINE uint32_t P0_10_read(void){\r
 374     return(PORT0->IN & 0x00000400UL);\r
 375 }\r
 376 \r
 377 __STATIC_INLINE void P0_11_set_mode(uint8_t mode){\r
 378     PORT0->IOCR8 &= ~0xf8000000UL;\r
 379     PORT0->IOCR8 |= mode << 24;\r
 380 }\r
 381 \r
 382 __STATIC_INLINE void P0_11_set_driver_strength(uint8_t strength){\r
 383     PORT0->PDR1 &= ~0x00007000UL;\r
 384     PORT0->PDR1 |= strength << 12;\r
 385 }\r
 386 \r
 387 __STATIC_INLINE void P0_11_set_hwsel(uint32_t config){\r
 388     PORT0->HWSEL &= ~0x00c00000UL;\r
 389     PORT0->HWSEL |= config << 22;\r
 390 }\r
 391 \r
 392 __STATIC_INLINE void P0_11_set(void){\r
 393     PORT0->OMR = 0x00000800UL;\r
 394 }\r
 395 \r
 396 __STATIC_INLINE void P0_11_reset(void){\r
 397     PORT0->OMR = 0x08000000UL;\r
 398 }\r
 399 \r
 400 __STATIC_INLINE void P0_11_toggle(void){\r
 401     PORT0->OMR = 0x08000800UL;\r
 402 }\r
 403 \r
 404 __STATIC_INLINE uint32_t P0_11_read(void){\r
 405     return(PORT0->IN & 0x00000800UL);\r
 406 }\r
 407 \r
 408 __STATIC_INLINE void P0_12_set_mode(uint8_t mode){\r
 409     PORT0->IOCR12 &= ~0x000000f8UL;\r
 410     PORT0->IOCR12 |= mode << 0;\r
 411 }\r
 412 \r
 413 __STATIC_INLINE void P0_12_set_driver_strength(uint8_t strength){\r
 414     PORT0->PDR1 &= ~0x00070000UL;\r
 415     PORT0->PDR1 |= strength << 16;\r
 416 }\r
 417 \r
 418 __STATIC_INLINE void P0_12_set_hwsel(uint32_t config){\r
 419     PORT0->HWSEL &= ~0x03000000UL;\r
 420     PORT0->HWSEL |= config << 24;\r
 421 }\r
 422 \r
 423 __STATIC_INLINE void P0_12_set(void){\r
 424     PORT0->OMR = 0x00001000UL;\r
 425 }\r
 426 \r
 427 __STATIC_INLINE void P0_12_reset(void){\r
 428     PORT0->OMR = 0x10000000UL;\r
 429 }\r
 430 \r
 431 __STATIC_INLINE void P0_12_toggle(void){\r
 432     PORT0->OMR = 0x10001000UL;\r
 433 }\r
 434 \r
 435 __STATIC_INLINE uint32_t P0_12_read(void){\r
 436     return(PORT0->IN & 0x00001000UL);\r
 437 }\r
 438 \r
 439 __STATIC_INLINE void P0_13_set_mode(uint8_t mode){\r
 440     PORT0->IOCR12 &= ~0x0000f800UL;\r
 441     PORT0->IOCR12 |= mode << 8;\r
 442 }\r
 443 \r
 444 __STATIC_INLINE void P0_13_set_driver_strength(uint8_t strength){\r
 445     PORT0->PDR1 &= ~0x00700000UL;\r
 446     PORT0->PDR1 |= strength << 20;\r
 447 }\r
 448 \r
 449 __STATIC_INLINE void P0_13_set_hwsel(uint32_t config){\r
 450     PORT0->HWSEL &= ~0x0c000000UL;\r
 451     PORT0->HWSEL |= config << 26;\r
 452 }\r
 453 \r
 454 __STATIC_INLINE void P0_13_set(void){\r
 455     PORT0->OMR = 0x00002000UL;\r
 456 }\r
 457 \r
 458 __STATIC_INLINE void P0_13_reset(void){\r
 459     PORT0->OMR = 0x20000000UL;\r
 460 }\r
 461 \r
 462 __STATIC_INLINE void P0_13_toggle(void){\r
 463     PORT0->OMR = 0x20002000UL;\r
 464 }\r
 465 \r
 466 __STATIC_INLINE uint32_t P0_13_read(void){\r
 467     return(PORT0->IN & 0x00002000UL);\r
 468 }\r
 469 \r
 470 __STATIC_INLINE void P0_14_set_mode(uint8_t mode){\r
 471     PORT0->IOCR12 &= ~0x00f80000UL;\r
 472     PORT0->IOCR12 |= mode << 16;\r
 473 }\r
 474 \r
 475 __STATIC_INLINE void P0_14_set_driver_strength(uint8_t strength){\r
 476     PORT0->PDR1 &= ~0x07000000UL;\r
 477     PORT0->PDR1 |= strength << 24;\r
 478 }\r
 479 \r
 480 __STATIC_INLINE void P0_14_set_hwsel(uint32_t config){\r
 481     PORT0->HWSEL &= ~0x30000000UL;\r
 482     PORT0->HWSEL |= config << 28;\r
 483 }\r
 484 \r
 485 __STATIC_INLINE void P0_14_set(void){\r
 486     PORT0->OMR = 0x00004000UL;\r
 487 }\r
 488 \r
 489 __STATIC_INLINE void P0_14_reset(void){\r
 490     PORT0->OMR = 0x40000000UL;\r
 491 }\r
 492 \r
 493 __STATIC_INLINE void P0_14_toggle(void){\r
 494     PORT0->OMR = 0x40004000UL;\r
 495 }\r
 496 \r
 497 __STATIC_INLINE uint32_t P0_14_read(void){\r
 498     return(PORT0->IN & 0x00004000UL);\r
 499 }\r
 500 \r
 501 __STATIC_INLINE void P0_15_set_mode(uint8_t mode){\r
 502     PORT0->IOCR12 &= ~0xf8000000UL;\r
 503     PORT0->IOCR12 |= mode << 24;\r
 504 }\r
 505 \r
 506 __STATIC_INLINE void P0_15_set_driver_strength(uint8_t strength){\r
 507     PORT0->PDR1 &= ~0x70000000UL;\r
 508     PORT0->PDR1 |= strength << 28;\r
 509 }\r
 510 \r
 511 __STATIC_INLINE void P0_15_set_hwsel(uint32_t config){\r
 512     PORT0->HWSEL &= ~0xc0000000UL;\r
 513     PORT0->HWSEL |= config << 30;\r
 514 }\r
 515 \r
 516 __STATIC_INLINE void P0_15_set(void){\r
 517     PORT0->OMR = 0x00008000UL;\r
 518 }\r
 519 \r
 520 __STATIC_INLINE void P0_15_reset(void){\r
 521     PORT0->OMR = 0x80000000UL;\r
 522 }\r
 523 \r
 524 __STATIC_INLINE void P0_15_toggle(void){\r
 525     PORT0->OMR = 0x80008000UL;\r
 526 }\r
 527 \r
 528 __STATIC_INLINE uint32_t P0_15_read(void){\r
 529     return(PORT0->IN & 0x00008000UL);\r
 530 }\r
 531 \r
 532 __STATIC_INLINE void P1_0_set_mode(uint8_t mode){\r
 533     PORT1->IOCR0 &= ~0x000000f8UL;\r
 534     PORT1->IOCR0 |= mode << 0;\r
 535 }\r
 536 \r
 537 __STATIC_INLINE void P1_0_set_driver_strength(uint8_t strength){\r
 538     PORT1->PDR0 &= ~0x00000007UL;\r
 539     PORT1->PDR0 |= strength << 0;\r
 540 }\r
 541 \r
 542 __STATIC_INLINE void P1_0_set_hwsel(uint32_t config){\r
 543     PORT1->HWSEL &= ~0x00000003UL;\r
 544     PORT1->HWSEL |= config << 0;\r
 545 }\r
 546 \r
 547 __STATIC_INLINE void P1_0_set(void){\r
 548     PORT1->OMR = 0x00000001UL;\r
 549 }\r
 550 \r
 551 __STATIC_INLINE void P1_0_reset(void){\r
 552     PORT1->OMR = 0x00010000UL;\r
 553 }\r
 554 \r
 555 __STATIC_INLINE void P1_0_toggle(void){\r
 556     PORT1->OMR = 0x00010001UL;\r
 557 }\r
 558 \r
 559 __STATIC_INLINE uint32_t P1_0_read(void){\r
 560     return(PORT1->IN & 0x00000001UL);\r
 561 }\r
 562 \r
 563 __STATIC_INLINE void P1_1_set_mode(uint8_t mode){\r
 564     PORT1->IOCR0 &= ~0x0000f800UL;\r
 565     PORT1->IOCR0 |= mode << 8;\r
 566 }\r
 567 \r
 568 __STATIC_INLINE void P1_1_set_driver_strength(uint8_t strength){\r
 569     PORT1->PDR0 &= ~0x00000070UL;\r
 570     PORT1->PDR0 |= strength << 4;\r
 571 }\r
 572 \r
 573 __STATIC_INLINE void P1_1_set_hwsel(uint32_t config){\r
 574     PORT1->HWSEL &= ~0x0000000cUL;\r
 575     PORT1->HWSEL |= config << 2;\r
 576 }\r
 577 \r
 578 __STATIC_INLINE void P1_1_set(void){\r
 579     PORT1->OMR = 0x00000002UL;\r
 580 }\r
 581 \r
 582 __STATIC_INLINE void P1_1_reset(void){\r
 583     PORT1->OMR = 0x00020000UL;\r
 584 }\r
 585 \r
 586 __STATIC_INLINE void P1_1_toggle(void){\r
 587     PORT1->OMR = 0x00020002UL;\r
 588 }\r
 589 \r
 590 __STATIC_INLINE uint32_t P1_1_read(void){\r
 591     return(PORT1->IN & 0x00000002UL);\r
 592 }\r
 593 \r
 594 __STATIC_INLINE void P1_2_set_mode(uint8_t mode){\r
 595     PORT1->IOCR0 &= ~0x00f80000UL;\r
 596     PORT1->IOCR0 |= mode << 16;\r
 597 }\r
 598 \r
 599 __STATIC_INLINE void P1_2_set_driver_strength(uint8_t strength){\r
 600     PORT1->PDR0 &= ~0x00000700UL;\r
 601     PORT1->PDR0 |= strength << 8;\r
 602 }\r
 603 \r
 604 __STATIC_INLINE void P1_2_set_hwsel(uint32_t config){\r
 605     PORT1->HWSEL &= ~0x00000030UL;\r
 606     PORT1->HWSEL |= config << 4;\r
 607 }\r
 608 \r
 609 __STATIC_INLINE void P1_2_set(void){\r
 610     PORT1->OMR = 0x00000004UL;\r
 611 }\r
 612 \r
 613 __STATIC_INLINE void P1_2_reset(void){\r
 614     PORT1->OMR = 0x00040000UL;\r
 615 }\r
 616 \r
 617 __STATIC_INLINE void P1_2_toggle(void){\r
 618     PORT1->OMR = 0x00040004UL;\r
 619 }\r
 620 \r
 621 __STATIC_INLINE uint32_t P1_2_read(void){\r
 622     return(PORT1->IN & 0x00000004UL);\r
 623 }\r
 624 \r
 625 __STATIC_INLINE void P1_3_set_mode(uint8_t mode){\r
 626     PORT1->IOCR0 &= ~0xf8000000UL;\r
 627     PORT1->IOCR0 |= mode << 24;\r
 628 }\r
 629 \r
 630 __STATIC_INLINE void P1_3_set_driver_strength(uint8_t strength){\r
 631     PORT1->PDR0 &= ~0x00007000UL;\r
 632     PORT1->PDR0 |= strength << 12;\r
 633 }\r
 634 \r
 635 __STATIC_INLINE void P1_3_set_hwsel(uint32_t config){\r
 636     PORT1->HWSEL &= ~0x000000c0UL;\r
 637     PORT1->HWSEL |= config << 6;\r
 638 }\r
 639 \r
 640 __STATIC_INLINE void P1_3_set(void){\r
 641     PORT1->OMR = 0x00000008UL;\r
 642 }\r
 643 \r
 644 __STATIC_INLINE void P1_3_reset(void){\r
 645     PORT1->OMR = 0x00080000UL;\r
 646 }\r
 647 \r
 648 __STATIC_INLINE void P1_3_toggle(void){\r
 649     PORT1->OMR = 0x00080008UL;\r
 650 }\r
 651 \r
 652 __STATIC_INLINE uint32_t P1_3_read(void){\r
 653     return(PORT1->IN & 0x00000008UL);\r
 654 }\r
 655 \r
 656 __STATIC_INLINE void P1_4_set_mode(uint8_t mode){\r
 657     PORT1->IOCR4 &= ~0x000000f8UL;\r
 658     PORT1->IOCR4 |= mode << 0;\r
 659 }\r
 660 \r
 661 __STATIC_INLINE void P1_4_set_driver_strength(uint8_t strength){\r
 662     PORT1->PDR0 &= ~0x00070000UL;\r
 663     PORT1->PDR0 |= strength << 16;\r
 664 }\r
 665 \r
 666 __STATIC_INLINE void P1_4_set_hwsel(uint32_t config){\r
 667     PORT1->HWSEL &= ~0x00000300UL;\r
 668     PORT1->HWSEL |= config << 8;\r
 669 }\r
 670 \r
 671 __STATIC_INLINE void P1_4_set(void){\r
 672     PORT1->OMR = 0x00000010UL;\r
 673 }\r
 674 \r
 675 __STATIC_INLINE void P1_4_reset(void){\r
 676     PORT1->OMR = 0x00100000UL;\r
 677 }\r
 678 \r
 679 __STATIC_INLINE void P1_4_toggle(void){\r
 680     PORT1->OMR = 0x00100010UL;\r
 681 }\r
 682 \r
 683 __STATIC_INLINE uint32_t P1_4_read(void){\r
 684     return(PORT1->IN & 0x00000010UL);\r
 685 }\r
 686 \r
 687 __STATIC_INLINE void P1_5_set_mode(uint8_t mode){\r
 688     PORT1->IOCR4 &= ~0x0000f800UL;\r
 689     PORT1->IOCR4 |= mode << 8;\r
 690 }\r
 691 \r
 692 __STATIC_INLINE void P1_5_set_driver_strength(uint8_t strength){\r
 693     PORT1->PDR0 &= ~0x00700000UL;\r
 694     PORT1->PDR0 |= strength << 20;\r
 695 }\r
 696 \r
 697 __STATIC_INLINE void P1_5_set_hwsel(uint32_t config){\r
 698     PORT1->HWSEL &= ~0x00000c00UL;\r
 699     PORT1->HWSEL |= config << 10;\r
 700 }\r
 701 \r
 702 __STATIC_INLINE void P1_5_set(void){\r
 703     PORT1->OMR = 0x00000020UL;\r
 704 }\r
 705 \r
 706 __STATIC_INLINE void P1_5_reset(void){\r
 707     PORT1->OMR = 0x00200000UL;\r
 708 }\r
 709 \r
 710 __STATIC_INLINE void P1_5_toggle(void){\r
 711     PORT1->OMR = 0x00200020UL;\r
 712 }\r
 713 \r
 714 __STATIC_INLINE uint32_t P1_5_read(void){\r
 715     return(PORT1->IN & 0x00000020UL);\r
 716 }\r
 717 \r
 718 __STATIC_INLINE void P1_6_set_mode(uint8_t mode){\r
 719     PORT1->IOCR4 &= ~0x00f80000UL;\r
 720     PORT1->IOCR4 |= mode << 16;\r
 721 }\r
 722 \r
 723 __STATIC_INLINE void P1_6_set_driver_strength(uint8_t strength){\r
 724     PORT1->PDR0 &= ~0x07000000UL;\r
 725     PORT1->PDR0 |= strength << 24;\r
 726 }\r
 727 \r
 728 __STATIC_INLINE void P1_6_set_hwsel(uint32_t config){\r
 729     PORT1->HWSEL &= ~0x00003000UL;\r
 730     PORT1->HWSEL |= config << 12;\r
 731 }\r
 732 \r
 733 __STATIC_INLINE void P1_6_set(void){\r
 734     PORT1->OMR = 0x00000040UL;\r
 735 }\r
 736 \r
 737 __STATIC_INLINE void P1_6_reset(void){\r
 738     PORT1->OMR = 0x00400000UL;\r
 739 }\r
 740 \r
 741 __STATIC_INLINE void P1_6_toggle(void){\r
 742     PORT1->OMR = 0x00400040UL;\r
 743 }\r
 744 \r
 745 __STATIC_INLINE uint32_t P1_6_read(void){\r
 746     return(PORT1->IN & 0x00000040UL);\r
 747 }\r
 748 \r
 749 __STATIC_INLINE void P1_7_set_mode(uint8_t mode){\r
 750     PORT1->IOCR4 &= ~0xf8000000UL;\r
 751     PORT1->IOCR4 |= mode << 24;\r
 752 }\r
 753 \r
 754 __STATIC_INLINE void P1_7_set_driver_strength(uint8_t strength){\r
 755     PORT1->PDR0 &= ~0x70000000UL;\r
 756     PORT1->PDR0 |= strength << 28;\r
 757 }\r
 758 \r
 759 __STATIC_INLINE void P1_7_set_hwsel(uint32_t config){\r
 760     PORT1->HWSEL &= ~0x0000c000UL;\r
 761     PORT1->HWSEL |= config << 14;\r
 762 }\r
 763 \r
 764 __STATIC_INLINE void P1_7_set(void){\r
 765     PORT1->OMR = 0x00000080UL;\r
 766 }\r
 767 \r
 768 __STATIC_INLINE void P1_7_reset(void){\r
 769     PORT1->OMR = 0x00800000UL;\r
 770 }\r
 771 \r
 772 __STATIC_INLINE void P1_7_toggle(void){\r
 773     PORT1->OMR = 0x00800080UL;\r
 774 }\r
 775 \r
 776 __STATIC_INLINE uint32_t P1_7_read(void){\r
 777     return(PORT1->IN & 0x00000080UL);\r
 778 }\r
 779 \r
 780 __STATIC_INLINE void P1_8_set_mode(uint8_t mode){\r
 781     PORT1->IOCR8 &= ~0x000000f8UL;\r
 782     PORT1->IOCR8 |= mode << 0;\r
 783 }\r
 784 \r
 785 __STATIC_INLINE void P1_8_set_driver_strength(uint8_t strength){\r
 786     PORT1->PDR1 &= ~0x00000007UL;\r
 787     PORT1->PDR1 |= strength << 0;\r
 788 }\r
 789 \r
 790 __STATIC_INLINE void P1_8_set_hwsel(uint32_t config){\r
 791     PORT1->HWSEL &= ~0x00030000UL;\r
 792     PORT1->HWSEL |= config << 16;\r
 793 }\r
 794 \r
 795 __STATIC_INLINE void P1_8_set(void){\r
 796     PORT1->OMR = 0x00000100UL;\r
 797 }\r
 798 \r
 799 __STATIC_INLINE void P1_8_reset(void){\r
 800     PORT1->OMR = 0x01000000UL;\r
 801 }\r
 802 \r
 803 __STATIC_INLINE void P1_8_toggle(void){\r
 804     PORT1->OMR = 0x01000100UL;\r
 805 }\r
 806 \r
 807 __STATIC_INLINE uint32_t P1_8_read(void){\r
 808     return(PORT1->IN & 0x00000100UL);\r
 809 }\r
 810 \r
 811 __STATIC_INLINE void P1_9_set_mode(uint8_t mode){\r
 812     PORT1->IOCR8 &= ~0x0000f800UL;\r
 813     PORT1->IOCR8 |= mode << 8;\r
 814 }\r
 815 \r
 816 __STATIC_INLINE void P1_9_set_driver_strength(uint8_t strength){\r
 817     PORT1->PDR1 &= ~0x00000070UL;\r
 818     PORT1->PDR1 |= strength << 4;\r
 819 }\r
 820 \r
 821 __STATIC_INLINE void P1_9_set_hwsel(uint32_t config){\r
 822     PORT1->HWSEL &= ~0x000c0000UL;\r
 823     PORT1->HWSEL |= config << 18;\r
 824 }\r
 825 \r
 826 __STATIC_INLINE void P1_9_set(void){\r
 827     PORT1->OMR = 0x00000200UL;\r
 828 }\r
 829 \r
 830 __STATIC_INLINE void P1_9_reset(void){\r
 831     PORT1->OMR = 0x02000000UL;\r
 832 }\r
 833 \r
 834 __STATIC_INLINE void P1_9_toggle(void){\r
 835     PORT1->OMR = 0x02000200UL;\r
 836 }\r
 837 \r
 838 __STATIC_INLINE uint32_t P1_9_read(void){\r
 839     return(PORT1->IN & 0x00000200UL);\r
 840 }\r
 841 \r
 842 __STATIC_INLINE void P1_10_set_mode(uint8_t mode){\r
 843     PORT1->IOCR8 &= ~0x00f80000UL;\r
 844     PORT1->IOCR8 |= mode << 16;\r
 845 }\r
 846 \r
 847 __STATIC_INLINE void P1_10_set_driver_strength(uint8_t strength){\r
 848     PORT1->PDR1 &= ~0x00000700UL;\r
 849     PORT1->PDR1 |= strength << 8;\r
 850 }\r
 851 \r
 852 __STATIC_INLINE void P1_10_set_hwsel(uint32_t config){\r
 853     PORT1->HWSEL &= ~0x00300000UL;\r
 854     PORT1->HWSEL |= config << 20;\r
 855 }\r
 856 \r
 857 __STATIC_INLINE void P1_10_set(void){\r
 858     PORT1->OMR = 0x00000400UL;\r
 859 }\r
 860 \r
 861 __STATIC_INLINE void P1_10_reset(void){\r
 862     PORT1->OMR = 0x04000000UL;\r
 863 }\r
 864 \r
 865 __STATIC_INLINE void P1_10_toggle(void){\r
 866     PORT1->OMR = 0x04000400UL;\r
 867 }\r
 868 \r
 869 __STATIC_INLINE uint32_t P1_10_read(void){\r
 870     return(PORT1->IN & 0x00000400UL);\r
 871 }\r
 872 \r
 873 __STATIC_INLINE void P1_11_set_mode(uint8_t mode){\r
 874     PORT1->IOCR8 &= ~0xf8000000UL;\r
 875     PORT1->IOCR8 |= mode << 24;\r
 876 }\r
 877 \r
 878 __STATIC_INLINE void P1_11_set_driver_strength(uint8_t strength){\r
 879     PORT1->PDR1 &= ~0x00007000UL;\r
 880     PORT1->PDR1 |= strength << 12;\r
 881 }\r
 882 \r
 883 __STATIC_INLINE void P1_11_set_hwsel(uint32_t config){\r
 884     PORT1->HWSEL &= ~0x00c00000UL;\r
 885     PORT1->HWSEL |= config << 22;\r
 886 }\r
 887 \r
 888 __STATIC_INLINE void P1_11_set(void){\r
 889     PORT1->OMR = 0x00000800UL;\r
 890 }\r
 891 \r
 892 __STATIC_INLINE void P1_11_reset(void){\r
 893     PORT1->OMR = 0x08000000UL;\r
 894 }\r
 895 \r
 896 __STATIC_INLINE void P1_11_toggle(void){\r
 897     PORT1->OMR = 0x08000800UL;\r
 898 }\r
 899 \r
 900 __STATIC_INLINE uint32_t P1_11_read(void){\r
 901     return(PORT1->IN & 0x00000800UL);\r
 902 }\r
 903 \r
 904 __STATIC_INLINE void P1_12_set_mode(uint8_t mode){\r
 905     PORT1->IOCR12 &= ~0x000000f8UL;\r
 906     PORT1->IOCR12 |= mode << 0;\r
 907 }\r
 908 \r
 909 __STATIC_INLINE void P1_12_set_driver_strength(uint8_t strength){\r
 910     PORT1->PDR1 &= ~0x00070000UL;\r
 911     PORT1->PDR1 |= strength << 16;\r
 912 }\r
 913 \r
 914 __STATIC_INLINE void P1_12_set_hwsel(uint32_t config){\r
 915     PORT1->HWSEL &= ~0x03000000UL;\r
 916     PORT1->HWSEL |= config << 24;\r
 917 }\r
 918 \r
 919 __STATIC_INLINE void P1_12_set(void){\r
 920     PORT1->OMR = 0x00001000UL;\r
 921 }\r
 922 \r
 923 __STATIC_INLINE void P1_12_reset(void){\r
 924     PORT1->OMR = 0x10000000UL;\r
 925 }\r
 926 \r
 927 __STATIC_INLINE void P1_12_toggle(void){\r
 928     PORT1->OMR = 0x10001000UL;\r
 929 }\r
 930 \r
 931 __STATIC_INLINE uint32_t P1_12_read(void){\r
 932     return(PORT1->IN & 0x00001000UL);\r
 933 }\r
 934 \r
 935 __STATIC_INLINE void P1_13_set_mode(uint8_t mode){\r
 936     PORT1->IOCR12 &= ~0x0000f800UL;\r
 937     PORT1->IOCR12 |= mode << 8;\r
 938 }\r
 939 \r
 940 __STATIC_INLINE void P1_13_set_driver_strength(uint8_t strength){\r
 941     PORT1->PDR1 &= ~0x00700000UL;\r
 942     PORT1->PDR1 |= strength << 20;\r
 943 }\r
 944 \r
 945 __STATIC_INLINE void P1_13_set_hwsel(uint32_t config){\r
 946     PORT1->HWSEL &= ~0x0c000000UL;\r
 947     PORT1->HWSEL |= config << 26;\r
 948 }\r
 949 \r
 950 __STATIC_INLINE void P1_13_set(void){\r
 951     PORT1->OMR = 0x00002000UL;\r
 952 }\r
 953 \r
 954 __STATIC_INLINE void P1_13_reset(void){\r
 955     PORT1->OMR = 0x20000000UL;\r
 956 }\r
 957 \r
 958 __STATIC_INLINE void P1_13_toggle(void){\r
 959     PORT1->OMR = 0x20002000UL;\r
 960 }\r
 961 \r
 962 __STATIC_INLINE uint32_t P1_13_read(void){\r
 963     return(PORT1->IN & 0x00002000UL);\r
 964 }\r
 965 \r
 966 __STATIC_INLINE void P1_14_set_mode(uint8_t mode){\r
 967     PORT1->IOCR12 &= ~0x00f80000UL;\r
 968     PORT1->IOCR12 |= mode << 16;\r
 969 }\r
 970 \r
 971 __STATIC_INLINE void P1_14_set_driver_strength(uint8_t strength){\r
 972     PORT1->PDR1 &= ~0x07000000UL;\r
 973     PORT1->PDR1 |= strength << 24;\r
 974 }\r
 975 \r
 976 __STATIC_INLINE void P1_14_set_hwsel(uint32_t config){\r
 977     PORT1->HWSEL &= ~0x30000000UL;\r
 978     PORT1->HWSEL |= config << 28;\r
 979 }\r
 980 \r
 981 __STATIC_INLINE void P1_14_set(void){\r
 982     PORT1->OMR = 0x00004000UL;\r
 983 }\r
 984 \r
 985 __STATIC_INLINE void P1_14_reset(void){\r
 986     PORT1->OMR = 0x40000000UL;\r
 987 }\r
 988 \r
 989 __STATIC_INLINE void P1_14_toggle(void){\r
 990     PORT1->OMR = 0x40004000UL;\r
 991 }\r
 992 \r
 993 __STATIC_INLINE uint32_t P1_14_read(void){\r
 994     return(PORT1->IN & 0x00004000UL);\r
 995 }\r
 996 \r
 997 __STATIC_INLINE void P1_15_set_mode(uint8_t mode){\r
 998     PORT1->IOCR12 &= ~0xf8000000UL;\r
 999     PORT1->IOCR12 |= mode << 24;\r
1000 }\r
1001 \r
1002 __STATIC_INLINE void P1_15_set_driver_strength(uint8_t strength){\r
1003     PORT1->PDR1 &= ~0x70000000UL;\r
1004     PORT1->PDR1 |= strength << 28;\r
1005 }\r
1006 \r
1007 __STATIC_INLINE void P1_15_set_hwsel(uint32_t config){\r
1008     PORT1->HWSEL &= ~0xc0000000UL;\r
1009     PORT1->HWSEL |= config << 30;\r
1010 }\r
1011 \r
1012 __STATIC_INLINE void P1_15_set(void){\r
1013     PORT1->OMR = 0x00008000UL;\r
1014 }\r
1015 \r
1016 __STATIC_INLINE void P1_15_reset(void){\r
1017     PORT1->OMR = 0x80000000UL;\r
1018 }\r
1019 \r
1020 __STATIC_INLINE void P1_15_toggle(void){\r
1021     PORT1->OMR = 0x80008000UL;\r
1022 }\r
1023 \r
1024 __STATIC_INLINE uint32_t P1_15_read(void){\r
1025     return(PORT1->IN & 0x00008000UL);\r
1026 }\r
1027 \r
1028 __STATIC_INLINE void P2_0_set_mode(uint8_t mode){\r
1029     PORT2->IOCR0 &= ~0x000000f8UL;\r
1030     PORT2->IOCR0 |= mode << 0;\r
1031 }\r
1032 \r
1033 __STATIC_INLINE void P2_0_set_driver_strength(uint8_t strength){\r
1034     PORT2->PDR0 &= ~0x00000007UL;\r
1035     PORT2->PDR0 |= strength << 0;\r
1036 }\r
1037 \r
1038 __STATIC_INLINE void P2_0_set_hwsel(uint32_t config){\r
1039     PORT2->HWSEL &= ~0x00000003UL;\r
1040     PORT2->HWSEL |= config << 0;\r
1041 }\r
1042 \r
1043 __STATIC_INLINE void P2_0_set(void){\r
1044     PORT2->OMR = 0x00000001UL;\r
1045 }\r
1046 \r
1047 __STATIC_INLINE void P2_0_reset(void){\r
1048     PORT2->OMR = 0x00010000UL;\r
1049 }\r
1050 \r
1051 __STATIC_INLINE void P2_0_toggle(void){\r
1052     PORT2->OMR = 0x00010001UL;\r
1053 }\r
1054 \r
1055 __STATIC_INLINE uint32_t P2_0_read(void){\r
1056     return(PORT2->IN & 0x00000001UL);\r
1057 }\r
1058 \r
1059 __STATIC_INLINE void P2_1_set_mode(uint8_t mode){\r
1060     PORT2->IOCR0 &= ~0x0000f800UL;\r
1061     PORT2->IOCR0 |= mode << 8;\r
1062 }\r
1063 \r
1064 __STATIC_INLINE void P2_1_set_driver_strength(uint8_t strength){\r
1065     PORT2->PDR0 &= ~0x00000070UL;\r
1066     PORT2->PDR0 |= strength << 4;\r
1067 }\r
1068 \r
1069 __STATIC_INLINE void P2_1_set_hwsel(uint32_t config){\r
1070     PORT2->HWSEL &= ~0x0000000cUL;\r
1071     PORT2->HWSEL |= config << 2;\r
1072 }\r
1073 \r
1074 __STATIC_INLINE void P2_1_set(void){\r
1075     PORT2->OMR = 0x00000002UL;\r
1076 }\r
1077 \r
1078 __STATIC_INLINE void P2_1_reset(void){\r
1079     PORT2->OMR = 0x00020000UL;\r
1080 }\r
1081 \r
1082 __STATIC_INLINE void P2_1_toggle(void){\r
1083     PORT2->OMR = 0x00020002UL;\r
1084 }\r
1085 \r
1086 __STATIC_INLINE uint32_t P2_1_read(void){\r
1087     return(PORT2->IN & 0x00000002UL);\r
1088 }\r
1089 \r
1090 __STATIC_INLINE void P2_2_set_mode(uint8_t mode){\r
1091     PORT2->IOCR0 &= ~0x00f80000UL;\r
1092     PORT2->IOCR0 |= mode << 16;\r
1093 }\r
1094 \r
1095 __STATIC_INLINE void P2_2_set_driver_strength(uint8_t strength){\r
1096     PORT2->PDR0 &= ~0x00000700UL;\r
1097     PORT2->PDR0 |= strength << 8;\r
1098 }\r
1099 \r
1100 __STATIC_INLINE void P2_2_set_hwsel(uint32_t config){\r
1101     PORT2->HWSEL &= ~0x00000030UL;\r
1102     PORT2->HWSEL |= config << 4;\r
1103 }\r
1104 \r
1105 __STATIC_INLINE void P2_2_set(void){\r
1106     PORT2->OMR = 0x00000004UL;\r
1107 }\r
1108 \r
1109 __STATIC_INLINE void P2_2_reset(void){\r
1110     PORT2->OMR = 0x00040000UL;\r
1111 }\r
1112 \r
1113 __STATIC_INLINE void P2_2_toggle(void){\r
1114     PORT2->OMR = 0x00040004UL;\r
1115 }\r
1116 \r
1117 __STATIC_INLINE uint32_t P2_2_read(void){\r
1118     return(PORT2->IN & 0x00000004UL);\r
1119 }\r
1120 \r
1121 __STATIC_INLINE void P2_3_set_mode(uint8_t mode){\r
1122     PORT2->IOCR0 &= ~0xf8000000UL;\r
1123     PORT2->IOCR0 |= mode << 24;\r
1124 }\r
1125 \r
1126 __STATIC_INLINE void P2_3_set_driver_strength(uint8_t strength){\r
1127     PORT2->PDR0 &= ~0x00007000UL;\r
1128     PORT2->PDR0 |= strength << 12;\r
1129 }\r
1130 \r
1131 __STATIC_INLINE void P2_3_set_hwsel(uint32_t config){\r
1132     PORT2->HWSEL &= ~0x000000c0UL;\r
1133     PORT2->HWSEL |= config << 6;\r
1134 }\r
1135 \r
1136 __STATIC_INLINE void P2_3_set(void){\r
1137     PORT2->OMR = 0x00000008UL;\r
1138 }\r
1139 \r
1140 __STATIC_INLINE void P2_3_reset(void){\r
1141     PORT2->OMR = 0x00080000UL;\r
1142 }\r
1143 \r
1144 __STATIC_INLINE void P2_3_toggle(void){\r
1145     PORT2->OMR = 0x00080008UL;\r
1146 }\r
1147 \r
1148 __STATIC_INLINE uint32_t P2_3_read(void){\r
1149     return(PORT2->IN & 0x00000008UL);\r
1150 }\r
1151 \r
1152 __STATIC_INLINE void P2_4_set_mode(uint8_t mode){\r
1153     PORT2->IOCR4 &= ~0x000000f8UL;\r
1154     PORT2->IOCR4 |= mode << 0;\r
1155 }\r
1156 \r
1157 __STATIC_INLINE void P2_4_set_driver_strength(uint8_t strength){\r
1158     PORT2->PDR0 &= ~0x00070000UL;\r
1159     PORT2->PDR0 |= strength << 16;\r
1160 }\r
1161 \r
1162 __STATIC_INLINE void P2_4_set_hwsel(uint32_t config){\r
1163     PORT2->HWSEL &= ~0x00000300UL;\r
1164     PORT2->HWSEL |= config << 8;\r
1165 }\r
1166 \r
1167 __STATIC_INLINE void P2_4_set(void){\r
1168     PORT2->OMR = 0x00000010UL;\r
1169 }\r
1170 \r
1171 __STATIC_INLINE void P2_4_reset(void){\r
1172     PORT2->OMR = 0x00100000UL;\r
1173 }\r
1174 \r
1175 __STATIC_INLINE void P2_4_toggle(void){\r
1176     PORT2->OMR = 0x00100010UL;\r
1177 }\r
1178 \r
1179 __STATIC_INLINE uint32_t P2_4_read(void){\r
1180     return(PORT2->IN & 0x00000010UL);\r
1181 }\r
1182 \r
1183 __STATIC_INLINE void P2_5_set_mode(uint8_t mode){\r
1184     PORT2->IOCR4 &= ~0x0000f800UL;\r
1185     PORT2->IOCR4 |= mode << 8;\r
1186 }\r
1187 \r
1188 __STATIC_INLINE void P2_5_set_driver_strength(uint8_t strength){\r
1189     PORT2->PDR0 &= ~0x00700000UL;\r
1190     PORT2->PDR0 |= strength << 20;\r
1191 }\r
1192 \r
1193 __STATIC_INLINE void P2_5_set_hwsel(uint32_t config){\r
1194     PORT2->HWSEL &= ~0x00000c00UL;\r
1195     PORT2->HWSEL |= config << 10;\r
1196 }\r
1197 \r
1198 __STATIC_INLINE void P2_5_set(void){\r
1199     PORT2->OMR = 0x00000020UL;\r
1200 }\r
1201 \r
1202 __STATIC_INLINE void P2_5_reset(void){\r
1203     PORT2->OMR = 0x00200000UL;\r
1204 }\r
1205 \r
1206 __STATIC_INLINE void P2_5_toggle(void){\r
1207     PORT2->OMR = 0x00200020UL;\r
1208 }\r
1209 \r
1210 __STATIC_INLINE uint32_t P2_5_read(void){\r
1211     return(PORT2->IN & 0x00000020UL);\r
1212 }\r
1213 \r
1214 __STATIC_INLINE void P2_6_set_mode(uint8_t mode){\r
1215     PORT2->IOCR4 &= ~0x00f80000UL;\r
1216     PORT2->IOCR4 |= mode << 16;\r
1217 }\r
1218 \r
1219 __STATIC_INLINE void P2_6_set_driver_strength(uint8_t strength){\r
1220     PORT2->PDR0 &= ~0x07000000UL;\r
1221     PORT2->PDR0 |= strength << 24;\r
1222 }\r
1223 \r
1224 __STATIC_INLINE void P2_6_set_hwsel(uint32_t config){\r
1225     PORT2->HWSEL &= ~0x00003000UL;\r
1226     PORT2->HWSEL |= config << 12;\r
1227 }\r
1228 \r
1229 __STATIC_INLINE void P2_6_set(void){\r
1230     PORT2->OMR = 0x00000040UL;\r
1231 }\r
1232 \r
1233 __STATIC_INLINE void P2_6_reset(void){\r
1234     PORT2->OMR = 0x00400000UL;\r
1235 }\r
1236 \r
1237 __STATIC_INLINE void P2_6_toggle(void){\r
1238     PORT2->OMR = 0x00400040UL;\r
1239 }\r
1240 \r
1241 __STATIC_INLINE uint32_t P2_6_read(void){\r
1242     return(PORT2->IN & 0x00000040UL);\r
1243 }\r
1244 \r
1245 __STATIC_INLINE void P2_7_set_mode(uint8_t mode){\r
1246     PORT2->IOCR4 &= ~0xf8000000UL;\r
1247     PORT2->IOCR4 |= mode << 24;\r
1248 }\r
1249 \r
1250 __STATIC_INLINE void P2_7_set_driver_strength(uint8_t strength){\r
1251     PORT2->PDR0 &= ~0x70000000UL;\r
1252     PORT2->PDR0 |= strength << 28;\r
1253 }\r
1254 \r
1255 __STATIC_INLINE void P2_7_set_hwsel(uint32_t config){\r
1256     PORT2->HWSEL &= ~0x0000c000UL;\r
1257     PORT2->HWSEL |= config << 14;\r
1258 }\r
1259 \r
1260 __STATIC_INLINE void P2_7_set(void){\r
1261     PORT2->OMR = 0x00000080UL;\r
1262 }\r
1263 \r
1264 __STATIC_INLINE void P2_7_reset(void){\r
1265     PORT2->OMR = 0x00800000UL;\r
1266 }\r
1267 \r
1268 __STATIC_INLINE void P2_7_toggle(void){\r
1269     PORT2->OMR = 0x00800080UL;\r
1270 }\r
1271 \r
1272 __STATIC_INLINE uint32_t P2_7_read(void){\r
1273     return(PORT2->IN & 0x00000080UL);\r
1274 }\r
1275 \r
1276 __STATIC_INLINE void P2_8_set_mode(uint8_t mode){\r
1277     PORT2->IOCR8 &= ~0x000000f8UL;\r
1278     PORT2->IOCR8 |= mode << 0;\r
1279 }\r
1280 \r
1281 __STATIC_INLINE void P2_8_set_driver_strength(uint8_t strength){\r
1282     PORT2->PDR1 &= ~0x00000007UL;\r
1283     PORT2->PDR1 |= strength << 0;\r
1284 }\r
1285 \r
1286 __STATIC_INLINE void P2_8_set_hwsel(uint32_t config){\r
1287     PORT2->HWSEL &= ~0x00030000UL;\r
1288     PORT2->HWSEL |= config << 16;\r
1289 }\r
1290 \r
1291 __STATIC_INLINE void P2_8_set(void){\r
1292     PORT2->OMR = 0x00000100UL;\r
1293 }\r
1294 \r
1295 __STATIC_INLINE void P2_8_reset(void){\r
1296     PORT2->OMR = 0x01000000UL;\r
1297 }\r
1298 \r
1299 __STATIC_INLINE void P2_8_toggle(void){\r
1300     PORT2->OMR = 0x01000100UL;\r
1301 }\r
1302 \r
1303 __STATIC_INLINE uint32_t P2_8_read(void){\r
1304     return(PORT2->IN & 0x00000100UL);\r
1305 }\r
1306 \r
1307 __STATIC_INLINE void P2_9_set_mode(uint8_t mode){\r
1308     PORT2->IOCR8 &= ~0x0000f800UL;\r
1309     PORT2->IOCR8 |= mode << 8;\r
1310 }\r
1311 \r
1312 __STATIC_INLINE void P2_9_set_driver_strength(uint8_t strength){\r
1313     PORT2->PDR1 &= ~0x00000070UL;\r
1314     PORT2->PDR1 |= strength << 4;\r
1315 }\r
1316 \r
1317 __STATIC_INLINE void P2_9_set_hwsel(uint32_t config){\r
1318     PORT2->HWSEL &= ~0x000c0000UL;\r
1319     PORT2->HWSEL |= config << 18;\r
1320 }\r
1321 \r
1322 __STATIC_INLINE void P2_9_set(void){\r
1323     PORT2->OMR = 0x00000200UL;\r
1324 }\r
1325 \r
1326 __STATIC_INLINE void P2_9_reset(void){\r
1327     PORT2->OMR = 0x02000000UL;\r
1328 }\r
1329 \r
1330 __STATIC_INLINE void P2_9_toggle(void){\r
1331     PORT2->OMR = 0x02000200UL;\r
1332 }\r
1333 \r
1334 __STATIC_INLINE uint32_t P2_9_read(void){\r
1335     return(PORT2->IN & 0x00000200UL);\r
1336 }\r
1337 \r
1338 __STATIC_INLINE void P2_10_set_mode(uint8_t mode){\r
1339     PORT2->IOCR8 &= ~0x00f80000UL;\r
1340     PORT2->IOCR8 |= mode << 16;\r
1341 }\r
1342 \r
1343 __STATIC_INLINE void P2_10_set_driver_strength(uint8_t strength){\r
1344     PORT2->PDR1 &= ~0x00000700UL;\r
1345     PORT2->PDR1 |= strength << 8;\r
1346 }\r
1347 \r
1348 __STATIC_INLINE void P2_10_set_hwsel(uint32_t config){\r
1349     PORT2->HWSEL &= ~0x00300000UL;\r
1350     PORT2->HWSEL |= config << 20;\r
1351 }\r
1352 \r
1353 __STATIC_INLINE void P2_10_set(void){\r
1354     PORT2->OMR = 0x00000400UL;\r
1355 }\r
1356 \r
1357 __STATIC_INLINE void P2_10_reset(void){\r
1358     PORT2->OMR = 0x04000000UL;\r
1359 }\r
1360 \r
1361 __STATIC_INLINE void P2_10_toggle(void){\r
1362     PORT2->OMR = 0x04000400UL;\r
1363 }\r
1364 \r
1365 __STATIC_INLINE uint32_t P2_10_read(void){\r
1366     return(PORT2->IN & 0x00000400UL);\r
1367 }\r
1368 \r
1369 __STATIC_INLINE void P2_11_set_mode(uint8_t mode){\r
1370     PORT2->IOCR8 &= ~0xf8000000UL;\r
1371     PORT2->IOCR8 |= mode << 24;\r
1372 }\r
1373 \r
1374 __STATIC_INLINE void P2_11_set_driver_strength(uint8_t strength){\r
1375     PORT2->PDR1 &= ~0x00007000UL;\r
1376     PORT2->PDR1 |= strength << 12;\r
1377 }\r
1378 \r
1379 __STATIC_INLINE void P2_11_set_hwsel(uint32_t config){\r
1380     PORT2->HWSEL &= ~0x00c00000UL;\r
1381     PORT2->HWSEL |= config << 22;\r
1382 }\r
1383 \r
1384 __STATIC_INLINE void P2_11_set(void){\r
1385     PORT2->OMR = 0x00000800UL;\r
1386 }\r
1387 \r
1388 __STATIC_INLINE void P2_11_reset(void){\r
1389     PORT2->OMR = 0x08000000UL;\r
1390 }\r
1391 \r
1392 __STATIC_INLINE void P2_11_toggle(void){\r
1393     PORT2->OMR = 0x08000800UL;\r
1394 }\r
1395 \r
1396 __STATIC_INLINE uint32_t P2_11_read(void){\r
1397     return(PORT2->IN & 0x00000800UL);\r
1398 }\r
1399 \r
1400 __STATIC_INLINE void P2_12_set_mode(uint8_t mode){\r
1401     PORT2->IOCR12 &= ~0x000000f8UL;\r
1402     PORT2->IOCR12 |= mode << 0;\r
1403 }\r
1404 \r
1405 __STATIC_INLINE void P2_12_set_driver_strength(uint8_t strength){\r
1406     PORT2->PDR1 &= ~0x00070000UL;\r
1407     PORT2->PDR1 |= strength << 16;\r
1408 }\r
1409 \r
1410 __STATIC_INLINE void P2_12_set_hwsel(uint32_t config){\r
1411     PORT2->HWSEL &= ~0x03000000UL;\r
1412     PORT2->HWSEL |= config << 24;\r
1413 }\r
1414 \r
1415 __STATIC_INLINE void P2_12_set(void){\r
1416     PORT2->OMR = 0x00001000UL;\r
1417 }\r
1418 \r
1419 __STATIC_INLINE void P2_12_reset(void){\r
1420     PORT2->OMR = 0x10000000UL;\r
1421 }\r
1422 \r
1423 __STATIC_INLINE void P2_12_toggle(void){\r
1424     PORT2->OMR = 0x10001000UL;\r
1425 }\r
1426 \r
1427 __STATIC_INLINE uint32_t P2_12_read(void){\r
1428     return(PORT2->IN & 0x00001000UL);\r
1429 }\r
1430 \r
1431 __STATIC_INLINE void P2_13_set_mode(uint8_t mode){\r
1432     PORT2->IOCR12 &= ~0x0000f800UL;\r
1433     PORT2->IOCR12 |= mode << 8;\r
1434 }\r
1435 \r
1436 __STATIC_INLINE void P2_13_set_driver_strength(uint8_t strength){\r
1437     PORT2->PDR1 &= ~0x00700000UL;\r
1438     PORT2->PDR1 |= strength << 20;\r
1439 }\r
1440 \r
1441 __STATIC_INLINE void P2_13_set_hwsel(uint32_t config){\r
1442     PORT2->HWSEL &= ~0x0c000000UL;\r
1443     PORT2->HWSEL |= config << 26;\r
1444 }\r
1445 \r
1446 __STATIC_INLINE void P2_13_set(void){\r
1447     PORT2->OMR = 0x00002000UL;\r
1448 }\r
1449 \r
1450 __STATIC_INLINE void P2_13_reset(void){\r
1451     PORT2->OMR = 0x20000000UL;\r
1452 }\r
1453 \r
1454 __STATIC_INLINE void P2_13_toggle(void){\r
1455     PORT2->OMR = 0x20002000UL;\r
1456 }\r
1457 \r
1458 __STATIC_INLINE uint32_t P2_13_read(void){\r
1459     return(PORT2->IN & 0x00002000UL);\r
1460 }\r
1461 \r
1462 __STATIC_INLINE void P2_14_set_mode(uint8_t mode){\r
1463     PORT2->IOCR12 &= ~0x00f80000UL;\r
1464     PORT2->IOCR12 |= mode << 16;\r
1465 }\r
1466 \r
1467 __STATIC_INLINE void P2_14_set_driver_strength(uint8_t strength){\r
1468     PORT2->PDR1 &= ~0x07000000UL;\r
1469     PORT2->PDR1 |= strength << 24;\r
1470 }\r
1471 \r
1472 __STATIC_INLINE void P2_14_set_hwsel(uint32_t config){\r
1473     PORT2->HWSEL &= ~0x30000000UL;\r
1474     PORT2->HWSEL |= config << 28;\r
1475 }\r
1476 \r
1477 __STATIC_INLINE void P2_14_set(void){\r
1478     PORT2->OMR = 0x00004000UL;\r
1479 }\r
1480 \r
1481 __STATIC_INLINE void P2_14_reset(void){\r
1482     PORT2->OMR = 0x40000000UL;\r
1483 }\r
1484 \r
1485 __STATIC_INLINE void P2_14_toggle(void){\r
1486     PORT2->OMR = 0x40004000UL;\r
1487 }\r
1488 \r
1489 __STATIC_INLINE uint32_t P2_14_read(void){\r
1490     return(PORT2->IN & 0x00004000UL);\r
1491 }\r
1492 \r
1493 __STATIC_INLINE void P2_15_set_mode(uint8_t mode){\r
1494     PORT2->IOCR12 &= ~0xf8000000UL;\r
1495     PORT2->IOCR12 |= mode << 24;\r
1496 }\r
1497 \r
1498 __STATIC_INLINE void P2_15_set_driver_strength(uint8_t strength){\r
1499     PORT2->PDR1 &= ~0x70000000UL;\r
1500     PORT2->PDR1 |= strength << 28;\r
1501 }\r
1502 \r
1503 __STATIC_INLINE void P2_15_set_hwsel(uint32_t config){\r
1504     PORT2->HWSEL &= ~0xc0000000UL;\r
1505     PORT2->HWSEL |= config << 30;\r
1506 }\r
1507 \r
1508 __STATIC_INLINE void P2_15_set(void){\r
1509     PORT2->OMR = 0x00008000UL;\r
1510 }\r
1511 \r
1512 __STATIC_INLINE void P2_15_reset(void){\r
1513     PORT2->OMR = 0x80000000UL;\r
1514 }\r
1515 \r
1516 __STATIC_INLINE void P2_15_toggle(void){\r
1517     PORT2->OMR = 0x80008000UL;\r
1518 }\r
1519 \r
1520 __STATIC_INLINE uint32_t P2_15_read(void){\r
1521     return(PORT2->IN & 0x00008000UL);\r
1522 }\r
1523 \r
1524 __STATIC_INLINE void P3_0_set_mode(uint8_t mode){\r
1525     PORT3->IOCR0 &= ~0x000000f8UL;\r
1526     PORT3->IOCR0 |= mode << 0;\r
1527 }\r
1528 \r
1529 __STATIC_INLINE void P3_0_set_driver_strength(uint8_t strength){\r
1530     PORT3->PDR0 &= ~0x00000007UL;\r
1531     PORT3->PDR0 |= strength << 0;\r
1532 }\r
1533 \r
1534 __STATIC_INLINE void P3_0_set_hwsel(uint32_t config){\r
1535     PORT3->HWSEL &= ~0x00000003UL;\r
1536     PORT3->HWSEL |= config << 0;\r
1537 }\r
1538 \r
1539 __STATIC_INLINE void P3_0_set(void){\r
1540     PORT3->OMR = 0x00000001UL;\r
1541 }\r
1542 \r
1543 __STATIC_INLINE void P3_0_reset(void){\r
1544     PORT3->OMR = 0x00010000UL;\r
1545 }\r
1546 \r
1547 __STATIC_INLINE void P3_0_toggle(void){\r
1548     PORT3->OMR = 0x00010001UL;\r
1549 }\r
1550 \r
1551 __STATIC_INLINE uint32_t P3_0_read(void){\r
1552     return(PORT3->IN & 0x00000001UL);\r
1553 }\r
1554 \r
1555 __STATIC_INLINE void P3_1_set_mode(uint8_t mode){\r
1556     PORT3->IOCR0 &= ~0x0000f800UL;\r
1557     PORT3->IOCR0 |= mode << 8;\r
1558 }\r
1559 \r
1560 __STATIC_INLINE void P3_1_set_driver_strength(uint8_t strength){\r
1561     PORT3->PDR0 &= ~0x00000070UL;\r
1562     PORT3->PDR0 |= strength << 4;\r
1563 }\r
1564 \r
1565 __STATIC_INLINE void P3_1_set_hwsel(uint32_t config){\r
1566     PORT3->HWSEL &= ~0x0000000cUL;\r
1567     PORT3->HWSEL |= config << 2;\r
1568 }\r
1569 \r
1570 __STATIC_INLINE void P3_1_set(void){\r
1571     PORT3->OMR = 0x00000002UL;\r
1572 }\r
1573 \r
1574 __STATIC_INLINE void P3_1_reset(void){\r
1575     PORT3->OMR = 0x00020000UL;\r
1576 }\r
1577 \r
1578 __STATIC_INLINE void P3_1_toggle(void){\r
1579     PORT3->OMR = 0x00020002UL;\r
1580 }\r
1581 \r
1582 __STATIC_INLINE uint32_t P3_1_read(void){\r
1583     return(PORT3->IN & 0x00000002UL);\r
1584 }\r
1585 \r
1586 __STATIC_INLINE void P3_2_set_mode(uint8_t mode){\r
1587     PORT3->IOCR0 &= ~0x00f80000UL;\r
1588     PORT3->IOCR0 |= mode << 16;\r
1589 }\r
1590 \r
1591 __STATIC_INLINE void P3_2_set_driver_strength(uint8_t strength){\r
1592     PORT3->PDR0 &= ~0x00000700UL;\r
1593     PORT3->PDR0 |= strength << 8;\r
1594 }\r
1595 \r
1596 __STATIC_INLINE void P3_2_set_hwsel(uint32_t config){\r
1597     PORT3->HWSEL &= ~0x00000030UL;\r
1598     PORT3->HWSEL |= config << 4;\r
1599 }\r
1600 \r
1601 __STATIC_INLINE void P3_2_set(void){\r
1602     PORT3->OMR = 0x00000004UL;\r
1603 }\r
1604 \r
1605 __STATIC_INLINE void P3_2_reset(void){\r
1606     PORT3->OMR = 0x00040000UL;\r
1607 }\r
1608 \r
1609 __STATIC_INLINE void P3_2_toggle(void){\r
1610     PORT3->OMR = 0x00040004UL;\r
1611 }\r
1612 \r
1613 __STATIC_INLINE uint32_t P3_2_read(void){\r
1614     return(PORT3->IN & 0x00000004UL);\r
1615 }\r
1616 \r
1617 __STATIC_INLINE void P3_3_set_mode(uint8_t mode){\r
1618     PORT3->IOCR0 &= ~0xf8000000UL;\r
1619     PORT3->IOCR0 |= mode << 24;\r
1620 }\r
1621 \r
1622 __STATIC_INLINE void P3_3_set_driver_strength(uint8_t strength){\r
1623     PORT3->PDR0 &= ~0x00007000UL;\r
1624     PORT3->PDR0 |= strength << 12;\r
1625 }\r
1626 \r
1627 __STATIC_INLINE void P3_3_set_hwsel(uint32_t config){\r
1628     PORT3->HWSEL &= ~0x000000c0UL;\r
1629     PORT3->HWSEL |= config << 6;\r
1630 }\r
1631 \r
1632 __STATIC_INLINE void P3_3_set(void){\r
1633     PORT3->OMR = 0x00000008UL;\r
1634 }\r
1635 \r
1636 __STATIC_INLINE void P3_3_reset(void){\r
1637     PORT3->OMR = 0x00080000UL;\r
1638 }\r
1639 \r
1640 __STATIC_INLINE void P3_3_toggle(void){\r
1641     PORT3->OMR = 0x00080008UL;\r
1642 }\r
1643 \r
1644 __STATIC_INLINE uint32_t P3_3_read(void){\r
1645     return(PORT3->IN & 0x00000008UL);\r
1646 }\r
1647 \r
1648 __STATIC_INLINE void P3_4_set_mode(uint8_t mode){\r
1649     PORT3->IOCR4 &= ~0x000000f8UL;\r
1650     PORT3->IOCR4 |= mode << 0;\r
1651 }\r
1652 \r
1653 __STATIC_INLINE void P3_4_set_driver_strength(uint8_t strength){\r
1654     PORT3->PDR0 &= ~0x00070000UL;\r
1655     PORT3->PDR0 |= strength << 16;\r
1656 }\r
1657 \r
1658 __STATIC_INLINE void P3_4_set_hwsel(uint32_t config){\r
1659     PORT3->HWSEL &= ~0x00000300UL;\r
1660     PORT3->HWSEL |= config << 8;\r
1661 }\r
1662 \r
1663 __STATIC_INLINE void P3_4_set(void){\r
1664     PORT3->OMR = 0x00000010UL;\r
1665 }\r
1666 \r
1667 __STATIC_INLINE void P3_4_reset(void){\r
1668     PORT3->OMR = 0x00100000UL;\r
1669 }\r
1670 \r
1671 __STATIC_INLINE void P3_4_toggle(void){\r
1672     PORT3->OMR = 0x00100010UL;\r
1673 }\r
1674 \r
1675 __STATIC_INLINE uint32_t P3_4_read(void){\r
1676     return(PORT3->IN & 0x00000010UL);\r
1677 }\r
1678 \r
1679 __STATIC_INLINE void P3_5_set_mode(uint8_t mode){\r
1680     PORT3->IOCR4 &= ~0x0000f800UL;\r
1681     PORT3->IOCR4 |= mode << 8;\r
1682 }\r
1683 \r
1684 __STATIC_INLINE void P3_5_set_driver_strength(uint8_t strength){\r
1685     PORT3->PDR0 &= ~0x00700000UL;\r
1686     PORT3->PDR0 |= strength << 20;\r
1687 }\r
1688 \r
1689 __STATIC_INLINE void P3_5_set_hwsel(uint32_t config){\r
1690     PORT3->HWSEL &= ~0x00000c00UL;\r
1691     PORT3->HWSEL |= config << 10;\r
1692 }\r
1693 \r
1694 __STATIC_INLINE void P3_5_set(void){\r
1695     PORT3->OMR = 0x00000020UL;\r
1696 }\r
1697 \r
1698 __STATIC_INLINE void P3_5_reset(void){\r
1699     PORT3->OMR = 0x00200000UL;\r
1700 }\r
1701 \r
1702 __STATIC_INLINE void P3_5_toggle(void){\r
1703     PORT3->OMR = 0x00200020UL;\r
1704 }\r
1705 \r
1706 __STATIC_INLINE uint32_t P3_5_read(void){\r
1707     return(PORT3->IN & 0x00000020UL);\r
1708 }\r
1709 \r
1710 __STATIC_INLINE void P3_6_set_mode(uint8_t mode){\r
1711     PORT3->IOCR4 &= ~0x00f80000UL;\r
1712     PORT3->IOCR4 |= mode << 16;\r
1713 }\r
1714 \r
1715 __STATIC_INLINE void P3_6_set_driver_strength(uint8_t strength){\r
1716     PORT3->PDR0 &= ~0x07000000UL;\r
1717     PORT3->PDR0 |= strength << 24;\r
1718 }\r
1719 \r
1720 __STATIC_INLINE void P3_6_set_hwsel(uint32_t config){\r
1721     PORT3->HWSEL &= ~0x00003000UL;\r
1722     PORT3->HWSEL |= config << 12;\r
1723 }\r
1724 \r
1725 __STATIC_INLINE void P3_6_set(void){\r
1726     PORT3->OMR = 0x00000040UL;\r
1727 }\r
1728 \r
1729 __STATIC_INLINE void P3_6_reset(void){\r
1730     PORT3->OMR = 0x00400000UL;\r
1731 }\r
1732 \r
1733 __STATIC_INLINE void P3_6_toggle(void){\r
1734     PORT3->OMR = 0x00400040UL;\r
1735 }\r
1736 \r
1737 __STATIC_INLINE uint32_t P3_6_read(void){\r
1738     return(PORT3->IN & 0x00000040UL);\r
1739 }\r
1740 \r
1741 __STATIC_INLINE void P3_7_set_mode(uint8_t mode){\r
1742     PORT3->IOCR4 &= ~0xf8000000UL;\r
1743     PORT3->IOCR4 |= mode << 24;\r
1744 }\r
1745 \r
1746 __STATIC_INLINE void P3_7_set_driver_strength(uint8_t strength){\r
1747     PORT3->PDR0 &= ~0x70000000UL;\r
1748     PORT3->PDR0 |= strength << 28;\r
1749 }\r
1750 \r
1751 __STATIC_INLINE void P3_7_set_hwsel(uint32_t config){\r
1752     PORT3->HWSEL &= ~0x0000c000UL;\r
1753     PORT3->HWSEL |= config << 14;\r
1754 }\r
1755 \r
1756 __STATIC_INLINE void P3_7_set(void){\r
1757     PORT3->OMR = 0x00000080UL;\r
1758 }\r
1759 \r
1760 __STATIC_INLINE void P3_7_reset(void){\r
1761     PORT3->OMR = 0x00800000UL;\r
1762 }\r
1763 \r
1764 __STATIC_INLINE void P3_7_toggle(void){\r
1765     PORT3->OMR = 0x00800080UL;\r
1766 }\r
1767 \r
1768 __STATIC_INLINE uint32_t P3_7_read(void){\r
1769     return(PORT3->IN & 0x00000080UL);\r
1770 }\r
1771 \r
1772 __STATIC_INLINE void P3_8_set_mode(uint8_t mode){\r
1773     PORT3->IOCR8 &= ~0x000000f8UL;\r
1774     PORT3->IOCR8 |= mode << 0;\r
1775 }\r
1776 \r
1777 __STATIC_INLINE void P3_8_set_driver_strength(uint8_t strength){\r
1778     PORT3->PDR1 &= ~0x00000007UL;\r
1779     PORT3->PDR1 |= strength << 0;\r
1780 }\r
1781 \r
1782 __STATIC_INLINE void P3_8_set_hwsel(uint32_t config){\r
1783     PORT3->HWSEL &= ~0x00030000UL;\r
1784     PORT3->HWSEL |= config << 16;\r
1785 }\r
1786 \r
1787 __STATIC_INLINE void P3_8_set(void){\r
1788     PORT3->OMR = 0x00000100UL;\r
1789 }\r
1790 \r
1791 __STATIC_INLINE void P3_8_reset(void){\r
1792     PORT3->OMR = 0x01000000UL;\r
1793 }\r
1794 \r
1795 __STATIC_INLINE void P3_8_toggle(void){\r
1796     PORT3->OMR = 0x01000100UL;\r
1797 }\r
1798 \r
1799 __STATIC_INLINE uint32_t P3_8_read(void){\r
1800     return(PORT3->IN & 0x00000100UL);\r
1801 }\r
1802 \r
1803 __STATIC_INLINE void P3_9_set_mode(uint8_t mode){\r
1804     PORT3->IOCR8 &= ~0x0000f800UL;\r
1805     PORT3->IOCR8 |= mode << 8;\r
1806 }\r
1807 \r
1808 __STATIC_INLINE void P3_9_set_driver_strength(uint8_t strength){\r
1809     PORT3->PDR1 &= ~0x00000070UL;\r
1810     PORT3->PDR1 |= strength << 4;\r
1811 }\r
1812 \r
1813 __STATIC_INLINE void P3_9_set_hwsel(uint32_t config){\r
1814     PORT3->HWSEL &= ~0x000c0000UL;\r
1815     PORT3->HWSEL |= config << 18;\r
1816 }\r
1817 \r
1818 __STATIC_INLINE void P3_9_set(void){\r
1819     PORT3->OMR = 0x00000200UL;\r
1820 }\r
1821 \r
1822 __STATIC_INLINE void P3_9_reset(void){\r
1823     PORT3->OMR = 0x02000000UL;\r
1824 }\r
1825 \r
1826 __STATIC_INLINE void P3_9_toggle(void){\r
1827     PORT3->OMR = 0x02000200UL;\r
1828 }\r
1829 \r
1830 __STATIC_INLINE uint32_t P3_9_read(void){\r
1831     return(PORT3->IN & 0x00000200UL);\r
1832 }\r
1833 \r
1834 __STATIC_INLINE void P3_10_set_mode(uint8_t mode){\r
1835     PORT3->IOCR8 &= ~0x00f80000UL;\r
1836     PORT3->IOCR8 |= mode << 16;\r
1837 }\r
1838 \r
1839 __STATIC_INLINE void P3_10_set_driver_strength(uint8_t strength){\r
1840     PORT3->PDR1 &= ~0x00000700UL;\r
1841     PORT3->PDR1 |= strength << 8;\r
1842 }\r
1843 \r
1844 __STATIC_INLINE void P3_10_set_hwsel(uint32_t config){\r
1845     PORT3->HWSEL &= ~0x00300000UL;\r
1846     PORT3->HWSEL |= config << 20;\r
1847 }\r
1848 \r
1849 __STATIC_INLINE void P3_10_set(void){\r
1850     PORT3->OMR = 0x00000400UL;\r
1851 }\r
1852 \r
1853 __STATIC_INLINE void P3_10_reset(void){\r
1854     PORT3->OMR = 0x04000000UL;\r
1855 }\r
1856 \r
1857 __STATIC_INLINE void P3_10_toggle(void){\r
1858     PORT3->OMR = 0x04000400UL;\r
1859 }\r
1860 \r
1861 __STATIC_INLINE uint32_t P3_10_read(void){\r
1862     return(PORT3->IN & 0x00000400UL);\r
1863 }\r
1864 \r
1865 __STATIC_INLINE void P3_11_set_mode(uint8_t mode){\r
1866     PORT3->IOCR8 &= ~0xf8000000UL;\r
1867     PORT3->IOCR8 |= mode << 24;\r
1868 }\r
1869 \r
1870 __STATIC_INLINE void P3_11_set_driver_strength(uint8_t strength){\r
1871     PORT3->PDR1 &= ~0x00007000UL;\r
1872     PORT3->PDR1 |= strength << 12;\r
1873 }\r
1874 \r
1875 __STATIC_INLINE void P3_11_set_hwsel(uint32_t config){\r
1876     PORT3->HWSEL &= ~0x00c00000UL;\r
1877     PORT3->HWSEL |= config << 22;\r
1878 }\r
1879 \r
1880 __STATIC_INLINE void P3_11_set(void){\r
1881     PORT3->OMR = 0x00000800UL;\r
1882 }\r
1883 \r
1884 __STATIC_INLINE void P3_11_reset(void){\r
1885     PORT3->OMR = 0x08000000UL;\r
1886 }\r
1887 \r
1888 __STATIC_INLINE void P3_11_toggle(void){\r
1889     PORT3->OMR = 0x08000800UL;\r
1890 }\r
1891 \r
1892 __STATIC_INLINE uint32_t P3_11_read(void){\r
1893     return(PORT3->IN & 0x00000800UL);\r
1894 }\r
1895 \r
1896 __STATIC_INLINE void P3_12_set_mode(uint8_t mode){\r
1897     PORT3->IOCR12 &= ~0x000000f8UL;\r
1898     PORT3->IOCR12 |= mode << 0;\r
1899 }\r
1900 \r
1901 __STATIC_INLINE void P3_12_set_driver_strength(uint8_t strength){\r
1902     PORT3->PDR1 &= ~0x00070000UL;\r
1903     PORT3->PDR1 |= strength << 16;\r
1904 }\r
1905 \r
1906 __STATIC_INLINE void P3_12_set_hwsel(uint32_t config){\r
1907     PORT3->HWSEL &= ~0x03000000UL;\r
1908     PORT3->HWSEL |= config << 24;\r
1909 }\r
1910 \r
1911 __STATIC_INLINE void P3_12_set(void){\r
1912     PORT3->OMR = 0x00001000UL;\r
1913 }\r
1914 \r
1915 __STATIC_INLINE void P3_12_reset(void){\r
1916     PORT3->OMR = 0x10000000UL;\r
1917 }\r
1918 \r
1919 __STATIC_INLINE void P3_12_toggle(void){\r
1920     PORT3->OMR = 0x10001000UL;\r
1921 }\r
1922 \r
1923 __STATIC_INLINE uint32_t P3_12_read(void){\r
1924     return(PORT3->IN & 0x00001000UL);\r
1925 }\r
1926 \r
1927 __STATIC_INLINE void P3_13_set_mode(uint8_t mode){\r
1928     PORT3->IOCR12 &= ~0x0000f800UL;\r
1929     PORT3->IOCR12 |= mode << 8;\r
1930 }\r
1931 \r
1932 __STATIC_INLINE void P3_13_set_driver_strength(uint8_t strength){\r
1933     PORT3->PDR1 &= ~0x00700000UL;\r
1934     PORT3->PDR1 |= strength << 20;\r
1935 }\r
1936 \r
1937 __STATIC_INLINE void P3_13_set_hwsel(uint32_t config){\r
1938     PORT3->HWSEL &= ~0x0c000000UL;\r
1939     PORT3->HWSEL |= config << 26;\r
1940 }\r
1941 \r
1942 __STATIC_INLINE void P3_13_set(void){\r
1943     PORT3->OMR = 0x00002000UL;\r
1944 }\r
1945 \r
1946 __STATIC_INLINE void P3_13_reset(void){\r
1947     PORT3->OMR = 0x20000000UL;\r
1948 }\r
1949 \r
1950 __STATIC_INLINE void P3_13_toggle(void){\r
1951     PORT3->OMR = 0x20002000UL;\r
1952 }\r
1953 \r
1954 __STATIC_INLINE uint32_t P3_13_read(void){\r
1955     return(PORT3->IN & 0x00002000UL);\r
1956 }\r
1957 \r
1958 __STATIC_INLINE void P3_14_set_mode(uint8_t mode){\r
1959     PORT3->IOCR12 &= ~0x00f80000UL;\r
1960     PORT3->IOCR12 |= mode << 16;\r
1961 }\r
1962 \r
1963 __STATIC_INLINE void P3_14_set_driver_strength(uint8_t strength){\r
1964     PORT3->PDR1 &= ~0x07000000UL;\r
1965     PORT3->PDR1 |= strength << 24;\r
1966 }\r
1967 \r
1968 __STATIC_INLINE void P3_14_set_hwsel(uint32_t config){\r
1969     PORT3->HWSEL &= ~0x30000000UL;\r
1970     PORT3->HWSEL |= config << 28;\r
1971 }\r
1972 \r
1973 __STATIC_INLINE void P3_14_set(void){\r
1974     PORT3->OMR = 0x00004000UL;\r
1975 }\r
1976 \r
1977 __STATIC_INLINE void P3_14_reset(void){\r
1978     PORT3->OMR = 0x40000000UL;\r
1979 }\r
1980 \r
1981 __STATIC_INLINE void P3_14_toggle(void){\r
1982     PORT3->OMR = 0x40004000UL;\r
1983 }\r
1984 \r
1985 __STATIC_INLINE uint32_t P3_14_read(void){\r
1986     return(PORT3->IN & 0x00004000UL);\r
1987 }\r
1988 \r
1989 __STATIC_INLINE void P3_15_set_mode(uint8_t mode){\r
1990     PORT3->IOCR12 &= ~0xf8000000UL;\r
1991     PORT3->IOCR12 |= mode << 24;\r
1992 }\r
1993 \r
1994 __STATIC_INLINE void P3_15_set_driver_strength(uint8_t strength){\r
1995     PORT3->PDR1 &= ~0x70000000UL;\r
1996     PORT3->PDR1 |= strength << 28;\r
1997 }\r
1998 \r
1999 __STATIC_INLINE void P3_15_set_hwsel(uint32_t config){\r
2000     PORT3->HWSEL &= ~0xc0000000UL;\r
2001     PORT3->HWSEL |= config << 30;\r
2002 }\r
2003 \r
2004 __STATIC_INLINE void P3_15_set(void){\r
2005     PORT3->OMR = 0x00008000UL;\r
2006 }\r
2007 \r
2008 __STATIC_INLINE void P3_15_reset(void){\r
2009     PORT3->OMR = 0x80000000UL;\r
2010 }\r
2011 \r
2012 __STATIC_INLINE void P3_15_toggle(void){\r
2013     PORT3->OMR = 0x80008000UL;\r
2014 }\r
2015 \r
2016 __STATIC_INLINE uint32_t P3_15_read(void){\r
2017     return(PORT3->IN & 0x00008000UL);\r
2018 }\r
2019 \r
2020 __STATIC_INLINE void P4_0_set_mode(uint8_t mode){\r
2021     PORT4->IOCR0 &= ~0x000000f8UL;\r
2022     PORT4->IOCR0 |= mode << 0;\r
2023 }\r
2024 \r
2025 __STATIC_INLINE void P4_0_set_driver_strength(uint8_t strength){\r
2026     PORT4->PDR0 &= ~0x00000007UL;\r
2027     PORT4->PDR0 |= strength << 0;\r
2028 }\r
2029 \r
2030 __STATIC_INLINE void P4_0_set_hwsel(uint32_t config){\r
2031     PORT4->HWSEL &= ~0x00000003UL;\r
2032     PORT4->HWSEL |= config << 0;\r
2033 }\r
2034 \r
2035 __STATIC_INLINE void P4_0_set(void){\r
2036     PORT4->OMR = 0x00000001UL;\r
2037 }\r
2038 \r
2039 __STATIC_INLINE void P4_0_reset(void){\r
2040     PORT4->OMR = 0x00010000UL;\r
2041 }\r
2042 \r
2043 __STATIC_INLINE void P4_0_toggle(void){\r
2044     PORT4->OMR = 0x00010001UL;\r
2045 }\r
2046 \r
2047 __STATIC_INLINE uint32_t P4_0_read(void){\r
2048     return(PORT4->IN & 0x00000001UL);\r
2049 }\r
2050 \r
2051 __STATIC_INLINE void P4_1_set_mode(uint8_t mode){\r
2052     PORT4->IOCR0 &= ~0x0000f800UL;\r
2053     PORT4->IOCR0 |= mode << 8;\r
2054 }\r
2055 \r
2056 __STATIC_INLINE void P4_1_set_driver_strength(uint8_t strength){\r
2057     PORT4->PDR0 &= ~0x00000070UL;\r
2058     PORT4->PDR0 |= strength << 4;\r
2059 }\r
2060 \r
2061 __STATIC_INLINE void P4_1_set_hwsel(uint32_t config){\r
2062     PORT4->HWSEL &= ~0x0000000cUL;\r
2063     PORT4->HWSEL |= config << 2;\r
2064 }\r
2065 \r
2066 __STATIC_INLINE void P4_1_set(void){\r
2067     PORT4->OMR = 0x00000002UL;\r
2068 }\r
2069 \r
2070 __STATIC_INLINE void P4_1_reset(void){\r
2071     PORT4->OMR = 0x00020000UL;\r
2072 }\r
2073 \r
2074 __STATIC_INLINE void P4_1_toggle(void){\r
2075     PORT4->OMR = 0x00020002UL;\r
2076 }\r
2077 \r
2078 __STATIC_INLINE uint32_t P4_1_read(void){\r
2079     return(PORT4->IN & 0x00000002UL);\r
2080 }\r
2081 \r
2082 __STATIC_INLINE void P4_2_set_mode(uint8_t mode){\r
2083     PORT4->IOCR0 &= ~0x00f80000UL;\r
2084     PORT4->IOCR0 |= mode << 16;\r
2085 }\r
2086 \r
2087 __STATIC_INLINE void P4_2_set_driver_strength(uint8_t strength){\r
2088     PORT4->PDR0 &= ~0x00000700UL;\r
2089     PORT4->PDR0 |= strength << 8;\r
2090 }\r
2091 \r
2092 __STATIC_INLINE void P4_2_set_hwsel(uint32_t config){\r
2093     PORT4->HWSEL &= ~0x00000030UL;\r
2094     PORT4->HWSEL |= config << 4;\r
2095 }\r
2096 \r
2097 __STATIC_INLINE void P4_2_set(void){\r
2098     PORT4->OMR = 0x00000004UL;\r
2099 }\r
2100 \r
2101 __STATIC_INLINE void P4_2_reset(void){\r
2102     PORT4->OMR = 0x00040000UL;\r
2103 }\r
2104 \r
2105 __STATIC_INLINE void P4_2_toggle(void){\r
2106     PORT4->OMR = 0x00040004UL;\r
2107 }\r
2108 \r
2109 __STATIC_INLINE uint32_t P4_2_read(void){\r
2110     return(PORT4->IN & 0x00000004UL);\r
2111 }\r
2112 \r
2113 __STATIC_INLINE void P4_3_set_mode(uint8_t mode){\r
2114     PORT4->IOCR0 &= ~0xf8000000UL;\r
2115     PORT4->IOCR0 |= mode << 24;\r
2116 }\r
2117 \r
2118 __STATIC_INLINE void P4_3_set_driver_strength(uint8_t strength){\r
2119     PORT4->PDR0 &= ~0x00007000UL;\r
2120     PORT4->PDR0 |= strength << 12;\r
2121 }\r
2122 \r
2123 __STATIC_INLINE void P4_3_set_hwsel(uint32_t config){\r
2124     PORT4->HWSEL &= ~0x000000c0UL;\r
2125     PORT4->HWSEL |= config << 6;\r
2126 }\r
2127 \r
2128 __STATIC_INLINE void P4_3_set(void){\r
2129     PORT4->OMR = 0x00000008UL;\r
2130 }\r
2131 \r
2132 __STATIC_INLINE void P4_3_reset(void){\r
2133     PORT4->OMR = 0x00080000UL;\r
2134 }\r
2135 \r
2136 __STATIC_INLINE void P4_3_toggle(void){\r
2137     PORT4->OMR = 0x00080008UL;\r
2138 }\r
2139 \r
2140 __STATIC_INLINE uint32_t P4_3_read(void){\r
2141     return(PORT4->IN & 0x00000008UL);\r
2142 }\r
2143 \r
2144 __STATIC_INLINE void P4_4_set_mode(uint8_t mode){\r
2145     PORT4->IOCR4 &= ~0x000000f8UL;\r
2146     PORT4->IOCR4 |= mode << 0;\r
2147 }\r
2148 \r
2149 __STATIC_INLINE void P4_4_set_driver_strength(uint8_t strength){\r
2150     PORT4->PDR0 &= ~0x00070000UL;\r
2151     PORT4->PDR0 |= strength << 16;\r
2152 }\r
2153 \r
2154 __STATIC_INLINE void P4_4_set_hwsel(uint32_t config){\r
2155     PORT4->HWSEL &= ~0x00000300UL;\r
2156     PORT4->HWSEL |= config << 8;\r
2157 }\r
2158 \r
2159 __STATIC_INLINE void P4_4_set(void){\r
2160     PORT4->OMR = 0x00000010UL;\r
2161 }\r
2162 \r
2163 __STATIC_INLINE void P4_4_reset(void){\r
2164     PORT4->OMR = 0x00100000UL;\r
2165 }\r
2166 \r
2167 __STATIC_INLINE void P4_4_toggle(void){\r
2168     PORT4->OMR = 0x00100010UL;\r
2169 }\r
2170 \r
2171 __STATIC_INLINE uint32_t P4_4_read(void){\r
2172     return(PORT4->IN & 0x00000010UL);\r
2173 }\r
2174 \r
2175 __STATIC_INLINE void P4_5_set_mode(uint8_t mode){\r
2176     PORT4->IOCR4 &= ~0x0000f800UL;\r
2177     PORT4->IOCR4 |= mode << 8;\r
2178 }\r
2179 \r
2180 __STATIC_INLINE void P4_5_set_driver_strength(uint8_t strength){\r
2181     PORT4->PDR0 &= ~0x00700000UL;\r
2182     PORT4->PDR0 |= strength << 20;\r
2183 }\r
2184 \r
2185 __STATIC_INLINE void P4_5_set_hwsel(uint32_t config){\r
2186     PORT4->HWSEL &= ~0x00000c00UL;\r
2187     PORT4->HWSEL |= config << 10;\r
2188 }\r
2189 \r
2190 __STATIC_INLINE void P4_5_set(void){\r
2191     PORT4->OMR = 0x00000020UL;\r
2192 }\r
2193 \r
2194 __STATIC_INLINE void P4_5_reset(void){\r
2195     PORT4->OMR = 0x00200000UL;\r
2196 }\r
2197 \r
2198 __STATIC_INLINE void P4_5_toggle(void){\r
2199     PORT4->OMR = 0x00200020UL;\r
2200 }\r
2201 \r
2202 __STATIC_INLINE uint32_t P4_5_read(void){\r
2203     return(PORT4->IN & 0x00000020UL);\r
2204 }\r
2205 \r
2206 __STATIC_INLINE void P4_6_set_mode(uint8_t mode){\r
2207     PORT4->IOCR4 &= ~0x00f80000UL;\r
2208     PORT4->IOCR4 |= mode << 16;\r
2209 }\r
2210 \r
2211 __STATIC_INLINE void P4_6_set_driver_strength(uint8_t strength){\r
2212     PORT4->PDR0 &= ~0x07000000UL;\r
2213     PORT4->PDR0 |= strength << 24;\r
2214 }\r
2215 \r
2216 __STATIC_INLINE void P4_6_set_hwsel(uint32_t config){\r
2217     PORT4->HWSEL &= ~0x00003000UL;\r
2218     PORT4->HWSEL |= config << 12;\r
2219 }\r
2220 \r
2221 __STATIC_INLINE void P4_6_set(void){\r
2222     PORT4->OMR = 0x00000040UL;\r
2223 }\r
2224 \r
2225 __STATIC_INLINE void P4_6_reset(void){\r
2226     PORT4->OMR = 0x00400000UL;\r
2227 }\r
2228 \r
2229 __STATIC_INLINE void P4_6_toggle(void){\r
2230     PORT4->OMR = 0x00400040UL;\r
2231 }\r
2232 \r
2233 __STATIC_INLINE uint32_t P4_6_read(void){\r
2234     return(PORT4->IN & 0x00000040UL);\r
2235 }\r
2236 \r
2237 __STATIC_INLINE void P4_7_set_mode(uint8_t mode){\r
2238     PORT4->IOCR4 &= ~0xf8000000UL;\r
2239     PORT4->IOCR4 |= mode << 24;\r
2240 }\r
2241 \r
2242 __STATIC_INLINE void P4_7_set_driver_strength(uint8_t strength){\r
2243     PORT4->PDR0 &= ~0x70000000UL;\r
2244     PORT4->PDR0 |= strength << 28;\r
2245 }\r
2246 \r
2247 __STATIC_INLINE void P4_7_set_hwsel(uint32_t config){\r
2248     PORT4->HWSEL &= ~0x0000c000UL;\r
2249     PORT4->HWSEL |= config << 14;\r
2250 }\r
2251 \r
2252 __STATIC_INLINE void P4_7_set(void){\r
2253     PORT4->OMR = 0x00000080UL;\r
2254 }\r
2255 \r
2256 __STATIC_INLINE void P4_7_reset(void){\r
2257     PORT4->OMR = 0x00800000UL;\r
2258 }\r
2259 \r
2260 __STATIC_INLINE void P4_7_toggle(void){\r
2261     PORT4->OMR = 0x00800080UL;\r
2262 }\r
2263 \r
2264 __STATIC_INLINE uint32_t P4_7_read(void){\r
2265     return(PORT4->IN & 0x00000080UL);\r
2266 }\r
2267 \r
2268 __STATIC_INLINE void P5_0_set_mode(uint8_t mode){\r
2269     PORT5->IOCR0 &= ~0x000000f8UL;\r
2270     PORT5->IOCR0 |= mode << 0;\r
2271 }\r
2272 \r
2273 __STATIC_INLINE void P5_0_set_driver_strength(uint8_t strength){\r
2274     PORT5->PDR0 &= ~0x00000007UL;\r
2275     PORT5->PDR0 |= strength << 0;\r
2276 }\r
2277 \r
2278 __STATIC_INLINE void P5_0_set_hwsel(uint32_t config){\r
2279     PORT5->HWSEL &= ~0x00000003UL;\r
2280     PORT5->HWSEL |= config << 0;\r
2281 }\r
2282 \r
2283 __STATIC_INLINE void P5_0_set(void){\r
2284     PORT5->OMR = 0x00000001UL;\r
2285 }\r
2286 \r
2287 __STATIC_INLINE void P5_0_reset(void){\r
2288     PORT5->OMR = 0x00010000UL;\r
2289 }\r
2290 \r
2291 __STATIC_INLINE void P5_0_toggle(void){\r
2292     PORT5->OMR = 0x00010001UL;\r
2293 }\r
2294 \r
2295 __STATIC_INLINE uint32_t P5_0_read(void){\r
2296     return(PORT5->IN & 0x00000001UL);\r
2297 }\r
2298 \r
2299 __STATIC_INLINE void P5_1_set_mode(uint8_t mode){\r
2300     PORT5->IOCR0 &= ~0x0000f800UL;\r
2301     PORT5->IOCR0 |= mode << 8;\r
2302 }\r
2303 \r
2304 __STATIC_INLINE void P5_1_set_driver_strength(uint8_t strength){\r
2305     PORT5->PDR0 &= ~0x00000070UL;\r
2306     PORT5->PDR0 |= strength << 4;\r
2307 }\r
2308 \r
2309 __STATIC_INLINE void P5_1_set_hwsel(uint32_t config){\r
2310     PORT5->HWSEL &= ~0x0000000cUL;\r
2311     PORT5->HWSEL |= config << 2;\r
2312 }\r
2313 \r
2314 __STATIC_INLINE void P5_1_set(void){\r
2315     PORT5->OMR = 0x00000002UL;\r
2316 }\r
2317 \r
2318 __STATIC_INLINE void P5_1_reset(void){\r
2319     PORT5->OMR = 0x00020000UL;\r
2320 }\r
2321 \r
2322 __STATIC_INLINE void P5_1_toggle(void){\r
2323     PORT5->OMR = 0x00020002UL;\r
2324 }\r
2325 \r
2326 __STATIC_INLINE uint32_t P5_1_read(void){\r
2327     return(PORT5->IN & 0x00000002UL);\r
2328 }\r
2329 \r
2330 __STATIC_INLINE void P5_2_set_mode(uint8_t mode){\r
2331     PORT5->IOCR0 &= ~0x00f80000UL;\r
2332     PORT5->IOCR0 |= mode << 16;\r
2333 }\r
2334 \r
2335 __STATIC_INLINE void P5_2_set_driver_strength(uint8_t strength){\r
2336     PORT5->PDR0 &= ~0x00000700UL;\r
2337     PORT5->PDR0 |= strength << 8;\r
2338 }\r
2339 \r
2340 __STATIC_INLINE void P5_2_set_hwsel(uint32_t config){\r
2341     PORT5->HWSEL &= ~0x00000030UL;\r
2342     PORT5->HWSEL |= config << 4;\r
2343 }\r
2344 \r
2345 __STATIC_INLINE void P5_2_set(void){\r
2346     PORT5->OMR = 0x00000004UL;\r
2347 }\r
2348 \r
2349 __STATIC_INLINE void P5_2_reset(void){\r
2350     PORT5->OMR = 0x00040000UL;\r
2351 }\r
2352 \r
2353 __STATIC_INLINE void P5_2_toggle(void){\r
2354     PORT5->OMR = 0x00040004UL;\r
2355 }\r
2356 \r
2357 __STATIC_INLINE uint32_t P5_2_read(void){\r
2358     return(PORT5->IN & 0x00000004UL);\r
2359 }\r
2360 \r
2361 __STATIC_INLINE void P5_3_set_mode(uint8_t mode){\r
2362     PORT5->IOCR0 &= ~0xf8000000UL;\r
2363     PORT5->IOCR0 |= mode << 24;\r
2364 }\r
2365 \r
2366 __STATIC_INLINE void P5_3_set_driver_strength(uint8_t strength){\r
2367     PORT5->PDR0 &= ~0x00007000UL;\r
2368     PORT5->PDR0 |= strength << 12;\r
2369 }\r
2370 \r
2371 __STATIC_INLINE void P5_3_set_hwsel(uint32_t config){\r
2372     PORT5->HWSEL &= ~0x000000c0UL;\r
2373     PORT5->HWSEL |= config << 6;\r
2374 }\r
2375 \r
2376 __STATIC_INLINE void P5_3_set(void){\r
2377     PORT5->OMR = 0x00000008UL;\r
2378 }\r
2379 \r
2380 __STATIC_INLINE void P5_3_reset(void){\r
2381     PORT5->OMR = 0x00080000UL;\r
2382 }\r
2383 \r
2384 __STATIC_INLINE void P5_3_toggle(void){\r
2385     PORT5->OMR = 0x00080008UL;\r
2386 }\r
2387 \r
2388 __STATIC_INLINE uint32_t P5_3_read(void){\r
2389     return(PORT5->IN & 0x00000008UL);\r
2390 }\r
2391 \r
2392 __STATIC_INLINE void P5_4_set_mode(uint8_t mode){\r
2393     PORT5->IOCR4 &= ~0x000000f8UL;\r
2394     PORT5->IOCR4 |= mode << 0;\r
2395 }\r
2396 \r
2397 __STATIC_INLINE void P5_4_set_driver_strength(uint8_t strength){\r
2398     PORT5->PDR0 &= ~0x00070000UL;\r
2399     PORT5->PDR0 |= strength << 16;\r
2400 }\r
2401 \r
2402 __STATIC_INLINE void P5_4_set_hwsel(uint32_t config){\r
2403     PORT5->HWSEL &= ~0x00000300UL;\r
2404     PORT5->HWSEL |= config << 8;\r
2405 }\r
2406 \r
2407 __STATIC_INLINE void P5_4_set(void){\r
2408     PORT5->OMR = 0x00000010UL;\r
2409 }\r
2410 \r
2411 __STATIC_INLINE void P5_4_reset(void){\r
2412     PORT5->OMR = 0x00100000UL;\r
2413 }\r
2414 \r
2415 __STATIC_INLINE void P5_4_toggle(void){\r
2416     PORT5->OMR = 0x00100010UL;\r
2417 }\r
2418 \r
2419 __STATIC_INLINE uint32_t P5_4_read(void){\r
2420     return(PORT5->IN & 0x00000010UL);\r
2421 }\r
2422 \r
2423 __STATIC_INLINE void P5_5_set_mode(uint8_t mode){\r
2424     PORT5->IOCR4 &= ~0x0000f800UL;\r
2425     PORT5->IOCR4 |= mode << 8;\r
2426 }\r
2427 \r
2428 __STATIC_INLINE void P5_5_set_driver_strength(uint8_t strength){\r
2429     PORT5->PDR0 &= ~0x00700000UL;\r
2430     PORT5->PDR0 |= strength << 20;\r
2431 }\r
2432 \r
2433 __STATIC_INLINE void P5_5_set_hwsel(uint32_t config){\r
2434     PORT5->HWSEL &= ~0x00000c00UL;\r
2435     PORT5->HWSEL |= config << 10;\r
2436 }\r
2437 \r
2438 __STATIC_INLINE void P5_5_set(void){\r
2439     PORT5->OMR = 0x00000020UL;\r
2440 }\r
2441 \r
2442 __STATIC_INLINE void P5_5_reset(void){\r
2443     PORT5->OMR = 0x00200000UL;\r
2444 }\r
2445 \r
2446 __STATIC_INLINE void P5_5_toggle(void){\r
2447     PORT5->OMR = 0x00200020UL;\r
2448 }\r
2449 \r
2450 __STATIC_INLINE uint32_t P5_5_read(void){\r
2451     return(PORT5->IN & 0x00000020UL);\r
2452 }\r
2453 \r
2454 __STATIC_INLINE void P5_6_set_mode(uint8_t mode){\r
2455     PORT5->IOCR4 &= ~0x00f80000UL;\r
2456     PORT5->IOCR4 |= mode << 16;\r
2457 }\r
2458 \r
2459 __STATIC_INLINE void P5_6_set_driver_strength(uint8_t strength){\r
2460     PORT5->PDR0 &= ~0x07000000UL;\r
2461     PORT5->PDR0 |= strength << 24;\r
2462 }\r
2463 \r
2464 __STATIC_INLINE void P5_6_set_hwsel(uint32_t config){\r
2465     PORT5->HWSEL &= ~0x00003000UL;\r
2466     PORT5->HWSEL |= config << 12;\r
2467 }\r
2468 \r
2469 __STATIC_INLINE void P5_6_set(void){\r
2470     PORT5->OMR = 0x00000040UL;\r
2471 }\r
2472 \r
2473 __STATIC_INLINE void P5_6_reset(void){\r
2474     PORT5->OMR = 0x00400000UL;\r
2475 }\r
2476 \r
2477 __STATIC_INLINE void P5_6_toggle(void){\r
2478     PORT5->OMR = 0x00400040UL;\r
2479 }\r
2480 \r
2481 __STATIC_INLINE uint32_t P5_6_read(void){\r
2482     return(PORT5->IN & 0x00000040UL);\r
2483 }\r
2484 \r
2485 __STATIC_INLINE void P5_7_set_mode(uint8_t mode){\r
2486     PORT5->IOCR4 &= ~0xf8000000UL;\r
2487     PORT5->IOCR4 |= mode << 24;\r
2488 }\r
2489 \r
2490 __STATIC_INLINE void P5_7_set_driver_strength(uint8_t strength){\r
2491     PORT5->PDR0 &= ~0x70000000UL;\r
2492     PORT5->PDR0 |= strength << 28;\r
2493 }\r
2494 \r
2495 __STATIC_INLINE void P5_7_set_hwsel(uint32_t config){\r
2496     PORT5->HWSEL &= ~0x0000c000UL;\r
2497     PORT5->HWSEL |= config << 14;\r
2498 }\r
2499 \r
2500 __STATIC_INLINE void P5_7_set(void){\r
2501     PORT5->OMR = 0x00000080UL;\r
2502 }\r
2503 \r
2504 __STATIC_INLINE void P5_7_reset(void){\r
2505     PORT5->OMR = 0x00800000UL;\r
2506 }\r
2507 \r
2508 __STATIC_INLINE void P5_7_toggle(void){\r
2509     PORT5->OMR = 0x00800080UL;\r
2510 }\r
2511 \r
2512 __STATIC_INLINE uint32_t P5_7_read(void){\r
2513     return(PORT5->IN & 0x00000080UL);\r
2514 }\r
2515 \r
2516 __STATIC_INLINE void P5_8_set_mode(uint8_t mode){\r
2517     PORT5->IOCR8 &= ~0x000000f8UL;\r
2518     PORT5->IOCR8 |= mode << 0;\r
2519 }\r
2520 \r
2521 __STATIC_INLINE void P5_8_set_driver_strength(uint8_t strength){\r
2522     PORT5->PDR1 &= ~0x00000007UL;\r
2523     PORT5->PDR1 |= strength << 0;\r
2524 }\r
2525 \r
2526 __STATIC_INLINE void P5_8_set_hwsel(uint32_t config){\r
2527     PORT5->HWSEL &= ~0x00030000UL;\r
2528     PORT5->HWSEL |= config << 16;\r
2529 }\r
2530 \r
2531 __STATIC_INLINE void P5_8_set(void){\r
2532     PORT5->OMR = 0x00000100UL;\r
2533 }\r
2534 \r
2535 __STATIC_INLINE void P5_8_reset(void){\r
2536     PORT5->OMR = 0x01000000UL;\r
2537 }\r
2538 \r
2539 __STATIC_INLINE void P5_8_toggle(void){\r
2540     PORT5->OMR = 0x01000100UL;\r
2541 }\r
2542 \r
2543 __STATIC_INLINE uint32_t P5_8_read(void){\r
2544     return(PORT5->IN & 0x00000100UL);\r
2545 }\r
2546 \r
2547 __STATIC_INLINE void P5_9_set_mode(uint8_t mode){\r
2548     PORT5->IOCR8 &= ~0x0000f800UL;\r
2549     PORT5->IOCR8 |= mode << 8;\r
2550 }\r
2551 \r
2552 __STATIC_INLINE void P5_9_set_driver_strength(uint8_t strength){\r
2553     PORT5->PDR1 &= ~0x00000070UL;\r
2554     PORT5->PDR1 |= strength << 4;\r
2555 }\r
2556 \r
2557 __STATIC_INLINE void P5_9_set_hwsel(uint32_t config){\r
2558     PORT5->HWSEL &= ~0x000c0000UL;\r
2559     PORT5->HWSEL |= config << 18;\r
2560 }\r
2561 \r
2562 __STATIC_INLINE void P5_9_set(void){\r
2563     PORT5->OMR = 0x00000200UL;\r
2564 }\r
2565 \r
2566 __STATIC_INLINE void P5_9_reset(void){\r
2567     PORT5->OMR = 0x02000000UL;\r
2568 }\r
2569 \r
2570 __STATIC_INLINE void P5_9_toggle(void){\r
2571     PORT5->OMR = 0x02000200UL;\r
2572 }\r
2573 \r
2574 __STATIC_INLINE uint32_t P5_9_read(void){\r
2575     return(PORT5->IN & 0x00000200UL);\r
2576 }\r
2577 \r
2578 __STATIC_INLINE void P5_10_set_mode(uint8_t mode){\r
2579     PORT5->IOCR8 &= ~0x00f80000UL;\r
2580     PORT5->IOCR8 |= mode << 16;\r
2581 }\r
2582 \r
2583 __STATIC_INLINE void P5_10_set_driver_strength(uint8_t strength){\r
2584     PORT5->PDR1 &= ~0x00000700UL;\r
2585     PORT5->PDR1 |= strength << 8;\r
2586 }\r
2587 \r
2588 __STATIC_INLINE void P5_10_set_hwsel(uint32_t config){\r
2589     PORT5->HWSEL &= ~0x00300000UL;\r
2590     PORT5->HWSEL |= config << 20;\r
2591 }\r
2592 \r
2593 __STATIC_INLINE void P5_10_set(void){\r
2594     PORT5->OMR = 0x00000400UL;\r
2595 }\r
2596 \r
2597 __STATIC_INLINE void P5_10_reset(void){\r
2598     PORT5->OMR = 0x04000000UL;\r
2599 }\r
2600 \r
2601 __STATIC_INLINE void P5_10_toggle(void){\r
2602     PORT5->OMR = 0x04000400UL;\r
2603 }\r
2604 \r
2605 __STATIC_INLINE uint32_t P5_10_read(void){\r
2606     return(PORT5->IN & 0x00000400UL);\r
2607 }\r
2608 \r
2609 __STATIC_INLINE void P5_11_set_mode(uint8_t mode){\r
2610     PORT5->IOCR8 &= ~0xf8000000UL;\r
2611     PORT5->IOCR8 |= mode << 24;\r
2612 }\r
2613 \r
2614 __STATIC_INLINE void P5_11_set_driver_strength(uint8_t strength){\r
2615     PORT5->PDR1 &= ~0x00007000UL;\r
2616     PORT5->PDR1 |= strength << 12;\r
2617 }\r
2618 \r
2619 __STATIC_INLINE void P5_11_set_hwsel(uint32_t config){\r
2620     PORT5->HWSEL &= ~0x00c00000UL;\r
2621     PORT5->HWSEL |= config << 22;\r
2622 }\r
2623 \r
2624 __STATIC_INLINE void P5_11_set(void){\r
2625     PORT5->OMR = 0x00000800UL;\r
2626 }\r
2627 \r
2628 __STATIC_INLINE void P5_11_reset(void){\r
2629     PORT5->OMR = 0x08000000UL;\r
2630 }\r
2631 \r
2632 __STATIC_INLINE void P5_11_toggle(void){\r
2633     PORT5->OMR = 0x08000800UL;\r
2634 }\r
2635 \r
2636 __STATIC_INLINE uint32_t P5_11_read(void){\r
2637     return(PORT5->IN & 0x00000800UL);\r
2638 }\r
2639 \r
2640 __STATIC_INLINE void P6_0_set_mode(uint8_t mode){\r
2641     PORT6->IOCR0 &= ~0x000000f8UL;\r
2642     PORT6->IOCR0 |= mode << 0;\r
2643 }\r
2644 \r
2645 __STATIC_INLINE void P6_0_set_driver_strength(uint8_t strength){\r
2646     PORT6->PDR0 &= ~0x00000007UL;\r
2647     PORT6->PDR0 |= strength << 0;\r
2648 }\r
2649 \r
2650 __STATIC_INLINE void P6_0_set_hwsel(uint32_t config){\r
2651     PORT6->HWSEL &= ~0x00000003UL;\r
2652     PORT6->HWSEL |= config << 0;\r
2653 }\r
2654 \r
2655 __STATIC_INLINE void P6_0_set(void){\r
2656     PORT6->OMR = 0x00000001UL;\r
2657 }\r
2658 \r
2659 __STATIC_INLINE void P6_0_reset(void){\r
2660     PORT6->OMR = 0x00010000UL;\r
2661 }\r
2662 \r
2663 __STATIC_INLINE void P6_0_toggle(void){\r
2664     PORT6->OMR = 0x00010001UL;\r
2665 }\r
2666 \r
2667 __STATIC_INLINE uint32_t P6_0_read(void){\r
2668     return(PORT6->IN & 0x00000001UL);\r
2669 }\r
2670 \r
2671 __STATIC_INLINE void P6_1_set_mode(uint8_t mode){\r
2672     PORT6->IOCR0 &= ~0x0000f800UL;\r
2673     PORT6->IOCR0 |= mode << 8;\r
2674 }\r
2675 \r
2676 __STATIC_INLINE void P6_1_set_driver_strength(uint8_t strength){\r
2677     PORT6->PDR0 &= ~0x00000070UL;\r
2678     PORT6->PDR0 |= strength << 4;\r
2679 }\r
2680 \r
2681 __STATIC_INLINE void P6_1_set_hwsel(uint32_t config){\r
2682     PORT6->HWSEL &= ~0x0000000cUL;\r
2683     PORT6->HWSEL |= config << 2;\r
2684 }\r
2685 \r
2686 __STATIC_INLINE void P6_1_set(void){\r
2687     PORT6->OMR = 0x00000002UL;\r
2688 }\r
2689 \r
2690 __STATIC_INLINE void P6_1_reset(void){\r
2691     PORT6->OMR = 0x00020000UL;\r
2692 }\r
2693 \r
2694 __STATIC_INLINE void P6_1_toggle(void){\r
2695     PORT6->OMR = 0x00020002UL;\r
2696 }\r
2697 \r
2698 __STATIC_INLINE uint32_t P6_1_read(void){\r
2699     return(PORT6->IN & 0x00000002UL);\r
2700 }\r
2701 \r
2702 __STATIC_INLINE void P6_2_set_mode(uint8_t mode){\r
2703     PORT6->IOCR0 &= ~0x00f80000UL;\r
2704     PORT6->IOCR0 |= mode << 16;\r
2705 }\r
2706 \r
2707 __STATIC_INLINE void P6_2_set_driver_strength(uint8_t strength){\r
2708     PORT6->PDR0 &= ~0x00000700UL;\r
2709     PORT6->PDR0 |= strength << 8;\r
2710 }\r
2711 \r
2712 __STATIC_INLINE void P6_2_set_hwsel(uint32_t config){\r
2713     PORT6->HWSEL &= ~0x00000030UL;\r
2714     PORT6->HWSEL |= config << 4;\r
2715 }\r
2716 \r
2717 __STATIC_INLINE void P6_2_set(void){\r
2718     PORT6->OMR = 0x00000004UL;\r
2719 }\r
2720 \r
2721 __STATIC_INLINE void P6_2_reset(void){\r
2722     PORT6->OMR = 0x00040000UL;\r
2723 }\r
2724 \r
2725 __STATIC_INLINE void P6_2_toggle(void){\r
2726     PORT6->OMR = 0x00040004UL;\r
2727 }\r
2728 \r
2729 __STATIC_INLINE uint32_t P6_2_read(void){\r
2730     return(PORT6->IN & 0x00000004UL);\r
2731 }\r
2732 \r
2733 __STATIC_INLINE void P6_3_set_mode(uint8_t mode){\r
2734     PORT6->IOCR0 &= ~0xf8000000UL;\r
2735     PORT6->IOCR0 |= mode << 24;\r
2736 }\r
2737 \r
2738 __STATIC_INLINE void P6_3_set_driver_strength(uint8_t strength){\r
2739     PORT6->PDR0 &= ~0x00007000UL;\r
2740     PORT6->PDR0 |= strength << 12;\r
2741 }\r
2742 \r
2743 __STATIC_INLINE void P6_3_set_hwsel(uint32_t config){\r
2744     PORT6->HWSEL &= ~0x000000c0UL;\r
2745     PORT6->HWSEL |= config << 6;\r
2746 }\r
2747 \r
2748 __STATIC_INLINE void P6_3_set(void){\r
2749     PORT6->OMR = 0x00000008UL;\r
2750 }\r
2751 \r
2752 __STATIC_INLINE void P6_3_reset(void){\r
2753     PORT6->OMR = 0x00080000UL;\r
2754 }\r
2755 \r
2756 __STATIC_INLINE void P6_3_toggle(void){\r
2757     PORT6->OMR = 0x00080008UL;\r
2758 }\r
2759 \r
2760 __STATIC_INLINE uint32_t P6_3_read(void){\r
2761     return(PORT6->IN & 0x00000008UL);\r
2762 }\r
2763 \r
2764 __STATIC_INLINE void P6_4_set_mode(uint8_t mode){\r
2765     PORT6->IOCR4 &= ~0x000000f8UL;\r
2766     PORT6->IOCR4 |= mode << 0;\r
2767 }\r
2768 \r
2769 __STATIC_INLINE void P6_4_set_driver_strength(uint8_t strength){\r
2770     PORT6->PDR0 &= ~0x00070000UL;\r
2771     PORT6->PDR0 |= strength << 16;\r
2772 }\r
2773 \r
2774 __STATIC_INLINE void P6_4_set_hwsel(uint32_t config){\r
2775     PORT6->HWSEL &= ~0x00000300UL;\r
2776     PORT6->HWSEL |= config << 8;\r
2777 }\r
2778 \r
2779 __STATIC_INLINE void P6_4_set(void){\r
2780     PORT6->OMR = 0x00000010UL;\r
2781 }\r
2782 \r
2783 __STATIC_INLINE void P6_4_reset(void){\r
2784     PORT6->OMR = 0x00100000UL;\r
2785 }\r
2786 \r
2787 __STATIC_INLINE void P6_4_toggle(void){\r
2788     PORT6->OMR = 0x00100010UL;\r
2789 }\r
2790 \r
2791 __STATIC_INLINE uint32_t P6_4_read(void){\r
2792     return(PORT6->IN & 0x00000010UL);\r
2793 }\r
2794 \r
2795 __STATIC_INLINE void P6_5_set_mode(uint8_t mode){\r
2796     PORT6->IOCR4 &= ~0x0000f800UL;\r
2797     PORT6->IOCR4 |= mode << 8;\r
2798 }\r
2799 \r
2800 __STATIC_INLINE void P6_5_set_driver_strength(uint8_t strength){\r
2801     PORT6->PDR0 &= ~0x00700000UL;\r
2802     PORT6->PDR0 |= strength << 20;\r
2803 }\r
2804 \r
2805 __STATIC_INLINE void P6_5_set_hwsel(uint32_t config){\r
2806     PORT6->HWSEL &= ~0x00000c00UL;\r
2807     PORT6->HWSEL |= config << 10;\r
2808 }\r
2809 \r
2810 __STATIC_INLINE void P6_5_set(void){\r
2811     PORT6->OMR = 0x00000020UL;\r
2812 }\r
2813 \r
2814 __STATIC_INLINE void P6_5_reset(void){\r
2815     PORT6->OMR = 0x00200000UL;\r
2816 }\r
2817 \r
2818 __STATIC_INLINE void P6_5_toggle(void){\r
2819     PORT6->OMR = 0x00200020UL;\r
2820 }\r
2821 \r
2822 __STATIC_INLINE uint32_t P6_5_read(void){\r
2823     return(PORT6->IN & 0x00000020UL);\r
2824 }\r
2825 \r
2826 __STATIC_INLINE void P6_6_set_mode(uint8_t mode){\r
2827     PORT6->IOCR4 &= ~0x00f80000UL;\r
2828     PORT6->IOCR4 |= mode << 16;\r
2829 }\r
2830 \r
2831 __STATIC_INLINE void P6_6_set_driver_strength(uint8_t strength){\r
2832     PORT6->PDR0 &= ~0x07000000UL;\r
2833     PORT6->PDR0 |= strength << 24;\r
2834 }\r
2835 \r
2836 __STATIC_INLINE void P6_6_set_hwsel(uint32_t config){\r
2837     PORT6->HWSEL &= ~0x00003000UL;\r
2838     PORT6->HWSEL |= config << 12;\r
2839 }\r
2840 \r
2841 __STATIC_INLINE void P6_6_set(void){\r
2842     PORT6->OMR = 0x00000040UL;\r
2843 }\r
2844 \r
2845 __STATIC_INLINE void P6_6_reset(void){\r
2846     PORT6->OMR = 0x00400000UL;\r
2847 }\r
2848 \r
2849 __STATIC_INLINE void P6_6_toggle(void){\r
2850     PORT6->OMR = 0x00400040UL;\r
2851 }\r
2852 \r
2853 __STATIC_INLINE uint32_t P6_6_read(void){\r
2854     return(PORT6->IN & 0x00000040UL);\r
2855 }\r
2856 \r
2857 __STATIC_INLINE void P14_0_set_mode(uint8_t mode){\r
2858     PORT14->IOCR0 &= ~0x000000f8UL;\r
2859     PORT14->IOCR0 |= mode << 0;\r
2860 }\r
2861 \r
2862 __STATIC_INLINE void P14_0_enable_digital(void){\r
2863     PORT14->PDISC &= ~0x00000001UL;\r
2864 }\r
2865 \r
2866 __STATIC_INLINE void P14_0_disable_digital(void){\r
2867     PORT14->PDISC |= 0x00000001UL;\r
2868 }\r
2869 \r
2870 __STATIC_INLINE uint32_t P14_0_read(void){\r
2871     return(PORT14->IN & 0x00000001UL);\r
2872 }\r
2873 \r
2874 __STATIC_INLINE void P14_1_set_mode(uint8_t mode){\r
2875     PORT14->IOCR0 &= ~0x0000f800UL;\r
2876     PORT14->IOCR0 |= mode << 8;\r
2877 }\r
2878 \r
2879 __STATIC_INLINE void P14_1_enable_digital(void){\r
2880     PORT14->PDISC &= ~0x00000002UL;\r
2881 }\r
2882 \r
2883 __STATIC_INLINE void P14_1_disable_digital(void){\r
2884     PORT14->PDISC |= 0x00000002UL;\r
2885 }\r
2886 \r
2887 __STATIC_INLINE uint32_t P14_1_read(void){\r
2888     return(PORT14->IN & 0x00000002UL);\r
2889 }\r
2890 \r
2891 __STATIC_INLINE void P14_2_set_mode(uint8_t mode){\r
2892     PORT14->IOCR0 &= ~0x00f80000UL;\r
2893     PORT14->IOCR0 |= mode << 16;\r
2894 }\r
2895 \r
2896 __STATIC_INLINE void P14_2_enable_digital(void){\r
2897     PORT14->PDISC &= ~0x00000004UL;\r
2898 }\r
2899 \r
2900 __STATIC_INLINE void P14_2_disable_digital(void){\r
2901     PORT14->PDISC |= 0x00000004UL;\r
2902 }\r
2903 \r
2904 __STATIC_INLINE uint32_t P14_2_read(void){\r
2905     return(PORT14->IN & 0x00000004UL);\r
2906 }\r
2907 \r
2908 __STATIC_INLINE void P14_3_set_mode(uint8_t mode){\r
2909     PORT14->IOCR0 &= ~0xf8000000UL;\r
2910     PORT14->IOCR0 |= mode << 24;\r
2911 }\r
2912 \r
2913 __STATIC_INLINE void P14_3_enable_digital(void){\r
2914     PORT14->PDISC &= ~0x00000008UL;\r
2915 }\r
2916 \r
2917 __STATIC_INLINE void P14_3_disable_digital(void){\r
2918     PORT14->PDISC |= 0x00000008UL;\r
2919 }\r
2920 \r
2921 __STATIC_INLINE uint32_t P14_3_read(void){\r
2922     return(PORT14->IN & 0x00000008UL);\r
2923 }\r
2924 \r
2925 __STATIC_INLINE void P14_4_set_mode(uint8_t mode){\r
2926     PORT14->IOCR4 &= ~0x000000f8UL;\r
2927     PORT14->IOCR4 |= mode << 0;\r
2928 }\r
2929 \r
2930 __STATIC_INLINE void P14_4_enable_digital(void){\r
2931     PORT14->PDISC &= ~0x00000010UL;\r
2932 }\r
2933 \r
2934 __STATIC_INLINE void P14_4_disable_digital(void){\r
2935     PORT14->PDISC |= 0x00000010UL;\r
2936 }\r
2937 \r
2938 __STATIC_INLINE uint32_t P14_4_read(void){\r
2939     return(PORT14->IN & 0x00000010UL);\r
2940 }\r
2941 \r
2942 __STATIC_INLINE void P14_5_set_mode(uint8_t mode){\r
2943     PORT14->IOCR4 &= ~0x0000f800UL;\r
2944     PORT14->IOCR4 |= mode << 8;\r
2945 }\r
2946 \r
2947 __STATIC_INLINE void P14_5_enable_digital(void){\r
2948     PORT14->PDISC &= ~0x00000020UL;\r
2949 }\r
2950 \r
2951 __STATIC_INLINE void P14_5_disable_digital(void){\r
2952     PORT14->PDISC |= 0x00000020UL;\r
2953 }\r
2954 \r
2955 __STATIC_INLINE uint32_t P14_5_read(void){\r
2956     return(PORT14->IN & 0x00000020UL);\r
2957 }\r
2958 \r
2959 __STATIC_INLINE void P14_6_set_mode(uint8_t mode){\r
2960     PORT14->IOCR4 &= ~0x00f80000UL;\r
2961     PORT14->IOCR4 |= mode << 16;\r
2962 }\r
2963 \r
2964 __STATIC_INLINE void P14_6_enable_digital(void){\r
2965     PORT14->PDISC &= ~0x00000040UL;\r
2966 }\r
2967 \r
2968 __STATIC_INLINE void P14_6_disable_digital(void){\r
2969     PORT14->PDISC |= 0x00000040UL;\r
2970 }\r
2971 \r
2972 __STATIC_INLINE uint32_t P14_6_read(void){\r
2973     return(PORT14->IN & 0x00000040UL);\r
2974 }\r
2975 \r
2976 __STATIC_INLINE void P14_7_set_mode(uint8_t mode){\r
2977     PORT14->IOCR4 &= ~0xf8000000UL;\r
2978     PORT14->IOCR4 |= mode << 24;\r
2979 }\r
2980 \r
2981 __STATIC_INLINE void P14_7_enable_digital(void){\r
2982     PORT14->PDISC &= ~0x00000080UL;\r
2983 }\r
2984 \r
2985 __STATIC_INLINE void P14_7_disable_digital(void){\r
2986     PORT14->PDISC |= 0x00000080UL;\r
2987 }\r
2988 \r
2989 __STATIC_INLINE uint32_t P14_7_read(void){\r
2990     return(PORT14->IN & 0x00000080UL);\r
2991 }\r
2992 \r
2993 __STATIC_INLINE void P14_8_set_mode(uint8_t mode){\r
2994     PORT14->IOCR8 &= ~0x000000f8UL;\r
2995     PORT14->IOCR8 |= mode << 0;\r
2996 }\r
2997 \r
2998 __STATIC_INLINE void P14_8_enable_digital(void){\r
2999     PORT14->PDISC &= ~0x00000100UL;\r
3000 }\r
3001 \r
3002 __STATIC_INLINE void P14_8_disable_digital(void){\r
3003     PORT14->PDISC |= 0x00000100UL;\r
3004 }\r
3005 \r
3006 __STATIC_INLINE uint32_t P14_8_read(void){\r
3007     return(PORT14->IN & 0x00000100UL);\r
3008 }\r
3009 \r
3010 __STATIC_INLINE void P14_9_set_mode(uint8_t mode){\r
3011     PORT14->IOCR8 &= ~0x0000f800UL;\r
3012     PORT14->IOCR8 |= mode << 8;\r
3013 }\r
3014 \r
3015 __STATIC_INLINE void P14_9_enable_digital(void){\r
3016     PORT14->PDISC &= ~0x00000200UL;\r
3017 }\r
3018 \r
3019 __STATIC_INLINE void P14_9_disable_digital(void){\r
3020     PORT14->PDISC |= 0x00000200UL;\r
3021 }\r
3022 \r
3023 __STATIC_INLINE uint32_t P14_9_read(void){\r
3024     return(PORT14->IN & 0x00000200UL);\r
3025 }\r
3026 \r
3027 __STATIC_INLINE void P14_12_set_mode(uint8_t mode){\r
3028     PORT14->IOCR12 &= ~0x000000f8UL;\r
3029     PORT14->IOCR12 |= mode << 0;\r
3030 }\r
3031 \r
3032 __STATIC_INLINE void P14_12_enable_digital(void){\r
3033     PORT14->PDISC &= ~0x00001000UL;\r
3034 }\r
3035 \r
3036 __STATIC_INLINE void P14_12_disable_digital(void){\r
3037     PORT14->PDISC |= 0x00001000UL;\r
3038 }\r
3039 \r
3040 __STATIC_INLINE uint32_t P14_12_read(void){\r
3041     return(PORT14->IN & 0x00001000UL);\r
3042 }\r
3043 \r
3044 __STATIC_INLINE void P14_13_set_mode(uint8_t mode){\r
3045     PORT14->IOCR12 &= ~0x0000f800UL;\r
3046     PORT14->IOCR12 |= mode << 8;\r
3047 }\r
3048 \r
3049 __STATIC_INLINE void P14_13_enable_digital(void){\r
3050     PORT14->PDISC &= ~0x00002000UL;\r
3051 }\r
3052 \r
3053 __STATIC_INLINE void P14_13_disable_digital(void){\r
3054     PORT14->PDISC |= 0x00002000UL;\r
3055 }\r
3056 \r
3057 __STATIC_INLINE uint32_t P14_13_read(void){\r
3058     return(PORT14->IN & 0x00002000UL);\r
3059 }\r
3060 \r
3061 __STATIC_INLINE void P14_14_set_mode(uint8_t mode){\r
3062     PORT14->IOCR12 &= ~0x00f80000UL;\r
3063     PORT14->IOCR12 |= mode << 16;\r
3064 }\r
3065 \r
3066 __STATIC_INLINE void P14_14_enable_digital(void){\r
3067     PORT14->PDISC &= ~0x00004000UL;\r
3068 }\r
3069 \r
3070 __STATIC_INLINE void P14_14_disable_digital(void){\r
3071     PORT14->PDISC |= 0x00004000UL;\r
3072 }\r
3073 \r
3074 __STATIC_INLINE uint32_t P14_14_read(void){\r
3075     return(PORT14->IN & 0x00004000UL);\r
3076 }\r
3077 \r
3078 __STATIC_INLINE void P14_15_set_mode(uint8_t mode){\r
3079     PORT14->IOCR12 &= ~0xf8000000UL;\r
3080     PORT14->IOCR12 |= mode << 24;\r
3081 }\r
3082 \r
3083 __STATIC_INLINE void P14_15_enable_digital(void){\r
3084     PORT14->PDISC &= ~0x00008000UL;\r
3085 }\r
3086 \r
3087 __STATIC_INLINE void P14_15_disable_digital(void){\r
3088     PORT14->PDISC |= 0x00008000UL;\r
3089 }\r
3090 \r
3091 __STATIC_INLINE uint32_t P14_15_read(void){\r
3092     return(PORT14->IN & 0x00008000UL);\r
3093 }\r
3094 \r
3095 __STATIC_INLINE void P15_2_set_mode(uint8_t mode){\r
3096     PORT15->IOCR0 &= ~0x00f80000UL;\r
3097     PORT15->IOCR0 |= mode << 16;\r
3098 }\r
3099 \r
3100 __STATIC_INLINE void P15_2_enable_digital(void){\r
3101     PORT15->PDISC &= ~0x00000004UL;\r
3102 }\r
3103 \r
3104 __STATIC_INLINE void P15_2_disable_digital(void){\r
3105     PORT15->PDISC |= 0x00000004UL;\r
3106 }\r
3107 \r
3108 __STATIC_INLINE uint32_t P15_2_read(void){\r
3109     return(PORT15->IN & 0x00000004UL);\r
3110 }\r
3111 \r
3112 __STATIC_INLINE void P15_3_set_mode(uint8_t mode){\r
3113     PORT15->IOCR0 &= ~0xf8000000UL;\r
3114     PORT15->IOCR0 |= mode << 24;\r
3115 }\r
3116 \r
3117 __STATIC_INLINE void P15_3_enable_digital(void){\r
3118     PORT15->PDISC &= ~0x00000008UL;\r
3119 }\r
3120 \r
3121 __STATIC_INLINE void P15_3_disable_digital(void){\r
3122     PORT15->PDISC |= 0x00000008UL;\r
3123 }\r
3124 \r
3125 __STATIC_INLINE uint32_t P15_3_read(void){\r
3126     return(PORT15->IN & 0x00000008UL);\r
3127 }\r
3128 \r
3129 __STATIC_INLINE void P15_4_set_mode(uint8_t mode){\r
3130     PORT15->IOCR4 &= ~0x000000f8UL;\r
3131     PORT15->IOCR4 |= mode << 0;\r
3132 }\r
3133 \r
3134 __STATIC_INLINE void P15_4_enable_digital(void){\r
3135     PORT15->PDISC &= ~0x00000010UL;\r
3136 }\r
3137 \r
3138 __STATIC_INLINE void P15_4_disable_digital(void){\r
3139     PORT15->PDISC |= 0x00000010UL;\r
3140 }\r
3141 \r
3142 __STATIC_INLINE uint32_t P15_4_read(void){\r
3143     return(PORT15->IN & 0x00000010UL);\r
3144 }\r
3145 \r
3146 __STATIC_INLINE void P15_5_set_mode(uint8_t mode){\r
3147     PORT15->IOCR4 &= ~0x0000f800UL;\r
3148     PORT15->IOCR4 |= mode << 8;\r
3149 }\r
3150 \r
3151 __STATIC_INLINE void P15_5_enable_digital(void){\r
3152     PORT15->PDISC &= ~0x00000020UL;\r
3153 }\r
3154 \r
3155 __STATIC_INLINE void P15_5_disable_digital(void){\r
3156     PORT15->PDISC |= 0x00000020UL;\r
3157 }\r
3158 \r
3159 __STATIC_INLINE uint32_t P15_5_read(void){\r
3160     return(PORT15->IN & 0x00000020UL);\r
3161 }\r
3162 \r
3163 __STATIC_INLINE void P15_6_set_mode(uint8_t mode){\r
3164     PORT15->IOCR4 &= ~0x00f80000UL;\r
3165     PORT15->IOCR4 |= mode << 16;\r
3166 }\r
3167 \r
3168 __STATIC_INLINE void P15_6_enable_digital(void){\r
3169     PORT15->PDISC &= ~0x00000040UL;\r
3170 }\r
3171 \r
3172 __STATIC_INLINE void P15_6_disable_digital(void){\r
3173     PORT15->PDISC |= 0x00000040UL;\r
3174 }\r
3175 \r
3176 __STATIC_INLINE uint32_t P15_6_read(void){\r
3177     return(PORT15->IN & 0x00000040UL);\r
3178 }\r
3179 \r
3180 __STATIC_INLINE void P15_7_set_mode(uint8_t mode){\r
3181     PORT15->IOCR4 &= ~0xf8000000UL;\r
3182     PORT15->IOCR4 |= mode << 24;\r
3183 }\r
3184 \r
3185 __STATIC_INLINE void P15_7_enable_digital(void){\r
3186     PORT15->PDISC &= ~0x00000080UL;\r
3187 }\r
3188 \r
3189 __STATIC_INLINE void P15_7_disable_digital(void){\r
3190     PORT15->PDISC |= 0x00000080UL;\r
3191 }\r
3192 \r
3193 __STATIC_INLINE uint32_t P15_7_read(void){\r
3194     return(PORT15->IN & 0x00000080UL);\r
3195 }\r
3196 \r
3197 __STATIC_INLINE void P15_8_set_mode(uint8_t mode){\r
3198     PORT15->IOCR8 &= ~0x000000f8UL;\r
3199     PORT15->IOCR8 |= mode << 0;\r
3200 }\r
3201 \r
3202 __STATIC_INLINE void P15_8_enable_digital(void){\r
3203     PORT15->PDISC &= ~0x00000100UL;\r
3204 }\r
3205 \r
3206 __STATIC_INLINE void P15_8_disable_digital(void){\r
3207     PORT15->PDISC |= 0x00000100UL;\r
3208 }\r
3209 \r
3210 __STATIC_INLINE uint32_t P15_8_read(void){\r
3211     return(PORT15->IN & 0x00000100UL);\r
3212 }\r
3213 \r
3214 __STATIC_INLINE void P15_9_set_mode(uint8_t mode){\r
3215     PORT15->IOCR8 &= ~0x0000f800UL;\r
3216     PORT15->IOCR8 |= mode << 8;\r
3217 }\r
3218 \r
3219 __STATIC_INLINE void P15_9_enable_digital(void){\r
3220     PORT15->PDISC &= ~0x00000200UL;\r
3221 }\r
3222 \r
3223 __STATIC_INLINE void P15_9_disable_digital(void){\r
3224     PORT15->PDISC |= 0x00000200UL;\r
3225 }\r
3226 \r
3227 __STATIC_INLINE uint32_t P15_9_read(void){\r
3228     return(PORT15->IN & 0x00000200UL);\r
3229 }\r
3230 \r
3231 __STATIC_INLINE void P15_12_set_mode(uint8_t mode){\r
3232     PORT15->IOCR12 &= ~0x000000f8UL;\r
3233     PORT15->IOCR12 |= mode << 0;\r
3234 }\r
3235 \r
3236 __STATIC_INLINE void P15_12_enable_digital(void){\r
3237     PORT15->PDISC &= ~0x00001000UL;\r
3238 }\r
3239 \r
3240 __STATIC_INLINE void P15_12_disable_digital(void){\r
3241     PORT15->PDISC |= 0x00001000UL;\r
3242 }\r
3243 \r
3244 __STATIC_INLINE uint32_t P15_12_read(void){\r
3245     return(PORT15->IN & 0x00001000UL);\r
3246 }\r
3247 \r
3248 __STATIC_INLINE void P15_13_set_mode(uint8_t mode){\r
3249     PORT15->IOCR12 &= ~0x0000f800UL;\r
3250     PORT15->IOCR12 |= mode << 8;\r
3251 }\r
3252 \r
3253 __STATIC_INLINE void P15_13_enable_digital(void){\r
3254     PORT15->PDISC &= ~0x00002000UL;\r
3255 }\r
3256 \r
3257 __STATIC_INLINE void P15_13_disable_digital(void){\r
3258     PORT15->PDISC |= 0x00002000UL;\r
3259 }\r
3260 \r
3261 __STATIC_INLINE uint32_t P15_13_read(void){\r
3262     return(PORT15->IN & 0x00002000UL);\r
3263 }\r
3264 \r
3265 __STATIC_INLINE void P15_14_set_mode(uint8_t mode){\r
3266     PORT15->IOCR12 &= ~0x00f80000UL;\r
3267     PORT15->IOCR12 |= mode << 16;\r
3268 }\r
3269 \r
3270 __STATIC_INLINE void P15_14_enable_digital(void){\r
3271     PORT15->PDISC &= ~0x00004000UL;\r
3272 }\r
3273 \r
3274 __STATIC_INLINE void P15_14_disable_digital(void){\r
3275     PORT15->PDISC |= 0x00004000UL;\r
3276 }\r
3277 \r
3278 __STATIC_INLINE uint32_t P15_14_read(void){\r
3279     return(PORT15->IN & 0x00004000UL);\r
3280 }\r
3281 \r
3282 __STATIC_INLINE void P15_15_set_mode(uint8_t mode){\r
3283     PORT15->IOCR12 &= ~0xf8000000UL;\r
3284     PORT15->IOCR12 |= mode << 24;\r
3285 }\r
3286 \r
3287 __STATIC_INLINE void P15_15_enable_digital(void){\r
3288     PORT15->PDISC &= ~0x00008000UL;\r
3289 }\r
3290 \r
3291 __STATIC_INLINE void P15_15_disable_digital(void){\r
3292     PORT15->PDISC |= 0x00008000UL;\r
3293 }\r
3294 \r
3295 __STATIC_INLINE uint32_t P15_15_read(void){\r
3296     return(PORT15->IN & 0x00008000UL);\r
3297 }\r
3298 \r
3299 #endif\r