git.sur5r.net Git - freertos/blob - FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_Keil/System_XMC4500.c

   1 /**************************************************************************//**\r
   2  * @file     system_XMC4500.c\r
   3  * @brief    CMSIS Cortex-M4 Device Peripheral Access Layer Header File\r
   4  *           for the Infineon XMC4500 Device Series\r
   5  * @version  V3.0.1 Alpha\r
   6  * @date     17. September 2012\r
   7  *\r
   8  * @note\r
   9  * Copyright (C) 2011 ARM Limited. All rights reserved.\r
  10  *\r
  11  * @par\r
  12  * ARM Limited (ARM) is supplying this software for use with Cortex-M\r
  13  * processor based microcontrollers.  This file can be freely distributed\r
  14  * within development tools that are supporting such ARM based processors.\r
  15  *\r
  16  * @par\r
  17  * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
  18  * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
  19  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
  20  * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
  21  * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
  22  *\r
  23  ******************************************************************************/\r
  24 \r
  25 #include "system_XMC4500.h"\r
  26 #include <XMC4500.h>\r
  27 \r
  28 /*----------------------------------------------------------------------------\r
  29   Clock Variable definitions\r
  30  *----------------------------------------------------------------------------*/\r
  31 /*!< System Clock Frequency (Core Clock)*/\r
  32 uint32_t SystemCoreClock;\r
  33 \r
  34 /* clock definitions, do not modify! */\r
  35 #define SCU_CLOCK_CRYSTAL               1\r
  36 #define SCU_CLOCK_BACK_UP_FACTORY                       2\r
  37 #define SCU_CLOCK_BACK_UP_AUTOMATIC             3\r
  38 \r
  39 \r
  40 #define HIB_CLOCK_FOSI                                  1\r
  41 #define HIB_CLOCK_OSCULP                                2\r
  42 \r
  43 \r
  44 \r
  45 \r
  46 /*\r
  47 //-------- <<< Use Configuration Wizard in Context Menu >>> ------------------\r
  48 */\r
  49 \r
  50 \r
  51 \r
  52 /*--------------------- Watchdog Configuration -------------------------------\r
  53 //\r
  54 // <e> Watchdog Configuration\r
  55 //     <o1.0> Disable Watchdog\r
  56 //\r
  57 // </e>\r
  58 */\r
  59 #define WDT_SETUP               1\r
  60 #define WDTENB_nVal             0x00000001\r
  61 \r
  62 /*--------------------- CLOCK Configuration -------------------------------\r
  63 //\r
  64 // <e> Main Clock Configuration\r
  65 //     <o1.0..1> CPU clock divider\r
  66 //                     <0=> fCPU = fSYS\r
  67 //                     <1=> fCPU = fSYS / 2\r
  68 //     <o2.0..1>  Peripheral Bus clock divider\r
  69 //                     <0=> fPB = fCPU\r
  70 //                     <1=> fPB = fCPU / 2\r
  71 //     <o3.0..1>  CCU Bus clock divider\r
  72 //                     <0=> fCCU = fCPU\r
  73 //                     <1=> fCCU = fCPU / 2\r
  74 //\r
  75 // </e>\r
  76 //\r
  77 */\r
  78 \r
  79 #define SCU_CLOCK_SETUP               1\r
  80 #define SCU_CPUCLKCR_DIV                0x00000000\r
  81 #define SCU_PBCLKCR_DIV             0x00000000\r
  82 #define SCU_CCUCLKCR_DIV                0x00000000\r
  83 /* not avalible in config wizzard*/\r
  84 /*\r
  85 * mandatory clock parameters **************************************************\r
  86 *\r
  87 * source for clock generation\r
  88 * range: SCU_CLOCK_CRYSTAL (crystal or external clock at crystal input)\r
  89 *\r
  90 **************************************************************************************/\r
  91 // Selection of imput lock for PLL\r
  92 /*************************************************************************************/\r
  93 #define SCU_PLL_CLOCK_INPUT     SCU_CLOCK_CRYSTAL\r
  94 //#define       SCU_PLL_CLOCK_INPUT     SCU_CLOCK_BACK_UP_FACTORY\r
  95 //#define       SCU_PLL_CLOCK_INPUT     SCU_CLOCK_BACK_UP_AUTOMATIC\r
  96 \r
  97 /*************************************************************************************/\r
  98 // Standby clock selection for Backup clock source trimming\r
  99 /*************************************************************************************/\r
 100 #define SCU_STANDBY_CLOCK  HIB_CLOCK_OSCULP\r
 101 //#define       SCU_STANDBY_CLOCK  HIB_CLOCK_FOSI\r
 102 \r
 103 /*************************************************************************************/\r
 104 // Global clock parameters\r
 105 /*************************************************************************************/\r
 106 #define CLOCK_FSYS                                                      120000000\r
 107 #define CLOCK_CRYSTAL_FREQUENCY 12000000\r
 108 #define CLOCK_BACK_UP                                           24000000\r
 109 \r
 110 /*************************************************************************************/\r
 111 /* OSC_HP setup parameters */\r
 112 /*************************************************************************************/\r
 113 #define SCU_OSC_HP_MODE 0xF0\r
 114 #define SCU_OSCHPWDGDIV 2\r
 115 \r
 116 /*************************************************************************************/\r
 117 /* MAIN PLL setup parameters */\r
 118 /*************************************************************************************/\r
 119 //Divider settings for external crystal @ 12 MHz\r
 120 /*************************************************************************************/\r
 121 #define         SCU_PLL_K1DIV   1\r
 122 #define         SCU_PLL_K2DIV   3\r
 123 #define         SCU_PLL_PDIV    1\r
 124 #define         SCU_PLL_NDIV    79\r
 125 \r
 126 /*************************************************************************************/\r
 127 //Divider settings for use of backup clock source trimmed\r
 128 /*************************************************************************************/\r
 129 //#define       SCU_PLL_K1DIV   1\r
 130 //#define       SCU_PLL_K2DIV   3\r
 131 //#define       SCU_PLL_PDIV    3\r
 132 //#define       SCU_PLL_NDIV    79\r
 133 /*************************************************************************************/\r
 134 \r
 135 /*--------------------- USB CLOCK Configuration ---------------------------\r
 136 //\r
 137 // <e> USB Clock Configuration\r
 138 //\r
 139 // </e>\r
 140 //\r
 141 */\r
 142 \r
 143 #define SCU_USB_CLOCK_SETUP              0\r
 144 /* not avalible in config wizzard*/\r
 145 #define         SCU_USBPLL_PDIV 0\r
 146 #define         SCU_USBPLL_NDIV 31\r
 147 #define         SCU_USBDIV      3\r
 148 \r
 149 /*--------------------- Flash Wait State Configuration -------------------------------\r
 150 //\r
 151 // <e> Flash Wait State Configuration\r
 152 //     <o1.0..3>   Flash Wait State\r
 153 //                     <0=> 3 WS\r
 154 //                     <1=> 4 WS\r
 155 //                     <2=> 5 WS\r
 156 //                                                                               <3=> 6 WS\r
 157 // </e>\r
 158 //\r
 159 */\r
 160 \r
 161 #define PMU_FLASH             1\r
 162 #define PMU_FLASH_WS                                    0x00000000\r
 163 \r
 164 \r
 165 /*--------------------- CLOCKOUT Configuration -------------------------------\r
 166 //\r
 167 // <e> Clock OUT Configuration\r
 168 //     <o1.0..1>   Clockout Source Selection\r
 169 //                     <0=> System Clock\r
 170 //                     <2=> Divided value of USB PLL output\r
 171 //                     <3=> Divided value of PLL Clock\r
 172 //     <o2.0..4>   Clockout divider <1-10><#-1>\r
 173 //     <o3.0..1>   Clockout Pin Selection\r
 174 //                     <0=> P1.15\r
 175 //                     <1=> P0.8\r
 176 //\r
 177 //\r
 178 // </e>\r
 179 //\r
 180 */\r
 181 \r
 182 #define SCU_CLOCKOUT_SETUP               0\r
 183 #define SCU_CLOCKOUT_SOURCE             0x00000003\r
 184 #define SCU_CLOCKOUT_DIV                0x00000009\r
 185 #define SCU_CLOCKOUT_PIN                0x00000001\r
 186 \r
 187 /*----------------------------------------------------------------------------\r
 188   Clock Variable definitions\r
 189  *----------------------------------------------------------------------------*/\r
 190 /*!< System Clock Frequency (Core Clock)*/\r
 191 #if SCU_CLOCK_SETUP\r
 192 uint32_t SystemCoreClock = CLOCK_FSYS;\r
 193 #else\r
 194 uint32_t SystemCoreClock = CLOCK_BACK_UP;\r
 195 #endif\r
 196 \r
 197 /*----------------------------------------------------------------------------\r
 198   static functions declarations\r
 199  *----------------------------------------------------------------------------*/\r
 200 #if (SCU_CLOCK_SETUP == 1)\r
 201 static int SystemClockSetup(void);\r
 202 #endif\r
 203 \r
 204 #if (SCU_USB_CLOCK_SETUP == 1)\r
 205 static int USBClockSetup(void);\r
 206 #endif\r
 207 \r
 208 \r
 209 /**\r
 210   * @brief  Setup the microcontroller system.\r
 211   *         Initialize the PLL and update the\r
 212   *         SystemCoreClock variable.\r
 213   * @param  None\r
 214   * @retval None\r
 215   */\r
 216 void SystemInit(void)\r
 217 {\r
 218 int temp;\r
 219 \r
 220 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)\r
 221 SCB->CPACR |= ((3UL << 10*2) |                 /* set CP10 Full Access */\r
 222                (3UL << 11*2)  );               /* set CP11 Full Access */\r
 223 #endif\r
 224 \r
 225 /* Enable unaligned memory access - SCB_CCR.UNALIGN_TRP = 0 */\r
 226 SCB->CCR &= ~(SCB_CCR_UNALIGN_TRP_Msk);\r
 227 \r
 228 /* Setup the WDT */\r
 229 #if WDT_SETUP\r
 230 \r
 231 WDT->CTR &= ~WDTENB_nVal;\r
 232 \r
 233 #endif\r
 234 \r
 235 /* Setup the Flash Wait State */\r
 236 #if PMU_FLASH\r
 237 temp = FLASH0->FCON;\r
 238 temp &= ~FLASH_FCON_WSPFLASH_Msk;\r
 239 temp |= PMU_FLASH_WS+3;\r
 240 FLASH0->FCON = temp;\r
 241 #endif\r
 242 \r
 243 \r
 244 /* Setup the clockout */\r
 245 #if SCU_CLOCKOUT_SETUP\r
 246 \r
 247 SCU_CLK->EXTCLKCR       |= SCU_CLOCKOUT_SOURCE;\r
 248 /*set PLL div for clkout */\r
 249 SCU_CLK->EXTCLKCR       |= SCU_CLOCKOUT_DIV<<16;\r
 250 \r
 251 if (SCU_CLOCKOUT_PIN) {\r
 252                                                 PORT0->IOCR8 = 0x00000088;   /*P0.8 --> ALT1 select +  HWSEL */\r
 253                                             PORT0->HWSEL &= (~PORT0_HWSEL_HW8_Msk);\r
 254                                             //PORT0->PDR1 &= (~PORT0_PDR1_PD8_Msk);  /*set to strong driver */\r
 255                                                 }\r
 256 else {\r
 257                 PORT1->IOCR12 = 0x88000000;                    /*P1.15--> ALT1 select */\r
 258             //PORT1->PDR1 &= (~PORT1_PDR1_PD15_Msk);  /*set to strong driver */\r
 259                 }\r
 260 \r
 261 #endif\r
 262 \r
 263 \r
 264 /* Setup the System clock */\r
 265 #if SCU_CLOCK_SETUP\r
 266 SystemClockSetup();\r
 267 #endif\r
 268 \r
 269 /*----------------------------------------------------------------------------\r
 270   Clock Variable definitions\r
 271  *----------------------------------------------------------------------------*/\r
 272 SystemCoreClockUpdate();/*!< System Clock Frequency (Core Clock)*/\r
 273 \r
 274 \r
 275 /* Setup the USB PL */\r
 276 #if SCU_USB_CLOCK_SETUP\r
 277 USBClockSetup();\r
 278 #endif\r
 279 \r
 280 \r
 281 \r
 282 }\r
 283 \r
 284 \r
 285 /**\r
 286   * @brief  Update SystemCoreClock according to Clock Register Values\r
 287   * @note   -\r
 288   * @param  None\r
 289   * @retval None\r
 290   */\r
 291 void SystemCoreClockUpdate(void)\r
 292 {\r
 293 unsigned int PDIV;\r
 294 unsigned int NDIV;\r
 295 unsigned int K2DIV;\r
 296 unsigned int long VCO;\r
 297 \r
 298 \r
 299 /*----------------------------------------------------------------------------\r
 300   Clock Variable definitions\r
 301  *----------------------------------------------------------------------------*/\r
 302 if (SCU_CLK->SYSCLKCR ==  0x00010000)\r
 303 {\r
 304         if (SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk){\r
 305                 /* check if PLL is locked */\r
 306                 /* read back divider settings */\r
 307                  PDIV = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_PDIV_Msk)>>24)+1;\r
 308                  NDIV = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_NDIV_Msk)>>8)+1;\r
 309                  K2DIV  = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_K2DIV_Msk)>>16)+1;\r
 310 \r
 311                 if(SCU_PLL->PLLCON2 & SCU_PLL_PLLCON2_PINSEL_Msk){\r
 312                 /* the selected clock is the Backup clock fofi */\r
 313                 VCO = (CLOCK_BACK_UP/PDIV)*NDIV;\r
 314                 SystemCoreClock = VCO/K2DIV;\r
 315                 /* in case the sysclock div is used */\r
 316                 SystemCoreClock = SystemCoreClock/((SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSDIV_Msk)+1);\r
 317 \r
 318                 }\r
 319                 else\r
 320                 {\r
 321                 /* the selected clock is the PLL external oscillator */\r
 322                 VCO = (CLOCK_CRYSTAL_FREQUENCY/PDIV)*NDIV;\r
 323                 SystemCoreClock = VCO/K2DIV;\r
 324                 /* in case the sysclock div is used */\r
 325                 SystemCoreClock = SystemCoreClock/((SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSDIV_Msk)+1);\r
 326                 }\r
 327 \r
 328 \r
 329         }\r
 330 }\r
 331 else\r
 332 {\r
 333 SystemCoreClock = CLOCK_BACK_UP;\r
 334 }\r
 335 \r
 336 \r
 337 }\r
 338 \r
 339 \r
 340 /**\r
 341   * @brief  -\r
 342   * @note   -\r
 343   * @param  None\r
 344   * @retval None\r
 345   */\r
 346 #if (SCU_CLOCK_SETUP == 1)\r
 347 static int SystemClockSetup(void)\r
 348 {\r
 349 int temp;\r
 350 unsigned int long VCO;\r
 351 int stepping_K2DIV;\r
 352 \r
 353 /* this weak function enables DAVE3 clock App usage */\r
 354 if(AllowPLLInitByStartup()){\r
 355 \r
 356 /* check if PLL is switched on */\r
 357 if ((SCU_PLL->PLLCON0 &(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk)) != 0){\r
 358 /* enable PLL first */\r
 359   SCU_PLL->PLLCON0 &= ~(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk);\r
 360 \r
 361 }\r
 362 \r
 363 /* Enable OSC_HP if not already on*/\r
 364   if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)\r
 365   {\r
 366         /********************************************************************************************************************/\r
 367         /*   Use external crystal for PLL clock input                                                                            */\r
 368         /********************************************************************************************************************/\r
 369 \r
 370    if (SCU_OSC->OSCHPCTRL & SCU_OSC_OSCHPCTRL_MODE_Msk){\r
 371            SCU_OSC->OSCHPCTRL &= ~(SCU_OSC_HP_MODE);     /*enable the OSC_HP*/\r
 372            /* setup OSC WDG devider */\r
 373            SCU_OSC->OSCHPCTRL |= (SCU_OSCHPWDGDIV<<16);\r
 374            /* select external OSC as PLL input */\r
 375            SCU_PLL->PLLCON2 &= ~SCU_PLL_PLLCON2_PINSEL_Msk;\r
 376            /* restart OSC Watchdog */\r
 377            SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCRES_Msk;\r
 378 \r
 379        /* Timeout for wait loop ~150ms */\r
 380            /********************************/\r
 381            SysTick->LOAD  = ((5000000+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */\r
 382            SysTick->VAL   = 0;                                         /* Load the SysTick Counter Value */\r
 383            SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\r
 384                            SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */\r
 385            do\r
 386            {\r
 387        ;/* wait for ~150ms  */\r
 388            }while((((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380)&&(SysTick->VAL >= 500));\r
 389 \r
 390            SysTick->CTRL  &= ~SysTick_CTRL_ENABLE_Msk;                 /* Stop SysTick Timer */\r
 391            if (((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380)\r
 392            return(0);/* Return Error */\r
 393 \r
 394     }\r
 395   }\r
 396   else if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY)\r
 397         {\r
 398         /********************************************************************************************************************/\r
 399         /*   Use factory trimming Back-up clock for PLL clock input                                                                            */\r
 400         /********************************************************************************************************************/\r
 401                 /* PLL Back up clock selected */\r
 402                 SCU_PLL->PLLCON2 |= SCU_PLL_PLLCON2_PINSEL_Msk;\r
 403 \r
 404         }\r
 405   else if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC)\r
 406   {\r
 407         /********************************************************************************************************************/\r
 408         /*   Use automatic trimming Back-up clock for PLL clock input                                                                            */\r
 409         /********************************************************************************************************************/\r
 410         /* check for HIB Domain enabled  */\r
 411         if((SCU_POWER->PWRSTAT & SCU_POWER_PWRSTAT_HIBEN_Msk) == 0)\r
 412                 SCU_POWER->PWRSET |= SCU_POWER_PWRSET_HIB_Msk; /*enable Hibernate domain*/\r
 413 \r
 414    /* check for HIB Domain is not in reset state  */\r
 415         if ((SCU_RESET->RSTSTAT & SCU_RESET_RSTSTAT_HIBRS_Msk)== 1)\r
 416             SCU_RESET->RSTCLR |= SCU_RESET_RSTCLR_HIBRS_Msk; /*de-assert hibernate reset*/\r
 417 \r
 418                         /* PLL Back up clock selected */\r
 419                 SCU_PLL->PLLCON2 |= SCU_PLL_PLLCON2_PINSEL_Msk;\r
 420 \r
 421                 if (SCU_STANDBY_CLOCK == HIB_CLOCK_FOSI)\r
 422                         {\r
 423                         /****************************************************************************************************************/\r
 424                         /*   Use fOSI as source of the standby clock                                                                             */\r
 425                         /****************************************************************************************************************/\r
 426                         SCU_HIBERNATE->HDCR &= ~SCU_HIBERNATE_HDCR_STDBYSEL_Msk;\r
 427 \r
 428                         SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_FOTR_Msk;\r
 429                         for(temp=0;temp<=0xFFFF;temp++);\r
 430 \r
 431                         SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_AOTREN_Msk;\r
 432                         }\r
 433                 else if (SCU_STANDBY_CLOCK == HIB_CLOCK_OSCULP)\r
 434                         {\r
 435                         /****************************************************************************************************************/\r
 436                         /*   Use fULP as source of the standby clock                                                                            */\r
 437                         /****************************************************************************************************************/\r
 438                         /*check OSCUL if running correct*/\r
 439                         if ((SCU_HIBERNATE->OSCULCTRL & SCU_HIBERNATE_OSCULCTRL_MODE_Msk)!= 0)\r
 440                                 {\r
 441                                         while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_OSCULCTRL_Msk);\r
 442 \r
 443                                         SCU_HIBERNATE->OSCULCTRL &= ~SCU_HIBERNATE_OSCULCTRL_MODE_Msk; /*enable OSCUL*/\r
 444                                         /*now ceck if the clock is OK using OSCULP Oscillator Watchdog (ULPWDG)*/\r
 445                                         /* select OSCUL clock for RTC*/\r
 446                                         SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_RCS_Msk;\r
 447                                         while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk);\r
 448                                         /*enable OSCULP WDG Alarm Enable*/\r
 449                                         SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_ULPWDGEN_Msk;\r
 450                                         while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk);\r
 451                                         /*wait now for clock is stable */\r
 452                                         do\r
 453                                         {\r
 454                                         SCU_HIBERNATE->HDCLR |= SCU_HIBERNATE_HDCLR_ULPWDG_Msk;\r
 455                                         while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCLR_Msk);\r
 456                                         for(temp=0;temp<=0xFFFF;temp++);\r
 457                                         }\r
 458                                         while ((SCU_HIBERNATE->HDSTAT & SCU_HIBERNATE_HDSTAT_ULPWDG_Msk)==SCU_HIBERNATE_HDSTAT_ULPWDG_Msk);\r
 459 \r
 460                                         SCU_HIBERNATE->HDCLR |= SCU_HIBERNATE_HDCLR_ULPWDG_Msk;\r
 461                                         while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCLR_Msk);\r
 462                                 }\r
 463                         // now OSCULP is running and can be used\r
 464                         SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_STDBYSEL_Msk;\r
 465                         while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk);\r
 466 \r
 467                         SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_FOTR_Msk;\r
 468                         /*TRIAL for delay loop*/\r
 469                         for(temp=0;temp<=0xFFFF;temp++);\r
 470 \r
 471                         SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_AOTREN_Msk;\r
 472                         /*TRIAL for delay loop*/\r
 473                         for(temp=0;temp<=0xFFFF;temp++);\r
 474 \r
 475                         }\r
 476   }\r
 477 \r
 478         /********************************************************************************************************************/\r
 479         /*   Setup and look the main PLL                                                                                    */\r
 480         /********************************************************************************************************************/\r
 481 \r
 482 if (!(SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk)){\r
 483         /* Systen is still running from internal clock */\r
 484                    /* select FOFI as system clock */\r
 485                    if((SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSSEL_Msk) != 0x0)SCU_CLK->SYSCLKCR &= ~SCU_CLK_SYSCLKCR_SYSSEL_Msk; /*Select FOFI*/\r
 486 \r
 487 \r
 488                          /*calulation for stepping*/\r
 489                          if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)VCO = (CLOCK_CRYSTAL_FREQUENCY/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);\r
 490                          if ((SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC) ||(SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY))\r
 491                                         VCO = (CLOCK_BACK_UP/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);\r
 492 \r
 493                          stepping_K2DIV = (VCO/24000000)-1;\r
 494                          /* Go to bypass the Main PLL */\r
 495                    SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_VCOBYP_Msk;\r
 496                    /* disconnect OSC_HP to PLL */\r
 497                    SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_FINDIS_Msk;\r
 498                    /* Setup devider settings for main PLL */\r
 499                    SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (stepping_K2DIV<<16) | (SCU_PLL_PDIV<<24));\r
 500                    /* we may have to set OSCDISCDIS */\r
 501                    SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_OSCDISCDIS_Msk;\r
 502                    /* connect OSC_HP to PLL */\r
 503                    SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_FINDIS_Msk;\r
 504                    /* restart PLL Lock detection */\r
 505                    SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_RESLD_Msk;\r
 506                    /* wait for PLL Lock */\r
 507                    /* setup time out loop */\r
 508                /* Timeout for wait loo ~150ms */\r
 509                    /********************************/\r
 510                    SysTick->LOAD  = ((5000000+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */\r
 511                    SysTick->VAL   = 0;                                         /* Load the SysTick Counter Value */\r
 512                    SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\r
 513                                    SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */\r
 514 \r
 515                    while ((!(SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk))&&(SysTick->VAL >= 500));\r
 516                SysTick->CTRL  &= ~SysTick_CTRL_ENABLE_Msk;                 /* Stop SysTick Timer */\r
 517 \r
 518                    if ((SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk)==SCU_PLL_PLLSTAT_VCOLOCK_Msk)\r
 519                                 {\r
 520                                 /* Go back to the Main PLL */\r
 521                                 SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_VCOBYP_Msk;\r
 522                                 }\r
 523                                 else return(0);\r
 524 \r
 525 \r
 526            /*********************************************************\r
 527            here we need to setup the system clock divider\r
 528            *********************************************************/\r
 529 \r
 530                 SCU_CLK->CPUCLKCR = SCU_CPUCLKCR_DIV;\r
 531                 SCU_CLK->PBCLKCR = SCU_PBCLKCR_DIV;\r
 532                 SCU_CLK->CCUCLKCR = SCU_CCUCLKCR_DIV;\r
 533 \r
 534 \r
 535                  /* Switch system clock to PLL */\r
 536            SCU_CLK->SYSCLKCR |=  0x00010000;\r
 537 \r
 538            /* we may have to reset OSCDISCDIS */\r
 539            SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCDISCDIS_Msk;\r
 540 \r
 541 \r
 542                  /*********************************************************/\r
 543                  /* Delay for next K2 step ~50µs */\r
 544                  /*********************************************************/\r
 545                  SysTick->LOAD  = ((1250+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */\r
 546                  SysTick->VAL   = 0;                                         /* Load the SysTick Counter Value */\r
 547                  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\r
 548                                                                                  SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */\r
 549 \r
 550                  while (SysTick->VAL >= 100);                                                              /* wait for ~50µs  */\r
 551                  SysTick->CTRL  &= ~SysTick_CTRL_ENABLE_Msk;                 /* Stop SysTick Timer */\r
 552                  /*********************************************************/\r
 553 \r
 554            /*********************************************************\r
 555            here the ramp up of the system clock starts FSys < 60MHz\r
 556            *********************************************************/\r
 557                 if (CLOCK_FSYS > 60000000){\r
 558                          /*calulation for stepping*/\r
 559                          if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)VCO = (CLOCK_CRYSTAL_FREQUENCY/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);\r
 560                          if ((SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC) ||(SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY))\r
 561                                         VCO = (CLOCK_BACK_UP/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);\r
 562 \r
 563                          stepping_K2DIV = (VCO/60000000)-1;\r
 564 \r
 565                          /* Setup devider settings for main PLL */\r
 566                                 SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (stepping_K2DIV<<16) | (SCU_PLL_PDIV<<24));\r
 567                  }\r
 568                  else\r
 569                  {\r
 570                                 /* Setup devider settings for main PLL */\r
 571                                 SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (SCU_PLL_K2DIV<<16) | (SCU_PLL_PDIV<<24));\r
 572                     SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_SOSCWDGT_Msk | SCU_TRAP_TRAPCLR_SVCOLCKT_Msk;  /* clear request for System OCS Watchdog Trap and System VCO Lock Trap  */\r
 573                           return(1);\r
 574                  }\r
 575 \r
 576                  /*********************************************************/\r
 577                  /* Delay for next K2 step ~50µs */\r
 578                  /*********************************************************/\r
 579            SysTick->LOAD  = ((3000+100) & SysTick_LOAD_RELOAD_Msk) - 1;\r
 580            SysTick->VAL   = 0;                                         /* Load the SysTick Counter Value */\r
 581            SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\r
 582                            SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */\r
 583 \r
 584            while (SysTick->VAL >= 100);                                                            /* wait for ~50µs  */\r
 585            SysTick->CTRL  &= ~SysTick_CTRL_ENABLE_Msk;                 /* Stop SysTick Timer */\r
 586            /********************************/\r
 587 \r
 588    /*********************************************************\r
 589            here the ramp up of the system clock starts FSys < 90MHz\r
 590            *********************************************************/\r
 591                 if (CLOCK_FSYS > 90000000){\r
 592                          /*calulation for stepping*/\r
 593                          if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)VCO = (CLOCK_CRYSTAL_FREQUENCY/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);\r
 594                          if ((SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC) ||(SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY))\r
 595                                         VCO = (CLOCK_BACK_UP/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1);\r
 596 \r
 597                          stepping_K2DIV = (VCO/90000000)-1;\r
 598 \r
 599                          /* Setup devider settings for main PLL */\r
 600                                 SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (stepping_K2DIV<<16) | (SCU_PLL_PDIV<<24));\r
 601                  }\r
 602                  else\r
 603                  {\r
 604                                 /* Setup devider settings for main PLL */\r
 605                                 SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (SCU_PLL_K2DIV<<16) | (SCU_PLL_PDIV<<24));\r
 606               SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_SOSCWDGT_Msk | SCU_TRAP_TRAPCLR_SVCOLCKT_Msk;  /* clear request for System OCS Watchdog Trap and System VCO Lock Trap  */\r
 607                                 return(1);\r
 608                  }\r
 609 \r
 610                  /*********************************************************/\r
 611                  /* Delay for next K2 step ~50µs */\r
 612                  /*********************************************************/\r
 613            SysTick->LOAD  = ((4800+100) & SysTick_LOAD_RELOAD_Msk) - 1;\r
 614            SysTick->VAL   = 0;                                         /* Load the SysTick Counter Value */\r
 615            SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\r
 616                            SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */\r
 617 \r
 618            while (SysTick->VAL >= 100);                                                            /* wait for ~50µs  */\r
 619            SysTick->CTRL  &= ~SysTick_CTRL_ENABLE_Msk;                 /* Stop SysTick Timer */\r
 620            /********************************/\r
 621 \r
 622            /* Setup devider settings for main PLL */\r
 623            SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (SCU_PLL_K2DIV<<16) | (SCU_PLL_PDIV<<24));\r
 624 \r
 625            SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_SOSCWDGT_Msk | SCU_TRAP_TRAPCLR_SVCOLCKT_Msk;  /* clear request for System OCS Watchdog Trap and System VCO Lock Trap  */\r
 626         }\r
 627  }/* end this weak function enables DAVE3 clock App usage */\r
 628    return(1);\r
 629 \r
 630 }\r
 631 #endif\r
 632 \r
 633 /**\r
 634   * @brief  -\r
 635   * @note   -\r
 636   * @param  None\r
 637   * @retval None\r
 638   */\r
 639 #if (SCU_USB_CLOCK_SETUP == 1)\r
 640 static int USBClockSetup(void)\r
 641 {\r
 642 /* this weak function enables DAVE3 clock App usage */\r
 643 if(AllowPLLInitByStartup()){\r
 644 \r
 645         /* check if PLL is switched on */\r
 646 if ((SCU_PLL->USBPLLCON &(SCU_PLL_USBPLLCON_VCOPWD_Msk | SCU_PLL_USBPLLCON_PLLPWD_Msk)) != 0){\r
 647         /* enable PLL first */\r
 648   SCU_PLL->USBPLLCON &= ~(SCU_PLL_USBPLLCON_VCOPWD_Msk | SCU_PLL_USBPLLCON_PLLPWD_Msk);\r
 649 }\r
 650 \r
 651 /* check and if not already running enable OSC_HP */\r
 652    if (SCU_OSC->OSCHPCTRL & SCU_OSC_OSCHPCTRL_MODE_Msk){\r
 653                  /* check if Main PLL is switched on for OSC WD*/\r
 654                  if ((SCU_PLL->PLLCON0 &(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk)) != 0){\r
 655                         /* enable PLL first */\r
 656                         SCU_PLL->PLLCON0 &= ~(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk);\r
 657                  }\r
 658            SCU_OSC->OSCHPCTRL &= ~(SCU_OSC_HP_MODE);     /*enable the OSC_HP*/\r
 659            /* setup OSC WDG devider */\r
 660            SCU_OSC->OSCHPCTRL |= (SCU_OSCHPWDGDIV<<16);\r
 661            /* restart OSC Watchdog */\r
 662            SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCRES_Msk;\r
 663 \r
 664        /* Timeout for wait loop ~150ms */\r
 665            /********************************/\r
 666            SysTick->LOAD  = ((5000000+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */\r
 667            SysTick->VAL   = 0;                                         /* Load the SysTick Counter Value */\r
 668            SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\r
 669                            SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */\r
 670            do\r
 671            {\r
 672        ;/* wait for ~150ms  */\r
 673            }while((((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380)&&(SysTick->VAL >= 500));\r
 674 \r
 675            SysTick->CTRL  &= ~SysTick_CTRL_ENABLE_Msk;                 /* Stop SysTick Timer */\r
 676            if (((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380)\r
 677            return(0);/* Return Error */\r
 678 \r
 679   }\r
 680 \r
 681 \r
 682 /* Setup USB PLL */\r
 683    /* Go to bypass the Main PLL */\r
 684    SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_VCOBYP_Msk;\r
 685    /* disconnect OSC_FI to PLL */\r
 686    SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_FINDIS_Msk;\r
 687    /* Setup devider settings for main PLL */\r
 688    SCU_PLL->USBPLLCON = ((SCU_USBPLL_NDIV<<8) | (SCU_USBPLL_PDIV<<24));\r
 689    /* Setup USBDIV settings USB clock */\r
 690    SCU_CLK->USBCLKCR = SCU_USBDIV;\r
 691    /* we may have to set OSCDISCDIS */\r
 692    SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_OSCDISCDIS_Msk;\r
 693    /* connect OSC_FI to PLL */\r
 694    SCU_PLL->USBPLLCON &= ~SCU_PLL_USBPLLCON_FINDIS_Msk;\r
 695    /* restart PLL Lock detection */\r
 696    SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_RESLD_Msk;\r
 697    /* wait for PLL Lock */\r
 698    while (!(SCU_PLL->USBPLLSTAT & SCU_PLL_USBPLLSTAT_VCOLOCK_Msk));\r
 699 \r
 700   }/* end this weak function enables DAVE3 clock App usage */\r
 701    return(1);\r
 702 \r
 703 }\r
 704 #endif\r
 705 \r