1 /***********************************************************************
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2 * $Id: emc_LPC43xx.c 8389 2011-10-19 13:53:14Z nxp28536 $ emc_LPC43xx.c
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4 * Project: NXP LPC43xx Common
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6 * Description: Initialisation of the external memory interface and
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7 * configuration for the specific memories connected to
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10 * Copyright(C) 2011, NXP Semiconductor
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11 * All rights reserved.
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13 ***********************************************************************
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14 * Software that is described herein is for illustrative purposes only
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15 * which provides customers with programming information regarding the
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16 * products. This software is supplied "AS IS" without any warranties.
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17 * NXP Semiconductors assumes no responsibility or liability for the
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18 * use of the software, conveys no license or title under any patent,
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19 * copyright, or mask work right to the product. NXP Semiconductors
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20 * reserves the right to make changes in the software without
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21 * notification. NXP Semiconductors also make no representation or
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22 * warranty that such application will be suitable for the specified
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23 * use without further testing or modification.
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24 **********************************************************************/
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26 #include "LPC43xx.h"
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27 #include "system_LPC43xx.h"
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30 #include "platform_config.h"
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32 #include "emc_LPC43xx.h"
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35 /**********************************************************************
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36 ** Function prototypes
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37 **********************************************************************/
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38 #define DELAY_1usFreq (1000000) // 1MHz equivalent to 1usec
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39 static uint32_t delayBase1us; // calculated depending on M4/EMI frequency
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40 static void vDelay(uint32_t u32Delay); // delay function
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44 /****************************************************************************************
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45 * Call the required memory setup functions from here
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48 ****************************************************************************************/
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49 void EMC_Init( void )
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51 // The address/data pins for the memory interface are required for the static and for
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53 EMC_Config_Pinmux();
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55 // Initialise the control signals for static memories
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56 #if (USE_EXT_STATIC_MEM == YES)
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58 // Initialise the control signals for static memories
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59 EMC_Config_Static();
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61 // #if (USE_EXT_DYNAMIC_MEM == NO)
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62 // LPC_EMC->CONTROL = 0x00000001; // Enable the external memory controller
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63 // LPC_EMC->CONFIG = 0;
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64 // // Buffers for the static memories are enabled as well. If there is SDRAM as well,
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65 // // then this is done after the initialisation for the dynamic memory interface.
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66 // LPC_EMC->STATICCONFIG0 = 0x00080081;
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71 #if (USE_EXT_DYNAMIC_MEM == YES)
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73 // The setup for dynamic memories (SDRAM)
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74 EMC_Init_SRDRAM(SDRAM_BASE, PART_WIDTH, PART_SIZE, EXT_WIDTH, COL_ADDR_BITS);
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76 #elif (USE_EXT_DYNAMIC_MEM == NO)
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78 LPC_EMC->CONTROL = 0x00000001; // Enable the external memory controller
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79 LPC_EMC->CONFIG = 0;
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83 // Buffers for the static memories can now be enabled as well. In a system with static and dynamic memory
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84 // this should only been done after the SDRAM initialisation --> here
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85 LPC_EMC->STATICCONFIG0 = 0x00080081;
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90 /****************************************************************************************
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91 * Set up the address/data pins for external memory interface in LP43xx
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93 * Modify this function in case not all of the address/data pins are needed.
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94 ****************************************************************************************/
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95 void EMC_Config_Pinmux(void)
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98 // Disable the external memory controller before changing pin control configuration
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99 LPC_EMC->CONTROL = 0x00000000;
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101 // EMC_OUT (PUP_CLEAR | SLEWRATE_FAST | FILTER_DISABLE)
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102 // EMC_IO (PUP_CLEAR | SLEWRATE_FAST | INBUF_ENABLE | FILTER_DISABLE)
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104 // Data line configuration
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105 scu_pinmux(0x1, 7, EMC_IO, FUNC3); // P1_7: D0
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106 scu_pinmux(0x1, 8, EMC_IO, FUNC3); // P1_8: D1
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107 scu_pinmux(0x1, 9, EMC_IO, FUNC3); // P1_9: D2
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108 scu_pinmux(0x1, 10, EMC_IO, FUNC3); // P1_10: D3
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109 scu_pinmux(0x1, 11, EMC_IO, FUNC3); // P1_11: D4
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110 scu_pinmux(0x1, 12, EMC_IO, FUNC3); // P1_12: D5
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111 scu_pinmux(0x1, 13, EMC_IO, FUNC3); // P1_13: D6
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112 scu_pinmux(0x1, 14, EMC_IO, FUNC3); // P1_14: D7
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113 scu_pinmux(0x5, 4, EMC_IO, FUNC2); // P5_4: D8
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114 scu_pinmux(0x5, 5, EMC_IO, FUNC2); // P5_5: D9
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115 scu_pinmux(0x5, 6, EMC_IO, FUNC2); // P5_6: D10
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116 scu_pinmux(0x5, 7, EMC_IO, FUNC2); // P5_7: D11
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117 scu_pinmux(0x5, 0, EMC_IO, FUNC2); // P5_0: D12
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118 scu_pinmux(0x5, 1, EMC_IO, FUNC2); // P5_1: D13
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119 scu_pinmux(0x5, 2, EMC_IO, FUNC2); // P5_2: D14
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120 scu_pinmux(0x5, 3, EMC_IO, FUNC2); // P5_3: D15
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121 scu_pinmux(0xD, 2, EMC_IO, FUNC2); // PD_2: D16
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122 scu_pinmux(0xD, 3, EMC_IO, FUNC2); // PD_3: D17
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123 scu_pinmux(0xD, 4, EMC_IO, FUNC2); // PD_4: D18
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124 scu_pinmux(0xD, 5, EMC_IO, FUNC2); // PD_5: D19
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125 scu_pinmux(0xD, 6, EMC_IO, FUNC2); // PD_6: D20
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126 scu_pinmux(0xD, 7, EMC_IO, FUNC2); // PD_7: D21
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127 scu_pinmux(0xD, 8, EMC_IO, FUNC2); // PD_8: D22
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128 scu_pinmux(0xD, 9, EMC_IO, FUNC2); // PD_9: D23
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129 scu_pinmux(0xE, 5, EMC_IO, FUNC3); // PE_5: D24
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130 scu_pinmux(0xE, 6, EMC_IO, FUNC3); // PE_6: D25
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131 scu_pinmux(0xE, 7, EMC_IO, FUNC3); // PE_7: D26
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132 scu_pinmux(0xE, 8, EMC_IO, FUNC3); // PE_8: D27
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133 scu_pinmux(0xE, 9, EMC_IO, FUNC3); // PE_9: D28
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134 scu_pinmux(0xE, 10, EMC_IO, FUNC3); // PE_10: D29
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135 scu_pinmux(0xE, 11, EMC_IO, FUNC3); // PE_11: D30
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136 scu_pinmux(0xE, 12, EMC_IO, FUNC3); // PE_12: D31
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138 // Address line configuration
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139 scu_pinmux(0x2, 9, EMC_IO, FUNC3); // P2_9: A0
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140 scu_pinmux(0x2, 10, EMC_IO, FUNC3); // P2_10: A1
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141 scu_pinmux(0x2, 11, EMC_IO, FUNC3); // P2_11: A2
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142 scu_pinmux(0x2, 12, EMC_IO, FUNC3); // P2_12: A3
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143 scu_pinmux(0x2, 13, EMC_IO, FUNC3); // P2_13: A4
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144 scu_pinmux(0x1, 0, EMC_IO, FUNC2); // P1_0: A5
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145 scu_pinmux(0x1, 1, EMC_IO, FUNC2); // P1_1: A6
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146 scu_pinmux(0x1, 2, EMC_IO, FUNC2); // P1_2: A7
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147 scu_pinmux(0x2, 8, EMC_IO, FUNC3); // P2_8: A8
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148 scu_pinmux(0x2, 7, EMC_IO, FUNC3); // P2_7: A9
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149 scu_pinmux(0x2, 6, EMC_IO, FUNC2); // P2_6: A10
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150 scu_pinmux(0x2, 2, EMC_IO, FUNC2); // P2_2: A11
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151 scu_pinmux(0x2, 1, EMC_IO, FUNC2); // P2_0: A12
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152 scu_pinmux(0x2, 0, EMC_IO, FUNC2); // P2_0: A13
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153 scu_pinmux(0x6, 8, EMC_IO, FUNC1); // P6_8: A14
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154 scu_pinmux(0x6, 7, EMC_IO, FUNC1); // P6_7: A15
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155 scu_pinmux(0xD, 16, EMC_IO, FUNC2); // PD_16: A16
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156 scu_pinmux(0xD, 15, EMC_IO, FUNC2); // PD_15: A17
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157 scu_pinmux(0xE, 0, EMC_IO, FUNC3); // PE_0: A18
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158 scu_pinmux(0xE, 1, EMC_IO, FUNC3); // PE_1: A19
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159 scu_pinmux(0xE, 2, EMC_IO, FUNC3); // PE_2: A20
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160 scu_pinmux(0xE, 3, EMC_IO, FUNC3); // PE_3: A21
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161 scu_pinmux(0xE, 4, EMC_IO, FUNC3); // PE_4: A22
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163 // Control signals for static memory
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164 scu_pinmux(0x1, 6, EMC_IO, FUNC3); // P1_6: WE
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165 scu_pinmux(0x1, 5, EMC_IO, FUNC3); // P1_5: CS0
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166 scu_pinmux(0x1, 3, EMC_IO, FUNC3); // P1_6: OE
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167 scu_pinmux(0x1, 4, EMC_IO, FUNC3); // P1_5: BLS0
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168 scu_pinmux(0x6, 6, EMC_IO, FUNC1); // P1_6: BLS1
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169 scu_pinmux(0xD, 12, EMC_IO, FUNC2); // PD_12: CS2
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171 #if (USE_EXT_DYNAMIC_MEM == YES)
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172 // Control signals for dynamic memory
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173 scu_pinmux(0x6, 9, EMC_IO, FUNC3); // P6_9: DYCS0
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174 scu_pinmux(0x6, 4, EMC_IO, FUNC3); // P6_4: CAS
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175 scu_pinmux(0x6, 5, EMC_IO, FUNC3); // P6_5: RAS
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176 scu_pinmux(0x6, 11, EMC_IO, FUNC3); // P6_11: CKEOUT0
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177 scu_pinmux(0x6, 12, EMC_IO, FUNC3); // P6_12: DQMOUT0
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178 scu_pinmux(0x6, 10, EMC_IO, FUNC3); // P6_10: DQMOUT1
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180 LPC_SCU_CLK(0) = 0 + EMC_IO; // EMC_CLK0 signal on pin CLK0 (needed for SDRAM)
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181 LPC_SCU_CLK(1) = 0 + EMC_IO;
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182 LPC_SCU_CLK(2) = 0 + EMC_IO;
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183 LPC_SCU_CLK(3) = 0 + EMC_IO;
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189 /****************************************************************************************
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190 * Configure CS0 for 70ns 16-bit flash memory on the Hitex board
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191 * Configure CS2 for 55ns 16-bit SRAM on the Hitex board
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193 ****************************************************************************************/
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194 void EMC_Config_Static(void)
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197 // Configure CS0 for flash memory
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198 // @120MHz there should be 8 or 9 waitstates for the 70ns flash, apparently it works with 7
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199 LPC_EMC->STATICCONFIG0 = 0x00000081; // CS0: 16 bit = WE
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200 LPC_EMC->STATICWAITOEN0 = 0; // CS0: WAITOEN = 0
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202 #if (PLATFORM == HITEX_A2_BOARD)
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204 LPC_EMC->STATICWAITRD0 = 7; // CS0: WAITRD = 7
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206 // The Hitex board has external SRAM on CS2
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207 // @120MHz there should be 7 waitstates for the 55ns SRAM, it should work with 6
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208 LPC_EMC->STATICCONFIG0 = 0x00000081; // CS2: 16 bit = WE
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209 LPC_EMC->STATICWAITOEN2 = 0; // CS2: WAITOEN = 0
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210 LPC_EMC->STATICWAITRD2 = 7; // CS2: WAITRD = 6
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212 #elif (PLATFORM == NXP_VALIDATION_BOARD)
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214 LPC_EMC->STATICWAITRD0 = check 9; // CS0: WAITRD = 8
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217 LPC_EMC->STATICCONFIG0 = check 0x00000081; // CS2: 16 bit = WE
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218 LPC_EMC->STATICWAITOEN2 = check 0; // CS2: WAITOEN = 0
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219 LPC_EMC->STATICWAITRD2 = check 7; // CS2: WAITRD = 6
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226 // Defines for EMC signal delay settings
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227 #define EMC_B_ENABLE (1 << 19)
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228 #define EMC_ENABLE (1 << 0)
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229 #define EMC_CE_ENABLE (1 << 0)
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230 #define EMC_CS_ENABLE (1 << 1)
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231 #define EMC_CLOCK_DELAYED_STRATEGY (0 << 0)
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232 #define EMC_COMMAND_DELAYED_STRATEGY (1 << 0)
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233 #define EMC_COMMAND_DELAYED_STRATEGY2 (2 << 0)
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234 #define EMC_COMMAND_DELAYED_STRATEGY3 (3 << 0)
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235 #define EMC_INIT(i) ((i) << 7)
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236 #define EMC_NORMAL (0)
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237 #define EMC_MODE (1)
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238 #define EMC_PRECHARGE_ALL (2)
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239 #define EMC_NOP (3)
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241 /****************************************************************************************
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242 * Configure the delays for the SDRAM
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244 * - on the Hitex board (IS42S16400D-7TL)
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245 * - on the NXP evaluation board (MT48LC4M32B2)
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246 * - on the NXP validation board (MT48LC4M32B2)
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248 ****************************************************************************************/
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249 #if (PLATFORM == HITEX_A2_BOARD) || (PLATFORM == NXP_VALIDATION_BOARD)
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251 // Defines for SDRAM devices
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252 #define DOUT_DELAY 0
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253 #define CLK0_DELAY 5
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254 #define CLKE0_DELAY 5
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255 #define RAS_DELAY 0
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256 #define CAS_DELAY 0
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258 #define DYCS0_DELAY 0
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259 #define DQM0_DELAY 0
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260 #define FBCLK0_DELAY 0
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261 #define CCLK_DELAY 0
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262 #define ADDR_DELAY 0
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263 #define DIN_DELAY 0
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264 #define DEN_DELAY 0
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268 void initEmiDelays(void)
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270 // eventually configure delays, defaults are zero
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272 // CLK & CLKE0 delay
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273 *(uint32_t*)(LPC_SCU_BASE + 0xD00) = ((CLK0_DELAY << 16) | (CLKE0_DELAY << 0) );
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275 // EMCCTRLDELAY, address 0x4008 6D04
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276 *(uint32_t*)(LPC_SCU_BASE + 0xD04) = ((WE_DELAY << 12)| (CAS_DELAY << 4) | (RAS_DELAY << 0) );
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278 // DYCS0_DELAY, address 0x4008 6D08
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279 *(uint32_t*)(LPC_SCU_BASE + 0xD08) = ((DYCS0_DELAY << 0));
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281 // data out delay for D0 to D31 EMCDOUTDELAY
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282 *(uint32_t*)(LPC_SCU_BASE + 0xD0C) = ((DOUT_DELAY << 28) | (DOUT_DELAY << 24) | (DOUT_DELAY << 20) | (DOUT_DELAY << 16)|(DQM0_DELAY << 12) | (DQM0_DELAY << 8) | (DQM0_DELAY << 4) | (DQM0_DELAY << 0)) ;
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284 // EMCFBCLKDELAY, address 0x4008 6D10
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285 *(uint32_t*)(LPC_SCU_BASE + 0xD10) = ((CCLK_DELAY << 16)|(FBCLK0_DELAY << 12) | (FBCLK0_DELAY << 8) | (FBCLK0_DELAY << 4) | (FBCLK0_DELAY << 0)) ;
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287 // EMCADDRDELAY, address 0x4008 6D14, 0x4008 6D18, 0x4008 6D1C)
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288 *(uint32_t*)(LPC_SCU_BASE + 0xD14) = ((ADDR_DELAY << 28)|(ADDR_DELAY << 24)|(ADDR_DELAY << 20)|(ADDR_DELAY << 16)|(ADDR_DELAY << 12) | (ADDR_DELAY << 8) | (ADDR_DELAY << 4) | (ADDR_DELAY << 0)) ;
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289 *(uint32_t*)(LPC_SCU_BASE + 0xD18) = ((ADDR_DELAY << 28)|(ADDR_DELAY << 24)|(ADDR_DELAY << 20)|(ADDR_DELAY << 16)|(ADDR_DELAY << 12) | (ADDR_DELAY << 8) | (ADDR_DELAY << 4) | (ADDR_DELAY << 0)) ;
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290 *(uint32_t*)(LPC_SCU_BASE + 0xD1C) = ((ADDR_DELAY << 28)|(ADDR_DELAY << 24)|(ADDR_DELAY << 20)|(ADDR_DELAY << 16)|(ADDR_DELAY << 12) | (ADDR_DELAY << 8) | (ADDR_DELAY << 4) | (ADDR_DELAY << 0)) ;
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292 // data in delay for D0 to D31 EMCDINDELAY
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293 *(uint32_t*)(LPC_SCU_BASE + 0xD24) = ((DEN_DELAY << 28)|(DEN_DELAY << 24)|(DEN_DELAY << 20)|(DEN_DELAY << 16)|(DIN_DELAY << 12)|(DIN_DELAY << 8)|(DIN_DELAY << 4)|(DIN_DELAY << 0));
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299 /****************************************************************************************
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300 * Configure the EMI for the SDRAM
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302 * - on the Hitex board (IS42S16400D-7TL)
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303 * - on the NXP validation board (MT48LC4M32B2)
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305 ****************************************************************************************/
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306 void EMC_Init_SRDRAM(uint32_t u32BaseAddr, uint32_t u32Width, uint32_t u32Size, uint32_t u32DataBus, uint32_t u32ColAddrBits)
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309 // calculate a 1 usec delay base
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310 delayBase1us = M4Frequency / DELAY_1usFreq;
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312 // eventually adjust the CCU delays for EMI (default to zero)
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315 // Initialize EMC to interface with SDRAM. The EMC needs to run for this.
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316 LPC_EMC->CONTROL = 0x00000001; // (Re-)enable the external memory controller
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317 LPC_EMC->CONFIG = 0;
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319 #if (PLATFORM == HITEX_A2_BOARD)
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321 LPC_EMC->DYNAMICCONFIG0 = ((u32Width << 7) | (u32Size << 9) | (u32DataBus << 14)); // Selects the configuration information for dynamic memory chip select 0.
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322 LPC_EMC->DYNAMICRASCAS0 = (2UL << 0) | (2UL << 8); // Selects the RAS and CAS latencies for dynamic memory chip select 0.
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323 LPC_EMC->DYNAMICREADCONFIG = EMC_COMMAND_DELAYED_STRATEGY; // Configures the dynamic memory read strategy.
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324 LPC_EMC->DYNAMICRP = 1; // Selects the precharge command period
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325 LPC_EMC->DYNAMICRAS = 3; // Selects the active to precharge command period
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326 LPC_EMC->DYNAMICSREX = 5; // Selects the self-refresh exit time
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327 LPC_EMC->DYNAMICAPR = 0; // Selects the last-data-out to active command time
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328 LPC_EMC->DYNAMICDAL = 4; // Selects the data-in to active command time.
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329 LPC_EMC->DYNAMICWR = 1; // Selects the write recovery time
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330 LPC_EMC->DYNAMICRC = 5; // Selects the active to active command period
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331 LPC_EMC->DYNAMICRFC = 5; // Selects the auto-refresh period
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332 LPC_EMC->DYNAMICXSR = 5; // Selects the exit self-refresh to active command time
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333 LPC_EMC->DYNAMICRRD = 0; // Selects the active bank A to active bank B latency
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334 LPC_EMC->DYNAMICMRD = 0; // Selects the load mode register to active command time
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336 LPC_EMC->DYNAMICCONTROL = EMC_CE_ENABLE | EMC_CS_ENABLE | EMC_INIT(EMC_NOP);
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339 LPC_EMC->DYNAMICCONTROL = EMC_CE_ENABLE | EMC_CS_ENABLE | EMC_INIT(EMC_PRECHARGE_ALL);
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341 LPC_EMC->DYNAMICREFRESH = 2; // Configures dynamic memory refresh operation
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344 LPC_EMC->DYNAMICREFRESH = 83; // Configures dynamic memory refresh operation
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346 LPC_EMC->DYNAMICCONTROL = EMC_CE_ENABLE | EMC_CS_ENABLE | EMC_INIT(EMC_MODE);
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348 // Write configuration data to SDRAM device
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349 if(u32DataBus == 0) // 16-bit data bus, the EMC enforces a burst size 8
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351 *((volatile uint32_t *)(u32BaseAddr | ((3UL | (2UL << 4)) << (u32ColAddrBits + 2 + 1))));
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353 else // burst size 4 (which is not an option for 16-bit data bus anyway)
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355 *((volatile uint32_t *)(u32BaseAddr | ((2UL | (2UL << 4)) << (u32ColAddrBits + 2 + 2))));
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357 #endif // HITEX_BOARD
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360 #if (PLATFORM == NXP_VALIDATION_BOARD)
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362 LPC_EMC->DYNAMICCONFIG0 = ((u32Width << 7) | (u32Size << 9) | (u32DataBus << 14));
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363 LPC_EMC->DYNAMICRASCAS0 = (2UL << 0) | (2UL << 8);
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364 LPC_EMC->DYNAMICREADCONFIG = EMC_COMMAND_DELAYED_STRATEGY;
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365 LPC_EMC->DYNAMICRP = 1; // calculated from xls sheet
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366 LPC_EMC->DYNAMICRAS = 2;
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367 LPC_EMC->DYNAMICSREX = 5;
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368 LPC_EMC->DYNAMICAPR = 0;
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369 LPC_EMC->DYNAMICDAL = 4;
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370 LPC_EMC->DYNAMICWR = 1;
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371 LPC_EMC->DYNAMICRC = 5;
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372 LPC_EMC->DYNAMICRFC = 5;
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373 LPC_EMC->DYNAMICXSR = 5;
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374 LPC_EMC->DYNAMICRRD = 0;
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375 LPC_EMC->DYNAMICMRD = 0;
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377 LPC_EMC->DYNAMICCONTROL = EMC_CE_ENABLE | EMC_CS_ENABLE | EMC_INIT(EMC_NOP);
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380 LPC_EMC->DYNAMICCONTROL = EMC_CE_ENABLE | EMC_CS_ENABLE | EMC_INIT(EMC_PRECHARGE_ALL);
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382 LPC_EMC->DYNAMICREFRESH = 2;
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385 LPC_EMC->DYNAMICREFRESH = 83;
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387 LPC_EMC->DYNAMICCONTROL = EMC_CE_ENABLE | EMC_CS_ENABLE | EMC_INIT(EMC_MODE);
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389 // Write configuration data to SDRAM device
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390 if(u32DataBus == 0) // burst size 8
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392 *((volatile uint32_t *)(u32BaseAddr | ((3UL | (2UL << 4)) << (u32ColAddrBits + 2 + 1))));
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394 else // burst size 4
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396 *((volatile uint32_t *)(u32BaseAddr | ((2UL | (2UL << 4)) << (u32ColAddrBits + 2 + 2))));
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398 #endif // Validation board
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400 LPC_EMC->DYNAMICCONTROL = 0;
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401 LPC_EMC->DYNAMICCONFIG0 |= EMC_B_ENABLE; // Enable the buffers
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406 /**********************************************************************
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414 **********************************************************************/
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415 static void vDelay(uint32_t u32Delay)
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417 volatile uint32_t i;
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419 for(i = 0; i < (u32Delay * delayBase1us); i++);
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