1 //*****************************************************************************
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3 // Copyright (C) 2012 - 2015 Texas Instruments Incorporated - http://www.ti.com/
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5 // Redistribution and use in source and binary forms, with or without
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6 // modification, are permitted provided that the following conditions
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9 // Redistributions of source code must retain the above copyright
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10 // notice, this list of conditions and the following disclaimer.
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12 // Redistributions in binary form must reproduce the above copyright
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13 // notice, this list of conditions and the following disclaimer in the
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14 // documentation and/or other materials provided with the
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17 // Neither the name of Texas Instruments Incorporated nor the names of
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18 // its contributors may be used to endorse or promote products derived
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19 // from this software without specific prior written permission.
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21 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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22 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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23 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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24 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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25 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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26 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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27 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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28 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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29 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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30 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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31 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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33 // MSP432P401R Register Definitions
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35 // This file includes definitions that are compatible with MSP430 code,
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36 // and additionally CMSIS compliant definitions
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38 // When using MSP430 definitions the physical registers can be directly
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40 // - ADC14CTL0 |= ADC14SSEL__ACLK;
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42 // When using CMSIS definitions, the register and bit defines have been
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43 // reformatted and shortened.
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44 // - Registers: ModuleName[ModuleInstance]->rRegisterName.r
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45 // - Bits: ModuleName[ModuleInstance]->rRegisterName.b.bBitName
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46 // - Alternate Bits: ModuleName[ModuleInstance]->rRegisterName.a.bBitName
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48 // Writing to CMSIS bit fields can be done through both register level
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49 // access or bit level access, e.g.
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50 // - ADC14->rCTL0.r |= ADC14SSEL__ACLK;
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51 // - ADC14->rCTL0.b.bSSEL = ADC14SSEL__ACLK >> ADC14SSEL_OFS;
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53 // File creation date: 2015-01-05
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55 //****************************************************************************
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57 #ifndef __MSP432P401R_H__
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58 #define __MSP432P401R_H__
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60 // Use standard integer types with explicit width
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63 // Remap MSP430 intrinsics to ARM equivalents
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64 #include "msp_compatibility.h"
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66 //*****************************************************************************
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67 // CMSIS-compatible Interrupt Number Definition
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68 //*****************************************************************************
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69 #ifndef __CMSIS_CONFIG__
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70 #define __CMSIS_CONFIG__
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74 // Cortex-M4 Processor Exceptions Numbers
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75 NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */
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76 HardFault_IRQn = -13, /* 3 Hard Fault Interrupt */
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77 MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */
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78 BusFault_IRQn = -11, /* 5 Bus Fault Interrupt */
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79 UsageFault_IRQn = -10, /* 6 Usage Fault Interrupt */
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80 SVCall_IRQn = -5, /* 11 SV Call Interrupt */
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81 DebugMonitor_IRQn = -4, /* 12 Debug Monitor Interrupt */
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82 PendSV_IRQn = -2, /* 14 Pend SV Interrupt */
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83 SysTick_IRQn = -1, /* 15 System Tick Interrupt */
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84 // Peripheral Exceptions Numbers
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85 PSS_IRQn = 0, /* 16 PSS Interrupt */
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86 CS_IRQn = 1, /* 17 CS Interrupt */
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87 PCM_IRQn = 2, /* 18 PCM Interrupt */
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88 WDT_A_IRQn = 3, /* 19 WDT_A Interrupt */
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89 FPU_IRQn = 4, /* 20 FPU Interrupt */
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90 FLCTL_IRQn = 5, /* 21 FLCTL Interrupt */
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91 COMP_E0_IRQn = 6, /* 22 COMP_E0 Interrupt */
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92 COMP_E1_IRQn = 7, /* 23 COMP_E1 Interrupt */
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93 TA0_0_IRQn = 8, /* 24 TA0_0 Interrupt */
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94 TA0_N_IRQn = 9, /* 25 TA0_N Interrupt */
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95 TA1_0_IRQn = 10, /* 26 TA1_0 Interrupt */
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96 TA1_N_IRQn = 11, /* 27 TA1_N Interrupt */
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97 TA2_0_IRQn = 12, /* 28 TA2_0 Interrupt */
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98 TA2_N_IRQn = 13, /* 29 TA2_N Interrupt */
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99 TA3_0_IRQn = 14, /* 30 TA3_0 Interrupt */
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100 TA3_N_IRQn = 15, /* 31 TA3_N Interrupt */
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101 EUSCIA0_IRQn = 16, /* 32 EUSCIA0 Interrupt */
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102 EUSCIA1_IRQn = 17, /* 33 EUSCIA1 Interrupt */
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103 EUSCIA2_IRQn = 18, /* 34 EUSCIA2 Interrupt */
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104 EUSCIA3_IRQn = 19, /* 35 EUSCIA3 Interrupt */
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105 EUSCIB0_IRQn = 20, /* 36 EUSCIB0 Interrupt */
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106 EUSCIB1_IRQn = 21, /* 37 EUSCIB1 Interrupt */
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107 EUSCIB2_IRQn = 22, /* 38 EUSCIB2 Interrupt */
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108 EUSCIB3_IRQn = 23, /* 39 EUSCIB3 Interrupt */
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109 ADC14_IRQn = 24, /* 40 ADC14 Interrupt */
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110 T32_INT1_IRQn = 25, /* 41 T32_INT1 Interrupt */
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111 T32_INT2_IRQn = 26, /* 42 T32_INT2 Interrupt */
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112 T32_INTC_IRQn = 27, /* 43 T32_INTC Interrupt */
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113 AES256_IRQn = 28, /* 44 AES256 Interrupt */
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114 RTC_C_IRQn = 29, /* 45 RTC_C Interrupt */
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115 DMA_ERR_IRQn = 30, /* 46 DMA_ERR Interrupt */
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116 DMA_INT3_IRQn = 31, /* 47 DMA_INT3 Interrupt */
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117 DMA_INT2_IRQn = 32, /* 48 DMA_INT2 Interrupt */
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118 DMA_INT1_IRQn = 33, /* 49 DMA_INT1 Interrupt */
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119 DMA_INT0_IRQn = 34, /* 50 DMA_INT0 Interrupt */
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120 PORT1_IRQn = 35, /* 51 PORT1 Interrupt */
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121 PORT2_IRQn = 36, /* 52 PORT2 Interrupt */
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122 PORT3_IRQn = 37, /* 53 PORT3 Interrupt */
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123 PORT4_IRQn = 38, /* 54 PORT4 Interrupt */
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124 PORT5_IRQn = 39, /* 55 PORT5 Interrupt */
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125 PORT6_IRQn = 40 /* 56 PORT6 Interrupt */
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128 //*****************************************************************************
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129 // CMSIS-compatible configuration of the Cortex-M4 Processor and Core Peripherals
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130 //*****************************************************************************
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131 #define __MPU_PRESENT 1 // MPU present or not
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132 #define __NVIC_PRIO_BITS 3 // Number of Bits used for Prio Levels
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133 #define __FPU_PRESENT 1 // FPU present or not
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135 #endif // __CMSIS_CONFIG__
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137 // Include CMSIS Cortex-M4 Core Peripheral Access Layer Header File
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140 #pragma CHECK_ULP("none")
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141 #include "core_cm4.h"
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144 #include "core_cm4.h"
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147 //*****************************************************************************
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148 // Definition of standard bits
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149 //*****************************************************************************
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150 #define BIT0 (0x0001u)
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151 #define BIT1 (0x0002u)
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152 #define BIT2 (0x0004u)
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153 #define BIT3 (0x0008u)
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154 #define BIT4 (0x0010u)
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155 #define BIT5 (0x0020u)
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156 #define BIT6 (0x0040u)
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157 #define BIT7 (0x0080u)
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158 #define BIT8 (0x0100u)
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159 #define BIT9 (0x0200u)
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160 #define BITA (0x0400u)
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161 #define BITB (0x0800u)
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162 #define BITC (0x1000u)
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163 #define BITD (0x2000u)
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164 #define BITE (0x4000u)
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165 #define BITF (0x8000u)
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166 #define BIT(x) (1 << (x))
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168 //*****************************************************************************
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169 // Definitions for 8/16/32-bit wide memory access
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170 //*****************************************************************************
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171 #define HWREG8(x) (*((volatile uint8_t *)(x)))
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172 #define HWREG16(x) (*((volatile uint16_t *)(x)))
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173 #define HWREG32(x) (*((volatile uint32_t *)(x)))
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174 #define HWREG(x) (HWREG16(x))
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175 #define HWREG8_L(x) (*((volatile uint8_t *)((uint8_t *)&x)))
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176 #define HWREG8_H(x) (*((volatile uint8_t *)(((uint8_t *)&x)+1)))
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177 #define HWREG16_L(x) (*((volatile uint16_t *)((uint16_t *)&x)))
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178 #define HWREG16_H(x) (*((volatile uint16_t *)(((uint16_t *)&x)+1)))
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180 //*****************************************************************************
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181 // Definitions for 8/16/32-bit wide bit band access
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182 //*****************************************************************************
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183 #define HWREGBIT8(x, b) (HWREG8(((uint32_t)(x) & 0xF0000000) | 0x02000000 | (((uint32_t)(x) & 0x000FFFFF) << 5) | ((b) << 2)))
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184 #define HWREGBIT16(x, b) (HWREG16(((uint32_t)(x) & 0xF0000000) | 0x02000000 | (((uint32_t)(x) & 0x000FFFFF) << 5) | ((b) << 2)))
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185 #define HWREGBIT32(x, b) (HWREG32(((uint32_t)(x) & 0xF0000000) | 0x02000000 | (((uint32_t)(x) & 0x000FFFFF) << 5) | ((b) << 2)))
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186 #define BITBAND_SRAM(x, b) (*((volatile uint8_t *) (0x22000000 + (((uint32_t)(uint32_t *)&x) - 0x20000000)*32 + b*4)))
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187 #define BITBAND_PERI(x, b) (*((volatile uint8_t *) (0x42000000 + (((uint32_t)(uint32_t *)&x) - 0x40000000)*32 + b*4)))
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189 //*****************************************************************************
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190 // Device memory map
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191 //*****************************************************************************
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192 #define __MAIN_MEMORY_START__ (0x00000000) /* Main Flash memory start address */
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193 #define __MAIN_MEMORY_END__ (0x0003FFFF) /* Main Flash memory end address */
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194 #define __BSL_MEMORY_START__ (0x00202000) /* BSL memory start address */
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195 #define __BSL_MEMORY_END__ (0x00203FFF) /* BSL memory end address */
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196 #define __SRAM_START__ (0x20000000) /* SRAM memory start address */
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197 #define __SRAM_END__ (0x2000FFFF) /* SRAM memory end address */
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199 //*****************************************************************************
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200 // Peripheral memory map
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201 //*****************************************************************************
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202 #define __MCU_HAS_ADC14__ /* Module is available */
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203 #define __MCU_HAS_AES256__ /* Module is available */
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204 #define __MCU_HAS_CAPTIO0__ /* Module is available */
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205 #define __MCU_HAS_CAPTIO1__ /* Module is available */
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206 #define __MCU_HAS_COMP_E0__ /* Module is available */
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207 #define __MCU_HAS_COMP_E1__ /* Module is available */
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208 #define __MCU_HAS_CRC32__ /* Module is available */
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209 #define __MCU_HAS_CS__ /* Module is available */
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210 #define __MCU_HAS_DIO__ /* Module is available */
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211 #define __MCU_HAS_DMA__ /* Module is available */
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212 #define __MCU_HAS_EUSCI_A0__ /* Module is available */
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213 #define __MCU_HAS_EUSCI_A1__ /* Module is available */
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214 #define __MCU_HAS_EUSCI_A2__ /* Module is available */
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215 #define __MCU_HAS_EUSCI_A3__ /* Module is available */
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216 #define __MCU_HAS_EUSCI_B0__ /* Module is available */
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217 #define __MCU_HAS_EUSCI_B1__ /* Module is available */
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218 #define __MCU_HAS_EUSCI_B2__ /* Module is available */
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219 #define __MCU_HAS_EUSCI_B3__ /* Module is available */
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220 #define __MCU_HAS_FLCTL__ /* Module is available */
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221 #define __MCU_HAS_FPB__ /* Module is available */
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222 #define __MCU_HAS_PCM__ /* Module is available */
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223 #define __MCU_HAS_PMAP__ /* Module is available */
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224 #define __MCU_HAS_PSS__ /* Module is available */
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225 #define __MCU_HAS_REF_A__ /* Module is available */
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226 #define __MCU_HAS_RSTCTL__ /* Module is available */
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227 #define __MCU_HAS_RTC_C__ /* Module is available */
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228 #define __MCU_HAS_SYSCTL__ /* Module is available */
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229 #define __MCU_HAS_TIMER32__ /* Module is available */
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230 #define __MCU_HAS_TIMER_A0__ /* Module is available */
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231 #define __MCU_HAS_TIMER_A1__ /* Module is available */
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232 #define __MCU_HAS_TIMER_A2__ /* Module is available */
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233 #define __MCU_HAS_TIMER_A3__ /* Module is available */
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234 #define __MCU_HAS_TLV__ /* Module is available */
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235 #define __MCU_HAS_WDT_A__ /* Module is available */
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237 #define ADC14_BASE (0x40012000) /* Base address of module registers */
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238 #define ADC14_MODULE (0x40012000) /* Base address of module registers */
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239 #define AES256_BASE (0x40003C00) /* Base address of module registers */
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240 #define AES256_MODULE (0x40003C00) /* Base address of module registers */
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241 #define CAPTIO0_BASE (0x40005400) /* Base address of module registers */
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242 #define CAPTIO0_MODULE (0x40005400) /* Base address of module registers */
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243 #define CAPTIO1_BASE (0x40005800) /* Base address of module registers */
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244 #define CAPTIO1_MODULE (0x40005800) /* Base address of module registers */
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245 #define COMP_E0_BASE (0x40003400) /* Base address of module registers */
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246 #define COMP_E0_MODULE (0x40003400) /* Base address of module registers */
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247 #define COMP_E1_BASE (0x40003800) /* Base address of module registers */
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248 #define COMP_E1_MODULE (0x40003800) /* Base address of module registers */
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249 #define CRC32_BASE (0x40004000) /* Base address of module registers */
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250 #define CRC32_MODULE (0x40004000) /* Base address of module registers */
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251 #define CS_BASE (0x40010400) /* Base address of module registers */
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252 #define CS_MODULE (0x40010400) /* Base address of module registers */
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253 #define DIO_BASE (0x40004C00) /* Base address of module registers */
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254 #define DIO_MODULE (0x40004C00) /* Base address of module registers */
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255 #define DMA_BASE (0x4000E000) /* Base address of module registers */
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256 #define DMA_MODULE (0x4000E000) /* Base address of module registers */
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257 #define EUSCI_A0_BASE (0x40001000) /* Base address of module registers */
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258 #define EUSCI_A0_MODULE (0x40001000) /* Base address of module registers */
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259 #define EUSCI_A1_BASE (0x40001400) /* Base address of module registers */
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260 #define EUSCI_A1_MODULE (0x40001400) /* Base address of module registers */
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261 #define EUSCI_A2_BASE (0x40001800) /* Base address of module registers */
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262 #define EUSCI_A2_MODULE (0x40001800) /* Base address of module registers */
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263 #define EUSCI_A3_BASE (0x40001C00) /* Base address of module registers */
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264 #define EUSCI_A3_MODULE (0x40001C00) /* Base address of module registers */
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265 #define EUSCI_B0_BASE (0x40002000) /* Base address of module registers */
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266 #define EUSCI_B0_MODULE (0x40002000) /* Base address of module registers */
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267 #define EUSCI_B1_BASE (0x40002400) /* Base address of module registers */
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268 #define EUSCI_B1_MODULE (0x40002400) /* Base address of module registers */
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269 #define EUSCI_B2_BASE (0x40002800) /* Base address of module registers */
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270 #define EUSCI_B2_MODULE (0x40002800) /* Base address of module registers */
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271 #define EUSCI_B3_BASE (0x40002C00) /* Base address of module registers */
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272 #define EUSCI_B3_MODULE (0x40002C00) /* Base address of module registers */
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273 #define FLCTL_BASE (0x40011000) /* Base address of module registers */
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274 #define FLCTL_MODULE (0x40011000) /* Base address of module registers */
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275 #define FPB_BASE (0xE0002000) /* Base address of module registers */
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276 #define FPB_MODULE (0xE0002000) /* Base address of module registers */
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277 #define PCM_BASE (0x40010000) /* Base address of module registers */
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278 #define PCM_MODULE (0x40010000) /* Base address of module registers */
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279 #define PMAP_BASE (0x40005000) /* Base address of module registers */
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280 #define PMAP_MODULE (0x40005000) /* Base address of module registers */
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281 #define PSS_BASE (0x40010800) /* Base address of module registers */
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282 #define PSS_MODULE (0x40010800) /* Base address of module registers */
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283 #define REF_A_BASE (0x40003000) /* Base address of module registers */
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284 #define REF_A_MODULE (0x40003000) /* Base address of module registers */
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285 #define RSTCTL_BASE (0xE0042000) /* Base address of module registers */
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286 #define RSTCTL_MODULE (0xE0042000) /* Base address of module registers */
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287 #define RTC_C_BASE (0x40004400) /* Base address of module registers */
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288 #define RTC_C_MODULE (0x40004400) /* Base address of module registers */
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289 #define SYSCTL_BASE (0xE0043000) /* Base address of module registers */
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290 #define SYSCTL_MODULE (0xE0043000) /* Base address of module registers */
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291 #define TIMER32_BASE (0x4000C000) /* Base address of module registers */
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292 #define TIMER32_MODULE (0x4000C000) /* Base address of module registers */
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293 #define TIMER_A0_BASE (0x40000000) /* Base address of module registers */
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294 #define TIMER_A0_MODULE (0x40000000) /* Base address of module registers */
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295 #define TIMER_A1_BASE (0x40000400) /* Base address of module registers */
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296 #define TIMER_A1_MODULE (0x40000400) /* Base address of module registers */
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297 #define TIMER_A2_BASE (0x40000800) /* Base address of module registers */
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298 #define TIMER_A2_MODULE (0x40000800) /* Base address of module registers */
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299 #define TIMER_A3_BASE (0x40000C00) /* Base address of module registers */
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300 #define TIMER_A3_MODULE (0x40000C00) /* Base address of module registers */
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301 #define TLV_BASE (0x00201000) /* Base address of module registers */
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302 #define TLV_MODULE (0x00201000) /* Base address of module registers */
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303 #define WDT_A_BASE (0x40004800) /* Base address of module registers */
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304 #define WDT_A_MODULE (0x40004800) /* Base address of module registers */
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306 #define ADC14 ((ADC14_Type *) ADC14_BASE)
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307 #define AES256 ((AES256_Type *) AES256_BASE)
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308 #define CAPTIO0 ((CAPTIO0_Type *) CAPTIO0_BASE)
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309 #define CAPTIO1 ((CAPTIO1_Type *) CAPTIO1_BASE)
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310 #define COMP_E0 ((COMP_E0_Type *) COMP_E0_BASE)
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311 #define COMP_E1 ((COMP_E1_Type *) COMP_E1_BASE)
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312 #define CRC32 ((CRC32_Type *) CRC32_BASE)
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313 #define CS ((CS_Type *) CS_BASE)
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314 #define DIO ((DIO_Type *) DIO_BASE)
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315 #define DMA ((DMA_Type *) DMA_BASE)
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316 #define EUSCI_A0 ((EUSCI_A0_Type *) EUSCI_A0_BASE)
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317 #define EUSCI_A1 ((EUSCI_A1_Type *) EUSCI_A1_BASE)
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318 #define EUSCI_A2 ((EUSCI_A2_Type *) EUSCI_A2_BASE)
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319 #define EUSCI_A3 ((EUSCI_A3_Type *) EUSCI_A3_BASE)
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320 #define EUSCI_B0 ((EUSCI_B0_Type *) EUSCI_B0_BASE)
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321 #define EUSCI_B1 ((EUSCI_B1_Type *) EUSCI_B1_BASE)
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322 #define EUSCI_B2 ((EUSCI_B2_Type *) EUSCI_B2_BASE)
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323 #define EUSCI_B3 ((EUSCI_B3_Type *) EUSCI_B3_BASE)
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324 #define FLCTL ((FLCTL_Type *) FLCTL_BASE)
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325 #define FPB ((FPB_Type *) FPB_BASE)
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326 #define PCM ((PCM_Type *) PCM_BASE)
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327 #define PMAP ((PMAP_Type *) PMAP_BASE)
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328 #define PSS ((PSS_Type *) PSS_BASE)
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329 #define REF_A ((REF_A_Type *) REF_A_BASE)
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330 #define RSTCTL ((RSTCTL_Type *) RSTCTL_BASE)
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331 #define RTC_C ((RTC_C_Type *) RTC_C_BASE)
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332 #define SYSCTL ((SYSCTL_Type *) SYSCTL_BASE)
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333 #define TIMER32 ((TIMER32_Type *) TIMER32_BASE)
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334 #define TIMER_A0 ((TIMER_A0_Type *) TIMER_A0_BASE)
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335 #define TIMER_A1 ((TIMER_A1_Type *) TIMER_A1_BASE)
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336 #define TIMER_A2 ((TIMER_A2_Type *) TIMER_A2_BASE)
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337 #define TIMER_A3 ((TIMER_A3_Type *) TIMER_A3_BASE)
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338 #define TLV ((TLV_Type *) TLV_BASE)
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339 #define WDT_A ((WDT_A_Type *) WDT_A_BASE)
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342 //*****************************************************************************
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343 // MSP-format peripheral registers
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344 //*****************************************************************************
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346 //*****************************************************************************
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348 //*****************************************************************************
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349 #define ADC14CTL0 (HWREG32(0x40012000)) /* Control 0 Register */
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350 #define ADC14CTL1 (HWREG32(0x40012004)) /* Control 1 Register */
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351 #define ADC14LO0 (HWREG32(0x40012008)) /* Window Comparator Low Threshold 0 Register */
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352 #define ADC14HI0 (HWREG32(0x4001200C)) /* Window Comparator High Threshold 0 Register */
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353 #define ADC14LO1 (HWREG32(0x40012010)) /* Window Comparator Low Threshold 1 Register */
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354 #define ADC14HI1 (HWREG32(0x40012014)) /* Window Comparator High Threshold 1 Register */
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355 #define ADC14MCTL0 (HWREG32(0x40012018)) /* Conversion Memory Control Register */
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356 #define ADC14MCTL1 (HWREG32(0x4001201C)) /* Conversion Memory Control Register */
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357 #define ADC14MCTL2 (HWREG32(0x40012020)) /* Conversion Memory Control Register */
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358 #define ADC14MCTL3 (HWREG32(0x40012024)) /* Conversion Memory Control Register */
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359 #define ADC14MCTL4 (HWREG32(0x40012028)) /* Conversion Memory Control Register */
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360 #define ADC14MCTL5 (HWREG32(0x4001202C)) /* Conversion Memory Control Register */
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361 #define ADC14MCTL6 (HWREG32(0x40012030)) /* Conversion Memory Control Register */
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362 #define ADC14MCTL7 (HWREG32(0x40012034)) /* Conversion Memory Control Register */
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363 #define ADC14MCTL8 (HWREG32(0x40012038)) /* Conversion Memory Control Register */
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364 #define ADC14MCTL9 (HWREG32(0x4001203C)) /* Conversion Memory Control Register */
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365 #define ADC14MCTL10 (HWREG32(0x40012040)) /* Conversion Memory Control Register */
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366 #define ADC14MCTL11 (HWREG32(0x40012044)) /* Conversion Memory Control Register */
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367 #define ADC14MCTL12 (HWREG32(0x40012048)) /* Conversion Memory Control Register */
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368 #define ADC14MCTL13 (HWREG32(0x4001204C)) /* Conversion Memory Control Register */
\r
369 #define ADC14MCTL14 (HWREG32(0x40012050)) /* Conversion Memory Control Register */
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370 #define ADC14MCTL15 (HWREG32(0x40012054)) /* Conversion Memory Control Register */
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371 #define ADC14MCTL16 (HWREG32(0x40012058)) /* Conversion Memory Control Register */
\r
372 #define ADC14MCTL17 (HWREG32(0x4001205C)) /* Conversion Memory Control Register */
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373 #define ADC14MCTL18 (HWREG32(0x40012060)) /* Conversion Memory Control Register */
\r
374 #define ADC14MCTL19 (HWREG32(0x40012064)) /* Conversion Memory Control Register */
\r
375 #define ADC14MCTL20 (HWREG32(0x40012068)) /* Conversion Memory Control Register */
\r
376 #define ADC14MCTL21 (HWREG32(0x4001206C)) /* Conversion Memory Control Register */
\r
377 #define ADC14MCTL22 (HWREG32(0x40012070)) /* Conversion Memory Control Register */
\r
378 #define ADC14MCTL23 (HWREG32(0x40012074)) /* Conversion Memory Control Register */
\r
379 #define ADC14MCTL24 (HWREG32(0x40012078)) /* Conversion Memory Control Register */
\r
380 #define ADC14MCTL25 (HWREG32(0x4001207C)) /* Conversion Memory Control Register */
\r
381 #define ADC14MCTL26 (HWREG32(0x40012080)) /* Conversion Memory Control Register */
\r
382 #define ADC14MCTL27 (HWREG32(0x40012084)) /* Conversion Memory Control Register */
\r
383 #define ADC14MCTL28 (HWREG32(0x40012088)) /* Conversion Memory Control Register */
\r
384 #define ADC14MCTL29 (HWREG32(0x4001208C)) /* Conversion Memory Control Register */
\r
385 #define ADC14MCTL30 (HWREG32(0x40012090)) /* Conversion Memory Control Register */
\r
386 #define ADC14MCTL31 (HWREG32(0x40012094)) /* Conversion Memory Control Register */
\r
387 #define ADC14MEM0 (HWREG32(0x40012098)) /* Conversion Memory Register */
\r
388 #define ADC14MEM1 (HWREG32(0x4001209C)) /* Conversion Memory Register */
\r
389 #define ADC14MEM2 (HWREG32(0x400120A0)) /* Conversion Memory Register */
\r
390 #define ADC14MEM3 (HWREG32(0x400120A4)) /* Conversion Memory Register */
\r
391 #define ADC14MEM4 (HWREG32(0x400120A8)) /* Conversion Memory Register */
\r
392 #define ADC14MEM5 (HWREG32(0x400120AC)) /* Conversion Memory Register */
\r
393 #define ADC14MEM6 (HWREG32(0x400120B0)) /* Conversion Memory Register */
\r
394 #define ADC14MEM7 (HWREG32(0x400120B4)) /* Conversion Memory Register */
\r
395 #define ADC14MEM8 (HWREG32(0x400120B8)) /* Conversion Memory Register */
\r
396 #define ADC14MEM9 (HWREG32(0x400120BC)) /* Conversion Memory Register */
\r
397 #define ADC14MEM10 (HWREG32(0x400120C0)) /* Conversion Memory Register */
\r
398 #define ADC14MEM11 (HWREG32(0x400120C4)) /* Conversion Memory Register */
\r
399 #define ADC14MEM12 (HWREG32(0x400120C8)) /* Conversion Memory Register */
\r
400 #define ADC14MEM13 (HWREG32(0x400120CC)) /* Conversion Memory Register */
\r
401 #define ADC14MEM14 (HWREG32(0x400120D0)) /* Conversion Memory Register */
\r
402 #define ADC14MEM15 (HWREG32(0x400120D4)) /* Conversion Memory Register */
\r
403 #define ADC14MEM16 (HWREG32(0x400120D8)) /* Conversion Memory Register */
\r
404 #define ADC14MEM17 (HWREG32(0x400120DC)) /* Conversion Memory Register */
\r
405 #define ADC14MEM18 (HWREG32(0x400120E0)) /* Conversion Memory Register */
\r
406 #define ADC14MEM19 (HWREG32(0x400120E4)) /* Conversion Memory Register */
\r
407 #define ADC14MEM20 (HWREG32(0x400120E8)) /* Conversion Memory Register */
\r
408 #define ADC14MEM21 (HWREG32(0x400120EC)) /* Conversion Memory Register */
\r
409 #define ADC14MEM22 (HWREG32(0x400120F0)) /* Conversion Memory Register */
\r
410 #define ADC14MEM23 (HWREG32(0x400120F4)) /* Conversion Memory Register */
\r
411 #define ADC14MEM24 (HWREG32(0x400120F8)) /* Conversion Memory Register */
\r
412 #define ADC14MEM25 (HWREG32(0x400120FC)) /* Conversion Memory Register */
\r
413 #define ADC14MEM26 (HWREG32(0x40012100)) /* Conversion Memory Register */
\r
414 #define ADC14MEM27 (HWREG32(0x40012104)) /* Conversion Memory Register */
\r
415 #define ADC14MEM28 (HWREG32(0x40012108)) /* Conversion Memory Register */
\r
416 #define ADC14MEM29 (HWREG32(0x4001210C)) /* Conversion Memory Register */
\r
417 #define ADC14MEM30 (HWREG32(0x40012110)) /* Conversion Memory Register */
\r
418 #define ADC14MEM31 (HWREG32(0x40012114)) /* Conversion Memory Register */
\r
419 #define ADC14IER0 (HWREG32(0x4001213C)) /* Interrupt Enable 0 Register */
\r
420 #define ADC14IER1 (HWREG32(0x40012140)) /* Interrupt Enable 1 Register */
\r
421 #define ADC14IFGR0 (HWREG32(0x40012144)) /* Interrupt Flag 0 Register */
\r
422 #define ADC14IFGR1 (HWREG32(0x40012148)) /* Interrupt Flag 1 Register */
\r
423 #define ADC14CLRIFGR0 (HWREG32(0x4001214C)) /* Clear Interrupt Flag 0 Register */
\r
424 #define ADC14CLRIFGR1 (HWREG32(0x40012150)) /* Clear Interrupt Flag 1 Register */
\r
425 #define ADC14IV (HWREG32(0x40012154)) /* Interrupt Vector Register */
\r
427 /* Register offsets from ADC14_BASE address */
\r
428 #define OFS_ADC14CTL0 (0x00000000) /* Control 0 Register */
\r
429 #define OFS_ADC14CTL1 (0x00000004) /* Control 1 Register */
\r
430 #define OFS_ADC14LO0 (0x00000008) /* Window Comparator Low Threshold 0 Register */
\r
431 #define OFS_ADC14HI0 (0x0000000c) /* Window Comparator High Threshold 0 Register */
\r
432 #define OFS_ADC14LO1 (0x00000010) /* Window Comparator Low Threshold 1 Register */
\r
433 #define OFS_ADC14HI1 (0x00000014) /* Window Comparator High Threshold 1 Register */
\r
434 #define OFS_ADC14MCTL0 (0x00000018) /* Conversion Memory Control Register */
\r
435 #define OFS_ADC14MCTL1 (0x0000001C) /* Conversion Memory Control Register */
\r
436 #define OFS_ADC14MCTL2 (0x00000020) /* Conversion Memory Control Register */
\r
437 #define OFS_ADC14MCTL3 (0x00000024) /* Conversion Memory Control Register */
\r
438 #define OFS_ADC14MCTL4 (0x00000028) /* Conversion Memory Control Register */
\r
439 #define OFS_ADC14MCTL5 (0x0000002C) /* Conversion Memory Control Register */
\r
440 #define OFS_ADC14MCTL6 (0x00000030) /* Conversion Memory Control Register */
\r
441 #define OFS_ADC14MCTL7 (0x00000034) /* Conversion Memory Control Register */
\r
442 #define OFS_ADC14MCTL8 (0x00000038) /* Conversion Memory Control Register */
\r
443 #define OFS_ADC14MCTL9 (0x0000003C) /* Conversion Memory Control Register */
\r
444 #define OFS_ADC14MCTL10 (0x00000040) /* Conversion Memory Control Register */
\r
445 #define OFS_ADC14MCTL11 (0x00000044) /* Conversion Memory Control Register */
\r
446 #define OFS_ADC14MCTL12 (0x00000048) /* Conversion Memory Control Register */
\r
447 #define OFS_ADC14MCTL13 (0x0000004C) /* Conversion Memory Control Register */
\r
448 #define OFS_ADC14MCTL14 (0x00000050) /* Conversion Memory Control Register */
\r
449 #define OFS_ADC14MCTL15 (0x00000054) /* Conversion Memory Control Register */
\r
450 #define OFS_ADC14MCTL16 (0x00000058) /* Conversion Memory Control Register */
\r
451 #define OFS_ADC14MCTL17 (0x0000005C) /* Conversion Memory Control Register */
\r
452 #define OFS_ADC14MCTL18 (0x00000060) /* Conversion Memory Control Register */
\r
453 #define OFS_ADC14MCTL19 (0x00000064) /* Conversion Memory Control Register */
\r
454 #define OFS_ADC14MCTL20 (0x00000068) /* Conversion Memory Control Register */
\r
455 #define OFS_ADC14MCTL21 (0x0000006C) /* Conversion Memory Control Register */
\r
456 #define OFS_ADC14MCTL22 (0x00000070) /* Conversion Memory Control Register */
\r
457 #define OFS_ADC14MCTL23 (0x00000074) /* Conversion Memory Control Register */
\r
458 #define OFS_ADC14MCTL24 (0x00000078) /* Conversion Memory Control Register */
\r
459 #define OFS_ADC14MCTL25 (0x0000007C) /* Conversion Memory Control Register */
\r
460 #define OFS_ADC14MCTL26 (0x00000080) /* Conversion Memory Control Register */
\r
461 #define OFS_ADC14MCTL27 (0x00000084) /* Conversion Memory Control Register */
\r
462 #define OFS_ADC14MCTL28 (0x00000088) /* Conversion Memory Control Register */
\r
463 #define OFS_ADC14MCTL29 (0x0000008C) /* Conversion Memory Control Register */
\r
464 #define OFS_ADC14MCTL30 (0x00000090) /* Conversion Memory Control Register */
\r
465 #define OFS_ADC14MCTL31 (0x00000094) /* Conversion Memory Control Register */
\r
466 #define OFS_ADC14MEM0 (0x00000098) /* Conversion Memory Register */
\r
467 #define OFS_ADC14MEM1 (0x0000009C) /* Conversion Memory Register */
\r
468 #define OFS_ADC14MEM2 (0x000000A0) /* Conversion Memory Register */
\r
469 #define OFS_ADC14MEM3 (0x000000A4) /* Conversion Memory Register */
\r
470 #define OFS_ADC14MEM4 (0x000000A8) /* Conversion Memory Register */
\r
471 #define OFS_ADC14MEM5 (0x000000AC) /* Conversion Memory Register */
\r
472 #define OFS_ADC14MEM6 (0x000000B0) /* Conversion Memory Register */
\r
473 #define OFS_ADC14MEM7 (0x000000B4) /* Conversion Memory Register */
\r
474 #define OFS_ADC14MEM8 (0x000000B8) /* Conversion Memory Register */
\r
475 #define OFS_ADC14MEM9 (0x000000BC) /* Conversion Memory Register */
\r
476 #define OFS_ADC14MEM10 (0x000000C0) /* Conversion Memory Register */
\r
477 #define OFS_ADC14MEM11 (0x000000C4) /* Conversion Memory Register */
\r
478 #define OFS_ADC14MEM12 (0x000000C8) /* Conversion Memory Register */
\r
479 #define OFS_ADC14MEM13 (0x000000CC) /* Conversion Memory Register */
\r
480 #define OFS_ADC14MEM14 (0x000000D0) /* Conversion Memory Register */
\r
481 #define OFS_ADC14MEM15 (0x000000D4) /* Conversion Memory Register */
\r
482 #define OFS_ADC14MEM16 (0x000000D8) /* Conversion Memory Register */
\r
483 #define OFS_ADC14MEM17 (0x000000DC) /* Conversion Memory Register */
\r
484 #define OFS_ADC14MEM18 (0x000000E0) /* Conversion Memory Register */
\r
485 #define OFS_ADC14MEM19 (0x000000E4) /* Conversion Memory Register */
\r
486 #define OFS_ADC14MEM20 (0x000000E8) /* Conversion Memory Register */
\r
487 #define OFS_ADC14MEM21 (0x000000EC) /* Conversion Memory Register */
\r
488 #define OFS_ADC14MEM22 (0x000000F0) /* Conversion Memory Register */
\r
489 #define OFS_ADC14MEM23 (0x000000F4) /* Conversion Memory Register */
\r
490 #define OFS_ADC14MEM24 (0x000000F8) /* Conversion Memory Register */
\r
491 #define OFS_ADC14MEM25 (0x000000FC) /* Conversion Memory Register */
\r
492 #define OFS_ADC14MEM26 (0x00000100) /* Conversion Memory Register */
\r
493 #define OFS_ADC14MEM27 (0x00000104) /* Conversion Memory Register */
\r
494 #define OFS_ADC14MEM28 (0x00000108) /* Conversion Memory Register */
\r
495 #define OFS_ADC14MEM29 (0x0000010C) /* Conversion Memory Register */
\r
496 #define OFS_ADC14MEM30 (0x00000110) /* Conversion Memory Register */
\r
497 #define OFS_ADC14MEM31 (0x00000114) /* Conversion Memory Register */
\r
498 #define OFS_ADC14IER0 (0x0000013c) /* Interrupt Enable 0 Register */
\r
499 #define OFS_ADC14IER1 (0x00000140) /* Interrupt Enable 1 Register */
\r
500 #define OFS_ADC14IFGR0 (0x00000144) /* Interrupt Flag 0 Register */
\r
501 #define OFS_ADC14IFGR1 (0x00000148) /* Interrupt Flag 1 Register */
\r
502 #define OFS_ADC14CLRIFGR0 (0x0000014c) /* Clear Interrupt Flag 0 Register */
\r
503 #define OFS_ADC14CLRIFGR1 (0x00000150) /* Clear Interrupt Flag 1 Register */
\r
504 #define OFS_ADC14IV (0x00000154) /* Interrupt Vector Register */
\r
507 //*****************************************************************************
\r
508 // AES256 Registers
\r
509 //*****************************************************************************
\r
510 #define AESACTL0 (HWREG16(0x40003C00)) /* AES Accelerator Control Register 0 */
\r
511 #define AESACTL1 (HWREG16(0x40003C02)) /* AES Accelerator Control Register 1 */
\r
512 #define AESASTAT (HWREG16(0x40003C04)) /* AES Accelerator Status Register */
\r
513 #define AESAKEY (HWREG16(0x40003C06)) /* AES Accelerator Key Register */
\r
514 #define AESADIN (HWREG16(0x40003C08)) /* AES Accelerator Data In Register */
\r
515 #define AESADOUT (HWREG16(0x40003C0A)) /* AES Accelerator Data Out Register */
\r
516 #define AESAXDIN (HWREG16(0x40003C0C)) /* AES Accelerator XORed Data In Register */
\r
517 #define AESAXIN (HWREG16(0x40003C0E)) /* AES Accelerator XORed Data In Register */
\r
519 /* Register offsets from AES256_BASE address */
\r
520 #define OFS_AESACTL0 (0x0000) /* AES Accelerator Control Register 0 */
\r
521 #define OFS_AESACTL1 (0x0002) /* AES Accelerator Control Register 1 */
\r
522 #define OFS_AESASTAT (0x0004) /* AES Accelerator Status Register */
\r
523 #define OFS_AESAKEY (0x0006) /* AES Accelerator Key Register */
\r
524 #define OFS_AESADIN (0x0008) /* AES Accelerator Data In Register */
\r
525 #define OFS_AESADOUT (0x000a) /* AES Accelerator Data Out Register */
\r
526 #define OFS_AESAXDIN (0x000c) /* AES Accelerator XORed Data In Register */
\r
527 #define OFS_AESAXIN (0x000e) /* AES Accelerator XORed Data In Register */
\r
530 //*****************************************************************************
\r
531 // CAPTIO0 Registers
\r
532 //*****************************************************************************
\r
533 #define CAPTIO0CTL (HWREG16(0x4000540E)) /* Capacitive Touch IO x Control Register */
\r
535 /* Register offsets from CAPTIO0_BASE address */
\r
536 #define OFS_CAPTIO0CTL (0x000e) /* Capacitive Touch IO x Control Register */
\r
538 #define CAPTIO0CTL_L (HWREG8_L(CAPTIO0CTL))/* Capacitive Touch IO x Control Register */
\r
539 #define CAPTIO0CTL_H (HWREG8_H(CAPTIO0CTL))/* Capacitive Touch IO x Control Register */
\r
541 //*****************************************************************************
\r
542 // CAPTIO1 Registers
\r
543 //*****************************************************************************
\r
544 #define CAPTIO1CTL (HWREG16(0x4000580E)) /* Capacitive Touch IO x Control Register */
\r
546 /* Register offsets from CAPTIO1_BASE address */
\r
547 #define OFS_CAPTIO1CTL (0x000e) /* Capacitive Touch IO x Control Register */
\r
549 #define CAPTIO1CTL_L (HWREG8_L(CAPTIO1CTL))/* Capacitive Touch IO x Control Register */
\r
550 #define CAPTIO1CTL_H (HWREG8_H(CAPTIO1CTL))/* Capacitive Touch IO x Control Register */
\r
552 //*****************************************************************************
\r
553 // COMP_E0 Registers
\r
554 //*****************************************************************************
\r
555 #define CE0CTL0 (HWREG16(0x40003400)) /* Comparator Control Register 0 */
\r
556 #define CE0CTL1 (HWREG16(0x40003402)) /* Comparator Control Register 1 */
\r
557 #define CE0CTL2 (HWREG16(0x40003404)) /* Comparator Control Register 2 */
\r
558 #define CE0CTL3 (HWREG16(0x40003406)) /* Comparator Control Register 3 */
\r
559 #define CE0INT (HWREG16(0x4000340C)) /* Comparator Interrupt Control Register */
\r
560 #define CE0IV (HWREG16(0x4000340E)) /* Comparator Interrupt Vector Word Register */
\r
562 /* Register offsets from COMP_E0_BASE address */
\r
563 #define OFS_CE0CTL0 (0x0000) /* Comparator Control Register 0 */
\r
564 #define OFS_CE0CTL1 (0x0002) /* Comparator Control Register 1 */
\r
565 #define OFS_CE0CTL2 (0x0004) /* Comparator Control Register 2 */
\r
566 #define OFS_CE0CTL3 (0x0006) /* Comparator Control Register 3 */
\r
567 #define OFS_CE0INT (0x000c) /* Comparator Interrupt Control Register */
\r
568 #define OFS_CE0IV (0x000e) /* Comparator Interrupt Vector Word Register */
\r
571 //*****************************************************************************
\r
572 // COMP_E1 Registers
\r
573 //*****************************************************************************
\r
574 #define CE1CTL0 (HWREG16(0x40003800)) /* Comparator Control Register 0 */
\r
575 #define CE1CTL1 (HWREG16(0x40003802)) /* Comparator Control Register 1 */
\r
576 #define CE1CTL2 (HWREG16(0x40003804)) /* Comparator Control Register 2 */
\r
577 #define CE1CTL3 (HWREG16(0x40003806)) /* Comparator Control Register 3 */
\r
578 #define CE1INT (HWREG16(0x4000380C)) /* Comparator Interrupt Control Register */
\r
579 #define CE1IV (HWREG16(0x4000380E)) /* Comparator Interrupt Vector Word Register */
\r
581 /* Register offsets from COMP_E1_BASE address */
\r
582 #define OFS_CE1CTL0 (0x0000) /* Comparator Control Register 0 */
\r
583 #define OFS_CE1CTL1 (0x0002) /* Comparator Control Register 1 */
\r
584 #define OFS_CE1CTL2 (0x0004) /* Comparator Control Register 2 */
\r
585 #define OFS_CE1CTL3 (0x0006) /* Comparator Control Register 3 */
\r
586 #define OFS_CE1INT (0x000c) /* Comparator Interrupt Control Register */
\r
587 #define OFS_CE1IV (0x000e) /* Comparator Interrupt Vector Word Register */
\r
590 //*****************************************************************************
\r
591 // COREDEBUG Registers
\r
592 //*****************************************************************************
\r
593 #define COREDEBUG_DHCSR (HWREG32(0xE000EDF0)) /* Debug Halting Control and Status Register */
\r
594 #define COREDEBUG_DCRSR (HWREG32(0xE000EDF4)) /* Deubg Core Register Selector Register */
\r
595 #define COREDEBUG_DCRDR (HWREG32(0xE000EDF8)) /* Debug Core Register Data Register */
\r
596 #define COREDEBUG_DEMCR (HWREG32(0xE000EDFC)) /* Debug Exception and Monitor Control Register */
\r
598 /* Register offsets from COREDEBUG_BASE address */
\r
599 #define OFS_COREDEBUG_DHCSR (0x00000DF0) /* Debug Halting Control and Status Register */
\r
600 #define OFS_COREDEBUG_DCRSR (0x00000DF4) /* Deubg Core Register Selector Register */
\r
601 #define OFS_COREDEBUG_DCRDR (0x00000DF8) /* Debug Core Register Data Register */
\r
602 #define OFS_COREDEBUG_DEMCR (0x00000DFC) /* Debug Exception and Monitor Control Register */
\r
605 //*****************************************************************************
\r
607 //*****************************************************************************
\r
608 #define CRC32DI (HWREG16(0x40004000)) /* Data Input for CRC32 Signature Computation */
\r
609 #define CRC32DIRB (HWREG16(0x40004004)) /* Data In Reverse for CRC32 Computation */
\r
610 #define CRC32INIRES_LO (HWREG16(0x40004008)) /* CRC32 Initialization and Result, lower 16 bits */
\r
611 #define CRC32INIRES_HI (HWREG16(0x4000400A)) /* CRC32 Initialization and Result, upper 16 bits */
\r
612 #define CRC32RESR_LO (HWREG16(0x4000400C)) /* CRC32 Result Reverse, lower 16 bits */
\r
613 #define CRC32RESR_HI (HWREG16(0x4000400E)) /* CRC32 Result Reverse, Upper 16 bits */
\r
614 #define CRC16DI (HWREG16(0x40004010)) /* Data Input for CRC16 computation */
\r
615 #define CRC16DIRB (HWREG16(0x40004014)) /* CRC16 Data In Reverse */
\r
616 #define CRC16INIRES (HWREG16(0x40004018)) /* CRC16 Initialization and Result register */
\r
617 #define CRC16RESR (HWREG16(0x4000401E)) /* CRC16 Result Reverse */
\r
619 /* Register offsets from CRC32_BASE address */
\r
620 #define OFS_CRC32DI (0x0000) /* Data Input for CRC32 Signature Computation */
\r
621 #define OFS_CRC32DIRB (0x0004) /* Data In Reverse for CRC32 Computation */
\r
622 #define OFS_CRC32INIRES_LO (0x0008) /* CRC32 Initialization and Result, lower 16 bits */
\r
623 #define OFS_CRC32INIRES_HI (0x000a) /* CRC32 Initialization and Result, upper 16 bits */
\r
624 #define OFS_CRC32RESR_LO (0x000c) /* CRC32 Result Reverse, lower 16 bits */
\r
625 #define OFS_CRC32RESR_HI (0x000e) /* CRC32 Result Reverse, Upper 16 bits */
\r
626 #define OFS_CRC16DI (0x0010) /* Data Input for CRC16 computation */
\r
627 #define OFS_CRC16DIRB (0x0014) /* CRC16 Data In Reverse */
\r
628 #define OFS_CRC16INIRES (0x0018) /* CRC16 Initialization and Result register */
\r
629 #define OFS_CRC16RESR (0x001e) /* CRC16 Result Reverse */
\r
632 //*****************************************************************************
\r
634 //*****************************************************************************
\r
635 #define CSKEY (HWREG32(0x40010400)) /* Key Register */
\r
636 #define CSCTL0 (HWREG32(0x40010404)) /* Control 0 Register */
\r
637 #define CSCTL1 (HWREG32(0x40010408)) /* Control 1 Register */
\r
638 #define CSCTL2 (HWREG32(0x4001040C)) /* Control 2 Register */
\r
639 #define CSCTL3 (HWREG32(0x40010410)) /* Control 3 Register */
\r
640 #define CSCTL4 (HWREG32(0x40010414)) /* Control 4 Register */
\r
641 #define CSCTL5 (HWREG32(0x40010418)) /* Control 5 Register */
\r
642 #define CSCTL6 (HWREG32(0x4001041C)) /* Control 6 Register */
\r
643 #define CSCTL7 (HWREG32(0x40010420)) /* Control 7 Register */
\r
644 #define CSCLKEN (HWREG32(0x40010430)) /* Clock Enable Register */
\r
645 #define CSSTAT (HWREG32(0x40010434)) /* Status Register */
\r
646 #define CSIE (HWREG32(0x40010440)) /* Interrupt Enable Register */
\r
647 #define CSIFG (HWREG32(0x40010448)) /* Interrupt Flag Register */
\r
648 #define CSCLRIFG (HWREG32(0x40010450)) /* Clear Interrupt Flag Register */
\r
649 #define CSSETIFG (HWREG32(0x40010458)) /* Set Interrupt Flag Register */
\r
650 #define CSDCOERCAL (HWREG32(0x40010460)) /* DCO external resistor cailbration register */
\r
652 /* Register offsets from CS_BASE address */
\r
653 #define OFS_CSKEY (0x00000000) /* Key Register */
\r
654 #define OFS_CSCTL0 (0x00000004) /* Control 0 Register */
\r
655 #define OFS_CSCTL1 (0x00000008) /* Control 1 Register */
\r
656 #define OFS_CSCTL2 (0x0000000c) /* Control 2 Register */
\r
657 #define OFS_CSCTL3 (0x00000010) /* Control 3 Register */
\r
658 #define OFS_CSCTL4 (0x00000014) /* Control 4 Register */
\r
659 #define OFS_CSCTL5 (0x00000018) /* Control 5 Register */
\r
660 #define OFS_CSCTL6 (0x0000001c) /* Control 6 Register */
\r
661 #define OFS_CSCTL7 (0x00000020) /* Control 7 Register */
\r
662 #define OFS_CSCLKEN (0x00000030) /* Clock Enable Register */
\r
663 #define OFS_CSSTAT (0x00000034) /* Status Register */
\r
664 #define OFS_CSIE (0x00000040) /* Interrupt Enable Register */
\r
665 #define OFS_CSIFG (0x00000048) /* Interrupt Flag Register */
\r
666 #define OFS_CSCLRIFG (0x00000050) /* Clear Interrupt Flag Register */
\r
667 #define OFS_CSSETIFG (0x00000058) /* Set Interrupt Flag Register */
\r
668 #define OFS_CSDCOERCAL (0x00000060) /* DCO external resistor cailbration register */
\r
671 //*****************************************************************************
\r
673 //*****************************************************************************
\r
674 #define PAIN (HWREG16(0x40004C00)) /* Port A Input */
\r
675 #define PAOUT (HWREG16(0x40004C02)) /* Port A Output */
\r
676 #define PADIR (HWREG16(0x40004C04)) /* Port A Direction */
\r
677 #define PAREN (HWREG16(0x40004C06)) /* Port A Resistor Enable */
\r
678 #define PADS (HWREG16(0x40004C08)) /* Port A Drive Strength */
\r
679 #define PASEL0 (HWREG16(0x40004C0A)) /* Port A Select 0 */
\r
680 #define PASEL1 (HWREG16(0x40004C0C)) /* Port A Select 1 */
\r
681 #define P1IV (HWREG16(0x40004C0E)) /* Port 1 Interrupt Vector Register */
\r
682 #define PASELC (HWREG16(0x40004C16)) /* Port A Complement Select */
\r
683 #define PAIES (HWREG16(0x40004C18)) /* Port A Interrupt Edge Select */
\r
684 #define PAIE (HWREG16(0x40004C1A)) /* Port A Interrupt Enable */
\r
685 #define PAIFG (HWREG16(0x40004C1C)) /* Port A Interrupt Flag */
\r
686 #define P2IV (HWREG16(0x40004C1E)) /* Port 2 Interrupt Vector Register */
\r
687 #define PBIN (HWREG16(0x40004C20)) /* Port B Input */
\r
688 #define PBOUT (HWREG16(0x40004C22)) /* Port B Output */
\r
689 #define PBDIR (HWREG16(0x40004C24)) /* Port B Direction */
\r
690 #define PBREN (HWREG16(0x40004C26)) /* Port B Resistor Enable */
\r
691 #define PBDS (HWREG16(0x40004C28)) /* Port B Drive Strength */
\r
692 #define PBSEL0 (HWREG16(0x40004C2A)) /* Port B Select 0 */
\r
693 #define PBSEL1 (HWREG16(0x40004C2C)) /* Port B Select 1 */
\r
694 #define P3IV (HWREG16(0x40004C2E)) /* Port 3 Interrupt Vector Register */
\r
695 #define PBSELC (HWREG16(0x40004C36)) /* Port B Complement Select */
\r
696 #define PBIES (HWREG16(0x40004C38)) /* Port B Interrupt Edge Select */
\r
697 #define PBIE (HWREG16(0x40004C3A)) /* Port B Interrupt Enable */
\r
698 #define PBIFG (HWREG16(0x40004C3C)) /* Port B Interrupt Flag */
\r
699 #define P4IV (HWREG16(0x40004C3E)) /* Port 4 Interrupt Vector Register */
\r
700 #define PCIN (HWREG16(0x40004C40)) /* Port C Input */
\r
701 #define PCOUT (HWREG16(0x40004C42)) /* Port C Output */
\r
702 #define PCDIR (HWREG16(0x40004C44)) /* Port C Direction */
\r
703 #define PCREN (HWREG16(0x40004C46)) /* Port C Resistor Enable */
\r
704 #define PCDS (HWREG16(0x40004C48)) /* Port C Drive Strength */
\r
705 #define PCSEL0 (HWREG16(0x40004C4A)) /* Port C Select 0 */
\r
706 #define PCSEL1 (HWREG16(0x40004C4C)) /* Port C Select 1 */
\r
707 #define P5IV (HWREG16(0x40004C4E)) /* Port 5 Interrupt Vector Register */
\r
708 #define PCSELC (HWREG16(0x40004C56)) /* Port C Complement Select */
\r
709 #define PCIES (HWREG16(0x40004C58)) /* Port C Interrupt Edge Select */
\r
710 #define PCIE (HWREG16(0x40004C5A)) /* Port C Interrupt Enable */
\r
711 #define PCIFG (HWREG16(0x40004C5C)) /* Port C Interrupt Flag */
\r
712 #define P6IV (HWREG16(0x40004C5E)) /* Port 6 Interrupt Vector Register */
\r
713 #define PDIN (HWREG16(0x40004C60)) /* Port D Input */
\r
714 #define PDOUT (HWREG16(0x40004C62)) /* Port D Output */
\r
715 #define PDDIR (HWREG16(0x40004C64)) /* Port D Direction */
\r
716 #define PDREN (HWREG16(0x40004C66)) /* Port D Resistor Enable */
\r
717 #define PDDS (HWREG16(0x40004C68)) /* Port D Drive Strength */
\r
718 #define PDSEL0 (HWREG16(0x40004C6A)) /* Port D Select 0 */
\r
719 #define PDSEL1 (HWREG16(0x40004C6C)) /* Port D Select 1 */
\r
720 #define P7IV (HWREG16(0x40004C6E)) /* Port 7 Interrupt Vector Register */
\r
721 #define PDSELC (HWREG16(0x40004C76)) /* Port D Complement Select */
\r
722 #define PDIES (HWREG16(0x40004C78)) /* Port D Interrupt Edge Select */
\r
723 #define PDIE (HWREG16(0x40004C7A)) /* Port D Interrupt Enable */
\r
724 #define PDIFG (HWREG16(0x40004C7C)) /* Port D Interrupt Flag */
\r
725 #define P8IV (HWREG16(0x40004C7E)) /* Port 8 Interrupt Vector Register */
\r
726 #define PEIN (HWREG16(0x40004C80)) /* Port E Input */
\r
727 #define PEOUT (HWREG16(0x40004C82)) /* Port E Output */
\r
728 #define PEDIR (HWREG16(0x40004C84)) /* Port E Direction */
\r
729 #define PEREN (HWREG16(0x40004C86)) /* Port E Resistor Enable */
\r
730 #define PEDS (HWREG16(0x40004C88)) /* Port E Drive Strength */
\r
731 #define PESEL0 (HWREG16(0x40004C8A)) /* Port E Select 0 */
\r
732 #define PESEL1 (HWREG16(0x40004C8C)) /* Port E Select 1 */
\r
733 #define P9IV (HWREG16(0x40004C8E)) /* Port 9 Interrupt Vector Register */
\r
734 #define PESELC (HWREG16(0x40004C96)) /* Port E Complement Select */
\r
735 #define PEIES (HWREG16(0x40004C98)) /* Port E Interrupt Edge Select */
\r
736 #define PEIE (HWREG16(0x40004C9A)) /* Port E Interrupt Enable */
\r
737 #define PEIFG (HWREG16(0x40004C9C)) /* Port E Interrupt Flag */
\r
738 #define P10IV (HWREG16(0x40004C9E)) /* Port 10 Interrupt Vector Register */
\r
739 #define PJIN (HWREG16(0x40004D20)) /* Port J Input */
\r
740 #define PJOUT (HWREG16(0x40004D22)) /* Port J Output */
\r
741 #define PJDIR (HWREG16(0x40004D24)) /* Port J Direction */
\r
742 #define PJREN (HWREG16(0x40004D26)) /* Port J Resistor Enable */
\r
743 #define PJDS (HWREG16(0x40004D28)) /* Port J Drive Strength */
\r
744 #define PJSEL0 (HWREG16(0x40004D2A)) /* Port J Select 0 */
\r
745 #define PJSEL1 (HWREG16(0x40004D2C)) /* Port J Select 1 */
\r
746 #define PJSELC (HWREG16(0x40004D36)) /* Port J Complement Select */
\r
747 #define P1IN (HWREG8(0x40004C00)) /* Port 1 Input */
\r
748 #define P2IN (HWREG8(0x40004C01)) /* Port 2 Input */
\r
749 #define P2OUT (HWREG8(0x40004C03)) /* Port 2 Output */
\r
750 #define P1OUT (HWREG8(0x40004C02)) /* Port 1 Output */
\r
751 #define P1DIR (HWREG8(0x40004C04)) /* Port 1 Direction */
\r
752 #define P2DIR (HWREG8(0x40004C05)) /* Port 2 Direction */
\r
753 #define P1REN (HWREG8(0x40004C06)) /* Port 1 Resistor Enable */
\r
754 #define P2REN (HWREG8(0x40004C07)) /* Port 2 Resistor Enable */
\r
755 #define P1DS (HWREG8(0x40004C08)) /* Port 1 Drive Strength */
\r
756 #define P2DS (HWREG8(0x40004C09)) /* Port 2 Drive Strength */
\r
757 #define P1SEL0 (HWREG8(0x40004C0A)) /* Port 1 Select 0 */
\r
758 #define P2SEL0 (HWREG8(0x40004C0B)) /* Port 2 Select 0 */
\r
759 #define P1SEL1 (HWREG8(0x40004C0C)) /* Port 1 Select 1 */
\r
760 #define P2SEL1 (HWREG8(0x40004C0D)) /* Port 2 Select 1 */
\r
761 #define P1SELC (HWREG8(0x40004C16)) /* Port 1 Complement Select */
\r
762 #define P2SELC (HWREG8(0x40004C17)) /* Port 2 Complement Select */
\r
763 #define P1IES (HWREG8(0x40004C18)) /* Port 1 Interrupt Edge Select */
\r
764 #define P2IES (HWREG8(0x40004C19)) /* Port 2 Interrupt Edge Select */
\r
765 #define P1IE (HWREG8(0x40004C1A)) /* Port 1 Interrupt Enable */
\r
766 #define P2IE (HWREG8(0x40004C1B)) /* Port 2 Interrupt Enable */
\r
767 #define P1IFG (HWREG8(0x40004C1C)) /* Port 1 Interrupt Flag */
\r
768 #define P2IFG (HWREG8(0x40004C1D)) /* Port 2 Interrupt Flag */
\r
769 #define P3IN (HWREG8(0x40004C20)) /* Port 3 Input */
\r
770 #define P4IN (HWREG8(0x40004C21)) /* Port 4 Input */
\r
771 #define P3OUT (HWREG8(0x40004C22)) /* Port 3 Output */
\r
772 #define P4OUT (HWREG8(0x40004C23)) /* Port 4 Output */
\r
773 #define P3DIR (HWREG8(0x40004C24)) /* Port 3 Direction */
\r
774 #define P4DIR (HWREG8(0x40004C25)) /* Port 4 Direction */
\r
775 #define P3REN (HWREG8(0x40004C26)) /* Port 3 Resistor Enable */
\r
776 #define P4REN (HWREG8(0x40004C27)) /* Port 4 Resistor Enable */
\r
777 #define P3DS (HWREG8(0x40004C28)) /* Port 3 Drive Strength */
\r
778 #define P4DS (HWREG8(0x40004C29)) /* Port 4 Drive Strength */
\r
779 #define P4SEL0 (HWREG8(0x40004C2B)) /* Port 4 Select 0 */
\r
780 #define P3SEL0 (HWREG8(0x40004C2A)) /* Port 3 Select 0 */
\r
781 #define P3SEL1 (HWREG8(0x40004C2C)) /* Port 3 Select 1 */
\r
782 #define P4SEL1 (HWREG8(0x40004C2D)) /* Port 4 Select 1 */
\r
783 #define P3SELC (HWREG8(0x40004C36)) /* Port 3 Complement Select */
\r
784 #define P4SELC (HWREG8(0x40004C37)) /* Port 4 Complement Select */
\r
785 #define P3IES (HWREG8(0x40004C38)) /* Port 3 Interrupt Edge Select */
\r
786 #define P4IES (HWREG8(0x40004C39)) /* Port 4 Interrupt Edge Select */
\r
787 #define P3IE (HWREG8(0x40004C3A)) /* Port 3 Interrupt Enable */
\r
788 #define P4IE (HWREG8(0x40004C3B)) /* Port 4 Interrupt Enable */
\r
789 #define P3IFG (HWREG8(0x40004C3C)) /* Port 3 Interrupt Flag */
\r
790 #define P4IFG (HWREG8(0x40004C3D)) /* Port 4 Interrupt Flag */
\r
791 #define P5IN (HWREG8(0x40004C40)) /* Port 5 Input */
\r
792 #define P6IN (HWREG8(0x40004C41)) /* Port 6 Input */
\r
793 #define P5OUT (HWREG8(0x40004C42)) /* Port 5 Output */
\r
794 #define P6OUT (HWREG8(0x40004C43)) /* Port 6 Output */
\r
795 #define P5DIR (HWREG8(0x40004C44)) /* Port 5 Direction */
\r
796 #define P6DIR (HWREG8(0x40004C45)) /* Port 6 Direction */
\r
797 #define P5REN (HWREG8(0x40004C46)) /* Port 5 Resistor Enable */
\r
798 #define P6REN (HWREG8(0x40004C47)) /* Port 6 Resistor Enable */
\r
799 #define P5DS (HWREG8(0x40004C48)) /* Port 5 Drive Strength */
\r
800 #define P6DS (HWREG8(0x40004C49)) /* Port 6 Drive Strength */
\r
801 #define P5SEL0 (HWREG8(0x40004C4A)) /* Port 5 Select 0 */
\r
802 #define P6SEL0 (HWREG8(0x40004C4B)) /* Port 6 Select 0 */
\r
803 #define P5SEL1 (HWREG8(0x40004C4C)) /* Port 5 Select 1 */
\r
804 #define P6SEL1 (HWREG8(0x40004C4D)) /* Port 6 Select 1 */
\r
805 #define P5SELC (HWREG8(0x40004C56)) /* Port 5 Complement Select */
\r
806 #define P6SELC (HWREG8(0x40004C57)) /* Port 6 Complement Select */
\r
807 #define P5IES (HWREG8(0x40004C58)) /* Port 5 Interrupt Edge Select */
\r
808 #define P6IES (HWREG8(0x40004C59)) /* Port 6 Interrupt Edge Select */
\r
809 #define P5IE (HWREG8(0x40004C5A)) /* Port 5 Interrupt Enable */
\r
810 #define P6IE (HWREG8(0x40004C5B)) /* Port 6 Interrupt Enable */
\r
811 #define P5IFG (HWREG8(0x40004C5C)) /* Port 5 Interrupt Flag */
\r
812 #define P6IFG (HWREG8(0x40004C5D)) /* Port 6 Interrupt Flag */
\r
813 #define P7IN (HWREG8(0x40004C60)) /* Port 7 Input */
\r
814 #define P8IN (HWREG8(0x40004C61)) /* Port 8 Input */
\r
815 #define P7OUT (HWREG8(0x40004C62)) /* Port 7 Output */
\r
816 #define P8OUT (HWREG8(0x40004C63)) /* Port 8 Output */
\r
817 #define P7DIR (HWREG8(0x40004C64)) /* Port 7 Direction */
\r
818 #define P8DIR (HWREG8(0x40004C65)) /* Port 8 Direction */
\r
819 #define P7REN (HWREG8(0x40004C66)) /* Port 7 Resistor Enable */
\r
820 #define P8REN (HWREG8(0x40004C67)) /* Port 8 Resistor Enable */
\r
821 #define P7DS (HWREG8(0x40004C68)) /* Port 7 Drive Strength */
\r
822 #define P8DS (HWREG8(0x40004C69)) /* Port 8 Drive Strength */
\r
823 #define P7SEL0 (HWREG8(0x40004C6A)) /* Port 7 Select 0 */
\r
824 #define P8SEL0 (HWREG8(0x40004C6B)) /* Port 8 Select 0 */
\r
825 #define P7SEL1 (HWREG8(0x40004C6C)) /* Port 7 Select 1 */
\r
826 #define P8SEL1 (HWREG8(0x40004C6D)) /* Port 8 Select 1 */
\r
827 #define P7SELC (HWREG8(0x40004C76)) /* Port 7 Complement Select */
\r
828 #define P8SELC (HWREG8(0x40004C77)) /* Port 8 Complement Select */
\r
829 #define P7IES (HWREG8(0x40004C78)) /* Port 7 Interrupt Edge Select */
\r
830 #define P8IES (HWREG8(0x40004C79)) /* Port 8 Interrupt Edge Select */
\r
831 #define P7IE (HWREG8(0x40004C7A)) /* Port 7 Interrupt Enable */
\r
832 #define P8IE (HWREG8(0x40004C7B)) /* Port 8 Interrupt Enable */
\r
833 #define P7IFG (HWREG8(0x40004C7C)) /* Port 7 Interrupt Flag */
\r
834 #define P8IFG (HWREG8(0x40004C7D)) /* Port 8 Interrupt Flag */
\r
835 #define P9IN (HWREG8(0x40004C80)) /* Port 9 Input */
\r
836 #define P10IN (HWREG8(0x40004C81)) /* Port 10 Input */
\r
837 #define P9OUT (HWREG8(0x40004C82)) /* Port 9 Output */
\r
838 #define P10OUT (HWREG8(0x40004C83)) /* Port 10 Output */
\r
839 #define P9DIR (HWREG8(0x40004C84)) /* Port 9 Direction */
\r
840 #define P10DIR (HWREG8(0x40004C85)) /* Port 10 Direction */
\r
841 #define P9REN (HWREG8(0x40004C86)) /* Port 9 Resistor Enable */
\r
842 #define P10REN (HWREG8(0x40004C87)) /* Port 10 Resistor Enable */
\r
843 #define P9DS (HWREG8(0x40004C88)) /* Port 9 Drive Strength */
\r
844 #define P10DS (HWREG8(0x40004C89)) /* Port 10 Drive Strength */
\r
845 #define P9SEL0 (HWREG8(0x40004C8A)) /* Port 9 Select 0 */
\r
846 #define P10SEL0 (HWREG8(0x40004C8B)) /* Port 10 Select 0 */
\r
847 #define P9SEL1 (HWREG8(0x40004C8C)) /* Port 9 Select 1 */
\r
848 #define P10SEL1 (HWREG8(0x40004C8D)) /* Port 10 Select 1 */
\r
849 #define P9SELC (HWREG8(0x40004C96)) /* Port 9 Complement Select */
\r
850 #define P10SELC (HWREG8(0x40004C97)) /* Port 10 Complement Select */
\r
851 #define P9IES (HWREG8(0x40004C98)) /* Port 9 Interrupt Edge Select */
\r
852 #define P10IES (HWREG8(0x40004C99)) /* Port 10 Interrupt Edge Select */
\r
853 #define P9IE (HWREG8(0x40004C9A)) /* Port 9 Interrupt Enable */
\r
854 #define P10IE (HWREG8(0x40004C9B)) /* Port 10 Interrupt Enable */
\r
855 #define P9IFG (HWREG8(0x40004C9C)) /* Port 9 Interrupt Flag */
\r
856 #define P10IFG (HWREG8(0x40004C9D)) /* Port 10 Interrupt Flag */
\r
858 /* Register offsets from DIO_BASE address */
\r
859 #define OFS_PAIN (0x0000) /* Port A Input */
\r
860 #define OFS_PAOUT (0x0002) /* Port A Output */
\r
861 #define OFS_PADIR (0x0004) /* Port A Direction */
\r
862 #define OFS_PAREN (0x0006) /* Port A Resistor Enable */
\r
863 #define OFS_PADS (0x0008) /* Port A Drive Strength */
\r
864 #define OFS_PASEL0 (0x000a) /* Port A Select 0 */
\r
865 #define OFS_PASEL1 (0x000c) /* Port A Select 1 */
\r
866 #define OFS_P1IV (0x000e) /* Port 1 Interrupt Vector Register */
\r
867 #define OFS_PASELC (0x0016) /* Port A Complement Select */
\r
868 #define OFS_PAIES (0x0018) /* Port A Interrupt Edge Select */
\r
869 #define OFS_PAIE (0x001a) /* Port A Interrupt Enable */
\r
870 #define OFS_PAIFG (0x001c) /* Port A Interrupt Flag */
\r
871 #define OFS_P2IV (0x001e) /* Port 2 Interrupt Vector Register */
\r
872 #define OFS_PBIN (0x0020) /* Port B Input */
\r
873 #define OFS_PBOUT (0x0022) /* Port B Output */
\r
874 #define OFS_PBDIR (0x0024) /* Port B Direction */
\r
875 #define OFS_PBREN (0x0026) /* Port B Resistor Enable */
\r
876 #define OFS_PBDS (0x0028) /* Port B Drive Strength */
\r
877 #define OFS_PBSEL0 (0x002a) /* Port B Select 0 */
\r
878 #define OFS_PBSEL1 (0x002c) /* Port B Select 1 */
\r
879 #define OFS_P3IV (0x002e) /* Port 3 Interrupt Vector Register */
\r
880 #define OFS_PBSELC (0x0036) /* Port B Complement Select */
\r
881 #define OFS_PBIES (0x0038) /* Port B Interrupt Edge Select */
\r
882 #define OFS_PBIE (0x003a) /* Port B Interrupt Enable */
\r
883 #define OFS_PBIFG (0x003c) /* Port B Interrupt Flag */
\r
884 #define OFS_P4IV (0x003e) /* Port 4 Interrupt Vector Register */
\r
885 #define OFS_PCIN (0x0040) /* Port C Input */
\r
886 #define OFS_PCOUT (0x0042) /* Port C Output */
\r
887 #define OFS_PCDIR (0x0044) /* Port C Direction */
\r
888 #define OFS_PCREN (0x0046) /* Port C Resistor Enable */
\r
889 #define OFS_PCDS (0x0048) /* Port C Drive Strength */
\r
890 #define OFS_PCSEL0 (0x004a) /* Port C Select 0 */
\r
891 #define OFS_PCSEL1 (0x004c) /* Port C Select 1 */
\r
892 #define OFS_P5IV (0x004e) /* Port 5 Interrupt Vector Register */
\r
893 #define OFS_PCSELC (0x0056) /* Port C Complement Select */
\r
894 #define OFS_PCIES (0x0058) /* Port C Interrupt Edge Select */
\r
895 #define OFS_PCIE (0x005a) /* Port C Interrupt Enable */
\r
896 #define OFS_PCIFG (0x005c) /* Port C Interrupt Flag */
\r
897 #define OFS_P6IV (0x005e) /* Port 6 Interrupt Vector Register */
\r
898 #define OFS_PDIN (0x0060) /* Port D Input */
\r
899 #define OFS_PDOUT (0x0062) /* Port D Output */
\r
900 #define OFS_PDDIR (0x0064) /* Port D Direction */
\r
901 #define OFS_PDREN (0x0066) /* Port D Resistor Enable */
\r
902 #define OFS_PDDS (0x0068) /* Port D Drive Strength */
\r
903 #define OFS_PDSEL0 (0x006a) /* Port D Select 0 */
\r
904 #define OFS_PDSEL1 (0x006c) /* Port D Select 1 */
\r
905 #define OFS_P7IV (0x006e) /* Port 7 Interrupt Vector Register */
\r
906 #define OFS_PDSELC (0x0076) /* Port D Complement Select */
\r
907 #define OFS_PDIES (0x0078) /* Port D Interrupt Edge Select */
\r
908 #define OFS_PDIE (0x007a) /* Port D Interrupt Enable */
\r
909 #define OFS_PDIFG (0x007c) /* Port D Interrupt Flag */
\r
910 #define OFS_P8IV (0x007e) /* Port 8 Interrupt Vector Register */
\r
911 #define OFS_PEIN (0x0080) /* Port E Input */
\r
912 #define OFS_PEOUT (0x0082) /* Port E Output */
\r
913 #define OFS_PEDIR (0x0084) /* Port E Direction */
\r
914 #define OFS_PEREN (0x0086) /* Port E Resistor Enable */
\r
915 #define OFS_PEDS (0x0088) /* Port E Drive Strength */
\r
916 #define OFS_PESEL0 (0x008a) /* Port E Select 0 */
\r
917 #define OFS_PESEL1 (0x008c) /* Port E Select 1 */
\r
918 #define OFS_P9IV (0x008e) /* Port 9 Interrupt Vector Register */
\r
919 #define OFS_PESELC (0x0096) /* Port E Complement Select */
\r
920 #define OFS_PEIES (0x0098) /* Port E Interrupt Edge Select */
\r
921 #define OFS_PEIE (0x009a) /* Port E Interrupt Enable */
\r
922 #define OFS_PEIFG (0x009c) /* Port E Interrupt Flag */
\r
923 #define OFS_P10IV (0x009e) /* Port 10 Interrupt Vector Register */
\r
924 #define OFS_PJIN (0x0120) /* Port J Input */
\r
925 #define OFS_PJOUT (0x0122) /* Port J Output */
\r
926 #define OFS_PJDIR (0x0124) /* Port J Direction */
\r
927 #define OFS_PJREN (0x0126) /* Port J Resistor Enable */
\r
928 #define OFS_PJDS (0x0128) /* Port J Drive Strength */
\r
929 #define OFS_PJSEL0 (0x012a) /* Port J Select 0 */
\r
930 #define OFS_PJSEL1 (0x012c) /* Port J Select 1 */
\r
931 #define OFS_PJSELC (0x0136) /* Port J Complement Select */
\r
932 #define OFS_P1IN (0x0000) /* Port 1 Input */
\r
933 #define OFS_P2IN (0x0000) /* Port 2 Input */
\r
934 #define OFS_P2OUT (0x0002) /* Port 2 Output */
\r
935 #define OFS_P1OUT (0x0002) /* Port 1 Output */
\r
936 #define OFS_P1DIR (0x0004) /* Port 1 Direction */
\r
937 #define OFS_P2DIR (0x0004) /* Port 2 Direction */
\r
938 #define OFS_P1REN (0x0006) /* Port 1 Resistor Enable */
\r
939 #define OFS_P2REN (0x0006) /* Port 2 Resistor Enable */
\r
940 #define OFS_P1DS (0x0008) /* Port 1 Drive Strength */
\r
941 #define OFS_P2DS (0x0008) /* Port 2 Drive Strength */
\r
942 #define OFS_P1SEL0 (0x000a) /* Port 1 Select 0 */
\r
943 #define OFS_P2SEL0 (0x000a) /* Port 2 Select 0 */
\r
944 #define OFS_P1SEL1 (0x000c) /* Port 1 Select 1 */
\r
945 #define OFS_P2SEL1 (0x000c) /* Port 2 Select 1 */
\r
946 #define OFS_P1SELC (0x0016) /* Port 1 Complement Select */
\r
947 #define OFS_P2SELC (0x0016) /* Port 2 Complement Select */
\r
948 #define OFS_P1IES (0x0018) /* Port 1 Interrupt Edge Select */
\r
949 #define OFS_P2IES (0x0018) /* Port 2 Interrupt Edge Select */
\r
950 #define OFS_P1IE (0x001a) /* Port 1 Interrupt Enable */
\r
951 #define OFS_P2IE (0x001a) /* Port 2 Interrupt Enable */
\r
952 #define OFS_P1IFG (0x001c) /* Port 1 Interrupt Flag */
\r
953 #define OFS_P2IFG (0x001c) /* Port 2 Interrupt Flag */
\r
954 #define OFS_P3IN (0x0020) /* Port 3 Input */
\r
955 #define OFS_P4IN (0x0020) /* Port 4 Input */
\r
956 #define OFS_P3OUT (0x0022) /* Port 3 Output */
\r
957 #define OFS_P4OUT (0x0022) /* Port 4 Output */
\r
958 #define OFS_P3DIR (0x0024) /* Port 3 Direction */
\r
959 #define OFS_P4DIR (0x0024) /* Port 4 Direction */
\r
960 #define OFS_P3REN (0x0026) /* Port 3 Resistor Enable */
\r
961 #define OFS_P4REN (0x0026) /* Port 4 Resistor Enable */
\r
962 #define OFS_P3DS (0x0028) /* Port 3 Drive Strength */
\r
963 #define OFS_P4DS (0x0028) /* Port 4 Drive Strength */
\r
964 #define OFS_P4SEL0 (0x002a) /* Port 4 Select 0 */
\r
965 #define OFS_P3SEL0 (0x002a) /* Port 3 Select 0 */
\r
966 #define OFS_P3SEL1 (0x002c) /* Port 3 Select 1 */
\r
967 #define OFS_P4SEL1 (0x002c) /* Port 4 Select 1 */
\r
968 #define OFS_P3SELC (0x0036) /* Port 3 Complement Select */
\r
969 #define OFS_P4SELC (0x0036) /* Port 4 Complement Select */
\r
970 #define OFS_P3IES (0x0038) /* Port 3 Interrupt Edge Select */
\r
971 #define OFS_P4IES (0x0038) /* Port 4 Interrupt Edge Select */
\r
972 #define OFS_P3IE (0x003a) /* Port 3 Interrupt Enable */
\r
973 #define OFS_P4IE (0x003a) /* Port 4 Interrupt Enable */
\r
974 #define OFS_P3IFG (0x003c) /* Port 3 Interrupt Flag */
\r
975 #define OFS_P4IFG (0x003c) /* Port 4 Interrupt Flag */
\r
976 #define OFS_P5IN (0x0040) /* Port 5 Input */
\r
977 #define OFS_P6IN (0x0040) /* Port 6 Input */
\r
978 #define OFS_P5OUT (0x0042) /* Port 5 Output */
\r
979 #define OFS_P6OUT (0x0042) /* Port 6 Output */
\r
980 #define OFS_P5DIR (0x0044) /* Port 5 Direction */
\r
981 #define OFS_P6DIR (0x0044) /* Port 6 Direction */
\r
982 #define OFS_P5REN (0x0046) /* Port 5 Resistor Enable */
\r
983 #define OFS_P6REN (0x0046) /* Port 6 Resistor Enable */
\r
984 #define OFS_P5DS (0x0048) /* Port 5 Drive Strength */
\r
985 #define OFS_P6DS (0x0048) /* Port 6 Drive Strength */
\r
986 #define OFS_P5SEL0 (0x004a) /* Port 5 Select 0 */
\r
987 #define OFS_P6SEL0 (0x004a) /* Port 6 Select 0 */
\r
988 #define OFS_P5SEL1 (0x004c) /* Port 5 Select 1 */
\r
989 #define OFS_P6SEL1 (0x004c) /* Port 6 Select 1 */
\r
990 #define OFS_P5SELC (0x0056) /* Port 5 Complement Select */
\r
991 #define OFS_P6SELC (0x0056) /* Port 6 Complement Select */
\r
992 #define OFS_P5IES (0x0058) /* Port 5 Interrupt Edge Select */
\r
993 #define OFS_P6IES (0x0058) /* Port 6 Interrupt Edge Select */
\r
994 #define OFS_P5IE (0x005a) /* Port 5 Interrupt Enable */
\r
995 #define OFS_P6IE (0x005a) /* Port 6 Interrupt Enable */
\r
996 #define OFS_P5IFG (0x005c) /* Port 5 Interrupt Flag */
\r
997 #define OFS_P6IFG (0x005c) /* Port 6 Interrupt Flag */
\r
998 #define OFS_P7IN (0x0060) /* Port 7 Input */
\r
999 #define OFS_P8IN (0x0060) /* Port 8 Input */
\r
1000 #define OFS_P7OUT (0x0062) /* Port 7 Output */
\r
1001 #define OFS_P8OUT (0x0062) /* Port 8 Output */
\r
1002 #define OFS_P7DIR (0x0064) /* Port 7 Direction */
\r
1003 #define OFS_P8DIR (0x0064) /* Port 8 Direction */
\r
1004 #define OFS_P7REN (0x0066) /* Port 7 Resistor Enable */
\r
1005 #define OFS_P8REN (0x0066) /* Port 8 Resistor Enable */
\r
1006 #define OFS_P7DS (0x0068) /* Port 7 Drive Strength */
\r
1007 #define OFS_P8DS (0x0068) /* Port 8 Drive Strength */
\r
1008 #define OFS_P7SEL0 (0x006a) /* Port 7 Select 0 */
\r
1009 #define OFS_P8SEL0 (0x006a) /* Port 8 Select 0 */
\r
1010 #define OFS_P7SEL1 (0x006c) /* Port 7 Select 1 */
\r
1011 #define OFS_P8SEL1 (0x006c) /* Port 8 Select 1 */
\r
1012 #define OFS_P7SELC (0x0076) /* Port 7 Complement Select */
\r
1013 #define OFS_P8SELC (0x0076) /* Port 8 Complement Select */
\r
1014 #define OFS_P7IES (0x0078) /* Port 7 Interrupt Edge Select */
\r
1015 #define OFS_P8IES (0x0078) /* Port 8 Interrupt Edge Select */
\r
1016 #define OFS_P7IE (0x007a) /* Port 7 Interrupt Enable */
\r
1017 #define OFS_P8IE (0x007a) /* Port 8 Interrupt Enable */
\r
1018 #define OFS_P7IFG (0x007c) /* Port 7 Interrupt Flag */
\r
1019 #define OFS_P8IFG (0x007c) /* Port 8 Interrupt Flag */
\r
1020 #define OFS_P9IN (0x0080) /* Port 9 Input */
\r
1021 #define OFS_P10IN (0x0080) /* Port 10 Input */
\r
1022 #define OFS_P9OUT (0x0082) /* Port 9 Output */
\r
1023 #define OFS_P10OUT (0x0082) /* Port 10 Output */
\r
1024 #define OFS_P9DIR (0x0084) /* Port 9 Direction */
\r
1025 #define OFS_P10DIR (0x0084) /* Port 10 Direction */
\r
1026 #define OFS_P9REN (0x0086) /* Port 9 Resistor Enable */
\r
1027 #define OFS_P10REN (0x0086) /* Port 10 Resistor Enable */
\r
1028 #define OFS_P9DS (0x0088) /* Port 9 Drive Strength */
\r
1029 #define OFS_P10DS (0x0088) /* Port 10 Drive Strength */
\r
1030 #define OFS_P9SEL0 (0x008a) /* Port 9 Select 0 */
\r
1031 #define OFS_P10SEL0 (0x008a) /* Port 10 Select 0 */
\r
1032 #define OFS_P9SEL1 (0x008c) /* Port 9 Select 1 */
\r
1033 #define OFS_P10SEL1 (0x008c) /* Port 10 Select 1 */
\r
1034 #define OFS_P9SELC (0x0096) /* Port 9 Complement Select */
\r
1035 #define OFS_P10SELC (0x0096) /* Port 10 Complement Select */
\r
1036 #define OFS_P9IES (0x0098) /* Port 9 Interrupt Edge Select */
\r
1037 #define OFS_P10IES (0x0098) /* Port 10 Interrupt Edge Select */
\r
1038 #define OFS_P9IE (0x009a) /* Port 9 Interrupt Enable */
\r
1039 #define OFS_P10IE (0x009a) /* Port 10 Interrupt Enable */
\r
1040 #define OFS_P9IFG (0x009c) /* Port 9 Interrupt Flag */
\r
1041 #define OFS_P10IFG (0x009c) /* Port 10 Interrupt Flag */
\r
1044 //*****************************************************************************
\r
1046 //*****************************************************************************
\r
1047 #define DMA_DEVICE_CFG (HWREG32(0x4000E000)) /* Device Configuration Status */
\r
1048 #define DMA_SW_CHTRIG (HWREG32(0x4000E004)) /* Software Channel Trigger Register */
\r
1049 #define DMA_CH0_SRCCFG (HWREG32(0x4000E010)) /* Channel n Source Configuration Register */
\r
1050 #define DMA_CH1_SRCCFG (HWREG32(0x4000E014)) /* Channel n Source Configuration Register */
\r
1051 #define DMA_CH2_SRCCFG (HWREG32(0x4000E018)) /* Channel n Source Configuration Register */
\r
1052 #define DMA_CH3_SRCCFG (HWREG32(0x4000E01C)) /* Channel n Source Configuration Register */
\r
1053 #define DMA_CH4_SRCCFG (HWREG32(0x4000E020)) /* Channel n Source Configuration Register */
\r
1054 #define DMA_CH5_SRCCFG (HWREG32(0x4000E024)) /* Channel n Source Configuration Register */
\r
1055 #define DMA_CH6_SRCCFG (HWREG32(0x4000E028)) /* Channel n Source Configuration Register */
\r
1056 #define DMA_CH7_SRCCFG (HWREG32(0x4000E02C)) /* Channel n Source Configuration Register */
\r
1057 #define DMA_CH8_SRCCFG (HWREG32(0x4000E030)) /* Channel n Source Configuration Register */
\r
1058 #define DMA_CH9_SRCCFG (HWREG32(0x4000E034)) /* Channel n Source Configuration Register */
\r
1059 #define DMA_CH10_SRCCFG (HWREG32(0x4000E038)) /* Channel n Source Configuration Register */
\r
1060 #define DMA_CH11_SRCCFG (HWREG32(0x4000E03C)) /* Channel n Source Configuration Register */
\r
1061 #define DMA_CH12_SRCCFG (HWREG32(0x4000E040)) /* Channel n Source Configuration Register */
\r
1062 #define DMA_CH13_SRCCFG (HWREG32(0x4000E044)) /* Channel n Source Configuration Register */
\r
1063 #define DMA_CH14_SRCCFG (HWREG32(0x4000E048)) /* Channel n Source Configuration Register */
\r
1064 #define DMA_CH15_SRCCFG (HWREG32(0x4000E04C)) /* Channel n Source Configuration Register */
\r
1065 #define DMA_CH16_SRCCFG (HWREG32(0x4000E050)) /* Channel n Source Configuration Register */
\r
1066 #define DMA_CH17_SRCCFG (HWREG32(0x4000E054)) /* Channel n Source Configuration Register */
\r
1067 #define DMA_CH18_SRCCFG (HWREG32(0x4000E058)) /* Channel n Source Configuration Register */
\r
1068 #define DMA_CH19_SRCCFG (HWREG32(0x4000E05C)) /* Channel n Source Configuration Register */
\r
1069 #define DMA_CH20_SRCCFG (HWREG32(0x4000E060)) /* Channel n Source Configuration Register */
\r
1070 #define DMA_CH21_SRCCFG (HWREG32(0x4000E064)) /* Channel n Source Configuration Register */
\r
1071 #define DMA_CH22_SRCCFG (HWREG32(0x4000E068)) /* Channel n Source Configuration Register */
\r
1072 #define DMA_CH23_SRCCFG (HWREG32(0x4000E06C)) /* Channel n Source Configuration Register */
\r
1073 #define DMA_CH24_SRCCFG (HWREG32(0x4000E070)) /* Channel n Source Configuration Register */
\r
1074 #define DMA_CH25_SRCCFG (HWREG32(0x4000E074)) /* Channel n Source Configuration Register */
\r
1075 #define DMA_CH26_SRCCFG (HWREG32(0x4000E078)) /* Channel n Source Configuration Register */
\r
1076 #define DMA_CH27_SRCCFG (HWREG32(0x4000E07C)) /* Channel n Source Configuration Register */
\r
1077 #define DMA_CH28_SRCCFG (HWREG32(0x4000E080)) /* Channel n Source Configuration Register */
\r
1078 #define DMA_CH29_SRCCFG (HWREG32(0x4000E084)) /* Channel n Source Configuration Register */
\r
1079 #define DMA_CH30_SRCCFG (HWREG32(0x4000E088)) /* Channel n Source Configuration Register */
\r
1080 #define DMA_CH31_SRCCFG (HWREG32(0x4000E08C)) /* Channel n Source Configuration Register */
\r
1081 #define DMA_INT1_SRCCFG (HWREG32(0x4000E100)) /* Interrupt 1 Source Channel Configuration */
\r
1082 #define DMA_INT2_SRCCFG (HWREG32(0x4000E104)) /* Interrupt 2 Source Channel Configuration Register */
\r
1083 #define DMA_INT3_SRCCFG (HWREG32(0x4000E108)) /* Interrupt 3 Source Channel Configuration Register */
\r
1084 #define DMA_INT0_SRCFLG (HWREG32(0x4000E110)) /* Interrupt 0 Source Channel Flag Register */
\r
1085 #define DMA_INT0_CLRFLG (HWREG32(0x4000E114)) /* Interrupt 0 Source Channel Clear Flag Register */
\r
1086 #define DMA_STAT (HWREG32(0x4000F000)) /* Status Register */
\r
1087 #define DMA_CFG (HWREG32(0x4000F004)) /* Configuration Register */
\r
1088 #define DMA_CTLBASE (HWREG32(0x4000F008)) /* Channel Control Data Base Pointer Register */
\r
1089 #define DMA_ATLBASE (HWREG32(0x4000F00C)) /* Channel Alternate Control Data Base Pointer Register */
\r
1090 #define DMA_WAITSTAT (HWREG32(0x4000F010)) /* Channel Wait on Request Status Register */
\r
1091 #define DMA_SWREQ (HWREG32(0x4000F014)) /* Channel Software Request Register */
\r
1092 #define DMA_USEBURSTSET (HWREG32(0x4000F018)) /* Channel Useburst Set Register */
\r
1093 #define DMA_USEBURSTCLR (HWREG32(0x4000F01C)) /* Channel Useburst Clear Register */
\r
1094 #define DMA_REQMASKSET (HWREG32(0x4000F020)) /* Channel Request Mask Set Register */
\r
1095 #define DMA_REQMASKCLR (HWREG32(0x4000F024)) /* Channel Request Mask Clear Register */
\r
1096 #define DMA_ENASET (HWREG32(0x4000F028)) /* Channel Enable Set Register */
\r
1097 #define DMA_ENACLR (HWREG32(0x4000F02C)) /* Channel Enable Clear Register */
\r
1098 #define DMA_ALTSET (HWREG32(0x4000F030)) /* Channel Primary-Alternate Set Register */
\r
1099 #define DMA_ALTCLR (HWREG32(0x4000F034)) /* Channel Primary-Alternate Clear Register */
\r
1100 #define DMA_PRIOSET (HWREG32(0x4000F038)) /* Channel Priority Set Register */
\r
1101 #define DMA_PRIOCLR (HWREG32(0x4000F03C)) /* Channel Priority Clear Register */
\r
1102 #define DMA_ERRCLR (HWREG32(0x4000F04C)) /* Bus Error Clear Register */
\r
1104 /* Register offsets from DMA_BASE address */
\r
1105 #define OFS_DMA_DEVICE_CFG (0x00000000) /* Device Configuration Status */
\r
1106 #define OFS_DMA_SW_CHTRIG (0x00000004) /* Software Channel Trigger Register */
\r
1107 #define OFS_DMA_CH0_SRCCFG (0x00000010) /* Channel n Source Configuration Register */
\r
1108 #define OFS_DMA_CH1_SRCCFG (0x00000014) /* Channel n Source Configuration Register */
\r
1109 #define OFS_DMA_CH2_SRCCFG (0x00000018) /* Channel n Source Configuration Register */
\r
1110 #define OFS_DMA_CH3_SRCCFG (0x0000001C) /* Channel n Source Configuration Register */
\r
1111 #define OFS_DMA_CH4_SRCCFG (0x00000020) /* Channel n Source Configuration Register */
\r
1112 #define OFS_DMA_CH5_SRCCFG (0x00000024) /* Channel n Source Configuration Register */
\r
1113 #define OFS_DMA_CH6_SRCCFG (0x00000028) /* Channel n Source Configuration Register */
\r
1114 #define OFS_DMA_CH7_SRCCFG (0x0000002C) /* Channel n Source Configuration Register */
\r
1115 #define OFS_DMA_CH8_SRCCFG (0x00000030) /* Channel n Source Configuration Register */
\r
1116 #define OFS_DMA_CH9_SRCCFG (0x00000034) /* Channel n Source Configuration Register */
\r
1117 #define OFS_DMA_CH10_SRCCFG (0x00000038) /* Channel n Source Configuration Register */
\r
1118 #define OFS_DMA_CH11_SRCCFG (0x0000003C) /* Channel n Source Configuration Register */
\r
1119 #define OFS_DMA_CH12_SRCCFG (0x00000040) /* Channel n Source Configuration Register */
\r
1120 #define OFS_DMA_CH13_SRCCFG (0x00000044) /* Channel n Source Configuration Register */
\r
1121 #define OFS_DMA_CH14_SRCCFG (0x00000048) /* Channel n Source Configuration Register */
\r
1122 #define OFS_DMA_CH15_SRCCFG (0x0000004C) /* Channel n Source Configuration Register */
\r
1123 #define OFS_DMA_CH16_SRCCFG (0x00000050) /* Channel n Source Configuration Register */
\r
1124 #define OFS_DMA_CH17_SRCCFG (0x00000054) /* Channel n Source Configuration Register */
\r
1125 #define OFS_DMA_CH18_SRCCFG (0x00000058) /* Channel n Source Configuration Register */
\r
1126 #define OFS_DMA_CH19_SRCCFG (0x0000005C) /* Channel n Source Configuration Register */
\r
1127 #define OFS_DMA_CH20_SRCCFG (0x00000060) /* Channel n Source Configuration Register */
\r
1128 #define OFS_DMA_CH21_SRCCFG (0x00000064) /* Channel n Source Configuration Register */
\r
1129 #define OFS_DMA_CH22_SRCCFG (0x00000068) /* Channel n Source Configuration Register */
\r
1130 #define OFS_DMA_CH23_SRCCFG (0x0000006C) /* Channel n Source Configuration Register */
\r
1131 #define OFS_DMA_CH24_SRCCFG (0x00000070) /* Channel n Source Configuration Register */
\r
1132 #define OFS_DMA_CH25_SRCCFG (0x00000074) /* Channel n Source Configuration Register */
\r
1133 #define OFS_DMA_CH26_SRCCFG (0x00000078) /* Channel n Source Configuration Register */
\r
1134 #define OFS_DMA_CH27_SRCCFG (0x0000007C) /* Channel n Source Configuration Register */
\r
1135 #define OFS_DMA_CH28_SRCCFG (0x00000080) /* Channel n Source Configuration Register */
\r
1136 #define OFS_DMA_CH29_SRCCFG (0x00000084) /* Channel n Source Configuration Register */
\r
1137 #define OFS_DMA_CH30_SRCCFG (0x00000088) /* Channel n Source Configuration Register */
\r
1138 #define OFS_DMA_CH31_SRCCFG (0x0000008C) /* Channel n Source Configuration Register */
\r
1139 #define OFS_DMA_INT1_SRCCFG (0x00000100) /* Interrupt 1 Source Channel Configuration */
\r
1140 #define OFS_DMA_INT2_SRCCFG (0x00000104) /* Interrupt 2 Source Channel Configuration Register */
\r
1141 #define OFS_DMA_INT3_SRCCFG (0x00000108) /* Interrupt 3 Source Channel Configuration Register */
\r
1142 #define OFS_DMA_INT0_SRCFLG (0x00000110) /* Interrupt 0 Source Channel Flag Register */
\r
1143 #define OFS_DMA_INT0_CLRFLG (0x00000114) /* Interrupt 0 Source Channel Clear Flag Register */
\r
1144 #define OFS_DMA_STAT (0x00001000) /* Status Register */
\r
1145 #define OFS_DMA_CFG (0x00001004) /* Configuration Register */
\r
1146 #define OFS_DMA_CTLBASE (0x00001008) /* Channel Control Data Base Pointer Register */
\r
1147 #define OFS_DMA_ATLBASE (0x0000100c) /* Channel Alternate Control Data Base Pointer Register */
\r
1148 #define OFS_DMA_WAITSTAT (0x00001010) /* Channel Wait on Request Status Register */
\r
1149 #define OFS_DMA_SWREQ (0x00001014) /* Channel Software Request Register */
\r
1150 #define OFS_DMA_USEBURSTSET (0x00001018) /* Channel Useburst Set Register */
\r
1151 #define OFS_DMA_USEBURSTCLR (0x0000101c) /* Channel Useburst Clear Register */
\r
1152 #define OFS_DMA_REQMASKSET (0x00001020) /* Channel Request Mask Set Register */
\r
1153 #define OFS_DMA_REQMASKCLR (0x00001024) /* Channel Request Mask Clear Register */
\r
1154 #define OFS_DMA_ENASET (0x00001028) /* Channel Enable Set Register */
\r
1155 #define OFS_DMA_ENACLR (0x0000102c) /* Channel Enable Clear Register */
\r
1156 #define OFS_DMA_ALTSET (0x00001030) /* Channel Primary-Alternate Set Register */
\r
1157 #define OFS_DMA_ALTCLR (0x00001034) /* Channel Primary-Alternate Clear Register */
\r
1158 #define OFS_DMA_PRIOSET (0x00001038) /* Channel Priority Set Register */
\r
1159 #define OFS_DMA_PRIOCLR (0x0000103c) /* Channel Priority Clear Register */
\r
1160 #define OFS_DMA_ERRCLR (0x0000104c) /* Bus Error Clear Register */
\r
1163 //*****************************************************************************
\r
1165 //*****************************************************************************
\r
1166 #define DWT_CTRL (HWREG32(0xE0001000)) /* DWT Control Register */
\r
1167 #define DWT_CYCCNT (HWREG32(0xE0001004)) /* DWT Current PC Sampler Cycle Count Register */
\r
1168 #define DWT_CPICNT (HWREG32(0xE0001008)) /* DWT CPI Count Register */
\r
1169 #define DWT_EXCCNT (HWREG32(0xE000100C)) /* DWT Exception Overhead Count Register */
\r
1170 #define DWT_SLEEPCNT (HWREG32(0xE0001010)) /* DWT Sleep Count Register */
\r
1171 #define DWT_LSUCNT (HWREG32(0xE0001014)) /* DWT LSU Count Register */
\r
1172 #define DWT_FOLDCNT (HWREG32(0xE0001018)) /* DWT Fold Count Register */
\r
1173 #define DWT_PCSR (HWREG32(0xE000101C)) /* DWT Program Counter Sample Register */
\r
1174 #define DWT_COMP0 (HWREG32(0xE0001020)) /* DWT Comparator Register 0 */
\r
1175 #define DWT_MASK0 (HWREG32(0xE0001024)) /* DWT Mask Register 0 */
\r
1176 #define DWT_FUNCTION0 (HWREG32(0xE0001028)) /* DWT Function Register 0 */
\r
1177 #define DWT_COMP1 (HWREG32(0xE0001030)) /* DWT Comparator Register 1 */
\r
1178 #define DWT_MASK1 (HWREG32(0xE0001034)) /* DWT Mask Register 1 */
\r
1179 #define DWT_FUNCTION1 (HWREG32(0xE0001038)) /* DWT Function Register 1 */
\r
1180 #define DWT_COMP2 (HWREG32(0xE0001040)) /* DWT Comparator Register 2 */
\r
1181 #define DWT_MASK2 (HWREG32(0xE0001044)) /* DWT Mask Register 2 */
\r
1182 #define DWT_FUNCTION2 (HWREG32(0xE0001048)) /* DWT Function Register 2 */
\r
1183 #define DWT_COMP3 (HWREG32(0xE0001050)) /* DWT Comparator Register 3 */
\r
1184 #define DWT_MASK3 (HWREG32(0xE0001054)) /* DWT Mask Register 3 */
\r
1185 #define DWT_FUNCTION3 (HWREG32(0xE0001058)) /* DWT Function Register 3 */
\r
1187 /* Register offsets from DWT_BASE address */
\r
1188 #define OFS_DWT_CTRL (0x00000000) /* DWT Control Register */
\r
1189 #define OFS_DWT_CYCCNT (0x00000004) /* DWT Current PC Sampler Cycle Count Register */
\r
1190 #define OFS_DWT_CPICNT (0x00000008) /* DWT CPI Count Register */
\r
1191 #define OFS_DWT_EXCCNT (0x0000000C) /* DWT Exception Overhead Count Register */
\r
1192 #define OFS_DWT_SLEEPCNT (0x00000010) /* DWT Sleep Count Register */
\r
1193 #define OFS_DWT_LSUCNT (0x00000014) /* DWT LSU Count Register */
\r
1194 #define OFS_DWT_FOLDCNT (0x00000018) /* DWT Fold Count Register */
\r
1195 #define OFS_DWT_PCSR (0x0000001C) /* DWT Program Counter Sample Register */
\r
1196 #define OFS_DWT_COMP0 (0x00000020) /* DWT Comparator Register 0 */
\r
1197 #define OFS_DWT_MASK0 (0x00000024) /* DWT Mask Register 0 */
\r
1198 #define OFS_DWT_FUNCTION0 (0x00000028) /* DWT Function Register 0 */
\r
1199 #define OFS_DWT_COMP1 (0x00000030) /* DWT Comparator Register 1 */
\r
1200 #define OFS_DWT_MASK1 (0x00000034) /* DWT Mask Register 1 */
\r
1201 #define OFS_DWT_FUNCTION1 (0x00000038) /* DWT Function Register 1 */
\r
1202 #define OFS_DWT_COMP2 (0x00000040) /* DWT Comparator Register 2 */
\r
1203 #define OFS_DWT_MASK2 (0x00000044) /* DWT Mask Register 2 */
\r
1204 #define OFS_DWT_FUNCTION2 (0x00000048) /* DWT Function Register 2 */
\r
1205 #define OFS_DWT_COMP3 (0x00000050) /* DWT Comparator Register 3 */
\r
1206 #define OFS_DWT_MASK3 (0x00000054) /* DWT Mask Register 3 */
\r
1207 #define OFS_DWT_FUNCTION3 (0x00000058) /* DWT Function Register 3 */
\r
1210 //*****************************************************************************
\r
1211 // EUSCI_A0 Registers
\r
1212 //*****************************************************************************
\r
1213 #define UCA0CTLW0 (HWREG16(0x40001000)) /* eUSCI_Ax Control Word Register 0 */
\r
1214 #define UCA0CTLW0_SPI (HWREG16(0x40001000)) /* */
\r
1215 #define UCA0CTLW1 (HWREG16(0x40001002)) /* eUSCI_Ax Control Word Register 1 */
\r
1216 #define UCA0BRW (HWREG16(0x40001006)) /* eUSCI_Ax Baud Rate Control Word Register */
\r
1217 #define UCA0BRW_SPI (HWREG16(0x40001006)) /* */
\r
1218 #define UCA0MCTLW (HWREG16(0x40001008)) /* eUSCI_Ax Modulation Control Word Register */
\r
1219 #define UCA0STATW (HWREG16(0x4000100A)) /* eUSCI_Ax Status Register */
\r
1220 #define UCA0STATW_SPI (HWREG16(0x4000100A)) /* */
\r
1221 #define UCA0RXBUF (HWREG16(0x4000100C)) /* eUSCI_Ax Receive Buffer Register */
\r
1222 #define UCA0RXBUF_SPI (HWREG16(0x4000100C)) /* */
\r
1223 #define UCA0TXBUF (HWREG16(0x4000100E)) /* eUSCI_Ax Transmit Buffer Register */
\r
1224 #define UCA0TXBUF_SPI (HWREG16(0x4000100E)) /* */
\r
1225 #define UCA0ABCTL (HWREG16(0x40001010)) /* eUSCI_Ax Auto Baud Rate Control Register */
\r
1226 #define UCA0IRCTL (HWREG16(0x40001012)) /* eUSCI_Ax IrDA Control Word Register */
\r
1227 #define UCA0IE (HWREG16(0x4000101A)) /* eUSCI_Ax Interrupt Enable Register */
\r
1228 #define UCA0IE_SPI (HWREG16(0x4000101A)) /* */
\r
1229 #define UCA0IFG (HWREG16(0x4000101C)) /* eUSCI_Ax Interrupt Flag Register */
\r
1230 #define UCA0IFG_SPI (HWREG16(0x4000101C)) /* */
\r
1231 #define UCA0IV (HWREG16(0x4000101E)) /* eUSCI_Ax Interrupt Vector Register */
\r
1232 #define UCA0IV_SPI (HWREG16(0x4000101E)) /* */
\r
1234 /* Register offsets from EUSCI_A0_BASE address */
\r
1235 #define OFS_UCA0CTLW0 (0x0000) /* eUSCI_Ax Control Word Register 0 */
\r
1236 #define OFS_UCA0CTLW0_SPI (0x0000) /* */
\r
1237 #define OFS_UCA0CTLW1 (0x0002) /* eUSCI_Ax Control Word Register 1 */
\r
1238 #define OFS_UCA0BRW (0x0006) /* eUSCI_Ax Baud Rate Control Word Register */
\r
1239 #define OFS_UCA0BRW_SPI (0x0006) /* */
\r
1240 #define OFS_UCA0MCTLW (0x0008) /* eUSCI_Ax Modulation Control Word Register */
\r
1241 #define OFS_UCA0STATW (0x000a) /* eUSCI_Ax Status Register */
\r
1242 #define OFS_UCA0STATW_SPI (0x000a) /* */
\r
1243 #define OFS_UCA0RXBUF (0x000c) /* eUSCI_Ax Receive Buffer Register */
\r
1244 #define OFS_UCA0RXBUF_SPI (0x000c) /* */
\r
1245 #define OFS_UCA0TXBUF (0x000e) /* eUSCI_Ax Transmit Buffer Register */
\r
1246 #define OFS_UCA0TXBUF_SPI (0x000e) /* */
\r
1247 #define OFS_UCA0ABCTL (0x0010) /* eUSCI_Ax Auto Baud Rate Control Register */
\r
1248 #define OFS_UCA0IRCTL (0x0012) /* eUSCI_Ax IrDA Control Word Register */
\r
1249 #define OFS_UCA0IE (0x001a) /* eUSCI_Ax Interrupt Enable Register */
\r
1250 #define OFS_UCA0IE_SPI (0x001a) /* */
\r
1251 #define OFS_UCA0IFG (0x001c) /* eUSCI_Ax Interrupt Flag Register */
\r
1252 #define OFS_UCA0IFG_SPI (0x001c) /* */
\r
1253 #define OFS_UCA0IV (0x001e) /* eUSCI_Ax Interrupt Vector Register */
\r
1254 #define OFS_UCA0IV_SPI (0x001e) /* */
\r
1256 #define UCA0CTL0 (HWREG8_L(UCA0CTLW0)) /* eUSCI_Ax Control 0 */
\r
1257 #define UCA0CTL1 (HWREG8_H(UCA0CTLW0)) /* eUSCI_Ax Control 1 */
\r
1258 #define UCA0BR0 (HWREG8_L(UCA0BRW)) /* eUSCI_Ax Baud Rate Control 0 */
\r
1259 #define UCA0BR1 (HWREG8_H(UCA0BRW)) /* eUSCI_Ax Baud Rate Control 1 */
\r
1260 #define UCA0IRTCTL (HWREG8_L(UCA0IRCTL)) /* eUSCI_Ax IrDA Transmit Control */
\r
1261 #define UCA0IRRCTL (HWREG8_H(UCA0IRCTL)) /* eUSCI_Ax IrDA Receive Control */
\r
1263 //*****************************************************************************
\r
1264 // EUSCI_A1 Registers
\r
1265 //*****************************************************************************
\r
1266 #define UCA1CTLW0 (HWREG16(0x40001400)) /* eUSCI_Ax Control Word Register 0 */
\r
1267 #define UCA1CTLW0_SPI (HWREG16(0x40001400)) /* */
\r
1268 #define UCA1CTLW1 (HWREG16(0x40001402)) /* eUSCI_Ax Control Word Register 1 */
\r
1269 #define UCA1BRW (HWREG16(0x40001406)) /* eUSCI_Ax Baud Rate Control Word Register */
\r
1270 #define UCA1BRW_SPI (HWREG16(0x40001406)) /* */
\r
1271 #define UCA1MCTLW (HWREG16(0x40001408)) /* eUSCI_Ax Modulation Control Word Register */
\r
1272 #define UCA1STATW (HWREG16(0x4000140A)) /* eUSCI_Ax Status Register */
\r
1273 #define UCA1STATW_SPI (HWREG16(0x4000140A)) /* */
\r
1274 #define UCA1RXBUF (HWREG16(0x4000140C)) /* eUSCI_Ax Receive Buffer Register */
\r
1275 #define UCA1RXBUF_SPI (HWREG16(0x4000140C)) /* */
\r
1276 #define UCA1TXBUF (HWREG16(0x4000140E)) /* eUSCI_Ax Transmit Buffer Register */
\r
1277 #define UCA1TXBUF_SPI (HWREG16(0x4000140E)) /* */
\r
1278 #define UCA1ABCTL (HWREG16(0x40001410)) /* eUSCI_Ax Auto Baud Rate Control Register */
\r
1279 #define UCA1IRCTL (HWREG16(0x40001412)) /* eUSCI_Ax IrDA Control Word Register */
\r
1280 #define UCA1IE (HWREG16(0x4000141A)) /* eUSCI_Ax Interrupt Enable Register */
\r
1281 #define UCA1IE_SPI (HWREG16(0x4000141A)) /* */
\r
1282 #define UCA1IFG (HWREG16(0x4000141C)) /* eUSCI_Ax Interrupt Flag Register */
\r
1283 #define UCA1IFG_SPI (HWREG16(0x4000141C)) /* */
\r
1284 #define UCA1IV (HWREG16(0x4000141E)) /* eUSCI_Ax Interrupt Vector Register */
\r
1285 #define UCA1IV_SPI (HWREG16(0x4000141E)) /* */
\r
1287 /* Register offsets from EUSCI_A1_BASE address */
\r
1288 #define OFS_UCA1CTLW0 (0x0000) /* eUSCI_Ax Control Word Register 0 */
\r
1289 #define OFS_UCA1CTLW0_SPI (0x0000) /* */
\r
1290 #define OFS_UCA1CTLW1 (0x0002) /* eUSCI_Ax Control Word Register 1 */
\r
1291 #define OFS_UCA1BRW (0x0006) /* eUSCI_Ax Baud Rate Control Word Register */
\r
1292 #define OFS_UCA1BRW_SPI (0x0006) /* */
\r
1293 #define OFS_UCA1MCTLW (0x0008) /* eUSCI_Ax Modulation Control Word Register */
\r
1294 #define OFS_UCA1STATW (0x000a) /* eUSCI_Ax Status Register */
\r
1295 #define OFS_UCA1STATW_SPI (0x000a) /* */
\r
1296 #define OFS_UCA1RXBUF (0x000c) /* eUSCI_Ax Receive Buffer Register */
\r
1297 #define OFS_UCA1RXBUF_SPI (0x000c) /* */
\r
1298 #define OFS_UCA1TXBUF (0x000e) /* eUSCI_Ax Transmit Buffer Register */
\r
1299 #define OFS_UCA1TXBUF_SPI (0x000e) /* */
\r
1300 #define OFS_UCA1ABCTL (0x0010) /* eUSCI_Ax Auto Baud Rate Control Register */
\r
1301 #define OFS_UCA1IRCTL (0x0012) /* eUSCI_Ax IrDA Control Word Register */
\r
1302 #define OFS_UCA1IE (0x001a) /* eUSCI_Ax Interrupt Enable Register */
\r
1303 #define OFS_UCA1IE_SPI (0x001a) /* */
\r
1304 #define OFS_UCA1IFG (0x001c) /* eUSCI_Ax Interrupt Flag Register */
\r
1305 #define OFS_UCA1IFG_SPI (0x001c) /* */
\r
1306 #define OFS_UCA1IV (0x001e) /* eUSCI_Ax Interrupt Vector Register */
\r
1307 #define OFS_UCA1IV_SPI (0x001e) /* */
\r
1309 #define UCA1CTL0 (HWREG8_L(UCA1CTLW0)) /* eUSCI_Ax Control 0 */
\r
1310 #define UCA1CTL1 (HWREG8_H(UCA1CTLW0)) /* eUSCI_Ax Control 1 */
\r
1311 #define UCA1BR0 (HWREG8_L(UCA1BRW)) /* eUSCI_Ax Baud Rate Control 0 */
\r
1312 #define UCA1BR1 (HWREG8_H(UCA1BRW)) /* eUSCI_Ax Baud Rate Control 1 */
\r
1313 #define UCA1IRTCTL (HWREG8_L(UCA1IRCTL)) /* eUSCI_Ax IrDA Transmit Control */
\r
1314 #define UCA1IRRCTL (HWREG8_H(UCA1IRCTL)) /* eUSCI_Ax IrDA Receive Control */
\r
1316 //*****************************************************************************
\r
1317 // EUSCI_A2 Registers
\r
1318 //*****************************************************************************
\r
1319 #define UCA2CTLW0 (HWREG16(0x40001800)) /* eUSCI_Ax Control Word Register 0 */
\r
1320 #define UCA2CTLW0_SPI (HWREG16(0x40001800)) /* */
\r
1321 #define UCA2CTLW1 (HWREG16(0x40001802)) /* eUSCI_Ax Control Word Register 1 */
\r
1322 #define UCA2BRW (HWREG16(0x40001806)) /* eUSCI_Ax Baud Rate Control Word Register */
\r
1323 #define UCA2BRW_SPI (HWREG16(0x40001806)) /* */
\r
1324 #define UCA2MCTLW (HWREG16(0x40001808)) /* eUSCI_Ax Modulation Control Word Register */
\r
1325 #define UCA2STATW (HWREG16(0x4000180A)) /* eUSCI_Ax Status Register */
\r
1326 #define UCA2STATW_SPI (HWREG16(0x4000180A)) /* */
\r
1327 #define UCA2RXBUF (HWREG16(0x4000180C)) /* eUSCI_Ax Receive Buffer Register */
\r
1328 #define UCA2RXBUF_SPI (HWREG16(0x4000180C)) /* */
\r
1329 #define UCA2TXBUF (HWREG16(0x4000180E)) /* eUSCI_Ax Transmit Buffer Register */
\r
1330 #define UCA2TXBUF_SPI (HWREG16(0x4000180E)) /* */
\r
1331 #define UCA2ABCTL (HWREG16(0x40001810)) /* eUSCI_Ax Auto Baud Rate Control Register */
\r
1332 #define UCA2IRCTL (HWREG16(0x40001812)) /* eUSCI_Ax IrDA Control Word Register */
\r
1333 #define UCA2IE (HWREG16(0x4000181A)) /* eUSCI_Ax Interrupt Enable Register */
\r
1334 #define UCA2IE_SPI (HWREG16(0x4000181A)) /* */
\r
1335 #define UCA2IFG (HWREG16(0x4000181C)) /* eUSCI_Ax Interrupt Flag Register */
\r
1336 #define UCA2IFG_SPI (HWREG16(0x4000181C)) /* */
\r
1337 #define UCA2IV (HWREG16(0x4000181E)) /* eUSCI_Ax Interrupt Vector Register */
\r
1338 #define UCA2IV_SPI (HWREG16(0x4000181E)) /* */
\r
1340 /* Register offsets from EUSCI_A2_BASE address */
\r
1341 #define OFS_UCA2CTLW0 (0x0000) /* eUSCI_Ax Control Word Register 0 */
\r
1342 #define OFS_UCA2CTLW0_SPI (0x0000) /* */
\r
1343 #define OFS_UCA2CTLW1 (0x0002) /* eUSCI_Ax Control Word Register 1 */
\r
1344 #define OFS_UCA2BRW (0x0006) /* eUSCI_Ax Baud Rate Control Word Register */
\r
1345 #define OFS_UCA2BRW_SPI (0x0006) /* */
\r
1346 #define OFS_UCA2MCTLW (0x0008) /* eUSCI_Ax Modulation Control Word Register */
\r
1347 #define OFS_UCA2STATW (0x000a) /* eUSCI_Ax Status Register */
\r
1348 #define OFS_UCA2STATW_SPI (0x000a) /* */
\r
1349 #define OFS_UCA2RXBUF (0x000c) /* eUSCI_Ax Receive Buffer Register */
\r
1350 #define OFS_UCA2RXBUF_SPI (0x000c) /* */
\r
1351 #define OFS_UCA2TXBUF (0x000e) /* eUSCI_Ax Transmit Buffer Register */
\r
1352 #define OFS_UCA2TXBUF_SPI (0x000e) /* */
\r
1353 #define OFS_UCA2ABCTL (0x0010) /* eUSCI_Ax Auto Baud Rate Control Register */
\r
1354 #define OFS_UCA2IRCTL (0x0012) /* eUSCI_Ax IrDA Control Word Register */
\r
1355 #define OFS_UCA2IE (0x001a) /* eUSCI_Ax Interrupt Enable Register */
\r
1356 #define OFS_UCA2IE_SPI (0x001a) /* */
\r
1357 #define OFS_UCA2IFG (0x001c) /* eUSCI_Ax Interrupt Flag Register */
\r
1358 #define OFS_UCA2IFG_SPI (0x001c) /* */
\r
1359 #define OFS_UCA2IV (0x001e) /* eUSCI_Ax Interrupt Vector Register */
\r
1360 #define OFS_UCA2IV_SPI (0x001e) /* */
\r
1362 #define UCA2CTL0 (HWREG8_L(UCA2CTLW0)) /* eUSCI_Ax Control 0 */
\r
1363 #define UCA2CTL1 (HWREG8_H(UCA2CTLW0)) /* eUSCI_Ax Control 1 */
\r
1364 #define UCA2BR0 (HWREG8_L(UCA2BRW)) /* eUSCI_Ax Baud Rate Control 0 */
\r
1365 #define UCA2BR1 (HWREG8_H(UCA2BRW)) /* eUSCI_Ax Baud Rate Control 1 */
\r
1366 #define UCA2IRTCTL (HWREG8_L(UCA2IRCTL)) /* eUSCI_Ax IrDA Transmit Control */
\r
1367 #define UCA2IRRCTL (HWREG8_H(UCA2IRCTL)) /* eUSCI_Ax IrDA Receive Control */
\r
1369 //*****************************************************************************
\r
1370 // EUSCI_A3 Registers
\r
1371 //*****************************************************************************
\r
1372 #define UCA3CTLW0 (HWREG16(0x40001C00)) /* eUSCI_Ax Control Word Register 0 */
\r
1373 #define UCA3CTLW0_SPI (HWREG16(0x40001C00)) /* */
\r
1374 #define UCA3CTLW1 (HWREG16(0x40001C02)) /* eUSCI_Ax Control Word Register 1 */
\r
1375 #define UCA3BRW (HWREG16(0x40001C06)) /* eUSCI_Ax Baud Rate Control Word Register */
\r
1376 #define UCA3BRW_SPI (HWREG16(0x40001C06)) /* */
\r
1377 #define UCA3MCTLW (HWREG16(0x40001C08)) /* eUSCI_Ax Modulation Control Word Register */
\r
1378 #define UCA3STATW (HWREG16(0x40001C0A)) /* eUSCI_Ax Status Register */
\r
1379 #define UCA3STATW_SPI (HWREG16(0x40001C0A)) /* */
\r
1380 #define UCA3RXBUF (HWREG16(0x40001C0C)) /* eUSCI_Ax Receive Buffer Register */
\r
1381 #define UCA3RXBUF_SPI (HWREG16(0x40001C0C)) /* */
\r
1382 #define UCA3TXBUF (HWREG16(0x40001C0E)) /* eUSCI_Ax Transmit Buffer Register */
\r
1383 #define UCA3TXBUF_SPI (HWREG16(0x40001C0E)) /* */
\r
1384 #define UCA3ABCTL (HWREG16(0x40001C10)) /* eUSCI_Ax Auto Baud Rate Control Register */
\r
1385 #define UCA3IRCTL (HWREG16(0x40001C12)) /* eUSCI_Ax IrDA Control Word Register */
\r
1386 #define UCA3IE (HWREG16(0x40001C1A)) /* eUSCI_Ax Interrupt Enable Register */
\r
1387 #define UCA3IE_SPI (HWREG16(0x40001C1A)) /* */
\r
1388 #define UCA3IFG (HWREG16(0x40001C1C)) /* eUSCI_Ax Interrupt Flag Register */
\r
1389 #define UCA3IFG_SPI (HWREG16(0x40001C1C)) /* */
\r
1390 #define UCA3IV (HWREG16(0x40001C1E)) /* eUSCI_Ax Interrupt Vector Register */
\r
1391 #define UCA3IV_SPI (HWREG16(0x40001C1E)) /* */
\r
1393 /* Register offsets from EUSCI_A3_BASE address */
\r
1394 #define OFS_UCA3CTLW0 (0x0000) /* eUSCI_Ax Control Word Register 0 */
\r
1395 #define OFS_UCA3CTLW0_SPI (0x0000) /* */
\r
1396 #define OFS_UCA3CTLW1 (0x0002) /* eUSCI_Ax Control Word Register 1 */
\r
1397 #define OFS_UCA3BRW (0x0006) /* eUSCI_Ax Baud Rate Control Word Register */
\r
1398 #define OFS_UCA3BRW_SPI (0x0006) /* */
\r
1399 #define OFS_UCA3MCTLW (0x0008) /* eUSCI_Ax Modulation Control Word Register */
\r
1400 #define OFS_UCA3STATW (0x000a) /* eUSCI_Ax Status Register */
\r
1401 #define OFS_UCA3STATW_SPI (0x000a) /* */
\r
1402 #define OFS_UCA3RXBUF (0x000c) /* eUSCI_Ax Receive Buffer Register */
\r
1403 #define OFS_UCA3RXBUF_SPI (0x000c) /* */
\r
1404 #define OFS_UCA3TXBUF (0x000e) /* eUSCI_Ax Transmit Buffer Register */
\r
1405 #define OFS_UCA3TXBUF_SPI (0x000e) /* */
\r
1406 #define OFS_UCA3ABCTL (0x0010) /* eUSCI_Ax Auto Baud Rate Control Register */
\r
1407 #define OFS_UCA3IRCTL (0x0012) /* eUSCI_Ax IrDA Control Word Register */
\r
1408 #define OFS_UCA3IE (0x001a) /* eUSCI_Ax Interrupt Enable Register */
\r
1409 #define OFS_UCA3IE_SPI (0x001a) /* */
\r
1410 #define OFS_UCA3IFG (0x001c) /* eUSCI_Ax Interrupt Flag Register */
\r
1411 #define OFS_UCA3IFG_SPI (0x001c) /* */
\r
1412 #define OFS_UCA3IV (0x001e) /* eUSCI_Ax Interrupt Vector Register */
\r
1413 #define OFS_UCA3IV_SPI (0x001e) /* */
\r
1415 #define UCA3CTL0 (HWREG8_L(UCA3CTLW0)) /* eUSCI_Ax Control 0 */
\r
1416 #define UCA3CTL1 (HWREG8_H(UCA3CTLW0)) /* eUSCI_Ax Control 1 */
\r
1417 #define UCA3BR0 (HWREG8_L(UCA3BRW)) /* eUSCI_Ax Baud Rate Control 0 */
\r
1418 #define UCA3BR1 (HWREG8_H(UCA3BRW)) /* eUSCI_Ax Baud Rate Control 1 */
\r
1419 #define UCA3IRTCTL (HWREG8_L(UCA3IRCTL)) /* eUSCI_Ax IrDA Transmit Control */
\r
1420 #define UCA3IRRCTL (HWREG8_H(UCA3IRCTL)) /* eUSCI_Ax IrDA Receive Control */
\r
1422 //*****************************************************************************
\r
1423 // EUSCI_B0 Registers
\r
1424 //*****************************************************************************
\r
1425 #define UCB0CTLW0 (HWREG16(0x40002000)) /* eUSCI_Bx Control Word Register 0 */
\r
1426 #define UCB0CTLW0_SPI (HWREG16(0x40002000)) /* */
\r
1427 #define UCB0CTLW1 (HWREG16(0x40002002)) /* eUSCI_Bx Control Word Register 1 */
\r
1428 #define UCB0BRW (HWREG16(0x40002006)) /* eUSCI_Bx Baud Rate Control Word Register */
\r
1429 #define UCB0BRW_SPI (HWREG16(0x40002006)) /* */
\r
1430 #define UCB0STATW (HWREG16(0x40002008)) /* eUSCI_Bx Status Register */
\r
1431 #define UCB0STATW_SPI (HWREG16(0x40002008)) /* */
\r
1432 #define UCB0TBCNT (HWREG16(0x4000200A)) /* eUSCI_Bx Byte Counter Threshold Register */
\r
1433 #define UCB0RXBUF (HWREG16(0x4000200C)) /* eUSCI_Bx Receive Buffer Register */
\r
1434 #define UCB0RXBUF_SPI (HWREG16(0x4000200C)) /* */
\r
1435 #define UCB0TXBUF (HWREG16(0x4000200E)) /* eUSCI_Bx Transmit Buffer Register */
\r
1436 #define UCB0TXBUF_SPI (HWREG16(0x4000200E)) /* */
\r
1437 #define UCB0I2COA0 (HWREG16(0x40002014)) /* eUSCI_Bx I2C Own Address 0 Register */
\r
1438 #define UCB0I2COA1 (HWREG16(0x40002016)) /* eUSCI_Bx I2C Own Address 1 Register */
\r
1439 #define UCB0I2COA2 (HWREG16(0x40002018)) /* eUSCI_Bx I2C Own Address 2 Register */
\r
1440 #define UCB0I2COA3 (HWREG16(0x4000201A)) /* eUSCI_Bx I2C Own Address 3 Register */
\r
1441 #define UCB0ADDRX (HWREG16(0x4000201C)) /* eUSCI_Bx I2C Received Address Register */
\r
1442 #define UCB0ADDMASK (HWREG16(0x4000201E)) /* eUSCI_Bx I2C Address Mask Register */
\r
1443 #define UCB0I2CSA (HWREG16(0x40002020)) /* eUSCI_Bx I2C Slave Address Register */
\r
1444 #define UCB0IE (HWREG16(0x4000202A)) /* eUSCI_Bx Interrupt Enable Register */
\r
1445 #define UCB0IE_SPI (HWREG16(0x4000202A)) /* */
\r
1446 #define UCB0IFG (HWREG16(0x4000202C)) /* eUSCI_Bx Interrupt Flag Register */
\r
1447 #define UCB0IFG_SPI (HWREG16(0x4000202C)) /* */
\r
1448 #define UCB0IV (HWREG16(0x4000202E)) /* eUSCI_Bx Interrupt Vector Register */
\r
1449 #define UCB0IV_SPI (HWREG16(0x4000202E)) /* */
\r
1451 /* Register offsets from EUSCI_B0_BASE address */
\r
1452 #define OFS_UCB0CTLW0 (0x0000) /* eUSCI_Bx Control Word Register 0 */
\r
1453 #define OFS_UCB0CTLW0_SPI (0x0000) /* */
\r
1454 #define OFS_UCB0CTLW1 (0x0002) /* eUSCI_Bx Control Word Register 1 */
\r
1455 #define OFS_UCB0BRW (0x0006) /* eUSCI_Bx Baud Rate Control Word Register */
\r
1456 #define OFS_UCB0BRW_SPI (0x0006) /* */
\r
1457 #define OFS_UCB0STATW (0x0008) /* eUSCI_Bx Status Register */
\r
1458 #define OFS_UCB0STATW_SPI (0x0008) /* */
\r
1459 #define OFS_UCB0TBCNT (0x000a) /* eUSCI_Bx Byte Counter Threshold Register */
\r
1460 #define OFS_UCB0RXBUF (0x000c) /* eUSCI_Bx Receive Buffer Register */
\r
1461 #define OFS_UCB0RXBUF_SPI (0x000c) /* */
\r
1462 #define OFS_UCB0TXBUF (0x000e) /* eUSCI_Bx Transmit Buffer Register */
\r
1463 #define OFS_UCB0TXBUF_SPI (0x000e) /* */
\r
1464 #define OFS_UCB0I2COA0 (0x0014) /* eUSCI_Bx I2C Own Address 0 Register */
\r
1465 #define OFS_UCB0I2COA1 (0x0016) /* eUSCI_Bx I2C Own Address 1 Register */
\r
1466 #define OFS_UCB0I2COA2 (0x0018) /* eUSCI_Bx I2C Own Address 2 Register */
\r
1467 #define OFS_UCB0I2COA3 (0x001a) /* eUSCI_Bx I2C Own Address 3 Register */
\r
1468 #define OFS_UCB0ADDRX (0x001c) /* eUSCI_Bx I2C Received Address Register */
\r
1469 #define OFS_UCB0ADDMASK (0x001e) /* eUSCI_Bx I2C Address Mask Register */
\r
1470 #define OFS_UCB0I2CSA (0x0020) /* eUSCI_Bx I2C Slave Address Register */
\r
1471 #define OFS_UCB0IE (0x002a) /* eUSCI_Bx Interrupt Enable Register */
\r
1472 #define OFS_UCB0IE_SPI (0x002a) /* */
\r
1473 #define OFS_UCB0IFG (0x002c) /* eUSCI_Bx Interrupt Flag Register */
\r
1474 #define OFS_UCB0IFG_SPI (0x002c) /* */
\r
1475 #define OFS_UCB0IV (0x002e) /* eUSCI_Bx Interrupt Vector Register */
\r
1476 #define OFS_UCB0IV_SPI (0x002e) /* */
\r
1478 #define UCB0CTL0 (HWREG8_L(UCB0CTLW0)) /* eUSCI_Bx Control 1 */
\r
1479 #define UCB0CTL1 (HWREG8_H(UCB0CTLW0)) /* eUSCI_Bx Control 0 */
\r
1480 #define UCB0BR0 (HWREG8_L(UCB0BRW)) /* eUSCI_Bx Bit Rate Control 0 */
\r
1481 #define UCB0BR1 (HWREG8_H(UCB0BRW)) /* eUSCI_Bx Bit Rate Control 1 */
\r
1482 #define UCB0STAT (HWREG8_L(UCB0STATW)) /* eUSCI_Bx Status */
\r
1483 #define UCB0BCNT (HWREG8_H(UCB0STATW)) /* eUSCI_Bx Byte Counter Register */
\r
1485 //*****************************************************************************
\r
1486 // EUSCI_B1 Registers
\r
1487 //*****************************************************************************
\r
1488 #define UCB1CTLW0 (HWREG16(0x40002400)) /* eUSCI_Bx Control Word Register 0 */
\r
1489 #define UCB1CTLW0_SPI (HWREG16(0x40002400)) /* */
\r
1490 #define UCB1CTLW1 (HWREG16(0x40002402)) /* eUSCI_Bx Control Word Register 1 */
\r
1491 #define UCB1BRW (HWREG16(0x40002406)) /* eUSCI_Bx Baud Rate Control Word Register */
\r
1492 #define UCB1BRW_SPI (HWREG16(0x40002406)) /* */
\r
1493 #define UCB1STATW (HWREG16(0x40002408)) /* eUSCI_Bx Status Register */
\r
1494 #define UCB1STATW_SPI (HWREG16(0x40002408)) /* */
\r
1495 #define UCB1TBCNT (HWREG16(0x4000240A)) /* eUSCI_Bx Byte Counter Threshold Register */
\r
1496 #define UCB1RXBUF (HWREG16(0x4000240C)) /* eUSCI_Bx Receive Buffer Register */
\r
1497 #define UCB1RXBUF_SPI (HWREG16(0x4000240C)) /* */
\r
1498 #define UCB1TXBUF (HWREG16(0x4000240E)) /* eUSCI_Bx Transmit Buffer Register */
\r
1499 #define UCB1TXBUF_SPI (HWREG16(0x4000240E)) /* */
\r
1500 #define UCB1I2COA0 (HWREG16(0x40002414)) /* eUSCI_Bx I2C Own Address 0 Register */
\r
1501 #define UCB1I2COA1 (HWREG16(0x40002416)) /* eUSCI_Bx I2C Own Address 1 Register */
\r
1502 #define UCB1I2COA2 (HWREG16(0x40002418)) /* eUSCI_Bx I2C Own Address 2 Register */
\r
1503 #define UCB1I2COA3 (HWREG16(0x4000241A)) /* eUSCI_Bx I2C Own Address 3 Register */
\r
1504 #define UCB1ADDRX (HWREG16(0x4000241C)) /* eUSCI_Bx I2C Received Address Register */
\r
1505 #define UCB1ADDMASK (HWREG16(0x4000241E)) /* eUSCI_Bx I2C Address Mask Register */
\r
1506 #define UCB1I2CSA (HWREG16(0x40002420)) /* eUSCI_Bx I2C Slave Address Register */
\r
1507 #define UCB1IE (HWREG16(0x4000242A)) /* eUSCI_Bx Interrupt Enable Register */
\r
1508 #define UCB1IE_SPI (HWREG16(0x4000242A)) /* */
\r
1509 #define UCB1IFG (HWREG16(0x4000242C)) /* eUSCI_Bx Interrupt Flag Register */
\r
1510 #define UCB1IFG_SPI (HWREG16(0x4000242C)) /* */
\r
1511 #define UCB1IV (HWREG16(0x4000242E)) /* eUSCI_Bx Interrupt Vector Register */
\r
1512 #define UCB1IV_SPI (HWREG16(0x4000242E)) /* */
\r
1514 /* Register offsets from EUSCI_B1_BASE address */
\r
1515 #define OFS_UCB1CTLW0 (0x0000) /* eUSCI_Bx Control Word Register 0 */
\r
1516 #define OFS_UCB1CTLW0_SPI (0x0000) /* */
\r
1517 #define OFS_UCB1CTLW1 (0x0002) /* eUSCI_Bx Control Word Register 1 */
\r
1518 #define OFS_UCB1BRW (0x0006) /* eUSCI_Bx Baud Rate Control Word Register */
\r
1519 #define OFS_UCB1BRW_SPI (0x0006) /* */
\r
1520 #define OFS_UCB1STATW (0x0008) /* eUSCI_Bx Status Register */
\r
1521 #define OFS_UCB1STATW_SPI (0x0008) /* */
\r
1522 #define OFS_UCB1TBCNT (0x000a) /* eUSCI_Bx Byte Counter Threshold Register */
\r
1523 #define OFS_UCB1RXBUF (0x000c) /* eUSCI_Bx Receive Buffer Register */
\r
1524 #define OFS_UCB1RXBUF_SPI (0x000c) /* */
\r
1525 #define OFS_UCB1TXBUF (0x000e) /* eUSCI_Bx Transmit Buffer Register */
\r
1526 #define OFS_UCB1TXBUF_SPI (0x000e) /* */
\r
1527 #define OFS_UCB1I2COA0 (0x0014) /* eUSCI_Bx I2C Own Address 0 Register */
\r
1528 #define OFS_UCB1I2COA1 (0x0016) /* eUSCI_Bx I2C Own Address 1 Register */
\r
1529 #define OFS_UCB1I2COA2 (0x0018) /* eUSCI_Bx I2C Own Address 2 Register */
\r
1530 #define OFS_UCB1I2COA3 (0x001a) /* eUSCI_Bx I2C Own Address 3 Register */
\r
1531 #define OFS_UCB1ADDRX (0x001c) /* eUSCI_Bx I2C Received Address Register */
\r
1532 #define OFS_UCB1ADDMASK (0x001e) /* eUSCI_Bx I2C Address Mask Register */
\r
1533 #define OFS_UCB1I2CSA (0x0020) /* eUSCI_Bx I2C Slave Address Register */
\r
1534 #define OFS_UCB1IE (0x002a) /* eUSCI_Bx Interrupt Enable Register */
\r
1535 #define OFS_UCB1IE_SPI (0x002a) /* */
\r
1536 #define OFS_UCB1IFG (0x002c) /* eUSCI_Bx Interrupt Flag Register */
\r
1537 #define OFS_UCB1IFG_SPI (0x002c) /* */
\r
1538 #define OFS_UCB1IV (0x002e) /* eUSCI_Bx Interrupt Vector Register */
\r
1539 #define OFS_UCB1IV_SPI (0x002e) /* */
\r
1541 #define UCB1CTL0 (HWREG8_L(UCB1CTLW0)) /* eUSCI_Bx Control 1 */
\r
1542 #define UCB1CTL1 (HWREG8_H(UCB1CTLW0)) /* eUSCI_Bx Control 0 */
\r
1543 #define UCB1BR0 (HWREG8_L(UCB1BRW)) /* eUSCI_Bx Bit Rate Control 0 */
\r
1544 #define UCB1BR1 (HWREG8_H(UCB1BRW)) /* eUSCI_Bx Bit Rate Control 1 */
\r
1545 #define UCB1STAT (HWREG8_L(UCB1STATW)) /* eUSCI_Bx Status */
\r
1546 #define UCB1BCNT (HWREG8_H(UCB1STATW)) /* eUSCI_Bx Byte Counter Register */
\r
1548 //*****************************************************************************
\r
1549 // EUSCI_B2 Registers
\r
1550 //*****************************************************************************
\r
1551 #define UCB2CTLW0 (HWREG16(0x40002800)) /* eUSCI_Bx Control Word Register 0 */
\r
1552 #define UCB2CTLW0_SPI (HWREG16(0x40002800)) /* */
\r
1553 #define UCB2CTLW1 (HWREG16(0x40002802)) /* eUSCI_Bx Control Word Register 1 */
\r
1554 #define UCB2BRW (HWREG16(0x40002806)) /* eUSCI_Bx Baud Rate Control Word Register */
\r
1555 #define UCB2BRW_SPI (HWREG16(0x40002806)) /* */
\r
1556 #define UCB2STATW (HWREG16(0x40002808)) /* eUSCI_Bx Status Register */
\r
1557 #define UCB2STATW_SPI (HWREG16(0x40002808)) /* */
\r
1558 #define UCB2TBCNT (HWREG16(0x4000280A)) /* eUSCI_Bx Byte Counter Threshold Register */
\r
1559 #define UCB2RXBUF (HWREG16(0x4000280C)) /* eUSCI_Bx Receive Buffer Register */
\r
1560 #define UCB2RXBUF_SPI (HWREG16(0x4000280C)) /* */
\r
1561 #define UCB2TXBUF (HWREG16(0x4000280E)) /* eUSCI_Bx Transmit Buffer Register */
\r
1562 #define UCB2TXBUF_SPI (HWREG16(0x4000280E)) /* */
\r
1563 #define UCB2I2COA0 (HWREG16(0x40002814)) /* eUSCI_Bx I2C Own Address 0 Register */
\r
1564 #define UCB2I2COA1 (HWREG16(0x40002816)) /* eUSCI_Bx I2C Own Address 1 Register */
\r
1565 #define UCB2I2COA2 (HWREG16(0x40002818)) /* eUSCI_Bx I2C Own Address 2 Register */
\r
1566 #define UCB2I2COA3 (HWREG16(0x4000281A)) /* eUSCI_Bx I2C Own Address 3 Register */
\r
1567 #define UCB2ADDRX (HWREG16(0x4000281C)) /* eUSCI_Bx I2C Received Address Register */
\r
1568 #define UCB2ADDMASK (HWREG16(0x4000281E)) /* eUSCI_Bx I2C Address Mask Register */
\r
1569 #define UCB2I2CSA (HWREG16(0x40002820)) /* eUSCI_Bx I2C Slave Address Register */
\r
1570 #define UCB2IE (HWREG16(0x4000282A)) /* eUSCI_Bx Interrupt Enable Register */
\r
1571 #define UCB2IE_SPI (HWREG16(0x4000282A)) /* */
\r
1572 #define UCB2IFG (HWREG16(0x4000282C)) /* eUSCI_Bx Interrupt Flag Register */
\r
1573 #define UCB2IFG_SPI (HWREG16(0x4000282C)) /* */
\r
1574 #define UCB2IV (HWREG16(0x4000282E)) /* eUSCI_Bx Interrupt Vector Register */
\r
1575 #define UCB2IV_SPI (HWREG16(0x4000282E)) /* */
\r
1577 /* Register offsets from EUSCI_B2_BASE address */
\r
1578 #define OFS_UCB2CTLW0 (0x0000) /* eUSCI_Bx Control Word Register 0 */
\r
1579 #define OFS_UCB2CTLW0_SPI (0x0000) /* */
\r
1580 #define OFS_UCB2CTLW1 (0x0002) /* eUSCI_Bx Control Word Register 1 */
\r
1581 #define OFS_UCB2BRW (0x0006) /* eUSCI_Bx Baud Rate Control Word Register */
\r
1582 #define OFS_UCB2BRW_SPI (0x0006) /* */
\r
1583 #define OFS_UCB2STATW (0x0008) /* eUSCI_Bx Status Register */
\r
1584 #define OFS_UCB2STATW_SPI (0x0008) /* */
\r
1585 #define OFS_UCB2TBCNT (0x000a) /* eUSCI_Bx Byte Counter Threshold Register */
\r
1586 #define OFS_UCB2RXBUF (0x000c) /* eUSCI_Bx Receive Buffer Register */
\r
1587 #define OFS_UCB2RXBUF_SPI (0x000c) /* */
\r
1588 #define OFS_UCB2TXBUF (0x000e) /* eUSCI_Bx Transmit Buffer Register */
\r
1589 #define OFS_UCB2TXBUF_SPI (0x000e) /* */
\r
1590 #define OFS_UCB2I2COA0 (0x0014) /* eUSCI_Bx I2C Own Address 0 Register */
\r
1591 #define OFS_UCB2I2COA1 (0x0016) /* eUSCI_Bx I2C Own Address 1 Register */
\r
1592 #define OFS_UCB2I2COA2 (0x0018) /* eUSCI_Bx I2C Own Address 2 Register */
\r
1593 #define OFS_UCB2I2COA3 (0x001a) /* eUSCI_Bx I2C Own Address 3 Register */
\r
1594 #define OFS_UCB2ADDRX (0x001c) /* eUSCI_Bx I2C Received Address Register */
\r
1595 #define OFS_UCB2ADDMASK (0x001e) /* eUSCI_Bx I2C Address Mask Register */
\r
1596 #define OFS_UCB2I2CSA (0x0020) /* eUSCI_Bx I2C Slave Address Register */
\r
1597 #define OFS_UCB2IE (0x002a) /* eUSCI_Bx Interrupt Enable Register */
\r
1598 #define OFS_UCB2IE_SPI (0x002a) /* */
\r
1599 #define OFS_UCB2IFG (0x002c) /* eUSCI_Bx Interrupt Flag Register */
\r
1600 #define OFS_UCB2IFG_SPI (0x002c) /* */
\r
1601 #define OFS_UCB2IV (0x002e) /* eUSCI_Bx Interrupt Vector Register */
\r
1602 #define OFS_UCB2IV_SPI (0x002e) /* */
\r
1604 #define UCB2CTL0 (HWREG8_L(UCB2CTLW0)) /* eUSCI_Bx Control 1 */
\r
1605 #define UCB2CTL1 (HWREG8_H(UCB2CTLW0)) /* eUSCI_Bx Control 0 */
\r
1606 #define UCB2BR0 (HWREG8_L(UCB2BRW)) /* eUSCI_Bx Bit Rate Control 0 */
\r
1607 #define UCB2BR1 (HWREG8_H(UCB2BRW)) /* eUSCI_Bx Bit Rate Control 1 */
\r
1608 #define UCB2STAT (HWREG8_L(UCB2STATW)) /* eUSCI_Bx Status */
\r
1609 #define UCB2BCNT (HWREG8_H(UCB2STATW)) /* eUSCI_Bx Byte Counter Register */
\r
1611 //*****************************************************************************
\r
1612 // EUSCI_B3 Registers
\r
1613 //*****************************************************************************
\r
1614 #define UCB3CTLW0 (HWREG16(0x40002C00)) /* eUSCI_Bx Control Word Register 0 */
\r
1615 #define UCB3CTLW0_SPI (HWREG16(0x40002C00)) /* */
\r
1616 #define UCB3CTLW1 (HWREG16(0x40002C02)) /* eUSCI_Bx Control Word Register 1 */
\r
1617 #define UCB3BRW (HWREG16(0x40002C06)) /* eUSCI_Bx Baud Rate Control Word Register */
\r
1618 #define UCB3BRW_SPI (HWREG16(0x40002C06)) /* */
\r
1619 #define UCB3STATW (HWREG16(0x40002C08)) /* eUSCI_Bx Status Register */
\r
1620 #define UCB3STATW_SPI (HWREG16(0x40002C08)) /* */
\r
1621 #define UCB3TBCNT (HWREG16(0x40002C0A)) /* eUSCI_Bx Byte Counter Threshold Register */
\r
1622 #define UCB3RXBUF (HWREG16(0x40002C0C)) /* eUSCI_Bx Receive Buffer Register */
\r
1623 #define UCB3RXBUF_SPI (HWREG16(0x40002C0C)) /* */
\r
1624 #define UCB3TXBUF (HWREG16(0x40002C0E)) /* eUSCI_Bx Transmit Buffer Register */
\r
1625 #define UCB3TXBUF_SPI (HWREG16(0x40002C0E)) /* */
\r
1626 #define UCB3I2COA0 (HWREG16(0x40002C14)) /* eUSCI_Bx I2C Own Address 0 Register */
\r
1627 #define UCB3I2COA1 (HWREG16(0x40002C16)) /* eUSCI_Bx I2C Own Address 1 Register */
\r
1628 #define UCB3I2COA2 (HWREG16(0x40002C18)) /* eUSCI_Bx I2C Own Address 2 Register */
\r
1629 #define UCB3I2COA3 (HWREG16(0x40002C1A)) /* eUSCI_Bx I2C Own Address 3 Register */
\r
1630 #define UCB3ADDRX (HWREG16(0x40002C1C)) /* eUSCI_Bx I2C Received Address Register */
\r
1631 #define UCB3ADDMASK (HWREG16(0x40002C1E)) /* eUSCI_Bx I2C Address Mask Register */
\r
1632 #define UCB3I2CSA (HWREG16(0x40002C20)) /* eUSCI_Bx I2C Slave Address Register */
\r
1633 #define UCB3IE (HWREG16(0x40002C2A)) /* eUSCI_Bx Interrupt Enable Register */
\r
1634 #define UCB3IE_SPI (HWREG16(0x40002C2A)) /* */
\r
1635 #define UCB3IFG (HWREG16(0x40002C2C)) /* eUSCI_Bx Interrupt Flag Register */
\r
1636 #define UCB3IFG_SPI (HWREG16(0x40002C2C)) /* */
\r
1637 #define UCB3IV (HWREG16(0x40002C2E)) /* eUSCI_Bx Interrupt Vector Register */
\r
1638 #define UCB3IV_SPI (HWREG16(0x40002C2E)) /* */
\r
1640 /* Register offsets from EUSCI_B3_BASE address */
\r
1641 #define OFS_UCB3CTLW0 (0x0000) /* eUSCI_Bx Control Word Register 0 */
\r
1642 #define OFS_UCB3CTLW0_SPI (0x0000) /* */
\r
1643 #define OFS_UCB3CTLW1 (0x0002) /* eUSCI_Bx Control Word Register 1 */
\r
1644 #define OFS_UCB3BRW (0x0006) /* eUSCI_Bx Baud Rate Control Word Register */
\r
1645 #define OFS_UCB3BRW_SPI (0x0006) /* */
\r
1646 #define OFS_UCB3STATW (0x0008) /* eUSCI_Bx Status Register */
\r
1647 #define OFS_UCB3STATW_SPI (0x0008) /* */
\r
1648 #define OFS_UCB3TBCNT (0x000a) /* eUSCI_Bx Byte Counter Threshold Register */
\r
1649 #define OFS_UCB3RXBUF (0x000c) /* eUSCI_Bx Receive Buffer Register */
\r
1650 #define OFS_UCB3RXBUF_SPI (0x000c) /* */
\r
1651 #define OFS_UCB3TXBUF (0x000e) /* eUSCI_Bx Transmit Buffer Register */
\r
1652 #define OFS_UCB3TXBUF_SPI (0x000e) /* */
\r
1653 #define OFS_UCB3I2COA0 (0x0014) /* eUSCI_Bx I2C Own Address 0 Register */
\r
1654 #define OFS_UCB3I2COA1 (0x0016) /* eUSCI_Bx I2C Own Address 1 Register */
\r
1655 #define OFS_UCB3I2COA2 (0x0018) /* eUSCI_Bx I2C Own Address 2 Register */
\r
1656 #define OFS_UCB3I2COA3 (0x001a) /* eUSCI_Bx I2C Own Address 3 Register */
\r
1657 #define OFS_UCB3ADDRX (0x001c) /* eUSCI_Bx I2C Received Address Register */
\r
1658 #define OFS_UCB3ADDMASK (0x001e) /* eUSCI_Bx I2C Address Mask Register */
\r
1659 #define OFS_UCB3I2CSA (0x0020) /* eUSCI_Bx I2C Slave Address Register */
\r
1660 #define OFS_UCB3IE (0x002a) /* eUSCI_Bx Interrupt Enable Register */
\r
1661 #define OFS_UCB3IE_SPI (0x002a) /* */
\r
1662 #define OFS_UCB3IFG (0x002c) /* eUSCI_Bx Interrupt Flag Register */
\r
1663 #define OFS_UCB3IFG_SPI (0x002c) /* */
\r
1664 #define OFS_UCB3IV (0x002e) /* eUSCI_Bx Interrupt Vector Register */
\r
1665 #define OFS_UCB3IV_SPI (0x002e) /* */
\r
1667 #define UCB3CTL0 (HWREG8_L(UCB3CTLW0)) /* eUSCI_Bx Control 1 */
\r
1668 #define UCB3CTL1 (HWREG8_H(UCB3CTLW0)) /* eUSCI_Bx Control 0 */
\r
1669 #define UCB3BR0 (HWREG8_L(UCB3BRW)) /* eUSCI_Bx Bit Rate Control 0 */
\r
1670 #define UCB3BR1 (HWREG8_H(UCB3BRW)) /* eUSCI_Bx Bit Rate Control 1 */
\r
1671 #define UCB3STAT (HWREG8_L(UCB3STATW)) /* eUSCI_Bx Status */
\r
1672 #define UCB3BCNT (HWREG8_H(UCB3STATW)) /* eUSCI_Bx Byte Counter Register */
\r
1674 //*****************************************************************************
\r
1675 // FLCTL Registers
\r
1676 //*****************************************************************************
\r
1677 #define FLCTL_POWER_STAT (HWREG32(0x40011000)) /* Power Status Register */
\r
1678 #define FLCTL_BANK0_RDCTL (HWREG32(0x40011010)) /* Bank0 Read Control Register */
\r
1679 #define FLCTL_BANK1_RDCTL (HWREG32(0x40011014)) /* Bank1 Read Control Register */
\r
1680 #define FLCTL_RDBRST_CTLSTAT (HWREG32(0x40011020)) /* Read Burst/Compare Control and Status Register */
\r
1681 #define FLCTL_RDBRST_STARTADDR (HWREG32(0x40011024)) /* Read Burst/Compare Start Address Register */
\r
1682 #define FLCTL_RDBRST_LEN (HWREG32(0x40011028)) /* Read Burst/Compare Length Register */
\r
1683 #define FLCTL_RDBRST_FAILADDR (HWREG32(0x4001103C)) /* Read Burst/Compare Fail Address Register */
\r
1684 #define FLCTL_RDBRST_FAILCNT (HWREG32(0x40011040)) /* Read Burst/Compare Fail Count Register */
\r
1685 #define FLCTL_PRG_CTLSTAT (HWREG32(0x40011050)) /* Program Control and Status Register */
\r
1686 #define FLCTL_PRGBRST_CTLSTAT (HWREG32(0x40011054)) /* Program Burst Control and Status Register */
\r
1687 #define FLCTL_PRGBRST_STARTADDR (HWREG32(0x40011058)) /* Program Burst Start Address Register */
\r
1688 #define FLCTL_PRGBRST_DATA0_0 (HWREG32(0x40011060)) /* Program Burst Data0 Register0 */
\r
1689 #define FLCTL_PRGBRST_DATA0_1 (HWREG32(0x40011064)) /* Program Burst Data0 Register1 */
\r
1690 #define FLCTL_PRGBRST_DATA0_2 (HWREG32(0x40011068)) /* Program Burst Data0 Register2 */
\r
1691 #define FLCTL_PRGBRST_DATA0_3 (HWREG32(0x4001106C)) /* Program Burst Data0 Register3 */
\r
1692 #define FLCTL_PRGBRST_DATA1_0 (HWREG32(0x40011070)) /* Program Burst Data1 Register0 */
\r
1693 #define FLCTL_PRGBRST_DATA1_1 (HWREG32(0x40011074)) /* Program Burst Data1 Register1 */
\r
1694 #define FLCTL_PRGBRST_DATA1_2 (HWREG32(0x40011078)) /* Program Burst Data1 Register2 */
\r
1695 #define FLCTL_PRGBRST_DATA1_3 (HWREG32(0x4001107C)) /* Program Burst Data1 Register3 */
\r
1696 #define FLCTL_PRGBRST_DATA2_0 (HWREG32(0x40011080)) /* Program Burst Data2 Register0 */
\r
1697 #define FLCTL_PRGBRST_DATA2_1 (HWREG32(0x40011084)) /* Program Burst Data2 Register1 */
\r
1698 #define FLCTL_PRGBRST_DATA2_2 (HWREG32(0x40011088)) /* Program Burst Data2 Register2 */
\r
1699 #define FLCTL_PRGBRST_DATA2_3 (HWREG32(0x4001108C)) /* Program Burst Data2 Register3 */
\r
1700 #define FLCTL_PRGBRST_DATA3_0 (HWREG32(0x40011090)) /* Program Burst Data3 Register0 */
\r
1701 #define FLCTL_PRGBRST_DATA3_1 (HWREG32(0x40011094)) /* Program Burst Data3 Register1 */
\r
1702 #define FLCTL_PRGBRST_DATA3_2 (HWREG32(0x40011098)) /* Program Burst Data3 Register2 */
\r
1703 #define FLCTL_PRGBRST_DATA3_3 (HWREG32(0x4001109C)) /* Program Burst Data3 Register3 */
\r
1704 #define FLCTL_ERASE_CTLSTAT (HWREG32(0x400110A0)) /* Erase Control and Status Register */
\r
1705 #define FLCTL_ERASE_SECTADDR (HWREG32(0x400110A4)) /* Erase Sector Address Register */
\r
1706 #define FLCTL_BANK0_INFO_WEPROT (HWREG32(0x400110B0)) /* Information Memory Bank0 Write/Erase Protection Register */
\r
1707 #define FLCTL_BANK0_MAIN_WEPROT (HWREG32(0x400110B4)) /* Main Memory Bank0 Write/Erase Protection Register */
\r
1708 #define FLCTL_BANK1_INFO_WEPROT (HWREG32(0x400110C0)) /* Information Memory Bank1 Write/Erase Protection Register */
\r
1709 #define FLCTL_BANK1_MAIN_WEPROT (HWREG32(0x400110C4)) /* Main Memory Bank1 Write/Erase Protection Register */
\r
1710 #define FLCTL_BMRK_CTLSTAT (HWREG32(0x400110D0)) /* Benchmark Control and Status Register */
\r
1711 #define FLCTL_BMRK_IFETCH (HWREG32(0x400110D4)) /* Benchmark Instruction Fetch Count Register */
\r
1712 #define FLCTL_BMRK_DREAD (HWREG32(0x400110D8)) /* Benchmark Data Read Count Register */
\r
1713 #define FLCTL_BMRK_CMP (HWREG32(0x400110DC)) /* Benchmark Count Compare Register */
\r
1714 #define FLCTL_IFG (HWREG32(0x400110F0)) /* Interrupt Flag Register */
\r
1715 #define FLCTL_IE (HWREG32(0x400110F4)) /* Interrupt Enable Register */
\r
1716 #define FLCTL_CLRIFG (HWREG32(0x400110F8)) /* Clear Interrupt Flag Register */
\r
1717 #define FLCTL_SETIFG (HWREG32(0x400110FC)) /* Set Interrupt Flag Register */
\r
1718 #define FLCTL_READ_TIMCTL (HWREG32(0x40011100)) /* Read Timing Control Register */
\r
1719 #define FLCTL_READMARGIN_TIMCTL (HWREG32(0x40011104)) /* Read Margin Timing Control Register */
\r
1720 #define FLCTL_PRGVER_TIMCTL (HWREG32(0x40011108)) /* Program Verify Timing Control Register */
\r
1721 #define FLCTL_ERSVER_TIMCTL (HWREG32(0x4001110C)) /* Erase Verify Timing Control Register */
\r
1722 #define FLCTL_LKGVER_TIMCTL (HWREG32(0x40011110)) /* Leakage Verify Timing Control Register */
\r
1723 #define FLCTL_PROGRAM_TIMCTL (HWREG32(0x40011114)) /* Program Timing Control Register */
\r
1724 #define FLCTL_ERASE_TIMCTL (HWREG32(0x40011118)) /* Erase Timing Control Register */
\r
1725 #define FLCTL_MASSERASE_TIMCTL (HWREG32(0x4001111C)) /* Mass Erase Timing Control Register */
\r
1726 #define FLCTL_BURSTPRG_TIMCTL (HWREG32(0x40011120)) /* Burst Program Timing Control Register */
\r
1728 /* Register offsets from FLCTL_BASE address */
\r
1729 #define OFS_FLCTL_POWER_STAT (0x00000000) /* Power Status Register */
\r
1730 #define OFS_FLCTL_BANK0_RDCTL (0x00000010) /* Bank0 Read Control Register */
\r
1731 #define OFS_FLCTL_BANK1_RDCTL (0x00000014) /* Bank1 Read Control Register */
\r
1732 #define OFS_FLCTL_RDBRST_CTLSTAT (0x00000020) /* Read Burst/Compare Control and Status Register */
\r
1733 #define OFS_FLCTL_RDBRST_STARTADDR (0x00000024) /* Read Burst/Compare Start Address Register */
\r
1734 #define OFS_FLCTL_RDBRST_LEN (0x00000028) /* Read Burst/Compare Length Register */
\r
1735 #define OFS_FLCTL_RDBRST_FAILADDR (0x0000003C) /* Read Burst/Compare Fail Address Register */
\r
1736 #define OFS_FLCTL_RDBRST_FAILCNT (0x00000040) /* Read Burst/Compare Fail Count Register */
\r
1737 #define OFS_FLCTL_PRG_CTLSTAT (0x00000050) /* Program Control and Status Register */
\r
1738 #define OFS_FLCTL_PRGBRST_CTLSTAT (0x00000054) /* Program Burst Control and Status Register */
\r
1739 #define OFS_FLCTL_PRGBRST_STARTADDR (0x00000058) /* Program Burst Start Address Register */
\r
1740 #define OFS_FLCTL_PRGBRST_DATA0_0 (0x00000060) /* Program Burst Data0 Register0 */
\r
1741 #define OFS_FLCTL_PRGBRST_DATA0_1 (0x00000064) /* Program Burst Data0 Register1 */
\r
1742 #define OFS_FLCTL_PRGBRST_DATA0_2 (0x00000068) /* Program Burst Data0 Register2 */
\r
1743 #define OFS_FLCTL_PRGBRST_DATA0_3 (0x0000006C) /* Program Burst Data0 Register3 */
\r
1744 #define OFS_FLCTL_PRGBRST_DATA1_0 (0x00000070) /* Program Burst Data1 Register0 */
\r
1745 #define OFS_FLCTL_PRGBRST_DATA1_1 (0x00000074) /* Program Burst Data1 Register1 */
\r
1746 #define OFS_FLCTL_PRGBRST_DATA1_2 (0x00000078) /* Program Burst Data1 Register2 */
\r
1747 #define OFS_FLCTL_PRGBRST_DATA1_3 (0x0000007C) /* Program Burst Data1 Register3 */
\r
1748 #define OFS_FLCTL_PRGBRST_DATA2_0 (0x00000080) /* Program Burst Data2 Register0 */
\r
1749 #define OFS_FLCTL_PRGBRST_DATA2_1 (0x00000084) /* Program Burst Data2 Register1 */
\r
1750 #define OFS_FLCTL_PRGBRST_DATA2_2 (0x00000088) /* Program Burst Data2 Register2 */
\r
1751 #define OFS_FLCTL_PRGBRST_DATA2_3 (0x0000008C) /* Program Burst Data2 Register3 */
\r
1752 #define OFS_FLCTL_PRGBRST_DATA3_0 (0x00000090) /* Program Burst Data3 Register0 */
\r
1753 #define OFS_FLCTL_PRGBRST_DATA3_1 (0x00000094) /* Program Burst Data3 Register1 */
\r
1754 #define OFS_FLCTL_PRGBRST_DATA3_2 (0x00000098) /* Program Burst Data3 Register2 */
\r
1755 #define OFS_FLCTL_PRGBRST_DATA3_3 (0x0000009C) /* Program Burst Data3 Register3 */
\r
1756 #define OFS_FLCTL_ERASE_CTLSTAT (0x000000A0) /* Erase Control and Status Register */
\r
1757 #define OFS_FLCTL_ERASE_SECTADDR (0x000000A4) /* Erase Sector Address Register */
\r
1758 #define OFS_FLCTL_BANK0_INFO_WEPROT (0x000000B0) /* Information Memory Bank0 Write/Erase Protection Register */
\r
1759 #define OFS_FLCTL_BANK0_MAIN_WEPROT (0x000000B4) /* Main Memory Bank0 Write/Erase Protection Register */
\r
1760 #define OFS_FLCTL_BANK1_INFO_WEPROT (0x000000C0) /* Information Memory Bank1 Write/Erase Protection Register */
\r
1761 #define OFS_FLCTL_BANK1_MAIN_WEPROT (0x000000C4) /* Main Memory Bank1 Write/Erase Protection Register */
\r
1762 #define OFS_FLCTL_BMRK_CTLSTAT (0x000000D0) /* Benchmark Control and Status Register */
\r
1763 #define OFS_FLCTL_BMRK_IFETCH (0x000000D4) /* Benchmark Instruction Fetch Count Register */
\r
1764 #define OFS_FLCTL_BMRK_DREAD (0x000000D8) /* Benchmark Data Read Count Register */
\r
1765 #define OFS_FLCTL_BMRK_CMP (0x000000DC) /* Benchmark Count Compare Register */
\r
1766 #define OFS_FLCTL_IFG (0x000000F0) /* Interrupt Flag Register */
\r
1767 #define OFS_FLCTL_IE (0x000000F4) /* Interrupt Enable Register */
\r
1768 #define OFS_FLCTL_CLRIFG (0x000000F8) /* Clear Interrupt Flag Register */
\r
1769 #define OFS_FLCTL_SETIFG (0x000000FC) /* Set Interrupt Flag Register */
\r
1770 #define OFS_FLCTL_READ_TIMCTL (0x00000100) /* Read Timing Control Register */
\r
1771 #define OFS_FLCTL_READMARGIN_TIMCTL (0x00000104) /* Read Margin Timing Control Register */
\r
1772 #define OFS_FLCTL_PRGVER_TIMCTL (0x00000108) /* Program Verify Timing Control Register */
\r
1773 #define OFS_FLCTL_ERSVER_TIMCTL (0x0000010C) /* Erase Verify Timing Control Register */
\r
1774 #define OFS_FLCTL_LKGVER_TIMCTL (0x00000110) /* Leakage Verify Timing Control Register */
\r
1775 #define OFS_FLCTL_PROGRAM_TIMCTL (0x00000114) /* Program Timing Control Register */
\r
1776 #define OFS_FLCTL_ERASE_TIMCTL (0x00000118) /* Erase Timing Control Register */
\r
1777 #define OFS_FLCTL_MASSERASE_TIMCTL (0x0000011C) /* Mass Erase Timing Control Register */
\r
1778 #define OFS_FLCTL_BURSTPRG_TIMCTL (0x00000120) /* Burst Program Timing Control Register */
\r
1781 //*****************************************************************************
\r
1783 //*****************************************************************************
\r
1784 #define FPB_FP_CTRL (HWREG32(0xE0002000)) /* Flash Patch Control Register */
\r
1785 #define FPB_FP_REMAP (HWREG32(0xE0002004)) /* Flash Patch Remap Register */
\r
1786 #define FPB_FP_COMP0 (HWREG32(0xE0002008)) /* Flash Patch Comparator Registers */
\r
1787 #define FPB_FP_COMP1 (HWREG32(0xE000200C)) /* Flash Patch Comparator Registers */
\r
1788 #define FPB_FP_COMP2 (HWREG32(0xE0002010)) /* Flash Patch Comparator Registers */
\r
1789 #define FPB_FP_COMP3 (HWREG32(0xE0002014)) /* Flash Patch Comparator Registers */
\r
1790 #define FPB_FP_COMP4 (HWREG32(0xE0002018)) /* Flash Patch Comparator Registers */
\r
1791 #define FPB_FP_COMP5 (HWREG32(0xE000201C)) /* Flash Patch Comparator Registers */
\r
1792 #define FPB_FP_COMP6 (HWREG32(0xE0002020)) /* Flash Patch Comparator Registers */
\r
1793 #define FPB_FP_COMP7 (HWREG32(0xE0002024)) /* Flash Patch Comparator Registers */
\r
1795 /* Register offsets from FPB_BASE address */
\r
1796 #define OFS_FPB_FP_CTRL (0x00000000) /* Flash Patch Control Register */
\r
1797 #define OFS_FPB_FP_REMAP (0x00000004) /* Flash Patch Remap Register */
\r
1798 #define OFS_FPB_FP_COMP0 (0x00000008) /* Flash Patch Comparator Registers */
\r
1799 #define OFS_FPB_FP_COMP1 (0x0000000C) /* Flash Patch Comparator Registers */
\r
1800 #define OFS_FPB_FP_COMP2 (0x00000010) /* Flash Patch Comparator Registers */
\r
1801 #define OFS_FPB_FP_COMP3 (0x00000014) /* Flash Patch Comparator Registers */
\r
1802 #define OFS_FPB_FP_COMP4 (0x00000018) /* Flash Patch Comparator Registers */
\r
1803 #define OFS_FPB_FP_COMP5 (0x0000001C) /* Flash Patch Comparator Registers */
\r
1804 #define OFS_FPB_FP_COMP6 (0x00000020) /* Flash Patch Comparator Registers */
\r
1805 #define OFS_FPB_FP_COMP7 (0x00000024) /* Flash Patch Comparator Registers */
\r
1808 //*****************************************************************************
\r
1810 //*****************************************************************************
\r
1811 #define FPU_FPCCR (HWREG32(0xE000EF34)) /* Floating Point Context Control Register */
\r
1812 #define FPU_FPCAR (HWREG32(0xE000EF38)) /* Floating-Point Context Address Register */
\r
1813 #define FPU_FPDSCR (HWREG32(0xE000EF3C)) /* Floating Point Default Status Control Register */
\r
1814 #define FPU_MVFR0 (HWREG32(0xE000EF40)) /* Media and FP Feature Register 0 (MVFR0) */
\r
1815 #define FPU_MVFR1 (HWREG32(0xE000EF44)) /* Media and FP Feature Register 1 (MVFR1) */
\r
1817 /* Register offsets from FPU_BASE address */
\r
1818 #define OFS_FPU_FPCCR (0x00000F34) /* Floating Point Context Control Register */
\r
1819 #define OFS_FPU_FPCAR (0x00000F38) /* Floating-Point Context Address Register */
\r
1820 #define OFS_FPU_FPDSCR (0x00000F3C) /* Floating Point Default Status Control Register */
\r
1821 #define OFS_FPU_MVFR0 (0x00000F40) /* Media and FP Feature Register 0 (MVFR0) */
\r
1822 #define OFS_FPU_MVFR1 (0x00000F44) /* Media and FP Feature Register 1 (MVFR1) */
\r
1825 //*****************************************************************************
\r
1827 //*****************************************************************************
\r
1828 #define ITM_STIM0 (HWREG32(0xE0000000)) /* ITM Stimulus Port 0 */
\r
1829 #define ITM_STIM1 (HWREG32(0xE0000004)) /* ITM Stimulus Port 1 */
\r
1830 #define ITM_STIM2 (HWREG32(0xE0000008)) /* ITM Stimulus Port 2 */
\r
1831 #define ITM_STIM3 (HWREG32(0xE000000C)) /* ITM Stimulus Port 3 */
\r
1832 #define ITM_STIM4 (HWREG32(0xE0000010)) /* ITM Stimulus Port 4 */
\r
1833 #define ITM_STIM5 (HWREG32(0xE0000014)) /* ITM Stimulus Port 5 */
\r
1834 #define ITM_STIM6 (HWREG32(0xE0000018)) /* ITM Stimulus Port 6 */
\r
1835 #define ITM_STIM7 (HWREG32(0xE000001C)) /* ITM Stimulus Port 7 */
\r
1836 #define ITM_STIM8 (HWREG32(0xE0000020)) /* ITM Stimulus Port 8 */
\r
1837 #define ITM_STIM9 (HWREG32(0xE0000024)) /* ITM Stimulus Port 9 */
\r
1838 #define ITM_STIM10 (HWREG32(0xE0000028)) /* ITM Stimulus Port 10 */
\r
1839 #define ITM_STIM11 (HWREG32(0xE000002C)) /* ITM Stimulus Port 11 */
\r
1840 #define ITM_STIM12 (HWREG32(0xE0000030)) /* ITM Stimulus Port 12 */
\r
1841 #define ITM_STIM13 (HWREG32(0xE0000034)) /* ITM Stimulus Port 13 */
\r
1842 #define ITM_STIM14 (HWREG32(0xE0000038)) /* ITM Stimulus Port 14 */
\r
1843 #define ITM_STIM15 (HWREG32(0xE000003C)) /* ITM Stimulus Port 15 */
\r
1844 #define ITM_STIM16 (HWREG32(0xE0000040)) /* ITM Stimulus Port 16 */
\r
1845 #define ITM_STIM17 (HWREG32(0xE0000044)) /* ITM Stimulus Port 17 */
\r
1846 #define ITM_STIM18 (HWREG32(0xE0000048)) /* ITM Stimulus Port 18 */
\r
1847 #define ITM_STIM19 (HWREG32(0xE000004C)) /* ITM Stimulus Port 19 */
\r
1848 #define ITM_STIM20 (HWREG32(0xE0000050)) /* ITM Stimulus Port 20 */
\r
1849 #define ITM_STIM21 (HWREG32(0xE0000054)) /* ITM Stimulus Port 21 */
\r
1850 #define ITM_STIM22 (HWREG32(0xE0000058)) /* ITM Stimulus Port 22 */
\r
1851 #define ITM_STIM23 (HWREG32(0xE000005C)) /* ITM Stimulus Port 23 */
\r
1852 #define ITM_STIM24 (HWREG32(0xE0000060)) /* ITM Stimulus Port 24 */
\r
1853 #define ITM_STIM25 (HWREG32(0xE0000064)) /* ITM Stimulus Port 25 */
\r
1854 #define ITM_STIM26 (HWREG32(0xE0000068)) /* ITM Stimulus Port 26 */
\r
1855 #define ITM_STIM27 (HWREG32(0xE000006C)) /* ITM Stimulus Port 27 */
\r
1856 #define ITM_STIM28 (HWREG32(0xE0000070)) /* ITM Stimulus Port 28 */
\r
1857 #define ITM_STIM29 (HWREG32(0xE0000074)) /* ITM Stimulus Port 29 */
\r
1858 #define ITM_STIM30 (HWREG32(0xE0000078)) /* ITM Stimulus Port 30 */
\r
1859 #define ITM_STIM31 (HWREG32(0xE000007C)) /* ITM Stimulus Port 31 */
\r
1860 #define ITM_TER (HWREG32(0xE0000E00)) /* ITM Trace Enable Register */
\r
1861 #define ITM_TPR (HWREG32(0xE0000E40)) /* ITM Trace Privilege Register */
\r
1862 #define ITM_TCR (HWREG32(0xE0000E80)) /* ITM Trace Control Register */
\r
1863 #define ITM_IWR (HWREG32(0xE0000EF8)) /* ITM Integration Write Register */
\r
1864 #define ITM_IMCR (HWREG32(0xE0000F00)) /* ITM Integration Mode Control Register */
\r
1865 #define ITM_LAR (HWREG32(0xE0000FB0)) /* ITM Lock Access Register */
\r
1866 #define ITM_LSR (HWREG32(0xE0000FB4)) /* ITM Lock Status Register */
\r
1868 /* Register offsets from ITM_BASE address */
\r
1869 #define OFS_ITM_STIM0 (0x00000000) /* ITM Stimulus Port 0 */
\r
1870 #define OFS_ITM_STIM1 (0x00000004) /* ITM Stimulus Port 1 */
\r
1871 #define OFS_ITM_STIM2 (0x00000008) /* ITM Stimulus Port 2 */
\r
1872 #define OFS_ITM_STIM3 (0x0000000C) /* ITM Stimulus Port 3 */
\r
1873 #define OFS_ITM_STIM4 (0x00000010) /* ITM Stimulus Port 4 */
\r
1874 #define OFS_ITM_STIM5 (0x00000014) /* ITM Stimulus Port 5 */
\r
1875 #define OFS_ITM_STIM6 (0x00000018) /* ITM Stimulus Port 6 */
\r
1876 #define OFS_ITM_STIM7 (0x0000001C) /* ITM Stimulus Port 7 */
\r
1877 #define OFS_ITM_STIM8 (0x00000020) /* ITM Stimulus Port 8 */
\r
1878 #define OFS_ITM_STIM9 (0x00000024) /* ITM Stimulus Port 9 */
\r
1879 #define OFS_ITM_STIM10 (0x00000028) /* ITM Stimulus Port 10 */
\r
1880 #define OFS_ITM_STIM11 (0x0000002C) /* ITM Stimulus Port 11 */
\r
1881 #define OFS_ITM_STIM12 (0x00000030) /* ITM Stimulus Port 12 */
\r
1882 #define OFS_ITM_STIM13 (0x00000034) /* ITM Stimulus Port 13 */
\r
1883 #define OFS_ITM_STIM14 (0x00000038) /* ITM Stimulus Port 14 */
\r
1884 #define OFS_ITM_STIM15 (0x0000003C) /* ITM Stimulus Port 15 */
\r
1885 #define OFS_ITM_STIM16 (0x00000040) /* ITM Stimulus Port 16 */
\r
1886 #define OFS_ITM_STIM17 (0x00000044) /* ITM Stimulus Port 17 */
\r
1887 #define OFS_ITM_STIM18 (0x00000048) /* ITM Stimulus Port 18 */
\r
1888 #define OFS_ITM_STIM19 (0x0000004C) /* ITM Stimulus Port 19 */
\r
1889 #define OFS_ITM_STIM20 (0x00000050) /* ITM Stimulus Port 20 */
\r
1890 #define OFS_ITM_STIM21 (0x00000054) /* ITM Stimulus Port 21 */
\r
1891 #define OFS_ITM_STIM22 (0x00000058) /* ITM Stimulus Port 22 */
\r
1892 #define OFS_ITM_STIM23 (0x0000005C) /* ITM Stimulus Port 23 */
\r
1893 #define OFS_ITM_STIM24 (0x00000060) /* ITM Stimulus Port 24 */
\r
1894 #define OFS_ITM_STIM25 (0x00000064) /* ITM Stimulus Port 25 */
\r
1895 #define OFS_ITM_STIM26 (0x00000068) /* ITM Stimulus Port 26 */
\r
1896 #define OFS_ITM_STIM27 (0x0000006C) /* ITM Stimulus Port 27 */
\r
1897 #define OFS_ITM_STIM28 (0x00000070) /* ITM Stimulus Port 28 */
\r
1898 #define OFS_ITM_STIM29 (0x00000074) /* ITM Stimulus Port 29 */
\r
1899 #define OFS_ITM_STIM30 (0x00000078) /* ITM Stimulus Port 30 */
\r
1900 #define OFS_ITM_STIM31 (0x0000007C) /* ITM Stimulus Port 31 */
\r
1901 #define OFS_ITM_TER (0x00000E00) /* ITM Trace Enable Register */
\r
1902 #define OFS_ITM_TPR (0x00000E40) /* ITM Trace Privilege Register */
\r
1903 #define OFS_ITM_TCR (0x00000E80) /* ITM Trace Control Register */
\r
1904 #define OFS_ITM_IWR (0x00000EF8) /* ITM Integration Write Register */
\r
1905 #define OFS_ITM_IMCR (0x00000F00) /* ITM Integration Mode Control Register */
\r
1906 #define OFS_ITM_LAR (0x00000FB0) /* ITM Lock Access Register */
\r
1907 #define OFS_ITM_LSR (0x00000FB4) /* ITM Lock Status Register */
\r
1910 //*****************************************************************************
\r
1912 //*****************************************************************************
\r
1913 #define MPU_TYPE (HWREG32(0xE000ED90)) /* MPU Type Register */
\r
1914 #define MPU_CTRL (HWREG32(0xE000ED94)) /* MPU Control Register */
\r
1915 #define MPU_RNR (HWREG32(0xE000ED98)) /* MPU Region Number Register */
\r
1916 #define MPU_RBAR (HWREG32(0xE000ED9C)) /* MPU Region Base Address Register */
\r
1917 #define MPU_RASR (HWREG32(0xE000EDA0)) /* MPU Region Attribute and Size Register */
\r
1918 #define MPU_RBAR_A1 (HWREG32(0xE000EDA4)) /* MPU Alias 1 Region Base Address register */
\r
1919 #define MPU_RASR_A1 (HWREG32(0xE000EDA8)) /* MPU Alias 1 Region Attribute and Size register */
\r
1920 #define MPU_RBAR_A2 (HWREG32(0xE000EDAC)) /* MPU Alias 2 Region Base Address register */
\r
1921 #define MPU_RASR_A2 (HWREG32(0xE000EDB0)) /* MPU Alias 2 Region Attribute and Size register */
\r
1922 #define MPU_RBAR_A3 (HWREG32(0xE000EDB4)) /* MPU Alias 3 Region Base Address register */
\r
1923 #define MPU_RASR_A3 (HWREG32(0xE000EDB8)) /* MPU Alias 3 Region Attribute and Size register */
\r
1925 /* Register offsets from MPU_BASE address */
\r
1926 #define OFS_MPU_TYPE (0x00000D90) /* MPU Type Register */
\r
1927 #define OFS_MPU_CTRL (0x00000D94) /* MPU Control Register */
\r
1928 #define OFS_MPU_RNR (0x00000D98) /* MPU Region Number Register */
\r
1929 #define OFS_MPU_RBAR (0x00000D9C) /* MPU Region Base Address Register */
\r
1930 #define OFS_MPU_RASR (0x00000DA0) /* MPU Region Attribute and Size Register */
\r
1931 #define OFS_MPU_RBAR_A1 (0x00000DA4) /* MPU Alias 1 Region Base Address register */
\r
1932 #define OFS_MPU_RASR_A1 (0x00000DA8) /* MPU Alias 1 Region Attribute and Size register */
\r
1933 #define OFS_MPU_RBAR_A2 (0x00000DAC) /* MPU Alias 2 Region Base Address register */
\r
1934 #define OFS_MPU_RASR_A2 (0x00000DB0) /* MPU Alias 2 Region Attribute and Size register */
\r
1935 #define OFS_MPU_RBAR_A3 (0x00000DB4) /* MPU Alias 3 Region Base Address register */
\r
1936 #define OFS_MPU_RASR_A3 (0x00000DB8) /* MPU Alias 3 Region Attribute and Size register */
\r
1939 //*****************************************************************************
\r
1941 //*****************************************************************************
\r
1942 #define NVIC_ISER0 (HWREG32(0xE000E100)) /* Irq 0 to 31 Set Enable Register */
\r
1943 #define NVIC_ISER1 (HWREG32(0xE000E104)) /* Irq 32 to 63 Set Enable Register */
\r
1944 #define NVIC_ICER0 (HWREG32(0xE000E180)) /* Irq 0 to 31 Clear Enable Register */
\r
1945 #define NVIC_ICER1 (HWREG32(0xE000E184)) /* Irq 32 to 63 Clear Enable Register */
\r
1946 #define NVIC_ISPR0 (HWREG32(0xE000E200)) /* Irq 0 to 31 Set Pending Register */
\r
1947 #define NVIC_ISPR1 (HWREG32(0xE000E204)) /* Irq 32 to 63 Set Pending Register */
\r
1948 #define NVIC_ICPR0 (HWREG32(0xE000E280)) /* Irq 0 to 31 Clear Pending Register */
\r
1949 #define NVIC_ICPR1 (HWREG32(0xE000E284)) /* Irq 32 to 63 Clear Pending Register */
\r
1950 #define NVIC_IABR0 (HWREG32(0xE000E300)) /* Irq 0 to 31 Active Bit Register */
\r
1951 #define NVIC_IABR1 (HWREG32(0xE000E304)) /* Irq 32 to 63 Active Bit Register */
\r
1952 #define NVIC_IPR0 (HWREG32(0xE000E400)) /* Irq 0 to 3 Priority Register */
\r
1953 #define NVIC_IPR1 (HWREG32(0xE000E404)) /* Irq 4 to 7 Priority Register */
\r
1954 #define NVIC_IPR2 (HWREG32(0xE000E408)) /* Irq 8 to 11 Priority Register */
\r
1955 #define NVIC_IPR3 (HWREG32(0xE000E40C)) /* Irq 12 to 15 Priority Register */
\r
1956 #define NVIC_IPR4 (HWREG32(0xE000E410)) /* Irq 16 to 19 Priority Register */
\r
1957 #define NVIC_IPR5 (HWREG32(0xE000E414)) /* Irq 20 to 23 Priority Register */
\r
1958 #define NVIC_IPR6 (HWREG32(0xE000E418)) /* Irq 24 to 27 Priority Register */
\r
1959 #define NVIC_IPR7 (HWREG32(0xE000E41C)) /* Irq 28 to 31 Priority Register */
\r
1960 #define NVIC_IPR8 (HWREG32(0xE000E420)) /* Irq 32 to 35 Priority Register */
\r
1961 #define NVIC_IPR9 (HWREG32(0xE000E424)) /* Irq 36 to 39 Priority Register */
\r
1962 #define NVIC_IPR10 (HWREG32(0xE000E428)) /* Irq 40 to 43 Priority Register */
\r
1963 #define NVIC_IPR11 (HWREG32(0xE000E42C)) /* Irq 44 to 47 Priority Register */
\r
1964 #define NVIC_IPR12 (HWREG32(0xE000E430)) /* Irq 48 to 51 Priority Register */
\r
1965 #define NVIC_IPR13 (HWREG32(0xE000E434)) /* Irq 52 to 55 Priority Register */
\r
1966 #define NVIC_IPR14 (HWREG32(0xE000E438)) /* Irq 56 to 59 Priority Register */
\r
1967 #define NVIC_IPR15 (HWREG32(0xE000E43C)) /* Irq 60 to 63 Priority Register */
\r
1968 #define NVIC_STIR (HWREG32(0xE000EF00)) /* Software Trigger Interrupt Register */
\r
1970 /* Register offsets from NVIC_BASE address */
\r
1971 #define OFS_NVIC_ISER0 (0x00000100) /* Irq 0 to 31 Set Enable Register */
\r
1972 #define OFS_NVIC_ISER1 (0x00000104) /* Irq 32 to 63 Set Enable Register */
\r
1973 #define OFS_NVIC_ICER0 (0x00000180) /* Irq 0 to 31 Clear Enable Register */
\r
1974 #define OFS_NVIC_ICER1 (0x00000184) /* Irq 32 to 63 Clear Enable Register */
\r
1975 #define OFS_NVIC_ISPR0 (0x00000200) /* Irq 0 to 31 Set Pending Register */
\r
1976 #define OFS_NVIC_ISPR1 (0x00000204) /* Irq 32 to 63 Set Pending Register */
\r
1977 #define OFS_NVIC_ICPR0 (0x00000280) /* Irq 0 to 31 Clear Pending Register */
\r
1978 #define OFS_NVIC_ICPR1 (0x00000284) /* Irq 32 to 63 Clear Pending Register */
\r
1979 #define OFS_NVIC_IABR0 (0x00000300) /* Irq 0 to 31 Active Bit Register */
\r
1980 #define OFS_NVIC_IABR1 (0x00000304) /* Irq 32 to 63 Active Bit Register */
\r
1981 #define OFS_NVIC_IPR0 (0x00000400) /* Irq 0 to 3 Priority Register */
\r
1982 #define OFS_NVIC_IPR1 (0x00000404) /* Irq 4 to 7 Priority Register */
\r
1983 #define OFS_NVIC_IPR2 (0x00000408) /* Irq 8 to 11 Priority Register */
\r
1984 #define OFS_NVIC_IPR3 (0x0000040C) /* Irq 12 to 15 Priority Register */
\r
1985 #define OFS_NVIC_IPR4 (0x00000410) /* Irq 16 to 19 Priority Register */
\r
1986 #define OFS_NVIC_IPR5 (0x00000414) /* Irq 20 to 23 Priority Register */
\r
1987 #define OFS_NVIC_IPR6 (0x00000418) /* Irq 24 to 27 Priority Register */
\r
1988 #define OFS_NVIC_IPR7 (0x0000041C) /* Irq 28 to 31 Priority Register */
\r
1989 #define OFS_NVIC_IPR8 (0x00000420) /* Irq 32 to 35 Priority Register */
\r
1990 #define OFS_NVIC_IPR9 (0x00000424) /* Irq 36 to 39 Priority Register */
\r
1991 #define OFS_NVIC_IPR10 (0x00000428) /* Irq 40 to 43 Priority Register */
\r
1992 #define OFS_NVIC_IPR11 (0x0000042C) /* Irq 44 to 47 Priority Register */
\r
1993 #define OFS_NVIC_IPR12 (0x00000430) /* Irq 48 to 51 Priority Register */
\r
1994 #define OFS_NVIC_IPR13 (0x00000434) /* Irq 52 to 55 Priority Register */
\r
1995 #define OFS_NVIC_IPR14 (0x00000438) /* Irq 56 to 59 Priority Register */
\r
1996 #define OFS_NVIC_IPR15 (0x0000043C) /* Irq 60 to 63 Priority Register */
\r
1997 #define OFS_NVIC_STIR (0x00000F00) /* Software Trigger Interrupt Register */
\r
2000 //*****************************************************************************
\r
2002 //*****************************************************************************
\r
2003 #define PCMCTL0 (HWREG32(0x40010000)) /* Control 0 Register */
\r
2004 #define PCMCTL1 (HWREG32(0x40010004)) /* Control 1 Register */
\r
2005 #define PCMIE (HWREG32(0x40010008)) /* Interrupt Enable Register */
\r
2006 #define PCMIFG (HWREG32(0x4001000C)) /* Interrupt Flag Register */
\r
2007 #define PCMCLRIFG (HWREG32(0x40010010)) /* Clear Interrupt Flag Register */
\r
2009 /* Register offsets from PCM_BASE address */
\r
2010 #define OFS_PCMCTL0 (0x00000000) /* Control 0 Register */
\r
2011 #define OFS_PCMCTL1 (0x00000004) /* Control 1 Register */
\r
2012 #define OFS_PCMIE (0x00000008) /* Interrupt Enable Register */
\r
2013 #define OFS_PCMIFG (0x0000000c) /* Interrupt Flag Register */
\r
2014 #define OFS_PCMCLRIFG (0x00000010) /* Clear Interrupt Flag Register */
\r
2017 //*****************************************************************************
\r
2019 //*****************************************************************************
\r
2020 #define PMAPKEYID (HWREG16(0x40005000)) /* Port Mapping Key Register */
\r
2021 #define PMAPCTL (HWREG16(0x40005002)) /* Port Mapping Control Register */
\r
2022 #define P1MAP01 (HWREG16(0x40005008)) /* Port mapping register, P1.0 and P1.1 */
\r
2023 #define P1MAP23 (HWREG16(0x4000500A)) /* Port mapping register, P1.2 and P1.3 */
\r
2024 #define P1MAP45 (HWREG16(0x4000500C)) /* Port mapping register, P1.4 and P1.5 */
\r
2025 #define P1MAP67 (HWREG16(0x4000500E)) /* Port mapping register, P1.6 and P1.7 */
\r
2026 #define P2MAP01 (HWREG16(0x40005010)) /* Port mapping register, P2.0 and P2.1 */
\r
2027 #define P2MAP23 (HWREG16(0x40005012)) /* Port mapping register, P2.2 and P2.3 */
\r
2028 #define P2MAP45 (HWREG16(0x40005014)) /* Port mapping register, P2.4 and P2.5 */
\r
2029 #define P2MAP67 (HWREG16(0x40005016)) /* Port mapping register, P2.6 and P2.7 */
\r
2030 #define P3MAP01 (HWREG16(0x40005018)) /* Port mapping register, P3.0 and P3.1 */
\r
2031 #define P3MAP23 (HWREG16(0x4000501A)) /* Port mapping register, P3.2 and P3.3 */
\r
2032 #define P3MAP45 (HWREG16(0x4000501C)) /* Port mapping register, P3.4 and P3.5 */
\r
2033 #define P3MAP67 (HWREG16(0x4000501E)) /* Port mapping register, P3.6 and P3.7 */
\r
2034 #define P4MAP01 (HWREG16(0x40005020)) /* Port mapping register, P4.0 and P4.1 */
\r
2035 #define P4MAP23 (HWREG16(0x40005022)) /* Port mapping register, P4.2 and P4.3 */
\r
2036 #define P4MAP45 (HWREG16(0x40005024)) /* Port mapping register, P4.4 and P4.5 */
\r
2037 #define P4MAP67 (HWREG16(0x40005026)) /* Port mapping register, P4.6 and P4.7 */
\r
2038 #define P5MAP01 (HWREG16(0x40005028)) /* Port mapping register, P5.0 and P5.1 */
\r
2039 #define P5MAP23 (HWREG16(0x4000502A)) /* Port mapping register, P5.2 and P5.3 */
\r
2040 #define P5MAP45 (HWREG16(0x4000502C)) /* Port mapping register, P5.4 and P5.5 */
\r
2041 #define P5MAP67 (HWREG16(0x4000502E)) /* Port mapping register, P5.6 and P5.7 */
\r
2042 #define P6MAP01 (HWREG16(0x40005030)) /* Port mapping register, P6.0 and P6.1 */
\r
2043 #define P6MAP23 (HWREG16(0x40005032)) /* Port mapping register, P6.2 and P6.3 */
\r
2044 #define P6MAP45 (HWREG16(0x40005034)) /* Port mapping register, P6.4 and P6.5 */
\r
2045 #define P6MAP67 (HWREG16(0x40005036)) /* Port mapping register, P6.6 and P6.7 */
\r
2046 #define P7MAP01 (HWREG16(0x40005038)) /* Port mapping register, P7.0 and P7.1 */
\r
2047 #define P7MAP23 (HWREG16(0x4000503A)) /* Port mapping register, P7.2 and P7.3 */
\r
2048 #define P7MAP45 (HWREG16(0x4000503C)) /* Port mapping register, P7.4 and P7.5 */
\r
2049 #define P7MAP67 (HWREG16(0x4000503E)) /* Port mapping register, P7.6 and P7.7 */
\r
2051 /* Register offsets from PMAP_BASE address */
\r
2052 #define OFS_PMAPKEYID (0x0000) /* Port Mapping Key Register */
\r
2053 #define OFS_PMAPCTL (0x0002) /* Port Mapping Control Register */
\r
2054 #define OFS_P1MAP01 (0x0008) /* Port mapping register, P1.0 and P1.1 */
\r
2055 #define OFS_P1MAP23 (0x000a) /* Port mapping register, P1.2 and P1.3 */
\r
2056 #define OFS_P1MAP45 (0x000c) /* Port mapping register, P1.4 and P1.5 */
\r
2057 #define OFS_P1MAP67 (0x000e) /* Port mapping register, P1.6 and P1.7 */
\r
2058 #define OFS_P2MAP01 (0x0010) /* Port mapping register, P2.0 and P2.1 */
\r
2059 #define OFS_P2MAP23 (0x0012) /* Port mapping register, P2.2 and P2.3 */
\r
2060 #define OFS_P2MAP45 (0x0014) /* Port mapping register, P2.4 and P2.5 */
\r
2061 #define OFS_P2MAP67 (0x0016) /* Port mapping register, P2.6 and P2.7 */
\r
2062 #define OFS_P3MAP01 (0x0018) /* Port mapping register, P3.0 and P3.1 */
\r
2063 #define OFS_P3MAP23 (0x001a) /* Port mapping register, P3.2 and P3.3 */
\r
2064 #define OFS_P3MAP45 (0x001c) /* Port mapping register, P3.4 and P3.5 */
\r
2065 #define OFS_P3MAP67 (0x001e) /* Port mapping register, P3.6 and P3.7 */
\r
2066 #define OFS_P4MAP01 (0x0020) /* Port mapping register, P4.0 and P4.1 */
\r
2067 #define OFS_P4MAP23 (0x0022) /* Port mapping register, P4.2 and P4.3 */
\r
2068 #define OFS_P4MAP45 (0x0024) /* Port mapping register, P4.4 and P4.5 */
\r
2069 #define OFS_P4MAP67 (0x0026) /* Port mapping register, P4.6 and P4.7 */
\r
2070 #define OFS_P5MAP01 (0x0028) /* Port mapping register, P5.0 and P5.1 */
\r
2071 #define OFS_P5MAP23 (0x002a) /* Port mapping register, P5.2 and P5.3 */
\r
2072 #define OFS_P5MAP45 (0x002c) /* Port mapping register, P5.4 and P5.5 */
\r
2073 #define OFS_P5MAP67 (0x002e) /* Port mapping register, P5.6 and P5.7 */
\r
2074 #define OFS_P6MAP01 (0x0030) /* Port mapping register, P6.0 and P6.1 */
\r
2075 #define OFS_P6MAP23 (0x0032) /* Port mapping register, P6.2 and P6.3 */
\r
2076 #define OFS_P6MAP45 (0x0034) /* Port mapping register, P6.4 and P6.5 */
\r
2077 #define OFS_P6MAP67 (0x0036) /* Port mapping register, P6.6 and P6.7 */
\r
2078 #define OFS_P7MAP01 (0x0038) /* Port mapping register, P7.0 and P7.1 */
\r
2079 #define OFS_P7MAP23 (0x003a) /* Port mapping register, P7.2 and P7.3 */
\r
2080 #define OFS_P7MAP45 (0x003c) /* Port mapping register, P7.4 and P7.5 */
\r
2081 #define OFS_P7MAP67 (0x003e) /* Port mapping register, P7.6 and P7.7 */
\r
2084 //*****************************************************************************
\r
2086 //*****************************************************************************
\r
2087 #define PSSKEY (HWREG32(0x40010800)) /* Key Register */
\r
2088 #define PSSCTL0 (HWREG32(0x40010804)) /* Control 0 Register */
\r
2089 #define PSSIE (HWREG32(0x40010834)) /* Interrupt Enable Register */
\r
2090 #define PSSIFG (HWREG32(0x40010838)) /* Interrupt Flag Register */
\r
2091 #define PSSCLRIFG (HWREG32(0x4001083C)) /* Clear Interrupt Flag Register */
\r
2093 /* Register offsets from PSS_BASE address */
\r
2094 #define OFS_PSSKEY (0x00000000) /* Key Register */
\r
2095 #define OFS_PSSCTL0 (0x00000004) /* Control 0 Register */
\r
2096 #define OFS_PSSIE (0x00000034) /* Interrupt Enable Register */
\r
2097 #define OFS_PSSIFG (0x00000038) /* Interrupt Flag Register */
\r
2098 #define OFS_PSSCLRIFG (0x0000003c) /* Clear Interrupt Flag Register */
\r
2101 //*****************************************************************************
\r
2102 // REF_A Registers
\r
2103 //*****************************************************************************
\r
2104 #define REFCTL0 (HWREG16(0x40003000)) /* REF Control Register 0 */
\r
2106 /* Register offsets from REF_A_BASE address */
\r
2107 #define OFS_REFCTL0 (0x0000) /* REF Control Register 0 */
\r
2109 #define REFCTL0_L (HWREG8_L(REFCTL0)) /* REF Control Register 0 */
\r
2110 #define REFCTL0_H (HWREG8_H(REFCTL0)) /* REF Control Register 0 */
\r
2112 //*****************************************************************************
\r
2113 // RSTCTL Registers
\r
2114 //*****************************************************************************
\r
2115 #define RSTCTL_RESET_REQ (HWREG32(0xE0042000)) /* Reset Request Register */
\r
2116 #define RSTCTL_HARDRESET_CLR (HWREG32(0xE0042008)) /* Hard Reset Status Clear Register */
\r
2117 #define RSTCTL_HARDRESET_SET (HWREG32(0xE004200C)) /* Hard Reset Status Set Register */
\r
2118 #define RSTCTL_SOFTRESET_STAT (HWREG32(0xE0042010)) /* Soft Reset Status Register */
\r
2119 #define RSTCTL_SOFTRESET_CLR (HWREG32(0xE0042014)) /* Soft Reset Status Clear Register */
\r
2120 #define RSTCTL_SOFTRESET_SET (HWREG32(0xE0042018)) /* Soft Reset Status Set Register */
\r
2121 #define RSTCTL_PSSRESET_STAT (HWREG32(0xE0042100)) /* PSS Reset Status Register */
\r
2122 #define RSTCTL_PSSRESET_CLR (HWREG32(0xE0042104)) /* PSS Reset Status Clear Register */
\r
2123 #define RSTCTL_PCMRESET_STAT (HWREG32(0xE0042108)) /* PCM Reset Status Register */
\r
2124 #define RSTCTL_PCMRESET_CLR (HWREG32(0xE004210C)) /* PCM Reset Status Clear Register */
\r
2125 #define RSTCTL_PINRESET_STAT (HWREG32(0xE0042110)) /* Pin Reset Status Register */
\r
2126 #define RSTCTL_PINRESET_CLR (HWREG32(0xE0042114)) /* Pin Reset Status Clear Register */
\r
2127 #define RSTCTL_REBOOTRESET_STAT (HWREG32(0xE0042118)) /* Reboot Reset Status Register */
\r
2128 #define RSTCTL_REBOOTRESET_CLR (HWREG32(0xE004211C)) /* Reboot Reset Status Clear Register */
\r
2130 /* Register offsets from RSTCTL_BASE address */
\r
2131 #define OFS_RSTCTL_RESET_REQ (0x00000000) /* Reset Request Register */
\r
2132 #define OFS_RSTCTL_HARDRESET_CLR (0x00000008) /* Hard Reset Status Clear Register */
\r
2133 #define OFS_RSTCTL_HARDRESET_SET (0x0000000c) /* Hard Reset Status Set Register */
\r
2134 #define OFS_RSTCTL_SOFTRESET_STAT (0x00000010) /* Soft Reset Status Register */
\r
2135 #define OFS_RSTCTL_SOFTRESET_CLR (0x00000014) /* Soft Reset Status Clear Register */
\r
2136 #define OFS_RSTCTL_SOFTRESET_SET (0x00000018) /* Soft Reset Status Set Register */
\r
2137 #define OFS_RSTCTL_PSSRESET_STAT (0x00000100) /* PSS Reset Status Register */
\r
2138 #define OFS_RSTCTL_PSSRESET_CLR (0x00000104) /* PSS Reset Status Clear Register */
\r
2139 #define OFS_RSTCTL_PCMRESET_STAT (0x00000108) /* PCM Reset Status Register */
\r
2140 #define OFS_RSTCTL_PCMRESET_CLR (0x0000010c) /* PCM Reset Status Clear Register */
\r
2141 #define OFS_RSTCTL_PINRESET_STAT (0x00000110) /* Pin Reset Status Register */
\r
2142 #define OFS_RSTCTL_PINRESET_CLR (0x00000114) /* Pin Reset Status Clear Register */
\r
2143 #define OFS_RSTCTL_REBOOTRESET_STAT (0x00000118) /* Reboot Reset Status Register */
\r
2144 #define OFS_RSTCTL_REBOOTRESET_CLR (0x0000011c) /* Reboot Reset Status Clear Register */
\r
2147 //*****************************************************************************
\r
2148 // RTC_C Registers
\r
2149 //*****************************************************************************
\r
2150 #define RTCCTL0 (HWREG16(0x40004400)) /* RTCCTL0 Register */
\r
2151 #define RTCCTL13 (HWREG16(0x40004402)) /* RTCCTL13 Register */
\r
2152 #define RTCOCAL (HWREG16(0x40004404)) /* RTCOCAL Register */
\r
2153 #define RTCTCMP (HWREG16(0x40004406)) /* RTCTCMP Register */
\r
2154 #define RTCPS0CTL (HWREG16(0x40004408)) /* Real-Time Clock Prescale Timer 0 Control Register */
\r
2155 #define RTCPS1CTL (HWREG16(0x4000440A)) /* Real-Time Clock Prescale Timer 1 Control Register */
\r
2156 #define RTCPS (HWREG16(0x4000440C)) /* Real-Time Clock Prescale Timer Counter Register */
\r
2157 #define RTCIV (HWREG16(0x4000440E)) /* Real-Time Clock Interrupt Vector Register */
\r
2158 #define RTCTIM0 (HWREG16(0x40004410)) /* RTCTIM0 Register ? Hexadecimal Format */
\r
2159 #define RTCTIM0_BCD (HWREG16(0x40004410)) /* */
\r
2160 #define RTCTIM1 (HWREG16(0x40004412)) /* Real-Time Clock Hour, Day of Week */
\r
2161 #define RTCTIM1_BCD (HWREG16(0x40004412)) /* */
\r
2162 #define RTCDATE (HWREG16(0x40004414)) /* RTCDATE - Hexadecimal Format */
\r
2163 #define RTCDATE_BCD (HWREG16(0x40004414)) /* */
\r
2164 #define RTCYEAR (HWREG16(0x40004416)) /* RTCYEAR Register ? Hexadecimal Format */
\r
2165 #define RTCYEAR_BCD (HWREG16(0x40004416)) /* */
\r
2166 #define RTCAMINHR (HWREG16(0x40004418)) /* RTCMINHR - Hexadecimal Format */
\r
2167 #define RTCAMINHR_BCD (HWREG16(0x40004418)) /* */
\r
2168 #define RTCADOWDAY (HWREG16(0x4000441A)) /* RTCADOWDAY - Hexadecimal Format */
\r
2169 #define RTCADOWDAY_BCD (HWREG16(0x4000441A)) /* */
\r
2170 #define RTCBIN2BCD (HWREG16(0x4000441C)) /* Binary-to-BCD Conversion Register */
\r
2171 #define RTCBCD2BIN (HWREG16(0x4000441E)) /* BCD-to-Binary Conversion Register */
\r
2173 /* Register offsets from RTC_C_BASE address */
\r
2174 #define OFS_RTCCTL0 (0x0000) /* RTCCTL0 Register */
\r
2175 #define OFS_RTCCTL13 (0x0002) /* RTCCTL13 Register */
\r
2176 #define OFS_RTCOCAL (0x0004) /* RTCOCAL Register */
\r
2177 #define OFS_RTCTCMP (0x0006) /* RTCTCMP Register */
\r
2178 #define OFS_RTCPS0CTL (0x0008) /* Real-Time Clock Prescale Timer 0 Control Register */
\r
2179 #define OFS_RTCPS1CTL (0x000a) /* Real-Time Clock Prescale Timer 1 Control Register */
\r
2180 #define OFS_RTCPS (0x000c) /* Real-Time Clock Prescale Timer Counter Register */
\r
2181 #define OFS_RTCIV (0x000e) /* Real-Time Clock Interrupt Vector Register */
\r
2182 #define OFS_RTCTIM0 (0x0010) /* RTCTIM0 Register ? Hexadecimal Format */
\r
2183 #define OFS_RTCTIM0_BCD (0x0010) /* */
\r
2184 #define OFS_RTCTIM1 (0x0012) /* Real-Time Clock Hour, Day of Week */
\r
2185 #define OFS_RTCTIM1_BCD (0x0012) /* */
\r
2186 #define OFS_RTCDATE (0x0014) /* RTCDATE - Hexadecimal Format */
\r
2187 #define OFS_RTCDATE_BCD (0x0014) /* */
\r
2188 #define OFS_RTCYEAR (0x0016) /* RTCYEAR Register ? Hexadecimal Format */
\r
2189 #define OFS_RTCYEAR_BCD (0x0016) /* */
\r
2190 #define OFS_RTCAMINHR (0x0018) /* RTCMINHR - Hexadecimal Format */
\r
2191 #define OFS_RTCAMINHR_BCD (0x0018) /* */
\r
2192 #define OFS_RTCADOWDAY (0x001a) /* RTCADOWDAY - Hexadecimal Format */
\r
2193 #define OFS_RTCADOWDAY_BCD (0x001a) /* */
\r
2194 #define OFS_RTCBIN2BCD (0x001c) /* Binary-to-BCD Conversion Register */
\r
2195 #define OFS_RTCBCD2BIN (0x001e) /* BCD-to-Binary Conversion Register */
\r
2197 #define RTCCTL0_L (HWREG8_L(RTCCTL0)) /* RTCCTL0 Register */
\r
2198 #define RTCCTL0_H (HWREG8_H(RTCCTL0)) /* RTCCTL0 Register */
\r
2199 #define RTCCTL1 (HWREG8_L(RTCCTL13)) /* RTCCTL13 Register */
\r
2200 #define RTCCTL13_L (HWREG8_L(RTCCTL13)) /* RTCCTL13 Register */
\r
2201 #define RTCCTL3 (HWREG8_H(RTCCTL13)) /* RTCCTL13 Register */
\r
2202 #define RTCCTL13_H (HWREG8_H(RTCCTL13)) /* RTCCTL13 Register */
\r
2203 #define RTCOCAL_L (HWREG8_L(RTCOCAL)) /* RTCOCAL Register */
\r
2204 #define RTCOCAL_H (HWREG8_H(RTCOCAL)) /* RTCOCAL Register */
\r
2205 #define RTCTCMP_L (HWREG8_L(RTCTCMP)) /* RTCTCMP Register */
\r
2206 #define RTCTCMP_H (HWREG8_H(RTCTCMP)) /* RTCTCMP Register */
\r
2207 #define RTCPS0CTL_L (HWREG8_L(RTCPS0CTL)) /* Real-Time Clock Prescale Timer 0 Control Register */
\r
2208 #define RTCPS0CTL_H (HWREG8_H(RTCPS0CTL)) /* Real-Time Clock Prescale Timer 0 Control Register */
\r
2209 #define RTCPS1CTL_L (HWREG8_L(RTCPS1CTL)) /* Real-Time Clock Prescale Timer 1 Control Register */
\r
2210 #define RTCPS1CTL_H (HWREG8_H(RTCPS1CTL)) /* Real-Time Clock Prescale Timer 1 Control Register */
\r
2211 #define RTCPS0 (HWREG8_L(RTCPS)) /* Real-Time Clock Prescale Timer Counter Register */
\r
2212 #define RTCPS_L (HWREG8_L(RTCPS)) /* Real-Time Clock Prescale Timer Counter Register */
\r
2213 #define RTCPS1 (HWREG8_H(RTCPS)) /* Real-Time Clock Prescale Timer Counter Register */
\r
2214 #define RTCPS_H (HWREG8_H(RTCPS)) /* Real-Time Clock Prescale Timer Counter Register */
\r
2215 #define RTCSEC (HWREG8_L(RTCTIM0)) /* Real-Time Clock Seconds */
\r
2216 #define RTCTIM0_L (HWREG8_L(RTCTIM0)) /* Real-Time Clock Seconds */
\r
2217 #define RTCMIN (HWREG8_H(RTCTIM0)) /* Real-Time Clock Minutes */
\r
2218 #define RTCTIM0_H (HWREG8_H(RTCTIM0)) /* Real-Time Clock Minutes */
\r
2219 #define RTCHOUR (HWREG8_L(RTCTIM1)) /* Real-Time Clock Hour */
\r
2220 #define RTCTIM1_L (HWREG8_L(RTCTIM1)) /* Real-Time Clock Hour */
\r
2221 #define RTCDOW (HWREG8_H(RTCTIM1)) /* Real-Time Clock Day of Week */
\r
2222 #define RTCTIM1_H (HWREG8_H(RTCTIM1)) /* Real-Time Clock Day of Week */
\r
2223 #define RTCDAY (HWREG8_L(RTCDATE)) /* Real-Time Clock Day of Month */
\r
2224 #define RTCDATE_L (HWREG8_L(RTCDATE)) /* Real-Time Clock Day of Month */
\r
2225 #define RTCMON (HWREG8_H(RTCDATE)) /* Real-Time Clock Month */
\r
2226 #define RTCDATE_H (HWREG8_H(RTCDATE)) /* Real-Time Clock Month */
\r
2227 #define RTCAMIN (HWREG8_L(RTCAMINHR)) /* Real-Time Clock Minutes Alarm */
\r
2228 #define RTCAMINHR_L (HWREG8_L(RTCAMINHR)) /* Real-Time Clock Minutes Alarm */
\r
2229 #define RTCAHOUR (HWREG8_H(RTCAMINHR)) /* Real-Time Clock Hours Alarm */
\r
2230 #define RTCAMINHR_H (HWREG8_H(RTCAMINHR)) /* Real-Time Clock Hours Alarm */
\r
2231 #define RTCADOW (HWREG8_L(RTCADOWDAY))/* Real-Time Clock Day of Week Alarm */
\r
2232 #define RTCADOWDAY_L (HWREG8_L(RTCADOWDAY))/* Real-Time Clock Day of Week Alarm */
\r
2233 #define RTCADAY (HWREG8_H(RTCADOWDAY))/* Real-Time Clock Day of Month Alarm */
\r
2234 #define RTCADOWDAY_H (HWREG8_H(RTCADOWDAY))/* Real-Time Clock Day of Month Alarm */
\r
2236 //*****************************************************************************
\r
2238 //*****************************************************************************
\r
2239 #define SCB_CPUID (HWREG32(0xE000ED00)) /* CPUID Base Register */
\r
2240 #define SCB_ICSR (HWREG32(0xE000ED04)) /* Interrupt Control State Register */
\r
2241 #define SCB_VTOR (HWREG32(0xE000ED08)) /* Vector Table Offset Register */
\r
2242 #define SCB_AIRCR (HWREG32(0xE000ED0C)) /* Application Interrupt/Reset Control Register */
\r
2243 #define SCB_SCR (HWREG32(0xE000ED10)) /* System Control Register */
\r
2244 #define SCB_CCR (HWREG32(0xE000ED14)) /* Configuration Control Register */
\r
2245 #define SCB_SHPR1 (HWREG32(0xE000ED18)) /* System Handlers 4-7 Priority Register */
\r
2246 #define SCB_SHPR2 (HWREG32(0xE000ED1C)) /* System Handlers 8-11 Priority Register */
\r
2247 #define SCB_SHPR3 (HWREG32(0xE000ED20)) /* System Handlers 12-15 Priority Register */
\r
2248 #define SCB_SHCSR (HWREG32(0xE000ED24)) /* System Handler Control and State Register */
\r
2249 #define SCB_CFSR (HWREG32(0xE000ED28)) /* Configurable Fault Status Registers */
\r
2250 #define SCB_HFSR (HWREG32(0xE000ED2C)) /* Hard Fault Status Register */
\r
2251 #define SCB_DFSR (HWREG32(0xE000ED30)) /* Debug Fault Status Register */
\r
2252 #define SCB_MMFAR (HWREG32(0xE000ED34)) /* Mem Manage Fault Address Register */
\r
2253 #define SCB_BFAR (HWREG32(0xE000ED38)) /* Bus Fault Address Register */
\r
2254 #define SCB_AFSR (HWREG32(0xE000ED3C)) /* Auxiliary Fault Status Register */
\r
2255 #define SCB_PFR0 (HWREG32(0xE000ED40)) /* Processor Feature register0 */
\r
2256 #define SCB_PFR1 (HWREG32(0xE000ED44)) /* Processor Feature register1 */
\r
2257 #define SCB_DFR0 (HWREG32(0xE000ED48)) /* Debug Feature register0 */
\r
2258 #define SCB_AFR0 (HWREG32(0xE000ED4C)) /* Auxiliary Feature register0 */
\r
2259 #define SCB_MMFR0 (HWREG32(0xE000ED50)) /* Memory Model Feature register0 */
\r
2260 #define SCB_MMFR1 (HWREG32(0xE000ED54)) /* Memory Model Feature register1 */
\r
2261 #define SCB_MMFR2 (HWREG32(0xE000ED58)) /* Memory Model Feature register2 */
\r
2262 #define SCB_MMFR3 (HWREG32(0xE000ED5C)) /* Memory Model Feature register3 */
\r
2263 #define SCB_ISAR0 (HWREG32(0xE000ED60)) /* ISA Feature register0 */
\r
2264 #define SCB_ISAR1 (HWREG32(0xE000ED64)) /* ISA Feature register1 */
\r
2265 #define SCB_ISAR2 (HWREG32(0xE000ED68)) /* ISA Feature register2 */
\r
2266 #define SCB_ISAR3 (HWREG32(0xE000ED6C)) /* ISA Feature register3 */
\r
2267 #define SCB_ISAR4 (HWREG32(0xE000ED70)) /* ISA Feature register4 */
\r
2268 #define SCB_CPACR (HWREG32(0xE000ED88)) /* Coprocessor Access Control Register */
\r
2270 /* Register offsets from SCB_BASE address */
\r
2271 #define OFS_SCB_CPUID (0x00000D00) /* CPUID Base Register */
\r
2272 #define OFS_SCB_ICSR (0x00000D04) /* Interrupt Control State Register */
\r
2273 #define OFS_SCB_VTOR (0x00000D08) /* Vector Table Offset Register */
\r
2274 #define OFS_SCB_AIRCR (0x00000D0C) /* Application Interrupt/Reset Control Register */
\r
2275 #define OFS_SCB_SCR (0x00000D10) /* System Control Register */
\r
2276 #define OFS_SCB_CCR (0x00000D14) /* Configuration Control Register */
\r
2277 #define OFS_SCB_SHPR1 (0x00000D18) /* System Handlers 4-7 Priority Register */
\r
2278 #define OFS_SCB_SHPR2 (0x00000D1C) /* System Handlers 8-11 Priority Register */
\r
2279 #define OFS_SCB_SHPR3 (0x00000D20) /* System Handlers 12-15 Priority Register */
\r
2280 #define OFS_SCB_SHCSR (0x00000D24) /* System Handler Control and State Register */
\r
2281 #define OFS_SCB_CFSR (0x00000D28) /* Configurable Fault Status Registers */
\r
2282 #define OFS_SCB_HFSR (0x00000D2C) /* Hard Fault Status Register */
\r
2283 #define OFS_SCB_DFSR (0x00000D30) /* Debug Fault Status Register */
\r
2284 #define OFS_SCB_MMFAR (0x00000D34) /* Mem Manage Fault Address Register */
\r
2285 #define OFS_SCB_BFAR (0x00000D38) /* Bus Fault Address Register */
\r
2286 #define OFS_SCB_AFSR (0x00000D3C) /* Auxiliary Fault Status Register */
\r
2287 #define OFS_SCB_PFR0 (0x00000D40) /* Processor Feature register0 */
\r
2288 #define OFS_SCB_PFR1 (0x00000D44) /* Processor Feature register1 */
\r
2289 #define OFS_SCB_DFR0 (0x00000D48) /* Debug Feature register0 */
\r
2290 #define OFS_SCB_AFR0 (0x00000D4C) /* Auxiliary Feature register0 */
\r
2291 #define OFS_SCB_MMFR0 (0x00000D50) /* Memory Model Feature register0 */
\r
2292 #define OFS_SCB_MMFR1 (0x00000D54) /* Memory Model Feature register1 */
\r
2293 #define OFS_SCB_MMFR2 (0x00000D58) /* Memory Model Feature register2 */
\r
2294 #define OFS_SCB_MMFR3 (0x00000D5C) /* Memory Model Feature register3 */
\r
2295 #define OFS_SCB_ISAR0 (0x00000D60) /* ISA Feature register0 */
\r
2296 #define OFS_SCB_ISAR1 (0x00000D64) /* ISA Feature register1 */
\r
2297 #define OFS_SCB_ISAR2 (0x00000D68) /* ISA Feature register2 */
\r
2298 #define OFS_SCB_ISAR3 (0x00000D6C) /* ISA Feature register3 */
\r
2299 #define OFS_SCB_ISAR4 (0x00000D70) /* ISA Feature register4 */
\r
2300 #define OFS_SCB_CPACR (0x00000D88) /* Coprocessor Access Control Register */
\r
2303 //*****************************************************************************
\r
2304 // SCnSCB Registers
\r
2305 //*****************************************************************************
\r
2306 #define SCnSCB_ICTR (HWREG32(0xE000E004)) /* Interrupt Control Type Register */
\r
2307 #define SCnSCB_ACTLR (HWREG32(0xE000E008)) /* Auxiliary Control Register */
\r
2309 /* Register offsets from SCnSCB_BASE address */
\r
2310 #define OFS_SCnSCB_ICTR (0x00000004) /* Interrupt Control Type Register */
\r
2311 #define OFS_SCnSCB_ACTLR (0x00000008) /* Auxiliary Control Register */
\r
2314 //*****************************************************************************
\r
2315 // SYSCTL Registers
\r
2316 //*****************************************************************************
\r
2317 #define SYSCTL_REBOOT_CTL (HWREG32(0xE0043000)) /* Reboot Control Register */
\r
2318 #define SYSCTL_NMI_CTLSTAT (HWREG32(0xE0043004)) /* NMI Control and Status Register */
\r
2319 #define SYSCTL_WDTRESET_CTL (HWREG32(0xE0043008)) /* Watchdog Reset Control Register */
\r
2320 #define SYSCTL_PERIHALT_CTL (HWREG32(0xE004300C)) /* Peripheral Halt Control Register */
\r
2321 #define SYSCTL_SRAM_SIZE (HWREG32(0xE0043010)) /* SRAM Size Register */
\r
2322 #define SYSCTL_SRAM_BANKEN (HWREG32(0xE0043014)) /* SRAM Bank Enable Register */
\r
2323 #define SYSCTL_SRAM_BANKRET (HWREG32(0xE0043018)) /* SRAM Bank Retention Control Register */
\r
2324 #define SYSCTL_FLASH_SIZE (HWREG32(0xE0043020)) /* Flash Size Register */
\r
2325 #define SYSCTL_DIO_GLTFLT_CTL (HWREG32(0xE0043030)) /* Digital I/O Glitch Filter Control Register */
\r
2326 #define SYSCTL_SECDATA_UNLOCK (HWREG32(0xE0043040)) /* IP Protected Secure Zone Data Access Unlock Register */
\r
2327 #define SYSCTL_MASTER_UNLOCK (HWREG32(0xE0044000)) /* Master Unlock Register */
\r
2328 #define SYSCTL_BOOTOVER_REQ0 (HWREG32(0xE0044004)) /* Boot Override Request Register */
\r
2329 #define SYSCTL_BOOTOVER_REQ1 (HWREG32(0xE0044008)) /* Boot Override Request Register */
\r
2330 #define SYSCTL_BOOTOVER_ACK (HWREG32(0xE004400C)) /* Boot Override Acknowledge Register */
\r
2331 #define SYSCTL_RESET_REQ (HWREG32(0xE0044010)) /* Reset Request Register */
\r
2332 #define SYSCTL_RESET_STATOVER (HWREG32(0xE0044014)) /* Reset Status and Override Register */
\r
2333 #define SYSCTL_SYSTEM_STAT (HWREG32(0xE0044020)) /* System Status Register */
\r
2335 /* Register offsets from SYSCTL_BASE address */
\r
2336 #define OFS_SYSCTL_REBOOT_CTL (0x00000000) /* Reboot Control Register */
\r
2337 #define OFS_SYSCTL_NMI_CTLSTAT (0x00000004) /* NMI Control and Status Register */
\r
2338 #define OFS_SYSCTL_WDTRESET_CTL (0x00000008) /* Watchdog Reset Control Register */
\r
2339 #define OFS_SYSCTL_PERIHALT_CTL (0x0000000c) /* Peripheral Halt Control Register */
\r
2340 #define OFS_SYSCTL_SRAM_SIZE (0x00000010) /* SRAM Size Register */
\r
2341 #define OFS_SYSCTL_SRAM_BANKEN (0x00000014) /* SRAM Bank Enable Register */
\r
2342 #define OFS_SYSCTL_SRAM_BANKRET (0x00000018) /* SRAM Bank Retention Control Register */
\r
2343 #define OFS_SYSCTL_FLASH_SIZE (0x00000020) /* Flash Size Register */
\r
2344 #define OFS_SYSCTL_DIO_GLTFLT_CTL (0x00000030) /* Digital I/O Glitch Filter Control Register */
\r
2345 #define OFS_SYSCTL_SECDATA_UNLOCK (0x00000040) /* IP Protected Secure Zone Data Access Unlock Register */
\r
2346 #define OFS_SYSCTL_MASTER_UNLOCK (0x00001000) /* Master Unlock Register */
\r
2347 #define OFS_SYSCTL_BOOTOVER_REQ0 (0x00001004) /* Boot Override Request Register */
\r
2348 #define OFS_SYSCTL_BOOTOVER_REQ1 (0x00001008) /* Boot Override Request Register */
\r
2349 #define OFS_SYSCTL_BOOTOVER_ACK (0x0000100c) /* Boot Override Acknowledge Register */
\r
2350 #define OFS_SYSCTL_RESET_REQ (0x00001010) /* Reset Request Register */
\r
2351 #define OFS_SYSCTL_RESET_STATOVER (0x00001014) /* Reset Status and Override Register */
\r
2352 #define OFS_SYSCTL_SYSTEM_STAT (0x00001020) /* System Status Register */
\r
2355 //*****************************************************************************
\r
2356 // SYSTICK Registers
\r
2357 //*****************************************************************************
\r
2358 #define SYSTICK_STCSR (HWREG32(0xE000E010)) /* SysTick Control and Status Register */
\r
2359 #define SYSTICK_STRVR (HWREG32(0xE000E014)) /* SysTick Reload Value Register */
\r
2360 #define SYSTICK_STCVR (HWREG32(0xE000E018)) /* SysTick Current Value Register */
\r
2361 #define SYSTICK_STCR (HWREG32(0xE000E01C)) /* SysTick Calibration Value Register */
\r
2363 /* Register offsets from SYSTICK_BASE address */
\r
2364 #define OFS_SYSTICK_STCSR (0x00000010) /* SysTick Control and Status Register */
\r
2365 #define OFS_SYSTICK_STRVR (0x00000014) /* SysTick Reload Value Register */
\r
2366 #define OFS_SYSTICK_STCVR (0x00000018) /* SysTick Current Value Register */
\r
2367 #define OFS_SYSTICK_STCR (0x0000001C) /* SysTick Calibration Value Register */
\r
2370 //*****************************************************************************
\r
2371 // TIMER32 Registers
\r
2372 //*****************************************************************************
\r
2373 #define TIMER32_LOAD1 (HWREG32(0x4000C000)) /* Timer 1 Load Register */
\r
2374 #define TIMER32_VALUE1 (HWREG32(0x4000C004)) /* Timer 1 Current Value Register */
\r
2375 #define TIMER32_CONTROL1 (HWREG32(0x4000C008)) /* Timer 1 Timer Control Register */
\r
2376 #define TIMER32_INTCLR1 (HWREG32(0x4000C00C)) /* Timer 1 Interrupt Clear Register */
\r
2377 #define TIMER32_RIS1 (HWREG32(0x4000C010)) /* Timer 1 Raw Interrupt Status Register */
\r
2378 #define TIMER32_MIS1 (HWREG32(0x4000C014)) /* Timer 1 Interrupt Status Register */
\r
2379 #define TIMER32_BGLOAD1 (HWREG32(0x4000C018)) /* Timer 1 Background Load Register */
\r
2380 #define TIMER32_LOAD2 (HWREG32(0x4000C020)) /* Timer 2 Load Register */
\r
2381 #define TIMER32_VALUE2 (HWREG32(0x4000C024)) /* Timer 2 Current Value Register */
\r
2382 #define TIMER32_CONTROL2 (HWREG32(0x4000C028)) /* Timer 2 Timer Control Register */
\r
2383 #define TIMER32_INTCLR2 (HWREG32(0x4000C02C)) /* Timer 2 Interrupt Clear Register */
\r
2384 #define TIMER32_RIS2 (HWREG32(0x4000C030)) /* Timer 2 Raw Interrupt Status Register */
\r
2385 #define TIMER32_MIS2 (HWREG32(0x4000C034)) /* Timer 2 Interrupt Status Register */
\r
2386 #define TIMER32_BGLOAD2 (HWREG32(0x4000C038)) /* Timer 2 Background Load Register */
\r
2388 /* Register offsets from TIMER32_BASE address */
\r
2389 #define OFS_TIMER32_LOAD1 (0x00000000) /* Timer 1 Load Register */
\r
2390 #define OFS_TIMER32_VALUE1 (0x00000004) /* Timer 1 Current Value Register */
\r
2391 #define OFS_TIMER32_CONTROL1 (0x00000008) /* Timer 1 Timer Control Register */
\r
2392 #define OFS_TIMER32_INTCLR1 (0x0000000C) /* Timer 1 Interrupt Clear Register */
\r
2393 #define OFS_TIMER32_RIS1 (0x00000010) /* Timer 1 Raw Interrupt Status Register */
\r
2394 #define OFS_TIMER32_MIS1 (0x00000014) /* Timer 1 Interrupt Status Register */
\r
2395 #define OFS_TIMER32_BGLOAD1 (0x00000018) /* Timer 1 Background Load Register */
\r
2396 #define OFS_TIMER32_LOAD2 (0x00000020) /* Timer 2 Load Register */
\r
2397 #define OFS_TIMER32_VALUE2 (0x00000024) /* Timer 2 Current Value Register */
\r
2398 #define OFS_TIMER32_CONTROL2 (0x00000028) /* Timer 2 Timer Control Register */
\r
2399 #define OFS_TIMER32_INTCLR2 (0x0000002C) /* Timer 2 Interrupt Clear Register */
\r
2400 #define OFS_TIMER32_RIS2 (0x00000030) /* Timer 2 Raw Interrupt Status Register */
\r
2401 #define OFS_TIMER32_MIS2 (0x00000034) /* Timer 2 Interrupt Status Register */
\r
2402 #define OFS_TIMER32_BGLOAD2 (0x00000038) /* Timer 2 Background Load Register */
\r
2405 //*****************************************************************************
\r
2406 // TIMER_A0 Registers
\r
2407 //*****************************************************************************
\r
2408 #define TA0CTL (HWREG16(0x40000000)) /* TimerAx Control Register */
\r
2409 #define TA0CCTL0 (HWREG16(0x40000002)) /* Timer_A Capture/Compare Control Register */
\r
2410 #define TA0CCTL1 (HWREG16(0x40000004)) /* Timer_A Capture/Compare Control Register */
\r
2411 #define TA0CCTL2 (HWREG16(0x40000006)) /* Timer_A Capture/Compare Control Register */
\r
2412 #define TA0CCTL3 (HWREG16(0x40000008)) /* Timer_A Capture/Compare Control Register */
\r
2413 #define TA0CCTL4 (HWREG16(0x4000000A)) /* Timer_A Capture/Compare Control Register */
\r
2414 #define TA0CCTL5 (HWREG16(0x4000000C)) /* Timer_A Capture/Compare Control Register */
\r
2415 #define TA0CCTL6 (HWREG16(0x4000000E)) /* Timer_A Capture/Compare Control Register */
\r
2416 #define TA0R (HWREG16(0x40000010)) /* TimerA register */
\r
2417 #define TA0CCR0 (HWREG16(0x40000012)) /* Timer_A Capture/Compare Register */
\r
2418 #define TA0CCR1 (HWREG16(0x40000014)) /* Timer_A Capture/Compare Register */
\r
2419 #define TA0CCR2 (HWREG16(0x40000016)) /* Timer_A Capture/Compare Register */
\r
2420 #define TA0CCR3 (HWREG16(0x40000018)) /* Timer_A Capture/Compare Register */
\r
2421 #define TA0CCR4 (HWREG16(0x4000001A)) /* Timer_A Capture/Compare Register */
\r
2422 #define TA0CCR5 (HWREG16(0x4000001C)) /* Timer_A Capture/Compare Register */
\r
2423 #define TA0CCR6 (HWREG16(0x4000001E)) /* Timer_A Capture/Compare Register */
\r
2424 #define TA0EX0 (HWREG16(0x40000020)) /* TimerAx Expansion 0 Register */
\r
2425 #define TA0IV (HWREG16(0x4000002E)) /* TimerAx Interrupt Vector Register */
\r
2427 /* Register offsets from TIMER_A0_BASE address */
\r
2428 #define OFS_TA0CTL (0x0000) /* TimerAx Control Register */
\r
2429 #define OFS_TA0CCTL0 (0x0002) /* Timer_A Capture/Compare Control Register */
\r
2430 #define OFS_TA0CCTL1 (0x0004) /* Timer_A Capture/Compare Control Register */
\r
2431 #define OFS_TA0CCTL2 (0x0006) /* Timer_A Capture/Compare Control Register */
\r
2432 #define OFS_TA0CCTL3 (0x0008) /* Timer_A Capture/Compare Control Register */
\r
2433 #define OFS_TA0CCTL4 (0x000A) /* Timer_A Capture/Compare Control Register */
\r
2434 #define OFS_TA0CCTL5 (0x000C) /* Timer_A Capture/Compare Control Register */
\r
2435 #define OFS_TA0CCTL6 (0x000E) /* Timer_A Capture/Compare Control Register */
\r
2436 #define OFS_TA0R (0x0010) /* TimerA register */
\r
2437 #define OFS_TA0CCR0 (0x0012) /* Timer_A Capture/Compare Register */
\r
2438 #define OFS_TA0CCR1 (0x0014) /* Timer_A Capture/Compare Register */
\r
2439 #define OFS_TA0CCR2 (0x0016) /* Timer_A Capture/Compare Register */
\r
2440 #define OFS_TA0CCR3 (0x0018) /* Timer_A Capture/Compare Register */
\r
2441 #define OFS_TA0CCR4 (0x001A) /* Timer_A Capture/Compare Register */
\r
2442 #define OFS_TA0CCR5 (0x001C) /* Timer_A Capture/Compare Register */
\r
2443 #define OFS_TA0CCR6 (0x001E) /* Timer_A Capture/Compare Register */
\r
2444 #define OFS_TA0EX0 (0x0020) /* TimerAx Expansion 0 Register */
\r
2445 #define OFS_TA0IV (0x002e) /* TimerAx Interrupt Vector Register */
\r
2448 //*****************************************************************************
\r
2449 // TIMER_A1 Registers
\r
2450 //*****************************************************************************
\r
2451 #define TA1CTL (HWREG16(0x40000400)) /* TimerAx Control Register */
\r
2452 #define TA1CCTL0 (HWREG16(0x40000402)) /* Timer_A Capture/Compare Control Register */
\r
2453 #define TA1CCTL1 (HWREG16(0x40000404)) /* Timer_A Capture/Compare Control Register */
\r
2454 #define TA1CCTL2 (HWREG16(0x40000406)) /* Timer_A Capture/Compare Control Register */
\r
2455 #define TA1CCTL3 (HWREG16(0x40000408)) /* Timer_A Capture/Compare Control Register */
\r
2456 #define TA1CCTL4 (HWREG16(0x4000040A)) /* Timer_A Capture/Compare Control Register */
\r
2457 #define TA1CCTL5 (HWREG16(0x4000040C)) /* Timer_A Capture/Compare Control Register */
\r
2458 #define TA1CCTL6 (HWREG16(0x4000040E)) /* Timer_A Capture/Compare Control Register */
\r
2459 #define TA1R (HWREG16(0x40000410)) /* TimerA register */
\r
2460 #define TA1CCR0 (HWREG16(0x40000412)) /* Timer_A Capture/Compare Register */
\r
2461 #define TA1CCR1 (HWREG16(0x40000414)) /* Timer_A Capture/Compare Register */
\r
2462 #define TA1CCR2 (HWREG16(0x40000416)) /* Timer_A Capture/Compare Register */
\r
2463 #define TA1CCR3 (HWREG16(0x40000418)) /* Timer_A Capture/Compare Register */
\r
2464 #define TA1CCR4 (HWREG16(0x4000041A)) /* Timer_A Capture/Compare Register */
\r
2465 #define TA1CCR5 (HWREG16(0x4000041C)) /* Timer_A Capture/Compare Register */
\r
2466 #define TA1CCR6 (HWREG16(0x4000041E)) /* Timer_A Capture/Compare Register */
\r
2467 #define TA1EX0 (HWREG16(0x40000420)) /* TimerAx Expansion 0 Register */
\r
2468 #define TA1IV (HWREG16(0x4000042E)) /* TimerAx Interrupt Vector Register */
\r
2470 /* Register offsets from TIMER_A1_BASE address */
\r
2471 #define OFS_TA1CTL (0x0000) /* TimerAx Control Register */
\r
2472 #define OFS_TA1CCTL0 (0x0002) /* Timer_A Capture/Compare Control Register */
\r
2473 #define OFS_TA1CCTL1 (0x0004) /* Timer_A Capture/Compare Control Register */
\r
2474 #define OFS_TA1CCTL2 (0x0006) /* Timer_A Capture/Compare Control Register */
\r
2475 #define OFS_TA1CCTL3 (0x0008) /* Timer_A Capture/Compare Control Register */
\r
2476 #define OFS_TA1CCTL4 (0x000A) /* Timer_A Capture/Compare Control Register */
\r
2477 #define OFS_TA1CCTL5 (0x000C) /* Timer_A Capture/Compare Control Register */
\r
2478 #define OFS_TA1CCTL6 (0x000E) /* Timer_A Capture/Compare Control Register */
\r
2479 #define OFS_TA1R (0x0010) /* TimerA register */
\r
2480 #define OFS_TA1CCR0 (0x0012) /* Timer_A Capture/Compare Register */
\r
2481 #define OFS_TA1CCR1 (0x0014) /* Timer_A Capture/Compare Register */
\r
2482 #define OFS_TA1CCR2 (0x0016) /* Timer_A Capture/Compare Register */
\r
2483 #define OFS_TA1CCR3 (0x0018) /* Timer_A Capture/Compare Register */
\r
2484 #define OFS_TA1CCR4 (0x001A) /* Timer_A Capture/Compare Register */
\r
2485 #define OFS_TA1CCR5 (0x001C) /* Timer_A Capture/Compare Register */
\r
2486 #define OFS_TA1CCR6 (0x001E) /* Timer_A Capture/Compare Register */
\r
2487 #define OFS_TA1EX0 (0x0020) /* TimerAx Expansion 0 Register */
\r
2488 #define OFS_TA1IV (0x002e) /* TimerAx Interrupt Vector Register */
\r
2491 //*****************************************************************************
\r
2492 // TIMER_A2 Registers
\r
2493 //*****************************************************************************
\r
2494 #define TA2CTL (HWREG16(0x40000800)) /* TimerAx Control Register */
\r
2495 #define TA2CCTL0 (HWREG16(0x40000802)) /* Timer_A Capture/Compare Control Register */
\r
2496 #define TA2CCTL1 (HWREG16(0x40000804)) /* Timer_A Capture/Compare Control Register */
\r
2497 #define TA2CCTL2 (HWREG16(0x40000806)) /* Timer_A Capture/Compare Control Register */
\r
2498 #define TA2CCTL3 (HWREG16(0x40000808)) /* Timer_A Capture/Compare Control Register */
\r
2499 #define TA2CCTL4 (HWREG16(0x4000080A)) /* Timer_A Capture/Compare Control Register */
\r
2500 #define TA2CCTL5 (HWREG16(0x4000080C)) /* Timer_A Capture/Compare Control Register */
\r
2501 #define TA2CCTL6 (HWREG16(0x4000080E)) /* Timer_A Capture/Compare Control Register */
\r
2502 #define TA2R (HWREG16(0x40000810)) /* TimerA register */
\r
2503 #define TA2CCR0 (HWREG16(0x40000812)) /* Timer_A Capture/Compare Register */
\r
2504 #define TA2CCR1 (HWREG16(0x40000814)) /* Timer_A Capture/Compare Register */
\r
2505 #define TA2CCR2 (HWREG16(0x40000816)) /* Timer_A Capture/Compare Register */
\r
2506 #define TA2CCR3 (HWREG16(0x40000818)) /* Timer_A Capture/Compare Register */
\r
2507 #define TA2CCR4 (HWREG16(0x4000081A)) /* Timer_A Capture/Compare Register */
\r
2508 #define TA2CCR5 (HWREG16(0x4000081C)) /* Timer_A Capture/Compare Register */
\r
2509 #define TA2CCR6 (HWREG16(0x4000081E)) /* Timer_A Capture/Compare Register */
\r
2510 #define TA2EX0 (HWREG16(0x40000820)) /* TimerAx Expansion 0 Register */
\r
2511 #define TA2IV (HWREG16(0x4000082E)) /* TimerAx Interrupt Vector Register */
\r
2513 /* Register offsets from TIMER_A2_BASE address */
\r
2514 #define OFS_TA2CTL (0x0000) /* TimerAx Control Register */
\r
2515 #define OFS_TA2CCTL0 (0x0002) /* Timer_A Capture/Compare Control Register */
\r
2516 #define OFS_TA2CCTL1 (0x0004) /* Timer_A Capture/Compare Control Register */
\r
2517 #define OFS_TA2CCTL2 (0x0006) /* Timer_A Capture/Compare Control Register */
\r
2518 #define OFS_TA2CCTL3 (0x0008) /* Timer_A Capture/Compare Control Register */
\r
2519 #define OFS_TA2CCTL4 (0x000A) /* Timer_A Capture/Compare Control Register */
\r
2520 #define OFS_TA2CCTL5 (0x000C) /* Timer_A Capture/Compare Control Register */
\r
2521 #define OFS_TA2CCTL6 (0x000E) /* Timer_A Capture/Compare Control Register */
\r
2522 #define OFS_TA2R (0x0010) /* TimerA register */
\r
2523 #define OFS_TA2CCR0 (0x0012) /* Timer_A Capture/Compare Register */
\r
2524 #define OFS_TA2CCR1 (0x0014) /* Timer_A Capture/Compare Register */
\r
2525 #define OFS_TA2CCR2 (0x0016) /* Timer_A Capture/Compare Register */
\r
2526 #define OFS_TA2CCR3 (0x0018) /* Timer_A Capture/Compare Register */
\r
2527 #define OFS_TA2CCR4 (0x001A) /* Timer_A Capture/Compare Register */
\r
2528 #define OFS_TA2CCR5 (0x001C) /* Timer_A Capture/Compare Register */
\r
2529 #define OFS_TA2CCR6 (0x001E) /* Timer_A Capture/Compare Register */
\r
2530 #define OFS_TA2EX0 (0x0020) /* TimerAx Expansion 0 Register */
\r
2531 #define OFS_TA2IV (0x002e) /* TimerAx Interrupt Vector Register */
\r
2534 //*****************************************************************************
\r
2535 // TIMER_A3 Registers
\r
2536 //*****************************************************************************
\r
2537 #define TA3CTL (HWREG16(0x40000C00)) /* TimerAx Control Register */
\r
2538 #define TA3CCTL0 (HWREG16(0x40000C02)) /* Timer_A Capture/Compare Control Register */
\r
2539 #define TA3CCTL1 (HWREG16(0x40000C04)) /* Timer_A Capture/Compare Control Register */
\r
2540 #define TA3CCTL2 (HWREG16(0x40000C06)) /* Timer_A Capture/Compare Control Register */
\r
2541 #define TA3CCTL3 (HWREG16(0x40000C08)) /* Timer_A Capture/Compare Control Register */
\r
2542 #define TA3CCTL4 (HWREG16(0x40000C0A)) /* Timer_A Capture/Compare Control Register */
\r
2543 #define TA3CCTL5 (HWREG16(0x40000C0C)) /* Timer_A Capture/Compare Control Register */
\r
2544 #define TA3CCTL6 (HWREG16(0x40000C0E)) /* Timer_A Capture/Compare Control Register */
\r
2545 #define TA3R (HWREG16(0x40000C10)) /* TimerA register */
\r
2546 #define TA3CCR0 (HWREG16(0x40000C12)) /* Timer_A Capture/Compare Register */
\r
2547 #define TA3CCR1 (HWREG16(0x40000C14)) /* Timer_A Capture/Compare Register */
\r
2548 #define TA3CCR2 (HWREG16(0x40000C16)) /* Timer_A Capture/Compare Register */
\r
2549 #define TA3CCR3 (HWREG16(0x40000C18)) /* Timer_A Capture/Compare Register */
\r
2550 #define TA3CCR4 (HWREG16(0x40000C1A)) /* Timer_A Capture/Compare Register */
\r
2551 #define TA3CCR5 (HWREG16(0x40000C1C)) /* Timer_A Capture/Compare Register */
\r
2552 #define TA3CCR6 (HWREG16(0x40000C1E)) /* Timer_A Capture/Compare Register */
\r
2553 #define TA3EX0 (HWREG16(0x40000C20)) /* TimerAx Expansion 0 Register */
\r
2554 #define TA3IV (HWREG16(0x40000C2E)) /* TimerAx Interrupt Vector Register */
\r
2556 /* Register offsets from TIMER_A3_BASE address */
\r
2557 #define OFS_TA3CTL (0x0000) /* TimerAx Control Register */
\r
2558 #define OFS_TA3CCTL0 (0x0002) /* Timer_A Capture/Compare Control Register */
\r
2559 #define OFS_TA3CCTL1 (0x0004) /* Timer_A Capture/Compare Control Register */
\r
2560 #define OFS_TA3CCTL2 (0x0006) /* Timer_A Capture/Compare Control Register */
\r
2561 #define OFS_TA3CCTL3 (0x0008) /* Timer_A Capture/Compare Control Register */
\r
2562 #define OFS_TA3CCTL4 (0x000A) /* Timer_A Capture/Compare Control Register */
\r
2563 #define OFS_TA3CCTL5 (0x000C) /* Timer_A Capture/Compare Control Register */
\r
2564 #define OFS_TA3CCTL6 (0x000E) /* Timer_A Capture/Compare Control Register */
\r
2565 #define OFS_TA3R (0x0010) /* TimerA register */
\r
2566 #define OFS_TA3CCR0 (0x0012) /* Timer_A Capture/Compare Register */
\r
2567 #define OFS_TA3CCR1 (0x0014) /* Timer_A Capture/Compare Register */
\r
2568 #define OFS_TA3CCR2 (0x0016) /* Timer_A Capture/Compare Register */
\r
2569 #define OFS_TA3CCR3 (0x0018) /* Timer_A Capture/Compare Register */
\r
2570 #define OFS_TA3CCR4 (0x001A) /* Timer_A Capture/Compare Register */
\r
2571 #define OFS_TA3CCR5 (0x001C) /* Timer_A Capture/Compare Register */
\r
2572 #define OFS_TA3CCR6 (0x001E) /* Timer_A Capture/Compare Register */
\r
2573 #define OFS_TA3EX0 (0x0020) /* TimerAx Expansion 0 Register */
\r
2574 #define OFS_TA3IV (0x002e) /* TimerAx Interrupt Vector Register */
\r
2577 //*****************************************************************************
\r
2579 //*****************************************************************************
\r
2580 #define TLV_TLV_CHECKSUM (HWREG32(0x00201000)) /* TLV Checksum */
\r
2581 #define TLV_DEVICE_INFO_TAG (HWREG32(0x00201004)) /* Device Info Tag */
\r
2582 #define TLV_DEVICE_INFO_LEN (HWREG32(0x00201008)) /* Device Info Length */
\r
2583 #define TLV_DEVICE_ID (HWREG32(0x0020100C)) /* Device ID */
\r
2584 #define TLV_HWREV (HWREG32(0x00201010)) /* HW Revision */
\r
2585 #define TLV_BCREV (HWREG32(0x00201014)) /* Boot Code Revision */
\r
2586 #define TLV_ROM_DRVLIB_REV (HWREG32(0x00201018)) /* ROM Driver Library Revision */
\r
2587 #define TLV_DIE_REC_TAG (HWREG32(0x0020101C)) /* Die Record Tag */
\r
2588 #define TLV_DIE_REC_LEN (HWREG32(0x00201020)) /* Die Record Length */
\r
2589 #define TLV_DIE_XPOS (HWREG32(0x00201024)) /* Die X-Position */
\r
2590 #define TLV_DIE_YPOS (HWREG32(0x00201028)) /* Die Y-Position */
\r
2591 #define TLV_WAFER_ID (HWREG32(0x0020102C)) /* Wafer ID */
\r
2592 #define TLV_LOT_ID (HWREG32(0x00201030)) /* Lot ID */
\r
2593 #define TLV_RESERVED0 (HWREG32(0x00201034)) /* Reserved */
\r
2594 #define TLV_RESERVED1 (HWREG32(0x00201038)) /* Reserved */
\r
2595 #define TLV_RESERVED2 (HWREG32(0x0020103C)) /* Reserved */
\r
2596 #define TLV_TEST_RESULTS (HWREG32(0x00201040)) /* Test Results */
\r
2597 #define TLV_CS_CAL_TAG (HWREG32(0x00201044)) /* Clock System Calibration Tag */
\r
2598 #define TLV_CS_CAL_LEN (HWREG32(0x00201048)) /* Clock System Calibration Length */
\r
2599 #define TLV_DCOIR_FCAL_RSEL04 (HWREG32(0x0020104C)) /* DCO IR mode: Frequency calibration for DCORSEL 0 to 4 */
\r
2600 #define TLV_DCOIR_FCAL_RSEL5 (HWREG32(0x00201050)) /* DCO IR mode: Frequency calibration for DCORSEL 5 */
\r
2601 #define TLV_DCOIR_MAXPOSTUNE_RSEL04 (HWREG32(0x00201054)) /* DCO IR mode: Max Positive Tune for DCORSEL 0 to 4 */
\r
2602 #define TLV_DCOIR_MAXNEGTUNE_RSEL04 (HWREG32(0x00201058)) /* DCO IR mode: Max Negative Tune for DCORSEL 0 to 4 */
\r
2603 #define TLV_DCOIR_MAXPOSTUNE_RSEL5 (HWREG32(0x0020105C)) /* DCO IR mode: Max Positive Tune for DCORSEL 5 */
\r
2604 #define TLV_DCOIR_MAXNEGTUNE_RSEL5 (HWREG32(0x00201060)) /* DCO IR mode: Max Negative Tune for DCORSEL 5 */
\r
2605 #define TLV_DCOIR_CONSTK_RSEL04 (HWREG32(0x00201064)) /* DCO IR mode: DCO Constant (K) for DCORSEL 0 to 4 */
\r
2606 #define TLV_DCOIR_CONSTK_RSEL5 (HWREG32(0x00201068)) /* DCO IR mode: DCO Constant (K) for DCORSEL 5 */
\r
2607 #define TLV_DCOER_FCAL_RSEL04 (HWREG32(0x0020106C)) /* DCO ER mode: Frequency calibration for DCORSEL 0 to 4 */
\r
2608 #define TLV_DCOER_FCAL_RSEL5 (HWREG32(0x00201070)) /* DCO ER mode: Frequency calibration for DCORSEL 5 */
\r
2609 #define TLV_DCOER_MAXPOSTUNE_RSEL04 (HWREG32(0x00201074)) /* DCO ER mode: Max Positive Tune for DCORSEL 0 to 4 */
\r
2610 #define TLV_DCOER_MAXNEGTUNE_RSEL04 (HWREG32(0x00201078)) /* DCO ER mode: Max Negative Tune for DCORSEL 0 to 4 */
\r
2611 #define TLV_DCOER_MAXPOSTUNE_RSEL5 (HWREG32(0x0020107C)) /* DCO ER mode: Max Positive Tune for DCORSEL 5 */
\r
2612 #define TLV_DCOER_MAXNEGTUNE_RSEL5 (HWREG32(0x00201080)) /* DCO ER mode: Max Negative Tune for DCORSEL 5 */
\r
2613 #define TLV_DCOER_CONSTK_RSEL04 (HWREG32(0x00201084)) /* DCO ER mode: DCO Constant (K) for DCORSEL 0 to 4 */
\r
2614 #define TLV_DCOER_CONSTK_RSEL5 (HWREG32(0x00201088)) /* DCO ER mode: DCO Constant (K) for DCORSEL 5 */
\r
2615 #define TLV_ADC14_CAL_TAG (HWREG32(0x0020108C)) /* ADC14 Calibration Tag */
\r
2616 #define TLV_ADC14_CAL_LEN (HWREG32(0x00201090)) /* ADC14 Calibration Length */
\r
2617 #define TLV_ADC14_GF_EXTREF30C (HWREG32(0x00201094)) /* ADC14 Gain Factor for External Reference 30°C */
\r
2618 #define TLV_ADC14_GF_EXTREF85C (HWREG32(0x00201098)) /* ADC14 Gain Factor for External Reference 85°C */
\r
2619 #define TLV_ADC14_GF_BUF_EXTREF30C (HWREG32(0x0020109C)) /* ADC14 Gain Factor for Buffered External Reference 30°C */
\r
2620 #define TLV_ADC14_GF_BUF_EXTREF85C (HWREG32(0x002010A0)) /* ADC14 Gain Factor for Buffered External Reference 85°C */
\r
2621 #define TLV_ADC14_GF_BUF1P2V_INTREF30C_REFOUT0 (HWREG32(0x002010A4)) /* ADC14 Gain Factor for Buffered 1.2V Internal Reference 30°C (REFOUT = 0) */
\r
2622 #define TLV_ADC14_GF_BUF1P2V_INTREF85C_REFOUT0 (HWREG32(0x002010A8)) /* ADC14 Gain Factor for Buffered 1.2V Internal Reference 85°C (REFOUT = 0) */
\r
2623 #define TLV_ADC14_GF_BUF1P2V_INTREF30C_REFOUT1 (HWREG32(0x002010AC)) /* ADC14 Gain Factor for Buffered 1.2V Internal Reference 30°C (REFOUT = 1) */
\r
2624 #define TLV_ADC14_GF_BUF1P2V_INTREF85C_REFOUT1 (HWREG32(0x002010B0)) /* ADC14 Gain Factor for Buffered 1.2V Internal Reference 85°C (REFOUT = 1) */
\r
2625 #define TLV_ADC14_GF_BUF1P45V_INTREF30C_REFOUT0 (HWREG32(0x002010B4)) /* ADC14 Gain Factor for Buffered 1.45V Internal Reference 30°C (REFOUT = 0) */
\r
2626 #define TLV_ADC14_GF_BUF1P45V_INTREF85C_REFOUT0 (HWREG32(0x002010B8)) /* ADC14 Gain Factor for Buffered 1.45V Internal Reference 85°C (REFOUT = 0) */
\r
2627 #define TLV_ADC14_GF_BUF1P45V_INTREF30C_REFOUT1 (HWREG32(0x002010BC)) /* ADC14 Gain Factor for Buffered 1.45V Internal Reference 30°C (REFOUT = 1) */
\r
2628 #define TLV_ADC14_GF_BUF1P45V_INTREF85C_REFOUT1 (HWREG32(0x002010C0)) /* ADC14 Gain Factor for Buffered 1.45V Internal Reference 85°C (REFOUT = 1) */
\r
2629 #define TLV_ADC14_GF_BUF2P5V_INTREF30C_REFOUT0 (HWREG32(0x002010C4)) /* ADC14 Gain Factor for Buffered 2.5V Internal Reference 30°C (REFOUT = 0) */
\r
2630 #define TLV_ADC14_GF_BUF2P5V_INTREF85C_REFOUT0 (HWREG32(0x002010C8)) /* ADC14 Gain Factor for Buffered 2.5V Internal Reference 85°C (REFOUT = 0) */
\r
2631 #define TLV_ADC14_GF_BUF2P5V_INTREF30C_REFOUT1 (HWREG32(0x002010CC)) /* ADC14 Gain Factor for Buffered 2.5V Internal Reference 30°C (REFOUT = 1) */
\r
2632 #define TLV_ADC14_GF_BUF2P5V_INTREF85C_REFOUT1 (HWREG32(0x002010D0)) /* ADC14 Gain Factor for Buffered 2.5V Internal Reference 85°C (REFOUT = 1) */
\r
2633 #define TLV_ADC14_OFFSET_VRSEL_1 (HWREG32(0x002010D4)) /* ADC14 Offset (ADC14VRSEL = 1h) */
\r
2634 #define TLV_ADC14_OFFSET_VRSEL_E (HWREG32(0x002010D8)) /* ADC14 Offset (ADC14VRSEL = Eh) */
\r
2635 #define TLV_ADC14_REF1P2V_TS30C (HWREG32(0x002010DC)) /* ADC14 1.2V Reference Temp. Sensor 30°C */
\r
2636 #define TLV_ADC14_REF1P2V_TS85C (HWREG32(0x002010E0)) /* ADC14 1.2V Reference Temp. Sensor 85°C */
\r
2637 #define TLV_ADC14_REF1P45V_TS30C (HWREG32(0x002010E4)) /* ADC14 1.45V Reference Temp. Sensor 30°C */
\r
2638 #define TLV_ADC14_REF1P45V_TS85C (HWREG32(0x002010E8)) /* ADC14 1.45V Reference Temp. Sensor 85°C */
\r
2639 #define TLV_ADC14_REF2P5V_TS30C (HWREG32(0x002010EC)) /* ADC14 2.5V Reference Temp. Sensor 30°C */
\r
2640 #define TLV_ADC14_REF2P5V_TS85C (HWREG32(0x002010F0)) /* ADC14 2.5V Reference Temp. Sensor 85°C */
\r
2641 #define TLV_REF_CAL_TAG (HWREG32(0x002010F4)) /* REF Calibration Tag */
\r
2642 #define TLV_REF_CAL_LEN (HWREG32(0x002010F8)) /* REF Calibration Length */
\r
2643 #define TLV_REF_1P2V (HWREG32(0x002010FC)) /* REF 1.2V Reference */
\r
2644 #define TLV_REF_1P45V (HWREG32(0x00201100)) /* REF 1.45V Reference */
\r
2645 #define TLV_REF_2P5V (HWREG32(0x00201104)) /* REF 2.5V Reference */
\r
2646 #define TLV_RANDOM_NUM_TAG (HWREG32(0x00201108)) /* 128-bit Random Number Tag */
\r
2647 #define TLV_RANDOM_NUM_LEN (HWREG32(0x0020110C)) /* 128-bit Random Number Length */
\r
2648 #define TLV_RANDOM_NUM_1 (HWREG32(0x00201110)) /* 32-bit Random Number 1 */
\r
2649 #define TLV_RANDOM_NUM_2 (HWREG32(0x00201114)) /* 32-bit Random Number 2 */
\r
2650 #define TLV_RANDOM_NUM_3 (HWREG32(0x00201118)) /* 32-bit Random Number 3 */
\r
2651 #define TLV_RANDOM_NUM_4 (HWREG32(0x0020111C)) /* 32-bit Random Number 4 */
\r
2652 #define TLV_BSL_CFG_TAG (HWREG32(0x00201120)) /* BSL Configuration Tag */
\r
2653 #define TLV_BSL_CFG_LEN (HWREG32(0x00201124)) /* BSL Configuration Length */
\r
2654 #define TLV_BSL_PERIPHIF_SEL (HWREG32(0x00201128)) /* BSL Peripheral Interface Selection */
\r
2655 #define TLV_BSL_PORTIF_CFG_UART (HWREG32(0x0020112C)) /* BSL Port Interface Configuration for UART */
\r
2656 #define TLV_BSL_PORTIF_CFG_SPI (HWREG32(0x00201130)) /* BSL Port Interface Configuration for SPI */
\r
2657 #define TLV_BSL_PORTIF_CFG_I2C (HWREG32(0x00201134)) /* BSL Port Interface Configuration for I2C */
\r
2658 #define TLV_TLV_END (HWREG32(0x00201138)) /* TLV End Word */
\r
2660 /* Register offsets from TLV_BASE address */
\r
2661 #define OFS_TLV_TLV_CHECKSUM (0x00000000) /* TLV Checksum */
\r
2662 #define OFS_TLV_DEVICE_INFO_TAG (0x00000004) /* Device Info Tag */
\r
2663 #define OFS_TLV_DEVICE_INFO_LEN (0x00000008) /* Device Info Length */
\r
2664 #define OFS_TLV_DEVICE_ID (0x0000000C) /* Device ID */
\r
2665 #define OFS_TLV_HWREV (0x00000010) /* HW Revision */
\r
2666 #define OFS_TLV_BCREV (0x00000014) /* Boot Code Revision */
\r
2667 #define OFS_TLV_ROM_DRVLIB_REV (0x00000018) /* ROM Driver Library Revision */
\r
2668 #define OFS_TLV_DIE_REC_TAG (0x0000001C) /* Die Record Tag */
\r
2669 #define OFS_TLV_DIE_REC_LEN (0x00000020) /* Die Record Length */
\r
2670 #define OFS_TLV_DIE_XPOS (0x00000024) /* Die X-Position */
\r
2671 #define OFS_TLV_DIE_YPOS (0x00000028) /* Die Y-Position */
\r
2672 #define OFS_TLV_WAFER_ID (0x0000002C) /* Wafer ID */
\r
2673 #define OFS_TLV_LOT_ID (0x00000030) /* Lot ID */
\r
2674 #define OFS_TLV_RESERVED0 (0x00000034) /* Reserved */
\r
2675 #define OFS_TLV_RESERVED1 (0x00000038) /* Reserved */
\r
2676 #define OFS_TLV_RESERVED2 (0x0000003c) /* Reserved */
\r
2677 #define OFS_TLV_TEST_RESULTS (0x00000040) /* Test Results */
\r
2678 #define OFS_TLV_CS_CAL_TAG (0x00000044) /* Clock System Calibration Tag */
\r
2679 #define OFS_TLV_CS_CAL_LEN (0x00000048) /* Clock System Calibration Length */
\r
2680 #define OFS_TLV_DCOIR_FCAL_RSEL04 (0x0000004c) /* DCO IR mode: Frequency calibration for DCORSEL 0 to 4 */
\r
2681 #define OFS_TLV_DCOIR_FCAL_RSEL5 (0x00000050) /* DCO IR mode: Frequency calibration for DCORSEL 5 */
\r
2682 #define OFS_TLV_DCOIR_MAXPOSTUNE_RSEL04 (0x00000054) /* DCO IR mode: Max Positive Tune for DCORSEL 0 to 4 */
\r
2683 #define OFS_TLV_DCOIR_MAXNEGTUNE_RSEL04 (0x00000058) /* DCO IR mode: Max Negative Tune for DCORSEL 0 to 4 */
\r
2684 #define OFS_TLV_DCOIR_MAXPOSTUNE_RSEL5 (0x0000005c) /* DCO IR mode: Max Positive Tune for DCORSEL 5 */
\r
2685 #define OFS_TLV_DCOIR_MAXNEGTUNE_RSEL5 (0x00000060) /* DCO IR mode: Max Negative Tune for DCORSEL 5 */
\r
2686 #define OFS_TLV_DCOIR_CONSTK_RSEL04 (0x00000064) /* DCO IR mode: DCO Constant (K) for DCORSEL 0 to 4 */
\r
2687 #define OFS_TLV_DCOIR_CONSTK_RSEL5 (0x00000068) /* DCO IR mode: DCO Constant (K) for DCORSEL 5 */
\r
2688 #define OFS_TLV_DCOER_FCAL_RSEL04 (0x0000006c) /* DCO ER mode: Frequency calibration for DCORSEL 0 to 4 */
\r
2689 #define OFS_TLV_DCOER_FCAL_RSEL5 (0x00000070) /* DCO ER mode: Frequency calibration for DCORSEL 5 */
\r
2690 #define OFS_TLV_DCOER_MAXPOSTUNE_RSEL04 (0x00000074) /* DCO ER mode: Max Positive Tune for DCORSEL 0 to 4 */
\r
2691 #define OFS_TLV_DCOER_MAXNEGTUNE_RSEL04 (0x00000078) /* DCO ER mode: Max Negative Tune for DCORSEL 0 to 4 */
\r
2692 #define OFS_TLV_DCOER_MAXPOSTUNE_RSEL5 (0x0000007c) /* DCO ER mode: Max Positive Tune for DCORSEL 5 */
\r
2693 #define OFS_TLV_DCOER_MAXNEGTUNE_RSEL5 (0x00000080) /* DCO ER mode: Max Negative Tune for DCORSEL 5 */
\r
2694 #define OFS_TLV_DCOER_CONSTK_RSEL04 (0x00000084) /* DCO ER mode: DCO Constant (K) for DCORSEL 0 to 4 */
\r
2695 #define OFS_TLV_DCOER_CONSTK_RSEL5 (0x00000088) /* DCO ER mode: DCO Constant (K) for DCORSEL 5 */
\r
2696 #define OFS_TLV_ADC14_CAL_TAG (0x0000008C) /* ADC14 Calibration Tag */
\r
2697 #define OFS_TLV_ADC14_CAL_LEN (0x00000090) /* ADC14 Calibration Length */
\r
2698 #define OFS_TLV_ADC14_GF_EXTREF30C (0x00000094) /* ADC14 Gain Factor for External Reference 30°C */
\r
2699 #define OFS_TLV_ADC14_GF_EXTREF85C (0x00000098) /* ADC14 Gain Factor for External Reference 85°C */
\r
2700 #define OFS_TLV_ADC14_GF_BUF_EXTREF30C (0x0000009C) /* ADC14 Gain Factor for Buffered External Reference 30°C */
\r
2701 #define OFS_TLV_ADC14_GF_BUF_EXTREF85C (0x000000A0) /* ADC14 Gain Factor for Buffered External Reference 85°C */
\r
2702 #define OFS_TLV_ADC14_GF_BUF1P2V_INTREF30C_REFOUT0 (0x000000A4) /* ADC14 Gain Factor for Buffered 1.2V Internal Reference 30°C (REFOUT = 0) */
\r
2703 #define OFS_TLV_ADC14_GF_BUF1P2V_INTREF85C_REFOUT0 (0x000000A8) /* ADC14 Gain Factor for Buffered 1.2V Internal Reference 85°C (REFOUT = 0) */
\r
2704 #define OFS_TLV_ADC14_GF_BUF1P2V_INTREF30C_REFOUT1 (0x000000AC) /* ADC14 Gain Factor for Buffered 1.2V Internal Reference 30°C (REFOUT = 1) */
\r
2705 #define OFS_TLV_ADC14_GF_BUF1P2V_INTREF85C_REFOUT1 (0x000000B0) /* ADC14 Gain Factor for Buffered 1.2V Internal Reference 85°C (REFOUT = 1) */
\r
2706 #define OFS_TLV_ADC14_GF_BUF1P45V_INTREF30C_REFOUT0 (0x000000B4) /* ADC14 Gain Factor for Buffered 1.45V Internal Reference 30°C (REFOUT = 0) */
\r
2707 #define OFS_TLV_ADC14_GF_BUF1P45V_INTREF85C_REFOUT0 (0x000000B8) /* ADC14 Gain Factor for Buffered 1.45V Internal Reference 85°C (REFOUT = 0) */
\r
2708 #define OFS_TLV_ADC14_GF_BUF1P45V_INTREF30C_REFOUT1 (0x000000BC) /* ADC14 Gain Factor for Buffered 1.45V Internal Reference 30°C (REFOUT = 1) */
\r
2709 #define OFS_TLV_ADC14_GF_BUF1P45V_INTREF85C_REFOUT1 (0x000000C0) /* ADC14 Gain Factor for Buffered 1.45V Internal Reference 85°C (REFOUT = 1) */
\r
2710 #define OFS_TLV_ADC14_GF_BUF2P5V_INTREF30C_REFOUT0 (0x000000C4) /* ADC14 Gain Factor for Buffered 2.5V Internal Reference 30°C (REFOUT = 0) */
\r
2711 #define OFS_TLV_ADC14_GF_BUF2P5V_INTREF85C_REFOUT0 (0x000000C8) /* ADC14 Gain Factor for Buffered 2.5V Internal Reference 85°C (REFOUT = 0) */
\r
2712 #define OFS_TLV_ADC14_GF_BUF2P5V_INTREF30C_REFOUT1 (0x000000CC) /* ADC14 Gain Factor for Buffered 2.5V Internal Reference 30°C (REFOUT = 1) */
\r
2713 #define OFS_TLV_ADC14_GF_BUF2P5V_INTREF85C_REFOUT1 (0x000000D0) /* ADC14 Gain Factor for Buffered 2.5V Internal Reference 85°C (REFOUT = 1) */
\r
2714 #define OFS_TLV_ADC14_OFFSET_VRSEL_1 (0x000000D4) /* ADC14 Offset (ADC14VRSEL = 1h) */
\r
2715 #define OFS_TLV_ADC14_OFFSET_VRSEL_E (0x000000D8) /* ADC14 Offset (ADC14VRSEL = Eh) */
\r
2716 #define OFS_TLV_ADC14_REF1P2V_TS30C (0x000000DC) /* ADC14 1.2V Reference Temp. Sensor 30°C */
\r
2717 #define OFS_TLV_ADC14_REF1P2V_TS85C (0x000000E0) /* ADC14 1.2V Reference Temp. Sensor 85°C */
\r
2718 #define OFS_TLV_ADC14_REF1P45V_TS30C (0x000000E4) /* ADC14 1.45V Reference Temp. Sensor 30°C */
\r
2719 #define OFS_TLV_ADC14_REF1P45V_TS85C (0x000000E8) /* ADC14 1.45V Reference Temp. Sensor 85°C */
\r
2720 #define OFS_TLV_ADC14_REF2P5V_TS30C (0x000000EC) /* ADC14 2.5V Reference Temp. Sensor 30°C */
\r
2721 #define OFS_TLV_ADC14_REF2P5V_TS85C (0x000000F0) /* ADC14 2.5V Reference Temp. Sensor 85°C */
\r
2722 #define OFS_TLV_REF_CAL_TAG (0x000000F4) /* REF Calibration Tag */
\r
2723 #define OFS_TLV_REF_CAL_LEN (0x000000F8) /* REF Calibration Length */
\r
2724 #define OFS_TLV_REF_1P2V (0x000000FC) /* REF 1.2V Reference */
\r
2725 #define OFS_TLV_REF_1P45V (0x00000100) /* REF 1.45V Reference */
\r
2726 #define OFS_TLV_REF_2P5V (0x00000104) /* REF 2.5V Reference */
\r
2727 #define OFS_TLV_RANDOM_NUM_TAG (0x00000108) /* 128-bit Random Number Tag */
\r
2728 #define OFS_TLV_RANDOM_NUM_LEN (0x0000010C) /* 128-bit Random Number Length */
\r
2729 #define OFS_TLV_RANDOM_NUM_1 (0x00000110) /* 32-bit Random Number 1 */
\r
2730 #define OFS_TLV_RANDOM_NUM_2 (0x00000114) /* 32-bit Random Number 2 */
\r
2731 #define OFS_TLV_RANDOM_NUM_3 (0x00000118) /* 32-bit Random Number 3 */
\r
2732 #define OFS_TLV_RANDOM_NUM_4 (0x0000011C) /* 32-bit Random Number 4 */
\r
2733 #define OFS_TLV_BSL_CFG_TAG (0x00000120) /* BSL Configuration Tag */
\r
2734 #define OFS_TLV_BSL_CFG_LEN (0x00000124) /* BSL Configuration Length */
\r
2735 #define OFS_TLV_BSL_PERIPHIF_SEL (0x00000128) /* BSL Peripheral Interface Selection */
\r
2736 #define OFS_TLV_BSL_PORTIF_CFG_UART (0x0000012C) /* BSL Port Interface Configuration for UART */
\r
2737 #define OFS_TLV_BSL_PORTIF_CFG_SPI (0x00000130) /* BSL Port Interface Configuration for SPI */
\r
2738 #define OFS_TLV_BSL_PORTIF_CFG_I2C (0x00000134) /* BSL Port Interface Configuration for I2C */
\r
2739 #define OFS_TLV_TLV_END (0x00000138) /* TLV End Word */
\r
2742 //*****************************************************************************
\r
2743 // WDT_A Registers
\r
2744 //*****************************************************************************
\r
2745 #define WDTCTL (HWREG16(0x4000480C)) /* Watchdog Timer Control Register */
\r
2747 /* Register offsets from WDT_A_BASE address */
\r
2748 #define OFS_WDTCTL (0x000c) /* Watchdog Timer Control Register */
\r
2751 //*****************************************************************************
\r
2752 // CMSIS-format peripheral registers
\r
2753 //*****************************************************************************
\r
2755 //*****************************************************************************
\r
2756 // ADC14 Registers
\r
2757 //*****************************************************************************
\r
2759 union { /* ADC14CTL0 Register */
\r
2761 struct { /* ADC14CTL0 Bits */
\r
2762 __IO uint32_t bSC : 1; /* ADC14 start conversion */
\r
2763 __IO uint32_t bENC : 1; /* ADC14 enable conversion */
\r
2764 __I uint32_t bRESERVED0 : 2; /* Reserved */
\r
2765 __IO uint32_t bON : 1; /* ADC14 on */
\r
2766 __I uint32_t bRESERVED1 : 2; /* Reserved */
\r
2767 __IO uint32_t bMSC : 1; /* ADC14 multiple sample and conversion */
\r
2768 __IO uint32_t bSHT0 : 4; /* ADC14 sample-and-hold time */
\r
2769 __IO uint32_t bSHT1 : 4; /* ADC14 sample-and-hold time */
\r
2770 __I uint32_t bBUSY : 1; /* ADC14 busy */
\r
2771 __IO uint32_t bCONSEQ : 2; /* ADC14 conversion sequence mode select */
\r
2772 __IO uint32_t bSSEL : 3; /* ADC14 clock source select */
\r
2773 __IO uint32_t bDIV : 3; /* ADC14 clock divider */
\r
2774 __IO uint32_t bISSH : 1; /* ADC14 invert signal sample-and-hold */
\r
2775 __IO uint32_t bSHP : 1; /* ADC14 sample-and-hold pulse-mode select */
\r
2776 __IO uint32_t bSHS : 3; /* ADC14 sample-and-hold source select */
\r
2777 __IO uint32_t bPDIV : 2; /* ADC14 predivider */
\r
2780 union { /* ADC14CTL1 Register */
\r
2782 struct { /* ADC14CTL1 Bits */
\r
2783 __IO uint32_t bPWRMD : 2; /* ADC14 power modes */
\r
2784 __IO uint32_t bREFBURST : 1; /* ADC14 reference buffer burst */
\r
2785 __IO uint32_t bDF : 1; /* ADC14 data read-back format */
\r
2786 __IO uint32_t bRES : 2; /* ADC14 resolution */
\r
2787 __I uint32_t bRESERVED0 : 10; /* Reserved */
\r
2788 __IO uint32_t bCSTARTADD : 5; /* ADC14 conversion start address */
\r
2789 __I uint32_t bRESERVED1 : 1; /* Reserved */
\r
2790 __IO uint32_t bBATMAP : 1; /* Controls 1/2 AVCC ADC input channel selection */
\r
2791 __IO uint32_t bTCMAP : 1; /* Controls temperature sensor ADC input channel selection */
\r
2792 __IO uint32_t bCH0MAP : 1; /* Controls internal channel 0 selection to ADC input channel MAX-2 */
\r
2793 __IO uint32_t bCH1MAP : 1; /* Controls internal channel 1 selection to ADC input channel MAX-3 */
\r
2794 __IO uint32_t bCH2MAP : 1; /* Controls internal channel 2 selection to ADC input channel MAX-4 */
\r
2795 __IO uint32_t bCH3MAP : 1; /* Controls internal channel 3 selection to ADC input channel MAX-5 */
\r
2796 __I uint32_t bRESERVED2 : 4; /* Reserved */
\r
2799 union { /* ADC14LO0 Register */
\r
2801 struct { /* ADC14LO0 Bits */
\r
2802 __IO uint32_t bLO0 : 16; /* Low threshold 0 */
\r
2803 __I uint32_t bRESERVED0 : 16; /* Reserved */
\r
2806 union { /* ADC14HI0 Register */
\r
2808 struct { /* ADC14HI0 Bits */
\r
2809 __IO uint32_t bHI0 : 16; /* High threshold 0 */
\r
2810 __I uint32_t bRESERVED0 : 16; /* Reserved */
\r
2813 union { /* ADC14LO1 Register */
\r
2815 struct { /* ADC14LO1 Bits */
\r
2816 __IO uint32_t bLO1 : 16; /* Low threshold 1 */
\r
2817 __I uint32_t bRESERVED0 : 16; /* Reserved */
\r
2820 union { /* ADC14HI1 Register */
\r
2822 struct { /* ADC14HI1 Bits */
\r
2823 __IO uint32_t bHI1 : 16; /* High threshold 1 */
\r
2824 __I uint32_t bRESERVED0 : 16; /* Reserved */
\r
2827 union { /* ADC14MCTL0 Register */
\r
2829 struct { /* ADC14MCTL0 Bits */
\r
2830 __IO uint32_t bINCH : 5; /* Input channel select */
\r
2831 __I uint32_t bRESERVED0 : 2; /* Reserved */
\r
2832 __IO uint32_t bEOS : 1; /* End of sequence */
\r
2833 __IO uint32_t bVRSEL : 4; /* Selects combinations of V(R+) and V(R-) sources */
\r
2834 __I uint32_t bRESERVED1 : 1; /* Reserved */
\r
2835 __IO uint32_t bDIF : 1; /* Differential mode */
\r
2836 __IO uint32_t bWINC : 1; /* Comparator window enable */
\r
2837 __IO uint32_t bWINCTH : 1; /* Window comparator threshold register selection */
\r
2838 __I uint32_t bRESERVED2 : 16; /* Reserved */
\r
2841 union { /* ADC14MCTL1 Register */
\r
2843 struct { /* ADC14MCTL1 Bits */
\r
2844 __IO uint32_t bINCH : 5; /* Input channel select */
\r
2845 __I uint32_t bRESERVED0 : 2; /* Reserved */
\r
2846 __IO uint32_t bEOS : 1; /* End of sequence */
\r
2847 __IO uint32_t bVRSEL : 4; /* Selects combinations of V(R+) and V(R-) sources */
\r
2848 __I uint32_t bRESERVED1 : 1; /* Reserved */
\r
2849 __IO uint32_t bDIF : 1; /* Differential mode */
\r
2850 __IO uint32_t bWINC : 1; /* Comparator window enable */
\r
2851 __IO uint32_t bWINCTH : 1; /* Window comparator threshold register selection */
\r
2852 __I uint32_t bRESERVED2 : 16; /* Reserved */
\r
2855 union { /* ADC14MCTL2 Register */
\r
2857 struct { /* ADC14MCTL2 Bits */
\r
2858 __IO uint32_t bINCH : 5; /* Input channel select */
\r
2859 __I uint32_t bRESERVED0 : 2; /* Reserved */
\r
2860 __IO uint32_t bEOS : 1; /* End of sequence */
\r
2861 __IO uint32_t bVRSEL : 4; /* Selects combinations of V(R+) and V(R-) sources */
\r
2862 __I uint32_t bRESERVED1 : 1; /* Reserved */
\r
2863 __IO uint32_t bDIF : 1; /* Differential mode */
\r
2864 __IO uint32_t bWINC : 1; /* Comparator window enable */
\r
2865 __IO uint32_t bWINCTH : 1; /* Window comparator threshold register selection */
\r
2866 __I uint32_t bRESERVED2 : 16; /* Reserved */
\r
2869 union { /* ADC14MCTL3 Register */
\r
2871 struct { /* ADC14MCTL3 Bits */
\r
2872 __IO uint32_t bINCH : 5; /* Input channel select */
\r
2873 __I uint32_t bRESERVED0 : 2; /* Reserved */
\r
2874 __IO uint32_t bEOS : 1; /* End of sequence */
\r
2875 __IO uint32_t bVRSEL : 4; /* Selects combinations of V(R+) and V(R-) sources */
\r
2876 __I uint32_t bRESERVED1 : 1; /* Reserved */
\r
2877 __IO uint32_t bDIF : 1; /* Differential mode */
\r
2878 __IO uint32_t bWINC : 1; /* Comparator window enable */
\r
2879 __IO uint32_t bWINCTH : 1; /* Window comparator threshold register selection */
\r
2880 __I uint32_t bRESERVED2 : 16; /* Reserved */
\r
2883 union { /* ADC14MCTL4 Register */
\r
2885 struct { /* ADC14MCTL4 Bits */
\r
2886 __IO uint32_t bINCH : 5; /* Input channel select */
\r
2887 __I uint32_t bRESERVED0 : 2; /* Reserved */
\r
2888 __IO uint32_t bEOS : 1; /* End of sequence */
\r
2889 __IO uint32_t bVRSEL : 4; /* Selects combinations of V(R+) and V(R-) sources */
\r
2890 __I uint32_t bRESERVED1 : 1; /* Reserved */
\r
2891 __IO uint32_t bDIF : 1; /* Differential mode */
\r
2892 __IO uint32_t bWINC : 1; /* Comparator window enable */
\r
2893 __IO uint32_t bWINCTH : 1; /* Window comparator threshold register selection */
\r
2894 __I uint32_t bRESERVED2 : 16; /* Reserved */
\r
2897 union { /* ADC14MCTL5 Register */
\r
2899 struct { /* ADC14MCTL5 Bits */
\r
2900 __IO uint32_t bINCH : 5; /* Input channel select */
\r
2901 __I uint32_t bRESERVED0 : 2; /* Reserved */
\r
2902 __IO uint32_t bEOS : 1; /* End of sequence */
\r
2903 __IO uint32_t bVRSEL : 4; /* Selects combinations of V(R+) and V(R-) sources */
\r
2904 __I uint32_t bRESERVED1 : 1; /* Reserved */
\r
2905 __IO uint32_t bDIF : 1; /* Differential mode */
\r
2906 __IO uint32_t bWINC : 1; /* Comparator window enable */
\r
2907 __IO uint32_t bWINCTH : 1; /* Window comparator threshold register selection */
\r
2908 __I uint32_t bRESERVED2 : 16; /* Reserved */
\r
2911 union { /* ADC14MCTL6 Register */
\r
2913 struct { /* ADC14MCTL6 Bits */
\r
2914 __IO uint32_t bINCH : 5; /* Input channel select */
\r
2915 __I uint32_t bRESERVED0 : 2; /* Reserved */
\r
2916 __IO uint32_t bEOS : 1; /* End of sequence */
\r
2917 __IO uint32_t bVRSEL : 4; /* Selects combinations of V(R+) and V(R-) sources */
\r
2918 __I uint32_t bRESERVED1 : 1; /* Reserved */
\r
2919 __IO uint32_t bDIF : 1; /* Differential mode */
\r
2920 __IO uint32_t bWINC : 1; /* Comparator window enable */
\r
2921 __IO uint32_t bWINCTH : 1; /* Window comparator threshold register selection */
\r
2922 __I uint32_t bRESERVED2 : 16; /* Reserved */
\r
2925 union { /* ADC14MCTL7 Register */
\r
2927 struct { /* ADC14MCTL7 Bits */
\r
2928 __IO uint32_t bINCH : 5; /* Input channel select */
\r
2929 __I uint32_t bRESERVED0 : 2; /* Reserved */
\r
2930 __IO uint32_t bEOS : 1; /* End of sequence */
\r
2931 __IO uint32_t bVRSEL : 4; /* Selects combinations of V(R+) and V(R-) sources */
\r
2932 __I uint32_t bRESERVED1 : 1; /* Reserved */
\r
2933 __IO uint32_t bDIF : 1; /* Differential mode */
\r
2934 __IO uint32_t bWINC : 1; /* Comparator window enable */
\r
2935 __IO uint32_t bWINCTH : 1; /* Window comparator threshold register selection */
\r
2936 __I uint32_t bRESERVED2 : 16; /* Reserved */
\r
2939 union { /* ADC14MCTL8 Register */
\r
2941 struct { /* ADC14MCTL8 Bits */
\r
2942 __IO uint32_t bINCH : 5; /* Input channel select */
\r
2943 __I uint32_t bRESERVED0 : 2; /* Reserved */
\r
2944 __IO uint32_t bEOS : 1; /* End of sequence */
\r
2945 __IO uint32_t bVRSEL : 4; /* Selects combinations of V(R+) and V(R-) sources */
\r
2946 __I uint32_t bRESERVED1 : 1; /* Reserved */
\r
2947 __IO uint32_t bDIF : 1; /* Differential mode */
\r
2948 __IO uint32_t bWINC : 1; /* Comparator window enable */
\r
2949 __IO uint32_t bWINCTH : 1; /* Window comparator threshold register selection */
\r
2950 __I uint32_t bRESERVED2 : 16; /* Reserved */
\r
2953 union { /* ADC14MCTL9 Register */
\r
2955 struct { /* ADC14MCTL9 Bits */
\r
2956 __IO uint32_t bINCH : 5; /* Input channel select */
\r
2957 __I uint32_t bRESERVED0 : 2; /* Reserved */
\r
2958 __IO uint32_t bEOS : 1; /* End of sequence */
\r
2959 __IO uint32_t bVRSEL : 4; /* Selects combinations of V(R+) and V(R-) sources */
\r
2960 __I uint32_t bRESERVED1 : 1; /* Reserved */
\r
2961 __IO uint32_t bDIF : 1; /* Differential mode */
\r
2962 __IO uint32_t bWINC : 1; /* Comparator window enable */
\r
2963 __IO uint32_t bWINCTH : 1; /* Window comparator threshold register selection */
\r
2964 __I uint32_t bRESERVED2 : 16; /* Reserved */
\r
2967 union { /* ADC14MCTL10 Register */
\r
2969 struct { /* ADC14MCTL10 Bits */
\r
2970 __IO uint32_t bINCH : 5; /* Input channel select */
\r
2971 __I uint32_t bRESERVED0 : 2; /* Reserved */
\r
2972 __IO uint32_t bEOS : 1; /* End of sequence */
\r
2973 __IO uint32_t bVRSEL : 4; /* Selects combinations of V(R+) and V(R-) sources */
\r
2974 __I uint32_t bRESERVED1 : 1; /* Reserved */
\r
2975 __IO uint32_t bDIF : 1; /* Differential mode */
\r
2976 __IO uint32_t bWINC : 1; /* Comparator window enable */
\r
2977 __IO uint32_t bWINCTH : 1; /* Window comparator threshold register selection */
\r
2978 __I uint32_t bRESERVED2 : 16; /* Reserved */
\r
2981 union { /* ADC14MCTL11 Register */
\r
2983 struct { /* ADC14MCTL11 Bits */
\r
2984 __IO uint32_t bINCH : 5; /* Input channel select */
\r
2985 __I uint32_t bRESERVED0 : 2; /* Reserved */
\r
2986 __IO uint32_t bEOS : 1; /* End of sequence */
\r
2987 __IO uint32_t bVRSEL : 4; /* Selects combinations of V(R+) and V(R-) sources */
\r
2988 __I uint32_t bRESERVED1 : 1; /* Reserved */
\r
2989 __IO uint32_t bDIF : 1; /* Differential mode */
\r
2990 __IO uint32_t bWINC : 1; /* Comparator window enable */
\r
2991 __IO uint32_t bWINCTH : 1; /* Window comparator threshold register selection */
\r
2992 __I uint32_t bRESERVED2 : 16; /* Reserved */
\r
2995 union { /* ADC14MCTL12 Register */
\r
2997 struct { /* ADC14MCTL12 Bits */
\r
2998 __IO uint32_t bINCH : 5; /* Input channel select */
\r
2999 __I uint32_t bRESERVED0 : 2; /* Reserved */
\r
3000 __IO uint32_t bEOS : 1; /* End of sequence */
\r
3001 __IO uint32_t bVRSEL : 4; /* Selects combinations of V(R+) and V(R-) sources */
\r
3002 __I uint32_t bRESERVED1 : 1; /* Reserved */
\r
3003 __IO uint32_t bDIF : 1; /* Differential mode */
\r
3004 __IO uint32_t bWINC : 1; /* Comparator window enable */
\r
3005 __IO uint32_t bWINCTH : 1; /* Window comparator threshold register selection */
\r
3006 __I uint32_t bRESERVED2 : 16; /* Reserved */
\r
3009 union { /* ADC14MCTL13 Register */
\r
3011 struct { /* ADC14MCTL13 Bits */
\r
3012 __IO uint32_t bINCH : 5; /* Input channel select */
\r
3013 __I uint32_t bRESERVED0 : 2; /* Reserved */
\r
3014 __IO uint32_t bEOS : 1; /* End of sequence */
\r
3015 __IO uint32_t bVRSEL : 4; /* Selects combinations of V(R+) and V(R-) sources */
\r
3016 __I uint32_t bRESERVED1 : 1; /* Reserved */
\r
3017 __IO uint32_t bDIF : 1; /* Differential mode */
\r
3018 __IO uint32_t bWINC : 1; /* Comparator window enable */
\r
3019 __IO uint32_t bWINCTH : 1; /* Window comparator threshold register selection */
\r
3020 __I uint32_t bRESERVED2 : 16; /* Reserved */
\r
3023 union { /* ADC14MCTL14 Register */
\r
3025 struct { /* ADC14MCTL14 Bits */
\r
3026 __IO uint32_t bINCH : 5; /* Input channel select */
\r
3027 __I uint32_t bRESERVED0 : 2; /* Reserved */
\r
3028 __IO uint32_t bEOS : 1; /* End of sequence */
\r
3029 __IO uint32_t bVRSEL : 4; /* Selects combinations of V(R+) and V(R-) sources */
\r
3030 __I uint32_t bRESERVED1 : 1; /* Reserved */
\r
3031 __IO uint32_t bDIF : 1; /* Differential mode */
\r
3032 __IO uint32_t bWINC : 1; /* Comparator window enable */
\r
3033 __IO uint32_t bWINCTH : 1; /* Window comparator threshold register selection */
\r
3034 __I uint32_t bRESERVED2 : 16; /* Reserved */
\r
3037 union { /* ADC14MCTL15 Register */
\r
3039 struct { /* ADC14MCTL15 Bits */
\r
3040 __IO uint32_t bINCH : 5; /* Input channel select */
\r
3041 __I uint32_t bRESERVED0 : 2; /* Reserved */
\r
3042 __IO uint32_t bEOS : 1; /* End of sequence */
\r
3043 __IO uint32_t bVRSEL : 4; /* Selects combinations of V(R+) and V(R-) sources */
\r
3044 __I uint32_t bRESERVED1 : 1; /* Reserved */
\r
3045 __IO uint32_t bDIF : 1; /* Differential mode */
\r
3046 __IO uint32_t bWINC : 1; /* Comparator window enable */
\r
3047 __IO uint32_t bWINCTH : 1; /* Window comparator threshold register selection */
\r
3048 __I uint32_t bRESERVED2 : 16; /* Reserved */
\r
3051 union { /* ADC14MCTL16 Register */
\r
3053 struct { /* ADC14MCTL16 Bits */
\r
3054 __IO uint32_t bINCH : 5; /* Input channel select */
\r
3055 __I uint32_t bRESERVED0 : 2; /* Reserved */
\r
3056 __IO uint32_t bEOS : 1; /* End of sequence */
\r
3057 __IO uint32_t bVRSEL : 4; /* Selects combinations of V(R+) and V(R-) sources */
\r
3058 __I uint32_t bRESERVED1 : 1; /* Reserved */
\r
3059 __IO uint32_t bDIF : 1; /* Differential mode */
\r
3060 __IO uint32_t bWINC : 1; /* Comparator window enable */
\r
3061 __IO uint32_t bWINCTH : 1; /* Window comparator threshold register selection */
\r
3062 __I uint32_t bRESERVED2 : 16; /* Reserved */
\r
3065 union { /* ADC14MCTL17 Register */
\r
3067 struct { /* ADC14MCTL17 Bits */
\r
3068 __IO uint32_t bINCH : 5; /* Input channel select */
\r
3069 __I uint32_t bRESERVED0 : 2; /* Reserved */
\r
3070 __IO uint32_t bEOS : 1; /* End of sequence */
\r
3071 __IO uint32_t bVRSEL : 4; /* Selects combinations of V(R+) and V(R-) sources */
\r
3072 __I uint32_t bRESERVED1 : 1; /* Reserved */
\r
3073 __IO uint32_t bDIF : 1; /* Differential mode */
\r
3074 __IO uint32_t bWINC : 1; /* Comparator window enable */
\r
3075 __IO uint32_t bWINCTH : 1; /* Window comparator threshold register selection */
\r
3076 __I uint32_t bRESERVED2 : 16; /* Reserved */
\r
3079 union { /* ADC14MCTL18 Register */
\r
3081 struct { /* ADC14MCTL18 Bits */
\r
3082 __IO uint32_t bINCH : 5; /* Input channel select */
\r
3083 __I uint32_t bRESERVED0 : 2; /* Reserved */
\r
3084 __IO uint32_t bEOS : 1; /* End of sequence */
\r
3085 __IO uint32_t bVRSEL : 4; /* Selects combinations of V(R+) and V(R-) sources */
\r
3086 __I uint32_t bRESERVED1 : 1; /* Reserved */
\r
3087 __IO uint32_t bDIF : 1; /* Differential mode */
\r
3088 __IO uint32_t bWINC : 1; /* Comparator window enable */
\r
3089 __IO uint32_t bWINCTH : 1; /* Window comparator threshold register selection */
\r
3090 __I uint32_t bRESERVED2 : 16; /* Reserved */
\r
3093 union { /* ADC14MCTL19 Register */
\r
3095 struct { /* ADC14MCTL19 Bits */
\r
3096 __IO uint32_t bINCH : 5; /* Input channel select */
\r
3097 __I uint32_t bRESERVED0 : 2; /* Reserved */
\r
3098 __IO uint32_t bEOS : 1; /* End of sequence */
\r
3099 __IO uint32_t bVRSEL : 4; /* Selects combinations of V(R+) and V(R-) sources */
\r
3100 __I uint32_t bRESERVED1 : 1; /* Reserved */
\r
3101 __IO uint32_t bDIF : 1; /* Differential mode */
\r
3102 __IO uint32_t bWINC : 1; /* Comparator window enable */
\r
3103 __IO uint32_t bWINCTH : 1; /* Window comparator threshold register selection */
\r
3104 __I uint32_t bRESERVED2 : 16; /* Reserved */
\r
3107 union { /* ADC14MCTL20 Register */
\r
3109 struct { /* ADC14MCTL20 Bits */
\r
3110 __IO uint32_t bINCH : 5; /* Input channel select */
\r
3111 __I uint32_t bRESERVED0 : 2; /* Reserved */
\r
3112 __IO uint32_t bEOS : 1; /* End of sequence */
\r
3113 __IO uint32_t bVRSEL : 4; /* Selects combinations of V(R+) and V(R-) sources */
\r
3114 __I uint32_t bRESERVED1 : 1; /* Reserved */
\r
3115 __IO uint32_t bDIF : 1; /* Differential mode */
\r
3116 __IO uint32_t bWINC : 1; /* Comparator window enable */
\r
3117 __IO uint32_t bWINCTH : 1; /* Window comparator threshold register selection */
\r
3118 __I uint32_t bRESERVED2 : 16; /* Reserved */
\r
3121 union { /* ADC14MCTL21 Register */
\r
3123 struct { /* ADC14MCTL21 Bits */
\r
3124 __IO uint32_t bINCH : 5; /* Input channel select */
\r
3125 __I uint32_t bRESERVED0 : 2; /* Reserved */
\r
3126 __IO uint32_t bEOS : 1; /* End of sequence */
\r
3127 __IO uint32_t bVRSEL : 4; /* Selects combinations of V(R+) and V(R-) sources */
\r
3128 __I uint32_t bRESERVED1 : 1; /* Reserved */
\r
3129 __IO uint32_t bDIF : 1; /* Differential mode */
\r
3130 __IO uint32_t bWINC : 1; /* Comparator window enable */
\r
3131 __IO uint32_t bWINCTH : 1; /* Window comparator threshold register selection */
\r
3132 __I uint32_t bRESERVED2 : 16; /* Reserved */
\r
3135 union { /* ADC14MCTL22 Register */
\r
3137 struct { /* ADC14MCTL22 Bits */
\r
3138 __IO uint32_t bINCH : 5; /* Input channel select */
\r
3139 __I uint32_t bRESERVED0 : 2; /* Reserved */
\r
3140 __IO uint32_t bEOS : 1; /* End of sequence */
\r
3141 __IO uint32_t bVRSEL : 4; /* Selects combinations of V(R+) and V(R-) sources */
\r
3142 __I uint32_t bRESERVED1 : 1; /* Reserved */
\r
3143 __IO uint32_t bDIF : 1; /* Differential mode */
\r
3144 __IO uint32_t bWINC : 1; /* Comparator window enable */
\r
3145 __IO uint32_t bWINCTH : 1; /* Window comparator threshold register selection */
\r
3146 __I uint32_t bRESERVED2 : 16; /* Reserved */
\r
3149 union { /* ADC14MCTL23 Register */
\r
3151 struct { /* ADC14MCTL23 Bits */
\r
3152 __IO uint32_t bINCH : 5; /* Input channel select */
\r
3153 __I uint32_t bRESERVED0 : 2; /* Reserved */
\r
3154 __IO uint32_t bEOS : 1; /* End of sequence */
\r
3155 __IO uint32_t bVRSEL : 4; /* Selects combinations of V(R+) and V(R-) sources */
\r
3156 __I uint32_t bRESERVED1 : 1; /* Reserved */
\r
3157 __IO uint32_t bDIF : 1; /* Differential mode */
\r
3158 __IO uint32_t bWINC : 1; /* Comparator window enable */
\r
3159 __IO uint32_t bWINCTH : 1; /* Window comparator threshold register selection */
\r
3160 __I uint32_t bRESERVED2 : 16; /* Reserved */
\r
3163 union { /* ADC14MCTL24 Register */
\r
3165 struct { /* ADC14MCTL24 Bits */
\r
3166 __IO uint32_t bINCH : 5; /* Input channel select */
\r
3167 __I uint32_t bRESERVED0 : 2; /* Reserved */
\r
3168 __IO uint32_t bEOS : 1; /* End of sequence */
\r
3169 __IO uint32_t bVRSEL : 4; /* Selects combinations of V(R+) and V(R-) sources */
\r
3170 __I uint32_t bRESERVED1 : 1; /* Reserved */
\r
3171 __IO uint32_t bDIF : 1; /* Differential mode */
\r
3172 __IO uint32_t bWINC : 1; /* Comparator window enable */
\r
3173 __IO uint32_t bWINCTH : 1; /* Window comparator threshold register selection */
\r
3174 __I uint32_t bRESERVED2 : 16; /* Reserved */
\r
3177 union { /* ADC14MCTL25 Register */
\r
3179 struct { /* ADC14MCTL25 Bits */
\r
3180 __IO uint32_t bINCH : 5; /* Input channel select */
\r
3181 __I uint32_t bRESERVED0 : 2; /* Reserved */
\r
3182 __IO uint32_t bEOS : 1; /* End of sequence */
\r
3183 __IO uint32_t bVRSEL : 4; /* Selects combinations of V(R+) and V(R-) sources */
\r
3184 __I uint32_t bRESERVED1 : 1; /* Reserved */
\r
3185 __IO uint32_t bDIF : 1; /* Differential mode */
\r
3186 __IO uint32_t bWINC : 1; /* Comparator window enable */
\r
3187 __IO uint32_t bWINCTH : 1; /* Window comparator threshold register selection */
\r
3188 __I uint32_t bRESERVED2 : 16; /* Reserved */
\r
3191 union { /* ADC14MCTL26 Register */
\r
3193 struct { /* ADC14MCTL26 Bits */
\r
3194 __IO uint32_t bINCH : 5; /* Input channel select */
\r
3195 __I uint32_t bRESERVED0 : 2; /* Reserved */
\r
3196 __IO uint32_t bEOS : 1; /* End of sequence */
\r
3197 __IO uint32_t bVRSEL : 4; /* Selects combinations of V(R+) and V(R-) sources */
\r
3198 __I uint32_t bRESERVED1 : 1; /* Reserved */
\r
3199 __IO uint32_t bDIF : 1; /* Differential mode */
\r
3200 __IO uint32_t bWINC : 1; /* Comparator window enable */
\r
3201 __IO uint32_t bWINCTH : 1; /* Window comparator threshold register selection */
\r
3202 __I uint32_t bRESERVED2 : 16; /* Reserved */
\r
3205 union { /* ADC14MCTL27 Register */
\r
3207 struct { /* ADC14MCTL27 Bits */
\r
3208 __IO uint32_t bINCH : 5; /* Input channel select */
\r
3209 __I uint32_t bRESERVED0 : 2; /* Reserved */
\r
3210 __IO uint32_t bEOS : 1; /* End of sequence */
\r
3211 __IO uint32_t bVRSEL : 4; /* Selects combinations of V(R+) and V(R-) sources */
\r
3212 __I uint32_t bRESERVED1 : 1; /* Reserved */
\r
3213 __IO uint32_t bDIF : 1; /* Differential mode */
\r
3214 __IO uint32_t bWINC : 1; /* Comparator window enable */
\r
3215 __IO uint32_t bWINCTH : 1; /* Window comparator threshold register selection */
\r
3216 __I uint32_t bRESERVED2 : 16; /* Reserved */
\r
3219 union { /* ADC14MCTL28 Register */
\r
3221 struct { /* ADC14MCTL28 Bits */
\r
3222 __IO uint32_t bINCH : 5; /* Input channel select */
\r
3223 __I uint32_t bRESERVED0 : 2; /* Reserved */
\r
3224 __IO uint32_t bEOS : 1; /* End of sequence */
\r
3225 __IO uint32_t bVRSEL : 4; /* Selects combinations of V(R+) and V(R-) sources */
\r
3226 __I uint32_t bRESERVED1 : 1; /* Reserved */
\r
3227 __IO uint32_t bDIF : 1; /* Differential mode */
\r
3228 __IO uint32_t bWINC : 1; /* Comparator window enable */
\r
3229 __IO uint32_t bWINCTH : 1; /* Window comparator threshold register selection */
\r
3230 __I uint32_t bRESERVED2 : 16; /* Reserved */
\r
3233 union { /* ADC14MCTL29 Register */
\r
3235 struct { /* ADC14MCTL29 Bits */
\r
3236 __IO uint32_t bINCH : 5; /* Input channel select */
\r
3237 __I uint32_t bRESERVED0 : 2; /* Reserved */
\r
3238 __IO uint32_t bEOS : 1; /* End of sequence */
\r
3239 __IO uint32_t bVRSEL : 4; /* Selects combinations of V(R+) and V(R-) sources */
\r
3240 __I uint32_t bRESERVED1 : 1; /* Reserved */
\r
3241 __IO uint32_t bDIF : 1; /* Differential mode */
\r
3242 __IO uint32_t bWINC : 1; /* Comparator window enable */
\r
3243 __IO uint32_t bWINCTH : 1; /* Window comparator threshold register selection */
\r
3244 __I uint32_t bRESERVED2 : 16; /* Reserved */
\r
3247 union { /* ADC14MCTL30 Register */
\r
3249 struct { /* ADC14MCTL30 Bits */
\r
3250 __IO uint32_t bINCH : 5; /* Input channel select */
\r
3251 __I uint32_t bRESERVED0 : 2; /* Reserved */
\r
3252 __IO uint32_t bEOS : 1; /* End of sequence */
\r
3253 __IO uint32_t bVRSEL : 4; /* Selects combinations of V(R+) and V(R-) sources */
\r
3254 __I uint32_t bRESERVED1 : 1; /* Reserved */
\r
3255 __IO uint32_t bDIF : 1; /* Differential mode */
\r
3256 __IO uint32_t bWINC : 1; /* Comparator window enable */
\r
3257 __IO uint32_t bWINCTH : 1; /* Window comparator threshold register selection */
\r
3258 __I uint32_t bRESERVED2 : 16; /* Reserved */
\r
3261 union { /* ADC14MCTL31 Register */
\r
3263 struct { /* ADC14MCTL31 Bits */
\r
3264 __IO uint32_t bINCH : 5; /* Input channel select */
\r
3265 __I uint32_t bRESERVED0 : 2; /* Reserved */
\r
3266 __IO uint32_t bEOS : 1; /* End of sequence */
\r
3267 __IO uint32_t bVRSEL : 4; /* Selects combinations of V(R+) and V(R-) sources */
\r
3268 __I uint32_t bRESERVED1 : 1; /* Reserved */
\r
3269 __IO uint32_t bDIF : 1; /* Differential mode */
\r
3270 __IO uint32_t bWINC : 1; /* Comparator window enable */
\r
3271 __IO uint32_t bWINCTH : 1; /* Window comparator threshold register selection */
\r
3272 __I uint32_t bRESERVED2 : 16; /* Reserved */
\r
3275 union { /* ADC14MEM0 Register */
\r
3277 struct { /* ADC14MEM0 Bits */
\r
3278 __IO uint32_t bCONVRES : 16; /* Conversion Result */
\r
3279 __I uint32_t bRESERVED0 : 16; /* Reserved */
\r
3282 union { /* ADC14MEM1 Register */
\r
3284 struct { /* ADC14MEM1 Bits */
\r
3285 __IO uint32_t bCONVRES : 16; /* Conversion Result */
\r
3286 __I uint32_t bRESERVED0 : 16; /* Reserved */
\r
3289 union { /* ADC14MEM2 Register */
\r
3291 struct { /* ADC14MEM2 Bits */
\r
3292 __IO uint32_t bCONVRES : 16; /* Conversion Result */
\r
3293 __I uint32_t bRESERVED0 : 16; /* Reserved */
\r
3296 union { /* ADC14MEM3 Register */
\r
3298 struct { /* ADC14MEM3 Bits */
\r
3299 __IO uint32_t bCONVRES : 16; /* Conversion Result */
\r
3300 __I uint32_t bRESERVED0 : 16; /* Reserved */
\r
3303 union { /* ADC14MEM4 Register */
\r
3305 struct { /* ADC14MEM4 Bits */
\r
3306 __IO uint32_t bCONVRES : 16; /* Conversion Result */
\r
3307 __I uint32_t bRESERVED0 : 16; /* Reserved */
\r
3310 union { /* ADC14MEM5 Register */
\r
3312 struct { /* ADC14MEM5 Bits */
\r
3313 __IO uint32_t bCONVRES : 16; /* Conversion Result */
\r
3314 __I uint32_t bRESERVED0 : 16; /* Reserved */
\r
3317 union { /* ADC14MEM6 Register */
\r
3319 struct { /* ADC14MEM6 Bits */
\r
3320 __IO uint32_t bCONVRES : 16; /* Conversion Result */
\r
3321 __I uint32_t bRESERVED0 : 16; /* Reserved */
\r
3324 union { /* ADC14MEM7 Register */
\r
3326 struct { /* ADC14MEM7 Bits */
\r
3327 __IO uint32_t bCONVRES : 16; /* Conversion Result */
\r
3328 __I uint32_t bRESERVED0 : 16; /* Reserved */
\r
3331 union { /* ADC14MEM8 Register */
\r
3333 struct { /* ADC14MEM8 Bits */
\r
3334 __IO uint32_t bCONVRES : 16; /* Conversion Result */
\r
3335 __I uint32_t bRESERVED0 : 16; /* Reserved */
\r
3338 union { /* ADC14MEM9 Register */
\r
3340 struct { /* ADC14MEM9 Bits */
\r
3341 __IO uint32_t bCONVRES : 16; /* Conversion Result */
\r
3342 __I uint32_t bRESERVED0 : 16; /* Reserved */
\r
3345 union { /* ADC14MEM10 Register */
\r
3347 struct { /* ADC14MEM10 Bits */
\r
3348 __IO uint32_t bCONVRES : 16; /* Conversion Result */
\r
3349 __I uint32_t bRESERVED0 : 16; /* Reserved */
\r
3352 union { /* ADC14MEM11 Register */
\r
3354 struct { /* ADC14MEM11 Bits */
\r
3355 __IO uint32_t bCONVRES : 16; /* Conversion Result */
\r
3356 __I uint32_t bRESERVED0 : 16; /* Reserved */
\r
3359 union { /* ADC14MEM12 Register */
\r
3361 struct { /* ADC14MEM12 Bits */
\r
3362 __IO uint32_t bCONVRES : 16; /* Conversion Result */
\r
3363 __I uint32_t bRESERVED0 : 16; /* Reserved */
\r
3366 union { /* ADC14MEM13 Register */
\r
3368 struct { /* ADC14MEM13 Bits */
\r
3369 __IO uint32_t bCONVRES : 16; /* Conversion Result */
\r
3370 __I uint32_t bRESERVED0 : 16; /* Reserved */
\r
3373 union { /* ADC14MEM14 Register */
\r
3375 struct { /* ADC14MEM14 Bits */
\r
3376 __IO uint32_t bCONVRES : 16; /* Conversion Result */
\r
3377 __I uint32_t bRESERVED0 : 16; /* Reserved */
\r
3380 union { /* ADC14MEM15 Register */
\r
3382 struct { /* ADC14MEM15 Bits */
\r
3383 __IO uint32_t bCONVRES : 16; /* Conversion Result */
\r
3384 __I uint32_t bRESERVED0 : 16; /* Reserved */
\r
3387 union { /* ADC14MEM16 Register */
\r
3389 struct { /* ADC14MEM16 Bits */
\r
3390 __IO uint32_t bCONVRES : 16; /* Conversion Result */
\r
3391 __I uint32_t bRESERVED0 : 16; /* Reserved */
\r
3394 union { /* ADC14MEM17 Register */
\r
3396 struct { /* ADC14MEM17 Bits */
\r
3397 __IO uint32_t bCONVRES : 16; /* Conversion Result */
\r
3398 __I uint32_t bRESERVED0 : 16; /* Reserved */
\r
3401 union { /* ADC14MEM18 Register */
\r
3403 struct { /* ADC14MEM18 Bits */
\r
3404 __IO uint32_t bCONVRES : 16; /* Conversion Result */
\r
3405 __I uint32_t bRESERVED0 : 16; /* Reserved */
\r
3408 union { /* ADC14MEM19 Register */
\r
3410 struct { /* ADC14MEM19 Bits */
\r
3411 __IO uint32_t bCONVRES : 16; /* Conversion Result */
\r
3412 __I uint32_t bRESERVED0 : 16; /* Reserved */
\r
3415 union { /* ADC14MEM20 Register */
\r
3417 struct { /* ADC14MEM20 Bits */
\r
3418 __IO uint32_t bCONVRES : 16; /* Conversion Result */
\r
3419 __I uint32_t bRESERVED0 : 16; /* Reserved */
\r
3422 union { /* ADC14MEM21 Register */
\r
3424 struct { /* ADC14MEM21 Bits */
\r
3425 __IO uint32_t bCONVRES : 16; /* Conversion Result */
\r
3426 __I uint32_t bRESERVED0 : 16; /* Reserved */
\r
3429 union { /* ADC14MEM22 Register */
\r
3431 struct { /* ADC14MEM22 Bits */
\r
3432 __IO uint32_t bCONVRES : 16; /* Conversion Result */
\r
3433 __I uint32_t bRESERVED0 : 16; /* Reserved */
\r
3436 union { /* ADC14MEM23 Register */
\r
3438 struct { /* ADC14MEM23 Bits */
\r
3439 __IO uint32_t bCONVRES : 16; /* Conversion Result */
\r
3440 __I uint32_t bRESERVED0 : 16; /* Reserved */
\r
3443 union { /* ADC14MEM24 Register */
\r
3445 struct { /* ADC14MEM24 Bits */
\r
3446 __IO uint32_t bCONVRES : 16; /* Conversion Result */
\r
3447 __I uint32_t bRESERVED0 : 16; /* Reserved */
\r
3450 union { /* ADC14MEM25 Register */
\r
3452 struct { /* ADC14MEM25 Bits */
\r
3453 __IO uint32_t bCONVRES : 16; /* Conversion Result */
\r
3454 __I uint32_t bRESERVED0 : 16; /* Reserved */
\r
3457 union { /* ADC14MEM26 Register */
\r
3459 struct { /* ADC14MEM26 Bits */
\r
3460 __IO uint32_t bCONVRES : 16; /* Conversion Result */
\r
3461 __I uint32_t bRESERVED0 : 16; /* Reserved */
\r
3464 union { /* ADC14MEM27 Register */
\r
3466 struct { /* ADC14MEM27 Bits */
\r
3467 __IO uint32_t bCONVRES : 16; /* Conversion Result */
\r
3468 __I uint32_t bRESERVED0 : 16; /* Reserved */
\r
3471 union { /* ADC14MEM28 Register */
\r
3473 struct { /* ADC14MEM28 Bits */
\r
3474 __IO uint32_t bCONVRES : 16; /* Conversion Result */
\r
3475 __I uint32_t bRESERVED0 : 16; /* Reserved */
\r
3478 union { /* ADC14MEM29 Register */
\r
3480 struct { /* ADC14MEM29 Bits */
\r
3481 __IO uint32_t bCONVRES : 16; /* Conversion Result */
\r
3482 __I uint32_t bRESERVED0 : 16; /* Reserved */
\r
3485 union { /* ADC14MEM30 Register */
\r
3487 struct { /* ADC14MEM30 Bits */
\r
3488 __IO uint32_t bCONVRES : 16; /* Conversion Result */
\r
3489 __I uint32_t bRESERVED0 : 16; /* Reserved */
\r
3492 union { /* ADC14MEM31 Register */
\r
3494 struct { /* ADC14MEM31 Bits */
\r
3495 __IO uint32_t bCONVRES : 16; /* Conversion Result */
\r
3496 __I uint32_t bRESERVED0 : 16; /* Reserved */
\r
3499 uint8_t RESERVED0[36];
\r
3500 union { /* ADC14IER0 Register */
\r
3502 struct { /* ADC14IER0 Bits */
\r
3503 __IO uint32_t bIE0 : 1; /* Interrupt enable */
\r
3504 __IO uint32_t bIE1 : 1; /* Interrupt enable */
\r
3505 __IO uint32_t bIE2 : 1; /* Interrupt enable */
\r
3506 __IO uint32_t bIE3 : 1; /* Interrupt enable */
\r
3507 __IO uint32_t bIE4 : 1; /* Interrupt enable */
\r
3508 __IO uint32_t bIE5 : 1; /* Interrupt enable */
\r
3509 __IO uint32_t bIE6 : 1; /* Interrupt enable */
\r
3510 __IO uint32_t bIE7 : 1; /* Interrupt enable */
\r
3511 __IO uint32_t bIE8 : 1; /* Interrupt enable */
\r
3512 __IO uint32_t bIE9 : 1; /* Interrupt enable */
\r
3513 __IO uint32_t bIE10 : 1; /* Interrupt enable */
\r
3514 __IO uint32_t bIE11 : 1; /* Interrupt enable */
\r
3515 __IO uint32_t bIE12 : 1; /* Interrupt enable */
\r
3516 __IO uint32_t bIE13 : 1; /* Interrupt enable */
\r
3517 __IO uint32_t bIE14 : 1; /* Interrupt enable */
\r
3518 __IO uint32_t bIE15 : 1; /* Interrupt enable */
\r
3519 __IO uint32_t bIE16 : 1; /* Interrupt enable */
\r
3520 __IO uint32_t bIE17 : 1; /* Interrupt enable */
\r
3521 __IO uint32_t bIE18 : 1; /* Interrupt enable */
\r
3522 __IO uint32_t bIE19 : 1; /* Interrupt enable */
\r
3523 __IO uint32_t bIE20 : 1; /* Interrupt enable */
\r
3524 __IO uint32_t bIE21 : 1; /* Interrupt enable */
\r
3525 __IO uint32_t bIE22 : 1; /* Interrupt enable */
\r
3526 __IO uint32_t bIE23 : 1; /* Interrupt enable */
\r
3527 __IO uint32_t bIE24 : 1; /* Interrupt enable */
\r
3528 __IO uint32_t bIE25 : 1; /* Interrupt enable */
\r
3529 __IO uint32_t bIE26 : 1; /* Interrupt enable */
\r
3530 __IO uint32_t bIE27 : 1; /* Interrupt enable */
\r
3531 __IO uint32_t bIE28 : 1; /* Interrupt enable */
\r
3532 __IO uint32_t bIE29 : 1; /* Interrupt enable */
\r
3533 __IO uint32_t bIE30 : 1; /* Interrupt enable */
\r
3534 __IO uint32_t bIE31 : 1; /* Interrupt enable */
\r
3537 union { /* ADC14IER1 Register */
\r
3539 struct { /* ADC14IER1 Bits */
\r
3540 __I uint32_t bRESERVED0 : 1; /* Reserved */
\r
3541 __IO uint32_t bINIE : 1; /* Interrupt enable for ADC14MEMx within comparator window */
\r
3542 __IO uint32_t bLOIE : 1; /* Interrupt enable for ADC14MEMx below comparator window */
\r
3543 __IO uint32_t bHIIE : 1; /* Interrupt enable for ADC14MEMx above comparator window */
\r
3544 __IO uint32_t bOVIE : 1; /* ADC14MEMx overflow-interrupt enable */
\r
3545 __IO uint32_t bTOVIE : 1; /* ADC14 conversion-time-overflow interrupt enable */
\r
3546 __IO uint32_t bRDYIE : 1; /* ADC14 local buffered reference ready interrupt enable */
\r
3547 __I uint32_t bRESERVED1 : 25; /* Reserved */
\r
3550 union { /* ADC14IFGR0 Register */
\r
3552 struct { /* ADC14IFGR0 Bits */
\r
3553 __I uint32_t bIFG0 : 1; /* ADC14MEM0 interrupt flag */
\r
3554 __I uint32_t bIFG1 : 1; /* ADC14MEM1 interrupt flag */
\r
3555 __I uint32_t bIFG2 : 1; /* ADC14MEM2 interrupt flag */
\r
3556 __I uint32_t bIFG3 : 1; /* ADC14MEM3 interrupt flag */
\r
3557 __I uint32_t bIFG4 : 1; /* ADC14MEM4 interrupt flag */
\r
3558 __I uint32_t bIFG5 : 1; /* ADC14MEM5 interrupt flag */
\r
3559 __I uint32_t bIFG6 : 1; /* ADC14MEM6 interrupt flag */
\r
3560 __I uint32_t bIFG7 : 1; /* ADC14MEM7 interrupt flag */
\r
3561 __I uint32_t bIFG8 : 1; /* ADC14MEM8 interrupt flag */
\r
3562 __I uint32_t bIFG9 : 1; /* ADC14MEM9 interrupt flag */
\r
3563 __I uint32_t bIFG10 : 1; /* ADC14MEM10 interrupt flag */
\r
3564 __I uint32_t bIFG11 : 1; /* ADC14MEM11 interrupt flag */
\r
3565 __I uint32_t bIFG12 : 1; /* ADC14MEM12 interrupt flag */
\r
3566 __I uint32_t bIFG13 : 1; /* ADC14MEM13 interrupt flag */
\r
3567 __I uint32_t bIFG14 : 1; /* ADC14MEM14 interrupt flag */
\r
3568 __I uint32_t bIFG15 : 1; /* ADC14MEM15 interrupt flag */
\r
3569 __I uint32_t bIFG16 : 1; /* ADC14MEM16 interrupt flag */
\r
3570 __I uint32_t bIFG17 : 1; /* ADC14MEM17 interrupt flag */
\r
3571 __I uint32_t bIFG18 : 1; /* ADC14MEM18 interrupt flag */
\r
3572 __I uint32_t bIFG19 : 1; /* ADC14MEM19 interrupt flag */
\r
3573 __I uint32_t bIFG20 : 1; /* ADC14MEM20 interrupt flag */
\r
3574 __I uint32_t bIFG21 : 1; /* ADC14MEM21 interrupt flag */
\r
3575 __I uint32_t bIFG22 : 1; /* ADC14MEM22 interrupt flag */
\r
3576 __I uint32_t bIFG23 : 1; /* ADC14MEM23 interrupt flag */
\r
3577 __I uint32_t bIFG24 : 1; /* ADC14MEM24 interrupt flag */
\r
3578 __I uint32_t bIFG25 : 1; /* ADC14MEM25 interrupt flag */
\r
3579 __I uint32_t bIFG26 : 1; /* ADC14MEM26 interrupt flag */
\r
3580 __I uint32_t bIFG27 : 1; /* ADC14MEM27 interrupt flag */
\r
3581 __I uint32_t bIFG28 : 1; /* ADC14MEM28 interrupt flag */
\r
3582 __I uint32_t bIFG29 : 1; /* ADC14MEM29 interrupt flag */
\r
3583 __I uint32_t bIFG30 : 1; /* ADC14MEM30 interrupt flag */
\r
3584 __I uint32_t bIFG31 : 1; /* ADC14MEM31 interrupt flag */
\r
3587 union { /* ADC14IFGR1 Register */
\r
3589 struct { /* ADC14IFGR1 Bits */
\r
3590 __I uint32_t bRESERVED0 : 1; /* Reserved */
\r
3591 __I uint32_t bINIFG : 1; /* Interrupt flag for ADC14MEMx within comparator window */
\r
3592 __I uint32_t bLOIFG : 1; /* Interrupt flag for ADC14MEMx below comparator window */
\r
3593 __I uint32_t bHIIFG : 1; /* Interrupt flag for ADC14MEMx above comparator window */
\r
3594 __I uint32_t bOVIFG : 1; /* ADC14MEMx overflow interrupt flag */
\r
3595 __I uint32_t bTOVIFG : 1; /* ADC14 conversion time overflow interrupt flag */
\r
3596 __I uint32_t bRDYIFG : 1; /* ADC14 local buffered reference ready interrupt flag */
\r
3597 __I uint32_t bRESERVED1 : 25; /* Reserved */
\r
3600 union { /* ADC14CLRIFGR0 Register */
\r
3602 struct { /* ADC14CLRIFGR0 Bits */
\r
3603 __O uint32_t bCLRIFG0 : 1; /* clear ADC14IFG0 */
\r
3604 __O uint32_t bCLRIFG1 : 1; /* clear ADC14IFG1 */
\r
3605 __O uint32_t bCLRIFG2 : 1; /* clear ADC14IFG2 */
\r
3606 __O uint32_t bCLRIFG3 : 1; /* clear ADC14IFG3 */
\r
3607 __O uint32_t bCLRIFG4 : 1; /* clear ADC14IFG4 */
\r
3608 __O uint32_t bCLRIFG5 : 1; /* clear ADC14IFG5 */
\r
3609 __O uint32_t bCLRIFG6 : 1; /* clear ADC14IFG6 */
\r
3610 __O uint32_t bCLRIFG7 : 1; /* clear ADC14IFG7 */
\r
3611 __O uint32_t bCLRIFG8 : 1; /* clear ADC14IFG8 */
\r
3612 __O uint32_t bCLRIFG9 : 1; /* clear ADC14IFG9 */
\r
3613 __O uint32_t bCLRIFG10 : 1; /* clear ADC14IFG10 */
\r
3614 __O uint32_t bCLRIFG11 : 1; /* clear ADC14IFG11 */
\r
3615 __O uint32_t bCLRIFG12 : 1; /* clear ADC14IFG12 */
\r
3616 __O uint32_t bCLRIFG13 : 1; /* clear ADC14IFG13 */
\r
3617 __O uint32_t bCLRIFG14 : 1; /* clear ADC14IFG14 */
\r
3618 __O uint32_t bCLRIFG15 : 1; /* clear ADC14IFG15 */
\r
3619 __O uint32_t bCLRIFG16 : 1; /* clear ADC14IFG16 */
\r
3620 __O uint32_t bCLRIFG17 : 1; /* clear ADC14IFG17 */
\r
3621 __O uint32_t bCLRIFG18 : 1; /* clear ADC14IFG18 */
\r
3622 __O uint32_t bCLRIFG19 : 1; /* clear ADC14IFG19 */
\r
3623 __O uint32_t bCLRIFG20 : 1; /* clear ADC14IFG20 */
\r
3624 __O uint32_t bCLRIFG21 : 1; /* clear ADC14IFG21 */
\r
3625 __O uint32_t bCLRIFG22 : 1; /* clear ADC14IFG22 */
\r
3626 __O uint32_t bCLRIFG23 : 1; /* clear ADC14IFG23 */
\r
3627 __O uint32_t bCLRIFG24 : 1; /* clear ADC14IFG24 */
\r
3628 __O uint32_t bCLRIFG25 : 1; /* clear ADC14IFG25 */
\r
3629 __O uint32_t bCLRIFG26 : 1; /* clear ADC14IFG26 */
\r
3630 __O uint32_t bCLRIFG27 : 1; /* clear ADC14IFG27 */
\r
3631 __O uint32_t bCLRIFG28 : 1; /* clear ADC14IFG28 */
\r
3632 __O uint32_t bCLRIFG29 : 1; /* clear ADC14IFG29 */
\r
3633 __O uint32_t bCLRIFG30 : 1; /* clear ADC14IFG30 */
\r
3634 __O uint32_t bCLRIFG31 : 1; /* clear ADC14IFG31 */
\r
3637 union { /* ADC14CLRIFGR1 Register */
\r
3639 struct { /* ADC14CLRIFGR1 Bits */
\r
3640 __I uint32_t bRESERVED0 : 1; /* Reserved */
\r
3641 __O uint32_t bCLRINIFG : 1; /* clear ADC14INIFG */
\r
3642 __O uint32_t bCLRLOIFG : 1; /* clear ADC14LOIFG */
\r
3643 __O uint32_t bCLRHIIFG : 1; /* clear ADC14HIIFG */
\r
3644 __O uint32_t bCLROVIFG : 1; /* clear ADC14OVIFG */
\r
3645 __O uint32_t bCLRTOVIFG : 1; /* clear ADC14TOVIFG */
\r
3646 __O uint32_t bCLRRDYIFG : 1; /* clear ADC14RDYIFG */
\r
3647 __I uint32_t bRESERVED1 : 25; /* Reserved */
\r
3650 __IO uint32_t rIV; /* Interrupt Vector Register */
\r
3654 //*****************************************************************************
\r
3655 // AES256 Registers
\r
3656 //*****************************************************************************
\r
3658 union { /* AESACTL0 Register */
\r
3660 struct { /* AESACTL0 Bits */
\r
3661 __IO uint16_t bOP : 2; /* AES operation */
\r
3662 __IO uint16_t bKL : 2; /* AES key length */
\r
3663 __I uint16_t bRESERVED0 : 1; /* Reserved */
\r
3664 __IO uint16_t bCM : 2; /* AES cipher mode select */
\r
3665 __IO uint16_t bSWRST : 1; /* AES software reset */
\r
3666 __IO uint16_t bRDYIFG : 1; /* AES ready interrupt flag */
\r
3667 __I uint16_t bRESERVED1 : 2; /* Reserved */
\r
3668 __IO uint16_t bERRFG : 1; /* AES error flag */
\r
3669 __IO uint16_t bRDYIE : 1; /* AES ready interrupt enable */
\r
3670 __I uint16_t bRESERVED2 : 2; /* Reserved */
\r
3671 __IO uint16_t bCMEN : 1; /* AES cipher mode enable */
\r
3674 union { /* AESACTL1 Register */
\r
3676 struct { /* AESACTL1 Bits */
\r
3677 __IO uint16_t bBLKCNT : 8; /* Cipher Block Counter */
\r
3678 __I uint16_t bRESERVED0 : 8; /* Reserved */
\r
3681 union { /* AESASTAT Register */
\r
3683 struct { /* AESASTAT Bits */
\r
3684 __IO uint16_t bBUSY : 1; /* AES accelerator module busy */
\r
3685 __IO uint16_t bKEYWR : 1; /* All 16 bytes written to AESAKEY */
\r
3686 __IO uint16_t bDINWR : 1; /* All 16 bytes written to AESADIN, AESAXDIN or AESAXIN */
\r
3687 __I uint16_t bDOUTRD : 1; /* All 16 bytes read from AESADOUT */
\r
3688 __I uint16_t bKEYCNT : 4; /* Bytes written via AESAKEY for AESKLx=00, half-words written via AESAKEY */
\r
3689 __I uint16_t bDINCNT : 4; /* Bytes written via AESADIN, AESAXDIN or AESAXIN */
\r
3690 __I uint16_t bDOUTCNT : 4; /* Bytes read via AESADOUT */
\r
3693 union { /* AESAKEY Register */
\r
3695 struct { /* AESAKEY Bits */
\r
3696 __O uint16_t bKEY0 : 8; /* AES key byte n when AESAKEY is written as half-word */
\r
3697 __O uint16_t bKEY1 : 8; /* AES key byte n+1 when AESAKEY is written as half-word */
\r
3700 union { /* AESADIN Register */
\r
3702 struct { /* AESADIN Bits */
\r
3703 __O uint16_t bDIN0 : 8; /* AES data in byte n when AESADIN is written as half-word */
\r
3704 __O uint16_t bDIN1 : 8; /* AES data in byte n+1 when AESADIN is written as half-word */
\r
3707 union { /* AESADOUT Register */
\r
3709 struct { /* AESADOUT Bits */
\r
3710 __O uint16_t bDOUT0 : 8; /* AES data out byte n when AESADOUT is read as half-word */
\r
3711 __O uint16_t bDOUT1 : 8; /* AES data out byte n+1 when AESADOUT is read as half-word */
\r
3714 union { /* AESAXDIN Register */
\r
3716 struct { /* AESAXDIN Bits */
\r
3717 __O uint16_t bXDIN0 : 8; /* AES data in byte n when AESAXDIN is written as half-word */
\r
3718 __O uint16_t bXDIN1 : 8; /* AES data in byte n+1 when AESAXDIN is written as half-word */
\r
3721 union { /* AESAXIN Register */
\r
3723 struct { /* AESAXIN Bits */
\r
3724 __O uint16_t bXIN0 : 8; /* AES data in byte n when AESAXIN is written as half-word */
\r
3725 __O uint16_t bXIN1 : 8; /* AES data in byte n+1 when AESAXIN is written as half-word */
\r
3731 //*****************************************************************************
\r
3732 // CAPTIO0 Registers
\r
3733 //*****************************************************************************
\r
3735 uint8_t RESERVED0[14];
\r
3736 union { /* CAPTIO0CTL Register */
\r
3738 struct { /* CAPTIO0CTL Bits */
\r
3739 __I uint16_t bRESERVED0 : 1; /* Reserved */
\r
3740 __IO uint16_t bPISEL : 3; /* Capacitive Touch IO pin select */
\r
3741 __IO uint16_t bPOSEL : 4; /* Capacitive Touch IO port select */
\r
3742 __IO uint16_t bEN : 1; /* Capacitive Touch IO enable */
\r
3743 __I uint16_t bSTATE : 1; /* Capacitive Touch IO state */
\r
3744 __I uint16_t bRESERVED1 : 6; /* Reserved */
\r
3750 //*****************************************************************************
\r
3751 // CAPTIO1 Registers
\r
3752 //*****************************************************************************
\r
3754 uint8_t RESERVED0[14];
\r
3755 union { /* CAPTIO1CTL Register */
\r
3757 struct { /* CAPTIO1CTL Bits */
\r
3758 __I uint16_t bRESERVED0 : 1; /* Reserved */
\r
3759 __IO uint16_t bPISEL : 3; /* Capacitive Touch IO pin select */
\r
3760 __IO uint16_t bPOSEL : 4; /* Capacitive Touch IO port select */
\r
3761 __IO uint16_t bEN : 1; /* Capacitive Touch IO enable */
\r
3762 __I uint16_t bSTATE : 1; /* Capacitive Touch IO state */
\r
3763 __I uint16_t bRESERVED1 : 6; /* Reserved */
\r
3769 //*****************************************************************************
\r
3770 // COMP_E0 Registers
\r
3771 //*****************************************************************************
\r
3773 union { /* CE0CTL0 Register */
\r
3775 struct { /* CE0CTL0 Bits */
\r
3776 __IO uint16_t bIPSEL : 4; /* Channel input selected for the V+ terminal */
\r
3777 __I uint16_t bRESERVED0 : 3; /* Reserved */
\r
3778 __IO uint16_t bIPEN : 1; /* Channel input enable for the V+ terminal */
\r
3779 __IO uint16_t bIMSEL : 4; /* Channel input selected for the - terminal */
\r
3780 __I uint16_t bRESERVED1 : 3; /* Reserved */
\r
3781 __IO uint16_t bIMEN : 1; /* Channel input enable for the - terminal */
\r
3784 union { /* CE0CTL1 Register */
\r
3786 struct { /* CE0CTL1 Bits */
\r
3787 __IO uint16_t bOUT : 1; /* Comparator output value */
\r
3788 __IO uint16_t bOUTPOL : 1; /* Comparator output polarity */
\r
3789 __IO uint16_t bF : 1; /* Comparator output filter */
\r
3790 __IO uint16_t bIES : 1; /* Interrupt edge select for CEIIFG and CEIFG */
\r
3791 __IO uint16_t bSHORT : 1; /* Input short */
\r
3792 __IO uint16_t bEX : 1; /* Exchange */
\r
3793 __IO uint16_t bFDLY : 2; /* Filter delay */
\r
3794 __IO uint16_t bPWRMD : 2; /* Power Mode */
\r
3795 __IO uint16_t bON : 1; /* Comparator On */
\r
3796 __IO uint16_t bMRVL : 1; /* This bit is valid of CEMRVS is set to 1 */
\r
3797 __IO uint16_t bMRVS : 1; /* */
\r
3798 __I uint16_t bRESERVED0 : 3; /* Reserved */
\r
3801 union { /* CE0CTL2 Register */
\r
3803 struct { /* CE0CTL2 Bits */
\r
3804 __IO uint16_t bREF0 : 5; /* Reference resistor tap 0 */
\r
3805 __IO uint16_t bRSEL : 1; /* Reference select */
\r
3806 __IO uint16_t bRS : 2; /* Reference source */
\r
3807 __IO uint16_t bREF1 : 5; /* Reference resistor tap 1 */
\r
3808 __IO uint16_t bREFL : 2; /* Reference voltage level */
\r
3809 __IO uint16_t bREFACC : 1; /* Reference accuracy */
\r
3812 union { /* CE0CTL3 Register */
\r
3814 struct { /* CE0CTL3 Bits */
\r
3815 __IO uint16_t bPD0 : 1; /* Port disable */
\r
3816 __IO uint16_t bPD1 : 1; /* Port disable */
\r
3817 __IO uint16_t bPD2 : 1; /* Port disable */
\r
3818 __IO uint16_t bPD3 : 1; /* Port disable */
\r
3819 __IO uint16_t bPD4 : 1; /* Port disable */
\r
3820 __IO uint16_t bPD5 : 1; /* Port disable */
\r
3821 __IO uint16_t bPD6 : 1; /* Port disable */
\r
3822 __IO uint16_t bPD7 : 1; /* Port disable */
\r
3823 __IO uint16_t bPD8 : 1; /* Port disable */
\r
3824 __IO uint16_t bPD9 : 1; /* Port disable */
\r
3825 __IO uint16_t bPD10 : 1; /* Port disable */
\r
3826 __IO uint16_t bPD11 : 1; /* Port disable */
\r
3827 __IO uint16_t bPD12 : 1; /* Port disable */
\r
3828 __IO uint16_t bPD13 : 1; /* Port disable */
\r
3829 __IO uint16_t bPD14 : 1; /* Port disable */
\r
3830 __IO uint16_t bPD15 : 1; /* Port disable */
\r
3833 uint8_t RESERVED0[4];
\r
3834 union { /* CE0INT Register */
\r
3836 struct { /* CE0INT Bits */
\r
3837 __IO uint16_t bIFG : 1; /* Comparator output interrupt flag */
\r
3838 __IO uint16_t bIIFG : 1; /* Comparator output inverted interrupt flag */
\r
3839 __I uint16_t bRESERVED0 : 2; /* Reserved */
\r
3840 __IO uint16_t bRDYIFG : 1; /* Comparator ready interrupt flag */
\r
3841 __I uint16_t bRESERVED1 : 3; /* Reserved */
\r
3842 __IO uint16_t bIE : 1; /* Comparator output interrupt enable */
\r
3843 __IO uint16_t bIIE : 1; /* Comparator output interrupt enable inverted polarity */
\r
3844 __I uint16_t bRESERVED2 : 2; /* Reserved */
\r
3845 __IO uint16_t bRDYIE : 1; /* Comparator ready interrupt enable */
\r
3846 __I uint16_t bRESERVED3 : 3; /* Reserved */
\r
3849 __I uint16_t rIV; /* Comparator Interrupt Vector Word Register */
\r
3853 //*****************************************************************************
\r
3854 // COMP_E1 Registers
\r
3855 //*****************************************************************************
\r
3857 union { /* CE1CTL0 Register */
\r
3859 struct { /* CE1CTL0 Bits */
\r
3860 __IO uint16_t bIPSEL : 4; /* Channel input selected for the V+ terminal */
\r
3861 __I uint16_t bRESERVED0 : 3; /* Reserved */
\r
3862 __IO uint16_t bIPEN : 1; /* Channel input enable for the V+ terminal */
\r
3863 __IO uint16_t bIMSEL : 4; /* Channel input selected for the - terminal */
\r
3864 __I uint16_t bRESERVED1 : 3; /* Reserved */
\r
3865 __IO uint16_t bIMEN : 1; /* Channel input enable for the - terminal */
\r
3868 union { /* CE1CTL1 Register */
\r
3870 struct { /* CE1CTL1 Bits */
\r
3871 __IO uint16_t bOUT : 1; /* Comparator output value */
\r
3872 __IO uint16_t bOUTPOL : 1; /* Comparator output polarity */
\r
3873 __IO uint16_t bF : 1; /* Comparator output filter */
\r
3874 __IO uint16_t bIES : 1; /* Interrupt edge select for CEIIFG and CEIFG */
\r
3875 __IO uint16_t bSHORT : 1; /* Input short */
\r
3876 __IO uint16_t bEX : 1; /* Exchange */
\r
3877 __IO uint16_t bFDLY : 2; /* Filter delay */
\r
3878 __IO uint16_t bPWRMD : 2; /* Power Mode */
\r
3879 __IO uint16_t bON : 1; /* Comparator On */
\r
3880 __IO uint16_t bMRVL : 1; /* This bit is valid of CEMRVS is set to 1 */
\r
3881 __IO uint16_t bMRVS : 1; /* */
\r
3882 __I uint16_t bRESERVED0 : 3; /* Reserved */
\r
3885 union { /* CE1CTL2 Register */
\r
3887 struct { /* CE1CTL2 Bits */
\r
3888 __IO uint16_t bREF0 : 5; /* Reference resistor tap 0 */
\r
3889 __IO uint16_t bRSEL : 1; /* Reference select */
\r
3890 __IO uint16_t bRS : 2; /* Reference source */
\r
3891 __IO uint16_t bREF1 : 5; /* Reference resistor tap 1 */
\r
3892 __IO uint16_t bREFL : 2; /* Reference voltage level */
\r
3893 __IO uint16_t bREFACC : 1; /* Reference accuracy */
\r
3896 union { /* CE1CTL3 Register */
\r
3898 struct { /* CE1CTL3 Bits */
\r
3899 __IO uint16_t bPD0 : 1; /* Port disable */
\r
3900 __IO uint16_t bPD1 : 1; /* Port disable */
\r
3901 __IO uint16_t bPD2 : 1; /* Port disable */
\r
3902 __IO uint16_t bPD3 : 1; /* Port disable */
\r
3903 __IO uint16_t bPD4 : 1; /* Port disable */
\r
3904 __IO uint16_t bPD5 : 1; /* Port disable */
\r
3905 __IO uint16_t bPD6 : 1; /* Port disable */
\r
3906 __IO uint16_t bPD7 : 1; /* Port disable */
\r
3907 __IO uint16_t bPD8 : 1; /* Port disable */
\r
3908 __IO uint16_t bPD9 : 1; /* Port disable */
\r
3909 __IO uint16_t bPD10 : 1; /* Port disable */
\r
3910 __IO uint16_t bPD11 : 1; /* Port disable */
\r
3911 __IO uint16_t bPD12 : 1; /* Port disable */
\r
3912 __IO uint16_t bPD13 : 1; /* Port disable */
\r
3913 __IO uint16_t bPD14 : 1; /* Port disable */
\r
3914 __IO uint16_t bPD15 : 1; /* Port disable */
\r
3917 uint8_t RESERVED0[4];
\r
3918 union { /* CE1INT Register */
\r
3920 struct { /* CE1INT Bits */
\r
3921 __IO uint16_t bIFG : 1; /* Comparator output interrupt flag */
\r
3922 __IO uint16_t bIIFG : 1; /* Comparator output inverted interrupt flag */
\r
3923 __I uint16_t bRESERVED0 : 2; /* Reserved */
\r
3924 __IO uint16_t bRDYIFG : 1; /* Comparator ready interrupt flag */
\r
3925 __I uint16_t bRESERVED1 : 3; /* Reserved */
\r
3926 __IO uint16_t bIE : 1; /* Comparator output interrupt enable */
\r
3927 __IO uint16_t bIIE : 1; /* Comparator output interrupt enable inverted polarity */
\r
3928 __I uint16_t bRESERVED2 : 2; /* Reserved */
\r
3929 __IO uint16_t bRDYIE : 1; /* Comparator ready interrupt enable */
\r
3930 __I uint16_t bRESERVED3 : 3; /* Reserved */
\r
3933 __I uint16_t rIV; /* Comparator Interrupt Vector Word Register */
\r
3937 //*****************************************************************************
\r
3938 // CRC32 Registers
\r
3939 //*****************************************************************************
\r
3941 __IO uint16_t rCRC32DI; /* Data Input for CRC32 Signature Computation */
\r
3942 uint8_t RESERVED0[2];
\r
3943 __IO uint16_t rCRC32DIRB; /* Data In Reverse for CRC32 Computation */
\r
3944 uint8_t RESERVED1[2];
\r
3945 __IO uint16_t rCRC32INIRES_LO; /* CRC32 Initialization and Result, lower 16 bits */
\r
3946 __IO uint16_t rCRC32INIRES_HI; /* CRC32 Initialization and Result, upper 16 bits */
\r
3947 __IO uint16_t rCRC32RESR_LO; /* CRC32 Result Reverse, lower 16 bits */
\r
3948 __IO uint16_t rCRC32RESR_HI; /* CRC32 Result Reverse, Upper 16 bits */
\r
3949 __IO uint16_t rCRC16DI; /* Data Input for CRC16 computation */
\r
3950 uint8_t RESERVED2[2];
\r
3951 __IO uint16_t rCRC16DIRB; /* CRC16 Data In Reverse */
\r
3952 uint8_t RESERVED3[2];
\r
3953 __IO uint16_t rCRC16INIRES; /* CRC16 Initialization and Result register */
\r
3954 uint8_t RESERVED4[4];
\r
3955 __IO uint16_t rCRC16RESR; /* CRC16 Result Reverse */
\r
3959 //*****************************************************************************
\r
3961 //*****************************************************************************
\r
3963 union { /* CSKEY Register */
\r
3965 struct { /* CSKEY Bits */
\r
3966 __IO uint32_t bKEY : 16; /* Write xxxx_695Ah to unlock */
\r
3967 __I uint32_t bRESERVED0 : 16; /* Reserved */
\r
3970 union { /* CSCTL0 Register */
\r
3972 struct { /* CSCTL0 Bits */
\r
3973 __IO uint32_t bDCOTUNE : 13; /* DCO frequency tuning select */
\r
3974 __I uint32_t bRESERVED0 : 3; /* Reserved */
\r
3975 __IO uint32_t bDCORSEL : 3; /* DCO frequency range select */
\r
3976 __I uint32_t bRESERVED1 : 3; /* Reserved */
\r
3977 __IO uint32_t bDCORES : 1; /* Enables the DCO external resistor mode */
\r
3978 __IO uint32_t bDCOEN : 1; /* Enables the DCO oscillator */
\r
3979 __IO uint32_t bDIS_DCO_DELAY_CNT : 1; /* */
\r
3980 __I uint32_t bRESERVED2 : 7; /* Reserved */
\r
3983 union { /* CSCTL1 Register */
\r
3985 struct { /* CSCTL1 Bits */
\r
3986 __IO uint32_t bSELM : 3; /* Selects the MCLK source */
\r
3987 __I uint32_t bRESERVED0 : 1; /* Reserved */
\r
3988 __IO uint32_t bSELS : 3; /* Selects the SMCLK and HSMCLK source */
\r
3989 __I uint32_t bRESERVED1 : 1; /* Reserved */
\r
3990 __IO uint32_t bSELA : 3; /* Selects the ACLK source */
\r
3991 __I uint32_t bRESERVED2 : 1; /* Reserved */
\r
3992 __IO uint32_t bSELB : 1; /* Selects the BCLK source */
\r
3993 __I uint32_t bRESERVED3 : 3; /* Reserved */
\r
3994 __IO uint32_t bDIVM : 3; /* MCLK source divider */
\r
3995 __I uint32_t bRESERVED4 : 1; /* Reserved */
\r
3996 __IO uint32_t bDIVHS : 3; /* HSMCLK source divider */
\r
3997 __I uint32_t bRESERVED5 : 1; /* Reserved */
\r
3998 __IO uint32_t bDIVA : 3; /* ACLK source divider */
\r
3999 __I uint32_t bRESERVED6 : 1; /* Reserved */
\r
4000 __IO uint32_t bDIVS : 3; /* SMCLK source divider */
\r
4001 __I uint32_t bRESERVED7 : 1; /* Reserved */
\r
4004 union { /* CSCTL2 Register */
\r
4006 struct { /* CSCTL2 Bits */
\r
4007 __IO uint32_t bLFXTDRIVE : 3; /* LFXT oscillator current can be adjusted to its drive needs */
\r
4008 __IO uint32_t bRESERVED0 : 4; /* Reserved */
\r
4009 __IO uint32_t bLFXTAGCOFF : 1; /* Disables the automatic gain control of the LFXT crystal */
\r
4010 __IO uint32_t bLFXT_EN : 1; /* Turns on the LFXT oscillator regardless if used as a clock resource */
\r
4011 __IO uint32_t bLFXTBYPASS : 1; /* LFXT bypass select */
\r
4012 __I uint32_t bRESERVED1 : 6; /* Reserved */
\r
4013 __IO uint32_t bHFXTDRIVE : 1; /* HFXT oscillator drive selection */
\r
4014 __IO uint32_t bRESERVED5 : 2; /* Reserved */
\r
4015 __I uint32_t bRESERVED2 : 1; /* Reserved */
\r
4016 __IO uint32_t bHFXTFREQ : 3; /* HFXT frequency selection */
\r
4017 __I uint32_t bRESERVED3 : 1; /* Reserved */
\r
4018 __IO uint32_t bHFXT_EN : 1; /* Turns on the HFXT oscillator regardless if used as a clock resource */
\r
4019 __IO uint32_t bHFXTBYPASS : 1; /* HFXT bypass select */
\r
4020 __I uint32_t bRESERVED4 : 6; /* Reserved */
\r
4023 union { /* CSCTL3 Register */
\r
4025 struct { /* CSCTL3 Bits */
\r
4026 __IO uint32_t bFCNTLF : 2; /* Start flag counter for LFXT */
\r
4027 __O uint32_t bRFCNTLF : 1; /* Reset start fault counter for LFXT */
\r
4028 __IO uint32_t bFCNTLF_EN : 1; /* Enable start fault counter for LFXT */
\r
4029 __IO uint32_t bFCNTHF : 2; /* Start flag counter for HFXT */
\r
4030 __O uint32_t bRFCNTHF : 1; /* Reset start fault counter for HFXT */
\r
4031 __IO uint32_t bFCNTHF_EN : 1; /* Enable start fault counter for HFXT */
\r
4032 __IO uint32_t bFCNTHF2 : 2; /* Start flag counter for HFXT2 */
\r
4033 __O uint32_t bRFCNTHF2 : 1; /* Reset start fault counter for HFXT2 */
\r
4034 __IO uint32_t bFCNTHF2_EN : 1; /* Enable start fault counter for HFXT2 */
\r
4035 __I uint32_t bRESERVED0 : 20; /* Reserved */
\r
4038 union { /* CSCTL4 Register */
\r
4040 struct { /* CSCTL4 Bits */
\r
4041 __IO uint32_t bHFXT2DRIVE : 3; /* HFXT2 oscillator current can be adjusted to its drive needs */
\r
4042 __I uint32_t bRESERVED0 : 1; /* Reserved */
\r
4043 __IO uint32_t bHFXT2FREQ : 3; /* HFXT2 frequency selection */
\r
4044 __I uint32_t bRESERVED1 : 1; /* Reserved */
\r
4045 __IO uint32_t bHFXT2_EN : 1; /* Turns on the HFXT2 oscillator */
\r
4046 __IO uint32_t bHFXT2BYPASS : 1; /* HFXT2 bypass select */
\r
4047 __I uint32_t bRESERVED2 : 22; /* Reserved */
\r
4050 union { /* CSCTL5 Register */
\r
4052 struct { /* CSCTL5 Bits */
\r
4053 __IO uint32_t bREFCNTSEL : 3; /* Reference counter source select */
\r
4054 __IO uint32_t bREFCNTPS : 3; /* Reference clock prescaler */
\r
4055 __I uint32_t bRESERVED0 : 1; /* Reserved */
\r
4056 __O uint32_t bCALSTART : 1; /* Start clock calibration counters */
\r
4057 __IO uint32_t bPERCNTSEL : 3; /* Period counter source select */
\r
4058 __I uint32_t bRESERVED1 : 21; /* Reserved */
\r
4061 union { /* CSCTL6 Register */
\r
4063 struct { /* CSCTL6 Bits */
\r
4064 __I uint32_t bPERCNT : 16; /* Calibration period counter */
\r
4065 __I uint32_t bRESERVED0 : 16; /* Reserved */
\r
4068 union { /* CSCTL7 Register */
\r
4070 struct { /* CSCTL7 Bits */
\r
4071 __IO uint32_t bREFCNT : 16; /* Calibration reference period counter */
\r
4072 __I uint32_t bRESERVED0 : 16; /* Reserved */
\r
4075 uint8_t RESERVED0[12];
\r
4076 union { /* CSCLKEN Register */
\r
4078 struct { /* CSCLKEN Bits */
\r
4079 __IO uint32_t bACLK_EN : 1; /* ACLK system clock conditional request enable */
\r
4080 __IO uint32_t bMCLK_EN : 1; /* MCLK system clock conditional request enable */
\r
4081 __IO uint32_t bHSMCLK_EN : 1; /* HSMCLK system clock conditional request enable */
\r
4082 __IO uint32_t bSMCLK_EN : 1; /* SMCLK system clock conditional request enable */
\r
4083 __I uint32_t bRESERVED0 : 4; /* Reserved */
\r
4084 __IO uint32_t bVLO_EN : 1; /* Turns on the VLO oscillator */
\r
4085 __IO uint32_t bREFO_EN : 1; /* Turns on the REFO oscillator */
\r
4086 __IO uint32_t bMODOSC_EN : 1; /* Turns on the MODOSC oscillator */
\r
4087 __I uint32_t bRESERVED1 : 4; /* Reserved */
\r
4088 __IO uint32_t bREFOFSEL : 1; /* Selects REFO nominal frequency */
\r
4089 __I uint32_t bRESERVED2 : 16; /* Reserved */
\r
4092 union { /* CSSTAT Register */
\r
4094 struct { /* CSSTAT Bits */
\r
4095 __I uint32_t bDCO_ON : 1; /* DCO status */
\r
4096 __I uint32_t bDCOBIAS_ON : 1; /* DCO bias status */
\r
4097 __I uint32_t bHFXT_ON : 1; /* HFXT status */
\r
4098 __I uint32_t bHFXT2_ON : 1; /* HFXT2 status */
\r
4099 __I uint32_t bMODOSC_ON : 1; /* MODOSC status */
\r
4100 __I uint32_t bVLO_ON : 1; /* VLO status */
\r
4101 __I uint32_t bLFXT_ON : 1; /* LFXT status */
\r
4102 __I uint32_t bREFO_ON : 1; /* REFO status */
\r
4103 __I uint32_t bRESERVED0 : 8; /* Reserved */
\r
4104 __I uint32_t bACLK_ON : 1; /* ACLK system clock status */
\r
4105 __I uint32_t bMCLK_ON : 1; /* MCLK system clock status */
\r
4106 __I uint32_t bHSMCLK_ON : 1; /* HSMCLK system clock status */
\r
4107 __I uint32_t bSMCLK_ON : 1; /* SMCLK system clock status */
\r
4108 __I uint32_t bMODCLK_ON : 1; /* MODCLK system clock status */
\r
4109 __I uint32_t bVLOCLK_ON : 1; /* VLOCLK system clock status */
\r
4110 __I uint32_t bLFXTCLK_ON : 1; /* LFXTCLK system clock status */
\r
4111 __I uint32_t bREFOCLK_ON : 1; /* REFOCLK system clock status */
\r
4112 __I uint32_t bACLK_READY : 1; /* ACLK Ready status */
\r
4113 __I uint32_t bMCLK_READY : 1; /* MCLK Ready status */
\r
4114 __I uint32_t bHSMCLK_READY : 1; /* HSMCLK Ready status */
\r
4115 __I uint32_t bSMCLK_READY : 1; /* SMCLK Ready status */
\r
4116 __I uint32_t bBCLK_READY : 1; /* BCLK Ready status */
\r
4117 __I uint32_t bRESERVED1 : 3; /* Reserved */
\r
4120 uint8_t RESERVED1[8];
\r
4121 union { /* CSIE Register */
\r
4123 struct { /* CSIE Bits */
\r
4124 __IO uint32_t bLFXTIE : 1; /* LFXT oscillator fault flag interrupt enable */
\r
4125 __IO uint32_t bHFXTIE : 1; /* HFXT oscillator fault flag interrupt enable */
\r
4126 __IO uint32_t bHFXT2IE : 1; /* HFXT2 oscillator fault flag interrupt enable */
\r
4127 __I uint32_t bRESERVED0 : 1; /* Reserved */
\r
4128 __IO uint32_t bDCOMINIE : 1; /* DCO minimum fault flag interrupt enable */
\r
4129 __IO uint32_t bDCOMAXIE : 1; /* DCO maximum fault flag interrupt enable */
\r
4130 __IO uint32_t bDCORIE : 1; /* DCO external resistor fault flag interrupt enable */
\r
4131 __I uint32_t bRESERVED1 : 1; /* Reserved */
\r
4132 __IO uint32_t bFCNTLFIE : 1; /* Start fault counter interrupt enable LFXT */
\r
4133 __IO uint32_t bFCNTHFIE : 1; /* Start fault counter interrupt enable HFXT */
\r
4134 __IO uint32_t bFCNTHF2IE : 1; /* Start fault counter interrupt enable HFXT2 */
\r
4135 __I uint32_t bRESERVED2 : 1; /* Reserved */
\r
4136 __IO uint32_t bPLLOOLIE : 1; /* PLL out-of-lock interrupt enable */
\r
4137 __IO uint32_t bPLLLOSIE : 1; /* PLL loss-of-signal interrupt enable */
\r
4138 __IO uint32_t bPLLOORIE : 1; /* PLL out-of-range interrupt enable */
\r
4139 __IO uint32_t bCALIE : 1; /* REFCNT period counter interrupt enable */
\r
4140 __I uint32_t bRESERVED3 : 16; /* Reserved */
\r
4143 uint8_t RESERVED2[4];
\r
4144 union { /* CSIFG Register */
\r
4146 struct { /* CSIFG Bits */
\r
4147 __I uint32_t bLFXTIFG : 1; /* LFXT oscillator fault flag */
\r
4148 __I uint32_t bHFXTIFG : 1; /* HFXT oscillator fault flag */
\r
4149 __I uint32_t bHFXT2IFG : 1; /* HFXT2 oscillator fault flag */
\r
4150 __I uint32_t bRESERVED0 : 1; /* Reserved */
\r
4151 __I uint32_t bDCOMINIFG : 1; /* DCO minimum fault flag */
\r
4152 __I uint32_t bDCOMAXIFG : 1; /* DCO maximum fault flag */
\r
4153 __I uint32_t bDCORIFG : 1; /* DCO external resistor fault flag */
\r
4154 __I uint32_t bRESERVED1 : 1; /* Reserved */
\r
4155 __I uint32_t bFCNTLFIFG : 1; /* Start fault counter interrupt flag LFXT */
\r
4156 __I uint32_t bFCNTHFIFG : 1; /* Start fault counter interrupt flag HFXT */
\r
4157 __I uint32_t bRESERVED2 : 1; /* Reserved */
\r
4158 __I uint32_t bFCNTHF2IFG : 1; /* Start fault counter interrupt flag HFXT2 */
\r
4159 __I uint32_t bPLLOOLIFG : 1; /* PLL out-of-lock interrupt flag */
\r
4160 __I uint32_t bPLLLOSIFG : 1; /* PLL loss-of-signal interrupt flag */
\r
4161 __I uint32_t bPLLOORIFG : 1; /* PLL out-of-range interrupt flag */
\r
4162 __I uint32_t bCALIFG : 1; /* REFCNT period counter expired */
\r
4163 __I uint32_t bRESERVED3 : 16; /* Reserved */
\r
4166 uint8_t RESERVED3[4];
\r
4167 union { /* CSCLRIFG Register */
\r
4169 struct { /* CSCLRIFG Bits */
\r
4170 __O uint32_t bCLR_LFXTIFG : 1; /* Clear LFXT oscillator fault interrupt flag */
\r
4171 __O uint32_t bCLR_HFXTIFG : 1; /* Clear HFXT oscillator fault interrupt flag */
\r
4172 __O uint32_t bCLR_HFXT2IFG : 1; /* Clear HFXT2 oscillator fault interrupt flag */
\r
4173 __I uint32_t bRESERVED0 : 1; /* Reserved */
\r
4174 __O uint32_t bCLR_DCOMINIFG : 1; /* Clear DCO minimum fault interrupt flag */
\r
4175 __O uint32_t bCLR_DCOMAXIFG : 1; /* Clear DCO maximum fault interrupt flag */
\r
4176 __O uint32_t bCLR_DCORIFG : 1; /* Clear DCO external resistor fault interrupt flag */
\r
4177 __O uint32_t bCLR_CALIFG : 1; /* REFCNT period counter clear interrupt flag */
\r
4178 __O uint32_t bCLR_FCNTLFIFG : 1; /* Start fault counter clear interrupt flag LFXT */
\r
4179 __O uint32_t bCLR_FCNTHFIFG : 1; /* Start fault counter clear interrupt flag HFXT */
\r
4180 __O uint32_t bCLR_FCNTHF2IFG : 1; /* Start fault counter clear interrupt flag HFXT2 */
\r
4181 __I uint32_t bRESERVED1 : 1; /* Reserved */
\r
4182 __O uint32_t bCLR_PLLOOLIFG : 1; /* PLL out-of-lock clear interrupt flag */
\r
4183 __O uint32_t bCLR_PLLLOSIFG : 1; /* PLL loss-of-signal clear interrupt flag */
\r
4184 __O uint32_t bCLR_PLLOORIFG : 1; /* PLL out-of-range clear interrupt flag */
\r
4185 __I uint32_t bRESERVED2 : 17; /* Reserved */
\r
4188 uint8_t RESERVED4[4];
\r
4189 union { /* CSSETIFG Register */
\r
4191 struct { /* CSSETIFG Bits */
\r
4192 __O uint32_t bSET_LFXTIFG : 1; /* Set LFXT oscillator fault interrupt flag */
\r
4193 __O uint32_t bSET_HFXTIFG : 1; /* Set HFXT oscillator fault interrupt flag */
\r
4194 __O uint32_t bSET_HFXT2IFG : 1; /* Set HFXT2 oscillator fault interrupt flag */
\r
4195 __I uint32_t bRESERVED0 : 1; /* Reserved */
\r
4196 __O uint32_t bSET_DCOMINIFG : 1; /* Set DCO minimum fault interrupt flag */
\r
4197 __O uint32_t bSET_DCOMAXIFG : 1; /* Set DCO maximum fault interrupt flag */
\r
4198 __O uint32_t bSET_DCORIFG : 1; /* Set DCO external resistor fault interrupt flag */
\r
4199 __O uint32_t bSET_CALIFG : 1; /* REFCNT period counter set interrupt flag */
\r
4200 __O uint32_t bSET_FCNTLFIFG : 1; /* Start fault counter set interrupt flag LFXT */
\r
4201 __O uint32_t bSET_FCNTHFIFG : 1; /* Start fault counter set interrupt flag HFXT */
\r
4202 __O uint32_t bSET_FCNTHF2IFG : 1; /* Start fault counter set interrupt flag HFXT2 */
\r
4203 __I uint32_t bRESERVED1 : 1; /* Reserved */
\r
4204 __O uint32_t bSET_PLLOOLIFG : 1; /* PLL out-of-lock set interrupt flag */
\r
4205 __O uint32_t bSET_PLLLOSIFG : 1; /* PLL loss-of-signal set interrupt flag */
\r
4206 __O uint32_t bSET_PLLOORIFG : 1; /* PLL out-of-range set interrupt flag */
\r
4207 __I uint32_t bRESERVED2 : 17; /* Reserved */
\r
4210 uint8_t RESERVED5[4];
\r
4211 union { /* CSDCOERCAL Register */
\r
4213 struct { /* CSDCOERCAL Bits */
\r
4214 __IO uint32_t bDCO_TCTRIM : 2; /* DCO Temperature compensation Trim */
\r
4215 __I uint32_t bRESERVED0 : 14; /* Reserved */
\r
4216 __IO uint32_t bDCO_FTRIM : 11; /* DCO frequency trim */
\r
4217 __I uint32_t bRESERVED1 : 5; /* Reserved */
\r
4223 //*****************************************************************************
\r
4225 //*****************************************************************************
\r
4227 union { /* PAIN Register */
\r
4229 struct { /* PAIN Bits */
\r
4230 __I uint16_t bP1IN : 8; /* Port 1 Input */
\r
4231 __I uint16_t bP2IN : 8; /* Port 2 Input */
\r
4234 union { /* PAOUT Register */
\r
4236 struct { /* PAOUT Bits */
\r
4237 __IO uint16_t bP1OUT : 8; /* Port 1 Output */
\r
4238 __IO uint16_t bP2OUT : 8; /* Port 2 Output */
\r
4241 union { /* PADIR Register */
\r
4243 struct { /* PADIR Bits */
\r
4244 __IO uint16_t bP1DIR : 8; /* Port 1 Direction */
\r
4245 __IO uint16_t bP2DIR : 8; /* Port 2 Direction */
\r
4248 union { /* PAREN Register */
\r
4250 struct { /* PAREN Bits */
\r
4251 __IO uint16_t bP1REN : 8; /* Port 1 Resistor Enable */
\r
4252 __IO uint16_t bP2REN : 8; /* Port 2 Resistor Enable */
\r
4255 union { /* PADS Register */
\r
4257 struct { /* PADS Bits */
\r
4258 __IO uint16_t bP1DS : 8; /* Port 1 Drive Strength */
\r
4259 __IO uint16_t bP2DS : 8; /* Port 2 Drive Strength */
\r
4262 union { /* PASEL0 Register */
\r
4264 struct { /* PASEL0 Bits */
\r
4265 __IO uint16_t bP1SEL0 : 8; /* Port 1 Select 0 */
\r
4266 __IO uint16_t bP2SEL0 : 8; /* Port 2 Select 0 */
\r
4269 union { /* PASEL1 Register */
\r
4271 struct { /* PASEL1 Bits */
\r
4272 __IO uint16_t bP1SEL1 : 8; /* Port 1 Select 1 */
\r
4273 __IO uint16_t bP2SEL1 : 8; /* Port 2 Select 1 */
\r
4276 union { /* P1IV Register */
\r
4278 struct { /* P1IV Bits */
\r
4279 __I uint16_t bP1IV : 5; /* Port 1 interrupt vector value */
\r
4280 __I uint16_t bRESERVED0 : 11; /* Reserved */
\r
4283 uint8_t RESERVED0[6];
\r
4284 union { /* PASELC Register */
\r
4286 struct { /* PASELC Bits */
\r
4287 __IO uint16_t bP1SELC : 8; /* Port 1 Complement Select */
\r
4288 __IO uint16_t bP2SELC : 8; /* Port 2 Complement Select */
\r
4291 union { /* PAIES Register */
\r
4293 struct { /* PAIES Bits */
\r
4294 __IO uint16_t bP1IES : 8; /* Port 1 Interrupt Edge Select */
\r
4295 __IO uint16_t bP2IES : 8; /* Port 2 Interrupt Edge Select */
\r
4298 union { /* PAIE Register */
\r
4300 struct { /* PAIE Bits */
\r
4301 __IO uint16_t bP1IE : 8; /* Port 1 Interrupt Enable */
\r
4302 __IO uint16_t bP2IE : 8; /* Port 2 Interrupt Enable */
\r
4305 union { /* PAIFG Register */
\r
4307 struct { /* PAIFG Bits */
\r
4308 __IO uint16_t bP1IFG : 8; /* Port 1 Interrupt Flag */
\r
4309 __IO uint16_t bP2IFG : 8; /* Port 2 Interrupt Flag */
\r
4312 union { /* P2IV Register */
\r
4314 struct { /* P2IV Bits */
\r
4315 __I uint16_t bP2IV : 5; /* Port 2 interrupt vector value */
\r
4316 __I uint16_t bRESERVED0 : 11; /* Reserved */
\r
4319 union { /* PBIN Register */
\r
4321 struct { /* PBIN Bits */
\r
4322 __I uint16_t bP3IN : 8; /* Port 3 Input */
\r
4323 __I uint16_t bP4IN : 8; /* Port 4 Input */
\r
4326 union { /* PBOUT Register */
\r
4328 struct { /* PBOUT Bits */
\r
4329 __IO uint16_t bP3OUT : 8; /* Port 3 Output */
\r
4330 __IO uint16_t bP4OUT : 8; /* Port 4 Output */
\r
4333 union { /* PBDIR Register */
\r
4335 struct { /* PBDIR Bits */
\r
4336 __IO uint16_t bP3DIR : 8; /* Port 3 Direction */
\r
4337 __IO uint16_t bP4DIR : 8; /* Port 4 Direction */
\r
4340 union { /* PBREN Register */
\r
4342 struct { /* PBREN Bits */
\r
4343 __IO uint16_t bP3REN : 8; /* Port 3 Resistor Enable */
\r
4344 __IO uint16_t bP4REN : 8; /* Port 4 Resistor Enable */
\r
4347 union { /* PBDS Register */
\r
4349 struct { /* PBDS Bits */
\r
4350 __IO uint16_t bP3DS : 8; /* Port 3 Drive Strength */
\r
4351 __IO uint16_t bP4DS : 8; /* Port 4 Drive Strength */
\r
4354 union { /* PBSEL0 Register */
\r
4356 struct { /* PBSEL0 Bits */
\r
4357 __IO uint16_t bP3SEL0 : 8; /* Port 3 Select 0 */
\r
4358 __IO uint16_t bP4SEL0 : 8; /* Port 4 Select 0 */
\r
4361 union { /* PBSEL1 Register */
\r
4363 struct { /* PBSEL1 Bits */
\r
4364 __IO uint16_t bP3SEL1 : 8; /* Port 3 Select 1 */
\r
4365 __IO uint16_t bP4SEL1 : 8; /* Port 4 Select 1 */
\r
4368 union { /* P3IV Register */
\r
4370 struct { /* P3IV Bits */
\r
4371 __I uint16_t bP3IV : 5; /* Port 3 interrupt vector value */
\r
4372 __I uint16_t bRESERVED0 : 11; /* Reserved */
\r
4375 uint8_t RESERVED1[6];
\r
4376 union { /* PBSELC Register */
\r
4378 struct { /* PBSELC Bits */
\r
4379 __IO uint16_t bP3SELC : 8; /* Port 3 Complement Select */
\r
4380 __IO uint16_t bP4SELC : 8; /* Port 4 Complement Select */
\r
4383 union { /* PBIES Register */
\r
4385 struct { /* PBIES Bits */
\r
4386 __IO uint16_t bP3IES : 8; /* Port 3 Interrupt Edge Select */
\r
4387 __IO uint16_t bP4IES : 8; /* Port 4 Interrupt Edge Select */
\r
4390 union { /* PBIE Register */
\r
4392 struct { /* PBIE Bits */
\r
4393 __IO uint16_t bP3IE : 8; /* Port 3 Interrupt Enable */
\r
4394 __IO uint16_t bP4IE : 8; /* Port 4 Interrupt Enable */
\r
4397 union { /* PBIFG Register */
\r
4399 struct { /* PBIFG Bits */
\r
4400 __IO uint16_t bP3IFG : 8; /* Port 3 Interrupt Flag */
\r
4401 __IO uint16_t bP4IFG : 8; /* Port 4 Interrupt Flag */
\r
4404 union { /* P4IV Register */
\r
4406 struct { /* P4IV Bits */
\r
4407 __I uint16_t bP4IV : 5; /* Port 4 interrupt vector value */
\r
4408 __I uint16_t bRESERVED0 : 11; /* Reserved */
\r
4411 union { /* PCIN Register */
\r
4413 struct { /* PCIN Bits */
\r
4414 __I uint16_t bP5IN : 8; /* Port 5 Input */
\r
4415 __I uint16_t bP6IN : 8; /* Port 6 Input */
\r
4418 union { /* PCOUT Register */
\r
4420 struct { /* PCOUT Bits */
\r
4421 __IO uint16_t bP5OUT : 8; /* Port 5 Output */
\r
4422 __IO uint16_t bP6OUT : 8; /* Port 6 Output */
\r
4425 union { /* PCDIR Register */
\r
4427 struct { /* PCDIR Bits */
\r
4428 __IO uint16_t bP5DIR : 8; /* Port 5 Direction */
\r
4429 __IO uint16_t bP6DIR : 8; /* Port 6 Direction */
\r
4432 union { /* PCREN Register */
\r
4434 struct { /* PCREN Bits */
\r
4435 __IO uint16_t bP5REN : 8; /* Port 5 Resistor Enable */
\r
4436 __IO uint16_t bP6REN : 8; /* Port 6 Resistor Enable */
\r
4439 union { /* PCDS Register */
\r
4441 struct { /* PCDS Bits */
\r
4442 __IO uint16_t bP5DS : 8; /* Port 5 Drive Strength */
\r
4443 __IO uint16_t bP6DS : 8; /* Port 6 Drive Strength */
\r
4446 union { /* PCSEL0 Register */
\r
4448 struct { /* PCSEL0 Bits */
\r
4449 __IO uint16_t bP5SEL0 : 8; /* Port 5 Select 0 */
\r
4450 __IO uint16_t bP6SEL0 : 8; /* Port 6 Select 0 */
\r
4453 union { /* PCSEL1 Register */
\r
4455 struct { /* PCSEL1 Bits */
\r
4456 __IO uint16_t bP5SEL1 : 8; /* Port 5 Select 1 */
\r
4457 __IO uint16_t bP6SEL1 : 8; /* Port 6 Select 1 */
\r
4460 union { /* P5IV Register */
\r
4462 struct { /* P5IV Bits */
\r
4463 __I uint16_t bP5IV : 5; /* Port 5 interrupt vector value */
\r
4464 __I uint16_t bRESERVED0 : 11; /* Reserved */
\r
4467 uint8_t RESERVED2[6];
\r
4468 union { /* PCSELC Register */
\r
4470 struct { /* PCSELC Bits */
\r
4471 __IO uint16_t bP5SELC : 8; /* Port 5 Complement Select */
\r
4472 __IO uint16_t bP6SELC : 8; /* Port 6 Complement Select */
\r
4475 union { /* PCIES Register */
\r
4477 struct { /* PCIES Bits */
\r
4478 __IO uint16_t bP5IES : 8; /* Port 5 Interrupt Edge Select */
\r
4479 __IO uint16_t bP6IES : 8; /* Port 6 Interrupt Edge Select */
\r
4482 union { /* PCIE Register */
\r
4484 struct { /* PCIE Bits */
\r
4485 __IO uint16_t bP5IE : 8; /* Port 5 Interrupt Enable */
\r
4486 __IO uint16_t bP6IE : 8; /* Port 6 Interrupt Enable */
\r
4489 union { /* PCIFG Register */
\r
4491 struct { /* PCIFG Bits */
\r
4492 __IO uint16_t bP5IFG : 8; /* Port 5 Interrupt Flag */
\r
4493 __IO uint16_t bP6IFG : 8; /* Port 6 Interrupt Flag */
\r
4496 union { /* P6IV Register */
\r
4498 struct { /* P6IV Bits */
\r
4499 __I uint16_t bP6IV : 5; /* Port 6 interrupt vector value */
\r
4500 __I uint16_t bRESERVED0 : 11; /* Reserved */
\r
4503 union { /* PDIN Register */
\r
4505 struct { /* PDIN Bits */
\r
4506 __I uint16_t bP7IN : 8; /* Port 7 Input */
\r
4507 __I uint16_t bP8IN : 8; /* Port 8 Input */
\r
4510 union { /* PDOUT Register */
\r
4512 struct { /* PDOUT Bits */
\r
4513 __IO uint16_t bP7OUT : 8; /* Port 7 Output */
\r
4514 __IO uint16_t bP8OUT : 8; /* Port 8 Output */
\r
4517 union { /* PDDIR Register */
\r
4519 struct { /* PDDIR Bits */
\r
4520 __IO uint16_t bP7DIR : 8; /* Port 7 Direction */
\r
4521 __IO uint16_t bP8DIR : 8; /* Port 8 Direction */
\r
4524 union { /* PDREN Register */
\r
4526 struct { /* PDREN Bits */
\r
4527 __IO uint16_t bP7REN : 8; /* Port 7 Resistor Enable */
\r
4528 __IO uint16_t bP8REN : 8; /* Port 8 Resistor Enable */
\r
4531 union { /* PDDS Register */
\r
4533 struct { /* PDDS Bits */
\r
4534 __IO uint16_t bP7DS : 8; /* Port 7 Drive Strength */
\r
4535 __IO uint16_t bP8DS : 8; /* Port 8 Drive Strength */
\r
4538 union { /* PDSEL0 Register */
\r
4540 struct { /* PDSEL0 Bits */
\r
4541 __IO uint16_t bP7SEL0 : 8; /* Port 7 Select 0 */
\r
4542 __IO uint16_t bP8SEL0 : 8; /* Port 8 Select 0 */
\r
4545 union { /* PDSEL1 Register */
\r
4547 struct { /* PDSEL1 Bits */
\r
4548 __IO uint16_t bP7SEL1 : 8; /* Port 7 Select 1 */
\r
4549 __IO uint16_t bP8SEL1 : 8; /* Port 8 Select 1 */
\r
4552 union { /* P7IV Register */
\r
4554 struct { /* P7IV Bits */
\r
4555 __I uint16_t bP7IV : 5; /* Port 7 interrupt vector value */
\r
4556 __I uint16_t bRESERVED0 : 11; /* Reserved */
\r
4559 uint8_t RESERVED3[6];
\r
4560 union { /* PDSELC Register */
\r
4562 struct { /* PDSELC Bits */
\r
4563 __IO uint16_t bP7SELC : 8; /* Port 7 Complement Select */
\r
4564 __IO uint16_t bP8SELC : 8; /* Port 8 Complement Select */
\r
4567 union { /* PDIES Register */
\r
4569 struct { /* PDIES Bits */
\r
4570 __IO uint16_t bP7IES : 8; /* Port 7 Interrupt Edge Select */
\r
4571 __IO uint16_t bP8IES : 8; /* Port 8 Interrupt Edge Select */
\r
4574 union { /* PDIE Register */
\r
4576 struct { /* PDIE Bits */
\r
4577 __IO uint16_t bP7IE : 8; /* Port 7 Interrupt Enable */
\r
4578 __IO uint16_t bP8IE : 8; /* Port 8 Interrupt Enable */
\r
4581 union { /* PDIFG Register */
\r
4583 struct { /* PDIFG Bits */
\r
4584 __IO uint16_t bP7IFG : 8; /* Port 7 Interrupt Flag */
\r
4585 __IO uint16_t bP8IFG : 8; /* Port 8 Interrupt Flag */
\r
4588 union { /* P8IV Register */
\r
4590 struct { /* P8IV Bits */
\r
4591 __I uint16_t bP8IV : 5; /* Port 8 interrupt vector value */
\r
4592 __I uint16_t bRESERVED0 : 11; /* Reserved */
\r
4595 union { /* PEIN Register */
\r
4597 struct { /* PEIN Bits */
\r
4598 __I uint16_t bP9IN : 8; /* Port 9 Input */
\r
4599 __I uint16_t bP10IN : 8; /* Port 10 Input */
\r
4602 union { /* PEOUT Register */
\r
4604 struct { /* PEOUT Bits */
\r
4605 __IO uint16_t bP9OUT : 8; /* Port 9 Output */
\r
4606 __IO uint16_t bP10OUT : 8; /* Port 10 Output */
\r
4609 union { /* PEDIR Register */
\r
4611 struct { /* PEDIR Bits */
\r
4612 __IO uint16_t bP9DIR : 8; /* Port 9 Direction */
\r
4613 __IO uint16_t bP10DIR : 8; /* Port 10 Direction */
\r
4616 union { /* PEREN Register */
\r
4618 struct { /* PEREN Bits */
\r
4619 __IO uint16_t bP9REN : 8; /* Port 9 Resistor Enable */
\r
4620 __IO uint16_t bP10REN : 8; /* Port 10 Resistor Enable */
\r
4623 union { /* PEDS Register */
\r
4625 struct { /* PEDS Bits */
\r
4626 __IO uint16_t bP9DS : 8; /* Port 9 Drive Strength */
\r
4627 __IO uint16_t bP10DS : 8; /* Port 10 Drive Strength */
\r
4630 union { /* PESEL0 Register */
\r
4632 struct { /* PESEL0 Bits */
\r
4633 __IO uint16_t bP9SEL0 : 8; /* Port 9 Select 0 */
\r
4634 __IO uint16_t bP10SEL0 : 8; /* Port 10 Select 0 */
\r
4637 union { /* PESEL1 Register */
\r
4639 struct { /* PESEL1 Bits */
\r
4640 __IO uint16_t bP9SEL1 : 8; /* Port 9 Select 1 */
\r
4641 __IO uint16_t bP10SEL1 : 8; /* Port 10 Select 1 */
\r
4644 union { /* P9IV Register */
\r
4646 struct { /* P9IV Bits */
\r
4647 __I uint16_t bP9IV : 5; /* Port 9 interrupt vector value */
\r
4648 __I uint16_t bRESERVED0 : 11; /* Reserved */
\r
4651 uint8_t RESERVED4[6];
\r
4652 union { /* PESELC Register */
\r
4654 struct { /* PESELC Bits */
\r
4655 __IO uint16_t bP9SELC : 8; /* Port 9 Complement Select */
\r
4656 __IO uint16_t bP10SELC : 8; /* Port 10 Complement Select */
\r
4659 union { /* PEIES Register */
\r
4661 struct { /* PEIES Bits */
\r
4662 __IO uint16_t bP9IES : 8; /* Port 9 Interrupt Edge Select */
\r
4663 __IO uint16_t bP10IES : 8; /* Port 10 Interrupt Edge Select */
\r
4666 union { /* PEIE Register */
\r
4668 struct { /* PEIE Bits */
\r
4669 __IO uint16_t bP9IE : 8; /* Port 9 Interrupt Enable */
\r
4670 __IO uint16_t bP10IE : 8; /* Port 10 Interrupt Enable */
\r
4673 union { /* PEIFG Register */
\r
4675 struct { /* PEIFG Bits */
\r
4676 __IO uint16_t bP9IFG : 8; /* Port 9 Interrupt Flag */
\r
4677 __IO uint16_t bP10IFG : 8; /* Port 10 Interrupt Flag */
\r
4680 union { /* P10IV Register */
\r
4682 struct { /* P10IV Bits */
\r
4683 __I uint16_t bP10IV : 5; /* Port 10 interrupt vector value */
\r
4684 __I uint16_t bRESERVED0 : 11; /* Reserved */
\r
4687 uint8_t RESERVED5[128];
\r
4688 __I uint16_t rPJIN; /* Port J Input */
\r
4689 __IO uint16_t rPJOUT; /* Port J Output */
\r
4690 __IO uint16_t rPJDIR; /* Port J Direction */
\r
4691 __IO uint16_t rPJREN; /* Port J Resistor Enable */
\r
4692 __IO uint16_t rPJDS; /* Port J Drive Strength */
\r
4693 __IO uint16_t rPJSEL0; /* Port J Select 0 */
\r
4694 __IO uint16_t rPJSEL1; /* Port J Select 1 */
\r
4695 uint8_t RESERVED6[8];
\r
4696 __IO uint16_t rPJSELC; /* Port J Complement Select */
\r
4700 //*****************************************************************************
\r
4702 //*****************************************************************************
\r
4704 union { /* DMA_DEVICE_CFG Register */
\r
4706 struct { /* DMA_DEVICE_CFG Bits */
\r
4707 __I uint32_t bNUM_DMA_CHANNELS : 8; /* Number of DMA channels available */
\r
4708 __I uint32_t bNUM_SRC_PER_CHANNEL : 8; /* Number of DMA sources per channel */
\r
4709 __I uint32_t bRESERVED0 : 16; /* Reserved */
\r
4712 union { /* DMA_SW_CHTRIG Register */
\r
4714 struct { /* DMA_SW_CHTRIG Bits */
\r
4715 __IO uint32_t bCH0 : 1; /* Write 1, triggers DMA_CHANNEL0 */
\r
4716 __IO uint32_t bCH1 : 1; /* Write 1, triggers DMA_CHANNEL1 */
\r
4717 __IO uint32_t bCH2 : 1; /* Write 1, triggers DMA_CHANNEL2 */
\r
4718 __IO uint32_t bCH3 : 1; /* Write 1, triggers DMA_CHANNEL3 */
\r
4719 __IO uint32_t bCH4 : 1; /* Write 1, triggers DMA_CHANNEL4 */
\r
4720 __IO uint32_t bCH5 : 1; /* Write 1, triggers DMA_CHANNEL5 */
\r
4721 __IO uint32_t bCH6 : 1; /* Write 1, triggers DMA_CHANNEL6 */
\r
4722 __IO uint32_t bCH7 : 1; /* Write 1, triggers DMA_CHANNEL7 */
\r
4723 __IO uint32_t bCH8 : 1; /* Write 1, triggers DMA_CHANNEL8 */
\r
4724 __IO uint32_t bCH9 : 1; /* Write 1, triggers DMA_CHANNEL9 */
\r
4725 __IO uint32_t bCH10 : 1; /* Write 1, triggers DMA_CHANNEL10 */
\r
4726 __IO uint32_t bCH11 : 1; /* Write 1, triggers DMA_CHANNEL11 */
\r
4727 __IO uint32_t bCH12 : 1; /* Write 1, triggers DMA_CHANNEL12 */
\r
4728 __IO uint32_t bCH13 : 1; /* Write 1, triggers DMA_CHANNEL13 */
\r
4729 __IO uint32_t bCH14 : 1; /* Write 1, triggers DMA_CHANNEL14 */
\r
4730 __IO uint32_t bCH15 : 1; /* Write 1, triggers DMA_CHANNEL15 */
\r
4731 __IO uint32_t bCH16 : 1; /* Write 1, triggers DMA_CHANNEL16 */
\r
4732 __IO uint32_t bCH17 : 1; /* Write 1, triggers DMA_CHANNEL17 */
\r
4733 __IO uint32_t bCH18 : 1; /* Write 1, triggers DMA_CHANNEL18 */
\r
4734 __IO uint32_t bCH19 : 1; /* Write 1, triggers DMA_CHANNEL19 */
\r
4735 __IO uint32_t bCH20 : 1; /* Write 1, triggers DMA_CHANNEL20 */
\r
4736 __IO uint32_t bCH21 : 1; /* Write 1, triggers DMA_CHANNEL21 */
\r
4737 __IO uint32_t bCH22 : 1; /* Write 1, triggers DMA_CHANNEL22 */
\r
4738 __IO uint32_t bCH23 : 1; /* Write 1, triggers DMA_CHANNEL23 */
\r
4739 __IO uint32_t bCH24 : 1; /* Write 1, triggers DMA_CHANNEL24 */
\r
4740 __IO uint32_t bCH25 : 1; /* Write 1, triggers DMA_CHANNEL25 */
\r
4741 __IO uint32_t bCH26 : 1; /* Write 1, triggers DMA_CHANNEL26 */
\r
4742 __IO uint32_t bCH27 : 1; /* Write 1, triggers DMA_CHANNEL27 */
\r
4743 __IO uint32_t bCH28 : 1; /* Write 1, triggers DMA_CHANNEL28 */
\r
4744 __IO uint32_t bCH29 : 1; /* Write 1, triggers DMA_CHANNEL29 */
\r
4745 __IO uint32_t bCH30 : 1; /* Write 1, triggers DMA_CHANNEL30 */
\r
4746 __IO uint32_t bCH31 : 1; /* Write 1, triggers DMA_CHANNEL31 */
\r
4749 uint8_t RESERVED0[8];
\r
4750 union { /* DMA_CH0_SRCCFG Register */
\r
4752 struct { /* DMA_CH0_SRCCFG Bits */
\r
4753 __IO uint32_t bDMA_SRC : 8; /* Device level DMA source mapping to channel input */
\r
4754 __I uint32_t bRESERVED0 : 24; /* Reserved */
\r
4757 union { /* DMA_CH1_SRCCFG Register */
\r
4759 struct { /* DMA_CH1_SRCCFG Bits */
\r
4760 __IO uint32_t bDMA_SRC : 8; /* Device level DMA source mapping to channel input */
\r
4761 __I uint32_t bRESERVED0 : 24; /* Reserved */
\r
4764 union { /* DMA_CH2_SRCCFG Register */
\r
4766 struct { /* DMA_CH2_SRCCFG Bits */
\r
4767 __IO uint32_t bDMA_SRC : 8; /* Device level DMA source mapping to channel input */
\r
4768 __I uint32_t bRESERVED0 : 24; /* Reserved */
\r
4771 union { /* DMA_CH3_SRCCFG Register */
\r
4773 struct { /* DMA_CH3_SRCCFG Bits */
\r
4774 __IO uint32_t bDMA_SRC : 8; /* Device level DMA source mapping to channel input */
\r
4775 __I uint32_t bRESERVED0 : 24; /* Reserved */
\r
4778 union { /* DMA_CH4_SRCCFG Register */
\r
4780 struct { /* DMA_CH4_SRCCFG Bits */
\r
4781 __IO uint32_t bDMA_SRC : 8; /* Device level DMA source mapping to channel input */
\r
4782 __I uint32_t bRESERVED0 : 24; /* Reserved */
\r
4785 union { /* DMA_CH5_SRCCFG Register */
\r
4787 struct { /* DMA_CH5_SRCCFG Bits */
\r
4788 __IO uint32_t bDMA_SRC : 8; /* Device level DMA source mapping to channel input */
\r
4789 __I uint32_t bRESERVED0 : 24; /* Reserved */
\r
4792 union { /* DMA_CH6_SRCCFG Register */
\r
4794 struct { /* DMA_CH6_SRCCFG Bits */
\r
4795 __IO uint32_t bDMA_SRC : 8; /* Device level DMA source mapping to channel input */
\r
4796 __I uint32_t bRESERVED0 : 24; /* Reserved */
\r
4799 union { /* DMA_CH7_SRCCFG Register */
\r
4801 struct { /* DMA_CH7_SRCCFG Bits */
\r
4802 __IO uint32_t bDMA_SRC : 8; /* Device level DMA source mapping to channel input */
\r
4803 __I uint32_t bRESERVED0 : 24; /* Reserved */
\r
4806 union { /* DMA_CH8_SRCCFG Register */
\r
4808 struct { /* DMA_CH8_SRCCFG Bits */
\r
4809 __IO uint32_t bDMA_SRC : 8; /* Device level DMA source mapping to channel input */
\r
4810 __I uint32_t bRESERVED0 : 24; /* Reserved */
\r
4813 union { /* DMA_CH9_SRCCFG Register */
\r
4815 struct { /* DMA_CH9_SRCCFG Bits */
\r
4816 __IO uint32_t bDMA_SRC : 8; /* Device level DMA source mapping to channel input */
\r
4817 __I uint32_t bRESERVED0 : 24; /* Reserved */
\r
4820 union { /* DMA_CH10_SRCCFG Register */
\r
4822 struct { /* DMA_CH10_SRCCFG Bits */
\r
4823 __IO uint32_t bDMA_SRC : 8; /* Device level DMA source mapping to channel input */
\r
4824 __I uint32_t bRESERVED0 : 24; /* Reserved */
\r
4827 union { /* DMA_CH11_SRCCFG Register */
\r
4829 struct { /* DMA_CH11_SRCCFG Bits */
\r
4830 __IO uint32_t bDMA_SRC : 8; /* Device level DMA source mapping to channel input */
\r
4831 __I uint32_t bRESERVED0 : 24; /* Reserved */
\r
4834 union { /* DMA_CH12_SRCCFG Register */
\r
4836 struct { /* DMA_CH12_SRCCFG Bits */
\r
4837 __IO uint32_t bDMA_SRC : 8; /* Device level DMA source mapping to channel input */
\r
4838 __I uint32_t bRESERVED0 : 24; /* Reserved */
\r
4841 union { /* DMA_CH13_SRCCFG Register */
\r
4843 struct { /* DMA_CH13_SRCCFG Bits */
\r
4844 __IO uint32_t bDMA_SRC : 8; /* Device level DMA source mapping to channel input */
\r
4845 __I uint32_t bRESERVED0 : 24; /* Reserved */
\r
4848 union { /* DMA_CH14_SRCCFG Register */
\r
4850 struct { /* DMA_CH14_SRCCFG Bits */
\r
4851 __IO uint32_t bDMA_SRC : 8; /* Device level DMA source mapping to channel input */
\r
4852 __I uint32_t bRESERVED0 : 24; /* Reserved */
\r
4855 union { /* DMA_CH15_SRCCFG Register */
\r
4857 struct { /* DMA_CH15_SRCCFG Bits */
\r
4858 __IO uint32_t bDMA_SRC : 8; /* Device level DMA source mapping to channel input */
\r
4859 __I uint32_t bRESERVED0 : 24; /* Reserved */
\r
4862 union { /* DMA_CH16_SRCCFG Register */
\r
4864 struct { /* DMA_CH16_SRCCFG Bits */
\r
4865 __IO uint32_t bDMA_SRC : 8; /* Device level DMA source mapping to channel input */
\r
4866 __I uint32_t bRESERVED0 : 24; /* Reserved */
\r
4869 union { /* DMA_CH17_SRCCFG Register */
\r
4871 struct { /* DMA_CH17_SRCCFG Bits */
\r
4872 __IO uint32_t bDMA_SRC : 8; /* Device level DMA source mapping to channel input */
\r
4873 __I uint32_t bRESERVED0 : 24; /* Reserved */
\r
4876 union { /* DMA_CH18_SRCCFG Register */
\r
4878 struct { /* DMA_CH18_SRCCFG Bits */
\r
4879 __IO uint32_t bDMA_SRC : 8; /* Device level DMA source mapping to channel input */
\r
4880 __I uint32_t bRESERVED0 : 24; /* Reserved */
\r
4883 union { /* DMA_CH19_SRCCFG Register */
\r
4885 struct { /* DMA_CH19_SRCCFG Bits */
\r
4886 __IO uint32_t bDMA_SRC : 8; /* Device level DMA source mapping to channel input */
\r
4887 __I uint32_t bRESERVED0 : 24; /* Reserved */
\r
4890 union { /* DMA_CH20_SRCCFG Register */
\r
4892 struct { /* DMA_CH20_SRCCFG Bits */
\r
4893 __IO uint32_t bDMA_SRC : 8; /* Device level DMA source mapping to channel input */
\r
4894 __I uint32_t bRESERVED0 : 24; /* Reserved */
\r
4897 union { /* DMA_CH21_SRCCFG Register */
\r
4899 struct { /* DMA_CH21_SRCCFG Bits */
\r
4900 __IO uint32_t bDMA_SRC : 8; /* Device level DMA source mapping to channel input */
\r
4901 __I uint32_t bRESERVED0 : 24; /* Reserved */
\r
4904 union { /* DMA_CH22_SRCCFG Register */
\r
4906 struct { /* DMA_CH22_SRCCFG Bits */
\r
4907 __IO uint32_t bDMA_SRC : 8; /* Device level DMA source mapping to channel input */
\r
4908 __I uint32_t bRESERVED0 : 24; /* Reserved */
\r
4911 union { /* DMA_CH23_SRCCFG Register */
\r
4913 struct { /* DMA_CH23_SRCCFG Bits */
\r
4914 __IO uint32_t bDMA_SRC : 8; /* Device level DMA source mapping to channel input */
\r
4915 __I uint32_t bRESERVED0 : 24; /* Reserved */
\r
4918 union { /* DMA_CH24_SRCCFG Register */
\r
4920 struct { /* DMA_CH24_SRCCFG Bits */
\r
4921 __IO uint32_t bDMA_SRC : 8; /* Device level DMA source mapping to channel input */
\r
4922 __I uint32_t bRESERVED0 : 24; /* Reserved */
\r
4925 union { /* DMA_CH25_SRCCFG Register */
\r
4927 struct { /* DMA_CH25_SRCCFG Bits */
\r
4928 __IO uint32_t bDMA_SRC : 8; /* Device level DMA source mapping to channel input */
\r
4929 __I uint32_t bRESERVED0 : 24; /* Reserved */
\r
4932 union { /* DMA_CH26_SRCCFG Register */
\r
4934 struct { /* DMA_CH26_SRCCFG Bits */
\r
4935 __IO uint32_t bDMA_SRC : 8; /* Device level DMA source mapping to channel input */
\r
4936 __I uint32_t bRESERVED0 : 24; /* Reserved */
\r
4939 union { /* DMA_CH27_SRCCFG Register */
\r
4941 struct { /* DMA_CH27_SRCCFG Bits */
\r
4942 __IO uint32_t bDMA_SRC : 8; /* Device level DMA source mapping to channel input */
\r
4943 __I uint32_t bRESERVED0 : 24; /* Reserved */
\r
4946 union { /* DMA_CH28_SRCCFG Register */
\r
4948 struct { /* DMA_CH28_SRCCFG Bits */
\r
4949 __IO uint32_t bDMA_SRC : 8; /* Device level DMA source mapping to channel input */
\r
4950 __I uint32_t bRESERVED0 : 24; /* Reserved */
\r
4953 union { /* DMA_CH29_SRCCFG Register */
\r
4955 struct { /* DMA_CH29_SRCCFG Bits */
\r
4956 __IO uint32_t bDMA_SRC : 8; /* Device level DMA source mapping to channel input */
\r
4957 __I uint32_t bRESERVED0 : 24; /* Reserved */
\r
4960 union { /* DMA_CH30_SRCCFG Register */
\r
4962 struct { /* DMA_CH30_SRCCFG Bits */
\r
4963 __IO uint32_t bDMA_SRC : 8; /* Device level DMA source mapping to channel input */
\r
4964 __I uint32_t bRESERVED0 : 24; /* Reserved */
\r
4967 union { /* DMA_CH31_SRCCFG Register */
\r
4969 struct { /* DMA_CH31_SRCCFG Bits */
\r
4970 __IO uint32_t bDMA_SRC : 8; /* Device level DMA source mapping to channel input */
\r
4971 __I uint32_t bRESERVED0 : 24; /* Reserved */
\r
4974 uint8_t RESERVED1[112];
\r
4975 union { /* DMA_INT1_SRCCFG Register */
\r
4977 struct { /* DMA_INT1_SRCCFG Bits */
\r
4978 __IO uint32_t bINT_SRC : 5; /* Controls which channel's completion event is mapped as a source of this Interrupt */
\r
4979 __IO uint32_t bEN : 1; /* Enables DMA_INT1 mapping */
\r
4980 __I uint32_t bRESERVED0 : 26; /* Reserved */
\r
4983 union { /* DMA_INT2_SRCCFG Register */
\r
4985 struct { /* DMA_INT2_SRCCFG Bits */
\r
4986 __IO uint32_t bINT_SRC : 5; /* Controls which channel's completion event is mapped as a source of this Interrupt */
\r
4987 __IO uint32_t bEN : 1; /* Enables DMA_INT2 mapping */
\r
4988 __I uint32_t bRESERVED0 : 26; /* Reserved */
\r
4991 union { /* DMA_INT3_SRCCFG Register */
\r
4993 struct { /* DMA_INT3_SRCCFG Bits */
\r
4994 __IO uint32_t bINT_SRC : 5; /* Controls which channel's completion event is mapped as a source of this Interrupt */
\r
4995 __IO uint32_t bEN : 1; /* Enables DMA_INT3 mapping */
\r
4996 __I uint32_t bRESERVED0 : 26; /* Reserved */
\r
4999 uint8_t RESERVED2[4];
\r
5000 union { /* DMA_INT0_SRCFLG Register */
\r
5002 struct { /* DMA_INT0_SRCFLG Bits */
\r
5003 __I uint32_t bCH0 : 1; /* Channel 0 was the source of DMA_INT0 */
\r
5004 __I uint32_t bCH1 : 1; /* Channel 1 was the source of DMA_INT0 */
\r
5005 __I uint32_t bCH2 : 1; /* Channel 2 was the source of DMA_INT0 */
\r
5006 __I uint32_t bCH3 : 1; /* Channel 3 was the source of DMA_INT0 */
\r
5007 __I uint32_t bCH4 : 1; /* Channel 4 was the source of DMA_INT0 */
\r
5008 __I uint32_t bCH5 : 1; /* Channel 5 was the source of DMA_INT0 */
\r
5009 __I uint32_t bCH6 : 1; /* Channel 6 was the source of DMA_INT0 */
\r
5010 __I uint32_t bCH7 : 1; /* Channel 7 was the source of DMA_INT0 */
\r
5011 __I uint32_t bCH8 : 1; /* Channel 8 was the source of DMA_INT0 */
\r
5012 __I uint32_t bCH9 : 1; /* Channel 9 was the source of DMA_INT0 */
\r
5013 __I uint32_t bCH10 : 1; /* Channel 10 was the source of DMA_INT0 */
\r
5014 __I uint32_t bCH11 : 1; /* Channel 11 was the source of DMA_INT0 */
\r
5015 __I uint32_t bCH12 : 1; /* Channel 12 was the source of DMA_INT0 */
\r
5016 __I uint32_t bCH13 : 1; /* Channel 13 was the source of DMA_INT0 */
\r
5017 __I uint32_t bCH14 : 1; /* Channel 14 was the source of DMA_INT0 */
\r
5018 __I uint32_t bCH15 : 1; /* Channel 15 was the source of DMA_INT0 */
\r
5019 __I uint32_t bCH16 : 1; /* Channel 16 was the source of DMA_INT0 */
\r
5020 __I uint32_t bCH17 : 1; /* Channel 17 was the source of DMA_INT0 */
\r
5021 __I uint32_t bCH18 : 1; /* Channel 18 was the source of DMA_INT0 */
\r
5022 __I uint32_t bCH19 : 1; /* Channel 19 was the source of DMA_INT0 */
\r
5023 __I uint32_t bCH20 : 1; /* Channel 20 was the source of DMA_INT0 */
\r
5024 __I uint32_t bCH21 : 1; /* Channel 21 was the source of DMA_INT0 */
\r
5025 __I uint32_t bCH22 : 1; /* Channel 22 was the source of DMA_INT0 */
\r
5026 __I uint32_t bCH23 : 1; /* Channel 23 was the source of DMA_INT0 */
\r
5027 __I uint32_t bCH24 : 1; /* Channel 24 was the source of DMA_INT0 */
\r
5028 __I uint32_t bCH25 : 1; /* Channel 25 was the source of DMA_INT0 */
\r
5029 __I uint32_t bCH26 : 1; /* Channel 26 was the source of DMA_INT0 */
\r
5030 __I uint32_t bCH27 : 1; /* Channel 27 was the source of DMA_INT0 */
\r
5031 __I uint32_t bCH28 : 1; /* Channel 28 was the source of DMA_INT0 */
\r
5032 __I uint32_t bCH29 : 1; /* Channel 29 was the source of DMA_INT0 */
\r
5033 __I uint32_t bCH30 : 1; /* Channel 30 was the source of DMA_INT0 */
\r
5034 __I uint32_t bCH31 : 1; /* Channel 31 was the source of DMA_INT0 */
\r
5037 union { /* DMA_INT0_CLRFLG Register */
\r
5039 struct { /* DMA_INT0_CLRFLG Bits */
\r
5040 __O uint32_t bCH0 : 1; /* Clear corresponding DMA_INT0_SRCFLG_REG */
\r
5041 __O uint32_t bCH1 : 1; /* Clear corresponding DMA_INT0_SRCFLG_REG */
\r
5042 __O uint32_t bCH2 : 1; /* Clear corresponding DMA_INT0_SRCFLG_REG */
\r
5043 __O uint32_t bCH3 : 1; /* Clear corresponding DMA_INT0_SRCFLG_REG */
\r
5044 __O uint32_t bCH4 : 1; /* Clear corresponding DMA_INT0_SRCFLG_REG */
\r
5045 __O uint32_t bCH5 : 1; /* Clear corresponding DMA_INT0_SRCFLG_REG */
\r
5046 __O uint32_t bCH6 : 1; /* Clear corresponding DMA_INT0_SRCFLG_REG */
\r
5047 __O uint32_t bCH7 : 1; /* Clear corresponding DMA_INT0_SRCFLG_REG */
\r
5048 __O uint32_t bCH8 : 1; /* Clear corresponding DMA_INT0_SRCFLG_REG */
\r
5049 __O uint32_t bCH9 : 1; /* Clear corresponding DMA_INT0_SRCFLG_REG */
\r
5050 __O uint32_t bCH10 : 1; /* Clear corresponding DMA_INT0_SRCFLG_REG */
\r
5051 __O uint32_t bCH11 : 1; /* Clear corresponding DMA_INT0_SRCFLG_REG */
\r
5052 __O uint32_t bCH12 : 1; /* Clear corresponding DMA_INT0_SRCFLG_REG */
\r
5053 __O uint32_t bCH13 : 1; /* Clear corresponding DMA_INT0_SRCFLG_REG */
\r
5054 __O uint32_t bCH14 : 1; /* Clear corresponding DMA_INT0_SRCFLG_REG */
\r
5055 __O uint32_t bCH15 : 1; /* Clear corresponding DMA_INT0_SRCFLG_REG */
\r
5056 __O uint32_t bCH16 : 1; /* Clear corresponding DMA_INT0_SRCFLG_REG */
\r
5057 __O uint32_t bCH17 : 1; /* Clear corresponding DMA_INT0_SRCFLG_REG */
\r
5058 __O uint32_t bCH18 : 1; /* Clear corresponding DMA_INT0_SRCFLG_REG */
\r
5059 __O uint32_t bCH19 : 1; /* Clear corresponding DMA_INT0_SRCFLG_REG */
\r
5060 __O uint32_t bCH20 : 1; /* Clear corresponding DMA_INT0_SRCFLG_REG */
\r
5061 __O uint32_t bCH21 : 1; /* Clear corresponding DMA_INT0_SRCFLG_REG */
\r
5062 __O uint32_t bCH22 : 1; /* Clear corresponding DMA_INT0_SRCFLG_REG */
\r
5063 __O uint32_t bCH23 : 1; /* Clear corresponding DMA_INT0_SRCFLG_REG */
\r
5064 __O uint32_t bCH24 : 1; /* Clear corresponding DMA_INT0_SRCFLG_REG */
\r
5065 __O uint32_t bCH25 : 1; /* Clear corresponding DMA_INT0_SRCFLG_REG */
\r
5066 __O uint32_t bCH26 : 1; /* Clear corresponding DMA_INT0_SRCFLG_REG */
\r
5067 __O uint32_t bCH27 : 1; /* Clear corresponding DMA_INT0_SRCFLG_REG */
\r
5068 __O uint32_t bCH28 : 1; /* Clear corresponding DMA_INT0_SRCFLG_REG */
\r
5069 __O uint32_t bCH29 : 1; /* Clear corresponding DMA_INT0_SRCFLG_REG */
\r
5070 __O uint32_t bCH30 : 1; /* Clear corresponding DMA_INT0_SRCFLG_REG */
\r
5071 __O uint32_t bCH31 : 1; /* Clear corresponding DMA_INT0_SRCFLG_REG */
\r
5074 uint8_t RESERVED3[3816];
\r
5075 union { /* DMA_STAT Register */
\r
5077 struct { /* DMA_STAT Bits */
\r
5078 __I uint32_t bMASTEN : 1; /* */
\r
5079 __I uint32_t bRESERVED0 : 3; /* Reserved */
\r
5080 __I uint32_t b : 4; /* */
\r
5081 __I uint32_t bRESERVED1 : 8; /* Reserved */
\r
5082 __I uint32_t bRESERVED2 : 7; /* Reserved */
\r
5085 union { /* DMA_CFG Register */
\r
5087 struct { /* DMA_CFG Bits */
\r
5088 __O uint32_t b : 1; /* */
\r
5089 __O uint32_t bRESERVED0 : 4; /* Reserved */
\r
5090 __O uint32_t bRESERVED1 : 24; /* Reserved */
\r
5093 union { /* DMA_CTLBASE Register */
\r
5095 struct { /* DMA_CTLBASE Bits */
\r
5096 __I uint32_t bRESERVED0 : 5; /* Reserved */
\r
5097 __IO uint32_t b : 27; /* */
\r
5100 __I uint32_t rATLBASE; /* Channel Alternate Control Data Base Pointer Register */
\r
5101 __I uint32_t rWAITSTAT; /* Channel Wait on Request Status Register */
\r
5102 __O uint32_t rSWREQ; /* Channel Software Request Register */
\r
5103 __IO uint32_t rUSEBURSTSET; /* Channel Useburst Set Register */
\r
5104 __O uint32_t rUSEBURSTCLR; /* Channel Useburst Clear Register */
\r
5105 __IO uint32_t rREQMASKSET; /* Channel Request Mask Set Register */
\r
5106 __O uint32_t rREQMASKCLR; /* Channel Request Mask Clear Register */
\r
5107 __IO uint32_t rENASET; /* Channel Enable Set Register */
\r
5108 __O uint32_t rENACLR; /* Channel Enable Clear Register */
\r
5109 __IO uint32_t rALTSET; /* Channel Primary-Alternate Set Register */
\r
5110 __O uint32_t rALTCLR; /* Channel Primary-Alternate Clear Register */
\r
5111 __IO uint32_t rPRIOSET; /* Channel Priority Set Register */
\r
5112 __O uint32_t rPRIOCLR; /* Channel Priority Clear Register */
\r
5113 uint8_t RESERVED4[12];
\r
5114 union { /* DMA_ERRCLR Register */
\r
5116 struct { /* DMA_ERRCLR Bits */
\r
5117 __IO uint32_t b : 1; /* */
\r
5118 __I uint32_t bRESERVED0 : 31; /* Reserved */
\r
5124 //*****************************************************************************
\r
5125 // EUSCI_A0 Registers
\r
5126 //*****************************************************************************
\r
5128 union { /* UCA0CTLW0 Register */
\r
5130 struct { /* UCA0CTLW0 Bits */
\r
5131 __IO uint16_t bSWRST : 1; /* Software reset enable */
\r
5132 __IO uint16_t bTXBRK : 1; /* Transmit break */
\r
5133 __IO uint16_t bTXADDR : 1; /* Transmit address */
\r
5134 __IO uint16_t bDORM : 1; /* Dormant */
\r
5135 __IO uint16_t bBRKIE : 1; /* Receive break character interrupt enable */
\r
5136 __IO uint16_t bRXEIE : 1; /* Receive erroneous-character interrupt enable */
\r
5137 __IO uint16_t bSSEL : 2; /* eUSCI_A clock source select */
\r
5138 __IO uint16_t bSYNC : 1; /* Synchronous mode enable */
\r
5139 __IO uint16_t bMODE : 2; /* eUSCI_A mode */
\r
5140 __IO uint16_t bSPB : 1; /* Stop bit select */
\r
5141 __IO uint16_t b7BIT : 1; /* Character length */
\r
5142 __IO uint16_t bMSB : 1; /* MSB first select */
\r
5143 __IO uint16_t bPAR : 1; /* Parity select */
\r
5144 __IO uint16_t bPEN : 1; /* Parity enable */
\r
5146 struct { /* UCA0CTLW0_SPI Bits */
\r
5147 __IO uint16_t bSWRST : 1; /* Software reset enable */
\r
5148 __IO uint16_t bSTEM : 1; /* STE mode select in master mode. */
\r
5149 __I uint16_t bRESERVED : 4; /* Reserved */
\r
5150 __IO uint16_t bSSEL : 2; /* eUSCI_A clock source select */
\r
5151 __IO uint16_t bSYNC : 1; /* Synchronous mode enable */
\r
5152 __IO uint16_t bMODE : 2; /* eUSCI mode */
\r
5153 __IO uint16_t bMST : 1; /* Master mode select */
\r
5154 __IO uint16_t b7BIT : 1; /* Character length */
\r
5155 __IO uint16_t bMSB : 1; /* MSB first select */
\r
5156 __IO uint16_t bCKPL : 1; /* Clock polarity select */
\r
5157 __IO uint16_t bCKPH : 1; /* Clock phase select */
\r
5160 union { /* UCA0CTLW1 Register */
\r
5162 struct { /* UCA0CTLW1 Bits */
\r
5163 __IO uint16_t bGLIT : 2; /* Deglitch time */
\r
5164 __I uint16_t bRESERVED0 : 14; /* Reserved */
\r
5167 uint8_t RESERVED0[2];
\r
5168 __IO uint16_t rBRW; /* eUSCI_Ax Baud Rate Control Word Register */
\r
5169 union { /* UCA0MCTLW Register */
\r
5171 struct { /* UCA0MCTLW Bits */
\r
5172 __IO uint16_t bOS16 : 1; /* Oversampling mode enabled */
\r
5173 __I uint16_t bRESERVED0 : 3; /* Reserved */
\r
5174 __IO uint16_t bBRF : 4; /* First modulation stage select */
\r
5175 __IO uint16_t bBRS : 8; /* Second modulation stage select */
\r
5178 union { /* UCA0STATW Register */
\r
5180 struct { /* UCA0STATW Bits */
\r
5181 __I uint16_t bBUSY : 1; /* eUSCI_A busy */
\r
5182 __IO uint16_t bADDR_IDLE : 1; /* Address received / Idle line detected */
\r
5183 __IO uint16_t bRXERR : 1; /* Receive error flag */
\r
5184 __IO uint16_t bBRK : 1; /* Break detect flag */
\r
5185 __IO uint16_t bPE : 1; /* */
\r
5186 __IO uint16_t bOE : 1; /* Overrun error flag */
\r
5187 __IO uint16_t bFE : 1; /* Framing error flag */
\r
5188 __IO uint16_t bLISTEN : 1; /* Listen enable */
\r
5189 __I uint16_t bRESERVED0 : 8; /* Reserved */
\r
5191 struct { /* UCA0STATW_SPI Bits */
\r
5192 __I uint16_t bBUSY : 1; /* eUSCI_A busy */
\r
5193 __IO uint16_t bRESERVED : 4; /* Reserved */
\r
5194 __IO uint16_t bOE : 1; /* Overrun error flag */
\r
5195 __IO uint16_t bFE : 1; /* Framing error flag */
\r
5196 __IO uint16_t bLISTEN : 1; /* Listen enable */
\r
5199 union { /* UCA0RXBUF Register */
\r
5201 struct { /* UCA0RXBUF Bits */
\r
5202 __I uint16_t bRXBUF : 8; /* Receive data buffer */
\r
5203 __I uint16_t bRESERVED0 : 8; /* Reserved */
\r
5205 struct { /* UCA0RXBUF_SPI Bits */
\r
5206 __I uint16_t bRXBUF : 8; /* Receive data buffer */
\r
5207 __I uint16_t bRESERVED : 8; /* Reserved */
\r
5210 union { /* UCA0TXBUF Register */
\r
5212 struct { /* UCA0TXBUF Bits */
\r
5213 __IO uint16_t bTXBUF : 8; /* Transmit data buffer */
\r
5214 __I uint16_t bRESERVED0 : 8; /* Reserved */
\r
5216 struct { /* UCA0TXBUF_SPI Bits */
\r
5217 __IO uint16_t bTXBUF : 8; /* Transmit data buffer */
\r
5218 __I uint16_t bRESERVED : 8; /* Reserved */
\r
5221 union { /* UCA0ABCTL Register */
\r
5223 struct { /* UCA0ABCTL Bits */
\r
5224 __IO uint16_t bABDEN : 1; /* Automatic baud-rate detect enable */
\r
5225 __I uint16_t bRESERVED0 : 1; /* Reserved */
\r
5226 __IO uint16_t bBTOE : 1; /* Break time out error */
\r
5227 __IO uint16_t bSTOE : 1; /* Synch field time out error */
\r
5228 __IO uint16_t bDELIM : 2; /* Break/synch delimiter length */
\r
5229 __I uint16_t bRESERVED1 : 10; /* Reserved */
\r
5232 union { /* UCA0IRCTL Register */
\r
5234 struct { /* UCA0IRCTL Bits */
\r
5235 __IO uint16_t bIREN : 1; /* IrDA encoder/decoder enable */
\r
5236 __IO uint16_t bIRTXCLK : 1; /* IrDA transmit pulse clock select */
\r
5237 __IO uint16_t bIRTXPL : 6; /* Transmit pulse length */
\r
5238 __IO uint16_t bIRRXFE : 1; /* IrDA receive filter enabled */
\r
5239 __IO uint16_t bIRRXPL : 1; /* IrDA receive input UCAxRXD polarity */
\r
5240 __IO uint16_t bIRRXFL : 4; /* Receive filter length */
\r
5243 uint8_t RESERVED1[6];
\r
5244 union { /* UCA0IE Register */
\r
5246 struct { /* UCA0IE Bits */
\r
5247 __IO uint16_t bRXIE : 1; /* Receive interrupt enable */
\r
5248 __IO uint16_t bTXIE : 1; /* Transmit interrupt enable */
\r
5249 __IO uint16_t bSTTIE : 1; /* Start bit interrupt enable */
\r
5250 __IO uint16_t bTXCPTIE : 1; /* Transmit complete interrupt enable */
\r
5251 __I uint16_t bRESERVED0 : 12; /* Reserved */
\r
5253 struct { /* UCA0IE_SPI Bits */
\r
5254 __IO uint16_t bRXIE : 1; /* Receive interrupt enable */
\r
5255 __IO uint16_t bTXIE : 1; /* Transmit interrupt enable */
\r
5256 __I uint16_t bRESERVED : 14; /* Reserved */
\r
5259 union { /* UCA0IFG Register */
\r
5261 struct { /* UCA0IFG Bits */
\r
5262 __IO uint16_t bRXIFG : 1; /* Receive interrupt flag */
\r
5263 __IO uint16_t bTXIFG : 1; /* Transmit interrupt flag */
\r
5264 __IO uint16_t bSTTIFG : 1; /* Start bit interrupt flag */
\r
5265 __IO uint16_t bTXCPTIFG : 1; /* Transmit ready interrupt enable */
\r
5266 __I uint16_t bRESERVED0 : 12; /* Reserved */
\r
5268 struct { /* UCA0IFG_SPI Bits */
\r
5269 __IO uint16_t bRXIFG : 1; /* Receive interrupt flag */
\r
5270 __IO uint16_t bTXIFG : 1; /* Transmit interrupt flag */
\r
5271 __I uint16_t bRESERVED : 14; /* Reserved */
\r
5274 __I uint16_t rIV; /* eUSCI_Ax Interrupt Vector Register */
\r
5278 //*****************************************************************************
\r
5279 // EUSCI_A1 Registers
\r
5280 //*****************************************************************************
\r
5282 union { /* UCA1CTLW0 Register */
\r
5284 struct { /* UCA1CTLW0 Bits */
\r
5285 __IO uint16_t bSWRST : 1; /* Software reset enable */
\r
5286 __IO uint16_t bTXBRK : 1; /* Transmit break */
\r
5287 __IO uint16_t bTXADDR : 1; /* Transmit address */
\r
5288 __IO uint16_t bDORM : 1; /* Dormant */
\r
5289 __IO uint16_t bBRKIE : 1; /* Receive break character interrupt enable */
\r
5290 __IO uint16_t bRXEIE : 1; /* Receive erroneous-character interrupt enable */
\r
5291 __IO uint16_t bSSEL : 2; /* eUSCI_A clock source select */
\r
5292 __IO uint16_t bSYNC : 1; /* Synchronous mode enable */
\r
5293 __IO uint16_t bMODE : 2; /* eUSCI_A mode */
\r
5294 __IO uint16_t bSPB : 1; /* Stop bit select */
\r
5295 __IO uint16_t b7BIT : 1; /* Character length */
\r
5296 __IO uint16_t bMSB : 1; /* MSB first select */
\r
5297 __IO uint16_t bPAR : 1; /* Parity select */
\r
5298 __IO uint16_t bPEN : 1; /* Parity enable */
\r
5300 struct { /* UCA1CTLW0_SPI Bits */
\r
5301 __IO uint16_t bSWRST : 1; /* Software reset enable */
\r
5302 __IO uint16_t bSTEM : 1; /* STE mode select in master mode. */
\r
5303 __I uint16_t bRESERVED : 4; /* Reserved */
\r
5304 __IO uint16_t bSSEL : 2; /* eUSCI_A clock source select */
\r
5305 __IO uint16_t bSYNC : 1; /* Synchronous mode enable */
\r
5306 __IO uint16_t bMODE : 2; /* eUSCI mode */
\r
5307 __IO uint16_t bMST : 1; /* Master mode select */
\r
5308 __IO uint16_t b7BIT : 1; /* Character length */
\r
5309 __IO uint16_t bMSB : 1; /* MSB first select */
\r
5310 __IO uint16_t bCKPL : 1; /* Clock polarity select */
\r
5311 __IO uint16_t bCKPH : 1; /* Clock phase select */
\r
5314 union { /* UCA1CTLW1 Register */
\r
5316 struct { /* UCA1CTLW1 Bits */
\r
5317 __IO uint16_t bGLIT : 2; /* Deglitch time */
\r
5318 __I uint16_t bRESERVED0 : 14; /* Reserved */
\r
5321 uint8_t RESERVED0[2];
\r
5322 __IO uint16_t rBRW; /* eUSCI_Ax Baud Rate Control Word Register */
\r
5323 union { /* UCA1MCTLW Register */
\r
5325 struct { /* UCA1MCTLW Bits */
\r
5326 __IO uint16_t bOS16 : 1; /* Oversampling mode enabled */
\r
5327 __I uint16_t bRESERVED0 : 3; /* Reserved */
\r
5328 __IO uint16_t bBRF : 4; /* First modulation stage select */
\r
5329 __IO uint16_t bBRS : 8; /* Second modulation stage select */
\r
5332 union { /* UCA1STATW Register */
\r
5334 struct { /* UCA1STATW Bits */
\r
5335 __I uint16_t bBUSY : 1; /* eUSCI_A busy */
\r
5336 __IO uint16_t bADDR_IDLE : 1; /* Address received / Idle line detected */
\r
5337 __IO uint16_t bRXERR : 1; /* Receive error flag */
\r
5338 __IO uint16_t bBRK : 1; /* Break detect flag */
\r
5339 __IO uint16_t bPE : 1; /* */
\r
5340 __IO uint16_t bOE : 1; /* Overrun error flag */
\r
5341 __IO uint16_t bFE : 1; /* Framing error flag */
\r
5342 __IO uint16_t bLISTEN : 1; /* Listen enable */
\r
5343 __I uint16_t bRESERVED0 : 8; /* Reserved */
\r
5345 struct { /* UCA1STATW_SPI Bits */
\r
5346 __I uint16_t bBUSY : 1; /* eUSCI_A busy */
\r
5347 __IO uint16_t bRESERVED : 4; /* Reserved */
\r
5348 __IO uint16_t bOE : 1; /* Overrun error flag */
\r
5349 __IO uint16_t bFE : 1; /* Framing error flag */
\r
5350 __IO uint16_t bLISTEN : 1; /* Listen enable */
\r
5353 union { /* UCA1RXBUF Register */
\r
5355 struct { /* UCA1RXBUF Bits */
\r
5356 __I uint16_t bRXBUF : 8; /* Receive data buffer */
\r
5357 __I uint16_t bRESERVED0 : 8; /* Reserved */
\r
5359 struct { /* UCA1RXBUF_SPI Bits */
\r
5360 __I uint16_t bRXBUF : 8; /* Receive data buffer */
\r
5361 __I uint16_t bRESERVED : 8; /* Reserved */
\r
5364 union { /* UCA1TXBUF Register */
\r
5366 struct { /* UCA1TXBUF Bits */
\r
5367 __IO uint16_t bTXBUF : 8; /* Transmit data buffer */
\r
5368 __I uint16_t bRESERVED0 : 8; /* Reserved */
\r
5370 struct { /* UCA1TXBUF_SPI Bits */
\r
5371 __IO uint16_t bTXBUF : 8; /* Transmit data buffer */
\r
5372 __I uint16_t bRESERVED : 8; /* Reserved */
\r
5375 union { /* UCA1ABCTL Register */
\r
5377 struct { /* UCA1ABCTL Bits */
\r
5378 __IO uint16_t bABDEN : 1; /* Automatic baud-rate detect enable */
\r
5379 __I uint16_t bRESERVED0 : 1; /* Reserved */
\r
5380 __IO uint16_t bBTOE : 1; /* Break time out error */
\r
5381 __IO uint16_t bSTOE : 1; /* Synch field time out error */
\r
5382 __IO uint16_t bDELIM : 2; /* Break/synch delimiter length */
\r
5383 __I uint16_t bRESERVED1 : 10; /* Reserved */
\r
5386 union { /* UCA1IRCTL Register */
\r
5388 struct { /* UCA1IRCTL Bits */
\r
5389 __IO uint16_t bIREN : 1; /* IrDA encoder/decoder enable */
\r
5390 __IO uint16_t bIRTXCLK : 1; /* IrDA transmit pulse clock select */
\r
5391 __IO uint16_t bIRTXPL : 6; /* Transmit pulse length */
\r
5392 __IO uint16_t bIRRXFE : 1; /* IrDA receive filter enabled */
\r
5393 __IO uint16_t bIRRXPL : 1; /* IrDA receive input UCAxRXD polarity */
\r
5394 __IO uint16_t bIRRXFL : 4; /* Receive filter length */
\r
5397 uint8_t RESERVED1[6];
\r
5398 union { /* UCA1IE Register */
\r
5400 struct { /* UCA1IE Bits */
\r
5401 __IO uint16_t bRXIE : 1; /* Receive interrupt enable */
\r
5402 __IO uint16_t bTXIE : 1; /* Transmit interrupt enable */
\r
5403 __IO uint16_t bSTTIE : 1; /* Start bit interrupt enable */
\r
5404 __IO uint16_t bTXCPTIE : 1; /* Transmit complete interrupt enable */
\r
5405 __I uint16_t bRESERVED0 : 12; /* Reserved */
\r
5407 struct { /* UCA1IE_SPI Bits */
\r
5408 __IO uint16_t bRXIE : 1; /* Receive interrupt enable */
\r
5409 __IO uint16_t bTXIE : 1; /* Transmit interrupt enable */
\r
5410 __I uint16_t bRESERVED : 14; /* Reserved */
\r
5413 union { /* UCA1IFG Register */
\r
5415 struct { /* UCA1IFG Bits */
\r
5416 __IO uint16_t bRXIFG : 1; /* Receive interrupt flag */
\r
5417 __IO uint16_t bTXIFG : 1; /* Transmit interrupt flag */
\r
5418 __IO uint16_t bSTTIFG : 1; /* Start bit interrupt flag */
\r
5419 __IO uint16_t bTXCPTIFG : 1; /* Transmit ready interrupt enable */
\r
5420 __I uint16_t bRESERVED0 : 12; /* Reserved */
\r
5422 struct { /* UCA1IFG_SPI Bits */
\r
5423 __IO uint16_t bRXIFG : 1; /* Receive interrupt flag */
\r
5424 __IO uint16_t bTXIFG : 1; /* Transmit interrupt flag */
\r
5425 __I uint16_t bRESERVED : 14; /* Reserved */
\r
5428 __I uint16_t rIV; /* eUSCI_Ax Interrupt Vector Register */
\r
5432 //*****************************************************************************
\r
5433 // EUSCI_A2 Registers
\r
5434 //*****************************************************************************
\r
5436 union { /* UCA2CTLW0 Register */
\r
5438 struct { /* UCA2CTLW0 Bits */
\r
5439 __IO uint16_t bSWRST : 1; /* Software reset enable */
\r
5440 __IO uint16_t bTXBRK : 1; /* Transmit break */
\r
5441 __IO uint16_t bTXADDR : 1; /* Transmit address */
\r
5442 __IO uint16_t bDORM : 1; /* Dormant */
\r
5443 __IO uint16_t bBRKIE : 1; /* Receive break character interrupt enable */
\r
5444 __IO uint16_t bRXEIE : 1; /* Receive erroneous-character interrupt enable */
\r
5445 __IO uint16_t bSSEL : 2; /* eUSCI_A clock source select */
\r
5446 __IO uint16_t bSYNC : 1; /* Synchronous mode enable */
\r
5447 __IO uint16_t bMODE : 2; /* eUSCI_A mode */
\r
5448 __IO uint16_t bSPB : 1; /* Stop bit select */
\r
5449 __IO uint16_t b7BIT : 1; /* Character length */
\r
5450 __IO uint16_t bMSB : 1; /* MSB first select */
\r
5451 __IO uint16_t bPAR : 1; /* Parity select */
\r
5452 __IO uint16_t bPEN : 1; /* Parity enable */
\r
5454 struct { /* UCA2CTLW0_SPI Bits */
\r
5455 __IO uint16_t bSWRST : 1; /* Software reset enable */
\r
5456 __IO uint16_t bSTEM : 1; /* STE mode select in master mode. */
\r
5457 __I uint16_t bRESERVED : 4; /* Reserved */
\r
5458 __IO uint16_t bSSEL : 2; /* eUSCI_A clock source select */
\r
5459 __IO uint16_t bSYNC : 1; /* Synchronous mode enable */
\r
5460 __IO uint16_t bMODE : 2; /* eUSCI mode */
\r
5461 __IO uint16_t bMST : 1; /* Master mode select */
\r
5462 __IO uint16_t b7BIT : 1; /* Character length */
\r
5463 __IO uint16_t bMSB : 1; /* MSB first select */
\r
5464 __IO uint16_t bCKPL : 1; /* Clock polarity select */
\r
5465 __IO uint16_t bCKPH : 1; /* Clock phase select */
\r
5468 union { /* UCA2CTLW1 Register */
\r
5470 struct { /* UCA2CTLW1 Bits */
\r
5471 __IO uint16_t bGLIT : 2; /* Deglitch time */
\r
5472 __I uint16_t bRESERVED0 : 14; /* Reserved */
\r
5475 uint8_t RESERVED0[2];
\r
5476 __IO uint16_t rBRW; /* eUSCI_Ax Baud Rate Control Word Register */
\r
5477 union { /* UCA2MCTLW Register */
\r
5479 struct { /* UCA2MCTLW Bits */
\r
5480 __IO uint16_t bOS16 : 1; /* Oversampling mode enabled */
\r
5481 __I uint16_t bRESERVED0 : 3; /* Reserved */
\r
5482 __IO uint16_t bBRF : 4; /* First modulation stage select */
\r
5483 __IO uint16_t bBRS : 8; /* Second modulation stage select */
\r
5486 union { /* UCA2STATW Register */
\r
5488 struct { /* UCA2STATW Bits */
\r
5489 __I uint16_t bBUSY : 1; /* eUSCI_A busy */
\r
5490 __IO uint16_t bADDR_IDLE : 1; /* Address received / Idle line detected */
\r
5491 __IO uint16_t bRXERR : 1; /* Receive error flag */
\r
5492 __IO uint16_t bBRK : 1; /* Break detect flag */
\r
5493 __IO uint16_t bPE : 1; /* */
\r
5494 __IO uint16_t bOE : 1; /* Overrun error flag */
\r
5495 __IO uint16_t bFE : 1; /* Framing error flag */
\r
5496 __IO uint16_t bLISTEN : 1; /* Listen enable */
\r
5497 __I uint16_t bRESERVED0 : 8; /* Reserved */
\r
5499 struct { /* UCA2STATW_SPI Bits */
\r
5500 __I uint16_t bBUSY : 1; /* eUSCI_A busy */
\r
5501 __IO uint16_t bRESERVED : 4; /* Reserved */
\r
5502 __IO uint16_t bOE : 1; /* Overrun error flag */
\r
5503 __IO uint16_t bFE : 1; /* Framing error flag */
\r
5504 __IO uint16_t bLISTEN : 1; /* Listen enable */
\r
5507 union { /* UCA2RXBUF Register */
\r
5509 struct { /* UCA2RXBUF Bits */
\r
5510 __I uint16_t bRXBUF : 8; /* Receive data buffer */
\r
5511 __I uint16_t bRESERVED0 : 8; /* Reserved */
\r
5513 struct { /* UCA2RXBUF_SPI Bits */
\r
5514 __I uint16_t bRXBUF : 8; /* Receive data buffer */
\r
5515 __I uint16_t bRESERVED : 8; /* Reserved */
\r
5518 union { /* UCA2TXBUF Register */
\r
5520 struct { /* UCA2TXBUF Bits */
\r
5521 __IO uint16_t bTXBUF : 8; /* Transmit data buffer */
\r
5522 __I uint16_t bRESERVED0 : 8; /* Reserved */
\r
5524 struct { /* UCA2TXBUF_SPI Bits */
\r
5525 __IO uint16_t bTXBUF : 8; /* Transmit data buffer */
\r
5526 __I uint16_t bRESERVED : 8; /* Reserved */
\r
5529 union { /* UCA2ABCTL Register */
\r
5531 struct { /* UCA2ABCTL Bits */
\r
5532 __IO uint16_t bABDEN : 1; /* Automatic baud-rate detect enable */
\r
5533 __I uint16_t bRESERVED0 : 1; /* Reserved */
\r
5534 __IO uint16_t bBTOE : 1; /* Break time out error */
\r
5535 __IO uint16_t bSTOE : 1; /* Synch field time out error */
\r
5536 __IO uint16_t bDELIM : 2; /* Break/synch delimiter length */
\r
5537 __I uint16_t bRESERVED1 : 10; /* Reserved */
\r
5540 union { /* UCA2IRCTL Register */
\r
5542 struct { /* UCA2IRCTL Bits */
\r
5543 __IO uint16_t bIREN : 1; /* IrDA encoder/decoder enable */
\r
5544 __IO uint16_t bIRTXCLK : 1; /* IrDA transmit pulse clock select */
\r
5545 __IO uint16_t bIRTXPL : 6; /* Transmit pulse length */
\r
5546 __IO uint16_t bIRRXFE : 1; /* IrDA receive filter enabled */
\r
5547 __IO uint16_t bIRRXPL : 1; /* IrDA receive input UCAxRXD polarity */
\r
5548 __IO uint16_t bIRRXFL : 4; /* Receive filter length */
\r
5551 uint8_t RESERVED1[6];
\r
5552 union { /* UCA2IE Register */
\r
5554 struct { /* UCA2IE Bits */
\r
5555 __IO uint16_t bRXIE : 1; /* Receive interrupt enable */
\r
5556 __IO uint16_t bTXIE : 1; /* Transmit interrupt enable */
\r
5557 __IO uint16_t bSTTIE : 1; /* Start bit interrupt enable */
\r
5558 __IO uint16_t bTXCPTIE : 1; /* Transmit complete interrupt enable */
\r
5559 __I uint16_t bRESERVED0 : 12; /* Reserved */
\r
5561 struct { /* UCA2IE_SPI Bits */
\r
5562 __IO uint16_t bRXIE : 1; /* Receive interrupt enable */
\r
5563 __IO uint16_t bTXIE : 1; /* Transmit interrupt enable */
\r
5564 __I uint16_t bRESERVED : 14; /* Reserved */
\r
5567 union { /* UCA2IFG Register */
\r
5569 struct { /* UCA2IFG Bits */
\r
5570 __IO uint16_t bRXIFG : 1; /* Receive interrupt flag */
\r
5571 __IO uint16_t bTXIFG : 1; /* Transmit interrupt flag */
\r
5572 __IO uint16_t bSTTIFG : 1; /* Start bit interrupt flag */
\r
5573 __IO uint16_t bTXCPTIFG : 1; /* Transmit ready interrupt enable */
\r
5574 __I uint16_t bRESERVED0 : 12; /* Reserved */
\r
5576 struct { /* UCA2IFG_SPI Bits */
\r
5577 __IO uint16_t bRXIFG : 1; /* Receive interrupt flag */
\r
5578 __IO uint16_t bTXIFG : 1; /* Transmit interrupt flag */
\r
5579 __I uint16_t bRESERVED : 14; /* Reserved */
\r
5582 __I uint16_t rIV; /* eUSCI_Ax Interrupt Vector Register */
\r
5586 //*****************************************************************************
\r
5587 // EUSCI_A3 Registers
\r
5588 //*****************************************************************************
\r
5590 union { /* UCA3CTLW0 Register */
\r
5592 struct { /* UCA3CTLW0 Bits */
\r
5593 __IO uint16_t bSWRST : 1; /* Software reset enable */
\r
5594 __IO uint16_t bTXBRK : 1; /* Transmit break */
\r
5595 __IO uint16_t bTXADDR : 1; /* Transmit address */
\r
5596 __IO uint16_t bDORM : 1; /* Dormant */
\r
5597 __IO uint16_t bBRKIE : 1; /* Receive break character interrupt enable */
\r
5598 __IO uint16_t bRXEIE : 1; /* Receive erroneous-character interrupt enable */
\r
5599 __IO uint16_t bSSEL : 2; /* eUSCI_A clock source select */
\r
5600 __IO uint16_t bSYNC : 1; /* Synchronous mode enable */
\r
5601 __IO uint16_t bMODE : 2; /* eUSCI_A mode */
\r
5602 __IO uint16_t bSPB : 1; /* Stop bit select */
\r
5603 __IO uint16_t b7BIT : 1; /* Character length */
\r
5604 __IO uint16_t bMSB : 1; /* MSB first select */
\r
5605 __IO uint16_t bPAR : 1; /* Parity select */
\r
5606 __IO uint16_t bPEN : 1; /* Parity enable */
\r
5608 struct { /* UCA3CTLW0_SPI Bits */
\r
5609 __IO uint16_t bSWRST : 1; /* Software reset enable */
\r
5610 __IO uint16_t bSTEM : 1; /* STE mode select in master mode. */
\r
5611 __I uint16_t bRESERVED : 4; /* Reserved */
\r
5612 __IO uint16_t bSSEL : 2; /* eUSCI_A clock source select */
\r
5613 __IO uint16_t bSYNC : 1; /* Synchronous mode enable */
\r
5614 __IO uint16_t bMODE : 2; /* eUSCI mode */
\r
5615 __IO uint16_t bMST : 1; /* Master mode select */
\r
5616 __IO uint16_t b7BIT : 1; /* Character length */
\r
5617 __IO uint16_t bMSB : 1; /* MSB first select */
\r
5618 __IO uint16_t bCKPL : 1; /* Clock polarity select */
\r
5619 __IO uint16_t bCKPH : 1; /* Clock phase select */
\r
5622 union { /* UCA3CTLW1 Register */
\r
5624 struct { /* UCA3CTLW1 Bits */
\r
5625 __IO uint16_t bGLIT : 2; /* Deglitch time */
\r
5626 __I uint16_t bRESERVED0 : 14; /* Reserved */
\r
5629 uint8_t RESERVED0[2];
\r
5630 __IO uint16_t rBRW; /* eUSCI_Ax Baud Rate Control Word Register */
\r
5631 union { /* UCA3MCTLW Register */
\r
5633 struct { /* UCA3MCTLW Bits */
\r
5634 __IO uint16_t bOS16 : 1; /* Oversampling mode enabled */
\r
5635 __I uint16_t bRESERVED0 : 3; /* Reserved */
\r
5636 __IO uint16_t bBRF : 4; /* First modulation stage select */
\r
5637 __IO uint16_t bBRS : 8; /* Second modulation stage select */
\r
5640 union { /* UCA3STATW Register */
\r
5642 struct { /* UCA3STATW Bits */
\r
5643 __I uint16_t bBUSY : 1; /* eUSCI_A busy */
\r
5644 __IO uint16_t bADDR_IDLE : 1; /* Address received / Idle line detected */
\r
5645 __IO uint16_t bRXERR : 1; /* Receive error flag */
\r
5646 __IO uint16_t bBRK : 1; /* Break detect flag */
\r
5647 __IO uint16_t bPE : 1; /* */
\r
5648 __IO uint16_t bOE : 1; /* Overrun error flag */
\r
5649 __IO uint16_t bFE : 1; /* Framing error flag */
\r
5650 __IO uint16_t bLISTEN : 1; /* Listen enable */
\r
5651 __I uint16_t bRESERVED0 : 8; /* Reserved */
\r
5653 struct { /* UCA3STATW_SPI Bits */
\r
5654 __I uint16_t bBUSY : 1; /* eUSCI_A busy */
\r
5655 __IO uint16_t bRESERVED : 4; /* Reserved */
\r
5656 __IO uint16_t bOE : 1; /* Overrun error flag */
\r
5657 __IO uint16_t bFE : 1; /* Framing error flag */
\r
5658 __IO uint16_t bLISTEN : 1; /* Listen enable */
\r
5661 union { /* UCA3RXBUF Register */
\r
5663 struct { /* UCA3RXBUF Bits */
\r
5664 __I uint16_t bRXBUF : 8; /* Receive data buffer */
\r
5665 __I uint16_t bRESERVED0 : 8; /* Reserved */
\r
5667 struct { /* UCA3RXBUF_SPI Bits */
\r
5668 __I uint16_t bRXBUF : 8; /* Receive data buffer */
\r
5669 __I uint16_t bRESERVED : 8; /* Reserved */
\r
5672 union { /* UCA3TXBUF Register */
\r
5674 struct { /* UCA3TXBUF Bits */
\r
5675 __IO uint16_t bTXBUF : 8; /* Transmit data buffer */
\r
5676 __I uint16_t bRESERVED0 : 8; /* Reserved */
\r
5678 struct { /* UCA3TXBUF_SPI Bits */
\r
5679 __IO uint16_t bTXBUF : 8; /* Transmit data buffer */
\r
5680 __I uint16_t bRESERVED : 8; /* Reserved */
\r
5683 union { /* UCA3ABCTL Register */
\r
5685 struct { /* UCA3ABCTL Bits */
\r
5686 __IO uint16_t bABDEN : 1; /* Automatic baud-rate detect enable */
\r
5687 __I uint16_t bRESERVED0 : 1; /* Reserved */
\r
5688 __IO uint16_t bBTOE : 1; /* Break time out error */
\r
5689 __IO uint16_t bSTOE : 1; /* Synch field time out error */
\r
5690 __IO uint16_t bDELIM : 2; /* Break/synch delimiter length */
\r
5691 __I uint16_t bRESERVED1 : 10; /* Reserved */
\r
5694 union { /* UCA3IRCTL Register */
\r
5696 struct { /* UCA3IRCTL Bits */
\r
5697 __IO uint16_t bIREN : 1; /* IrDA encoder/decoder enable */
\r
5698 __IO uint16_t bIRTXCLK : 1; /* IrDA transmit pulse clock select */
\r
5699 __IO uint16_t bIRTXPL : 6; /* Transmit pulse length */
\r
5700 __IO uint16_t bIRRXFE : 1; /* IrDA receive filter enabled */
\r
5701 __IO uint16_t bIRRXPL : 1; /* IrDA receive input UCAxRXD polarity */
\r
5702 __IO uint16_t bIRRXFL : 4; /* Receive filter length */
\r
5705 uint8_t RESERVED1[6];
\r
5706 union { /* UCA3IE Register */
\r
5708 struct { /* UCA3IE Bits */
\r
5709 __IO uint16_t bRXIE : 1; /* Receive interrupt enable */
\r
5710 __IO uint16_t bTXIE : 1; /* Transmit interrupt enable */
\r
5711 __IO uint16_t bSTTIE : 1; /* Start bit interrupt enable */
\r
5712 __IO uint16_t bTXCPTIE : 1; /* Transmit complete interrupt enable */
\r
5713 __I uint16_t bRESERVED0 : 12; /* Reserved */
\r
5715 struct { /* UCA3IE_SPI Bits */
\r
5716 __IO uint16_t bRXIE : 1; /* Receive interrupt enable */
\r
5717 __IO uint16_t bTXIE : 1; /* Transmit interrupt enable */
\r
5718 __I uint16_t bRESERVED : 14; /* Reserved */
\r
5721 union { /* UCA3IFG Register */
\r
5723 struct { /* UCA3IFG Bits */
\r
5724 __IO uint16_t bRXIFG : 1; /* Receive interrupt flag */
\r
5725 __IO uint16_t bTXIFG : 1; /* Transmit interrupt flag */
\r
5726 __IO uint16_t bSTTIFG : 1; /* Start bit interrupt flag */
\r
5727 __IO uint16_t bTXCPTIFG : 1; /* Transmit ready interrupt enable */
\r
5728 __I uint16_t bRESERVED0 : 12; /* Reserved */
\r
5730 struct { /* UCA3IFG_SPI Bits */
\r
5731 __IO uint16_t bRXIFG : 1; /* Receive interrupt flag */
\r
5732 __IO uint16_t bTXIFG : 1; /* Transmit interrupt flag */
\r
5733 __I uint16_t bRESERVED : 14; /* Reserved */
\r
5736 __I uint16_t rIV; /* eUSCI_Ax Interrupt Vector Register */
\r
5740 //*****************************************************************************
\r
5741 // EUSCI_B0 Registers
\r
5742 //*****************************************************************************
\r
5744 union { /* UCB0CTLW0 Register */
\r
5746 struct { /* UCB0CTLW0 Bits */
\r
5747 __IO uint16_t bSWRST : 1; /* Software reset enable */
\r
5748 __IO uint16_t bTXSTT : 1; /* Transmit START condition in master mode */
\r
5749 __IO uint16_t bTXSTP : 1; /* Transmit STOP condition in master mode */
\r
5750 __IO uint16_t bTXNACK : 1; /* Transmit a NACK */
\r
5751 __IO uint16_t bTR : 1; /* Transmitter/receiver */
\r
5752 __IO uint16_t bTXACK : 1; /* Transmit ACK condition in slave mode */
\r
5753 __IO uint16_t bSSEL : 2; /* eUSCI_B clock source select */
\r
5754 __IO uint16_t bSYNC : 1; /* Synchronous mode enable */
\r
5755 __IO uint16_t bMODE : 2; /* eUSCI_B mode */
\r
5756 __IO uint16_t bMST : 1; /* Master mode select */
\r
5757 __I uint16_t bRESERVED0 : 1; /* Reserved */
\r
5758 __IO uint16_t bMM : 1; /* Multi-master environment select */
\r
5759 __IO uint16_t bSLA10 : 1; /* Slave addressing mode select */
\r
5760 __IO uint16_t bA10 : 1; /* Own addressing mode select */
\r
5762 struct { /* UCB0CTLW0_SPI Bits */
\r
5763 __IO uint16_t bSWRST : 1; /* Software reset enable */
\r
5764 __IO uint16_t bSTEM : 1; /* STE mode select in master mode. */
\r
5765 __I uint16_t bRESERVED : 4; /* Reserved */
\r
5766 __IO uint16_t bSSEL : 2; /* eUSCI_B clock source select */
\r
5767 __IO uint16_t bSYNC : 1; /* Synchronous mode enable */
\r
5768 __IO uint16_t bMODE : 2; /* eUSCI mode */
\r
5769 __IO uint16_t bMST : 1; /* Master mode select */
\r
5770 __IO uint16_t b7BIT : 1; /* Character length */
\r
5771 __IO uint16_t bMSB : 1; /* MSB first select */
\r
5772 __IO uint16_t bCKPL : 1; /* Clock polarity select */
\r
5773 __IO uint16_t bCKPH : 1; /* Clock phase select */
\r
5776 union { /* UCB0CTLW1 Register */
\r
5778 struct { /* UCB0CTLW1 Bits */
\r
5779 __IO uint16_t bGLIT : 2; /* Deglitch time */
\r
5780 __IO uint16_t bASTP : 2; /* Automatic STOP condition generation */
\r
5781 __IO uint16_t bSWACK : 1; /* SW or HW ACK control */
\r
5782 __IO uint16_t bSTPNACK : 1; /* ACK all master bytes */
\r
5783 __IO uint16_t bCLTO : 2; /* Clock low timeout select */
\r
5784 __IO uint16_t bETXINT : 1; /* Early UCTXIFG0 */
\r
5785 __I uint16_t bRESERVED0 : 7; /* Reserved */
\r
5788 uint8_t RESERVED0[2];
\r
5789 __IO uint16_t rBRW; /* eUSCI_Bx Baud Rate Control Word Register */
\r
5790 union { /* UCB0STATW Register */
\r
5792 struct { /* UCB0STATW Bits */
\r
5793 __I uint16_t bRESERVED1 : 4; /* Reserved */
\r
5794 __I uint16_t bBBUSY : 1; /* Bus busy */
\r
5795 __I uint16_t bGC : 1; /* General call address received */
\r
5796 __I uint16_t bSCLLOW : 1; /* SCL low */
\r
5797 __I uint16_t bRESERVED0 : 1; /* Reserved */
\r
5798 __I uint16_t bBCNT : 8; /* Hardware byte counter value */
\r
5800 struct { /* UCB0STATW_SPI Bits */
\r
5801 __I uint16_t bBUSY : 1; /* eUSCI_B busy */
\r
5802 __IO uint16_t bRESERVED : 4; /* Reserved */
\r
5803 __IO uint16_t bOE : 1; /* Overrun error flag */
\r
5804 __IO uint16_t bFE : 1; /* Framing error flag */
\r
5805 __IO uint16_t bLISTEN : 1; /* Listen enable */
\r
5808 union { /* UCB0TBCNT Register */
\r
5810 struct { /* UCB0TBCNT Bits */
\r
5811 __IO uint16_t bTBCNT : 8; /* Byte counter threshold value */
\r
5812 __I uint16_t bRESERVED0 : 8; /* Reserved */
\r
5815 union { /* UCB0RXBUF Register */
\r
5817 struct { /* UCB0RXBUF Bits */
\r
5818 __I uint16_t bRXBUF : 8; /* Receive data buffer */
\r
5819 __I uint16_t bRESERVED0 : 8; /* Reserved */
\r
5821 struct { /* UCB0RXBUF_SPI Bits */
\r
5822 __I uint16_t bRXBUF : 8; /* Receive data buffer */
\r
5823 __I uint16_t bRESERVED : 8; /* Reserved */
\r
5826 union { /* UCB0TXBUF Register */
\r
5828 struct { /* UCB0TXBUF Bits */
\r
5829 __IO uint16_t bTXBUF : 8; /* Transmit data buffer */
\r
5830 __I uint16_t bRESERVED0 : 8; /* Reserved */
\r
5832 struct { /* UCB0TXBUF_SPI Bits */
\r
5833 __IO uint16_t bTXBUF : 8; /* Transmit data buffer */
\r
5834 __I uint16_t bRESERVED : 8; /* Reserved */
\r
5837 uint8_t RESERVED1[4];
\r
5838 union { /* UCB0I2COA0 Register */
\r
5840 struct { /* UCB0I2COA0 Bits */
\r
5841 __IO uint16_t bI2COA0 : 10; /* I2C own address */
\r
5842 __IO uint16_t bOAEN : 1; /* Own Address enable register */
\r
5843 __I uint16_t bRESERVED0 : 4; /* Reserved */
\r
5844 __IO uint16_t bGCEN : 1; /* General call response enable */
\r
5847 union { /* UCB0I2COA1 Register */
\r
5849 struct { /* UCB0I2COA1 Bits */
\r
5850 __IO uint16_t bI2COA1 : 10; /* I2C own address */
\r
5851 __IO uint16_t bOAEN : 1; /* Own Address enable register */
\r
5852 __I uint16_t bRESERVED0 : 5; /* Reserved */
\r
5855 union { /* UCB0I2COA2 Register */
\r
5857 struct { /* UCB0I2COA2 Bits */
\r
5858 __IO uint16_t bI2COA2 : 10; /* I2C own address */
\r
5859 __IO uint16_t bOAEN : 1; /* Own Address enable register */
\r
5860 __I uint16_t bRESERVED0 : 5; /* Reserved */
\r
5863 union { /* UCB0I2COA3 Register */
\r
5865 struct { /* UCB0I2COA3 Bits */
\r
5866 __IO uint16_t bI2COA3 : 10; /* I2C own address */
\r
5867 __IO uint16_t bOAEN : 1; /* Own Address enable register */
\r
5868 __I uint16_t bRESERVED0 : 5; /* Reserved */
\r
5871 union { /* UCB0ADDRX Register */
\r
5873 struct { /* UCB0ADDRX Bits */
\r
5874 __I uint16_t bADDRX : 10; /* Received Address Register */
\r
5875 __I uint16_t bRESERVED0 : 6; /* Reserved */
\r
5878 union { /* UCB0ADDMASK Register */
\r
5880 struct { /* UCB0ADDMASK Bits */
\r
5881 __IO uint16_t bADDMASK : 10; /* */
\r
5882 __I uint16_t bRESERVED0 : 6; /* Reserved */
\r
5885 union { /* UCB0I2CSA Register */
\r
5887 struct { /* UCB0I2CSA Bits */
\r
5888 __IO uint16_t bI2CSA : 10; /* I2C slave address */
\r
5889 __I uint16_t bRESERVED0 : 6; /* Reserved */
\r
5892 uint8_t RESERVED2[8];
\r
5893 union { /* UCB0IE Register */
\r
5895 struct { /* UCB0IE Bits */
\r
5896 __IO uint16_t bRXIE0 : 1; /* Receive interrupt enable 0 */
\r
5897 __IO uint16_t bTXIE0 : 1; /* Transmit interrupt enable 0 */
\r
5898 __IO uint16_t bSTTIE : 1; /* START condition interrupt enable */
\r
5899 __IO uint16_t bSTPIE : 1; /* STOP condition interrupt enable */
\r
5900 __IO uint16_t bALIE : 1; /* Arbitration lost interrupt enable */
\r
5901 __IO uint16_t bNACKIE : 1; /* Not-acknowledge interrupt enable */
\r
5902 __IO uint16_t bBCNTIE : 1; /* Byte counter interrupt enable */
\r
5903 __IO uint16_t bCLTOIE : 1; /* Clock low timeout interrupt enable */
\r
5904 __IO uint16_t bRXIE1 : 1; /* Receive interrupt enable 1 */
\r
5905 __IO uint16_t bTXIE1 : 1; /* Transmit interrupt enable 1 */
\r
5906 __IO uint16_t bRXIE2 : 1; /* Receive interrupt enable 2 */
\r
5907 __IO uint16_t bTXIE2 : 1; /* Transmit interrupt enable 2 */
\r
5908 __IO uint16_t bRXIE3 : 1; /* Receive interrupt enable 3 */
\r
5909 __IO uint16_t bTXIE3 : 1; /* Transmit interrupt enable 3 */
\r
5910 __IO uint16_t bBIT9IE : 1; /* Bit position 9 interrupt enable */
\r
5911 __I uint16_t bRESERVED0 : 1; /* Reserved */
\r
5913 struct { /* UCB0IE_SPI Bits */
\r
5914 __IO uint16_t bRXIE : 1; /* Receive interrupt enable */
\r
5915 __IO uint16_t bTXIE : 1; /* Transmit interrupt enable */
\r
5916 __I uint16_t bRESERVED : 14; /* Reserved */
\r
5919 union { /* UCB0IFG Register */
\r
5921 struct { /* UCB0IFG Bits */
\r
5922 __IO uint16_t bRXIFG0 : 1; /* eUSCI_B receive interrupt flag 0 */
\r
5923 __IO uint16_t bTXIFG0 : 1; /* eUSCI_B transmit interrupt flag 0 */
\r
5924 __IO uint16_t bSTTIFG : 1; /* START condition interrupt flag */
\r
5925 __IO uint16_t bSTPIFG : 1; /* STOP condition interrupt flag */
\r
5926 __IO uint16_t bALIFG : 1; /* Arbitration lost interrupt flag */
\r
5927 __IO uint16_t bNACKIFG : 1; /* Not-acknowledge received interrupt flag */
\r
5928 __IO uint16_t bBCNTIFG : 1; /* Byte counter interrupt flag */
\r
5929 __IO uint16_t bCLTOIFG : 1; /* Clock low timeout interrupt flag */
\r
5930 __IO uint16_t bRXIFG1 : 1; /* eUSCI_B receive interrupt flag 1 */
\r
5931 __IO uint16_t bTXIFG1 : 1; /* eUSCI_B transmit interrupt flag 1 */
\r
5932 __IO uint16_t bRXIFG2 : 1; /* eUSCI_B receive interrupt flag 2 */
\r
5933 __IO uint16_t bTXIFG2 : 1; /* eUSCI_B transmit interrupt flag 2 */
\r
5934 __IO uint16_t bRXIFG3 : 1; /* eUSCI_B receive interrupt flag 3 */
\r
5935 __IO uint16_t bTXIFG3 : 1; /* eUSCI_B transmit interrupt flag 3 */
\r
5936 __IO uint16_t bBIT9IFG : 1; /* Bit position 9 interrupt flag */
\r
5937 __I uint16_t bRESERVED0 : 1; /* Reserved */
\r
5939 struct { /* UCB0IFG_SPI Bits */
\r
5940 __IO uint16_t bRXIFG : 1; /* Receive interrupt flag */
\r
5941 __IO uint16_t bTXIFG : 1; /* Transmit interrupt flag */
\r
5942 __I uint16_t bRESERVED : 14; /* Reserved */
\r
5945 __I uint16_t rIV; /* eUSCI_Bx Interrupt Vector Register */
\r
5949 //*****************************************************************************
\r
5950 // EUSCI_B1 Registers
\r
5951 //*****************************************************************************
\r
5953 union { /* UCB1CTLW0 Register */
\r
5955 struct { /* UCB1CTLW0 Bits */
\r
5956 __IO uint16_t bSWRST : 1; /* Software reset enable */
\r
5957 __IO uint16_t bTXSTT : 1; /* Transmit START condition in master mode */
\r
5958 __IO uint16_t bTXSTP : 1; /* Transmit STOP condition in master mode */
\r
5959 __IO uint16_t bTXNACK : 1; /* Transmit a NACK */
\r
5960 __IO uint16_t bTR : 1; /* Transmitter/receiver */
\r
5961 __IO uint16_t bTXACK : 1; /* Transmit ACK condition in slave mode */
\r
5962 __IO uint16_t bSSEL : 2; /* eUSCI_B clock source select */
\r
5963 __IO uint16_t bSYNC : 1; /* Synchronous mode enable */
\r
5964 __IO uint16_t bMODE : 2; /* eUSCI_B mode */
\r
5965 __IO uint16_t bMST : 1; /* Master mode select */
\r
5966 __I uint16_t bRESERVED0 : 1; /* Reserved */
\r
5967 __IO uint16_t bMM : 1; /* Multi-master environment select */
\r
5968 __IO uint16_t bSLA10 : 1; /* Slave addressing mode select */
\r
5969 __IO uint16_t bA10 : 1; /* Own addressing mode select */
\r
5971 struct { /* UCB1CTLW0_SPI Bits */
\r
5972 __IO uint16_t bSWRST : 1; /* Software reset enable */
\r
5973 __IO uint16_t bSTEM : 1; /* STE mode select in master mode. */
\r
5974 __I uint16_t bRESERVED : 4; /* Reserved */
\r
5975 __IO uint16_t bSSEL : 2; /* eUSCI_B clock source select */
\r
5976 __IO uint16_t bSYNC : 1; /* Synchronous mode enable */
\r
5977 __IO uint16_t bMODE : 2; /* eUSCI mode */
\r
5978 __IO uint16_t bMST : 1; /* Master mode select */
\r
5979 __IO uint16_t b7BIT : 1; /* Character length */
\r
5980 __IO uint16_t bMSB : 1; /* MSB first select */
\r
5981 __IO uint16_t bCKPL : 1; /* Clock polarity select */
\r
5982 __IO uint16_t bCKPH : 1; /* Clock phase select */
\r
5985 union { /* UCB1CTLW1 Register */
\r
5987 struct { /* UCB1CTLW1 Bits */
\r
5988 __IO uint16_t bGLIT : 2; /* Deglitch time */
\r
5989 __IO uint16_t bASTP : 2; /* Automatic STOP condition generation */
\r
5990 __IO uint16_t bSWACK : 1; /* SW or HW ACK control */
\r
5991 __IO uint16_t bSTPNACK : 1; /* ACK all master bytes */
\r
5992 __IO uint16_t bCLTO : 2; /* Clock low timeout select */
\r
5993 __IO uint16_t bETXINT : 1; /* Early UCTXIFG0 */
\r
5994 __I uint16_t bRESERVED0 : 7; /* Reserved */
\r
5997 uint8_t RESERVED0[2];
\r
5998 __IO uint16_t rBRW; /* eUSCI_Bx Baud Rate Control Word Register */
\r
5999 union { /* UCB1STATW Register */
\r
6001 struct { /* UCB1STATW Bits */
\r
6002 __I uint16_t bRESERVED1 : 4; /* Reserved */
\r
6003 __I uint16_t bBBUSY : 1; /* Bus busy */
\r
6004 __I uint16_t bGC : 1; /* General call address received */
\r
6005 __I uint16_t bSCLLOW : 1; /* SCL low */
\r
6006 __I uint16_t bRESERVED0 : 1; /* Reserved */
\r
6007 __I uint16_t bBCNT : 8; /* Hardware byte counter value */
\r
6009 struct { /* UCB1STATW_SPI Bits */
\r
6010 __I uint16_t bBUSY : 1; /* eUSCI_B busy */
\r
6011 __IO uint16_t bRESERVED : 4; /* Reserved */
\r
6012 __IO uint16_t bOE : 1; /* Overrun error flag */
\r
6013 __IO uint16_t bFE : 1; /* Framing error flag */
\r
6014 __IO uint16_t bLISTEN : 1; /* Listen enable */
\r
6017 union { /* UCB1TBCNT Register */
\r
6019 struct { /* UCB1TBCNT Bits */
\r
6020 __IO uint16_t bTBCNT : 8; /* Byte counter threshold value */
\r
6021 __I uint16_t bRESERVED0 : 8; /* Reserved */
\r
6024 union { /* UCB1RXBUF Register */
\r
6026 struct { /* UCB1RXBUF Bits */
\r
6027 __I uint16_t bRXBUF : 8; /* Receive data buffer */
\r
6028 __I uint16_t bRESERVED0 : 8; /* Reserved */
\r
6030 struct { /* UCB1RXBUF_SPI Bits */
\r
6031 __I uint16_t bRXBUF : 8; /* Receive data buffer */
\r
6032 __I uint16_t bRESERVED : 8; /* Reserved */
\r
6035 union { /* UCB1TXBUF Register */
\r
6037 struct { /* UCB1TXBUF Bits */
\r
6038 __IO uint16_t bTXBUF : 8; /* Transmit data buffer */
\r
6039 __I uint16_t bRESERVED0 : 8; /* Reserved */
\r
6041 struct { /* UCB1TXBUF_SPI Bits */
\r
6042 __IO uint16_t bTXBUF : 8; /* Transmit data buffer */
\r
6043 __I uint16_t bRESERVED : 8; /* Reserved */
\r
6046 uint8_t RESERVED1[4];
\r
6047 union { /* UCB1I2COA0 Register */
\r
6049 struct { /* UCB1I2COA0 Bits */
\r
6050 __IO uint16_t bI2COA0 : 10; /* I2C own address */
\r
6051 __IO uint16_t bOAEN : 1; /* Own Address enable register */
\r
6052 __I uint16_t bRESERVED0 : 4; /* Reserved */
\r
6053 __IO uint16_t bGCEN : 1; /* General call response enable */
\r
6056 union { /* UCB1I2COA1 Register */
\r
6058 struct { /* UCB1I2COA1 Bits */
\r
6059 __IO uint16_t bI2COA1 : 10; /* I2C own address */
\r
6060 __IO uint16_t bOAEN : 1; /* Own Address enable register */
\r
6061 __I uint16_t bRESERVED0 : 5; /* Reserved */
\r
6064 union { /* UCB1I2COA2 Register */
\r
6066 struct { /* UCB1I2COA2 Bits */
\r
6067 __IO uint16_t bI2COA2 : 10; /* I2C own address */
\r
6068 __IO uint16_t bOAEN : 1; /* Own Address enable register */
\r
6069 __I uint16_t bRESERVED0 : 5; /* Reserved */
\r
6072 union { /* UCB1I2COA3 Register */
\r
6074 struct { /* UCB1I2COA3 Bits */
\r
6075 __IO uint16_t bI2COA3 : 10; /* I2C own address */
\r
6076 __IO uint16_t bOAEN : 1; /* Own Address enable register */
\r
6077 __I uint16_t bRESERVED0 : 5; /* Reserved */
\r
6080 union { /* UCB1ADDRX Register */
\r
6082 struct { /* UCB1ADDRX Bits */
\r
6083 __I uint16_t bADDRX : 10; /* Received Address Register */
\r
6084 __I uint16_t bRESERVED0 : 6; /* Reserved */
\r
6087 union { /* UCB1ADDMASK Register */
\r
6089 struct { /* UCB1ADDMASK Bits */
\r
6090 __IO uint16_t bADDMASK : 10; /* */
\r
6091 __I uint16_t bRESERVED0 : 6; /* Reserved */
\r
6094 union { /* UCB1I2CSA Register */
\r
6096 struct { /* UCB1I2CSA Bits */
\r
6097 __IO uint16_t bI2CSA : 10; /* I2C slave address */
\r
6098 __I uint16_t bRESERVED0 : 6; /* Reserved */
\r
6101 uint8_t RESERVED2[8];
\r
6102 union { /* UCB1IE Register */
\r
6104 struct { /* UCB1IE Bits */
\r
6105 __IO uint16_t bRXIE0 : 1; /* Receive interrupt enable 0 */
\r
6106 __IO uint16_t bTXIE0 : 1; /* Transmit interrupt enable 0 */
\r
6107 __IO uint16_t bSTTIE : 1; /* START condition interrupt enable */
\r
6108 __IO uint16_t bSTPIE : 1; /* STOP condition interrupt enable */
\r
6109 __IO uint16_t bALIE : 1; /* Arbitration lost interrupt enable */
\r
6110 __IO uint16_t bNACKIE : 1; /* Not-acknowledge interrupt enable */
\r
6111 __IO uint16_t bBCNTIE : 1; /* Byte counter interrupt enable */
\r
6112 __IO uint16_t bCLTOIE : 1; /* Clock low timeout interrupt enable */
\r
6113 __IO uint16_t bRXIE1 : 1; /* Receive interrupt enable 1 */
\r
6114 __IO uint16_t bTXIE1 : 1; /* Transmit interrupt enable 1 */
\r
6115 __IO uint16_t bRXIE2 : 1; /* Receive interrupt enable 2 */
\r
6116 __IO uint16_t bTXIE2 : 1; /* Transmit interrupt enable 2 */
\r
6117 __IO uint16_t bRXIE3 : 1; /* Receive interrupt enable 3 */
\r
6118 __IO uint16_t bTXIE3 : 1; /* Transmit interrupt enable 3 */
\r
6119 __IO uint16_t bBIT9IE : 1; /* Bit position 9 interrupt enable */
\r
6120 __I uint16_t bRESERVED0 : 1; /* Reserved */
\r
6122 struct { /* UCB1IE_SPI Bits */
\r
6123 __IO uint16_t bRXIE : 1; /* Receive interrupt enable */
\r
6124 __IO uint16_t bTXIE : 1; /* Transmit interrupt enable */
\r
6125 __I uint16_t bRESERVED : 14; /* Reserved */
\r
6128 union { /* UCB1IFG Register */
\r
6130 struct { /* UCB1IFG Bits */
\r
6131 __IO uint16_t bRXIFG0 : 1; /* eUSCI_B receive interrupt flag 0 */
\r
6132 __IO uint16_t bTXIFG0 : 1; /* eUSCI_B transmit interrupt flag 0 */
\r
6133 __IO uint16_t bSTTIFG : 1; /* START condition interrupt flag */
\r
6134 __IO uint16_t bSTPIFG : 1; /* STOP condition interrupt flag */
\r
6135 __IO uint16_t bALIFG : 1; /* Arbitration lost interrupt flag */
\r
6136 __IO uint16_t bNACKIFG : 1; /* Not-acknowledge received interrupt flag */
\r
6137 __IO uint16_t bBCNTIFG : 1; /* Byte counter interrupt flag */
\r
6138 __IO uint16_t bCLTOIFG : 1; /* Clock low timeout interrupt flag */
\r
6139 __IO uint16_t bRXIFG1 : 1; /* eUSCI_B receive interrupt flag 1 */
\r
6140 __IO uint16_t bTXIFG1 : 1; /* eUSCI_B transmit interrupt flag 1 */
\r
6141 __IO uint16_t bRXIFG2 : 1; /* eUSCI_B receive interrupt flag 2 */
\r
6142 __IO uint16_t bTXIFG2 : 1; /* eUSCI_B transmit interrupt flag 2 */
\r
6143 __IO uint16_t bRXIFG3 : 1; /* eUSCI_B receive interrupt flag 3 */
\r
6144 __IO uint16_t bTXIFG3 : 1; /* eUSCI_B transmit interrupt flag 3 */
\r
6145 __IO uint16_t bBIT9IFG : 1; /* Bit position 9 interrupt flag */
\r
6146 __I uint16_t bRESERVED0 : 1; /* Reserved */
\r
6148 struct { /* UCB1IFG_SPI Bits */
\r
6149 __IO uint16_t bRXIFG : 1; /* Receive interrupt flag */
\r
6150 __IO uint16_t bTXIFG : 1; /* Transmit interrupt flag */
\r
6151 __I uint16_t bRESERVED : 14; /* Reserved */
\r
6154 __I uint16_t rIV; /* eUSCI_Bx Interrupt Vector Register */
\r
6158 //*****************************************************************************
\r
6159 // EUSCI_B2 Registers
\r
6160 //*****************************************************************************
\r
6162 union { /* UCB2CTLW0 Register */
\r
6164 struct { /* UCB2CTLW0 Bits */
\r
6165 __IO uint16_t bSWRST : 1; /* Software reset enable */
\r
6166 __IO uint16_t bTXSTT : 1; /* Transmit START condition in master mode */
\r
6167 __IO uint16_t bTXSTP : 1; /* Transmit STOP condition in master mode */
\r
6168 __IO uint16_t bTXNACK : 1; /* Transmit a NACK */
\r
6169 __IO uint16_t bTR : 1; /* Transmitter/receiver */
\r
6170 __IO uint16_t bTXACK : 1; /* Transmit ACK condition in slave mode */
\r
6171 __IO uint16_t bSSEL : 2; /* eUSCI_B clock source select */
\r
6172 __IO uint16_t bSYNC : 1; /* Synchronous mode enable */
\r
6173 __IO uint16_t bMODE : 2; /* eUSCI_B mode */
\r
6174 __IO uint16_t bMST : 1; /* Master mode select */
\r
6175 __I uint16_t bRESERVED0 : 1; /* Reserved */
\r
6176 __IO uint16_t bMM : 1; /* Multi-master environment select */
\r
6177 __IO uint16_t bSLA10 : 1; /* Slave addressing mode select */
\r
6178 __IO uint16_t bA10 : 1; /* Own addressing mode select */
\r
6180 struct { /* UCB2CTLW0_SPI Bits */
\r
6181 __IO uint16_t bSWRST : 1; /* Software reset enable */
\r
6182 __IO uint16_t bSTEM : 1; /* STE mode select in master mode. */
\r
6183 __I uint16_t bRESERVED : 4; /* Reserved */
\r
6184 __IO uint16_t bSSEL : 2; /* eUSCI_B clock source select */
\r
6185 __IO uint16_t bSYNC : 1; /* Synchronous mode enable */
\r
6186 __IO uint16_t bMODE : 2; /* eUSCI mode */
\r
6187 __IO uint16_t bMST : 1; /* Master mode select */
\r
6188 __IO uint16_t b7BIT : 1; /* Character length */
\r
6189 __IO uint16_t bMSB : 1; /* MSB first select */
\r
6190 __IO uint16_t bCKPL : 1; /* Clock polarity select */
\r
6191 __IO uint16_t bCKPH : 1; /* Clock phase select */
\r
6194 union { /* UCB2CTLW1 Register */
\r
6196 struct { /* UCB2CTLW1 Bits */
\r
6197 __IO uint16_t bGLIT : 2; /* Deglitch time */
\r
6198 __IO uint16_t bASTP : 2; /* Automatic STOP condition generation */
\r
6199 __IO uint16_t bSWACK : 1; /* SW or HW ACK control */
\r
6200 __IO uint16_t bSTPNACK : 1; /* ACK all master bytes */
\r
6201 __IO uint16_t bCLTO : 2; /* Clock low timeout select */
\r
6202 __IO uint16_t bETXINT : 1; /* Early UCTXIFG0 */
\r
6203 __I uint16_t bRESERVED0 : 7; /* Reserved */
\r
6206 uint8_t RESERVED0[2];
\r
6207 __IO uint16_t rBRW; /* eUSCI_Bx Baud Rate Control Word Register */
\r
6208 union { /* UCB2STATW Register */
\r
6210 struct { /* UCB2STATW Bits */
\r
6211 __I uint16_t bRESERVED1 : 4; /* Reserved */
\r
6212 __I uint16_t bBBUSY : 1; /* Bus busy */
\r
6213 __I uint16_t bGC : 1; /* General call address received */
\r
6214 __I uint16_t bSCLLOW : 1; /* SCL low */
\r
6215 __I uint16_t bRESERVED0 : 1; /* Reserved */
\r
6216 __I uint16_t bBCNT : 8; /* Hardware byte counter value */
\r
6218 struct { /* UCB2STATW_SPI Bits */
\r
6219 __I uint16_t bBUSY : 1; /* eUSCI_B busy */
\r
6220 __IO uint16_t bRESERVED : 4; /* Reserved */
\r
6221 __IO uint16_t bOE : 1; /* Overrun error flag */
\r
6222 __IO uint16_t bFE : 1; /* Framing error flag */
\r
6223 __IO uint16_t bLISTEN : 1; /* Listen enable */
\r
6226 union { /* UCB2TBCNT Register */
\r
6228 struct { /* UCB2TBCNT Bits */
\r
6229 __IO uint16_t bTBCNT : 8; /* Byte counter threshold value */
\r
6230 __I uint16_t bRESERVED0 : 8; /* Reserved */
\r
6233 union { /* UCB2RXBUF Register */
\r
6235 struct { /* UCB2RXBUF Bits */
\r
6236 __I uint16_t bRXBUF : 8; /* Receive data buffer */
\r
6237 __I uint16_t bRESERVED0 : 8; /* Reserved */
\r
6239 struct { /* UCB2RXBUF_SPI Bits */
\r
6240 __I uint16_t bRXBUF : 8; /* Receive data buffer */
\r
6241 __I uint16_t bRESERVED : 8; /* Reserved */
\r
6244 union { /* UCB2TXBUF Register */
\r
6246 struct { /* UCB2TXBUF Bits */
\r
6247 __IO uint16_t bTXBUF : 8; /* Transmit data buffer */
\r
6248 __I uint16_t bRESERVED0 : 8; /* Reserved */
\r
6250 struct { /* UCB2TXBUF_SPI Bits */
\r
6251 __IO uint16_t bTXBUF : 8; /* Transmit data buffer */
\r
6252 __I uint16_t bRESERVED : 8; /* Reserved */
\r
6255 uint8_t RESERVED1[4];
\r
6256 union { /* UCB2I2COA0 Register */
\r
6258 struct { /* UCB2I2COA0 Bits */
\r
6259 __IO uint16_t bI2COA0 : 10; /* I2C own address */
\r
6260 __IO uint16_t bOAEN : 1; /* Own Address enable register */
\r
6261 __I uint16_t bRESERVED0 : 4; /* Reserved */
\r
6262 __IO uint16_t bGCEN : 1; /* General call response enable */
\r
6265 union { /* UCB2I2COA1 Register */
\r
6267 struct { /* UCB2I2COA1 Bits */
\r
6268 __IO uint16_t bI2COA1 : 10; /* I2C own address */
\r
6269 __IO uint16_t bOAEN : 1; /* Own Address enable register */
\r
6270 __I uint16_t bRESERVED0 : 5; /* Reserved */
\r
6273 union { /* UCB2I2COA2 Register */
\r
6275 struct { /* UCB2I2COA2 Bits */
\r
6276 __IO uint16_t bI2COA2 : 10; /* I2C own address */
\r
6277 __IO uint16_t bOAEN : 1; /* Own Address enable register */
\r
6278 __I uint16_t bRESERVED0 : 5; /* Reserved */
\r
6281 union { /* UCB2I2COA3 Register */
\r
6283 struct { /* UCB2I2COA3 Bits */
\r
6284 __IO uint16_t bI2COA3 : 10; /* I2C own address */
\r
6285 __IO uint16_t bOAEN : 1; /* Own Address enable register */
\r
6286 __I uint16_t bRESERVED0 : 5; /* Reserved */
\r
6289 union { /* UCB2ADDRX Register */
\r
6291 struct { /* UCB2ADDRX Bits */
\r
6292 __I uint16_t bADDRX : 10; /* Received Address Register */
\r
6293 __I uint16_t bRESERVED0 : 6; /* Reserved */
\r
6296 union { /* UCB2ADDMASK Register */
\r
6298 struct { /* UCB2ADDMASK Bits */
\r
6299 __IO uint16_t bADDMASK : 10; /* */
\r
6300 __I uint16_t bRESERVED0 : 6; /* Reserved */
\r
6303 union { /* UCB2I2CSA Register */
\r
6305 struct { /* UCB2I2CSA Bits */
\r
6306 __IO uint16_t bI2CSA : 10; /* I2C slave address */
\r
6307 __I uint16_t bRESERVED0 : 6; /* Reserved */
\r
6310 uint8_t RESERVED2[8];
\r
6311 union { /* UCB2IE Register */
\r
6313 struct { /* UCB2IE Bits */
\r
6314 __IO uint16_t bRXIE0 : 1; /* Receive interrupt enable 0 */
\r
6315 __IO uint16_t bTXIE0 : 1; /* Transmit interrupt enable 0 */
\r
6316 __IO uint16_t bSTTIE : 1; /* START condition interrupt enable */
\r
6317 __IO uint16_t bSTPIE : 1; /* STOP condition interrupt enable */
\r
6318 __IO uint16_t bALIE : 1; /* Arbitration lost interrupt enable */
\r
6319 __IO uint16_t bNACKIE : 1; /* Not-acknowledge interrupt enable */
\r
6320 __IO uint16_t bBCNTIE : 1; /* Byte counter interrupt enable */
\r
6321 __IO uint16_t bCLTOIE : 1; /* Clock low timeout interrupt enable */
\r
6322 __IO uint16_t bRXIE1 : 1; /* Receive interrupt enable 1 */
\r
6323 __IO uint16_t bTXIE1 : 1; /* Transmit interrupt enable 1 */
\r
6324 __IO uint16_t bRXIE2 : 1; /* Receive interrupt enable 2 */
\r
6325 __IO uint16_t bTXIE2 : 1; /* Transmit interrupt enable 2 */
\r
6326 __IO uint16_t bRXIE3 : 1; /* Receive interrupt enable 3 */
\r
6327 __IO uint16_t bTXIE3 : 1; /* Transmit interrupt enable 3 */
\r
6328 __IO uint16_t bBIT9IE : 1; /* Bit position 9 interrupt enable */
\r
6329 __I uint16_t bRESERVED0 : 1; /* Reserved */
\r
6331 struct { /* UCB2IE_SPI Bits */
\r
6332 __IO uint16_t bRXIE : 1; /* Receive interrupt enable */
\r
6333 __IO uint16_t bTXIE : 1; /* Transmit interrupt enable */
\r
6334 __I uint16_t bRESERVED : 14; /* Reserved */
\r
6337 union { /* UCB2IFG Register */
\r
6339 struct { /* UCB2IFG Bits */
\r
6340 __IO uint16_t bRXIFG0 : 1; /* eUSCI_B receive interrupt flag 0 */
\r
6341 __IO uint16_t bTXIFG0 : 1; /* eUSCI_B transmit interrupt flag 0 */
\r
6342 __IO uint16_t bSTTIFG : 1; /* START condition interrupt flag */
\r
6343 __IO uint16_t bSTPIFG : 1; /* STOP condition interrupt flag */
\r
6344 __IO uint16_t bALIFG : 1; /* Arbitration lost interrupt flag */
\r
6345 __IO uint16_t bNACKIFG : 1; /* Not-acknowledge received interrupt flag */
\r
6346 __IO uint16_t bBCNTIFG : 1; /* Byte counter interrupt flag */
\r
6347 __IO uint16_t bCLTOIFG : 1; /* Clock low timeout interrupt flag */
\r
6348 __IO uint16_t bRXIFG1 : 1; /* eUSCI_B receive interrupt flag 1 */
\r
6349 __IO uint16_t bTXIFG1 : 1; /* eUSCI_B transmit interrupt flag 1 */
\r
6350 __IO uint16_t bRXIFG2 : 1; /* eUSCI_B receive interrupt flag 2 */
\r
6351 __IO uint16_t bTXIFG2 : 1; /* eUSCI_B transmit interrupt flag 2 */
\r
6352 __IO uint16_t bRXIFG3 : 1; /* eUSCI_B receive interrupt flag 3 */
\r
6353 __IO uint16_t bTXIFG3 : 1; /* eUSCI_B transmit interrupt flag 3 */
\r
6354 __IO uint16_t bBIT9IFG : 1; /* Bit position 9 interrupt flag */
\r
6355 __I uint16_t bRESERVED0 : 1; /* Reserved */
\r
6357 struct { /* UCB2IFG_SPI Bits */
\r
6358 __IO uint16_t bRXIFG : 1; /* Receive interrupt flag */
\r
6359 __IO uint16_t bTXIFG : 1; /* Transmit interrupt flag */
\r
6360 __I uint16_t bRESERVED : 14; /* Reserved */
\r
6363 __I uint16_t rIV; /* eUSCI_Bx Interrupt Vector Register */
\r
6367 //*****************************************************************************
\r
6368 // EUSCI_B3 Registers
\r
6369 //*****************************************************************************
\r
6371 union { /* UCB3CTLW0 Register */
\r
6373 struct { /* UCB3CTLW0 Bits */
\r
6374 __IO uint16_t bSWRST : 1; /* Software reset enable */
\r
6375 __IO uint16_t bTXSTT : 1; /* Transmit START condition in master mode */
\r
6376 __IO uint16_t bTXSTP : 1; /* Transmit STOP condition in master mode */
\r
6377 __IO uint16_t bTXNACK : 1; /* Transmit a NACK */
\r
6378 __IO uint16_t bTR : 1; /* Transmitter/receiver */
\r
6379 __IO uint16_t bTXACK : 1; /* Transmit ACK condition in slave mode */
\r
6380 __IO uint16_t bSSEL : 2; /* eUSCI_B clock source select */
\r
6381 __IO uint16_t bSYNC : 1; /* Synchronous mode enable */
\r
6382 __IO uint16_t bMODE : 2; /* eUSCI_B mode */
\r
6383 __IO uint16_t bMST : 1; /* Master mode select */
\r
6384 __I uint16_t bRESERVED0 : 1; /* Reserved */
\r
6385 __IO uint16_t bMM : 1; /* Multi-master environment select */
\r
6386 __IO uint16_t bSLA10 : 1; /* Slave addressing mode select */
\r
6387 __IO uint16_t bA10 : 1; /* Own addressing mode select */
\r
6389 struct { /* UCB3CTLW0_SPI Bits */
\r
6390 __IO uint16_t bSWRST : 1; /* Software reset enable */
\r
6391 __IO uint16_t bSTEM : 1; /* STE mode select in master mode. */
\r
6392 __I uint16_t bRESERVED : 4; /* Reserved */
\r
6393 __IO uint16_t bSSEL : 2; /* eUSCI_B clock source select */
\r
6394 __IO uint16_t bSYNC : 1; /* Synchronous mode enable */
\r
6395 __IO uint16_t bMODE : 2; /* eUSCI mode */
\r
6396 __IO uint16_t bMST : 1; /* Master mode select */
\r
6397 __IO uint16_t b7BIT : 1; /* Character length */
\r
6398 __IO uint16_t bMSB : 1; /* MSB first select */
\r
6399 __IO uint16_t bCKPL : 1; /* Clock polarity select */
\r
6400 __IO uint16_t bCKPH : 1; /* Clock phase select */
\r
6403 union { /* UCB3CTLW1 Register */
\r
6405 struct { /* UCB3CTLW1 Bits */
\r
6406 __IO uint16_t bGLIT : 2; /* Deglitch time */
\r
6407 __IO uint16_t bASTP : 2; /* Automatic STOP condition generation */
\r
6408 __IO uint16_t bSWACK : 1; /* SW or HW ACK control */
\r
6409 __IO uint16_t bSTPNACK : 1; /* ACK all master bytes */
\r
6410 __IO uint16_t bCLTO : 2; /* Clock low timeout select */
\r
6411 __IO uint16_t bETXINT : 1; /* Early UCTXIFG0 */
\r
6412 __I uint16_t bRESERVED0 : 7; /* Reserved */
\r
6415 uint8_t RESERVED0[2];
\r
6416 __IO uint16_t rBRW; /* eUSCI_Bx Baud Rate Control Word Register */
\r
6417 union { /* UCB3STATW Register */
\r
6419 struct { /* UCB3STATW Bits */
\r
6420 __I uint16_t bRESERVED1 : 4; /* Reserved */
\r
6421 __I uint16_t bBBUSY : 1; /* Bus busy */
\r
6422 __I uint16_t bGC : 1; /* General call address received */
\r
6423 __I uint16_t bSCLLOW : 1; /* SCL low */
\r
6424 __I uint16_t bRESERVED0 : 1; /* Reserved */
\r
6425 __I uint16_t bBCNT : 8; /* Hardware byte counter value */
\r
6427 struct { /* UCB3STATW_SPI Bits */
\r
6428 __I uint16_t bBUSY : 1; /* eUSCI_B busy */
\r
6429 __IO uint16_t bRESERVED : 4; /* Reserved */
\r
6430 __IO uint16_t bOE : 1; /* Overrun error flag */
\r
6431 __IO uint16_t bFE : 1; /* Framing error flag */
\r
6432 __IO uint16_t bLISTEN : 1; /* Listen enable */
\r
6435 union { /* UCB3TBCNT Register */
\r
6437 struct { /* UCB3TBCNT Bits */
\r
6438 __IO uint16_t bTBCNT : 8; /* Byte counter threshold value */
\r
6439 __I uint16_t bRESERVED0 : 8; /* Reserved */
\r
6442 union { /* UCB3RXBUF Register */
\r
6444 struct { /* UCB3RXBUF Bits */
\r
6445 __I uint16_t bRXBUF : 8; /* Receive data buffer */
\r
6446 __I uint16_t bRESERVED0 : 8; /* Reserved */
\r
6448 struct { /* UCB3RXBUF_SPI Bits */
\r
6449 __I uint16_t bRXBUF : 8; /* Receive data buffer */
\r
6450 __I uint16_t bRESERVED : 8; /* Reserved */
\r
6453 union { /* UCB3TXBUF Register */
\r
6455 struct { /* UCB3TXBUF Bits */
\r
6456 __IO uint16_t bTXBUF : 8; /* Transmit data buffer */
\r
6457 __I uint16_t bRESERVED0 : 8; /* Reserved */
\r
6459 struct { /* UCB3TXBUF_SPI Bits */
\r
6460 __IO uint16_t bTXBUF : 8; /* Transmit data buffer */
\r
6461 __I uint16_t bRESERVED : 8; /* Reserved */
\r
6464 uint8_t RESERVED1[4];
\r
6465 union { /* UCB3I2COA0 Register */
\r
6467 struct { /* UCB3I2COA0 Bits */
\r
6468 __IO uint16_t bI2COA0 : 10; /* I2C own address */
\r
6469 __IO uint16_t bOAEN : 1; /* Own Address enable register */
\r
6470 __I uint16_t bRESERVED0 : 4; /* Reserved */
\r
6471 __IO uint16_t bGCEN : 1; /* General call response enable */
\r
6474 union { /* UCB3I2COA1 Register */
\r
6476 struct { /* UCB3I2COA1 Bits */
\r
6477 __IO uint16_t bI2COA1 : 10; /* I2C own address */
\r
6478 __IO uint16_t bOAEN : 1; /* Own Address enable register */
\r
6479 __I uint16_t bRESERVED0 : 5; /* Reserved */
\r
6482 union { /* UCB3I2COA2 Register */
\r
6484 struct { /* UCB3I2COA2 Bits */
\r
6485 __IO uint16_t bI2COA2 : 10; /* I2C own address */
\r
6486 __IO uint16_t bOAEN : 1; /* Own Address enable register */
\r
6487 __I uint16_t bRESERVED0 : 5; /* Reserved */
\r
6490 union { /* UCB3I2COA3 Register */
\r
6492 struct { /* UCB3I2COA3 Bits */
\r
6493 __IO uint16_t bI2COA3 : 10; /* I2C own address */
\r
6494 __IO uint16_t bOAEN : 1; /* Own Address enable register */
\r
6495 __I uint16_t bRESERVED0 : 5; /* Reserved */
\r
6498 union { /* UCB3ADDRX Register */
\r
6500 struct { /* UCB3ADDRX Bits */
\r
6501 __I uint16_t bADDRX : 10; /* Received Address Register */
\r
6502 __I uint16_t bRESERVED0 : 6; /* Reserved */
\r
6505 union { /* UCB3ADDMASK Register */
\r
6507 struct { /* UCB3ADDMASK Bits */
\r
6508 __IO uint16_t bADDMASK : 10; /* */
\r
6509 __I uint16_t bRESERVED0 : 6; /* Reserved */
\r
6512 union { /* UCB3I2CSA Register */
\r
6514 struct { /* UCB3I2CSA Bits */
\r
6515 __IO uint16_t bI2CSA : 10; /* I2C slave address */
\r
6516 __I uint16_t bRESERVED0 : 6; /* Reserved */
\r
6519 uint8_t RESERVED2[8];
\r
6520 union { /* UCB3IE Register */
\r
6522 struct { /* UCB3IE Bits */
\r
6523 __IO uint16_t bRXIE0 : 1; /* Receive interrupt enable 0 */
\r
6524 __IO uint16_t bTXIE0 : 1; /* Transmit interrupt enable 0 */
\r
6525 __IO uint16_t bSTTIE : 1; /* START condition interrupt enable */
\r
6526 __IO uint16_t bSTPIE : 1; /* STOP condition interrupt enable */
\r
6527 __IO uint16_t bALIE : 1; /* Arbitration lost interrupt enable */
\r
6528 __IO uint16_t bNACKIE : 1; /* Not-acknowledge interrupt enable */
\r
6529 __IO uint16_t bBCNTIE : 1; /* Byte counter interrupt enable */
\r
6530 __IO uint16_t bCLTOIE : 1; /* Clock low timeout interrupt enable */
\r
6531 __IO uint16_t bRXIE1 : 1; /* Receive interrupt enable 1 */
\r
6532 __IO uint16_t bTXIE1 : 1; /* Transmit interrupt enable 1 */
\r
6533 __IO uint16_t bRXIE2 : 1; /* Receive interrupt enable 2 */
\r
6534 __IO uint16_t bTXIE2 : 1; /* Transmit interrupt enable 2 */
\r
6535 __IO uint16_t bRXIE3 : 1; /* Receive interrupt enable 3 */
\r
6536 __IO uint16_t bTXIE3 : 1; /* Transmit interrupt enable 3 */
\r
6537 __IO uint16_t bBIT9IE : 1; /* Bit position 9 interrupt enable */
\r
6538 __I uint16_t bRESERVED0 : 1; /* Reserved */
\r
6540 struct { /* UCB3IE_SPI Bits */
\r
6541 __IO uint16_t bRXIE : 1; /* Receive interrupt enable */
\r
6542 __IO uint16_t bTXIE : 1; /* Transmit interrupt enable */
\r
6543 __I uint16_t bRESERVED : 14; /* Reserved */
\r
6546 union { /* UCB3IFG Register */
\r
6548 struct { /* UCB3IFG Bits */
\r
6549 __IO uint16_t bRXIFG0 : 1; /* eUSCI_B receive interrupt flag 0 */
\r
6550 __IO uint16_t bTXIFG0 : 1; /* eUSCI_B transmit interrupt flag 0 */
\r
6551 __IO uint16_t bSTTIFG : 1; /* START condition interrupt flag */
\r
6552 __IO uint16_t bSTPIFG : 1; /* STOP condition interrupt flag */
\r
6553 __IO uint16_t bALIFG : 1; /* Arbitration lost interrupt flag */
\r
6554 __IO uint16_t bNACKIFG : 1; /* Not-acknowledge received interrupt flag */
\r
6555 __IO uint16_t bBCNTIFG : 1; /* Byte counter interrupt flag */
\r
6556 __IO uint16_t bCLTOIFG : 1; /* Clock low timeout interrupt flag */
\r
6557 __IO uint16_t bRXIFG1 : 1; /* eUSCI_B receive interrupt flag 1 */
\r
6558 __IO uint16_t bTXIFG1 : 1; /* eUSCI_B transmit interrupt flag 1 */
\r
6559 __IO uint16_t bRXIFG2 : 1; /* eUSCI_B receive interrupt flag 2 */
\r
6560 __IO uint16_t bTXIFG2 : 1; /* eUSCI_B transmit interrupt flag 2 */
\r
6561 __IO uint16_t bRXIFG3 : 1; /* eUSCI_B receive interrupt flag 3 */
\r
6562 __IO uint16_t bTXIFG3 : 1; /* eUSCI_B transmit interrupt flag 3 */
\r
6563 __IO uint16_t bBIT9IFG : 1; /* Bit position 9 interrupt flag */
\r
6564 __I uint16_t bRESERVED0 : 1; /* Reserved */
\r
6566 struct { /* UCB3IFG_SPI Bits */
\r
6567 __IO uint16_t bRXIFG : 1; /* Receive interrupt flag */
\r
6568 __IO uint16_t bTXIFG : 1; /* Transmit interrupt flag */
\r
6569 __I uint16_t bRESERVED : 14; /* Reserved */
\r
6572 __I uint16_t rIV; /* eUSCI_Bx Interrupt Vector Register */
\r
6576 //*****************************************************************************
\r
6577 // FLCTL Registers
\r
6578 //*****************************************************************************
\r
6580 union { /* FLCTL_POWER_STAT Register */
\r
6582 struct { /* FLCTL_POWER_STAT Bits */
\r
6583 __I uint32_t bPSTAT : 3; /* */
\r
6584 __I uint32_t bLDOSTAT : 1; /* PSS FLDO GOOD status */
\r
6585 __I uint32_t bVREFSTAT : 1; /* PSS VREF stable status */
\r
6586 __I uint32_t bIREFSTAT : 1; /* PSS IREF stable status */
\r
6587 __I uint32_t bTRIMSTAT : 1; /* PSS trim done status */
\r
6588 __I uint32_t bRD_2T : 1; /* Indicates if Flash is being accessed in 2T mode */
\r
6589 __I uint32_t bRESERVED0 : 24; /* Reserved */
\r
6592 uint8_t RESERVED0[12];
\r
6593 union { /* FLCTL_BANK0_RDCTL Register */
\r
6595 struct { /* FLCTL_BANK0_RDCTL Bits */
\r
6596 __IO uint32_t bRD_MODE : 4; /* Flash read mode control setting for Bank 0 */
\r
6597 __IO uint32_t bBUFI : 1; /* Enables read buffering feature for instruction fetches to this Bank */
\r
6598 __IO uint32_t bBUFD : 1; /* Enables read buffering feature for data reads to this Bank */
\r
6599 __I uint32_t bRESERVED0 : 2; /* Reserved */
\r
6600 __IO uint32_t bRESERVED1 : 1; /* Reserved */
\r
6601 __IO uint32_t bRESERVED2 : 1; /* Reserved */
\r
6602 __IO uint32_t bRESERVED3 : 1; /* Reserved */
\r
6603 __IO uint32_t bRESERVED4 : 1; /* Reserved */
\r
6604 __IO uint32_t bWAIT : 4; /* Number of wait states for read */
\r
6605 __I uint32_t bRD_MODE_STATUS : 4; /* Read mode */
\r
6606 __I uint32_t bRESERVED5 : 12; /* Reserved */
\r
6609 union { /* FLCTL_BANK1_RDCTL Register */
\r
6611 struct { /* FLCTL_BANK1_RDCTL Bits */
\r
6612 __IO uint32_t bRD_MODE : 4; /* Flash read mode control setting for Bank 0 */
\r
6613 __IO uint32_t bBUFI : 1; /* Enables read buffering feature for instruction fetches to this Bank */
\r
6614 __IO uint32_t bBUFD : 1; /* Enables read buffering feature for data reads to this Bank */
\r
6615 __I uint32_t bRESERVED0 : 2; /* Reserved */
\r
6616 __IO uint32_t bRESERVED1 : 1; /* Reserved */
\r
6617 __IO uint32_t bRESERVED2 : 1; /* Reserved */
\r
6618 __IO uint32_t bRESERVED3 : 1; /* Reserved */
\r
6619 __IO uint32_t bRESERVED4 : 1; /* Reserved */
\r
6620 __IO uint32_t bWAIT : 4; /* Number of wait states for read */
\r
6621 __I uint32_t bRD_MODE_STATUS : 4; /* Read mode */
\r
6622 __I uint32_t bRESERVED5 : 12; /* Reserved */
\r
6625 uint8_t RESERVED1[8];
\r
6626 union { /* FLCTL_RDBRST_CTLSTAT Register */
\r
6628 struct { /* FLCTL_RDBRST_CTLSTAT Bits */
\r
6629 __O uint32_t bSTART : 1; /* Start of burst/compare operation */
\r
6630 __IO uint32_t bMEM_TYPE : 2; /* Type of memory that burst is carried out on */
\r
6631 __IO uint32_t bSTOP_FAIL : 1; /* Terminate burst/compare operation */
\r
6632 __IO uint32_t bDATA_CMP : 1; /* Data pattern used for comparison against memory read data */
\r
6633 __IO uint32_t bRESERVED0 : 1; /* Reserved */
\r
6634 __IO uint32_t bTEST_EN : 1; /* Enable comparison against test data compare registers */
\r
6635 __I uint32_t bRESERVED1 : 9; /* Reserved */
\r
6636 __I uint32_t bBRST_STAT : 2; /* Status of Burst/Compare operation */
\r
6637 __I uint32_t bCMP_ERR : 1; /* Burst/Compare Operation encountered atleast one data */
\r
6638 __I uint32_t bADDR_ERR : 1; /* Burst/Compare Operation was terminated due to access to */
\r
6639 __I uint32_t bRESERVED2 : 3; /* Reserved */
\r
6640 __O uint32_t bCLR_STAT : 1; /* Clear status bits 19-16 of this register */
\r
6641 __I uint32_t bRESERVED3 : 8; /* Reserved */
\r
6643 } rRDBRST_CTLSTAT;
\r
6644 union { /* FLCTL_RDBRST_STARTADDR Register */
\r
6646 struct { /* FLCTL_RDBRST_STARTADDR Bits */
\r
6647 __IO uint32_t bSTART_ADDRESS : 21; /* Start Address of Burst Operation */
\r
6648 __I uint32_t bRESERVED0 : 11; /* Reserved */
\r
6650 } rRDBRST_STARTADDR;
\r
6651 union { /* FLCTL_RDBRST_LEN Register */
\r
6653 struct { /* FLCTL_RDBRST_LEN Bits */
\r
6654 __IO uint32_t bBURST_LENGTH : 21; /* Length of Burst Operation */
\r
6655 __I uint32_t bRESERVED0 : 11; /* Reserved */
\r
6658 uint8_t RESERVED2[16];
\r
6659 union { /* FLCTL_RDBRST_FAILADDR Register */
\r
6661 struct { /* FLCTL_RDBRST_FAILADDR Bits */
\r
6662 __IO uint32_t bFAIL_ADDRESS : 21; /* Reflects address of last failed compare */
\r
6663 __I uint32_t bRESERVED0 : 11; /* Reserved */
\r
6665 } rRDBRST_FAILADDR;
\r
6666 union { /* FLCTL_RDBRST_FAILCNT Register */
\r
6668 struct { /* FLCTL_RDBRST_FAILCNT Bits */
\r
6669 __IO uint32_t bFAIL_COUNT : 17; /* Number of failures encountered in burst operation */
\r
6670 __I uint32_t bRESERVED0 : 15; /* Reserved */
\r
6672 } rRDBRST_FAILCNT;
\r
6673 uint8_t RESERVED3[12];
\r
6674 union { /* FLCTL_PRG_CTLSTAT Register */
\r
6676 struct { /* FLCTL_PRG_CTLSTAT Bits */
\r
6677 __IO uint32_t bENABLE : 1; /* Master control for all word program operations */
\r
6678 __IO uint32_t bMODE : 1; /* Write mode */
\r
6679 __IO uint32_t bVER_PRE : 1; /* Controls automatic pre program verify operations */
\r
6680 __IO uint32_t bVER_PST : 1; /* Controls automatic post program verify operations */
\r
6681 __I uint32_t bRESERVED0 : 12; /* Reserved */
\r
6682 __I uint32_t bSTATUS : 2; /* Status of program operations in the Flash memory */
\r
6683 __I uint32_t bBNK_ACT : 1; /* Bank active */
\r
6684 __I uint32_t bRESERVED1 : 13; /* Reserved */
\r
6687 union { /* FLCTL_PRGBRST_CTLSTAT Register */
\r
6689 struct { /* FLCTL_PRGBRST_CTLSTAT Bits */
\r
6690 __O uint32_t bSTART : 1; /* Trigger start of burst program operation */
\r
6691 __IO uint32_t bTYPE : 2; /* Type of memory that burst program is carried out on */
\r
6692 __IO uint32_t bLEN : 3; /* Length of burst */
\r
6693 __IO uint32_t bAUTO_PRE : 1; /* Auto-Verify operation before the Burst Program */
\r
6694 __IO uint32_t bAUTO_PST : 1; /* Auto-Verify operation after the Burst Program */
\r
6695 __I uint32_t bRESERVED0 : 8; /* Reserved */
\r
6696 __I uint32_t bBURST_STATUS : 3; /* Status of a Burst Operation */
\r
6697 __I uint32_t bPRE_ERR : 1; /* Burst Operation encountered preprogram auto-verify errors */
\r
6698 __I uint32_t bPST_ERR : 1; /* Burst Operation encountered postprogram auto-verify errors */
\r
6699 __I uint32_t bADDR_ERR : 1; /* Burst Operation was terminated due to attempted program of reserved memory */
\r
6700 __I uint32_t bRESERVED1 : 1; /* Reserved */
\r
6701 __O uint32_t bCLR_STAT : 1; /* Clear status bits 21-16 of this register */
\r
6702 __I uint32_t bRESERVED2 : 8; /* Reserved */
\r
6704 } rPRGBRST_CTLSTAT;
\r
6705 union { /* FLCTL_PRGBRST_STARTADDR Register */
\r
6707 struct { /* FLCTL_PRGBRST_STARTADDR Bits */
\r
6708 __IO uint32_t bSTART_ADDRESS : 22; /* Start Address of Program Burst Operation */
\r
6709 __I uint32_t bRESERVED0 : 10; /* Reserved */
\r
6711 } rPRGBRST_STARTADDR;
\r
6712 uint8_t RESERVED4[4];
\r
6713 __IO uint32_t rPRGBRST_DATA0_0; /* Program Burst Data0 Register0 */
\r
6714 __IO uint32_t rPRGBRST_DATA0_1; /* Program Burst Data0 Register1 */
\r
6715 __IO uint32_t rPRGBRST_DATA0_2; /* Program Burst Data0 Register2 */
\r
6716 __IO uint32_t rPRGBRST_DATA0_3; /* Program Burst Data0 Register3 */
\r
6717 __IO uint32_t rPRGBRST_DATA1_0; /* Program Burst Data1 Register0 */
\r
6718 __IO uint32_t rPRGBRST_DATA1_1; /* Program Burst Data1 Register1 */
\r
6719 __IO uint32_t rPRGBRST_DATA1_2; /* Program Burst Data1 Register2 */
\r
6720 __IO uint32_t rPRGBRST_DATA1_3; /* Program Burst Data1 Register3 */
\r
6721 __IO uint32_t rPRGBRST_DATA2_0; /* Program Burst Data2 Register0 */
\r
6722 __IO uint32_t rPRGBRST_DATA2_1; /* Program Burst Data2 Register1 */
\r
6723 __IO uint32_t rPRGBRST_DATA2_2; /* Program Burst Data2 Register2 */
\r
6724 __IO uint32_t rPRGBRST_DATA2_3; /* Program Burst Data2 Register3 */
\r
6725 __IO uint32_t rPRGBRST_DATA3_0; /* Program Burst Data3 Register0 */
\r
6726 __IO uint32_t rPRGBRST_DATA3_1; /* Program Burst Data3 Register1 */
\r
6727 __IO uint32_t rPRGBRST_DATA3_2; /* Program Burst Data3 Register2 */
\r
6728 __IO uint32_t rPRGBRST_DATA3_3; /* Program Burst Data3 Register3 */
\r
6729 union { /* FLCTL_ERASE_CTLSTAT Register */
\r
6731 struct { /* FLCTL_ERASE_CTLSTAT Bits */
\r
6732 __O uint32_t bSTART : 1; /* Start of Erase operation */
\r
6733 __IO uint32_t bMODE : 1; /* Erase mode selected by application */
\r
6734 __IO uint32_t bTYPE : 2; /* Type of memory that erase operation is carried out on */
\r
6735 __I uint32_t bRESERVED0 : 12; /* Reserved */
\r
6736 __I uint32_t bSTATUS : 2; /* Status of erase operations in the Flash memory */
\r
6737 __I uint32_t bADDR_ERR : 1; /* Erase Operation was terminated due to attempted erase of reserved memory address */
\r
6738 __O uint32_t bCLR_STAT : 1; /* Clear status bits 18-16 of this register */
\r
6739 __I uint32_t bRESERVED1 : 12; /* Reserved */
\r
6742 union { /* FLCTL_ERASE_SECTADDR Register */
\r
6744 struct { /* FLCTL_ERASE_SECTADDR Bits */
\r
6745 __IO uint32_t bSECT_ADDRESS : 22; /* Address of Sector being Erased */
\r
6746 __I uint32_t bRESERVED0 : 10; /* Reserved */
\r
6748 } rERASE_SECTADDR;
\r
6749 uint8_t RESERVED5[8];
\r
6750 union { /* FLCTL_BANK0_INFO_WEPROT Register */
\r
6752 struct { /* FLCTL_BANK0_INFO_WEPROT Bits */
\r
6753 __IO uint32_t bPROT0 : 1; /* Protects Sector 0 from program or erase */
\r
6754 __IO uint32_t bPROT1 : 1; /* Protects Sector 1 from program or erase */
\r
6755 __I uint32_t bRESERVED0 : 30; /* Reserved */
\r
6757 } rBANK0_INFO_WEPROT;
\r
6758 union { /* FLCTL_BANK0_MAIN_WEPROT Register */
\r
6760 struct { /* FLCTL_BANK0_MAIN_WEPROT Bits */
\r
6761 __IO uint32_t bPROT0 : 1; /* Protects Sector 0 from program or erase */
\r
6762 __IO uint32_t bPROT1 : 1; /* Protects Sector 1 from program or erase */
\r
6763 __IO uint32_t bPROT2 : 1; /* Protects Sector 2 from program or erase */
\r
6764 __IO uint32_t bPROT3 : 1; /* Protects Sector 3 from program or erase */
\r
6765 __IO uint32_t bPROT4 : 1; /* Protects Sector 4 from program or erase */
\r
6766 __IO uint32_t bPROT5 : 1; /* Protects Sector 5 from program or erase */
\r
6767 __IO uint32_t bPROT6 : 1; /* Protects Sector 6 from program or erase */
\r
6768 __IO uint32_t bPROT7 : 1; /* Protects Sector 7 from program or erase */
\r
6769 __IO uint32_t bPROT8 : 1; /* Protects Sector 8 from program or erase */
\r
6770 __IO uint32_t bPROT9 : 1; /* Protects Sector 9 from program or erase */
\r
6771 __IO uint32_t bPROT10 : 1; /* Protects Sector 10 from program or erase */
\r
6772 __IO uint32_t bPROT11 : 1; /* Protects Sector 11 from program or erase */
\r
6773 __IO uint32_t bPROT12 : 1; /* Protects Sector 12 from program or erase */
\r
6774 __IO uint32_t bPROT13 : 1; /* Protects Sector 13 from program or erase */
\r
6775 __IO uint32_t bPROT14 : 1; /* Protects Sector 14 from program or erase */
\r
6776 __IO uint32_t bPROT15 : 1; /* Protects Sector 15 from program or erase */
\r
6777 __IO uint32_t bPROT16 : 1; /* Protects Sector 16 from program or erase */
\r
6778 __IO uint32_t bPROT17 : 1; /* Protects Sector 17 from program or erase */
\r
6779 __IO uint32_t bPROT18 : 1; /* Protects Sector 18 from program or erase */
\r
6780 __IO uint32_t bPROT19 : 1; /* Protects Sector 19 from program or erase */
\r
6781 __IO uint32_t bPROT20 : 1; /* Protects Sector 20 from program or erase */
\r
6782 __IO uint32_t bPROT21 : 1; /* Protects Sector 21 from program or erase */
\r
6783 __IO uint32_t bPROT22 : 1; /* Protects Sector 22 from program or erase */
\r
6784 __IO uint32_t bPROT23 : 1; /* Protects Sector 23 from program or erase */
\r
6785 __IO uint32_t bPROT24 : 1; /* Protects Sector 24 from program or erase */
\r
6786 __IO uint32_t bPROT25 : 1; /* Protects Sector 25 from program or erase */
\r
6787 __IO uint32_t bPROT26 : 1; /* Protects Sector 26 from program or erase */
\r
6788 __IO uint32_t bPROT27 : 1; /* Protects Sector 27 from program or erase */
\r
6789 __IO uint32_t bPROT28 : 1; /* Protects Sector 28 from program or erase */
\r
6790 __IO uint32_t bPROT29 : 1; /* Protects Sector 29 from program or erase */
\r
6791 __IO uint32_t bPROT30 : 1; /* Protects Sector 30 from program or erase */
\r
6792 __IO uint32_t bPROT31 : 1; /* Protects Sector 31 from program or erase */
\r
6794 } rBANK0_MAIN_WEPROT;
\r
6795 uint8_t RESERVED6[8];
\r
6796 union { /* FLCTL_BANK1_INFO_WEPROT Register */
\r
6798 struct { /* FLCTL_BANK1_INFO_WEPROT Bits */
\r
6799 __IO uint32_t bPROT0 : 1; /* Protects Sector 0 from program or erase operations */
\r
6800 __IO uint32_t bPROT1 : 1; /* Protects Sector 1 from program or erase operations */
\r
6801 __I uint32_t bRESERVED0 : 30; /* Reserved */
\r
6803 } rBANK1_INFO_WEPROT;
\r
6804 union { /* FLCTL_BANK1_MAIN_WEPROT Register */
\r
6806 struct { /* FLCTL_BANK1_MAIN_WEPROT Bits */
\r
6807 __IO uint32_t bPROT0 : 1; /* Protects Sector 0 from program or erase operations */
\r
6808 __IO uint32_t bPROT1 : 1; /* Protects Sector 1 from program or erase operations */
\r
6809 __IO uint32_t bPROT2 : 1; /* Protects Sector 2 from program or erase operations */
\r
6810 __IO uint32_t bPROT3 : 1; /* Protects Sector 3 from program or erase operations */
\r
6811 __IO uint32_t bPROT4 : 1; /* Protects Sector 4 from program or erase operations */
\r
6812 __IO uint32_t bPROT5 : 1; /* Protects Sector 5 from program or erase operations */
\r
6813 __IO uint32_t bPROT6 : 1; /* Protects Sector 6 from program or erase operations */
\r
6814 __IO uint32_t bPROT7 : 1; /* Protects Sector 7 from program or erase operations */
\r
6815 __IO uint32_t bPROT8 : 1; /* Protects Sector 8 from program or erase operations */
\r
6816 __IO uint32_t bPROT9 : 1; /* Protects Sector 9 from program or erase operations */
\r
6817 __IO uint32_t bPROT10 : 1; /* Protects Sector 10 from program or erase operations */
\r
6818 __IO uint32_t bPROT11 : 1; /* Protects Sector 11 from program or erase operations */
\r
6819 __IO uint32_t bPROT12 : 1; /* Protects Sector 12 from program or erase operations */
\r
6820 __IO uint32_t bPROT13 : 1; /* Protects Sector 13 from program or erase operations */
\r
6821 __IO uint32_t bPROT14 : 1; /* Protects Sector 14 from program or erase operations */
\r
6822 __IO uint32_t bPROT15 : 1; /* Protects Sector 15 from program or erase operations */
\r
6823 __IO uint32_t bPROT16 : 1; /* Protects Sector 16 from program or erase operations */
\r
6824 __IO uint32_t bPROT17 : 1; /* Protects Sector 17 from program or erase operations */
\r
6825 __IO uint32_t bPROT18 : 1; /* Protects Sector 18 from program or erase operations */
\r
6826 __IO uint32_t bPROT19 : 1; /* Protects Sector 19 from program or erase operations */
\r
6827 __IO uint32_t bPROT20 : 1; /* Protects Sector 20 from program or erase operations */
\r
6828 __IO uint32_t bPROT21 : 1; /* Protects Sector 21 from program or erase operations */
\r
6829 __IO uint32_t bPROT22 : 1; /* Protects Sector 22 from program or erase operations */
\r
6830 __IO uint32_t bPROT23 : 1; /* Protects Sector 23 from program or erase operations */
\r
6831 __IO uint32_t bPROT24 : 1; /* Protects Sector 24 from program or erase operations */
\r
6832 __IO uint32_t bPROT25 : 1; /* Protects Sector 25 from program or erase operations */
\r
6833 __IO uint32_t bPROT26 : 1; /* Protects Sector 26 from program or erase operations */
\r
6834 __IO uint32_t bPROT27 : 1; /* Protects Sector 27 from program or erase operations */
\r
6835 __IO uint32_t bPROT28 : 1; /* Protects Sector 28 from program or erase operations */
\r
6836 __IO uint32_t bPROT29 : 1; /* Protects Sector 29 from program or erase operations */
\r
6837 __IO uint32_t bPROT30 : 1; /* Protects Sector 30 from program or erase operations */
\r
6838 __IO uint32_t bPROT31 : 1; /* Protects Sector 31 from program or erase operations */
\r
6840 } rBANK1_MAIN_WEPROT;
\r
6841 uint8_t RESERVED7[8];
\r
6842 union { /* FLCTL_BMRK_CTLSTAT Register */
\r
6844 struct { /* FLCTL_BMRK_CTLSTAT Bits */
\r
6845 __IO uint32_t bI_BMRK : 1; /* */
\r
6846 __IO uint32_t bD_BMRK : 1; /* */
\r
6847 __IO uint32_t bCMP_EN : 1; /* */
\r
6848 __IO uint32_t bCMP_SEL : 1; /* */
\r
6849 __I uint32_t bRESERVED0 : 28; /* Reserved */
\r
6852 __IO uint32_t rBMRK_IFETCH; /* Benchmark Instruction Fetch Count Register */
\r
6853 __IO uint32_t rBMRK_DREAD; /* Benchmark Data Read Count Register */
\r
6854 __IO uint32_t rBMRK_CMP; /* Benchmark Count Compare Register */
\r
6855 uint8_t RESERVED8[16];
\r
6856 union { /* FLCTL_IFG Register */
\r
6858 struct { /* FLCTL_IFG Bits */
\r
6859 __I uint32_t bRDBRST : 1; /* */
\r
6860 __I uint32_t bAVPRE : 1; /* */
\r
6861 __I uint32_t bAVPST : 1; /* */
\r
6862 __I uint32_t bPRG : 1; /* */
\r
6863 __I uint32_t bPRGB : 1; /* */
\r
6864 __I uint32_t bERASE : 1; /* */
\r
6865 __I uint32_t bRESERVED0 : 1; /* Reserved */
\r
6866 __I uint32_t bRESERVED1 : 1; /* Reserved */
\r
6867 __I uint32_t bBMRK : 1; /* */
\r
6868 __I uint32_t bPRG_ERR : 1; /* */
\r
6869 __I uint32_t bRESERVED2 : 22; /* Reserved */
\r
6872 union { /* FLCTL_IE Register */
\r
6874 struct { /* FLCTL_IE Bits */
\r
6875 __IO uint32_t bRDBRST : 1; /* */
\r
6876 __IO uint32_t bAVPRE : 1; /* */
\r
6877 __IO uint32_t bAVPST : 1; /* */
\r
6878 __IO uint32_t bPRG : 1; /* */
\r
6879 __IO uint32_t bPRGB : 1; /* */
\r
6880 __IO uint32_t bERASE : 1; /* */
\r
6881 __IO uint32_t bRESERVED0 : 1; /* Reserved */
\r
6882 __IO uint32_t bRESERVED1 : 1; /* Reserved */
\r
6883 __IO uint32_t bBMRK : 1; /* */
\r
6884 __IO uint32_t bPRG_ERR : 1; /* */
\r
6885 __I uint32_t bRESERVED2 : 22; /* Reserved */
\r
6888 union { /* FLCTL_CLRIFG Register */
\r
6890 struct { /* FLCTL_CLRIFG Bits */
\r
6891 __O uint32_t bRDBRST : 1; /* */
\r
6892 __O uint32_t bAVPRE : 1; /* */
\r
6893 __O uint32_t bAVPST : 1; /* */
\r
6894 __O uint32_t bPRG : 1; /* */
\r
6895 __O uint32_t bPRGB : 1; /* */
\r
6896 __O uint32_t bERASE : 1; /* */
\r
6897 __O uint32_t bRESERVED0 : 1; /* Reserved */
\r
6898 __O uint32_t bRESERVED1 : 1; /* Reserved */
\r
6899 __O uint32_t bBMRK : 1; /* */
\r
6900 __O uint32_t bPRG_ERR : 1; /* */
\r
6901 __I uint32_t bRESERVED2 : 22; /* Reserved */
\r
6904 union { /* FLCTL_SETIFG Register */
\r
6906 struct { /* FLCTL_SETIFG Bits */
\r
6907 __O uint32_t bRDBRST : 1; /* */
\r
6908 __O uint32_t bAVPRE : 1; /* */
\r
6909 __O uint32_t bAVPST : 1; /* */
\r
6910 __O uint32_t bPRG : 1; /* */
\r
6911 __O uint32_t bPRGB : 1; /* */
\r
6912 __O uint32_t bERASE : 1; /* */
\r
6913 __O uint32_t bRESERVED0 : 1; /* Reserved */
\r
6914 __O uint32_t bRESERVED1 : 1; /* Reserved */
\r
6915 __O uint32_t bBMRK : 1; /* */
\r
6916 __O uint32_t bPRG_ERR : 1; /* */
\r
6917 __I uint32_t bRESERVED2 : 22; /* Reserved */
\r
6920 union { /* FLCTL_READ_TIMCTL Register */
\r
6922 struct { /* FLCTL_READ_TIMCTL Bits */
\r
6923 __IO uint32_t bSETUP : 8; /* */
\r
6924 __IO uint32_t bHOLD : 4; /* */
\r
6925 __IO uint32_t bIREF_BOOST1 : 4; /* */
\r
6926 __IO uint32_t bSETUP_LONG : 8; /* */
\r
6927 __I uint32_t bRESERVED0 : 8; /* Reserved */
\r
6930 union { /* FLCTL_READMARGIN_TIMCTL Register */
\r
6932 struct { /* FLCTL_READMARGIN_TIMCTL Bits */
\r
6933 __IO uint32_t bSETUP : 8; /* */
\r
6934 __IO uint32_t bHOLD : 4; /* */
\r
6935 __I uint32_t bRESERVED0 : 4; /* Reserved */
\r
6936 __I uint32_t bRESERVED1 : 16; /* Reserved */
\r
6938 } rREADMARGIN_TIMCTL;
\r
6939 union { /* FLCTL_PRGVER_TIMCTL Register */
\r
6941 struct { /* FLCTL_PRGVER_TIMCTL Bits */
\r
6942 __IO uint32_t bSETUP : 8; /* */
\r
6943 __IO uint32_t bACTIVE : 4; /* */
\r
6944 __IO uint32_t bHOLD : 4; /* */
\r
6945 __I uint32_t bRESERVED0 : 16; /* Reserved */
\r
6948 union { /* FLCTL_ERSVER_TIMCTL Register */
\r
6950 struct { /* FLCTL_ERSVER_TIMCTL Bits */
\r
6951 __IO uint32_t bSETUP : 8; /* */
\r
6952 __IO uint32_t bHOLD : 4; /* */
\r
6953 __I uint32_t bRESERVED0 : 4; /* Reserved */
\r
6954 __I uint32_t bRESERVED1 : 16; /* Reserved */
\r
6957 union { /* FLCTL_LKGVER_TIMCTL Register */
\r
6959 struct { /* FLCTL_LKGVER_TIMCTL Bits */
\r
6960 __IO uint32_t bSETUP : 8; /* */
\r
6961 __IO uint32_t bHOLD : 4; /* */
\r
6962 __I uint32_t bRESERVED0 : 4; /* Reserved */
\r
6963 __I uint32_t bRESERVED1 : 16; /* Reserved */
\r
6966 union { /* FLCTL_PROGRAM_TIMCTL Register */
\r
6968 struct { /* FLCTL_PROGRAM_TIMCTL Bits */
\r
6969 __IO uint32_t bSETUP : 8; /* */
\r
6970 __IO uint32_t bACTIVE : 20; /* */
\r
6971 __IO uint32_t bHOLD : 4; /* */
\r
6973 } rPROGRAM_TIMCTL;
\r
6974 union { /* FLCTL_ERASE_TIMCTL Register */
\r
6976 struct { /* FLCTL_ERASE_TIMCTL Bits */
\r
6977 __IO uint32_t bSETUP : 8; /* */
\r
6978 __IO uint32_t bACTIVE : 20; /* */
\r
6979 __IO uint32_t bHOLD : 4; /* */
\r
6982 union { /* FLCTL_MASSERASE_TIMCTL Register */
\r
6984 struct { /* FLCTL_MASSERASE_TIMCTL Bits */
\r
6985 __IO uint32_t bBOOST_ACTIVE : 8; /* */
\r
6986 __IO uint32_t bBOOST_HOLD : 8; /* */
\r
6987 __I uint32_t bRESERVED0 : 16; /* Reserved */
\r
6989 } rMASSERASE_TIMCTL;
\r
6990 union { /* FLCTL_BURSTPRG_TIMCTL Register */
\r
6992 struct { /* FLCTL_BURSTPRG_TIMCTL Bits */
\r
6993 __I uint32_t bRESERVED0 : 8; /* Reserved */
\r
6994 __IO uint32_t bACTIVE : 20; /* */
\r
6995 __I uint32_t bRESERVED1 : 4; /* Reserved */
\r
6997 } rBURSTPRG_TIMCTL;
\r
7001 //*****************************************************************************
\r
7003 //*****************************************************************************
\r
7005 union { /* PCMCTL0 Register */
\r
7007 struct { /* PCMCTL0 Bits */
\r
7008 __IO uint32_t bAMR : 4; /* Active Mode Request */
\r
7009 __IO uint32_t bLPMR : 4; /* Low Power Mode Request */
\r
7010 __I uint32_t bCPM : 6; /* Current Power Mode */
\r
7011 __I uint32_t bRESERVED0 : 2; /* Reserved */
\r
7012 __IO uint32_t bKEY : 16; /* PCM key */
\r
7015 union { /* PCMCTL1 Register */
\r
7017 struct { /* PCMCTL1 Bits */
\r
7018 __IO uint32_t bLOCKLPM5 : 1; /* Lock LPM5 */
\r
7019 __IO uint32_t bLOCKBKUP : 1; /* Lock Backup */
\r
7020 __IO uint32_t bFORCE_LPM_ENTRY : 1; /* Force LPM entry */
\r
7021 __I uint32_t bRESERVED0 : 5; /* Reserved */
\r
7022 __IO uint32_t bPMR_BUSY : 1; /* Power mode request busy flag */
\r
7023 __I uint32_t bRESERVED1 : 7; /* Reserved */
\r
7024 __IO uint32_t bKEY : 16; /* PCM key */
\r
7027 union { /* PCMIE Register */
\r
7029 struct { /* PCMIE Bits */
\r
7030 __IO uint32_t bLPM_INVALID_TR_IE : 1; /* LPM invalid transition interrupt enable */
\r
7031 __IO uint32_t bLPM_INVALID_CLK_IE : 1; /* LPM invalid clock interrupt enable */
\r
7032 __IO uint32_t bAM_INVALID_TR_IE : 1; /* Active mode invalid transition interrupt enable */
\r
7033 __I uint32_t bRESERVED0 : 3; /* Reserved */
\r
7034 __IO uint32_t bDCDC_ERROR_IE : 1; /* DC-DC error interrupt enable */
\r
7035 __I uint32_t bRESERVED1 : 25; /* Reserved */
\r
7038 union { /* PCMIFG Register */
\r
7040 struct { /* PCMIFG Bits */
\r
7041 __I uint32_t bLPM_INVALID_TR_IFG : 1; /* LPM invalid transition flag */
\r
7042 __I uint32_t bLPM_INVALID_CLK_IFG : 1; /* LPM invalid clock flag */
\r
7043 __I uint32_t bAM_INVALID_TR_IFG : 1; /* Active mode invalid transition flag */
\r
7044 __I uint32_t bRESERVED0 : 3; /* Reserved */
\r
7045 __I uint32_t bDCDC_ERROR_IFG : 1; /* DC-DC error flag */
\r
7046 __I uint32_t bRESERVED1 : 25; /* Reserved */
\r
7049 union { /* PCMCLRIFG Register */
\r
7051 struct { /* PCMCLRIFG Bits */
\r
7052 __O uint32_t bCLR_LPM_INVALID_TR_IFG : 1; /* Clear LPM invalid transition flag */
\r
7053 __O uint32_t bCLR_LPM_INVALID_CLK_IFG : 1; /* Clear LPM invalid clock flag */
\r
7054 __O uint32_t bCLR_AM_INVALID_TR_IFG : 1; /* Clear active mode invalid transition flag */
\r
7055 __O uint32_t bRESERVED0 : 3; /* Reserved */
\r
7056 __O uint32_t bCLR_DCDC_ERROR_IFG : 1; /* Clear DC-DC error flag */
\r
7057 __O uint32_t bRESERVED1 : 25; /* Reserved */
\r
7063 //*****************************************************************************
\r
7065 //*****************************************************************************
\r
7067 __IO uint16_t rKEYID; /* Port Mapping Key Register */
\r
7068 union { /* PMAPCTL Register */
\r
7070 struct { /* PMAPCTL Bits */
\r
7071 __I uint16_t bLOCKED : 1; /* Port mapping lock bit */
\r
7072 __IO uint16_t bPRECFG : 1; /* Port mapping reconfiguration control bit */
\r
7073 __I uint16_t bRESERVED0 : 14; /* Reserved */
\r
7076 uint8_t RESERVED0[4];
\r
7077 __IO uint16_t rP1MAP01; /* Port mapping register, P1.0 and P1.1 */
\r
7078 __IO uint16_t rP1MAP23; /* Port mapping register, P1.2 and P1.3 */
\r
7079 __IO uint16_t rP1MAP45; /* Port mapping register, P1.4 and P1.5 */
\r
7080 __IO uint16_t rP1MAP67; /* Port mapping register, P1.6 and P1.7 */
\r
7081 __IO uint16_t rP2MAP01; /* Port mapping register, P2.0 and P2.1 */
\r
7082 __IO uint16_t rP2MAP23; /* Port mapping register, P2.2 and P2.3 */
\r
7083 __IO uint16_t rP2MAP45; /* Port mapping register, P2.4 and P2.5 */
\r
7084 __IO uint16_t rP2MAP67; /* Port mapping register, P2.6 and P2.7 */
\r
7085 __IO uint16_t rP3MAP01; /* Port mapping register, P3.0 and P3.1 */
\r
7086 __IO uint16_t rP3MAP23; /* Port mapping register, P3.2 and P3.3 */
\r
7087 __IO uint16_t rP3MAP45; /* Port mapping register, P3.4 and P3.5 */
\r
7088 __IO uint16_t rP3MAP67; /* Port mapping register, P3.6 and P3.7 */
\r
7089 __IO uint16_t rP4MAP01; /* Port mapping register, P4.0 and P4.1 */
\r
7090 __IO uint16_t rP4MAP23; /* Port mapping register, P4.2 and P4.3 */
\r
7091 __IO uint16_t rP4MAP45; /* Port mapping register, P4.4 and P4.5 */
\r
7092 __IO uint16_t rP4MAP67; /* Port mapping register, P4.6 and P4.7 */
\r
7093 __IO uint16_t rP5MAP01; /* Port mapping register, P5.0 and P5.1 */
\r
7094 __IO uint16_t rP5MAP23; /* Port mapping register, P5.2 and P5.3 */
\r
7095 __IO uint16_t rP5MAP45; /* Port mapping register, P5.4 and P5.5 */
\r
7096 __IO uint16_t rP5MAP67; /* Port mapping register, P5.6 and P5.7 */
\r
7097 __IO uint16_t rP6MAP01; /* Port mapping register, P6.0 and P6.1 */
\r
7098 __IO uint16_t rP6MAP23; /* Port mapping register, P6.2 and P6.3 */
\r
7099 __IO uint16_t rP6MAP45; /* Port mapping register, P6.4 and P6.5 */
\r
7100 __IO uint16_t rP6MAP67; /* Port mapping register, P6.6 and P6.7 */
\r
7101 __IO uint16_t rP7MAP01; /* Port mapping register, P7.0 and P7.1 */
\r
7102 __IO uint16_t rP7MAP23; /* Port mapping register, P7.2 and P7.3 */
\r
7103 __IO uint16_t rP7MAP45; /* Port mapping register, P7.4 and P7.5 */
\r
7104 __IO uint16_t rP7MAP67; /* Port mapping register, P7.6 and P7.7 */
\r
7108 //*****************************************************************************
\r
7110 //*****************************************************************************
\r
7112 union { /* PSSKEY Register */
\r
7114 struct { /* PSSKEY Bits */
\r
7115 __IO uint32_t bKEY : 16; /* PSS control key */
\r
7116 __I uint32_t bRESERVED0 : 16; /* Reserved */
\r
7119 union { /* PSSCTL0 Register */
\r
7121 struct { /* PSSCTL0 Bits */
\r
7122 __IO uint32_t bSVSMHOFF : 1; /* SVSM high-side off */
\r
7123 __IO uint32_t bSVSMHLP : 1; /* SVSM high-side low power normal performance mode */
\r
7124 __IO uint32_t bSVSMHS : 1; /* Supply supervisor or monitor selection for the high-side */
\r
7125 __IO uint32_t bSVSMHTH : 3; /* SVSM high-side reset voltage level */
\r
7126 __IO uint32_t bSVMHOE : 1; /* SVSM high-side output enable */
\r
7127 __IO uint32_t bSVMHOUTPOLAL : 1; /* SVMHOUT pin polarity active low */
\r
7128 __IO uint32_t bSVSLOFF : 1; /* SVS low-side off */
\r
7129 __IO uint32_t bSVSLLP : 1; /* SVS low-side low power normal performance mode */
\r
7130 __IO uint32_t bDCDC_FORCE : 1; /* Disables automatic supply voltage detection */
\r
7131 __I uint32_t bRESERVED0 : 1; /* Reserved */
\r
7132 __IO uint32_t bVCORETRAN : 2; /* Controls VCORE Level Transition time */
\r
7133 __I uint32_t bRESERVED1 : 18; /* Reserved */
\r
7136 union { /* PSSCTL1 Register */
\r
7138 struct { /* PSSCTL1 Bits */
\r
7139 __IO uint32_t bDOCMON : 1; /* Turns the DOCM module on or off */
\r
7140 __IO uint32_t bDOCMSAMP : 1; /* DOCM sample current */
\r
7141 __I uint32_t bRESERVED0 : 1; /* Reserved */
\r
7142 __IO uint32_t bDOCMCM : 6; /* Controls current mirrors in DOCM for conversion */
\r
7143 __I uint32_t bRESERVED1 : 23; /* Reserved */
\r
7146 union { /* PSSCTL2 Register */
\r
7148 struct { /* PSSCTL2 Bits */
\r
7149 __I uint32_t bDOCMOUT : 6; /* DOCM comparator output */
\r
7150 __I uint32_t bRESERVED0 : 26; /* Reserved */
\r
7153 uint8_t RESERVED0[36];
\r
7154 union { /* PSSIE Register */
\r
7156 struct { /* PSSIE Bits */
\r
7157 __I uint32_t bRESERVED0 : 1; /* Reserved */
\r
7158 __IO uint32_t bSVSMHIE : 1; /* High-side SVSM interrupt enable */
\r
7159 __I uint32_t bRESERVED1 : 30; /* Reserved */
\r
7162 union { /* PSSIFG Register */
\r
7164 struct { /* PSSIFG Bits */
\r
7165 __I uint32_t bRESERVED0 : 1; /* Reserved */
\r
7166 __I uint32_t bSVSMHIFG : 1; /* High-side SVSM interrupt flag */
\r
7167 __I uint32_t bRESERVED1 : 30; /* Reserved */
\r
7170 union { /* PSSCLRIFG Register */
\r
7172 struct { /* PSSCLRIFG Bits */
\r
7173 __I uint32_t bRESERVED0 : 1; /* Reserved */
\r
7174 __O uint32_t bCLRSVSMHIFG : 1; /* SVSMH clear interrupt flag */
\r
7175 __I uint32_t bRESERVED1 : 30; /* Reserved */
\r
7181 //*****************************************************************************
\r
7182 // REF_A Registers
\r
7183 //*****************************************************************************
\r
7185 union { /* REFCTL0 Register */
\r
7187 struct { /* REFCTL0 Bits */
\r
7188 __IO uint16_t bON : 1; /* Reference enable */
\r
7189 __IO uint16_t bOUT : 1; /* Reference output buffer */
\r
7190 __IO uint16_t bRESERVED0 : 1; /* Reserved */
\r
7191 __IO uint16_t bTCOFF : 1; /* Temperature sensor disabled */
\r
7192 __IO uint16_t bVSEL : 2; /* Reference voltage level select */
\r
7193 __IO uint16_t bGENOT : 1; /* Reference generator one-time trigger */
\r
7194 __IO uint16_t bBGOT : 1; /* Bandgap and bandgap buffer one-time trigger */
\r
7195 __I uint16_t bGENACT : 1; /* Reference generator active */
\r
7196 __I uint16_t bBGACT : 1; /* Reference bandgap active */
\r
7197 __I uint16_t bGENBUSY : 1; /* Reference generator busy */
\r
7198 __I uint16_t bBGMODE : 1; /* Bandgap mode */
\r
7199 __I uint16_t bGENRDY : 1; /* Variable reference voltage ready status */
\r
7200 __I uint16_t bBGRDY : 1; /* Buffered bandgap voltage ready status */
\r
7201 __I uint16_t bRESERVED1 : 2; /* Reserved */
\r
7207 //*****************************************************************************
\r
7208 // RSTCTL Registers
\r
7209 //*****************************************************************************
\r
7211 union { /* RSTCTL_RESET_REQ Register */
\r
7213 struct { /* RSTCTL_RESET_REQ Bits */
\r
7214 __O uint32_t bSOFT_REQ : 1; /* Soft Reset request */
\r
7215 __O uint32_t bHARD_REQ : 1; /* Hard Reset request */
\r
7216 __I uint32_t bRESERVED0 : 6; /* Reserved */
\r
7217 __O uint32_t bRSTKEY : 8; /* Write key to unlock reset request bits */
\r
7218 __I uint32_t bRESERVED1 : 16; /* Reserved */
\r
7221 union { /* RSTCTL_HARDRESET_STAT Register */
\r
7223 struct { /* RSTCTL_HARDRESET_STAT Bits */
\r
7224 __I uint32_t bSRC0 : 1; /* Indicates that SRC0 was the source of the Hard Reset */
\r
7225 __I uint32_t bSRC1 : 1; /* Indicates that SRC1 was the source of the Hard Reset */
\r
7226 __I uint32_t bSRC2 : 1; /* Indicates that SRC2 was the source of the Hard Reset */
\r
7227 __I uint32_t bSRC3 : 1; /* Indicates that SRC3 was the source of the Hard Reset */
\r
7228 __I uint32_t bSRC4 : 1; /* Indicates that SRC4 was the source of the Hard Reset */
\r
7229 __I uint32_t bSRC5 : 1; /* Indicates that SRC5 was the source of the Hard Reset */
\r
7230 __I uint32_t bSRC6 : 1; /* Indicates that SRC6 was the source of the Hard Reset */
\r
7231 __I uint32_t bSRC7 : 1; /* Indicates that SRC7 was the source of the Hard Reset */
\r
7232 __I uint32_t bSRC8 : 1; /* Indicates that SRC8 was the source of the Hard Reset */
\r
7233 __I uint32_t bSRC9 : 1; /* Indicates that SRC9 was the source of the Hard Reset */
\r
7234 __I uint32_t bSRC10 : 1; /* Indicates that SRC10 was the source of the Hard Reset */
\r
7235 __I uint32_t bSRC11 : 1; /* Indicates that SRC11 was the source of the Hard Reset */
\r
7236 __I uint32_t bSRC12 : 1; /* Indicates that SRC12 was the source of the Hard Reset */
\r
7237 __I uint32_t bSRC13 : 1; /* Indicates that SRC13 was the source of the Hard Reset */
\r
7238 __I uint32_t bSRC14 : 1; /* Indicates that SRC14 was the source of the Hard Reset */
\r
7239 __I uint32_t bSRC15 : 1; /* Indicates that SRC15 was the source of the Hard Reset */
\r
7240 __I uint32_t bRESERVED0 : 16; /* Reserved */
\r
7242 } rHARDRESET_STAT;
\r
7243 union { /* RSTCTL_HARDRESET_CLR Register */
\r
7245 struct { /* RSTCTL_HARDRESET_CLR Bits */
\r
7246 __O uint32_t bSRC0 : 1; /* Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */
\r
7247 __O uint32_t bSRC1 : 1; /* Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */
\r
7248 __O uint32_t bSRC2 : 1; /* Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */
\r
7249 __O uint32_t bSRC3 : 1; /* Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */
\r
7250 __O uint32_t bSRC4 : 1; /* Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */
\r
7251 __O uint32_t bSRC5 : 1; /* Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */
\r
7252 __O uint32_t bSRC6 : 1; /* Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */
\r
7253 __O uint32_t bSRC7 : 1; /* Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */
\r
7254 __O uint32_t bSRC8 : 1; /* Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */
\r
7255 __O uint32_t bSRC9 : 1; /* Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */
\r
7256 __O uint32_t bSRC10 : 1; /* Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */
\r
7257 __O uint32_t bSRC11 : 1; /* Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */
\r
7258 __O uint32_t bSRC12 : 1; /* Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */
\r
7259 __O uint32_t bSRC13 : 1; /* Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */
\r
7260 __O uint32_t bSRC14 : 1; /* Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */
\r
7261 __O uint32_t bSRC15 : 1; /* Write 1 clears the corresponding bit in the RSTCTL_HRDRESETSTAT_REG */
\r
7262 __I uint32_t bRESERVED0 : 16; /* Reserved */
\r
7265 union { /* RSTCTL_HARDRESET_SET Register */
\r
7267 struct { /* RSTCTL_HARDRESET_SET Bits */
\r
7268 __O uint32_t bSRC0 : 1; /* Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset) */
\r
7269 __O uint32_t bSRC1 : 1; /* Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset) */
\r
7270 __O uint32_t bSRC2 : 1; /* Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset) */
\r
7271 __O uint32_t bSRC3 : 1; /* Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset) */
\r
7272 __O uint32_t bSRC4 : 1; /* Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset) */
\r
7273 __O uint32_t bSRC5 : 1; /* Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset) */
\r
7274 __O uint32_t bSRC6 : 1; /* Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset) */
\r
7275 __O uint32_t bSRC7 : 1; /* Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset) */
\r
7276 __O uint32_t bSRC8 : 1; /* Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset) */
\r
7277 __O uint32_t bSRC9 : 1; /* Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset) */
\r
7278 __O uint32_t bSRC10 : 1; /* Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset) */
\r
7279 __O uint32_t bSRC11 : 1; /* Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset) */
\r
7280 __O uint32_t bSRC12 : 1; /* Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset) */
\r
7281 __O uint32_t bSRC13 : 1; /* Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset) */
\r
7282 __O uint32_t bSRC14 : 1; /* Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset) */
\r
7283 __O uint32_t bSRC15 : 1; /* Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset) */
\r
7284 __I uint32_t bRESERVED0 : 16; /* Reserved */
\r
7287 union { /* RSTCTL_SOFTRESET_STAT Register */
\r
7289 struct { /* RSTCTL_SOFTRESET_STAT Bits */
\r
7290 __I uint32_t bSRC0 : 1; /* If 1, indicates that SRC0 was the source of the Soft Reset */
\r
7291 __I uint32_t bSRC1 : 1; /* If 1, indicates that SRC1 was the source of the Soft Reset */
\r
7292 __I uint32_t bSRC2 : 1; /* If 1, indicates that SRC2 was the source of the Soft Reset */
\r
7293 __I uint32_t bSRC3 : 1; /* If 1, indicates that SRC3 was the source of the Soft Reset */
\r
7294 __I uint32_t bSRC4 : 1; /* If 1, indicates that SRC4 was the source of the Soft Reset */
\r
7295 __I uint32_t bSRC5 : 1; /* If 1, indicates that SRC5 was the source of the Soft Reset */
\r
7296 __I uint32_t bSRC6 : 1; /* If 1, indicates that SRC6 was the source of the Soft Reset */
\r
7297 __I uint32_t bSRC7 : 1; /* If 1, indicates that SRC7 was the source of the Soft Reset */
\r
7298 __I uint32_t bSRC8 : 1; /* If 1, indicates that SRC8 was the source of the Soft Reset */
\r
7299 __I uint32_t bSRC9 : 1; /* If 1, indicates that SRC9 was the source of the Soft Reset */
\r
7300 __I uint32_t bSRC10 : 1; /* If 1, indicates that SRC10 was the source of the Soft Reset */
\r
7301 __I uint32_t bSRC11 : 1; /* If 1, indicates that SRC11 was the source of the Soft Reset */
\r
7302 __I uint32_t bSRC12 : 1; /* If 1, indicates that SRC12 was the source of the Soft Reset */
\r
7303 __I uint32_t bSRC13 : 1; /* If 1, indicates that SRC13 was the source of the Soft Reset */
\r
7304 __I uint32_t bSRC14 : 1; /* If 1, indicates that SRC14 was the source of the Soft Reset */
\r
7305 __I uint32_t bSRC15 : 1; /* If 1, indicates that SRC15 was the source of the Soft Reset */
\r
7306 __I uint32_t bRESERVED0 : 16; /* Reserved */
\r
7308 } rSOFTRESET_STAT;
\r
7309 union { /* RSTCTL_SOFTRESET_CLR Register */
\r
7311 struct { /* RSTCTL_SOFTRESET_CLR Bits */
\r
7312 __O uint32_t bSRC0 : 1; /* Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */
\r
7313 __O uint32_t bSRC1 : 1; /* Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */
\r
7314 __O uint32_t bSRC2 : 1; /* Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */
\r
7315 __O uint32_t bSRC3 : 1; /* Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */
\r
7316 __O uint32_t bSRC4 : 1; /* Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */
\r
7317 __O uint32_t bSRC5 : 1; /* Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */
\r
7318 __O uint32_t bSRC6 : 1; /* Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */
\r
7319 __O uint32_t bSRC7 : 1; /* Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */
\r
7320 __O uint32_t bSRC8 : 1; /* Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */
\r
7321 __O uint32_t bSRC9 : 1; /* Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */
\r
7322 __O uint32_t bSRC10 : 1; /* Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */
\r
7323 __O uint32_t bSRC11 : 1; /* Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */
\r
7324 __O uint32_t bSRC12 : 1; /* Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */
\r
7325 __O uint32_t bSRC13 : 1; /* Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */
\r
7326 __O uint32_t bSRC14 : 1; /* Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */
\r
7327 __O uint32_t bSRC15 : 1; /* Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */
\r
7328 __I uint32_t bRESERVED0 : 16; /* Reserved */
\r
7331 union { /* RSTCTL_SOFTRESET_SET Register */
\r
7333 struct { /* RSTCTL_SOFTRESET_SET Bits */
\r
7334 __O uint32_t bSRC0 : 1; /* Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset) */
\r
7335 __O uint32_t bSRC1 : 1; /* Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset) */
\r
7336 __O uint32_t bSRC2 : 1; /* Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset) */
\r
7337 __O uint32_t bSRC3 : 1; /* Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset) */
\r
7338 __O uint32_t bSRC4 : 1; /* Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset) */
\r
7339 __O uint32_t bSRC5 : 1; /* Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset) */
\r
7340 __O uint32_t bSRC6 : 1; /* Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset) */
\r
7341 __O uint32_t bSRC7 : 1; /* Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset) */
\r
7342 __O uint32_t bSRC8 : 1; /* Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset) */
\r
7343 __O uint32_t bSRC9 : 1; /* Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset) */
\r
7344 __O uint32_t bSRC10 : 1; /* Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset) */
\r
7345 __O uint32_t bSRC11 : 1; /* Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset) */
\r
7346 __O uint32_t bSRC12 : 1; /* Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset) */
\r
7347 __O uint32_t bSRC13 : 1; /* Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset) */
\r
7348 __O uint32_t bSRC14 : 1; /* Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset) */
\r
7349 __O uint32_t bSRC15 : 1; /* Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset) */
\r
7350 __I uint32_t bRESERVED0 : 16; /* Reserved */
\r
7353 uint8_t RESERVED0[228];
\r
7354 union { /* RSTCTL_PSSRESET_STAT Register */
\r
7356 struct { /* RSTCTL_PSSRESET_STAT Bits */
\r
7357 __I uint32_t bSVSL : 1; /* Indicates if POR was caused by an SVSL trip condition in the PSS */
\r
7358 __I uint32_t bSVSMH : 1; /* Indicates if POR was caused by an SVSMH trip condition int the PSS */
\r
7359 __I uint32_t bBGREF : 1; /* Indicates if POR was caused by a BGREF not okay condition in the PSS */
\r
7360 __I uint32_t bVCCDET : 1; /* Indicates if POR was caused by a VCCDET trip condition in the PSS */
\r
7361 __I uint32_t bRESERVED0 : 28; /* Reserved */
\r
7364 union { /* RSTCTL_PSSRESET_CLR Register */
\r
7366 struct { /* RSTCTL_PSSRESET_CLR Bits */
\r
7367 __O uint32_t bCLR : 1; /* Write 1 clears all PSS Reset Flags in the RSTCTL_PSSRESET_STAT */
\r
7368 __I uint32_t bRESERVED0 : 31; /* Reserved */
\r
7371 union { /* RSTCTL_PCMRESET_STAT Register */
\r
7373 struct { /* RSTCTL_PCMRESET_STAT Bits */
\r
7374 __I uint32_t bLPM35 : 1; /* Indicates if POR was caused by PCM due to an exit from LPM3.5 */
\r
7375 __I uint32_t bLPM45 : 1; /* Indicates if POR was caused by PCM due to an exit from LPM4.5 */
\r
7376 __I uint32_t bRESERVED0 : 30; /* Reserved */
\r
7379 union { /* RSTCTL_PCMRESET_CLR Register */
\r
7381 struct { /* RSTCTL_PCMRESET_CLR Bits */
\r
7382 __O uint32_t bCLR : 1; /* Write 1 clears all PCM Reset Flags in the RSTCTL_PCMRESET_STAT */
\r
7383 __I uint32_t bRESERVED0 : 31; /* Reserved */
\r
7386 union { /* RSTCTL_PINRESET_STAT Register */
\r
7388 struct { /* RSTCTL_PINRESET_STAT Bits */
\r
7389 __I uint32_t bRSTNMI : 1; /* POR was caused by RSTn/NMI pin based reset event */
\r
7390 __I uint32_t bRESERVED0 : 31; /* Reserved */
\r
7393 union { /* RSTCTL_PINRESET_CLR Register */
\r
7395 struct { /* RSTCTL_PINRESET_CLR Bits */
\r
7396 __O uint32_t bCLR : 1; /* Write 1 clears the RSTn/NMI Pin Reset Flag in RSTCTL_PINRESET_STAT */
\r
7397 __I uint32_t bRESERVED0 : 31; /* Reserved */
\r
7400 union { /* RSTCTL_REBOOTRESET_STAT Register */
\r
7402 struct { /* RSTCTL_REBOOTRESET_STAT Bits */
\r
7403 __I uint32_t bREBOOT : 1; /* Indicates if Reboot reset was caused by the SYSCTL module. */
\r
7404 __I uint32_t bRESERVED0 : 31; /* Reserved */
\r
7406 } rREBOOTRESET_STAT;
\r
7407 union { /* RSTCTL_REBOOTRESET_CLR Register */
\r
7409 struct { /* RSTCTL_REBOOTRESET_CLR Bits */
\r
7410 __O uint32_t bCLR : 1; /* Write 1 clears the Reboot Reset Flag in RSTCTL_REBOOTRESET_STAT */
\r
7411 __I uint32_t bRESERVED0 : 31; /* Reserved */
\r
7413 } rREBOOTRESET_CLR;
\r
7417 //*****************************************************************************
\r
7418 // RTC_C Registers
\r
7419 //*****************************************************************************
\r
7421 union { /* RTCCTL0 Register */
\r
7423 struct { /* RTCCTL0 Bits */
\r
7424 __IO uint16_t bRDYIFG : 1; /* Real-time clock ready interrupt flag */
\r
7425 __IO uint16_t bAIFG : 1; /* Real-time clock alarm interrupt flag */
\r
7426 __IO uint16_t bTEVIFG : 1; /* Real-time clock time event interrupt flag */
\r
7427 __IO uint16_t bOFIFG : 1; /* 32-kHz crystal oscillator fault interrupt flag */
\r
7428 __IO uint16_t bRDYIE : 1; /* Real-time clock ready interrupt enable */
\r
7429 __IO uint16_t bAIE : 1; /* Real-time clock alarm interrupt enable */
\r
7430 __IO uint16_t bTEVIE : 1; /* Real-time clock time event interrupt enable */
\r
7431 __IO uint16_t bOFIE : 1; /* 32-kHz crystal oscillator fault interrupt enable */
\r
7432 __IO uint16_t bKEY : 8; /* Real-time clock key */
\r
7435 union { /* RTCCTL13 Register */
\r
7437 struct { /* RTCCTL13 Bits */
\r
7438 __IO uint16_t bTEV : 2; /* Real-time clock time event */
\r
7439 __IO uint16_t bSSEL : 2; /* Real-time clock source select */
\r
7440 __I uint16_t bRDY : 1; /* Real-time clock ready */
\r
7441 __I uint16_t bMODE : 1; /* */
\r
7442 __IO uint16_t bHOLD : 1; /* Real-time clock hold */
\r
7443 __IO uint16_t bBCD : 1; /* Real-time clock BCD select */
\r
7444 __IO uint16_t bCALF : 2; /* Real-time clock calibration frequency */
\r
7445 __I uint16_t bRESERVED0 : 6; /* Reserved */
\r
7448 union { /* RTCOCAL Register */
\r
7450 struct { /* RTCOCAL Bits */
\r
7451 __IO uint16_t bOCAL : 8; /* Real-time clock offset error calibration */
\r
7452 __I uint16_t bRESERVED0 : 7; /* Reserved */
\r
7453 __IO uint16_t bOCALS : 1; /* Real-time clock offset error calibration sign */
\r
7456 union { /* RTCTCMP Register */
\r
7458 struct { /* RTCTCMP Bits */
\r
7459 __IO uint16_t bTCMP : 8; /* Real-time clock temperature compensation */
\r
7460 __I uint16_t bRESERVED0 : 5; /* Reserved */
\r
7461 __I uint16_t bTCOK : 1; /* Real-time clock temperature compensation write OK */
\r
7462 __I uint16_t bTCRDY : 1; /* Real-time clock temperature compensation ready */
\r
7463 __IO uint16_t bTCMPS : 1; /* Real-time clock temperature compensation sign */
\r
7466 union { /* RTCPS0CTL Register */
\r
7468 struct { /* RTCPS0CTL Bits */
\r
7469 __IO uint16_t bRT0PSIFG : 1; /* Prescale timer 0 interrupt flag */
\r
7470 __IO uint16_t bRT0PSIE : 1; /* Prescale timer 0 interrupt enable */
\r
7471 __IO uint16_t bRT0IP : 3; /* Prescale timer 0 interrupt interval */
\r
7472 __I uint16_t bRESERVED0 : 11; /* Reserved */
\r
7475 union { /* RTCPS1CTL Register */
\r
7477 struct { /* RTCPS1CTL Bits */
\r
7478 __IO uint16_t bRT1PSIFG : 1; /* Prescale timer 1 interrupt flag */
\r
7479 __IO uint16_t bRT1PSIE : 1; /* Prescale timer 1 interrupt enable */
\r
7480 __IO uint16_t bRT1IP : 3; /* Prescale timer 1 interrupt interval */
\r
7481 __I uint16_t bRESERVED0 : 11; /* Reserved */
\r
7484 union { /* RTCPS Register */
\r
7486 struct { /* RTCPS Bits */
\r
7487 __IO uint16_t bRT0PS : 8; /* Prescale timer 0 counter value */
\r
7488 __IO uint16_t bRT1PS : 8; /* Prescale timer 1 counter value */
\r
7491 __I uint16_t rIV; /* Real-Time Clock Interrupt Vector Register */
\r
7492 union { /* RTCTIM0 Register */
\r
7494 struct { /* RTCTIM0 Bits */
\r
7495 __IO uint16_t bSEC : 6; /* Seconds (0 to 59) */
\r
7496 __I uint16_t bRESERVED0 : 2; /* Reserved */
\r
7497 __IO uint16_t bMIN : 6; /* Minutes (0 to 59) */
\r
7498 __I uint16_t bRESERVED1 : 2; /* Reserved */
\r
7500 struct { /* RTCTIM0_BCD Bits */
\r
7501 __IO uint16_t bSEC_LD : 4; /* Seconds ? low digit (0 to 9) */
\r
7502 __IO uint16_t bSEC_HD : 3; /* Seconds ? high digit (0 to 5) */
\r
7503 __I uint16_t bRESERVED : 1; /* Reserved */
\r
7504 __IO uint16_t bMIN_LD : 4; /* Minutes ? low digit (0 to 9) */
\r
7505 __IO uint16_t bMIN_HD : 3; /* Minutes ? high digit (0 to 5) */
\r
7508 union { /* RTCTIM1 Register */
\r
7510 struct { /* RTCTIM1 Bits */
\r
7511 __IO uint16_t bHOUR : 5; /* Hours (0 to 23) */
\r
7512 __I uint16_t bRESERVED0 : 3; /* Reserved */
\r
7513 __IO uint16_t bDOW : 3; /* Day of week (0 to 6) */
\r
7514 __I uint16_t bRESERVED1 : 5; /* Reserved */
\r
7516 struct { /* RTCTIM1_BCD Bits */
\r
7517 __IO uint16_t bHOUR_LD : 4; /* Hours ? low digit (0 to 9) */
\r
7518 __IO uint16_t bHOUR_HD : 2; /* Hours ? high digit (0 to 2) */
\r
7519 __I uint16_t bRESERVED : 2; /* Reserved */
\r
7520 __IO uint16_t bDOW : 3; /* Day of week (0 to 6) */
\r
7523 union { /* RTCDATE Register */
\r
7525 struct { /* RTCDATE Bits */
\r
7526 __IO uint16_t bDAY : 5; /* Day of month (1 to 28, 29, 30, 31) */
\r
7527 __I uint16_t bRESERVED0 : 3; /* Reserved */
\r
7528 __IO uint16_t bMON : 4; /* Month (1 to 12) */
\r
7529 __I uint16_t bRESERVED1 : 4; /* Reserved */
\r
7531 struct { /* RTCDATE_BCD Bits */
\r
7532 __IO uint16_t bDAY_LD : 4; /* Day of month ? low digit (0 to 9) */
\r
7533 __IO uint16_t bDAY_HD : 2; /* Day of month ? high digit (0 to 3) */
\r
7534 __I uint16_t bRESERVED : 2; /* Reserved */
\r
7535 __IO uint16_t bMON_LD : 4; /* Month ? low digit (0 to 9) */
\r
7536 __IO uint16_t bMON_HD : 1; /* Month ? high digit (0 or 1) */
\r
7539 union { /* RTCYEAR Register */
\r
7541 struct { /* RTCYEAR Bits */
\r
7542 __IO uint16_t bYEAR_LB : 8; /* Year ? low byte. Valid values for Year are 0 to 4095. */
\r
7543 __IO uint16_t bYEAR_HB : 4; /* Year ? high byte. Valid values for Year are 0 to 4095. */
\r
7544 __I uint16_t bRESERVED0 : 4; /* Reserved */
\r
7546 struct { /* RTCYEAR_BCD Bits */
\r
7547 __IO uint16_t bYEAR : 4; /* Year ? lowest digit (0 to 9) */
\r
7548 __IO uint16_t bDEC : 4; /* Decade (0 to 9) */
\r
7549 __IO uint16_t bCENT_LD : 4; /* Century ? low digit (0 to 9) */
\r
7550 __IO uint16_t bCENT_HD : 3; /* Century ? high digit (0 to 4) */
\r
7551 __I uint16_t bRESERVED : 1; /* Reserved */
\r
7554 union { /* RTCAMINHR Register */
\r
7556 struct { /* RTCAMINHR Bits */
\r
7557 __IO uint16_t bMIN : 6; /* Minutes (0 to 59) */
\r
7558 __I uint16_t bRESERVED0 : 1; /* Reserved */
\r
7559 __IO uint16_t bMINAE : 1; /* Alarm enable */
\r
7560 __IO uint16_t bHOUR : 5; /* Hours (0 to 23) */
\r
7561 __I uint16_t bRESERVED1 : 2; /* Reserved */
\r
7562 __IO uint16_t bHOURAE : 1; /* Alarm enable */
\r
7564 struct { /* RTCAMINHR_BCD Bits */
\r
7565 __IO uint16_t bMIN_LD : 4; /* Minutes ? low digit (0 to 9) */
\r
7566 __IO uint16_t bMIN_HD : 3; /* Minutes ? high digit (0 to 5) */
\r
7567 __IO uint16_t b : 1; /* Alarm enable */
\r
7568 __IO uint16_t bHOUR_LD : 4; /* Hours ? low digit (0 to 9) */
\r
7569 __IO uint16_t bHOUR_HD : 2; /* Hours ? high digit (0 to 2) */
\r
7570 __I uint16_t bRESERVED : 1; /* Reserved */
\r
7571 __IO uint16_t bHOURAE : 1; /* Alarm enable */
\r
7574 union { /* RTCADOWDAY Register */
\r
7576 struct { /* RTCADOWDAY Bits */
\r
7577 __IO uint16_t bDOW : 3; /* Day of week (0 to 6) */
\r
7578 __I uint16_t bRESERVED0 : 4; /* Reserved */
\r
7579 __IO uint16_t bDOWAE : 1; /* Alarm enable */
\r
7580 __IO uint16_t bDAY : 5; /* Day of month (1 to 28, 29, 30, 31) */
\r
7581 __I uint16_t bRESERVED1 : 2; /* Reserved */
\r
7582 __IO uint16_t bDAYAE : 1; /* Alarm enable */
\r
7584 struct { /* RTCADOWDAY_BCD Bits */
\r
7585 __IO uint16_t bDOW : 3; /* Day of week (0 to 6) */
\r
7586 __I uint16_t bRESERVED : 4; /* Reserved */
\r
7587 __IO uint16_t bDOWAE : 1; /* Alarm enable */
\r
7588 __IO uint16_t bDAY_LD : 4; /* Day of month ? low digit (0 to 9) */
\r
7589 __IO uint16_t bDAY_HD : 2; /* Day of month ? high digit (0 to 3) */
\r
7590 __IO uint16_t bDAYAE : 1; /* Alarm enable */
\r
7593 __IO uint16_t rBIN2BCD; /* Binary-to-BCD Conversion Register */
\r
7594 __IO uint16_t rBCD2BIN; /* BCD-to-Binary Conversion Register */
\r
7598 //*****************************************************************************
\r
7599 // SYSCTL Registers
\r
7600 //*****************************************************************************
\r
7602 union { /* SYS_REBOOT_CTL Register */
\r
7604 struct { /* SYS_REBOOT_CTL Bits */
\r
7605 __IO uint32_t bREBOOT : 1; /* Write 1 initiates a Reboot of the device */
\r
7606 __I uint32_t bRESERVED0 : 7; /* Reserved */
\r
7607 __O uint32_t bWKEY : 8; /* Key to enable writes to bit 0 */
\r
7608 __I uint32_t bRESERVED1 : 16; /* Reserved */
\r
7611 union { /* SYS_NMI_CTLSTAT Register */
\r
7613 struct { /* SYS_NMI_CTLSTAT Bits */
\r
7614 __IO uint32_t bCS_SRC : 1; /* CS interrupt as a source of NMI */
\r
7615 __IO uint32_t bPSS_SRC : 1; /* PSS interrupt as a source of NMI */
\r
7616 __IO uint32_t bPCM_SRC : 1; /* PCM interrupt as a source of NMI */
\r
7617 __IO uint32_t bPIN_SRC : 1; /* */
\r
7618 __I uint32_t bRESERVED0 : 12; /* Reserved */
\r
7619 __I uint32_t bCS_FLG : 1; /* CS interrupt was the source of NMI */
\r
7620 __I uint32_t bPSS_FLG : 1; /* PSS interrupt was the source of NMI */
\r
7621 __I uint32_t bPCM_FLG : 1; /* PCM interrupt was the source of NMI */
\r
7622 __IO uint32_t bPIN_FLG : 1; /* RSTn/NMI pin was the source of NMI */
\r
7623 __I uint32_t bRESERVED1 : 12; /* Reserved */
\r
7626 union { /* SYS_WDTRESET_CTL Register */
\r
7628 struct { /* SYS_WDTRESET_CTL Bits */
\r
7629 __IO uint32_t bTIMEOUT : 1; /* WDT timeout reset type */
\r
7630 __IO uint32_t bVIOLATION : 1; /* WDT password violation reset type */
\r
7631 __I uint32_t bRESERVED0 : 30; /* Reserved */
\r
7634 union { /* SYS_PERIHALT_CTL Register */
\r
7636 struct { /* SYS_PERIHALT_CTL Bits */
\r
7637 __IO uint32_t bT16_0 : 1; /* Freezes IP operation when CPU is halted */
\r
7638 __IO uint32_t bT16_1 : 1; /* Freezes IP operation when CPU is halted */
\r
7639 __IO uint32_t bT16_2 : 1; /* Freezes IP operation when CPU is halted */
\r
7640 __IO uint32_t bT16_3 : 1; /* Freezes IP operation when CPU is halted */
\r
7641 __IO uint32_t bT32_0 : 1; /* Freezes IP operation when CPU is halted */
\r
7642 __IO uint32_t bEUA0 : 1; /* Freezes IP operation when CPU is halted */
\r
7643 __IO uint32_t bEUA1 : 1; /* Freezes IP operation when CPU is halted */
\r
7644 __IO uint32_t bEUA2 : 1; /* Freezes IP operation when CPU is halted */
\r
7645 __IO uint32_t bEUA3 : 1; /* Freezes IP operation when CPU is halted */
\r
7646 __IO uint32_t bEUB0 : 1; /* Freezes IP operation when CPU is halted */
\r
7647 __IO uint32_t bEUB1 : 1; /* Freezes IP operation when CPU is halted */
\r
7648 __IO uint32_t bEUB2 : 1; /* Freezes IP operation when CPU is halted */
\r
7649 __IO uint32_t bEUB3 : 1; /* Freezes IP operation when CPU is halted */
\r
7650 __IO uint32_t bADC : 1; /* Freezes IP operation when CPU is halted */
\r
7651 __IO uint32_t bWDT : 1; /* Freezes IP operation when CPU is halted */
\r
7652 __IO uint32_t bDMA : 1; /* Freezes IP operation when CPU is halted */
\r
7653 __I uint32_t bRESERVED0 : 16; /* Reserved */
\r
7656 __I uint32_t rSRAM_SIZE; /* SRAM Size Register */
\r
7657 union { /* SYS_SRAM_BANKEN Register */
\r
7659 struct { /* SYS_SRAM_BANKEN Bits */
\r
7660 __I uint32_t bBNK0_EN : 1; /* SRAM Bank0 enable */
\r
7661 __IO uint32_t bBNK1_EN : 1; /* SRAM Bank1 enable */
\r
7662 __IO uint32_t bBNK2_EN : 1; /* SRAM Bank1 enable */
\r
7663 __IO uint32_t bBNK3_EN : 1; /* SRAM Bank1 enable */
\r
7664 __IO uint32_t bBNK4_EN : 1; /* SRAM Bank1 enable */
\r
7665 __IO uint32_t bBNK5_EN : 1; /* SRAM Bank1 enable */
\r
7666 __IO uint32_t bBNK6_EN : 1; /* SRAM Bank1 enable */
\r
7667 __IO uint32_t bBNK7_EN : 1; /* SRAM Bank1 enable */
\r
7668 __I uint32_t bRESERVED0 : 8; /* Reserved */
\r
7669 __I uint32_t bSRAM_RDY : 1; /* SRAM ready */
\r
7670 __I uint32_t bRESERVED1 : 15; /* Reserved */
\r
7673 union { /* SYS_SRAM_BANKRET Register */
\r
7675 struct { /* SYS_SRAM_BANKRET Bits */
\r
7676 __I uint32_t bBNK0_RET : 1; /* Bank0 retention */
\r
7677 __IO uint32_t bBNK1_RET : 1; /* Bank1 retention */
\r
7678 __IO uint32_t bBNK2_RET : 1; /* Bank2 retention */
\r
7679 __IO uint32_t bBNK3_RET : 1; /* Bank3 retention */
\r
7680 __IO uint32_t bBNK4_RET : 1; /* Bank4 retention */
\r
7681 __IO uint32_t bBNK5_RET : 1; /* Bank5 retention */
\r
7682 __IO uint32_t bBNK6_RET : 1; /* Bank6 retention */
\r
7683 __IO uint32_t bBNK7_RET : 1; /* Bank7 retention */
\r
7684 __I uint32_t bRESERVED0 : 8; /* Reserved */
\r
7685 __I uint32_t bSRAM_RDY : 1; /* SRAM ready */
\r
7686 __I uint32_t bRESERVED1 : 15; /* Reserved */
\r
7689 uint8_t RESERVED0[4];
\r
7690 __I uint32_t rFLASH_SIZE; /* Flash Size Register */
\r
7691 uint8_t RESERVED1[12];
\r
7692 union { /* SYS_DIO_GLTFLT_CTL Register */
\r
7694 struct { /* SYS_DIO_GLTFLT_CTL Bits */
\r
7695 __IO uint32_t bGLTCH_EN : 1; /* Glitch filter enable */
\r
7696 __I uint32_t bRESERVED0 : 31; /* Reserved */
\r
7698 } rDIO_GLTFLT_CTL;
\r
7699 uint8_t RESERVED2[12];
\r
7700 union { /* SYS_SECDATA_UNLOCK Register */
\r
7702 struct { /* SYS_SECDATA_UNLOCK Bits */
\r
7703 __IO uint32_t bUNLKEY : 16; /* Unlock key */
\r
7704 __I uint32_t bRESERVED0 : 16; /* Reserved */
\r
7706 } rSECDATA_UNLOCK;
\r
7707 uint8_t RESERVED3[4028];
\r
7708 union { /* SYS_MASTER_UNLOCK Register */
\r
7710 struct { /* SYS_MASTER_UNLOCK Bits */
\r
7711 __IO uint32_t bUNLKEY : 16; /* Unlock Key */
\r
7712 __I uint32_t bRESERVED0 : 16; /* Reserved */
\r
7715 __IO uint32_t rBOOTOVER_REQ0; /* Boot Override Request Register */
\r
7716 __IO uint32_t rBOOTOVER_REQ1; /* Boot Override Request Register */
\r
7717 __IO uint32_t rBOOTOVER_ACK; /* Boot Override Acknowledge Register */
\r
7718 union { /* SYS_RESET_REQ Register */
\r
7720 struct { /* SYS_RESET_REQ Bits */
\r
7721 __O uint32_t bPOR : 1; /* Generate POR */
\r
7722 __O uint32_t bREBOOT : 1; /* Generate Reboot_Reset */
\r
7723 __I uint32_t bRESERVED0 : 6; /* Reserved */
\r
7724 __O uint32_t bWKEY : 8; /* Write key */
\r
7725 __I uint32_t bRESERVED1 : 16; /* Reserved */
\r
7728 union { /* SYS_RESET_STATOVER Register */
\r
7730 struct { /* SYS_RESET_STATOVER Bits */
\r
7731 __I uint32_t bSOFT : 1; /* Indicates if SOFT Reset is active */
\r
7732 __I uint32_t bHARD : 1; /* Indicates if HARD Reset is active */
\r
7733 __I uint32_t bREBOOT : 1; /* Indicates if Reboot Reset is active */
\r
7734 __I uint32_t bRESERVED0 : 5; /* Reserved */
\r
7735 __IO uint32_t bSOFT_OVER : 1; /* SOFT_Reset overwrite request */
\r
7736 __IO uint32_t bHARD_OVER : 1; /* HARD_Reset overwrite request */
\r
7737 __IO uint32_t bRBT_OVER : 1; /* Reboot Reset overwrite request */
\r
7738 __I uint32_t bRESERVED1 : 21; /* Reserved */
\r
7740 } rRESET_STATOVER;
\r
7741 uint8_t RESERVED4[8];
\r
7742 union { /* SYS_SYSTEM_STAT Register */
\r
7744 struct { /* SYS_SYSTEM_STAT Bits */
\r
7745 __I uint32_t bRESERVED0 : 3; /* Reserved */
\r
7746 __I uint32_t bDBG_SEC_ACT : 1; /* Debug Security active */
\r
7747 __I uint32_t bJTAG_SWD_LOCK_ACT : 1; /* Indicates if JTAG and SWD Lock is active */
\r
7748 __I uint32_t bIP_PROT_ACT : 1; /* Indicates if IP protection is active */
\r
7749 __I uint32_t bRESERVED1 : 26; /* Reserved */
\r
7755 //*****************************************************************************
\r
7756 // TIMER32 Registers
\r
7757 //*****************************************************************************
\r
7759 __IO uint32_t rLOAD1; /* Timer 1 Load Register */
\r
7760 __I uint32_t rVALUE1; /* Timer 1 Current Value Register */
\r
7761 union { /* T32CONTROL1 Register */
\r
7763 struct { /* T32CONTROL1 Bits */
\r
7764 __IO uint32_t bONESHOT : 1; /* Selects one-shot or wrapping counter mode */
\r
7765 __IO uint32_t bSIZE : 1; /* Selects 16 or 32 bit counter operation */
\r
7766 __IO uint32_t bPRESCALE : 2; /* Prescale bits */
\r
7767 __I uint32_t bRESERVED0 : 1; /* Reserved */
\r
7768 __IO uint32_t bIE : 1; /* Interrupt enable bit */
\r
7769 __IO uint32_t bMODE : 1; /* Mode bit */
\r
7770 __IO uint32_t bENABLE : 1; /* */
\r
7771 __I uint32_t bRESERVED1 : 24; /* Reserved */
\r
7774 __O uint32_t rINTCLR1; /* Timer 1 Interrupt Clear Register */
\r
7775 union { /* T32RIS1 Register */
\r
7777 struct { /* T32RIS1 Bits */
\r
7778 __I uint32_t bRAW_IFG : 1; /* Raw interrupt status */
\r
7779 __I uint32_t b : 31; /* */
\r
7782 union { /* T32MIS1 Register */
\r
7784 struct { /* T32MIS1 Bits */
\r
7785 __I uint32_t b : 1; /* Enabled interrupt status */
\r
7786 __I uint32_t bRESERVED0 : 31; /* Reserved */
\r
7789 __IO uint32_t rBGLOAD1; /* Timer 1 Background Load Register */
\r
7790 uint8_t RESERVED0[4];
\r
7791 __IO uint32_t rLOAD2; /* Timer 2 Load Register */
\r
7792 __I uint32_t rVALUE2; /* Timer 2 Current Value Register */
\r
7793 union { /* T32CONTROL2 Register */
\r
7795 struct { /* T32CONTROL2 Bits */
\r
7796 __IO uint32_t bONESHOT : 1; /* Selects one-shot or wrapping counter mode */
\r
7797 __IO uint32_t bSIZE : 1; /* Selects 16 or 32 bit counter operation */
\r
7798 __IO uint32_t bPRESCALE : 2; /* Prescale bits */
\r
7799 __I uint32_t bRESERVED0 : 1; /* Reserved */
\r
7800 __IO uint32_t bIE : 1; /* Interrupt enable bit */
\r
7801 __IO uint32_t bMODE : 1; /* Mode bit */
\r
7802 __IO uint32_t bENABLE : 1; /* */
\r
7803 __I uint32_t bRESERVED1 : 24; /* Reserved */
\r
7806 __O uint32_t rINTCLR2; /* Timer 2 Interrupt Clear Register */
\r
7807 union { /* T32RIS2 Register */
\r
7809 struct { /* T32RIS2 Bits */
\r
7810 __I uint32_t bRAW_IFG : 1; /* Raw interrupt status */
\r
7811 __I uint32_t bRESERVED0 : 31; /* Reserved */
\r
7814 union { /* T32MIS2 Register */
\r
7816 struct { /* T32MIS2 Bits */
\r
7817 __I uint32_t bIFG : 1; /* Enabled interrupt status */
\r
7818 __I uint32_t bRESERVED0 : 31; /* Reserved */
\r
7821 __IO uint32_t rBGLOAD2; /* Timer 2 Background Load Register */
\r
7822 uint8_t RESERVED1[3780];
\r
7823 union { /* T32ITCR Register */
\r
7825 struct { /* T32ITCR Bits */
\r
7826 __IO uint32_t bTEST_EN : 1; /* Test mode */
\r
7827 __I uint32_t b : 31; /* */
\r
7830 union { /* T32ITOP Register */
\r
7832 struct { /* T32ITOP Bits */
\r
7833 __O uint32_t bTIMINT1_VAL : 1; /* Value output on TIMINT1 */
\r
7834 __O uint32_t bTIMINT2_VAL : 1; /* Value output on TIMINT2 */
\r
7835 __I uint32_t bRESERVED0 : 30; /* Reserved */
\r
7841 //*****************************************************************************
\r
7842 // TIMER_A0 Registers
\r
7843 //*****************************************************************************
\r
7845 union { /* TA0CTL Register */
\r
7847 struct { /* TA0CTL Bits */
\r
7848 __IO uint16_t bIFG : 1; /* TimerA interrupt flag */
\r
7849 __IO uint16_t bIE : 1; /* TimerA interrupt enable */
\r
7850 __IO uint16_t bCLR : 1; /* TimerA clear */
\r
7851 __IO uint16_t bRESERVED0 : 1; /* Reserved */
\r
7852 __IO uint16_t bMC : 2; /* Mode control */
\r
7853 __IO uint16_t bID : 2; /* Input divider */
\r
7854 __IO uint16_t bSSEL : 2; /* TimerA clock source select */
\r
7855 __IO uint16_t bRESERVED1 : 6; /* Reserved */
\r
7858 union { /* TA0CCTL0 Register */
\r
7860 struct { /* TA0CCTL0 Bits */
\r
7861 __IO uint16_t bCCIFG : 1; /* Capture/compare interrupt flag */
\r
7862 __IO uint16_t bCOV : 1; /* Capture overflow */
\r
7863 __IO uint16_t bOUT : 1; /* Output */
\r
7864 __I uint16_t bCCI : 1; /* Capture/compare input */
\r
7865 __IO uint16_t bCCIE : 1; /* Capture/compare interrupt enable */
\r
7866 __IO uint16_t bOUTMOD : 3; /* Output mode */
\r
7867 __IO uint16_t bCAP : 1; /* Capture mode */
\r
7868 __I uint16_t bRESERVED0 : 1; /* Reserved */
\r
7869 __IO uint16_t bSCCI : 1; /* Synchronized capture/compare input */
\r
7870 __IO uint16_t bSCS : 1; /* Synchronize capture source */
\r
7871 __IO uint16_t bCCIS : 2; /* Capture/compare input select */
\r
7872 __IO uint16_t bCM : 2; /* Capture mode */
\r
7875 union { /* TA0CCTL1 Register */
\r
7877 struct { /* TA0CCTL1 Bits */
\r
7878 __IO uint16_t bCCIFG : 1; /* Capture/compare interrupt flag */
\r
7879 __IO uint16_t bCOV : 1; /* Capture overflow */
\r
7880 __IO uint16_t bOUT : 1; /* Output */
\r
7881 __I uint16_t bCCI : 1; /* Capture/compare input */
\r
7882 __IO uint16_t bCCIE : 1; /* Capture/compare interrupt enable */
\r
7883 __IO uint16_t bOUTMOD : 3; /* Output mode */
\r
7884 __IO uint16_t bCAP : 1; /* Capture mode */
\r
7885 __I uint16_t bRESERVED0 : 1; /* Reserved */
\r
7886 __IO uint16_t bSCCI : 1; /* Synchronized capture/compare input */
\r
7887 __IO uint16_t bSCS : 1; /* Synchronize capture source */
\r
7888 __IO uint16_t bCCIS : 2; /* Capture/compare input select */
\r
7889 __IO uint16_t bCM : 2; /* Capture mode */
\r
7892 union { /* TA0CCTL2 Register */
\r
7894 struct { /* TA0CCTL2 Bits */
\r
7895 __IO uint16_t bCCIFG : 1; /* Capture/compare interrupt flag */
\r
7896 __IO uint16_t bCOV : 1; /* Capture overflow */
\r
7897 __IO uint16_t bOUT : 1; /* Output */
\r
7898 __I uint16_t bCCI : 1; /* Capture/compare input */
\r
7899 __IO uint16_t bCCIE : 1; /* Capture/compare interrupt enable */
\r
7900 __IO uint16_t bOUTMOD : 3; /* Output mode */
\r
7901 __IO uint16_t bCAP : 1; /* Capture mode */
\r
7902 __I uint16_t bRESERVED0 : 1; /* Reserved */
\r
7903 __IO uint16_t bSCCI : 1; /* Synchronized capture/compare input */
\r
7904 __IO uint16_t bSCS : 1; /* Synchronize capture source */
\r
7905 __IO uint16_t bCCIS : 2; /* Capture/compare input select */
\r
7906 __IO uint16_t bCM : 2; /* Capture mode */
\r
7909 union { /* TA0CCTL3 Register */
\r
7911 struct { /* TA0CCTL3 Bits */
\r
7912 __IO uint16_t bCCIFG : 1; /* Capture/compare interrupt flag */
\r
7913 __IO uint16_t bCOV : 1; /* Capture overflow */
\r
7914 __IO uint16_t bOUT : 1; /* Output */
\r
7915 __I uint16_t bCCI : 1; /* Capture/compare input */
\r
7916 __IO uint16_t bCCIE : 1; /* Capture/compare interrupt enable */
\r
7917 __IO uint16_t bOUTMOD : 3; /* Output mode */
\r
7918 __IO uint16_t bCAP : 1; /* Capture mode */
\r
7919 __I uint16_t bRESERVED0 : 1; /* Reserved */
\r
7920 __IO uint16_t bSCCI : 1; /* Synchronized capture/compare input */
\r
7921 __IO uint16_t bSCS : 1; /* Synchronize capture source */
\r
7922 __IO uint16_t bCCIS : 2; /* Capture/compare input select */
\r
7923 __IO uint16_t bCM : 2; /* Capture mode */
\r
7926 union { /* TA0CCTL4 Register */
\r
7928 struct { /* TA0CCTL4 Bits */
\r
7929 __IO uint16_t bCCIFG : 1; /* Capture/compare interrupt flag */
\r
7930 __IO uint16_t bCOV : 1; /* Capture overflow */
\r
7931 __IO uint16_t bOUT : 1; /* Output */
\r
7932 __I uint16_t bCCI : 1; /* Capture/compare input */
\r
7933 __IO uint16_t bCCIE : 1; /* Capture/compare interrupt enable */
\r
7934 __IO uint16_t bOUTMOD : 3; /* Output mode */
\r
7935 __IO uint16_t bCAP : 1; /* Capture mode */
\r
7936 __I uint16_t bRESERVED0 : 1; /* Reserved */
\r
7937 __IO uint16_t bSCCI : 1; /* Synchronized capture/compare input */
\r
7938 __IO uint16_t bSCS : 1; /* Synchronize capture source */
\r
7939 __IO uint16_t bCCIS : 2; /* Capture/compare input select */
\r
7940 __IO uint16_t bCM : 2; /* Capture mode */
\r
7943 union { /* TA0CCTL5 Register */
\r
7945 struct { /* TA0CCTL5 Bits */
\r
7946 __IO uint16_t bCCIFG : 1; /* Capture/compare interrupt flag */
\r
7947 __IO uint16_t bCOV : 1; /* Capture overflow */
\r
7948 __IO uint16_t bOUT : 1; /* Output */
\r
7949 __I uint16_t bCCI : 1; /* Capture/compare input */
\r
7950 __IO uint16_t bCCIE : 1; /* Capture/compare interrupt enable */
\r
7951 __IO uint16_t bOUTMOD : 3; /* Output mode */
\r
7952 __IO uint16_t bCAP : 1; /* Capture mode */
\r
7953 __I uint16_t bRESERVED0 : 1; /* Reserved */
\r
7954 __IO uint16_t bSCCI : 1; /* Synchronized capture/compare input */
\r
7955 __IO uint16_t bSCS : 1; /* Synchronize capture source */
\r
7956 __IO uint16_t bCCIS : 2; /* Capture/compare input select */
\r
7957 __IO uint16_t bCM : 2; /* Capture mode */
\r
7960 union { /* TA0CCTL6 Register */
\r
7962 struct { /* TA0CCTL6 Bits */
\r
7963 __IO uint16_t bCCIFG : 1; /* Capture/compare interrupt flag */
\r
7964 __IO uint16_t bCOV : 1; /* Capture overflow */
\r
7965 __IO uint16_t bOUT : 1; /* Output */
\r
7966 __I uint16_t bCCI : 1; /* Capture/compare input */
\r
7967 __IO uint16_t bCCIE : 1; /* Capture/compare interrupt enable */
\r
7968 __IO uint16_t bOUTMOD : 3; /* Output mode */
\r
7969 __IO uint16_t bCAP : 1; /* Capture mode */
\r
7970 __I uint16_t bRESERVED0 : 1; /* Reserved */
\r
7971 __IO uint16_t bSCCI : 1; /* Synchronized capture/compare input */
\r
7972 __IO uint16_t bSCS : 1; /* Synchronize capture source */
\r
7973 __IO uint16_t bCCIS : 2; /* Capture/compare input select */
\r
7974 __IO uint16_t bCM : 2; /* Capture mode */
\r
7977 __IO uint16_t rR; /* TimerA register */
\r
7978 __IO uint16_t rCCR0; /* Timer_A Capture/Compare Register */
\r
7979 __IO uint16_t rCCR1; /* Timer_A Capture/Compare Register */
\r
7980 __IO uint16_t rCCR2; /* Timer_A Capture/Compare Register */
\r
7981 __IO uint16_t rCCR3; /* Timer_A Capture/Compare Register */
\r
7982 __IO uint16_t rCCR4; /* Timer_A Capture/Compare Register */
\r
7983 __IO uint16_t rCCR5; /* Timer_A Capture/Compare Register */
\r
7984 __IO uint16_t rCCR6; /* Timer_A Capture/Compare Register */
\r
7985 union { /* TA0EX0 Register */
\r
7987 struct { /* TA0EX0 Bits */
\r
7988 __IO uint16_t bIDEX : 3; /* Input divider expansion */
\r
7989 __I uint16_t bRESERVED0 : 13; /* Reserved */
\r
7992 uint8_t RESERVED0[12];
\r
7993 __I uint16_t rIV; /* TimerAx Interrupt Vector Register */
\r
7997 //*****************************************************************************
\r
7998 // TIMER_A1 Registers
\r
7999 //*****************************************************************************
\r
8001 union { /* TA1CTL Register */
\r
8003 struct { /* TA1CTL Bits */
\r
8004 __IO uint16_t bIFG : 1; /* TimerA interrupt flag */
\r
8005 __IO uint16_t bIE : 1; /* TimerA interrupt enable */
\r
8006 __IO uint16_t bCLR : 1; /* TimerA clear */
\r
8007 __IO uint16_t bRESERVED0 : 1; /* Reserved */
\r
8008 __IO uint16_t bMC : 2; /* Mode control */
\r
8009 __IO uint16_t bID : 2; /* Input divider */
\r
8010 __IO uint16_t bSSEL : 2; /* TimerA clock source select */
\r
8011 __IO uint16_t bRESERVED1 : 6; /* Reserved */
\r
8014 union { /* TA1CCTL0 Register */
\r
8016 struct { /* TA1CCTL0 Bits */
\r
8017 __IO uint16_t bCCIFG : 1; /* Capture/compare interrupt flag */
\r
8018 __IO uint16_t bCOV : 1; /* Capture overflow */
\r
8019 __IO uint16_t bOUT : 1; /* Output */
\r
8020 __I uint16_t bCCI : 1; /* Capture/compare input */
\r
8021 __IO uint16_t bCCIE : 1; /* Capture/compare interrupt enable */
\r
8022 __IO uint16_t bOUTMOD : 3; /* Output mode */
\r
8023 __IO uint16_t bCAP : 1; /* Capture mode */
\r
8024 __I uint16_t bRESERVED0 : 1; /* Reserved */
\r
8025 __IO uint16_t bSCCI : 1; /* Synchronized capture/compare input */
\r
8026 __IO uint16_t bSCS : 1; /* Synchronize capture source */
\r
8027 __IO uint16_t bCCIS : 2; /* Capture/compare input select */
\r
8028 __IO uint16_t bCM : 2; /* Capture mode */
\r
8031 union { /* TA1CCTL1 Register */
\r
8033 struct { /* TA1CCTL1 Bits */
\r
8034 __IO uint16_t bCCIFG : 1; /* Capture/compare interrupt flag */
\r
8035 __IO uint16_t bCOV : 1; /* Capture overflow */
\r
8036 __IO uint16_t bOUT : 1; /* Output */
\r
8037 __I uint16_t bCCI : 1; /* Capture/compare input */
\r
8038 __IO uint16_t bCCIE : 1; /* Capture/compare interrupt enable */
\r
8039 __IO uint16_t bOUTMOD : 3; /* Output mode */
\r
8040 __IO uint16_t bCAP : 1; /* Capture mode */
\r
8041 __I uint16_t bRESERVED0 : 1; /* Reserved */
\r
8042 __IO uint16_t bSCCI : 1; /* Synchronized capture/compare input */
\r
8043 __IO uint16_t bSCS : 1; /* Synchronize capture source */
\r
8044 __IO uint16_t bCCIS : 2; /* Capture/compare input select */
\r
8045 __IO uint16_t bCM : 2; /* Capture mode */
\r
8048 union { /* TA1CCTL2 Register */
\r
8050 struct { /* TA1CCTL2 Bits */
\r
8051 __IO uint16_t bCCIFG : 1; /* Capture/compare interrupt flag */
\r
8052 __IO uint16_t bCOV : 1; /* Capture overflow */
\r
8053 __IO uint16_t bOUT : 1; /* Output */
\r
8054 __I uint16_t bCCI : 1; /* Capture/compare input */
\r
8055 __IO uint16_t bCCIE : 1; /* Capture/compare interrupt enable */
\r
8056 __IO uint16_t bOUTMOD : 3; /* Output mode */
\r
8057 __IO uint16_t bCAP : 1; /* Capture mode */
\r
8058 __I uint16_t bRESERVED0 : 1; /* Reserved */
\r
8059 __IO uint16_t bSCCI : 1; /* Synchronized capture/compare input */
\r
8060 __IO uint16_t bSCS : 1; /* Synchronize capture source */
\r
8061 __IO uint16_t bCCIS : 2; /* Capture/compare input select */
\r
8062 __IO uint16_t bCM : 2; /* Capture mode */
\r
8065 union { /* TA1CCTL3 Register */
\r
8067 struct { /* TA1CCTL3 Bits */
\r
8068 __IO uint16_t bCCIFG : 1; /* Capture/compare interrupt flag */
\r
8069 __IO uint16_t bCOV : 1; /* Capture overflow */
\r
8070 __IO uint16_t bOUT : 1; /* Output */
\r
8071 __I uint16_t bCCI : 1; /* Capture/compare input */
\r
8072 __IO uint16_t bCCIE : 1; /* Capture/compare interrupt enable */
\r
8073 __IO uint16_t bOUTMOD : 3; /* Output mode */
\r
8074 __IO uint16_t bCAP : 1; /* Capture mode */
\r
8075 __I uint16_t bRESERVED0 : 1; /* Reserved */
\r
8076 __IO uint16_t bSCCI : 1; /* Synchronized capture/compare input */
\r
8077 __IO uint16_t bSCS : 1; /* Synchronize capture source */
\r
8078 __IO uint16_t bCCIS : 2; /* Capture/compare input select */
\r
8079 __IO uint16_t bCM : 2; /* Capture mode */
\r
8082 union { /* TA1CCTL4 Register */
\r
8084 struct { /* TA1CCTL4 Bits */
\r
8085 __IO uint16_t bCCIFG : 1; /* Capture/compare interrupt flag */
\r
8086 __IO uint16_t bCOV : 1; /* Capture overflow */
\r
8087 __IO uint16_t bOUT : 1; /* Output */
\r
8088 __I uint16_t bCCI : 1; /* Capture/compare input */
\r
8089 __IO uint16_t bCCIE : 1; /* Capture/compare interrupt enable */
\r
8090 __IO uint16_t bOUTMOD : 3; /* Output mode */
\r
8091 __IO uint16_t bCAP : 1; /* Capture mode */
\r
8092 __I uint16_t bRESERVED0 : 1; /* Reserved */
\r
8093 __IO uint16_t bSCCI : 1; /* Synchronized capture/compare input */
\r
8094 __IO uint16_t bSCS : 1; /* Synchronize capture source */
\r
8095 __IO uint16_t bCCIS : 2; /* Capture/compare input select */
\r
8096 __IO uint16_t bCM : 2; /* Capture mode */
\r
8099 union { /* TA1CCTL5 Register */
\r
8101 struct { /* TA1CCTL5 Bits */
\r
8102 __IO uint16_t bCCIFG : 1; /* Capture/compare interrupt flag */
\r
8103 __IO uint16_t bCOV : 1; /* Capture overflow */
\r
8104 __IO uint16_t bOUT : 1; /* Output */
\r
8105 __I uint16_t bCCI : 1; /* Capture/compare input */
\r
8106 __IO uint16_t bCCIE : 1; /* Capture/compare interrupt enable */
\r
8107 __IO uint16_t bOUTMOD : 3; /* Output mode */
\r
8108 __IO uint16_t bCAP : 1; /* Capture mode */
\r
8109 __I uint16_t bRESERVED0 : 1; /* Reserved */
\r
8110 __IO uint16_t bSCCI : 1; /* Synchronized capture/compare input */
\r
8111 __IO uint16_t bSCS : 1; /* Synchronize capture source */
\r
8112 __IO uint16_t bCCIS : 2; /* Capture/compare input select */
\r
8113 __IO uint16_t bCM : 2; /* Capture mode */
\r
8116 union { /* TA1CCTL6 Register */
\r
8118 struct { /* TA1CCTL6 Bits */
\r
8119 __IO uint16_t bCCIFG : 1; /* Capture/compare interrupt flag */
\r
8120 __IO uint16_t bCOV : 1; /* Capture overflow */
\r
8121 __IO uint16_t bOUT : 1; /* Output */
\r
8122 __I uint16_t bCCI : 1; /* Capture/compare input */
\r
8123 __IO uint16_t bCCIE : 1; /* Capture/compare interrupt enable */
\r
8124 __IO uint16_t bOUTMOD : 3; /* Output mode */
\r
8125 __IO uint16_t bCAP : 1; /* Capture mode */
\r
8126 __I uint16_t bRESERVED0 : 1; /* Reserved */
\r
8127 __IO uint16_t bSCCI : 1; /* Synchronized capture/compare input */
\r
8128 __IO uint16_t bSCS : 1; /* Synchronize capture source */
\r
8129 __IO uint16_t bCCIS : 2; /* Capture/compare input select */
\r
8130 __IO uint16_t bCM : 2; /* Capture mode */
\r
8133 __IO uint16_t rR; /* TimerA register */
\r
8134 __IO uint16_t rCCR0; /* Timer_A Capture/Compare Register */
\r
8135 __IO uint16_t rCCR1; /* Timer_A Capture/Compare Register */
\r
8136 __IO uint16_t rCCR2; /* Timer_A Capture/Compare Register */
\r
8137 __IO uint16_t rCCR3; /* Timer_A Capture/Compare Register */
\r
8138 __IO uint16_t rCCR4; /* Timer_A Capture/Compare Register */
\r
8139 __IO uint16_t rCCR5; /* Timer_A Capture/Compare Register */
\r
8140 __IO uint16_t rCCR6; /* Timer_A Capture/Compare Register */
\r
8141 union { /* TA1EX0 Register */
\r
8143 struct { /* TA1EX0 Bits */
\r
8144 __IO uint16_t bIDEX : 3; /* Input divider expansion */
\r
8145 __I uint16_t bRESERVED0 : 13; /* Reserved */
\r
8148 uint8_t RESERVED0[12];
\r
8149 __I uint16_t rIV; /* TimerAx Interrupt Vector Register */
\r
8153 //*****************************************************************************
\r
8154 // TIMER_A2 Registers
\r
8155 //*****************************************************************************
\r
8157 union { /* TA2CTL Register */
\r
8159 struct { /* TA2CTL Bits */
\r
8160 __IO uint16_t bIFG : 1; /* TimerA interrupt flag */
\r
8161 __IO uint16_t bIE : 1; /* TimerA interrupt enable */
\r
8162 __IO uint16_t bCLR : 1; /* TimerA clear */
\r
8163 __IO uint16_t bRESERVED0 : 1; /* Reserved */
\r
8164 __IO uint16_t bMC : 2; /* Mode control */
\r
8165 __IO uint16_t bID : 2; /* Input divider */
\r
8166 __IO uint16_t bSSEL : 2; /* TimerA clock source select */
\r
8167 __IO uint16_t bRESERVED1 : 6; /* Reserved */
\r
8170 union { /* TA2CCTL0 Register */
\r
8172 struct { /* TA2CCTL0 Bits */
\r
8173 __IO uint16_t bCCIFG : 1; /* Capture/compare interrupt flag */
\r
8174 __IO uint16_t bCOV : 1; /* Capture overflow */
\r
8175 __IO uint16_t bOUT : 1; /* Output */
\r
8176 __I uint16_t bCCI : 1; /* Capture/compare input */
\r
8177 __IO uint16_t bCCIE : 1; /* Capture/compare interrupt enable */
\r
8178 __IO uint16_t bOUTMOD : 3; /* Output mode */
\r
8179 __IO uint16_t bCAP : 1; /* Capture mode */
\r
8180 __I uint16_t bRESERVED0 : 1; /* Reserved */
\r
8181 __IO uint16_t bSCCI : 1; /* Synchronized capture/compare input */
\r
8182 __IO uint16_t bSCS : 1; /* Synchronize capture source */
\r
8183 __IO uint16_t bCCIS : 2; /* Capture/compare input select */
\r
8184 __IO uint16_t bCM : 2; /* Capture mode */
\r
8187 union { /* TA2CCTL1 Register */
\r
8189 struct { /* TA2CCTL1 Bits */
\r
8190 __IO uint16_t bCCIFG : 1; /* Capture/compare interrupt flag */
\r
8191 __IO uint16_t bCOV : 1; /* Capture overflow */
\r
8192 __IO uint16_t bOUT : 1; /* Output */
\r
8193 __I uint16_t bCCI : 1; /* Capture/compare input */
\r
8194 __IO uint16_t bCCIE : 1; /* Capture/compare interrupt enable */
\r
8195 __IO uint16_t bOUTMOD : 3; /* Output mode */
\r
8196 __IO uint16_t bCAP : 1; /* Capture mode */
\r
8197 __I uint16_t bRESERVED0 : 1; /* Reserved */
\r
8198 __IO uint16_t bSCCI : 1; /* Synchronized capture/compare input */
\r
8199 __IO uint16_t bSCS : 1; /* Synchronize capture source */
\r
8200 __IO uint16_t bCCIS : 2; /* Capture/compare input select */
\r
8201 __IO uint16_t bCM : 2; /* Capture mode */
\r
8204 union { /* TA2CCTL2 Register */
\r
8206 struct { /* TA2CCTL2 Bits */
\r
8207 __IO uint16_t bCCIFG : 1; /* Capture/compare interrupt flag */
\r
8208 __IO uint16_t bCOV : 1; /* Capture overflow */
\r
8209 __IO uint16_t bOUT : 1; /* Output */
\r
8210 __I uint16_t bCCI : 1; /* Capture/compare input */
\r
8211 __IO uint16_t bCCIE : 1; /* Capture/compare interrupt enable */
\r
8212 __IO uint16_t bOUTMOD : 3; /* Output mode */
\r
8213 __IO uint16_t bCAP : 1; /* Capture mode */
\r
8214 __I uint16_t bRESERVED0 : 1; /* Reserved */
\r
8215 __IO uint16_t bSCCI : 1; /* Synchronized capture/compare input */
\r
8216 __IO uint16_t bSCS : 1; /* Synchronize capture source */
\r
8217 __IO uint16_t bCCIS : 2; /* Capture/compare input select */
\r
8218 __IO uint16_t bCM : 2; /* Capture mode */
\r
8221 union { /* TA2CCTL3 Register */
\r
8223 struct { /* TA2CCTL3 Bits */
\r
8224 __IO uint16_t bCCIFG : 1; /* Capture/compare interrupt flag */
\r
8225 __IO uint16_t bCOV : 1; /* Capture overflow */
\r
8226 __IO uint16_t bOUT : 1; /* Output */
\r
8227 __I uint16_t bCCI : 1; /* Capture/compare input */
\r
8228 __IO uint16_t bCCIE : 1; /* Capture/compare interrupt enable */
\r
8229 __IO uint16_t bOUTMOD : 3; /* Output mode */
\r
8230 __IO uint16_t bCAP : 1; /* Capture mode */
\r
8231 __I uint16_t bRESERVED0 : 1; /* Reserved */
\r
8232 __IO uint16_t bSCCI : 1; /* Synchronized capture/compare input */
\r
8233 __IO uint16_t bSCS : 1; /* Synchronize capture source */
\r
8234 __IO uint16_t bCCIS : 2; /* Capture/compare input select */
\r
8235 __IO uint16_t bCM : 2; /* Capture mode */
\r
8238 union { /* TA2CCTL4 Register */
\r
8240 struct { /* TA2CCTL4 Bits */
\r
8241 __IO uint16_t bCCIFG : 1; /* Capture/compare interrupt flag */
\r
8242 __IO uint16_t bCOV : 1; /* Capture overflow */
\r
8243 __IO uint16_t bOUT : 1; /* Output */
\r
8244 __I uint16_t bCCI : 1; /* Capture/compare input */
\r
8245 __IO uint16_t bCCIE : 1; /* Capture/compare interrupt enable */
\r
8246 __IO uint16_t bOUTMOD : 3; /* Output mode */
\r
8247 __IO uint16_t bCAP : 1; /* Capture mode */
\r
8248 __I uint16_t bRESERVED0 : 1; /* Reserved */
\r
8249 __IO uint16_t bSCCI : 1; /* Synchronized capture/compare input */
\r
8250 __IO uint16_t bSCS : 1; /* Synchronize capture source */
\r
8251 __IO uint16_t bCCIS : 2; /* Capture/compare input select */
\r
8252 __IO uint16_t bCM : 2; /* Capture mode */
\r
8255 union { /* TA2CCTL5 Register */
\r
8257 struct { /* TA2CCTL5 Bits */
\r
8258 __IO uint16_t bCCIFG : 1; /* Capture/compare interrupt flag */
\r
8259 __IO uint16_t bCOV : 1; /* Capture overflow */
\r
8260 __IO uint16_t bOUT : 1; /* Output */
\r
8261 __I uint16_t bCCI : 1; /* Capture/compare input */
\r
8262 __IO uint16_t bCCIE : 1; /* Capture/compare interrupt enable */
\r
8263 __IO uint16_t bOUTMOD : 3; /* Output mode */
\r
8264 __IO uint16_t bCAP : 1; /* Capture mode */
\r
8265 __I uint16_t bRESERVED0 : 1; /* Reserved */
\r
8266 __IO uint16_t bSCCI : 1; /* Synchronized capture/compare input */
\r
8267 __IO uint16_t bSCS : 1; /* Synchronize capture source */
\r
8268 __IO uint16_t bCCIS : 2; /* Capture/compare input select */
\r
8269 __IO uint16_t bCM : 2; /* Capture mode */
\r
8272 union { /* TA2CCTL6 Register */
\r
8274 struct { /* TA2CCTL6 Bits */
\r
8275 __IO uint16_t bCCIFG : 1; /* Capture/compare interrupt flag */
\r
8276 __IO uint16_t bCOV : 1; /* Capture overflow */
\r
8277 __IO uint16_t bOUT : 1; /* Output */
\r
8278 __I uint16_t bCCI : 1; /* Capture/compare input */
\r
8279 __IO uint16_t bCCIE : 1; /* Capture/compare interrupt enable */
\r
8280 __IO uint16_t bOUTMOD : 3; /* Output mode */
\r
8281 __IO uint16_t bCAP : 1; /* Capture mode */
\r
8282 __I uint16_t bRESERVED0 : 1; /* Reserved */
\r
8283 __IO uint16_t bSCCI : 1; /* Synchronized capture/compare input */
\r
8284 __IO uint16_t bSCS : 1; /* Synchronize capture source */
\r
8285 __IO uint16_t bCCIS : 2; /* Capture/compare input select */
\r
8286 __IO uint16_t bCM : 2; /* Capture mode */
\r
8289 __IO uint16_t rR; /* TimerA register */
\r
8290 __IO uint16_t rCCR0; /* Timer_A Capture/Compare Register */
\r
8291 __IO uint16_t rCCR1; /* Timer_A Capture/Compare Register */
\r
8292 __IO uint16_t rCCR2; /* Timer_A Capture/Compare Register */
\r
8293 __IO uint16_t rCCR3; /* Timer_A Capture/Compare Register */
\r
8294 __IO uint16_t rCCR4; /* Timer_A Capture/Compare Register */
\r
8295 __IO uint16_t rCCR5; /* Timer_A Capture/Compare Register */
\r
8296 __IO uint16_t rCCR6; /* Timer_A Capture/Compare Register */
\r
8297 union { /* TA2EX0 Register */
\r
8299 struct { /* TA2EX0 Bits */
\r
8300 __IO uint16_t bIDEX : 3; /* Input divider expansion */
\r
8301 __I uint16_t bRESERVED0 : 13; /* Reserved */
\r
8304 uint8_t RESERVED0[12];
\r
8305 __I uint16_t rIV; /* TimerAx Interrupt Vector Register */
\r
8309 //*****************************************************************************
\r
8310 // TIMER_A3 Registers
\r
8311 //*****************************************************************************
\r
8313 union { /* TA3CTL Register */
\r
8315 struct { /* TA3CTL Bits */
\r
8316 __IO uint16_t bIFG : 1; /* TimerA interrupt flag */
\r
8317 __IO uint16_t bIE : 1; /* TimerA interrupt enable */
\r
8318 __IO uint16_t bCLR : 1; /* TimerA clear */
\r
8319 __IO uint16_t bRESERVED0 : 1; /* Reserved */
\r
8320 __IO uint16_t bMC : 2; /* Mode control */
\r
8321 __IO uint16_t bID : 2; /* Input divider */
\r
8322 __IO uint16_t bSSEL : 2; /* TimerA clock source select */
\r
8323 __IO uint16_t bRESERVED1 : 6; /* Reserved */
\r
8326 union { /* TA3CCTL0 Register */
\r
8328 struct { /* TA3CCTL0 Bits */
\r
8329 __IO uint16_t bCCIFG : 1; /* Capture/compare interrupt flag */
\r
8330 __IO uint16_t bCOV : 1; /* Capture overflow */
\r
8331 __IO uint16_t bOUT : 1; /* Output */
\r
8332 __I uint16_t bCCI : 1; /* Capture/compare input */
\r
8333 __IO uint16_t bCCIE : 1; /* Capture/compare interrupt enable */
\r
8334 __IO uint16_t bOUTMOD : 3; /* Output mode */
\r
8335 __IO uint16_t bCAP : 1; /* Capture mode */
\r
8336 __I uint16_t bRESERVED0 : 1; /* Reserved */
\r
8337 __IO uint16_t bSCCI : 1; /* Synchronized capture/compare input */
\r
8338 __IO uint16_t bSCS : 1; /* Synchronize capture source */
\r
8339 __IO uint16_t bCCIS : 2; /* Capture/compare input select */
\r
8340 __IO uint16_t bCM : 2; /* Capture mode */
\r
8343 union { /* TA3CCTL1 Register */
\r
8345 struct { /* TA3CCTL1 Bits */
\r
8346 __IO uint16_t bCCIFG : 1; /* Capture/compare interrupt flag */
\r
8347 __IO uint16_t bCOV : 1; /* Capture overflow */
\r
8348 __IO uint16_t bOUT : 1; /* Output */
\r
8349 __I uint16_t bCCI : 1; /* Capture/compare input */
\r
8350 __IO uint16_t bCCIE : 1; /* Capture/compare interrupt enable */
\r
8351 __IO uint16_t bOUTMOD : 3; /* Output mode */
\r
8352 __IO uint16_t bCAP : 1; /* Capture mode */
\r
8353 __I uint16_t bRESERVED0 : 1; /* Reserved */
\r
8354 __IO uint16_t bSCCI : 1; /* Synchronized capture/compare input */
\r
8355 __IO uint16_t bSCS : 1; /* Synchronize capture source */
\r
8356 __IO uint16_t bCCIS : 2; /* Capture/compare input select */
\r
8357 __IO uint16_t bCM : 2; /* Capture mode */
\r
8360 union { /* TA3CCTL2 Register */
\r
8362 struct { /* TA3CCTL2 Bits */
\r
8363 __IO uint16_t bCCIFG : 1; /* Capture/compare interrupt flag */
\r
8364 __IO uint16_t bCOV : 1; /* Capture overflow */
\r
8365 __IO uint16_t bOUT : 1; /* Output */
\r
8366 __I uint16_t bCCI : 1; /* Capture/compare input */
\r
8367 __IO uint16_t bCCIE : 1; /* Capture/compare interrupt enable */
\r
8368 __IO uint16_t bOUTMOD : 3; /* Output mode */
\r
8369 __IO uint16_t bCAP : 1; /* Capture mode */
\r
8370 __I uint16_t bRESERVED0 : 1; /* Reserved */
\r
8371 __IO uint16_t bSCCI : 1; /* Synchronized capture/compare input */
\r
8372 __IO uint16_t bSCS : 1; /* Synchronize capture source */
\r
8373 __IO uint16_t bCCIS : 2; /* Capture/compare input select */
\r
8374 __IO uint16_t bCM : 2; /* Capture mode */
\r
8377 union { /* TA3CCTL3 Register */
\r
8379 struct { /* TA3CCTL3 Bits */
\r
8380 __IO uint16_t bCCIFG : 1; /* Capture/compare interrupt flag */
\r
8381 __IO uint16_t bCOV : 1; /* Capture overflow */
\r
8382 __IO uint16_t bOUT : 1; /* Output */
\r
8383 __I uint16_t bCCI : 1; /* Capture/compare input */
\r
8384 __IO uint16_t bCCIE : 1; /* Capture/compare interrupt enable */
\r
8385 __IO uint16_t bOUTMOD : 3; /* Output mode */
\r
8386 __IO uint16_t bCAP : 1; /* Capture mode */
\r
8387 __I uint16_t bRESERVED0 : 1; /* Reserved */
\r
8388 __IO uint16_t bSCCI : 1; /* Synchronized capture/compare input */
\r
8389 __IO uint16_t bSCS : 1; /* Synchronize capture source */
\r
8390 __IO uint16_t bCCIS : 2; /* Capture/compare input select */
\r
8391 __IO uint16_t bCM : 2; /* Capture mode */
\r
8394 union { /* TA3CCTL4 Register */
\r
8396 struct { /* TA3CCTL4 Bits */
\r
8397 __IO uint16_t bCCIFG : 1; /* Capture/compare interrupt flag */
\r
8398 __IO uint16_t bCOV : 1; /* Capture overflow */
\r
8399 __IO uint16_t bOUT : 1; /* Output */
\r
8400 __I uint16_t bCCI : 1; /* Capture/compare input */
\r
8401 __IO uint16_t bCCIE : 1; /* Capture/compare interrupt enable */
\r
8402 __IO uint16_t bOUTMOD : 3; /* Output mode */
\r
8403 __IO uint16_t bCAP : 1; /* Capture mode */
\r
8404 __I uint16_t bRESERVED0 : 1; /* Reserved */
\r
8405 __IO uint16_t bSCCI : 1; /* Synchronized capture/compare input */
\r
8406 __IO uint16_t bSCS : 1; /* Synchronize capture source */
\r
8407 __IO uint16_t bCCIS : 2; /* Capture/compare input select */
\r
8408 __IO uint16_t bCM : 2; /* Capture mode */
\r
8411 union { /* TA3CCTL5 Register */
\r
8413 struct { /* TA3CCTL5 Bits */
\r
8414 __IO uint16_t bCCIFG : 1; /* Capture/compare interrupt flag */
\r
8415 __IO uint16_t bCOV : 1; /* Capture overflow */
\r
8416 __IO uint16_t bOUT : 1; /* Output */
\r
8417 __I uint16_t bCCI : 1; /* Capture/compare input */
\r
8418 __IO uint16_t bCCIE : 1; /* Capture/compare interrupt enable */
\r
8419 __IO uint16_t bOUTMOD : 3; /* Output mode */
\r
8420 __IO uint16_t bCAP : 1; /* Capture mode */
\r
8421 __I uint16_t bRESERVED0 : 1; /* Reserved */
\r
8422 __IO uint16_t bSCCI : 1; /* Synchronized capture/compare input */
\r
8423 __IO uint16_t bSCS : 1; /* Synchronize capture source */
\r
8424 __IO uint16_t bCCIS : 2; /* Capture/compare input select */
\r
8425 __IO uint16_t bCM : 2; /* Capture mode */
\r
8428 union { /* TA3CCTL6 Register */
\r
8430 struct { /* TA3CCTL6 Bits */
\r
8431 __IO uint16_t bCCIFG : 1; /* Capture/compare interrupt flag */
\r
8432 __IO uint16_t bCOV : 1; /* Capture overflow */
\r
8433 __IO uint16_t bOUT : 1; /* Output */
\r
8434 __I uint16_t bCCI : 1; /* Capture/compare input */
\r
8435 __IO uint16_t bCCIE : 1; /* Capture/compare interrupt enable */
\r
8436 __IO uint16_t bOUTMOD : 3; /* Output mode */
\r
8437 __IO uint16_t bCAP : 1; /* Capture mode */
\r
8438 __I uint16_t bRESERVED0 : 1; /* Reserved */
\r
8439 __IO uint16_t bSCCI : 1; /* Synchronized capture/compare input */
\r
8440 __IO uint16_t bSCS : 1; /* Synchronize capture source */
\r
8441 __IO uint16_t bCCIS : 2; /* Capture/compare input select */
\r
8442 __IO uint16_t bCM : 2; /* Capture mode */
\r
8445 __IO uint16_t rR; /* TimerA register */
\r
8446 __IO uint16_t rCCR0; /* Timer_A Capture/Compare Register */
\r
8447 __IO uint16_t rCCR1; /* Timer_A Capture/Compare Register */
\r
8448 __IO uint16_t rCCR2; /* Timer_A Capture/Compare Register */
\r
8449 __IO uint16_t rCCR3; /* Timer_A Capture/Compare Register */
\r
8450 __IO uint16_t rCCR4; /* Timer_A Capture/Compare Register */
\r
8451 __IO uint16_t rCCR5; /* Timer_A Capture/Compare Register */
\r
8452 __IO uint16_t rCCR6; /* Timer_A Capture/Compare Register */
\r
8453 union { /* TA3EX0 Register */
\r
8455 struct { /* TA3EX0 Bits */
\r
8456 __IO uint16_t bIDEX : 3; /* Input divider expansion */
\r
8457 __I uint16_t bRESERVED0 : 13; /* Reserved */
\r
8460 uint8_t RESERVED0[12];
\r
8461 __I uint16_t rIV; /* TimerAx Interrupt Vector Register */
\r
8465 //*****************************************************************************
\r
8467 //*****************************************************************************
\r
8469 __IO uint32_t rTLV_CHECKSUM; /* TLV Checksum */
\r
8470 __IO uint32_t rDEVICE_INFO_TAG; /* Device Info Tag */
\r
8471 __IO uint32_t rDEVICE_INFO_LEN; /* Device Info Length */
\r
8472 __IO uint32_t rDEVICE_ID; /* Device ID */
\r
8473 __IO uint32_t rHWREV; /* HW Revision */
\r
8474 __IO uint32_t rBCREV; /* Boot Code Revision */
\r
8475 __IO uint32_t rROM_DRVLIB_REV; /* ROM Driver Library Revision */
\r
8476 __IO uint32_t rDIE_REC_TAG; /* Die Record Tag */
\r
8477 __IO uint32_t rDIE_REC_LEN; /* Die Record Length */
\r
8478 __IO uint32_t rDIE_XPOS; /* Die X-Position */
\r
8479 __IO uint32_t rDIE_YPOS; /* Die Y-Position */
\r
8480 __IO uint32_t rWAFER_ID; /* Wafer ID */
\r
8481 __IO uint32_t rLOT_ID; /* Lot ID */
\r
8482 __IO uint32_t rRESERVED0; /* Reserved */
\r
8483 __IO uint32_t rRESERVED1; /* Reserved */
\r
8484 __IO uint32_t rRESERVED2; /* Reserved */
\r
8485 __IO uint32_t rTEST_RESULTS; /* Test Results */
\r
8486 __IO uint32_t rCS_CAL_TAG; /* Clock System Calibration Tag */
\r
8487 __IO uint32_t rCS_CAL_LEN; /* Clock System Calibration Length */
\r
8488 __IO uint32_t rDCOIR_FCAL_RSEL04; /* DCO IR mode: Frequency calibration for DCORSEL 0 to 4 */
\r
8489 __IO uint32_t rDCOIR_FCAL_RSEL5; /* DCO IR mode: Frequency calibration for DCORSEL 5 */
\r
8490 __IO uint32_t rDCOIR_MAXPOSTUNE_RSEL04; /* DCO IR mode: Max Positive Tune for DCORSEL 0 to 4 */
\r
8491 __IO uint32_t rDCOIR_MAXNEGTUNE_RSEL04; /* DCO IR mode: Max Negative Tune for DCORSEL 0 to 4 */
\r
8492 __IO uint32_t rDCOIR_MAXPOSTUNE_RSEL5; /* DCO IR mode: Max Positive Tune for DCORSEL 5 */
\r
8493 __IO uint32_t rDCOIR_MAXNEGTUNE_RSEL5; /* DCO IR mode: Max Negative Tune for DCORSEL 5 */
\r
8494 __IO uint32_t rDCOIR_CONSTK_RSEL04; /* DCO IR mode: DCO Constant (K) for DCORSEL 0 to 4 */
\r
8495 __IO uint32_t rDCOIR_CONSTK_RSEL5; /* DCO IR mode: DCO Constant (K) for DCORSEL 5 */
\r
8496 __IO uint32_t rDCOER_FCAL_RSEL04; /* DCO ER mode: Frequency calibration for DCORSEL 0 to 4 */
\r
8497 __IO uint32_t rDCOER_FCAL_RSEL5; /* DCO ER mode: Frequency calibration for DCORSEL 5 */
\r
8498 __IO uint32_t rDCOER_MAXPOSTUNE_RSEL04; /* DCO ER mode: Max Positive Tune for DCORSEL 0 to 4 */
\r
8499 __IO uint32_t rDCOER_MAXNEGTUNE_RSEL04; /* DCO ER mode: Max Negative Tune for DCORSEL 0 to 4 */
\r
8500 __IO uint32_t rDCOER_MAXPOSTUNE_RSEL5; /* DCO ER mode: Max Positive Tune for DCORSEL 5 */
\r
8501 __IO uint32_t rDCOER_MAXNEGTUNE_RSEL5; /* DCO ER mode: Max Negative Tune for DCORSEL 5 */
\r
8502 __IO uint32_t rDCOER_CONSTK_RSEL04; /* DCO ER mode: DCO Constant (K) for DCORSEL 0 to 4 */
\r
8503 __IO uint32_t rDCOER_CONSTK_RSEL5; /* DCO ER mode: DCO Constant (K) for DCORSEL 5 */
\r
8504 __IO uint32_t rADC14_CAL_TAG; /* ADC14 Calibration Tag */
\r
8505 __IO uint32_t rADC14_CAL_LEN; /* ADC14 Calibration Length */
\r
8506 __IO uint32_t rADC14_GF_EXTREF30C; /* ADC14 Gain Factor for External Reference 30°C */
\r
8507 __IO uint32_t rADC14_GF_EXTREF85C; /* ADC14 Gain Factor for External Reference 85°C */
\r
8508 __IO uint32_t rADC14_GF_BUF_EXTREF30C; /* ADC14 Gain Factor for Buffered External Reference 30°C */
\r
8509 __IO uint32_t rADC14_GF_BUF_EXTREF85C; /* ADC14 Gain Factor for Buffered External Reference 85°C */
\r
8510 __IO uint32_t rADC14_GF_BUF1P2V_INTREF30C_REFOUT0; /* ADC14 Gain Factor for Buffered 1.2V Internal Reference 30°C (REFOUT = 0) */
\r
8511 __IO uint32_t rADC14_GF_BUF1P2V_INTREF85C_REFOUT0; /* ADC14 Gain Factor for Buffered 1.2V Internal Reference 85°C (REFOUT = 0) */
\r
8512 __IO uint32_t rADC14_GF_BUF1P2V_INTREF30C_REFOUT1; /* ADC14 Gain Factor for Buffered 1.2V Internal Reference 30°C (REFOUT = 1) */
\r
8513 __IO uint32_t rADC14_GF_BUF1P2V_INTREF85C_REFOUT1; /* ADC14 Gain Factor for Buffered 1.2V Internal Reference 85°C (REFOUT = 1) */
\r
8514 __IO uint32_t rADC14_GF_BUF1P45V_INTREF30C_REFOUT0; /* ADC14 Gain Factor for Buffered 1.45V Internal Reference 30°C (REFOUT = 0) */
\r
8515 __IO uint32_t rADC14_GF_BUF1P45V_INTREF85C_REFOUT0; /* ADC14 Gain Factor for Buffered 1.45V Internal Reference 85°C (REFOUT = 0) */
\r
8516 __IO uint32_t rADC14_GF_BUF1P45V_INTREF30C_REFOUT1; /* ADC14 Gain Factor for Buffered 1.45V Internal Reference 30°C (REFOUT = 1) */
\r
8517 __IO uint32_t rADC14_GF_BUF1P45V_INTREF85C_REFOUT1; /* ADC14 Gain Factor for Buffered 1.45V Internal Reference 85°C (REFOUT = 1) */
\r
8518 __IO uint32_t rADC14_GF_BUF2P5V_INTREF30C_REFOUT0; /* ADC14 Gain Factor for Buffered 2.5V Internal Reference 30°C (REFOUT = 0) */
\r
8519 __IO uint32_t rADC14_GF_BUF2P5V_INTREF85C_REFOUT0; /* ADC14 Gain Factor for Buffered 2.5V Internal Reference 85°C (REFOUT = 0) */
\r
8520 __IO uint32_t rADC14_GF_BUF2P5V_INTREF30C_REFOUT1; /* ADC14 Gain Factor for Buffered 2.5V Internal Reference 30°C (REFOUT = 1) */
\r
8521 __IO uint32_t rADC14_GF_BUF2P5V_INTREF85C_REFOUT1; /* ADC14 Gain Factor for Buffered 2.5V Internal Reference 85°C (REFOUT = 1) */
\r
8522 __IO uint32_t rADC14_OFFSET_VRSEL_1; /* ADC14 Offset (ADC14VRSEL = 1h) */
\r
8523 __IO uint32_t rADC14_OFFSET_VRSEL_E; /* ADC14 Offset (ADC14VRSEL = Eh) */
\r
8524 __IO uint32_t rADC14_REF1P2V_TS30C; /* ADC14 1.2V Reference Temp. Sensor 30°C */
\r
8525 __IO uint32_t rADC14_REF1P2V_TS85C; /* ADC14 1.2V Reference Temp. Sensor 85°C */
\r
8526 __IO uint32_t rADC14_REF1P45V_TS30C; /* ADC14 1.45V Reference Temp. Sensor 30°C */
\r
8527 __IO uint32_t rADC14_REF1P45V_TS85C; /* ADC14 1.45V Reference Temp. Sensor 85°C */
\r
8528 __IO uint32_t rADC14_REF2P5V_TS30C; /* ADC14 2.5V Reference Temp. Sensor 30°C */
\r
8529 __IO uint32_t rADC14_REF2P5V_TS85C; /* ADC14 2.5V Reference Temp. Sensor 85°C */
\r
8530 __IO uint32_t rREF_CAL_TAG; /* REF Calibration Tag */
\r
8531 __IO uint32_t rREF_CAL_LEN; /* REF Calibration Length */
\r
8532 __IO uint32_t rREF_1P2V; /* REF 1.2V Reference */
\r
8533 __IO uint32_t rREF_1P45V; /* REF 1.45V Reference */
\r
8534 __IO uint32_t rREF_2P5V; /* REF 2.5V Reference */
\r
8535 __IO uint32_t rRANDOM_NUM_TAG; /* 128-bit Random Number Tag */
\r
8536 __IO uint32_t rRANDOM_NUM_LEN; /* 128-bit Random Number Length */
\r
8537 __IO uint32_t rRANDOM_NUM_1; /* 32-bit Random Number 1 */
\r
8538 __IO uint32_t rRANDOM_NUM_2; /* 32-bit Random Number 2 */
\r
8539 __IO uint32_t rRANDOM_NUM_3; /* 32-bit Random Number 3 */
\r
8540 __IO uint32_t rRANDOM_NUM_4; /* 32-bit Random Number 4 */
\r
8541 __IO uint32_t rBSL_CFG_TAG; /* BSL Configuration Tag */
\r
8542 __IO uint32_t rBSL_CFG_LEN; /* BSL Configuration Length */
\r
8543 __IO uint32_t rBSL_PERIPHIF_SEL; /* BSL Peripheral Interface Selection */
\r
8544 __IO uint32_t rBSL_PORTIF_CFG_UART; /* BSL Port Interface Configuration for UART */
\r
8545 __IO uint32_t rBSL_PORTIF_CFG_SPI; /* BSL Port Interface Configuration for SPI */
\r
8546 __IO uint32_t rBSL_PORTIF_CFG_I2C; /* BSL Port Interface Configuration for I2C */
\r
8547 __IO uint32_t rTLV_END; /* TLV End Word */
\r
8551 //*****************************************************************************
\r
8552 // WDT_A Registers
\r
8553 //*****************************************************************************
\r
8555 uint8_t RESERVED0[12];
\r
8556 union { /* WDTCTL Register */
\r
8558 struct { /* WDTCTL Bits */
\r
8559 __IO uint16_t bIS : 3; /* Watchdog timer interval select */
\r
8560 __O uint16_t bCNTCL : 1; /* Watchdog timer counter clear */
\r
8561 __IO uint16_t bTMSEL : 1; /* Watchdog timer mode select */
\r
8562 __IO uint16_t bSSEL : 2; /* Watchdog timer clock source select */
\r
8563 __IO uint16_t bHOLD : 1; /* Watchdog timer hold */
\r
8564 __IO uint16_t bPW : 8; /* Watchdog timer password */
\r
8570 //*****************************************************************************
\r
8571 // Peripheral register control bits
\r
8572 //*****************************************************************************
\r
8574 //*****************************************************************************
\r
8576 //*****************************************************************************
\r
8577 /* ADC14CTL0[ADC14SC] Bits */
\r
8578 #define ADC14SC_OFS ( 0) /* ADC14SC Offset */
\r
8579 #define ADC14SC (0x00000001) /* ADC14 start conversion */
\r
8580 /* ADC14CTL0[ADC14ENC] Bits */
\r
8581 #define ADC14ENC_OFS ( 1) /* ADC14ENC Offset */
\r
8582 #define ADC14ENC (0x00000002) /* ADC14 enable conversion */
\r
8583 /* ADC14CTL0[ADC14ON] Bits */
\r
8584 #define ADC14ON_OFS ( 4) /* ADC14ON Offset */
\r
8585 #define ADC14ON (0x00000010) /* ADC14 on */
\r
8586 /* ADC14CTL0[ADC14MSC] Bits */
\r
8587 #define ADC14MSC_OFS ( 7) /* ADC14MSC Offset */
\r
8588 #define ADC14MSC (0x00000080) /* ADC14 multiple sample and conversion */
\r
8589 /* ADC14CTL0[ADC14SHT0] Bits */
\r
8590 #define ADC14SHT0_OFS ( 8) /* ADC14SHT0 Offset */
\r
8591 #define ADC14SHT0_M (0x00000f00) /* ADC14 sample-and-hold time */
\r
8592 #define ADC14SHT00 (0x00000100) /* ADC14 sample-and-hold time */
\r
8593 #define ADC14SHT01 (0x00000200) /* ADC14 sample-and-hold time */
\r
8594 #define ADC14SHT02 (0x00000400) /* ADC14 sample-and-hold time */
\r
8595 #define ADC14SHT03 (0x00000800) /* ADC14 sample-and-hold time */
\r
8596 #define ADC14SHT0_0 (0x00000000) /* 4 */
\r
8597 #define ADC14SHT0_1 (0x00000100) /* 8 */
\r
8598 #define ADC14SHT0_2 (0x00000200) /* 16 */
\r
8599 #define ADC14SHT0_3 (0x00000300) /* 32 */
\r
8600 #define ADC14SHT0_4 (0x00000400) /* 64 */
\r
8601 #define ADC14SHT0_5 (0x00000500) /* 96 */
\r
8602 #define ADC14SHT0_6 (0x00000600) /* 128 */
\r
8603 #define ADC14SHT0_7 (0x00000700) /* 192 */
\r
8604 #define ADC14SHT0__4 (0x00000000) /* 4 */
\r
8605 #define ADC14SHT0__8 (0x00000100) /* 8 */
\r
8606 #define ADC14SHT0__16 (0x00000200) /* 16 */
\r
8607 #define ADC14SHT0__32 (0x00000300) /* 32 */
\r
8608 #define ADC14SHT0__64 (0x00000400) /* 64 */
\r
8609 #define ADC14SHT0__96 (0x00000500) /* 96 */
\r
8610 #define ADC14SHT0__128 (0x00000600) /* 128 */
\r
8611 #define ADC14SHT0__192 (0x00000700) /* 192 */
\r
8612 /* ADC14CTL0[ADC14SHT1] Bits */
\r
8613 #define ADC14SHT1_OFS (12) /* ADC14SHT1 Offset */
\r
8614 #define ADC14SHT1_M (0x0000f000) /* ADC14 sample-and-hold time */
\r
8615 #define ADC14SHT10 (0x00001000) /* ADC14 sample-and-hold time */
\r
8616 #define ADC14SHT11 (0x00002000) /* ADC14 sample-and-hold time */
\r
8617 #define ADC14SHT12 (0x00004000) /* ADC14 sample-and-hold time */
\r
8618 #define ADC14SHT13 (0x00008000) /* ADC14 sample-and-hold time */
\r
8619 #define ADC14SHT1_0 (0x00000000) /* 4 */
\r
8620 #define ADC14SHT1_1 (0x00001000) /* 8 */
\r
8621 #define ADC14SHT1_2 (0x00002000) /* 16 */
\r
8622 #define ADC14SHT1_3 (0x00003000) /* 32 */
\r
8623 #define ADC14SHT1_4 (0x00004000) /* 64 */
\r
8624 #define ADC14SHT1_5 (0x00005000) /* 96 */
\r
8625 #define ADC14SHT1_6 (0x00006000) /* 128 */
\r
8626 #define ADC14SHT1_7 (0x00007000) /* 192 */
\r
8627 #define ADC14SHT1__4 (0x00000000) /* 4 */
\r
8628 #define ADC14SHT1__8 (0x00001000) /* 8 */
\r
8629 #define ADC14SHT1__16 (0x00002000) /* 16 */
\r
8630 #define ADC14SHT1__32 (0x00003000) /* 32 */
\r
8631 #define ADC14SHT1__64 (0x00004000) /* 64 */
\r
8632 #define ADC14SHT1__96 (0x00005000) /* 96 */
\r
8633 #define ADC14SHT1__128 (0x00006000) /* 128 */
\r
8634 #define ADC14SHT1__192 (0x00007000) /* 192 */
\r
8635 /* ADC14CTL0[ADC14BUSY] Bits */
\r
8636 #define ADC14BUSY_OFS (16) /* ADC14BUSY Offset */
\r
8637 #define ADC14BUSY (0x00010000) /* ADC14 busy */
\r
8638 /* ADC14CTL0[ADC14CONSEQ] Bits */
\r
8639 #define ADC14CONSEQ_OFS (17) /* ADC14CONSEQ Offset */
\r
8640 #define ADC14CONSEQ_M (0x00060000) /* ADC14 conversion sequence mode select */
\r
8641 #define ADC14CONSEQ0 (0x00020000) /* ADC14 conversion sequence mode select */
\r
8642 #define ADC14CONSEQ1 (0x00040000) /* ADC14 conversion sequence mode select */
\r
8643 #define ADC14CONSEQ_0 (0x00000000) /* Single-channel, single-conversion */
\r
8644 #define ADC14CONSEQ_1 (0x00020000) /* Sequence-of-channels */
\r
8645 #define ADC14CONSEQ_2 (0x00040000) /* Repeat-single-channel */
\r
8646 #define ADC14CONSEQ_3 (0x00060000) /* Repeat-sequence-of-channels */
\r
8647 /* ADC14CTL0[ADC14SSEL] Bits */
\r
8648 #define ADC14SSEL_OFS (19) /* ADC14SSEL Offset */
\r
8649 #define ADC14SSEL_M (0x00380000) /* ADC14 clock source select */
\r
8650 #define ADC14SSEL0 (0x00080000) /* ADC14 clock source select */
\r
8651 #define ADC14SSEL1 (0x00100000) /* ADC14 clock source select */
\r
8652 #define ADC14SSEL2 (0x00200000) /* ADC14 clock source select */
\r
8653 #define ADC14SSEL_0 (0x00000000) /* MODCLK */
\r
8654 #define ADC14SSEL_1 (0x00080000) /* SYSCLK */
\r
8655 #define ADC14SSEL_2 (0x00100000) /* ACLK */
\r
8656 #define ADC14SSEL_3 (0x00180000) /* MCLK */
\r
8657 #define ADC14SSEL_4 (0x00200000) /* SMCLK */
\r
8658 #define ADC14SSEL_5 (0x00280000) /* HSMCLK */
\r
8659 #define ADC14SSEL__MODCLK (0x00000000) /* MODCLK */
\r
8660 #define ADC14SSEL__SYSCLK (0x00080000) /* SYSCLK */
\r
8661 #define ADC14SSEL__ACLK (0x00100000) /* ACLK */
\r
8662 #define ADC14SSEL__MCLK (0x00180000) /* MCLK */
\r
8663 #define ADC14SSEL__SMCLK (0x00200000) /* SMCLK */
\r
8664 #define ADC14SSEL__HSMCLK (0x00280000) /* HSMCLK */
\r
8665 /* ADC14CTL0[ADC14DIV] Bits */
\r
8666 #define ADC14DIV_OFS (22) /* ADC14DIV Offset */
\r
8667 #define ADC14DIV_M (0x01c00000) /* ADC14 clock divider */
\r
8668 #define ADC14DIV0 (0x00400000) /* ADC14 clock divider */
\r
8669 #define ADC14DIV1 (0x00800000) /* ADC14 clock divider */
\r
8670 #define ADC14DIV2 (0x01000000) /* ADC14 clock divider */
\r
8671 #define ADC14DIV_0 (0x00000000) /* /1 */
\r
8672 #define ADC14DIV_1 (0x00400000) /* /2 */
\r
8673 #define ADC14DIV_2 (0x00800000) /* /3 */
\r
8674 #define ADC14DIV_3 (0x00c00000) /* /4 */
\r
8675 #define ADC14DIV_4 (0x01000000) /* /5 */
\r
8676 #define ADC14DIV_5 (0x01400000) /* /6 */
\r
8677 #define ADC14DIV_6 (0x01800000) /* /7 */
\r
8678 #define ADC14DIV_7 (0x01c00000) /* /8 */
\r
8679 #define ADC14DIV__1 (0x00000000) /* /1 */
\r
8680 #define ADC14DIV__2 (0x00400000) /* /2 */
\r
8681 #define ADC14DIV__3 (0x00800000) /* /3 */
\r
8682 #define ADC14DIV__4 (0x00c00000) /* /4 */
\r
8683 #define ADC14DIV__5 (0x01000000) /* /5 */
\r
8684 #define ADC14DIV__6 (0x01400000) /* /6 */
\r
8685 #define ADC14DIV__7 (0x01800000) /* /7 */
\r
8686 #define ADC14DIV__8 (0x01c00000) /* /8 */
\r
8687 /* ADC14CTL0[ADC14ISSH] Bits */
\r
8688 #define ADC14ISSH_OFS (25) /* ADC14ISSH Offset */
\r
8689 #define ADC14ISSH (0x02000000) /* ADC14 invert signal sample-and-hold */
\r
8690 /* ADC14CTL0[ADC14SHP] Bits */
\r
8691 #define ADC14SHP_OFS (26) /* ADC14SHP Offset */
\r
8692 #define ADC14SHP (0x04000000) /* ADC14 sample-and-hold pulse-mode select */
\r
8693 /* ADC14CTL0[ADC14SHS] Bits */
\r
8694 #define ADC14SHS_OFS (27) /* ADC14SHS Offset */
\r
8695 #define ADC14SHS_M (0x38000000) /* ADC14 sample-and-hold source select */
\r
8696 #define ADC14SHS0 (0x08000000) /* ADC14 sample-and-hold source select */
\r
8697 #define ADC14SHS1 (0x10000000) /* ADC14 sample-and-hold source select */
\r
8698 #define ADC14SHS2 (0x20000000) /* ADC14 sample-and-hold source select */
\r
8699 #define ADC14SHS_0 (0x00000000) /* ADC14SC bit */
\r
8700 #define ADC14SHS_1 (0x08000000) /* See device-specific data sheet for source */
\r
8701 #define ADC14SHS_2 (0x10000000) /* See device-specific data sheet for source */
\r
8702 #define ADC14SHS_3 (0x18000000) /* See device-specific data sheet for source */
\r
8703 #define ADC14SHS_4 (0x20000000) /* See device-specific data sheet for source */
\r
8704 #define ADC14SHS_5 (0x28000000) /* See device-specific data sheet for source */
\r
8705 #define ADC14SHS_6 (0x30000000) /* See device-specific data sheet for source */
\r
8706 #define ADC14SHS_7 (0x38000000) /* See device-specific data sheet for source */
\r
8707 /* ADC14CTL0[ADC14PDIV] Bits */
\r
8708 #define ADC14PDIV_OFS (30) /* ADC14PDIV Offset */
\r
8709 #define ADC14PDIV_M (0xc0000000) /* ADC14 predivider */
\r
8710 #define ADC14PDIV0 (0x40000000) /* ADC14 predivider */
\r
8711 #define ADC14PDIV1 (0x80000000) /* ADC14 predivider */
\r
8712 #define ADC14PDIV_0 (0x00000000) /* Predivide by 1 */
\r
8713 #define ADC14PDIV_1 (0x40000000) /* Predivide by 4 */
\r
8714 #define ADC14PDIV_2 (0x80000000) /* Predivide by 32 */
\r
8715 #define ADC14PDIV_3 (0xc0000000) /* Predivide by 64 */
\r
8716 #define ADC14PDIV__1 (0x00000000) /* Predivide by 1 */
\r
8717 #define ADC14PDIV__4 (0x40000000) /* Predivide by 4 */
\r
8718 #define ADC14PDIV__32 (0x80000000) /* Predivide by 32 */
\r
8719 #define ADC14PDIV__64 (0xc0000000) /* Predivide by 64 */
\r
8720 /* ADC14CTL1[ADC14PWRMD] Bits */
\r
8721 #define ADC14PWRMD_OFS ( 0) /* ADC14PWRMD Offset */
\r
8722 #define ADC14PWRMD_M (0x00000003) /* ADC14 power modes */
\r
8723 #define ADC14PWRMD0 (0x00000001) /* ADC14 power modes */
\r
8724 #define ADC14PWRMD1 (0x00000002) /* ADC14 power modes */
\r
8725 #define ADC14PWRMD_0 (0x00000000) /* Regular power mode for use with any resolution setting. Sample rate can be up to 1 Msps. */
\r
8726 #define ADC14PWRMD_2 (0x00000002) /* Low-power mode for 12-bit, 10-bit, and 8-bit resolution settings. Sample rate must not exceed 200 ksps. */
\r
8727 /* ADC14CTL1[ADC14REFBURST] Bits */
\r
8728 #define ADC14REFBURST_OFS ( 2) /* ADC14REFBURST Offset */
\r
8729 #define ADC14REFBURST (0x00000004) /* ADC14 reference buffer burst */
\r
8730 /* ADC14CTL1[ADC14DF] Bits */
\r
8731 #define ADC14DF_OFS ( 3) /* ADC14DF Offset */
\r
8732 #define ADC14DF (0x00000008) /* ADC14 data read-back format */
\r
8733 /* ADC14CTL1[ADC14RES] Bits */
\r
8734 #define ADC14RES_OFS ( 4) /* ADC14RES Offset */
\r
8735 #define ADC14RES_M (0x00000030) /* ADC14 resolution */
\r
8736 #define ADC14RES0 (0x00000010) /* ADC14 resolution */
\r
8737 #define ADC14RES1 (0x00000020) /* ADC14 resolution */
\r
8738 #define ADC14RES_0 (0x00000000) /* 8 bit (9 clock cycle conversion time) */
\r
8739 #define ADC14RES_1 (0x00000010) /* 10 bit (11 clock cycle conversion time) */
\r
8740 #define ADC14RES_2 (0x00000020) /* 12 bit (14 clock cycle conversion time) */
\r
8741 #define ADC14RES_3 (0x00000030) /* 14 bit (16 clock cycle conversion time) */
\r
8742 #define ADC14RES__8BIT (0x00000000) /* 8 bit (9 clock cycle conversion time) */
\r
8743 #define ADC14RES__10BIT (0x00000010) /* 10 bit (11 clock cycle conversion time) */
\r
8744 #define ADC14RES__12BIT (0x00000020) /* 12 bit (14 clock cycle conversion time) */
\r
8745 #define ADC14RES__14BIT (0x00000030) /* 14 bit (16 clock cycle conversion time) */
\r
8746 /* ADC14CTL1[ADC14CSTARTADD] Bits */
\r
8747 #define ADC14CSTARTADD_OFS (16) /* ADC14CSTARTADD Offset */
\r
8748 #define ADC14CSTARTADD_M (0x001f0000) /* ADC14 conversion start address */
\r
8749 /* ADC14CTL1[ADC14BATMAP] Bits */
\r
8750 #define ADC14BATMAP_OFS (22) /* ADC14BATMAP Offset */
\r
8751 #define ADC14BATMAP (0x00400000) /* Controls 1/2 AVCC ADC input channel selection */
\r
8752 /* ADC14CTL1[ADC14TCMAP] Bits */
\r
8753 #define ADC14TCMAP_OFS (23) /* ADC14TCMAP Offset */
\r
8754 #define ADC14TCMAP (0x00800000) /* Controls temperature sensor ADC input channel selection */
\r
8755 /* ADC14CTL1[ADC14CH0MAP] Bits */
\r
8756 #define ADC14CH0MAP_OFS (24) /* ADC14CH0MAP Offset */
\r
8757 #define ADC14CH0MAP (0x01000000) /* Controls internal channel 0 selection to ADC input channel MAX-2 */
\r
8758 /* ADC14CTL1[ADC14CH1MAP] Bits */
\r
8759 #define ADC14CH1MAP_OFS (25) /* ADC14CH1MAP Offset */
\r
8760 #define ADC14CH1MAP (0x02000000) /* Controls internal channel 1 selection to ADC input channel MAX-3 */
\r
8761 /* ADC14CTL1[ADC14CH2MAP] Bits */
\r
8762 #define ADC14CH2MAP_OFS (26) /* ADC14CH2MAP Offset */
\r
8763 #define ADC14CH2MAP (0x04000000) /* Controls internal channel 2 selection to ADC input channel MAX-4 */
\r
8764 /* ADC14CTL1[ADC14CH3MAP] Bits */
\r
8765 #define ADC14CH3MAP_OFS (27) /* ADC14CH3MAP Offset */
\r
8766 #define ADC14CH3MAP (0x08000000) /* Controls internal channel 3 selection to ADC input channel MAX-5 */
\r
8767 /* ADC14LO0[ADC14LO0] Bits */
\r
8768 #define ADC14LO0_OFS ( 0) /* ADC14LO0 Offset */
\r
8769 #define ADC14LO0_M (0x0000ffff) /* Low threshold 0 */
\r
8770 /* ADC14HI0[ADC14HI0] Bits */
\r
8771 #define ADC14HI0_OFS ( 0) /* ADC14HI0 Offset */
\r
8772 #define ADC14HI0_M (0x0000ffff) /* High threshold 0 */
\r
8773 /* ADC14LO1[ADC14LO1] Bits */
\r
8774 #define ADC14LO1_OFS ( 0) /* ADC14LO1 Offset */
\r
8775 #define ADC14LO1_M (0x0000ffff) /* Low threshold 1 */
\r
8776 /* ADC14HI1[ADC14HI1] Bits */
\r
8777 #define ADC14HI1_OFS ( 0) /* ADC14HI1 Offset */
\r
8778 #define ADC14HI1_M (0x0000ffff) /* High threshold 1 */
\r
8779 /* ADC14MCTL[ADC14INCH] Bits */
\r
8780 #define ADC14INCH_OFS ( 0) /* ADC14INCH Offset */
\r
8781 #define ADC14INCH_M (0x0000001f) /* Input channel select */
\r
8782 #define ADC14INCH0 (0x00000001) /* Input channel select */
\r
8783 #define ADC14INCH1 (0x00000002) /* Input channel select */
\r
8784 #define ADC14INCH2 (0x00000004) /* Input channel select */
\r
8785 #define ADC14INCH3 (0x00000008) /* Input channel select */
\r
8786 #define ADC14INCH4 (0x00000010) /* Input channel select */
\r
8787 #define ADC14INCH_0 (0x00000000) /* If ADC14DIF = 0: A0; If ADC14DIF = 1: Ain+ = A0, Ain- = A1 */
\r
8788 #define ADC14INCH_1 (0x00000001) /* If ADC14DIF = 0: A1; If ADC14DIF = 1: Ain+ = A0, Ain- = A1 */
\r
8789 #define ADC14INCH_2 (0x00000002) /* If ADC14DIF = 0: A2; If ADC14DIF = 1: Ain+ = A2, Ain- = A3 */
\r
8790 #define ADC14INCH_3 (0x00000003) /* If ADC14DIF = 0: A3; If ADC14DIF = 1: Ain+ = A2, Ain- = A3 */
\r
8791 #define ADC14INCH_4 (0x00000004) /* If ADC14DIF = 0: A4; If ADC14DIF = 1: Ain+ = A4, Ain- = A5 */
\r
8792 #define ADC14INCH_5 (0x00000005) /* If ADC14DIF = 0: A5; If ADC14DIF = 1: Ain+ = A4, Ain- = A5 */
\r
8793 #define ADC14INCH_6 (0x00000006) /* If ADC14DIF = 0: A6; If ADC14DIF = 1: Ain+ = A6, Ain- = A7 */
\r
8794 #define ADC14INCH_7 (0x00000007) /* If ADC14DIF = 0: A7; If ADC14DIF = 1: Ain+ = A6, Ain- = A7 */
\r
8795 #define ADC14INCH_8 (0x00000008) /* If ADC14DIF = 0: A8; If ADC14DIF = 1: Ain+ = A8, Ain- = A9 */
\r
8796 #define ADC14INCH_9 (0x00000009) /* If ADC14DIF = 0: A9; If ADC14DIF = 1: Ain+ = A8, Ain- = A9 */
\r
8797 #define ADC14INCH_10 (0x0000000a) /* If ADC14DIF = 0: A10; If ADC14DIF = 1: Ain+ = A10, Ain- = A11 */
\r
8798 #define ADC14INCH_11 (0x0000000b) /* If ADC14DIF = 0: A11; If ADC14DIF = 1: Ain+ = A10, Ain- = A11 */
\r
8799 #define ADC14INCH_12 (0x0000000c) /* If ADC14DIF = 0: A12; If ADC14DIF = 1: Ain+ = A12, Ain- = A13 */
\r
8800 #define ADC14INCH_13 (0x0000000d) /* If ADC14DIF = 0: A13; If ADC14DIF = 1: Ain+ = A12, Ain- = A13 */
\r
8801 #define ADC14INCH_14 (0x0000000e) /* If ADC14DIF = 0: A14; If ADC14DIF = 1: Ain+ = A14, Ain- = A15 */
\r
8802 #define ADC14INCH_15 (0x0000000f) /* If ADC14DIF = 0: A15; If ADC14DIF = 1: Ain+ = A14, Ain- = A15 */
\r
8803 #define ADC14INCH_16 (0x00000010) /* If ADC14DIF = 0: A16; If ADC14DIF = 1: Ain+ = A16, Ain- = A17 */
\r
8804 #define ADC14INCH_17 (0x00000011) /* If ADC14DIF = 0: A17; If ADC14DIF = 1: Ain+ = A16, Ain- = A17 */
\r
8805 #define ADC14INCH_18 (0x00000012) /* If ADC14DIF = 0: A18; If ADC14DIF = 1: Ain+ = A18, Ain- = A19 */
\r
8806 #define ADC14INCH_19 (0x00000013) /* If ADC14DIF = 0: A19; If ADC14DIF = 1: Ain+ = A18, Ain- = A19 */
\r
8807 #define ADC14INCH_20 (0x00000014) /* If ADC14DIF = 0: A20; If ADC14DIF = 1: Ain+ = A20, Ain- = A21 */
\r
8808 #define ADC14INCH_21 (0x00000015) /* If ADC14DIF = 0: A21; If ADC14DIF = 1: Ain+ = A20, Ain- = A21 */
\r
8809 #define ADC14INCH_22 (0x00000016) /* If ADC14DIF = 0: A22; If ADC14DIF = 1: Ain+ = A22, Ain- = A23 */
\r
8810 #define ADC14INCH_23 (0x00000017) /* If ADC14DIF = 0: A23; If ADC14DIF = 1: Ain+ = A22, Ain- = A23 */
\r
8811 #define ADC14INCH_24 (0x00000018) /* If ADC14DIF = 0: A24; If ADC14DIF = 1: Ain+ = A24, Ain- = A25 */
\r
8812 #define ADC14INCH_25 (0x00000019) /* If ADC14DIF = 0: A25; If ADC14DIF = 1: Ain+ = A24, Ain- = A25 */
\r
8813 #define ADC14INCH_26 (0x0000001a) /* If ADC14DIF = 0: A26; If ADC14DIF = 1: Ain+ = A26, Ain- = A27 */
\r
8814 #define ADC14INCH_27 (0x0000001b) /* If ADC14DIF = 0: A27; If ADC14DIF = 1: Ain+ = A26, Ain- = A27 */
\r
8815 #define ADC14INCH_28 (0x0000001c) /* If ADC14DIF = 0: A28; If ADC14DIF = 1: Ain+ = A28, Ain- = A29 */
\r
8816 #define ADC14INCH_29 (0x0000001d) /* If ADC14DIF = 0: A29; If ADC14DIF = 1: Ain+ = A28, Ain- = A29 */
\r
8817 #define ADC14INCH_30 (0x0000001e) /* If ADC14DIF = 0: A30; If ADC14DIF = 1: Ain+ = A30, Ain- = A31 */
\r
8818 #define ADC14INCH_31 (0x0000001f) /* If ADC14DIF = 0: A31; If ADC14DIF = 1: Ain+ = A30, Ain- = A31 */
\r
8819 /* ADC14MCTL[ADC14EOS] Bits */
\r
8820 #define ADC14EOS_OFS ( 7) /* ADC14EOS Offset */
\r
8821 #define ADC14EOS (0x00000080) /* End of sequence */
\r
8822 /* ADC14MCTL[ADC14VRSEL] Bits */
\r
8823 #define ADC14VRSEL_OFS ( 8) /* ADC14VRSEL Offset */
\r
8824 #define ADC14VRSEL_M (0x00000f00) /* Selects combinations of V(R+) and V(R-) sources */
\r
8825 #define ADC14VRSEL0 (0x00000100) /* Selects combinations of V(R+) and V(R-) sources */
\r
8826 #define ADC14VRSEL1 (0x00000200) /* Selects combinations of V(R+) and V(R-) sources */
\r
8827 #define ADC14VRSEL2 (0x00000400) /* Selects combinations of V(R+) and V(R-) sources */
\r
8828 #define ADC14VRSEL3 (0x00000800) /* Selects combinations of V(R+) and V(R-) sources */
\r
8829 #define ADC14VRSEL_0 (0x00000000) /* V(R+) = AVCC, V(R-) = AVSS */
\r
8830 #define ADC14VRSEL_1 (0x00000100) /* V(R+) = VREF buffered, V(R-) = AVSS */
\r
8831 #define ADC14VRSEL_14 (0x00000e00) /* V(R+) = VeREF+, V(R-) = VeREF- */
\r
8832 #define ADC14VRSEL_15 (0x00000f00) /* V(R+) = VeREF+ buffered, V(R-) = VeREF */
\r
8833 /* ADC14MCTL[ADC14DIF] Bits */
\r
8834 #define ADC14DIF_OFS (13) /* ADC14DIF Offset */
\r
8835 #define ADC14DIF (0x00002000) /* Differential mode */
\r
8836 /* ADC14MCTL[ADC14WINC] Bits */
\r
8837 #define ADC14WINC_OFS (14) /* ADC14WINC Offset */
\r
8838 #define ADC14WINC (0x00004000) /* Comparator window enable */
\r
8839 /* ADC14MCTL[ADC14WINCTH] Bits */
\r
8840 #define ADC14WINCTH_OFS (15) /* ADC14WINCTH Offset */
\r
8841 #define ADC14WINCTH (0x00008000) /* Window comparator threshold register selection */
\r
8842 /* ADC14MEM[CONVERSION_RESULTS] Bits */
\r
8843 #define CONVERSION_RESULTS_OFS ( 0) /* Conversion_Results Offset */
\r
8844 #define CONVERSION_RESULTS_M (0x0000ffff) /* Conversion Result */
\r
8845 /* ADC14IER0[ADC14IE0] Bits */
\r
8846 #define ADC14IE0_OFS ( 0) /* ADC14IE0 Offset */
\r
8847 #define ADC14IE0 (0x00000001) /* Interrupt enable */
\r
8848 /* ADC14IER0[ADC14IE1] Bits */
\r
8849 #define ADC14IE1_OFS ( 1) /* ADC14IE1 Offset */
\r
8850 #define ADC14IE1 (0x00000002) /* Interrupt enable */
\r
8851 /* ADC14IER0[ADC14IE2] Bits */
\r
8852 #define ADC14IE2_OFS ( 2) /* ADC14IE2 Offset */
\r
8853 #define ADC14IE2 (0x00000004) /* Interrupt enable */
\r
8854 /* ADC14IER0[ADC14IE3] Bits */
\r
8855 #define ADC14IE3_OFS ( 3) /* ADC14IE3 Offset */
\r
8856 #define ADC14IE3 (0x00000008) /* Interrupt enable */
\r
8857 /* ADC14IER0[ADC14IE4] Bits */
\r
8858 #define ADC14IE4_OFS ( 4) /* ADC14IE4 Offset */
\r
8859 #define ADC14IE4 (0x00000010) /* Interrupt enable */
\r
8860 /* ADC14IER0[ADC14IE5] Bits */
\r
8861 #define ADC14IE5_OFS ( 5) /* ADC14IE5 Offset */
\r
8862 #define ADC14IE5 (0x00000020) /* Interrupt enable */
\r
8863 /* ADC14IER0[ADC14IE6] Bits */
\r
8864 #define ADC14IE6_OFS ( 6) /* ADC14IE6 Offset */
\r
8865 #define ADC14IE6 (0x00000040) /* Interrupt enable */
\r
8866 /* ADC14IER0[ADC14IE7] Bits */
\r
8867 #define ADC14IE7_OFS ( 7) /* ADC14IE7 Offset */
\r
8868 #define ADC14IE7 (0x00000080) /* Interrupt enable */
\r
8869 /* ADC14IER0[ADC14IE8] Bits */
\r
8870 #define ADC14IE8_OFS ( 8) /* ADC14IE8 Offset */
\r
8871 #define ADC14IE8 (0x00000100) /* Interrupt enable */
\r
8872 /* ADC14IER0[ADC14IE9] Bits */
\r
8873 #define ADC14IE9_OFS ( 9) /* ADC14IE9 Offset */
\r
8874 #define ADC14IE9 (0x00000200) /* Interrupt enable */
\r
8875 /* ADC14IER0[ADC14IE10] Bits */
\r
8876 #define ADC14IE10_OFS (10) /* ADC14IE10 Offset */
\r
8877 #define ADC14IE10 (0x00000400) /* Interrupt enable */
\r
8878 /* ADC14IER0[ADC14IE11] Bits */
\r
8879 #define ADC14IE11_OFS (11) /* ADC14IE11 Offset */
\r
8880 #define ADC14IE11 (0x00000800) /* Interrupt enable */
\r
8881 /* ADC14IER0[ADC14IE12] Bits */
\r
8882 #define ADC14IE12_OFS (12) /* ADC14IE12 Offset */
\r
8883 #define ADC14IE12 (0x00001000) /* Interrupt enable */
\r
8884 /* ADC14IER0[ADC14IE13] Bits */
\r
8885 #define ADC14IE13_OFS (13) /* ADC14IE13 Offset */
\r
8886 #define ADC14IE13 (0x00002000) /* Interrupt enable */
\r
8887 /* ADC14IER0[ADC14IE14] Bits */
\r
8888 #define ADC14IE14_OFS (14) /* ADC14IE14 Offset */
\r
8889 #define ADC14IE14 (0x00004000) /* Interrupt enable */
\r
8890 /* ADC14IER0[ADC14IE15] Bits */
\r
8891 #define ADC14IE15_OFS (15) /* ADC14IE15 Offset */
\r
8892 #define ADC14IE15 (0x00008000) /* Interrupt enable */
\r
8893 /* ADC14IER0[ADC14IE16] Bits */
\r
8894 #define ADC14IE16_OFS (16) /* ADC14IE16 Offset */
\r
8895 #define ADC14IE16 (0x00010000) /* Interrupt enable */
\r
8896 /* ADC14IER0[ADC14IE17] Bits */
\r
8897 #define ADC14IE17_OFS (17) /* ADC14IE17 Offset */
\r
8898 #define ADC14IE17 (0x00020000) /* Interrupt enable */
\r
8899 /* ADC14IER0[ADC14IE19] Bits */
\r
8900 #define ADC14IE19_OFS (19) /* ADC14IE19 Offset */
\r
8901 #define ADC14IE19 (0x00080000) /* Interrupt enable */
\r
8902 /* ADC14IER0[ADC14IE18] Bits */
\r
8903 #define ADC14IE18_OFS (18) /* ADC14IE18 Offset */
\r
8904 #define ADC14IE18 (0x00040000) /* Interrupt enable */
\r
8905 /* ADC14IER0[ADC14IE20] Bits */
\r
8906 #define ADC14IE20_OFS (20) /* ADC14IE20 Offset */
\r
8907 #define ADC14IE20 (0x00100000) /* Interrupt enable */
\r
8908 /* ADC14IER0[ADC14IE21] Bits */
\r
8909 #define ADC14IE21_OFS (21) /* ADC14IE21 Offset */
\r
8910 #define ADC14IE21 (0x00200000) /* Interrupt enable */
\r
8911 /* ADC14IER0[ADC14IE22] Bits */
\r
8912 #define ADC14IE22_OFS (22) /* ADC14IE22 Offset */
\r
8913 #define ADC14IE22 (0x00400000) /* Interrupt enable */
\r
8914 /* ADC14IER0[ADC14IE23] Bits */
\r
8915 #define ADC14IE23_OFS (23) /* ADC14IE23 Offset */
\r
8916 #define ADC14IE23 (0x00800000) /* Interrupt enable */
\r
8917 /* ADC14IER0[ADC14IE24] Bits */
\r
8918 #define ADC14IE24_OFS (24) /* ADC14IE24 Offset */
\r
8919 #define ADC14IE24 (0x01000000) /* Interrupt enable */
\r
8920 /* ADC14IER0[ADC14IE25] Bits */
\r
8921 #define ADC14IE25_OFS (25) /* ADC14IE25 Offset */
\r
8922 #define ADC14IE25 (0x02000000) /* Interrupt enable */
\r
8923 /* ADC14IER0[ADC14IE26] Bits */
\r
8924 #define ADC14IE26_OFS (26) /* ADC14IE26 Offset */
\r
8925 #define ADC14IE26 (0x04000000) /* Interrupt enable */
\r
8926 /* ADC14IER0[ADC14IE27] Bits */
\r
8927 #define ADC14IE27_OFS (27) /* ADC14IE27 Offset */
\r
8928 #define ADC14IE27 (0x08000000) /* Interrupt enable */
\r
8929 /* ADC14IER0[ADC14IE28] Bits */
\r
8930 #define ADC14IE28_OFS (28) /* ADC14IE28 Offset */
\r
8931 #define ADC14IE28 (0x10000000) /* Interrupt enable */
\r
8932 /* ADC14IER0[ADC14IE29] Bits */
\r
8933 #define ADC14IE29_OFS (29) /* ADC14IE29 Offset */
\r
8934 #define ADC14IE29 (0x20000000) /* Interrupt enable */
\r
8935 /* ADC14IER0[ADC14IE30] Bits */
\r
8936 #define ADC14IE30_OFS (30) /* ADC14IE30 Offset */
\r
8937 #define ADC14IE30 (0x40000000) /* Interrupt enable */
\r
8938 /* ADC14IER0[ADC14IE31] Bits */
\r
8939 #define ADC14IE31_OFS (31) /* ADC14IE31 Offset */
\r
8940 #define ADC14IE31 (0x80000000) /* Interrupt enable */
\r
8941 /* ADC14IER1[ADC14INIE] Bits */
\r
8942 #define ADC14INIE_OFS ( 1) /* ADC14INIE Offset */
\r
8943 #define ADC14INIE (0x00000002) /* Interrupt enable for ADC14MEMx within comparator window */
\r
8944 /* ADC14IER1[ADC14LOIE] Bits */
\r
8945 #define ADC14LOIE_OFS ( 2) /* ADC14LOIE Offset */
\r
8946 #define ADC14LOIE (0x00000004) /* Interrupt enable for ADC14MEMx below comparator window */
\r
8947 /* ADC14IER1[ADC14HIIE] Bits */
\r
8948 #define ADC14HIIE_OFS ( 3) /* ADC14HIIE Offset */
\r
8949 #define ADC14HIIE (0x00000008) /* Interrupt enable for ADC14MEMx above comparator window */
\r
8950 /* ADC14IER1[ADC14OVIE] Bits */
\r
8951 #define ADC14OVIE_OFS ( 4) /* ADC14OVIE Offset */
\r
8952 #define ADC14OVIE (0x00000010) /* ADC14MEMx overflow-interrupt enable */
\r
8953 /* ADC14IER1[ADC14TOVIE] Bits */
\r
8954 #define ADC14TOVIE_OFS ( 5) /* ADC14TOVIE Offset */
\r
8955 #define ADC14TOVIE (0x00000020) /* ADC14 conversion-time-overflow interrupt enable */
\r
8956 /* ADC14IER1[ADC14RDYIE] Bits */
\r
8957 #define ADC14RDYIE_OFS ( 6) /* ADC14RDYIE Offset */
\r
8958 #define ADC14RDYIE (0x00000040) /* ADC14 local buffered reference ready interrupt enable */
\r
8959 /* ADC14IFGR0[ADC14IFG0] Bits */
\r
8960 #define ADC14IFG0_OFS ( 0) /* ADC14IFG0 Offset */
\r
8961 #define ADC14IFG0 (0x00000001) /* ADC14MEM0 interrupt flag */
\r
8962 /* ADC14IFGR0[ADC14IFG1] Bits */
\r
8963 #define ADC14IFG1_OFS ( 1) /* ADC14IFG1 Offset */
\r
8964 #define ADC14IFG1 (0x00000002) /* ADC14MEM1 interrupt flag */
\r
8965 /* ADC14IFGR0[ADC14IFG2] Bits */
\r
8966 #define ADC14IFG2_OFS ( 2) /* ADC14IFG2 Offset */
\r
8967 #define ADC14IFG2 (0x00000004) /* ADC14MEM2 interrupt flag */
\r
8968 /* ADC14IFGR0[ADC14IFG3] Bits */
\r
8969 #define ADC14IFG3_OFS ( 3) /* ADC14IFG3 Offset */
\r
8970 #define ADC14IFG3 (0x00000008) /* ADC14MEM3 interrupt flag */
\r
8971 /* ADC14IFGR0[ADC14IFG4] Bits */
\r
8972 #define ADC14IFG4_OFS ( 4) /* ADC14IFG4 Offset */
\r
8973 #define ADC14IFG4 (0x00000010) /* ADC14MEM4 interrupt flag */
\r
8974 /* ADC14IFGR0[ADC14IFG5] Bits */
\r
8975 #define ADC14IFG5_OFS ( 5) /* ADC14IFG5 Offset */
\r
8976 #define ADC14IFG5 (0x00000020) /* ADC14MEM5 interrupt flag */
\r
8977 /* ADC14IFGR0[ADC14IFG6] Bits */
\r
8978 #define ADC14IFG6_OFS ( 6) /* ADC14IFG6 Offset */
\r
8979 #define ADC14IFG6 (0x00000040) /* ADC14MEM6 interrupt flag */
\r
8980 /* ADC14IFGR0[ADC14IFG7] Bits */
\r
8981 #define ADC14IFG7_OFS ( 7) /* ADC14IFG7 Offset */
\r
8982 #define ADC14IFG7 (0x00000080) /* ADC14MEM7 interrupt flag */
\r
8983 /* ADC14IFGR0[ADC14IFG8] Bits */
\r
8984 #define ADC14IFG8_OFS ( 8) /* ADC14IFG8 Offset */
\r
8985 #define ADC14IFG8 (0x00000100) /* ADC14MEM8 interrupt flag */
\r
8986 /* ADC14IFGR0[ADC14IFG9] Bits */
\r
8987 #define ADC14IFG9_OFS ( 9) /* ADC14IFG9 Offset */
\r
8988 #define ADC14IFG9 (0x00000200) /* ADC14MEM9 interrupt flag */
\r
8989 /* ADC14IFGR0[ADC14IFG10] Bits */
\r
8990 #define ADC14IFG10_OFS (10) /* ADC14IFG10 Offset */
\r
8991 #define ADC14IFG10 (0x00000400) /* ADC14MEM10 interrupt flag */
\r
8992 /* ADC14IFGR0[ADC14IFG11] Bits */
\r
8993 #define ADC14IFG11_OFS (11) /* ADC14IFG11 Offset */
\r
8994 #define ADC14IFG11 (0x00000800) /* ADC14MEM11 interrupt flag */
\r
8995 /* ADC14IFGR0[ADC14IFG12] Bits */
\r
8996 #define ADC14IFG12_OFS (12) /* ADC14IFG12 Offset */
\r
8997 #define ADC14IFG12 (0x00001000) /* ADC14MEM12 interrupt flag */
\r
8998 /* ADC14IFGR0[ADC14IFG13] Bits */
\r
8999 #define ADC14IFG13_OFS (13) /* ADC14IFG13 Offset */
\r
9000 #define ADC14IFG13 (0x00002000) /* ADC14MEM13 interrupt flag */
\r
9001 /* ADC14IFGR0[ADC14IFG14] Bits */
\r
9002 #define ADC14IFG14_OFS (14) /* ADC14IFG14 Offset */
\r
9003 #define ADC14IFG14 (0x00004000) /* ADC14MEM14 interrupt flag */
\r
9004 /* ADC14IFGR0[ADC14IFG15] Bits */
\r
9005 #define ADC14IFG15_OFS (15) /* ADC14IFG15 Offset */
\r
9006 #define ADC14IFG15 (0x00008000) /* ADC14MEM15 interrupt flag */
\r
9007 /* ADC14IFGR0[ADC14IFG16] Bits */
\r
9008 #define ADC14IFG16_OFS (16) /* ADC14IFG16 Offset */
\r
9009 #define ADC14IFG16 (0x00010000) /* ADC14MEM16 interrupt flag */
\r
9010 /* ADC14IFGR0[ADC14IFG17] Bits */
\r
9011 #define ADC14IFG17_OFS (17) /* ADC14IFG17 Offset */
\r
9012 #define ADC14IFG17 (0x00020000) /* ADC14MEM17 interrupt flag */
\r
9013 /* ADC14IFGR0[ADC14IFG18] Bits */
\r
9014 #define ADC14IFG18_OFS (18) /* ADC14IFG18 Offset */
\r
9015 #define ADC14IFG18 (0x00040000) /* ADC14MEM18 interrupt flag */
\r
9016 /* ADC14IFGR0[ADC14IFG19] Bits */
\r
9017 #define ADC14IFG19_OFS (19) /* ADC14IFG19 Offset */
\r
9018 #define ADC14IFG19 (0x00080000) /* ADC14MEM19 interrupt flag */
\r
9019 /* ADC14IFGR0[ADC14IFG20] Bits */
\r
9020 #define ADC14IFG20_OFS (20) /* ADC14IFG20 Offset */
\r
9021 #define ADC14IFG20 (0x00100000) /* ADC14MEM20 interrupt flag */
\r
9022 /* ADC14IFGR0[ADC14IFG21] Bits */
\r
9023 #define ADC14IFG21_OFS (21) /* ADC14IFG21 Offset */
\r
9024 #define ADC14IFG21 (0x00200000) /* ADC14MEM21 interrupt flag */
\r
9025 /* ADC14IFGR0[ADC14IFG22] Bits */
\r
9026 #define ADC14IFG22_OFS (22) /* ADC14IFG22 Offset */
\r
9027 #define ADC14IFG22 (0x00400000) /* ADC14MEM22 interrupt flag */
\r
9028 /* ADC14IFGR0[ADC14IFG23] Bits */
\r
9029 #define ADC14IFG23_OFS (23) /* ADC14IFG23 Offset */
\r
9030 #define ADC14IFG23 (0x00800000) /* ADC14MEM23 interrupt flag */
\r
9031 /* ADC14IFGR0[ADC14IFG24] Bits */
\r
9032 #define ADC14IFG24_OFS (24) /* ADC14IFG24 Offset */
\r
9033 #define ADC14IFG24 (0x01000000) /* ADC14MEM24 interrupt flag */
\r
9034 /* ADC14IFGR0[ADC14IFG25] Bits */
\r
9035 #define ADC14IFG25_OFS (25) /* ADC14IFG25 Offset */
\r
9036 #define ADC14IFG25 (0x02000000) /* ADC14MEM25 interrupt flag */
\r
9037 /* ADC14IFGR0[ADC14IFG26] Bits */
\r
9038 #define ADC14IFG26_OFS (26) /* ADC14IFG26 Offset */
\r
9039 #define ADC14IFG26 (0x04000000) /* ADC14MEM26 interrupt flag */
\r
9040 /* ADC14IFGR0[ADC14IFG27] Bits */
\r
9041 #define ADC14IFG27_OFS (27) /* ADC14IFG27 Offset */
\r
9042 #define ADC14IFG27 (0x08000000) /* ADC14MEM27 interrupt flag */
\r
9043 /* ADC14IFGR0[ADC14IFG28] Bits */
\r
9044 #define ADC14IFG28_OFS (28) /* ADC14IFG28 Offset */
\r
9045 #define ADC14IFG28 (0x10000000) /* ADC14MEM28 interrupt flag */
\r
9046 /* ADC14IFGR0[ADC14IFG29] Bits */
\r
9047 #define ADC14IFG29_OFS (29) /* ADC14IFG29 Offset */
\r
9048 #define ADC14IFG29 (0x20000000) /* ADC14MEM29 interrupt flag */
\r
9049 /* ADC14IFGR0[ADC14IFG30] Bits */
\r
9050 #define ADC14IFG30_OFS (30) /* ADC14IFG30 Offset */
\r
9051 #define ADC14IFG30 (0x40000000) /* ADC14MEM30 interrupt flag */
\r
9052 /* ADC14IFGR0[ADC14IFG31] Bits */
\r
9053 #define ADC14IFG31_OFS (31) /* ADC14IFG31 Offset */
\r
9054 #define ADC14IFG31 (0x80000000) /* ADC14MEM31 interrupt flag */
\r
9055 /* ADC14IFGR1[ADC14INIFG] Bits */
\r
9056 #define ADC14INIFG_OFS ( 1) /* ADC14INIFG Offset */
\r
9057 #define ADC14INIFG (0x00000002) /* Interrupt flag for ADC14MEMx within comparator window */
\r
9058 /* ADC14IFGR1[ADC14LOIFG] Bits */
\r
9059 #define ADC14LOIFG_OFS ( 2) /* ADC14LOIFG Offset */
\r
9060 #define ADC14LOIFG (0x00000004) /* Interrupt flag for ADC14MEMx below comparator window */
\r
9061 /* ADC14IFGR1[ADC14HIIFG] Bits */
\r
9062 #define ADC14HIIFG_OFS ( 3) /* ADC14HIIFG Offset */
\r
9063 #define ADC14HIIFG (0x00000008) /* Interrupt flag for ADC14MEMx above comparator window */
\r
9064 /* ADC14IFGR1[ADC14OVIFG] Bits */
\r
9065 #define ADC14OVIFG_OFS ( 4) /* ADC14OVIFG Offset */
\r
9066 #define ADC14OVIFG (0x00000010) /* ADC14MEMx overflow interrupt flag */
\r
9067 /* ADC14IFGR1[ADC14TOVIFG] Bits */
\r
9068 #define ADC14TOVIFG_OFS ( 5) /* ADC14TOVIFG Offset */
\r
9069 #define ADC14TOVIFG (0x00000020) /* ADC14 conversion time overflow interrupt flag */
\r
9070 /* ADC14IFGR1[ADC14RDYIFG] Bits */
\r
9071 #define ADC14RDYIFG_OFS ( 6) /* ADC14RDYIFG Offset */
\r
9072 #define ADC14RDYIFG (0x00000040) /* ADC14 local buffered reference ready interrupt flag */
\r
9073 /* ADC14CLRIFGR0[CLRADC14IFG0] Bits */
\r
9074 #define CLRADC14IFG0_OFS ( 0) /* CLRADC14IFG0 Offset */
\r
9075 #define CLRADC14IFG0 (0x00000001) /* clear ADC14IFG0 */
\r
9076 /* ADC14CLRIFGR0[CLRADC14IFG1] Bits */
\r
9077 #define CLRADC14IFG1_OFS ( 1) /* CLRADC14IFG1 Offset */
\r
9078 #define CLRADC14IFG1 (0x00000002) /* clear ADC14IFG1 */
\r
9079 /* ADC14CLRIFGR0[CLRADC14IFG2] Bits */
\r
9080 #define CLRADC14IFG2_OFS ( 2) /* CLRADC14IFG2 Offset */
\r
9081 #define CLRADC14IFG2 (0x00000004) /* clear ADC14IFG2 */
\r
9082 /* ADC14CLRIFGR0[CLRADC14IFG3] Bits */
\r
9083 #define CLRADC14IFG3_OFS ( 3) /* CLRADC14IFG3 Offset */
\r
9084 #define CLRADC14IFG3 (0x00000008) /* clear ADC14IFG3 */
\r
9085 /* ADC14CLRIFGR0[CLRADC14IFG4] Bits */
\r
9086 #define CLRADC14IFG4_OFS ( 4) /* CLRADC14IFG4 Offset */
\r
9087 #define CLRADC14IFG4 (0x00000010) /* clear ADC14IFG4 */
\r
9088 /* ADC14CLRIFGR0[CLRADC14IFG5] Bits */
\r
9089 #define CLRADC14IFG5_OFS ( 5) /* CLRADC14IFG5 Offset */
\r
9090 #define CLRADC14IFG5 (0x00000020) /* clear ADC14IFG5 */
\r
9091 /* ADC14CLRIFGR0[CLRADC14IFG6] Bits */
\r
9092 #define CLRADC14IFG6_OFS ( 6) /* CLRADC14IFG6 Offset */
\r
9093 #define CLRADC14IFG6 (0x00000040) /* clear ADC14IFG6 */
\r
9094 /* ADC14CLRIFGR0[CLRADC14IFG7] Bits */
\r
9095 #define CLRADC14IFG7_OFS ( 7) /* CLRADC14IFG7 Offset */
\r
9096 #define CLRADC14IFG7 (0x00000080) /* clear ADC14IFG7 */
\r
9097 /* ADC14CLRIFGR0[CLRADC14IFG8] Bits */
\r
9098 #define CLRADC14IFG8_OFS ( 8) /* CLRADC14IFG8 Offset */
\r
9099 #define CLRADC14IFG8 (0x00000100) /* clear ADC14IFG8 */
\r
9100 /* ADC14CLRIFGR0[CLRADC14IFG9] Bits */
\r
9101 #define CLRADC14IFG9_OFS ( 9) /* CLRADC14IFG9 Offset */
\r
9102 #define CLRADC14IFG9 (0x00000200) /* clear ADC14IFG9 */
\r
9103 /* ADC14CLRIFGR0[CLRADC14IFG10] Bits */
\r
9104 #define CLRADC14IFG10_OFS (10) /* CLRADC14IFG10 Offset */
\r
9105 #define CLRADC14IFG10 (0x00000400) /* clear ADC14IFG10 */
\r
9106 /* ADC14CLRIFGR0[CLRADC14IFG11] Bits */
\r
9107 #define CLRADC14IFG11_OFS (11) /* CLRADC14IFG11 Offset */
\r
9108 #define CLRADC14IFG11 (0x00000800) /* clear ADC14IFG11 */
\r
9109 /* ADC14CLRIFGR0[CLRADC14IFG12] Bits */
\r
9110 #define CLRADC14IFG12_OFS (12) /* CLRADC14IFG12 Offset */
\r
9111 #define CLRADC14IFG12 (0x00001000) /* clear ADC14IFG12 */
\r
9112 /* ADC14CLRIFGR0[CLRADC14IFG13] Bits */
\r
9113 #define CLRADC14IFG13_OFS (13) /* CLRADC14IFG13 Offset */
\r
9114 #define CLRADC14IFG13 (0x00002000) /* clear ADC14IFG13 */
\r
9115 /* ADC14CLRIFGR0[CLRADC14IFG14] Bits */
\r
9116 #define CLRADC14IFG14_OFS (14) /* CLRADC14IFG14 Offset */
\r
9117 #define CLRADC14IFG14 (0x00004000) /* clear ADC14IFG14 */
\r
9118 /* ADC14CLRIFGR0[CLRADC14IFG15] Bits */
\r
9119 #define CLRADC14IFG15_OFS (15) /* CLRADC14IFG15 Offset */
\r
9120 #define CLRADC14IFG15 (0x00008000) /* clear ADC14IFG15 */
\r
9121 /* ADC14CLRIFGR0[CLRADC14IFG16] Bits */
\r
9122 #define CLRADC14IFG16_OFS (16) /* CLRADC14IFG16 Offset */
\r
9123 #define CLRADC14IFG16 (0x00010000) /* clear ADC14IFG16 */
\r
9124 /* ADC14CLRIFGR0[CLRADC14IFG17] Bits */
\r
9125 #define CLRADC14IFG17_OFS (17) /* CLRADC14IFG17 Offset */
\r
9126 #define CLRADC14IFG17 (0x00020000) /* clear ADC14IFG17 */
\r
9127 /* ADC14CLRIFGR0[CLRADC14IFG18] Bits */
\r
9128 #define CLRADC14IFG18_OFS (18) /* CLRADC14IFG18 Offset */
\r
9129 #define CLRADC14IFG18 (0x00040000) /* clear ADC14IFG18 */
\r
9130 /* ADC14CLRIFGR0[CLRADC14IFG19] Bits */
\r
9131 #define CLRADC14IFG19_OFS (19) /* CLRADC14IFG19 Offset */
\r
9132 #define CLRADC14IFG19 (0x00080000) /* clear ADC14IFG19 */
\r
9133 /* ADC14CLRIFGR0[CLRADC14IFG20] Bits */
\r
9134 #define CLRADC14IFG20_OFS (20) /* CLRADC14IFG20 Offset */
\r
9135 #define CLRADC14IFG20 (0x00100000) /* clear ADC14IFG20 */
\r
9136 /* ADC14CLRIFGR0[CLRADC14IFG21] Bits */
\r
9137 #define CLRADC14IFG21_OFS (21) /* CLRADC14IFG21 Offset */
\r
9138 #define CLRADC14IFG21 (0x00200000) /* clear ADC14IFG21 */
\r
9139 /* ADC14CLRIFGR0[CLRADC14IFG22] Bits */
\r
9140 #define CLRADC14IFG22_OFS (22) /* CLRADC14IFG22 Offset */
\r
9141 #define CLRADC14IFG22 (0x00400000) /* clear ADC14IFG22 */
\r
9142 /* ADC14CLRIFGR0[CLRADC14IFG23] Bits */
\r
9143 #define CLRADC14IFG23_OFS (23) /* CLRADC14IFG23 Offset */
\r
9144 #define CLRADC14IFG23 (0x00800000) /* clear ADC14IFG23 */
\r
9145 /* ADC14CLRIFGR0[CLRADC14IFG24] Bits */
\r
9146 #define CLRADC14IFG24_OFS (24) /* CLRADC14IFG24 Offset */
\r
9147 #define CLRADC14IFG24 (0x01000000) /* clear ADC14IFG24 */
\r
9148 /* ADC14CLRIFGR0[CLRADC14IFG25] Bits */
\r
9149 #define CLRADC14IFG25_OFS (25) /* CLRADC14IFG25 Offset */
\r
9150 #define CLRADC14IFG25 (0x02000000) /* clear ADC14IFG25 */
\r
9151 /* ADC14CLRIFGR0[CLRADC14IFG26] Bits */
\r
9152 #define CLRADC14IFG26_OFS (26) /* CLRADC14IFG26 Offset */
\r
9153 #define CLRADC14IFG26 (0x04000000) /* clear ADC14IFG26 */
\r
9154 /* ADC14CLRIFGR0[CLRADC14IFG27] Bits */
\r
9155 #define CLRADC14IFG27_OFS (27) /* CLRADC14IFG27 Offset */
\r
9156 #define CLRADC14IFG27 (0x08000000) /* clear ADC14IFG27 */
\r
9157 /* ADC14CLRIFGR0[CLRADC14IFG28] Bits */
\r
9158 #define CLRADC14IFG28_OFS (28) /* CLRADC14IFG28 Offset */
\r
9159 #define CLRADC14IFG28 (0x10000000) /* clear ADC14IFG28 */
\r
9160 /* ADC14CLRIFGR0[CLRADC14IFG29] Bits */
\r
9161 #define CLRADC14IFG29_OFS (29) /* CLRADC14IFG29 Offset */
\r
9162 #define CLRADC14IFG29 (0x20000000) /* clear ADC14IFG29 */
\r
9163 /* ADC14CLRIFGR0[CLRADC14IFG30] Bits */
\r
9164 #define CLRADC14IFG30_OFS (30) /* CLRADC14IFG30 Offset */
\r
9165 #define CLRADC14IFG30 (0x40000000) /* clear ADC14IFG30 */
\r
9166 /* ADC14CLRIFGR0[CLRADC14IFG31] Bits */
\r
9167 #define CLRADC14IFG31_OFS (31) /* CLRADC14IFG31 Offset */
\r
9168 #define CLRADC14IFG31 (0x80000000) /* clear ADC14IFG31 */
\r
9169 /* ADC14CLRIFGR1[CLRADC14INIFG] Bits */
\r
9170 #define CLRADC14INIFG_OFS ( 1) /* CLRADC14INIFG Offset */
\r
9171 #define CLRADC14INIFG (0x00000002) /* clear ADC14INIFG */
\r
9172 /* ADC14CLRIFGR1[CLRADC14LOIFG] Bits */
\r
9173 #define CLRADC14LOIFG_OFS ( 2) /* CLRADC14LOIFG Offset */
\r
9174 #define CLRADC14LOIFG (0x00000004) /* clear ADC14LOIFG */
\r
9175 /* ADC14CLRIFGR1[CLRADC14HIIFG] Bits */
\r
9176 #define CLRADC14HIIFG_OFS ( 3) /* CLRADC14HIIFG Offset */
\r
9177 #define CLRADC14HIIFG (0x00000008) /* clear ADC14HIIFG */
\r
9178 /* ADC14CLRIFGR1[CLRADC14OVIFG] Bits */
\r
9179 #define CLRADC14OVIFG_OFS ( 4) /* CLRADC14OVIFG Offset */
\r
9180 #define CLRADC14OVIFG (0x00000010) /* clear ADC14OVIFG */
\r
9181 /* ADC14CLRIFGR1[CLRADC14TOVIFG] Bits */
\r
9182 #define CLRADC14TOVIFG_OFS ( 5) /* CLRADC14TOVIFG Offset */
\r
9183 #define CLRADC14TOVIFG (0x00000020) /* clear ADC14TOVIFG */
\r
9184 /* ADC14CLRIFGR1[CLRADC14RDYIFG] Bits */
\r
9185 #define CLRADC14RDYIFG_OFS ( 6) /* CLRADC14RDYIFG Offset */
\r
9186 #define CLRADC14RDYIFG (0x00000040) /* clear ADC14RDYIFG */
\r
9189 //*****************************************************************************
\r
9191 //*****************************************************************************
\r
9192 /* AESACTL0[AESOP] Bits */
\r
9193 #define AESOP0 (0x0001) /* AESOP Bit 0 */
\r
9194 #define AESOP1 (0x0002) /* AESOP Bit 1 */
\r
9195 /* AESACTL0[AESOP] Bits */
\r
9196 #define AESOP_OFS ( 0) /* AESOPx Offset */
\r
9197 #define AESOP_M (0x0003) /* AES operation */
\r
9198 //#define AESOP0 (0x0001) /* AES operation */
\r
9199 //#define AESOP1 (0x0002) /* AES operation */
\r
9200 #define AESOP_0 (0x0000) /* Encryption */
\r
9201 #define AESOP_1 (0x0001) /* Decryption. The provided key is the same key used for encryption */
\r
9202 #define AESOP_2 (0x0002) /* Generate first round key required for decryption */
\r
9203 #define AESOP_3 (0x0003) /* Decryption. The provided key is the first round key required for decryption */
\r
9204 /* AESACTL0[AESKL] Bits */
\r
9205 #define AESKL0 (0x0004) /* AESKL Bit 0 */
\r
9206 #define AESKL1 (0x0008) /* AESKL Bit 1 */
\r
9207 /* AESACTL0[AESKL] Bits */
\r
9208 #define AESKL_OFS ( 2) /* AESKLx Offset */
\r
9209 #define AESKL_M (0x000c) /* AES key length */
\r
9210 //#define AESKL0 (0x0004) /* AES key length */
\r
9211 //#define AESKL1 (0x0008) /* AES key length */
\r
9212 #define AESKL_0 (0x0000) /* AES128. The key size is 128 bit */
\r
9213 #define AESKL_1 (0x0004) /* AES192. The key size is 192 bit. */
\r
9214 #define AESKL_2 (0x0008) /* AES256. The key size is 256 bit */
\r
9215 #define AESKL__128BIT (0x0000) /* AES128. The key size is 128 bit */
\r
9216 #define AESKL__192BIT (0x0004) /* AES192. The key size is 192 bit. */
\r
9217 #define AESKL__256BIT (0x0008) /* AES256. The key size is 256 bit */
\r
9218 /* AESACTL0[AESCM] Bits */
\r
9219 #define AESCM0 (0x0020) /* AESCM Bit 0 */
\r
9220 #define AESCM1 (0x0040) /* AESCM Bit 1 */
\r
9221 /* AESACTL0[AESCM] Bits */
\r
9222 #define AESCM_OFS ( 5) /* AESCMx Offset */
\r
9223 #define AESCM_M (0x0060) /* AES cipher mode select */
\r
9224 //#define AESCM0 (0x0020) /* AES cipher mode select */
\r
9225 //#define AESCM1 (0x0040) /* AES cipher mode select */
\r
9226 #define AESCM_0 (0x0000) /* ECB */
\r
9227 #define AESCM_1 (0x0020) /* CBC */
\r
9228 #define AESCM_2 (0x0040) /* OFB */
\r
9229 #define AESCM_3 (0x0060) /* CFB */
\r
9230 #define AESCM__ECB (0x0000) /* ECB */
\r
9231 #define AESCM__CBC (0x0020) /* CBC */
\r
9232 #define AESCM__OFB (0x0040) /* OFB */
\r
9233 #define AESCM__CFB (0x0060) /* CFB */
\r
9234 /* AESACTL0[AESSWRST] Bits */
\r
9235 #define AESSWRST_OFS ( 7) /* AESSWRST Offset */
\r
9236 #define AESSWRST (0x0080) /* AES software reset */
\r
9237 /* AESACTL0[AESRDYIFG] Bits */
\r
9238 #define AESRDYIFG_OFS ( 8) /* AESRDYIFG Offset */
\r
9239 #define AESRDYIFG (0x0100) /* AES ready interrupt flag */
\r
9240 /* AESACTL0[AESERRFG] Bits */
\r
9241 #define AESERRFG_OFS (11) /* AESERRFG Offset */
\r
9242 #define AESERRFG (0x0800) /* AES error flag */
\r
9243 /* AESACTL0[AESRDYIE] Bits */
\r
9244 #define AESRDYIE_OFS (12) /* AESRDYIE Offset */
\r
9245 #define AESRDYIE (0x1000) /* AES ready interrupt enable */
\r
9246 /* AESACTL0[AESCMEN] Bits */
\r
9247 #define AESCMEN_OFS (15) /* AESCMEN Offset */
\r
9248 #define AESCMEN (0x8000) /* AES cipher mode enable */
\r
9249 /* AESACTL1[AESBLKCNT] Bits */
\r
9250 #define AESBLKCNT0 (0x0001) /* AESBLKCNT Bit 0 */
\r
9251 #define AESBLKCNT1 (0x0002) /* AESBLKCNT Bit 1 */
\r
9252 #define AESBLKCNT2 (0x0004) /* AESBLKCNT Bit 2 */
\r
9253 #define AESBLKCNT3 (0x0008) /* AESBLKCNT Bit 3 */
\r
9254 #define AESBLKCNT4 (0x0010) /* AESBLKCNT Bit 4 */
\r
9255 #define AESBLKCNT5 (0x0020) /* AESBLKCNT Bit 5 */
\r
9256 #define AESBLKCNT6 (0x0040) /* AESBLKCNT Bit 6 */
\r
9257 #define AESBLKCNT7 (0x0080) /* AESBLKCNT Bit 7 */
\r
9258 /* AESACTL1[AESBLKCNT] Bits */
\r
9259 #define AESBLKCNT_OFS ( 0) /* AESBLKCNTx Offset */
\r
9260 #define AESBLKCNT_M (0x00ff) /* Cipher Block Counter */
\r
9261 /* AESASTAT[AESBUSY] Bits */
\r
9262 #define AESBUSY_OFS ( 0) /* AESBUSY Offset */
\r
9263 #define AESBUSY (0x0001) /* AES accelerator module busy */
\r
9264 /* AESASTAT[AESKEYWR] Bits */
\r
9265 #define AESKEYWR_OFS ( 1) /* AESKEYWR Offset */
\r
9266 #define AESKEYWR (0x0002) /* All 16 bytes written to AESAKEY */
\r
9267 /* AESASTAT[AESDINWR] Bits */
\r
9268 #define AESDINWR_OFS ( 2) /* AESDINWR Offset */
\r
9269 #define AESDINWR (0x0004) /* All 16 bytes written to AESADIN, AESAXDIN or AESAXIN */
\r
9270 /* AESASTAT[AESDOUTRD] Bits */
\r
9271 #define AESDOUTRD_OFS ( 3) /* AESDOUTRD Offset */
\r
9272 #define AESDOUTRD (0x0008) /* All 16 bytes read from AESADOUT */
\r
9273 /* AESASTAT[AESKEYCNT] Bits */
\r
9274 #define AESKEYCNT0 (0x0010) /* AESKEYCNT Bit 0 */
\r
9275 #define AESKEYCNT1 (0x0020) /* AESKEYCNT Bit 1 */
\r
9276 #define AESKEYCNT2 (0x0040) /* AESKEYCNT Bit 2 */
\r
9277 #define AESKEYCNT3 (0x0080) /* AESKEYCNT Bit 3 */
\r
9278 /* AESASTAT[AESKEYCNT] Bits */
\r
9279 #define AESKEYCNT_OFS ( 4) /* AESKEYCNTx Offset */
\r
9280 #define AESKEYCNT_M (0x00f0) /* Bytes written via AESAKEY for AESKLx=00, half-words written via AESAKEY */
\r
9281 /* AESASTAT[AESDINCNT] Bits */
\r
9282 #define AESDINCNT0 (0x0100) /* AESDINCNT Bit 0 */
\r
9283 #define AESDINCNT1 (0x0200) /* AESDINCNT Bit 1 */
\r
9284 #define AESDINCNT2 (0x0400) /* AESDINCNT Bit 2 */
\r
9285 #define AESDINCNT3 (0x0800) /* AESDINCNT Bit 3 */
\r
9286 /* AESASTAT[AESDINCNT] Bits */
\r
9287 #define AESDINCNT_OFS ( 8) /* AESDINCNTx Offset */
\r
9288 #define AESDINCNT_M (0x0f00) /* Bytes written via AESADIN, AESAXDIN or AESAXIN */
\r
9289 /* AESASTAT[AESDOUTCNT] Bits */
\r
9290 #define AESDOUTCNT0 (0x1000) /* AESDOUTCNT Bit 0 */
\r
9291 #define AESDOUTCNT1 (0x2000) /* AESDOUTCNT Bit 1 */
\r
9292 #define AESDOUTCNT2 (0x4000) /* AESDOUTCNT Bit 2 */
\r
9293 #define AESDOUTCNT3 (0x8000) /* AESDOUTCNT Bit 3 */
\r
9294 /* AESASTAT[AESDOUTCNT] Bits */
\r
9295 #define AESDOUTCNT_OFS (12) /* AESDOUTCNTx Offset */
\r
9296 #define AESDOUTCNT_M (0xf000) /* Bytes read via AESADOUT */
\r
9297 /* AESAKEY[AESKEY0] Bits */
\r
9298 #define AESKEY00 (0x0001) /* AESKEY0 Bit 0 */
\r
9299 #define AESKEY01 (0x0002) /* AESKEY0 Bit 1 */
\r
9300 #define AESKEY02 (0x0004) /* AESKEY0 Bit 2 */
\r
9301 #define AESKEY03 (0x0008) /* AESKEY0 Bit 3 */
\r
9302 #define AESKEY04 (0x0010) /* AESKEY0 Bit 4 */
\r
9303 #define AESKEY05 (0x0020) /* AESKEY0 Bit 5 */
\r
9304 #define AESKEY06 (0x0040) /* AESKEY0 Bit 6 */
\r
9305 #define AESKEY07 (0x0080) /* AESKEY0 Bit 7 */
\r
9306 /* AESAKEY[AESKEY0] Bits */
\r
9307 #define AESKEY0_OFS ( 0) /* AESKEY0x Offset */
\r
9308 #define AESKEY0_M (0x00ff) /* AES key byte n when AESAKEY is written as half-word */
\r
9309 /* AESAKEY[AESKEY1] Bits */
\r
9310 #define AESKEY10 (0x0100) /* AESKEY1 Bit 0 */
\r
9311 #define AESKEY11 (0x0200) /* AESKEY1 Bit 1 */
\r
9312 #define AESKEY12 (0x0400) /* AESKEY1 Bit 2 */
\r
9313 #define AESKEY13 (0x0800) /* AESKEY1 Bit 3 */
\r
9314 #define AESKEY14 (0x1000) /* AESKEY1 Bit 4 */
\r
9315 #define AESKEY15 (0x2000) /* AESKEY1 Bit 5 */
\r
9316 #define AESKEY16 (0x4000) /* AESKEY1 Bit 6 */
\r
9317 #define AESKEY17 (0x8000) /* AESKEY1 Bit 7 */
\r
9318 /* AESAKEY[AESKEY1] Bits */
\r
9319 #define AESKEY1_OFS ( 8) /* AESKEY1x Offset */
\r
9320 #define AESKEY1_M (0xff00) /* AES key byte n+1 when AESAKEY is written as half-word */
\r
9321 /* AESADIN[AESDIN0] Bits */
\r
9322 #define AESDIN00 (0x0001) /* AESDIN0 Bit 0 */
\r
9323 #define AESDIN01 (0x0002) /* AESDIN0 Bit 1 */
\r
9324 #define AESDIN02 (0x0004) /* AESDIN0 Bit 2 */
\r
9325 #define AESDIN03 (0x0008) /* AESDIN0 Bit 3 */
\r
9326 #define AESDIN04 (0x0010) /* AESDIN0 Bit 4 */
\r
9327 #define AESDIN05 (0x0020) /* AESDIN0 Bit 5 */
\r
9328 #define AESDIN06 (0x0040) /* AESDIN0 Bit 6 */
\r
9329 #define AESDIN07 (0x0080) /* AESDIN0 Bit 7 */
\r
9330 /* AESADIN[AESDIN0] Bits */
\r
9331 #define AESDIN0_OFS ( 0) /* AESDIN0x Offset */
\r
9332 #define AESDIN0_M (0x00ff) /* AES data in byte n when AESADIN is written as half-word */
\r
9333 /* AESADIN[AESDIN1] Bits */
\r
9334 #define AESDIN10 (0x0100) /* AESDIN1 Bit 0 */
\r
9335 #define AESDIN11 (0x0200) /* AESDIN1 Bit 1 */
\r
9336 #define AESDIN12 (0x0400) /* AESDIN1 Bit 2 */
\r
9337 #define AESDIN13 (0x0800) /* AESDIN1 Bit 3 */
\r
9338 #define AESDIN14 (0x1000) /* AESDIN1 Bit 4 */
\r
9339 #define AESDIN15 (0x2000) /* AESDIN1 Bit 5 */
\r
9340 #define AESDIN16 (0x4000) /* AESDIN1 Bit 6 */
\r
9341 #define AESDIN17 (0x8000) /* AESDIN1 Bit 7 */
\r
9342 /* AESADIN[AESDIN1] Bits */
\r
9343 #define AESDIN1_OFS ( 8) /* AESDIN1x Offset */
\r
9344 #define AESDIN1_M (0xff00) /* AES data in byte n+1 when AESADIN is written as half-word */
\r
9345 /* AESADOUT[AESDOUT0] Bits */
\r
9346 #define AESDOUT00 (0x0001) /* AESDOUT0 Bit 0 */
\r
9347 #define AESDOUT01 (0x0002) /* AESDOUT0 Bit 1 */
\r
9348 #define AESDOUT02 (0x0004) /* AESDOUT0 Bit 2 */
\r
9349 #define AESDOUT03 (0x0008) /* AESDOUT0 Bit 3 */
\r
9350 #define AESDOUT04 (0x0010) /* AESDOUT0 Bit 4 */
\r
9351 #define AESDOUT05 (0x0020) /* AESDOUT0 Bit 5 */
\r
9352 #define AESDOUT06 (0x0040) /* AESDOUT0 Bit 6 */
\r
9353 #define AESDOUT07 (0x0080) /* AESDOUT0 Bit 7 */
\r
9354 /* AESADOUT[AESDOUT0] Bits */
\r
9355 #define AESDOUT0_OFS ( 0) /* AESDOUT0x Offset */
\r
9356 #define AESDOUT0_M (0x00ff) /* AES data out byte n when AESADOUT is read as half-word */
\r
9357 /* AESADOUT[AESDOUT1] Bits */
\r
9358 #define AESDOUT10 (0x0100) /* AESDOUT1 Bit 0 */
\r
9359 #define AESDOUT11 (0x0200) /* AESDOUT1 Bit 1 */
\r
9360 #define AESDOUT12 (0x0400) /* AESDOUT1 Bit 2 */
\r
9361 #define AESDOUT13 (0x0800) /* AESDOUT1 Bit 3 */
\r
9362 #define AESDOUT14 (0x1000) /* AESDOUT1 Bit 4 */
\r
9363 #define AESDOUT15 (0x2000) /* AESDOUT1 Bit 5 */
\r
9364 #define AESDOUT16 (0x4000) /* AESDOUT1 Bit 6 */
\r
9365 #define AESDOUT17 (0x8000) /* AESDOUT1 Bit 7 */
\r
9366 /* AESADOUT[AESDOUT1] Bits */
\r
9367 #define AESDOUT1_OFS ( 8) /* AESDOUT1x Offset */
\r
9368 #define AESDOUT1_M (0xff00) /* AES data out byte n+1 when AESADOUT is read as half-word */
\r
9369 /* AESAXDIN[AESXDIN0] Bits */
\r
9370 #define AESXDIN00 (0x0001) /* AESXDIN0 Bit 0 */
\r
9371 #define AESXDIN01 (0x0002) /* AESXDIN0 Bit 1 */
\r
9372 #define AESXDIN02 (0x0004) /* AESXDIN0 Bit 2 */
\r
9373 #define AESXDIN03 (0x0008) /* AESXDIN0 Bit 3 */
\r
9374 #define AESXDIN04 (0x0010) /* AESXDIN0 Bit 4 */
\r
9375 #define AESXDIN05 (0x0020) /* AESXDIN0 Bit 5 */
\r
9376 #define AESXDIN06 (0x0040) /* AESXDIN0 Bit 6 */
\r
9377 #define AESXDIN07 (0x0080) /* AESXDIN0 Bit 7 */
\r
9378 /* AESAXDIN[AESXDIN0] Bits */
\r
9379 #define AESXDIN0_OFS ( 0) /* AESXDIN0x Offset */
\r
9380 #define AESXDIN0_M (0x00ff) /* AES data in byte n when AESAXDIN is written as half-word */
\r
9381 /* AESAXDIN[AESXDIN1] Bits */
\r
9382 #define AESXDIN10 (0x0100) /* AESXDIN1 Bit 0 */
\r
9383 #define AESXDIN11 (0x0200) /* AESXDIN1 Bit 1 */
\r
9384 #define AESXDIN12 (0x0400) /* AESXDIN1 Bit 2 */
\r
9385 #define AESXDIN13 (0x0800) /* AESXDIN1 Bit 3 */
\r
9386 #define AESXDIN14 (0x1000) /* AESXDIN1 Bit 4 */
\r
9387 #define AESXDIN15 (0x2000) /* AESXDIN1 Bit 5 */
\r
9388 #define AESXDIN16 (0x4000) /* AESXDIN1 Bit 6 */
\r
9389 #define AESXDIN17 (0x8000) /* AESXDIN1 Bit 7 */
\r
9390 /* AESAXDIN[AESXDIN1] Bits */
\r
9391 #define AESXDIN1_OFS ( 8) /* AESXDIN1x Offset */
\r
9392 #define AESXDIN1_M (0xff00) /* AES data in byte n+1 when AESAXDIN is written as half-word */
\r
9393 /* AESAXIN[AESXIN0] Bits */
\r
9394 #define AESXIN00 (0x0001) /* AESXIN0 Bit 0 */
\r
9395 #define AESXIN01 (0x0002) /* AESXIN0 Bit 1 */
\r
9396 #define AESXIN02 (0x0004) /* AESXIN0 Bit 2 */
\r
9397 #define AESXIN03 (0x0008) /* AESXIN0 Bit 3 */
\r
9398 #define AESXIN04 (0x0010) /* AESXIN0 Bit 4 */
\r
9399 #define AESXIN05 (0x0020) /* AESXIN0 Bit 5 */
\r
9400 #define AESXIN06 (0x0040) /* AESXIN0 Bit 6 */
\r
9401 #define AESXIN07 (0x0080) /* AESXIN0 Bit 7 */
\r
9402 /* AESAXIN[AESXIN0] Bits */
\r
9403 #define AESXIN0_OFS ( 0) /* AESXIN0x Offset */
\r
9404 #define AESXIN0_M (0x00ff) /* AES data in byte n when AESAXIN is written as half-word */
\r
9405 /* AESAXIN[AESXIN1] Bits */
\r
9406 #define AESXIN10 (0x0100) /* AESXIN1 Bit 0 */
\r
9407 #define AESXIN11 (0x0200) /* AESXIN1 Bit 1 */
\r
9408 #define AESXIN12 (0x0400) /* AESXIN1 Bit 2 */
\r
9409 #define AESXIN13 (0x0800) /* AESXIN1 Bit 3 */
\r
9410 #define AESXIN14 (0x1000) /* AESXIN1 Bit 4 */
\r
9411 #define AESXIN15 (0x2000) /* AESXIN1 Bit 5 */
\r
9412 #define AESXIN16 (0x4000) /* AESXIN1 Bit 6 */
\r
9413 #define AESXIN17 (0x8000) /* AESXIN1 Bit 7 */
\r
9414 /* AESAXIN[AESXIN1] Bits */
\r
9415 #define AESXIN1_OFS ( 8) /* AESXIN1x Offset */
\r
9416 #define AESXIN1_M (0xff00) /* AES data in byte n+1 when AESAXIN is written as half-word */
\r
9419 //*****************************************************************************
\r
9421 //*****************************************************************************
\r
9422 /* CAPTIO0CTL[CAPTIOPISEL] Bits */
\r
9423 #define CAPTIOPISEL0 (0x0002) /* CAPTIOPISEL Bit 0 */
\r
9424 #define CAPTIOPISEL1 (0x0004) /* CAPTIOPISEL Bit 1 */
\r
9425 #define CAPTIOPISEL2 (0x0008) /* CAPTIOPISEL Bit 2 */
\r
9426 /* CAPTIO0CTL[CAPTIOPISEL] Bits */
\r
9427 #define CAPTIOPISEL_OFS ( 1) /* CAPTIOPISELx Offset */
\r
9428 #define CAPTIOPISEL_M (0x000e) /* Capacitive Touch IO pin select */
\r
9429 //#define CAPTIOPISEL0 (0x0002) /* Capacitive Touch IO pin select */
\r
9430 //#define CAPTIOPISEL1 (0x0004) /* Capacitive Touch IO pin select */
\r
9431 //#define CAPTIOPISEL2 (0x0008) /* Capacitive Touch IO pin select */
\r
9432 #define CAPTIOPISEL_0 (0x0000) /* Px.0 */
\r
9433 #define CAPTIOPISEL_1 (0x0002) /* Px.1 */
\r
9434 #define CAPTIOPISEL_2 (0x0004) /* Px.2 */
\r
9435 #define CAPTIOPISEL_3 (0x0006) /* Px.3 */
\r
9436 #define CAPTIOPISEL_4 (0x0008) /* Px.4 */
\r
9437 #define CAPTIOPISEL_5 (0x000a) /* Px.5 */
\r
9438 #define CAPTIOPISEL_6 (0x000c) /* Px.6 */
\r
9439 #define CAPTIOPISEL_7 (0x000e) /* Px.7 */
\r
9440 /* CAPTIO0CTL[CAPTIOPOSEL] Bits */
\r
9441 #define CAPTIOPOSEL0 (0x0010) /* CAPTIOPOSEL Bit 0 */
\r
9442 #define CAPTIOPOSEL1 (0x0020) /* CAPTIOPOSEL Bit 1 */
\r
9443 #define CAPTIOPOSEL2 (0x0040) /* CAPTIOPOSEL Bit 2 */
\r
9444 #define CAPTIOPOSEL3 (0x0080) /* CAPTIOPOSEL Bit 3 */
\r
9445 /* CAPTIO0CTL[CAPTIOPOSEL] Bits */
\r
9446 #define CAPTIOPOSEL_OFS ( 4) /* CAPTIOPOSELx Offset */
\r
9447 #define CAPTIOPOSEL_M (0x00f0) /* Capacitive Touch IO port select */
\r
9448 //#define CAPTIOPOSEL0 (0x0010) /* Capacitive Touch IO port select */
\r
9449 //#define CAPTIOPOSEL1 (0x0020) /* Capacitive Touch IO port select */
\r
9450 //#define CAPTIOPOSEL2 (0x0040) /* Capacitive Touch IO port select */
\r
9451 //#define CAPTIOPOSEL3 (0x0080) /* Capacitive Touch IO port select */
\r
9452 #define CAPTIOPOSEL_0 (0x0000) /* Px = PJ */
\r
9453 #define CAPTIOPOSEL_1 (0x0010) /* Px = P1 */
\r
9454 #define CAPTIOPOSEL_2 (0x0020) /* Px = P2 */
\r
9455 #define CAPTIOPOSEL_3 (0x0030) /* Px = P3 */
\r
9456 #define CAPTIOPOSEL_4 (0x0040) /* Px = P4 */
\r
9457 #define CAPTIOPOSEL_5 (0x0050) /* Px = P5 */
\r
9458 #define CAPTIOPOSEL_6 (0x0060) /* Px = P6 */
\r
9459 #define CAPTIOPOSEL_7 (0x0070) /* Px = P7 */
\r
9460 #define CAPTIOPOSEL_8 (0x0080) /* Px = P8 */
\r
9461 #define CAPTIOPOSEL_9 (0x0090) /* Px = P9 */
\r
9462 #define CAPTIOPOSEL_10 (0x00a0) /* Px = P10 */
\r
9463 #define CAPTIOPOSEL_11 (0x00b0) /* Px = P11 */
\r
9464 #define CAPTIOPOSEL_12 (0x00c0) /* Px = P12 */
\r
9465 #define CAPTIOPOSEL_13 (0x00d0) /* Px = P13 */
\r
9466 #define CAPTIOPOSEL_14 (0x00e0) /* Px = P14 */
\r
9467 #define CAPTIOPOSEL_15 (0x00f0) /* Px = P15 */
\r
9468 #define CAPTIOPOSEL__PJ (0x0000) /* Px = PJ */
\r
9469 #define CAPTIOPOSEL__P1 (0x0010) /* Px = P1 */
\r
9470 #define CAPTIOPOSEL__P2 (0x0020) /* Px = P2 */
\r
9471 #define CAPTIOPOSEL__P3 (0x0030) /* Px = P3 */
\r
9472 #define CAPTIOPOSEL__P4 (0x0040) /* Px = P4 */
\r
9473 #define CAPTIOPOSEL__P5 (0x0050) /* Px = P5 */
\r
9474 #define CAPTIOPOSEL__P6 (0x0060) /* Px = P6 */
\r
9475 #define CAPTIOPOSEL__P7 (0x0070) /* Px = P7 */
\r
9476 #define CAPTIOPOSEL__P8 (0x0080) /* Px = P8 */
\r
9477 #define CAPTIOPOSEL__P9 (0x0090) /* Px = P9 */
\r
9478 #define CAPTIOPOSEL__P10 (0x00a0) /* Px = P10 */
\r
9479 #define CAPTIOPOSEL__P11 (0x00b0) /* Px = P11 */
\r
9480 #define CAPTIOPOSEL__P12 (0x00c0) /* Px = P12 */
\r
9481 #define CAPTIOPOSEL__P13 (0x00d0) /* Px = P13 */
\r
9482 #define CAPTIOPOSEL__P14 (0x00e0) /* Px = P14 */
\r
9483 #define CAPTIOPOSEL__P15 (0x00f0) /* Px = P15 */
\r
9484 /* CAPTIO0CTL[CAPTIOEN] Bits */
\r
9485 #define CAPTIOEN_OFS ( 8) /* CAPTIOEN Offset */
\r
9486 #define CAPTIOEN (0x0100) /* Capacitive Touch IO enable */
\r
9487 /* CAPTIO0CTL[CAPTIOSTATE] Bits */
\r
9488 #define CAPTIOSTATE_OFS ( 9) /* CAPTIOSTATE Offset */
\r
9489 #define CAPTIOSTATE (0x0200) /* Capacitive Touch IO state */
\r
9492 //*****************************************************************************
\r
9494 //*****************************************************************************
\r
9495 /* CAPTIO1CTL[CAPTIOPISEL] Bits */
\r
9496 //#define CAPTIOPISEL0 (0x0002) /* CAPTIOPISEL Bit 0 */
\r
9497 //#define CAPTIOPISEL1 (0x0004) /* CAPTIOPISEL Bit 1 */
\r
9498 //#define CAPTIOPISEL2 (0x0008) /* CAPTIOPISEL Bit 2 */
\r
9499 /* CAPTIO1CTL[CAPTIOPISEL] Bits */
\r
9500 //#define CAPTIOPISEL_OFS ( 1) /* CAPTIOPISELx Offset */
\r
9501 //#define CAPTIOPISEL_M (0x000e) /* Capacitive Touch IO pin select */
\r
9502 //#define CAPTIOPISEL0 (0x0002) /* Capacitive Touch IO pin select */
\r
9503 //#define CAPTIOPISEL1 (0x0004) /* Capacitive Touch IO pin select */
\r
9504 //#define CAPTIOPISEL2 (0x0008) /* Capacitive Touch IO pin select */
\r
9505 //#define CAPTIOPISEL_0 (0x0000) /* Px.0 */
\r
9506 //#define CAPTIOPISEL_1 (0x0002) /* Px.1 */
\r
9507 //#define CAPTIOPISEL_2 (0x0004) /* Px.2 */
\r
9508 //#define CAPTIOPISEL_3 (0x0006) /* Px.3 */
\r
9509 //#define CAPTIOPISEL_4 (0x0008) /* Px.4 */
\r
9510 //#define CAPTIOPISEL_5 (0x000a) /* Px.5 */
\r
9511 //#define CAPTIOPISEL_6 (0x000c) /* Px.6 */
\r
9512 //#define CAPTIOPISEL_7 (0x000e) /* Px.7 */
\r
9513 /* CAPTIO1CTL[CAPTIOPOSEL] Bits */
\r
9514 //#define CAPTIOPOSEL0 (0x0010) /* CAPTIOPOSEL Bit 0 */
\r
9515 //#define CAPTIOPOSEL1 (0x0020) /* CAPTIOPOSEL Bit 1 */
\r
9516 //#define CAPTIOPOSEL2 (0x0040) /* CAPTIOPOSEL Bit 2 */
\r
9517 //#define CAPTIOPOSEL3 (0x0080) /* CAPTIOPOSEL Bit 3 */
\r
9518 /* CAPTIO1CTL[CAPTIOPOSEL] Bits */
\r
9519 //#define CAPTIOPOSEL_OFS ( 4) /* CAPTIOPOSELx Offset */
\r
9520 //#define CAPTIOPOSEL_M (0x00f0) /* Capacitive Touch IO port select */
\r
9521 //#define CAPTIOPOSEL0 (0x0010) /* Capacitive Touch IO port select */
\r
9522 //#define CAPTIOPOSEL1 (0x0020) /* Capacitive Touch IO port select */
\r
9523 //#define CAPTIOPOSEL2 (0x0040) /* Capacitive Touch IO port select */
\r
9524 //#define CAPTIOPOSEL3 (0x0080) /* Capacitive Touch IO port select */
\r
9525 //#define CAPTIOPOSEL_0 (0x0000) /* Px = PJ */
\r
9526 //#define CAPTIOPOSEL_1 (0x0010) /* Px = P1 */
\r
9527 //#define CAPTIOPOSEL_2 (0x0020) /* Px = P2 */
\r
9528 //#define CAPTIOPOSEL_3 (0x0030) /* Px = P3 */
\r
9529 //#define CAPTIOPOSEL_4 (0x0040) /* Px = P4 */
\r
9530 //#define CAPTIOPOSEL_5 (0x0050) /* Px = P5 */
\r
9531 //#define CAPTIOPOSEL_6 (0x0060) /* Px = P6 */
\r
9532 //#define CAPTIOPOSEL_7 (0x0070) /* Px = P7 */
\r
9533 //#define CAPTIOPOSEL_8 (0x0080) /* Px = P8 */
\r
9534 //#define CAPTIOPOSEL_9 (0x0090) /* Px = P9 */
\r
9535 //#define CAPTIOPOSEL_10 (0x00a0) /* Px = P10 */
\r
9536 //#define CAPTIOPOSEL_11 (0x00b0) /* Px = P11 */
\r
9537 //#define CAPTIOPOSEL_12 (0x00c0) /* Px = P12 */
\r
9538 //#define CAPTIOPOSEL_13 (0x00d0) /* Px = P13 */
\r
9539 //#define CAPTIOPOSEL_14 (0x00e0) /* Px = P14 */
\r
9540 //#define CAPTIOPOSEL_15 (0x00f0) /* Px = P15 */
\r
9541 //#define CAPTIOPOSEL__PJ (0x0000) /* Px = PJ */
\r
9542 //#define CAPTIOPOSEL__P1 (0x0010) /* Px = P1 */
\r
9543 //#define CAPTIOPOSEL__P2 (0x0020) /* Px = P2 */
\r
9544 //#define CAPTIOPOSEL__P3 (0x0030) /* Px = P3 */
\r
9545 //#define CAPTIOPOSEL__P4 (0x0040) /* Px = P4 */
\r
9546 //#define CAPTIOPOSEL__P5 (0x0050) /* Px = P5 */
\r
9547 //#define CAPTIOPOSEL__P6 (0x0060) /* Px = P6 */
\r
9548 //#define CAPTIOPOSEL__P7 (0x0070) /* Px = P7 */
\r
9549 //#define CAPTIOPOSEL__P8 (0x0080) /* Px = P8 */
\r
9550 //#define CAPTIOPOSEL__P9 (0x0090) /* Px = P9 */
\r
9551 //#define CAPTIOPOSEL__P10 (0x00a0) /* Px = P10 */
\r
9552 //#define CAPTIOPOSEL__P11 (0x00b0) /* Px = P11 */
\r
9553 //#define CAPTIOPOSEL__P12 (0x00c0) /* Px = P12 */
\r
9554 //#define CAPTIOPOSEL__P13 (0x00d0) /* Px = P13 */
\r
9555 //#define CAPTIOPOSEL__P14 (0x00e0) /* Px = P14 */
\r
9556 //#define CAPTIOPOSEL__P15 (0x00f0) /* Px = P15 */
\r
9557 /* CAPTIO1CTL[CAPTIOEN] Bits */
\r
9558 //#define CAPTIOEN_OFS ( 8) /* CAPTIOEN Offset */
\r
9559 //#define CAPTIOEN (0x0100) /* Capacitive Touch IO enable */
\r
9560 /* CAPTIO1CTL[CAPTIOSTATE] Bits */
\r
9561 //#define CAPTIOSTATE_OFS ( 9) /* CAPTIOSTATE Offset */
\r
9562 //#define CAPTIOSTATE (0x0200) /* Capacitive Touch IO state */
\r
9565 //*****************************************************************************
\r
9567 //*****************************************************************************
\r
9568 /* CE0CTL0[CEIPSEL] Bits */
\r
9569 #define CEIPSEL_OFS ( 0) /* CEIPSEL Offset */
\r
9570 #define CEIPSEL_M (0x000f) /* Channel input selected for the V+ terminal */
\r
9571 #define CEIPSEL0 (0x0001) /* Channel input selected for the V+ terminal */
\r
9572 #define CEIPSEL1 (0x0002) /* Channel input selected for the V+ terminal */
\r
9573 #define CEIPSEL2 (0x0004) /* Channel input selected for the V+ terminal */
\r
9574 #define CEIPSEL3 (0x0008) /* Channel input selected for the V+ terminal */
\r
9575 #define CEIPSEL_0 (0x0000) /* Channel 0 selected */
\r
9576 #define CEIPSEL_1 (0x0001) /* Channel 1 selected */
\r
9577 #define CEIPSEL_2 (0x0002) /* Channel 2 selected */
\r
9578 #define CEIPSEL_3 (0x0003) /* Channel 3 selected */
\r
9579 #define CEIPSEL_4 (0x0004) /* Channel 4 selected */
\r
9580 #define CEIPSEL_5 (0x0005) /* Channel 5 selected */
\r
9581 #define CEIPSEL_6 (0x0006) /* Channel 6 selected */
\r
9582 #define CEIPSEL_7 (0x0007) /* Channel 7 selected */
\r
9583 #define CEIPSEL_8 (0x0008) /* Channel 8 selected */
\r
9584 #define CEIPSEL_9 (0x0009) /* Channel 9 selected */
\r
9585 #define CEIPSEL_10 (0x000a) /* Channel 10 selected */
\r
9586 #define CEIPSEL_11 (0x000b) /* Channel 11 selected */
\r
9587 #define CEIPSEL_12 (0x000c) /* Channel 12 selected */
\r
9588 #define CEIPSEL_13 (0x000d) /* Channel 13 selected */
\r
9589 #define CEIPSEL_14 (0x000e) /* Channel 14 selected */
\r
9590 #define CEIPSEL_15 (0x000f) /* Channel 15 selected */
\r
9591 /* CE0CTL0[CEIPEN] Bits */
\r
9592 #define CEIPEN_OFS ( 7) /* CEIPEN Offset */
\r
9593 #define CEIPEN (0x0080) /* Channel input enable for the V+ terminal */
\r
9594 /* CE0CTL0[CEIMSEL] Bits */
\r
9595 #define CEIMSEL_OFS ( 8) /* CEIMSEL Offset */
\r
9596 #define CEIMSEL_M (0x0f00) /* Channel input selected for the - terminal */
\r
9597 #define CEIMSEL0 (0x0100) /* Channel input selected for the - terminal */
\r
9598 #define CEIMSEL1 (0x0200) /* Channel input selected for the - terminal */
\r
9599 #define CEIMSEL2 (0x0400) /* Channel input selected for the - terminal */
\r
9600 #define CEIMSEL3 (0x0800) /* Channel input selected for the - terminal */
\r
9601 #define CEIMSEL_0 (0x0000) /* Channel 0 selected */
\r
9602 #define CEIMSEL_1 (0x0100) /* Channel 1 selected */
\r
9603 #define CEIMSEL_2 (0x0200) /* Channel 2 selected */
\r
9604 #define CEIMSEL_3 (0x0300) /* Channel 3 selected */
\r
9605 #define CEIMSEL_4 (0x0400) /* Channel 4 selected */
\r
9606 #define CEIMSEL_5 (0x0500) /* Channel 5 selected */
\r
9607 #define CEIMSEL_6 (0x0600) /* Channel 6 selected */
\r
9608 #define CEIMSEL_7 (0x0700) /* Channel 7 selected */
\r
9609 #define CEIMSEL_8 (0x0800) /* Channel 8 selected */
\r
9610 #define CEIMSEL_9 (0x0900) /* Channel 9 selected */
\r
9611 #define CEIMSEL_10 (0x0a00) /* Channel 10 selected */
\r
9612 #define CEIMSEL_11 (0x0b00) /* Channel 11 selected */
\r
9613 #define CEIMSEL_12 (0x0c00) /* Channel 12 selected */
\r
9614 #define CEIMSEL_13 (0x0d00) /* Channel 13 selected */
\r
9615 #define CEIMSEL_14 (0x0e00) /* Channel 14 selected */
\r
9616 #define CEIMSEL_15 (0x0f00) /* Channel 15 selected */
\r
9617 /* CE0CTL0[CEIMEN] Bits */
\r
9618 #define CEIMEN_OFS (15) /* CEIMEN Offset */
\r
9619 #define CEIMEN (0x8000) /* Channel input enable for the - terminal */
\r
9620 /* CE0CTL1[CEOUT] Bits */
\r
9621 #define CEOUT_OFS ( 0) /* CEOUT Offset */
\r
9622 #define CEOUT (0x0001) /* Comparator output value */
\r
9623 /* CE0CTL1[CEOUTPOL] Bits */
\r
9624 #define CEOUTPOL_OFS ( 1) /* CEOUTPOL Offset */
\r
9625 #define CEOUTPOL (0x0002) /* Comparator output polarity */
\r
9626 /* CE0CTL1[CEF] Bits */
\r
9627 #define CEF_OFS ( 2) /* CEF Offset */
\r
9628 #define CEF (0x0004) /* Comparator output filter */
\r
9629 /* CE0CTL1[CEIES] Bits */
\r
9630 #define CEIES_OFS ( 3) /* CEIES Offset */
\r
9631 #define CEIES (0x0008) /* Interrupt edge select for CEIIFG and CEIFG */
\r
9632 /* CE0CTL1[CESHORT] Bits */
\r
9633 #define CESHORT_OFS ( 4) /* CESHORT Offset */
\r
9634 #define CESHORT (0x0010) /* Input short */
\r
9635 /* CE0CTL1[CEEX] Bits */
\r
9636 #define CEEX_OFS ( 5) /* CEEX Offset */
\r
9637 #define CEEX (0x0020) /* Exchange */
\r
9638 /* CE0CTL1[CEFDLY] Bits */
\r
9639 #define CEFDLY_OFS ( 6) /* CEFDLY Offset */
\r
9640 #define CEFDLY_M (0x00c0) /* Filter delay */
\r
9641 #define CEFDLY0 (0x0040) /* Filter delay */
\r
9642 #define CEFDLY1 (0x0080) /* Filter delay */
\r
9643 #define CEFDLY_0 (0x0000) /* Typical filter delay of TBD (450) ns */
\r
9644 #define CEFDLY_1 (0x0040) /* Typical filter delay of TBD (900) ns */
\r
9645 #define CEFDLY_2 (0x0080) /* Typical filter delay of TBD (1800) ns */
\r
9646 #define CEFDLY_3 (0x00c0) /* Typical filter delay of TBD (3600) ns */
\r
9647 /* CE0CTL1[CEPWRMD] Bits */
\r
9648 #define CEPWRMD_OFS ( 8) /* CEPWRMD Offset */
\r
9649 #define CEPWRMD_M (0x0300) /* Power Mode */
\r
9650 #define CEPWRMD0 (0x0100) /* Power Mode */
\r
9651 #define CEPWRMD1 (0x0200) /* Power Mode */
\r
9652 #define CEPWRMD_0 (0x0000) /* High-speed mode */
\r
9653 #define CEPWRMD_1 (0x0100) /* Normal mode */
\r
9654 #define CEPWRMD_2 (0x0200) /* Ultra-low power mode */
\r
9655 /* CE0CTL1[CEON] Bits */
\r
9656 #define CEON_OFS (10) /* CEON Offset */
\r
9657 #define CEON (0x0400) /* Comparator On */
\r
9658 /* CE0CTL1[CEMRVL] Bits */
\r
9659 #define CEMRVL_OFS (11) /* CEMRVL Offset */
\r
9660 #define CEMRVL (0x0800) /* This bit is valid of CEMRVS is set to 1 */
\r
9661 /* CE0CTL1[CEMRVS] Bits */
\r
9662 #define CEMRVS_OFS (12) /* CEMRVS Offset */
\r
9663 #define CEMRVS (0x1000) /* */
\r
9664 /* CE0CTL2[CEREF0] Bits */
\r
9665 #define CEREF0_OFS ( 0) /* CEREF0 Offset */
\r
9666 #define CEREF0_M (0x001f) /* Reference resistor tap 0 */
\r
9667 /* CE0CTL2[CERSEL] Bits */
\r
9668 #define CERSEL_OFS ( 5) /* CERSEL Offset */
\r
9669 #define CERSEL (0x0020) /* Reference select */
\r
9670 /* CE0CTL2[CERS] Bits */
\r
9671 #define CERS_OFS ( 6) /* CERS Offset */
\r
9672 #define CERS_M (0x00c0) /* Reference source */
\r
9673 #define CERS0 (0x0040) /* Reference source */
\r
9674 #define CERS1 (0x0080) /* Reference source */
\r
9675 #define CERS_0 (0x0000) /* No current is drawn by the reference circuitry */
\r
9676 #define CERS_1 (0x0040) /* VCC applied to the resistor ladder */
\r
9677 #define CERS_2 (0x0080) /* Shared reference voltage applied to the resistor ladder */
\r
9678 #define CERS_3 (0x00c0) /* Shared reference voltage supplied to V(CREF). Resistor ladder is off */
\r
9679 /* CE0CTL2[CEREF1] Bits */
\r
9680 #define CEREF1_OFS ( 8) /* CEREF1 Offset */
\r
9681 #define CEREF1_M (0x1f00) /* Reference resistor tap 1 */
\r
9682 /* CE0CTL2[CEREFL] Bits */
\r
9683 #define CEREFL_OFS (13) /* CEREFL Offset */
\r
9684 #define CEREFL_M (0x6000) /* Reference voltage level */
\r
9685 #define CEREFL0 (0x2000) /* Reference voltage level */
\r
9686 #define CEREFL1 (0x4000) /* Reference voltage level */
\r
9687 #define CEREFL_0 (0x0000) /* Reference amplifier is disabled. No reference voltage is requested */
\r
9688 #define CEREFL_1 (0x2000) /* 1.2 V is selected as shared reference voltage input */
\r
9689 #define CEREFL_2 (0x4000) /* 2.0 V is selected as shared reference voltage input */
\r
9690 #define CEREFL_3 (0x6000) /* 2.5 V is selected as shared reference voltage input */
\r
9691 #define CEREFL__OFF (0x0000) /* Reference amplifier is disabled. No reference voltage is requested */
\r
9692 #define CEREFL__1P2V (0x2000) /* 1.2 V is selected as shared reference voltage input */
\r
9693 #define CEREFL__2P0V (0x4000) /* 2.0 V is selected as shared reference voltage input */
\r
9694 #define CEREFL__2P5V (0x6000) /* 2.5 V is selected as shared reference voltage input */
\r
9695 /* CE0CTL2[CEREFACC] Bits */
\r
9696 #define CEREFACC_OFS (15) /* CEREFACC Offset */
\r
9697 #define CEREFACC (0x8000) /* Reference accuracy */
\r
9698 /* CE0CTL3[CEPD0] Bits */
\r
9699 #define CEPD0_OFS ( 0) /* CEPD0 Offset */
\r
9700 #define CEPD0 (0x0001) /* Port disable */
\r
9701 /* CE0CTL3[CEPD1] Bits */
\r
9702 #define CEPD1_OFS ( 1) /* CEPD1 Offset */
\r
9703 #define CEPD1 (0x0002) /* Port disable */
\r
9704 /* CE0CTL3[CEPD2] Bits */
\r
9705 #define CEPD2_OFS ( 2) /* CEPD2 Offset */
\r
9706 #define CEPD2 (0x0004) /* Port disable */
\r
9707 /* CE0CTL3[CEPD3] Bits */
\r
9708 #define CEPD3_OFS ( 3) /* CEPD3 Offset */
\r
9709 #define CEPD3 (0x0008) /* Port disable */
\r
9710 /* CE0CTL3[CEPD4] Bits */
\r
9711 #define CEPD4_OFS ( 4) /* CEPD4 Offset */
\r
9712 #define CEPD4 (0x0010) /* Port disable */
\r
9713 /* CE0CTL3[CEPD5] Bits */
\r
9714 #define CEPD5_OFS ( 5) /* CEPD5 Offset */
\r
9715 #define CEPD5 (0x0020) /* Port disable */
\r
9716 /* CE0CTL3[CEPD6] Bits */
\r
9717 #define CEPD6_OFS ( 6) /* CEPD6 Offset */
\r
9718 #define CEPD6 (0x0040) /* Port disable */
\r
9719 /* CE0CTL3[CEPD7] Bits */
\r
9720 #define CEPD7_OFS ( 7) /* CEPD7 Offset */
\r
9721 #define CEPD7 (0x0080) /* Port disable */
\r
9722 /* CE0CTL3[CEPD8] Bits */
\r
9723 #define CEPD8_OFS ( 8) /* CEPD8 Offset */
\r
9724 #define CEPD8 (0x0100) /* Port disable */
\r
9725 /* CE0CTL3[CEPD9] Bits */
\r
9726 #define CEPD9_OFS ( 9) /* CEPD9 Offset */
\r
9727 #define CEPD9 (0x0200) /* Port disable */
\r
9728 /* CE0CTL3[CEPD10] Bits */
\r
9729 #define CEPD10_OFS (10) /* CEPD10 Offset */
\r
9730 #define CEPD10 (0x0400) /* Port disable */
\r
9731 /* CE0CTL3[CEPD11] Bits */
\r
9732 #define CEPD11_OFS (11) /* CEPD11 Offset */
\r
9733 #define CEPD11 (0x0800) /* Port disable */
\r
9734 /* CE0CTL3[CEPD12] Bits */
\r
9735 #define CEPD12_OFS (12) /* CEPD12 Offset */
\r
9736 #define CEPD12 (0x1000) /* Port disable */
\r
9737 /* CE0CTL3[CEPD13] Bits */
\r
9738 #define CEPD13_OFS (13) /* CEPD13 Offset */
\r
9739 #define CEPD13 (0x2000) /* Port disable */
\r
9740 /* CE0CTL3[CEPD14] Bits */
\r
9741 #define CEPD14_OFS (14) /* CEPD14 Offset */
\r
9742 #define CEPD14 (0x4000) /* Port disable */
\r
9743 /* CE0CTL3[CEPD15] Bits */
\r
9744 #define CEPD15_OFS (15) /* CEPD15 Offset */
\r
9745 #define CEPD15 (0x8000) /* Port disable */
\r
9746 /* CE0INT[CEIFG] Bits */
\r
9747 #define CEIFG_OFS ( 0) /* CEIFG Offset */
\r
9748 #define CEIFG (0x0001) /* Comparator output interrupt flag */
\r
9749 /* CE0INT[CEIIFG] Bits */
\r
9750 #define CEIIFG_OFS ( 1) /* CEIIFG Offset */
\r
9751 #define CEIIFG (0x0002) /* Comparator output inverted interrupt flag */
\r
9752 /* CE0INT[CERDYIFG] Bits */
\r
9753 #define CERDYIFG_OFS ( 4) /* CERDYIFG Offset */
\r
9754 #define CERDYIFG (0x0010) /* Comparator ready interrupt flag */
\r
9755 /* CE0INT[CEIE] Bits */
\r
9756 #define CEIE_OFS ( 8) /* CEIE Offset */
\r
9757 #define CEIE (0x0100) /* Comparator output interrupt enable */
\r
9758 /* CE0INT[CEIIE] Bits */
\r
9759 #define CEIIE_OFS ( 9) /* CEIIE Offset */
\r
9760 #define CEIIE (0x0200) /* Comparator output interrupt enable inverted polarity */
\r
9761 /* CE0INT[CERDYIE] Bits */
\r
9762 #define CERDYIE_OFS (12) /* CERDYIE Offset */
\r
9763 #define CERDYIE (0x1000) /* Comparator ready interrupt enable */
\r
9766 //*****************************************************************************
\r
9768 //*****************************************************************************
\r
9769 /* CE1CTL0[CEIPSEL] Bits */
\r
9770 //#define CEIPSEL_OFS ( 0) /* CEIPSEL Offset */
\r
9771 //#define CEIPSEL_M (0x000f) /* Channel input selected for the V+ terminal */
\r
9772 //#define CEIPSEL0 (0x0001) /* Channel input selected for the V+ terminal */
\r
9773 //#define CEIPSEL1 (0x0002) /* Channel input selected for the V+ terminal */
\r
9774 //#define CEIPSEL2 (0x0004) /* Channel input selected for the V+ terminal */
\r
9775 //#define CEIPSEL3 (0x0008) /* Channel input selected for the V+ terminal */
\r
9776 //#define CEIPSEL_0 (0x0000) /* Channel 0 selected */
\r
9777 //#define CEIPSEL_1 (0x0001) /* Channel 1 selected */
\r
9778 //#define CEIPSEL_2 (0x0002) /* Channel 2 selected */
\r
9779 //#define CEIPSEL_3 (0x0003) /* Channel 3 selected */
\r
9780 //#define CEIPSEL_4 (0x0004) /* Channel 4 selected */
\r
9781 //#define CEIPSEL_5 (0x0005) /* Channel 5 selected */
\r
9782 //#define CEIPSEL_6 (0x0006) /* Channel 6 selected */
\r
9783 //#define CEIPSEL_7 (0x0007) /* Channel 7 selected */
\r
9784 //#define CEIPSEL_8 (0x0008) /* Channel 8 selected */
\r
9785 //#define CEIPSEL_9 (0x0009) /* Channel 9 selected */
\r
9786 //#define CEIPSEL_10 (0x000a) /* Channel 10 selected */
\r
9787 //#define CEIPSEL_11 (0x000b) /* Channel 11 selected */
\r
9788 //#define CEIPSEL_12 (0x000c) /* Channel 12 selected */
\r
9789 //#define CEIPSEL_13 (0x000d) /* Channel 13 selected */
\r
9790 //#define CEIPSEL_14 (0x000e) /* Channel 14 selected */
\r
9791 //#define CEIPSEL_15 (0x000f) /* Channel 15 selected */
\r
9792 /* CE1CTL0[CEIPEN] Bits */
\r
9793 //#define CEIPEN_OFS ( 7) /* CEIPEN Offset */
\r
9794 //#define CEIPEN (0x0080) /* Channel input enable for the V+ terminal */
\r
9795 /* CE1CTL0[CEIMSEL] Bits */
\r
9796 //#define CEIMSEL_OFS ( 8) /* CEIMSEL Offset */
\r
9797 //#define CEIMSEL_M (0x0f00) /* Channel input selected for the - terminal */
\r
9798 //#define CEIMSEL0 (0x0100) /* Channel input selected for the - terminal */
\r
9799 //#define CEIMSEL1 (0x0200) /* Channel input selected for the - terminal */
\r
9800 //#define CEIMSEL2 (0x0400) /* Channel input selected for the - terminal */
\r
9801 //#define CEIMSEL3 (0x0800) /* Channel input selected for the - terminal */
\r
9802 //#define CEIMSEL_0 (0x0000) /* Channel 0 selected */
\r
9803 //#define CEIMSEL_1 (0x0100) /* Channel 1 selected */
\r
9804 //#define CEIMSEL_2 (0x0200) /* Channel 2 selected */
\r
9805 //#define CEIMSEL_3 (0x0300) /* Channel 3 selected */
\r
9806 //#define CEIMSEL_4 (0x0400) /* Channel 4 selected */
\r
9807 //#define CEIMSEL_5 (0x0500) /* Channel 5 selected */
\r
9808 //#define CEIMSEL_6 (0x0600) /* Channel 6 selected */
\r
9809 //#define CEIMSEL_7 (0x0700) /* Channel 7 selected */
\r
9810 //#define CEIMSEL_8 (0x0800) /* Channel 8 selected */
\r
9811 //#define CEIMSEL_9 (0x0900) /* Channel 9 selected */
\r
9812 //#define CEIMSEL_10 (0x0a00) /* Channel 10 selected */
\r
9813 //#define CEIMSEL_11 (0x0b00) /* Channel 11 selected */
\r
9814 //#define CEIMSEL_12 (0x0c00) /* Channel 12 selected */
\r
9815 //#define CEIMSEL_13 (0x0d00) /* Channel 13 selected */
\r
9816 //#define CEIMSEL_14 (0x0e00) /* Channel 14 selected */
\r
9817 //#define CEIMSEL_15 (0x0f00) /* Channel 15 selected */
\r
9818 /* CE1CTL0[CEIMEN] Bits */
\r
9819 //#define CEIMEN_OFS (15) /* CEIMEN Offset */
\r
9820 //#define CEIMEN (0x8000) /* Channel input enable for the - terminal */
\r
9821 /* CE1CTL1[CEOUT] Bits */
\r
9822 //#define CEOUT_OFS ( 0) /* CEOUT Offset */
\r
9823 //#define CEOUT (0x0001) /* Comparator output value */
\r
9824 /* CE1CTL1[CEOUTPOL] Bits */
\r
9825 //#define CEOUTPOL_OFS ( 1) /* CEOUTPOL Offset */
\r
9826 //#define CEOUTPOL (0x0002) /* Comparator output polarity */
\r
9827 /* CE1CTL1[CEF] Bits */
\r
9828 //#define CEF_OFS ( 2) /* CEF Offset */
\r
9829 //#define CEF (0x0004) /* Comparator output filter */
\r
9830 /* CE1CTL1[CEIES] Bits */
\r
9831 //#define CEIES_OFS ( 3) /* CEIES Offset */
\r
9832 //#define CEIES (0x0008) /* Interrupt edge select for CEIIFG and CEIFG */
\r
9833 /* CE1CTL1[CESHORT] Bits */
\r
9834 //#define CESHORT_OFS ( 4) /* CESHORT Offset */
\r
9835 //#define CESHORT (0x0010) /* Input short */
\r
9836 /* CE1CTL1[CEEX] Bits */
\r
9837 //#define CEEX_OFS ( 5) /* CEEX Offset */
\r
9838 //#define CEEX (0x0020) /* Exchange */
\r
9839 /* CE1CTL1[CEFDLY] Bits */
\r
9840 //#define CEFDLY_OFS ( 6) /* CEFDLY Offset */
\r
9841 //#define CEFDLY_M (0x00c0) /* Filter delay */
\r
9842 //#define CEFDLY0 (0x0040) /* Filter delay */
\r
9843 //#define CEFDLY1 (0x0080) /* Filter delay */
\r
9844 //#define CEFDLY_0 (0x0000) /* Typical filter delay of TBD (450) ns */
\r
9845 //#define CEFDLY_1 (0x0040) /* Typical filter delay of TBD (900) ns */
\r
9846 //#define CEFDLY_2 (0x0080) /* Typical filter delay of TBD (1800) ns */
\r
9847 //#define CEFDLY_3 (0x00c0) /* Typical filter delay of TBD (3600) ns */
\r
9848 /* CE1CTL1[CEPWRMD] Bits */
\r
9849 //#define CEPWRMD_OFS ( 8) /* CEPWRMD Offset */
\r
9850 //#define CEPWRMD_M (0x0300) /* Power Mode */
\r
9851 //#define CEPWRMD0 (0x0100) /* Power Mode */
\r
9852 //#define CEPWRMD1 (0x0200) /* Power Mode */
\r
9853 //#define CEPWRMD_0 (0x0000) /* High-speed mode */
\r
9854 //#define CEPWRMD_1 (0x0100) /* Normal mode */
\r
9855 //#define CEPWRMD_2 (0x0200) /* Ultra-low power mode */
\r
9856 /* CE1CTL1[CEON] Bits */
\r
9857 //#define CEON_OFS (10) /* CEON Offset */
\r
9858 //#define CEON (0x0400) /* Comparator On */
\r
9859 /* CE1CTL1[CEMRVL] Bits */
\r
9860 //#define CEMRVL_OFS (11) /* CEMRVL Offset */
\r
9861 //#define CEMRVL (0x0800) /* This bit is valid of CEMRVS is set to 1 */
\r
9862 /* CE1CTL1[CEMRVS] Bits */
\r
9863 //#define CEMRVS_OFS (12) /* CEMRVS Offset */
\r
9864 //#define CEMRVS (0x1000) /* */
\r
9865 /* CE1CTL2[CEREF0] Bits */
\r
9866 //#define CEREF0_OFS ( 0) /* CEREF0 Offset */
\r
9867 //#define CEREF0_M (0x001f) /* Reference resistor tap 0 */
\r
9868 /* CE1CTL2[CERSEL] Bits */
\r
9869 //#define CERSEL_OFS ( 5) /* CERSEL Offset */
\r
9870 //#define CERSEL (0x0020) /* Reference select */
\r
9871 /* CE1CTL2[CERS] Bits */
\r
9872 //#define CERS_OFS ( 6) /* CERS Offset */
\r
9873 //#define CERS_M (0x00c0) /* Reference source */
\r
9874 //#define CERS0 (0x0040) /* Reference source */
\r
9875 //#define CERS1 (0x0080) /* Reference source */
\r
9876 //#define CERS_0 (0x0000) /* No current is drawn by the reference circuitry */
\r
9877 //#define CERS_1 (0x0040) /* VCC applied to the resistor ladder */
\r
9878 //#define CERS_2 (0x0080) /* Shared reference voltage applied to the resistor ladder */
\r
9879 //#define CERS_3 (0x00c0) /* Shared reference voltage supplied to V(CREF). Resistor ladder is off */
\r
9880 /* CE1CTL2[CEREF1] Bits */
\r
9881 //#define CEREF1_OFS ( 8) /* CEREF1 Offset */
\r
9882 //#define CEREF1_M (0x1f00) /* Reference resistor tap 1 */
\r
9883 /* CE1CTL2[CEREFL] Bits */
\r
9884 //#define CEREFL_OFS (13) /* CEREFL Offset */
\r
9885 //#define CEREFL_M (0x6000) /* Reference voltage level */
\r
9886 //#define CEREFL0 (0x2000) /* Reference voltage level */
\r
9887 //#define CEREFL1 (0x4000) /* Reference voltage level */
\r
9888 //#define CEREFL_0 (0x0000) /* Reference amplifier is disabled. No reference voltage is requested */
\r
9889 //#define CEREFL_1 (0x2000) /* 1.2 V is selected as shared reference voltage input */
\r
9890 //#define CEREFL_2 (0x4000) /* 2.0 V is selected as shared reference voltage input */
\r
9891 //#define CEREFL_3 (0x6000) /* 2.5 V is selected as shared reference voltage input */
\r
9892 //#define CEREFL__OFF (0x0000) /* Reference amplifier is disabled. No reference voltage is requested */
\r
9893 //#define CEREFL__1P2V (0x2000) /* 1.2 V is selected as shared reference voltage input */
\r
9894 //#define CEREFL__2P0V (0x4000) /* 2.0 V is selected as shared reference voltage input */
\r
9895 //#define CEREFL__2P5V (0x6000) /* 2.5 V is selected as shared reference voltage input */
\r
9896 /* CE1CTL2[CEREFACC] Bits */
\r
9897 //#define CEREFACC_OFS (15) /* CEREFACC Offset */
\r
9898 //#define CEREFACC (0x8000) /* Reference accuracy */
\r
9899 /* CE1CTL3[CEPD0] Bits */
\r
9900 //#define CEPD0_OFS ( 0) /* CEPD0 Offset */
\r
9901 //#define CEPD0 (0x0001) /* Port disable */
\r
9902 /* CE1CTL3[CEPD1] Bits */
\r
9903 //#define CEPD1_OFS ( 1) /* CEPD1 Offset */
\r
9904 //#define CEPD1 (0x0002) /* Port disable */
\r
9905 /* CE1CTL3[CEPD2] Bits */
\r
9906 //#define CEPD2_OFS ( 2) /* CEPD2 Offset */
\r
9907 //#define CEPD2 (0x0004) /* Port disable */
\r
9908 /* CE1CTL3[CEPD3] Bits */
\r
9909 //#define CEPD3_OFS ( 3) /* CEPD3 Offset */
\r
9910 //#define CEPD3 (0x0008) /* Port disable */
\r
9911 /* CE1CTL3[CEPD4] Bits */
\r
9912 //#define CEPD4_OFS ( 4) /* CEPD4 Offset */
\r
9913 //#define CEPD4 (0x0010) /* Port disable */
\r
9914 /* CE1CTL3[CEPD5] Bits */
\r
9915 //#define CEPD5_OFS ( 5) /* CEPD5 Offset */
\r
9916 //#define CEPD5 (0x0020) /* Port disable */
\r
9917 /* CE1CTL3[CEPD6] Bits */
\r
9918 //#define CEPD6_OFS ( 6) /* CEPD6 Offset */
\r
9919 //#define CEPD6 (0x0040) /* Port disable */
\r
9920 /* CE1CTL3[CEPD7] Bits */
\r
9921 //#define CEPD7_OFS ( 7) /* CEPD7 Offset */
\r
9922 //#define CEPD7 (0x0080) /* Port disable */
\r
9923 /* CE1CTL3[CEPD8] Bits */
\r
9924 //#define CEPD8_OFS ( 8) /* CEPD8 Offset */
\r
9925 //#define CEPD8 (0x0100) /* Port disable */
\r
9926 /* CE1CTL3[CEPD9] Bits */
\r
9927 //#define CEPD9_OFS ( 9) /* CEPD9 Offset */
\r
9928 //#define CEPD9 (0x0200) /* Port disable */
\r
9929 /* CE1CTL3[CEPD10] Bits */
\r
9930 //#define CEPD10_OFS (10) /* CEPD10 Offset */
\r
9931 //#define CEPD10 (0x0400) /* Port disable */
\r
9932 /* CE1CTL3[CEPD11] Bits */
\r
9933 //#define CEPD11_OFS (11) /* CEPD11 Offset */
\r
9934 //#define CEPD11 (0x0800) /* Port disable */
\r
9935 /* CE1CTL3[CEPD12] Bits */
\r
9936 //#define CEPD12_OFS (12) /* CEPD12 Offset */
\r
9937 //#define CEPD12 (0x1000) /* Port disable */
\r
9938 /* CE1CTL3[CEPD13] Bits */
\r
9939 //#define CEPD13_OFS (13) /* CEPD13 Offset */
\r
9940 //#define CEPD13 (0x2000) /* Port disable */
\r
9941 /* CE1CTL3[CEPD14] Bits */
\r
9942 //#define CEPD14_OFS (14) /* CEPD14 Offset */
\r
9943 //#define CEPD14 (0x4000) /* Port disable */
\r
9944 /* CE1CTL3[CEPD15] Bits */
\r
9945 //#define CEPD15_OFS (15) /* CEPD15 Offset */
\r
9946 //#define CEPD15 (0x8000) /* Port disable */
\r
9947 /* CE1INT[CEIFG] Bits */
\r
9948 //#define CEIFG_OFS ( 0) /* CEIFG Offset */
\r
9949 //#define CEIFG (0x0001) /* Comparator output interrupt flag */
\r
9950 /* CE1INT[CEIIFG] Bits */
\r
9951 //#define CEIIFG_OFS ( 1) /* CEIIFG Offset */
\r
9952 //#define CEIIFG (0x0002) /* Comparator output inverted interrupt flag */
\r
9953 /* CE1INT[CERDYIFG] Bits */
\r
9954 //#define CERDYIFG_OFS ( 4) /* CERDYIFG Offset */
\r
9955 //#define CERDYIFG (0x0010) /* Comparator ready interrupt flag */
\r
9956 /* CE1INT[CEIE] Bits */
\r
9957 //#define CEIE_OFS ( 8) /* CEIE Offset */
\r
9958 //#define CEIE (0x0100) /* Comparator output interrupt enable */
\r
9959 /* CE1INT[CEIIE] Bits */
\r
9960 //#define CEIIE_OFS ( 9) /* CEIIE Offset */
\r
9961 //#define CEIIE (0x0200) /* Comparator output interrupt enable inverted polarity */
\r
9962 /* CE1INT[CERDYIE] Bits */
\r
9963 //#define CERDYIE_OFS (12) /* CERDYIE Offset */
\r
9964 //#define CERDYIE (0x1000) /* Comparator ready interrupt enable */
\r
9967 //*****************************************************************************
\r
9969 //*****************************************************************************
\r
9970 /* COREDEBUG_DHCSR[COREDEBUG_DHCSR_C_DEBUGEN] Bits */
\r
9971 #define COREDEBUG_DHCSR_C_DEBUGEN_OFS ( 0) /* C_DEBUGEN Offset */
\r
9972 #define COREDEBUG_DHCSR_C_DEBUGEN (0x00000001) /* */
\r
9973 /* COREDEBUG_DHCSR[COREDEBUG_DHCSR_C_HALT] Bits */
\r
9974 #define COREDEBUG_DHCSR_C_HALT_OFS ( 1) /* C_HALT Offset */
\r
9975 #define COREDEBUG_DHCSR_C_HALT (0x00000002) /* */
\r
9976 /* COREDEBUG_DHCSR[COREDEBUG_DHCSR_C_STEP] Bits */
\r
9977 #define COREDEBUG_DHCSR_C_STEP_OFS ( 2) /* C_STEP Offset */
\r
9978 #define COREDEBUG_DHCSR_C_STEP (0x00000004) /* */
\r
9979 /* COREDEBUG_DHCSR[COREDEBUG_DHCSR_C_MASKINTS] Bits */
\r
9980 #define COREDEBUG_DHCSR_C_MASKINTS_OFS ( 3) /* C_MASKINTS Offset */
\r
9981 #define COREDEBUG_DHCSR_C_MASKINTS (0x00000008) /* */
\r
9982 /* COREDEBUG_DHCSR[COREDEBUG_DHCSR_C_SNAPSTALL] Bits */
\r
9983 #define COREDEBUG_DHCSR_C_SNAPSTALL_OFS ( 5) /* C_SNAPSTALL Offset */
\r
9984 #define COREDEBUG_DHCSR_C_SNAPSTALL (0x00000020) /* */
\r
9985 /* COREDEBUG_DHCSR[COREDEBUG_DHCSR_S_REGRDY] Bits */
\r
9986 #define COREDEBUG_DHCSR_S_REGRDY_OFS (16) /* S_REGRDY Offset */
\r
9987 #define COREDEBUG_DHCSR_S_REGRDY (0x00010000) /* */
\r
9988 /* COREDEBUG_DHCSR[COREDEBUG_DHCSR_S_HALT] Bits */
\r
9989 #define COREDEBUG_DHCSR_S_HALT_OFS (17) /* S_HALT Offset */
\r
9990 #define COREDEBUG_DHCSR_S_HALT (0x00020000) /* */
\r
9991 /* COREDEBUG_DHCSR[COREDEBUG_DHCSR_S_SLEEP] Bits */
\r
9992 #define COREDEBUG_DHCSR_S_SLEEP_OFS (18) /* S_SLEEP Offset */
\r
9993 #define COREDEBUG_DHCSR_S_SLEEP (0x00040000) /* */
\r
9994 /* COREDEBUG_DHCSR[COREDEBUG_DHCSR_S_LOCKUP] Bits */
\r
9995 #define COREDEBUG_DHCSR_S_LOCKUP_OFS (19) /* S_LOCKUP Offset */
\r
9996 #define COREDEBUG_DHCSR_S_LOCKUP (0x00080000) /* */
\r
9997 /* COREDEBUG_DHCSR[COREDEBUG_DHCSR_S_RETIRE_ST] Bits */
\r
9998 #define COREDEBUG_DHCSR_S_RETIRE_ST_OFS (24) /* S_RETIRE_ST Offset */
\r
9999 #define COREDEBUG_DHCSR_S_RETIRE_ST (0x01000000) /* */
\r
10000 /* COREDEBUG_DHCSR[COREDEBUG_DHCSR_S_RESET_ST] Bits */
\r
10001 #define COREDEBUG_DHCSR_S_RESET_ST_OFS (25) /* S_RESET_ST Offset */
\r
10002 #define COREDEBUG_DHCSR_S_RESET_ST (0x02000000) /* */
\r
10003 /* COREDEBUG_DCRSR[COREDEBUG_DCRSR_REGSEL] Bits */
\r
10004 #define COREDEBUG_DCRSR_REGSEL_OFS ( 0) /* REGSEL Offset */
\r
10005 #define COREDEBUG_DCRSR_REGSEL_M (0x0000001f) /* */
\r
10006 #define COREDEBUG_DCRSR_REGSEL0 (0x00000001) /* */
\r
10007 #define COREDEBUG_DCRSR_REGSEL1 (0x00000002) /* */
\r
10008 #define COREDEBUG_DCRSR_REGSEL2 (0x00000004) /* */
\r
10009 #define COREDEBUG_DCRSR_REGSEL3 (0x00000008) /* */
\r
10010 #define COREDEBUG_DCRSR_REGSEL4 (0x00000010) /* */
\r
10011 #define COREDEBUG_DCRSR_REGSEL_0 (0x00000000) /* R11 */
\r
10012 //#define COREDEBUG_DCRSR_REGSEL_0 (0x00000000) /* R0 */
\r
10013 #define COREDEBUG_DCRSR_REGSEL_1 (0x00000001) /* R1 */
\r
10014 #define COREDEBUG_DCRSR_REGSEL_2 (0x00000002) /* R2 */
\r
10015 #define COREDEBUG_DCRSR_REGSEL_3 (0x00000003) /* R3 */
\r
10016 #define COREDEBUG_DCRSR_REGSEL_4 (0x00000004) /* R4 */
\r
10017 #define COREDEBUG_DCRSR_REGSEL_5 (0x00000005) /* R5 */
\r
10018 #define COREDEBUG_DCRSR_REGSEL_6 (0x00000006) /* R6 */
\r
10019 #define COREDEBUG_DCRSR_REGSEL_7 (0x00000007) /* R7 */
\r
10020 #define COREDEBUG_DCRSR_REGSEL_8 (0x00000008) /* R8 */
\r
10021 #define COREDEBUG_DCRSR_REGSEL_9 (0x00000009) /* R9 */
\r
10022 #define COREDEBUG_DCRSR_REGSEL_10 (0x0000000a) /* R10 */
\r
10023 #define COREDEBUG_DCRSR_REGSEL_12 (0x0000000c) /* R12 */
\r
10024 #define COREDEBUG_DCRSR_REGSEL_13 (0x0000000d) /* Current SP */
\r
10025 #define COREDEBUG_DCRSR_REGSEL_14 (0x0000000e) /* LR */
\r
10026 #define COREDEBUG_DCRSR_REGSEL_15 (0x0000000f) /* DebugReturnAddress */
\r
10027 #define COREDEBUG_DCRSR_REGSEL_16 (0x00000010) /* xPSR/flags, execution state information, and exception number */
\r
10028 #define COREDEBUG_DCRSR_REGSEL_17 (0x00000011) /* MSP (Main SP) */
\r
10029 #define COREDEBUG_DCRSR_REGSEL_18 (0x00000012) /* PSP (Process SP) */
\r
10030 #define COREDEBUG_DCRSR_REGSEL_20 (0x00000014) /* CONTROL bits [31:24], FAULTMASK bits [23:16], BASEPRI bits [15:8], PRIMASK bits [7:0] */
\r
10031 /* COREDEBUG_DCRSR[COREDEBUG_DCRSR_REGWNR] Bits */
\r
10032 #define COREDEBUG_DCRSR_REGWNR_OFS (16) /* REGWNR Offset */
\r
10033 #define COREDEBUG_DCRSR_REGWNR (0x00010000) /* */
\r
10034 /* COREDEBUG_DEMCR[COREDEBUG_DEMCR_VC_CORERESET] Bits */
\r
10035 #define COREDEBUG_DEMCR_VC_CORERESET_OFS ( 0) /* VC_CORERESET Offset */
\r
10036 #define COREDEBUG_DEMCR_VC_CORERESET (0x00000001) /* */
\r
10037 /* COREDEBUG_DEMCR[COREDEBUG_DEMCR_VC_MMERR] Bits */
\r
10038 #define COREDEBUG_DEMCR_VC_MMERR_OFS ( 4) /* VC_MMERR Offset */
\r
10039 #define COREDEBUG_DEMCR_VC_MMERR (0x00000010) /* */
\r
10040 /* COREDEBUG_DEMCR[COREDEBUG_DEMCR_VC_NOCPERR] Bits */
\r
10041 #define COREDEBUG_DEMCR_VC_NOCPERR_OFS ( 5) /* VC_NOCPERR Offset */
\r
10042 #define COREDEBUG_DEMCR_VC_NOCPERR (0x00000020) /* */
\r
10043 /* COREDEBUG_DEMCR[COREDEBUG_DEMCR_VC_CHKERR] Bits */
\r
10044 #define COREDEBUG_DEMCR_VC_CHKERR_OFS ( 6) /* VC_CHKERR Offset */
\r
10045 #define COREDEBUG_DEMCR_VC_CHKERR (0x00000040) /* */
\r
10046 /* COREDEBUG_DEMCR[COREDEBUG_DEMCR_VC_STATERR] Bits */
\r
10047 #define COREDEBUG_DEMCR_VC_STATERR_OFS ( 7) /* VC_STATERR Offset */
\r
10048 #define COREDEBUG_DEMCR_VC_STATERR (0x00000080) /* */
\r
10049 /* COREDEBUG_DEMCR[COREDEBUG_DEMCR_VC_BUSERR] Bits */
\r
10050 #define COREDEBUG_DEMCR_VC_BUSERR_OFS ( 8) /* VC_BUSERR Offset */
\r
10051 #define COREDEBUG_DEMCR_VC_BUSERR (0x00000100) /* */
\r
10052 /* COREDEBUG_DEMCR[COREDEBUG_DEMCR_VC_INTERR] Bits */
\r
10053 #define COREDEBUG_DEMCR_VC_INTERR_OFS ( 9) /* VC_INTERR Offset */
\r
10054 #define COREDEBUG_DEMCR_VC_INTERR (0x00000200) /* */
\r
10055 /* COREDEBUG_DEMCR[COREDEBUG_DEMCR_VC_HARDERR] Bits */
\r
10056 #define COREDEBUG_DEMCR_VC_HARDERR_OFS (10) /* VC_HARDERR Offset */
\r
10057 #define COREDEBUG_DEMCR_VC_HARDERR (0x00000400) /* */
\r
10058 /* COREDEBUG_DEMCR[COREDEBUG_DEMCR_MON_EN] Bits */
\r
10059 #define COREDEBUG_DEMCR_MON_EN_OFS (16) /* MON_EN Offset */
\r
10060 #define COREDEBUG_DEMCR_MON_EN (0x00010000) /* */
\r
10061 /* COREDEBUG_DEMCR[COREDEBUG_DEMCR_MON_PEND] Bits */
\r
10062 #define COREDEBUG_DEMCR_MON_PEND_OFS (17) /* MON_PEND Offset */
\r
10063 #define COREDEBUG_DEMCR_MON_PEND (0x00020000) /* */
\r
10064 /* COREDEBUG_DEMCR[COREDEBUG_DEMCR_MON_STEP] Bits */
\r
10065 #define COREDEBUG_DEMCR_MON_STEP_OFS (18) /* MON_STEP Offset */
\r
10066 #define COREDEBUG_DEMCR_MON_STEP (0x00040000) /* */
\r
10067 /* COREDEBUG_DEMCR[COREDEBUG_DEMCR_MON_REQ] Bits */
\r
10068 #define COREDEBUG_DEMCR_MON_REQ_OFS (19) /* MON_REQ Offset */
\r
10069 #define COREDEBUG_DEMCR_MON_REQ (0x00080000) /* */
\r
10070 /* COREDEBUG_DEMCR[COREDEBUG_DEMCR_TRCENA] Bits */
\r
10071 #define COREDEBUG_DEMCR_TRCENA_OFS (24) /* TRCENA Offset */
\r
10072 #define COREDEBUG_DEMCR_TRCENA (0x01000000) /* */
\r
10075 //*****************************************************************************
\r
10077 //*****************************************************************************
\r
10080 //*****************************************************************************
\r
10082 //*****************************************************************************
\r
10083 /* CSKEY[CSKEY] Bits */
\r
10084 #define CSKEY_OFS ( 0) /* CSKEY Offset */
\r
10085 #define CSKEY_M (0x0000ffff) /* Write xxxx_695Ah to unlock */
\r
10086 /* CSCTL0[DCOTUNE] Bits */
\r
10087 #define DCOTUNE_OFS ( 0) /* DCOTUNE Offset */
\r
10088 #define DCOTUNE_M (0x00001fff) /* DCO frequency tuning select */
\r
10089 /* CSCTL0[DCORSEL] Bits */
\r
10090 #define DCORSEL_OFS (16) /* DCORSEL Offset */
\r
10091 #define DCORSEL_M (0x00070000) /* DCO frequency range select */
\r
10092 #define DCORSEL0 (0x00010000) /* DCO frequency range select */
\r
10093 #define DCORSEL1 (0x00020000) /* DCO frequency range select */
\r
10094 #define DCORSEL2 (0x00040000) /* DCO frequency range select */
\r
10095 #define DCORSEL_0 (0x00000000) /* Nominal DCO Frequency Range (MHz): 1 to 2 */
\r
10096 #define DCORSEL_1 (0x00010000) /* Nominal DCO Frequency Range (MHz): 2 to 4 */
\r
10097 #define DCORSEL_2 (0x00020000) /* Nominal DCO Frequency Range (MHz): 4 to 8 */
\r
10098 #define DCORSEL_3 (0x00030000) /* Nominal DCO Frequency Range (MHz): 8 to 16 */
\r
10099 #define DCORSEL_4 (0x00040000) /* Nominal DCO Frequency Range (MHz): 16 to 32 */
\r
10100 #define DCORSEL_5 (0x00050000) /* Nominal DCO Frequency Range (MHz): 32 to 64 */
\r
10101 /* CSCTL0[DCORES] Bits */
\r
10102 #define DCORES_OFS (22) /* DCORES Offset */
\r
10103 #define DCORES (0x00400000) /* Enables the DCO external resistor mode */
\r
10104 /* CSCTL0[DCOEN] Bits */
\r
10105 #define DCOEN_OFS (23) /* DCOEN Offset */
\r
10106 #define DCOEN (0x00800000) /* Enables the DCO oscillator */
\r
10107 /* CSCTL0[DIS_DCO_DELAY_CNT] Bits */
\r
10108 #define DIS_DCO_DELAY_CNT_OFS (24) /* DIS_DCO_DELAY_CNT Offset */
\r
10109 #define DIS_DCO_DELAY_CNT (0x01000000) /* */
\r
10110 /* CSCTL1[SELM] Bits */
\r
10111 #define SELM_OFS ( 0) /* SELM Offset */
\r
10112 #define SELM_M (0x00000007) /* Selects the MCLK source */
\r
10113 #define SELM0 (0x00000001) /* Selects the MCLK source */
\r
10114 #define SELM1 (0x00000002) /* Selects the MCLK source */
\r
10115 #define SELM2 (0x00000004) /* Selects the MCLK source */
\r
10116 #define SELM_0 (0x00000000) /* when LFXT available, otherwise REFOCLK */
\r
10117 #define SELM_1 (0x00000001) /* */
\r
10118 #define SELM_2 (0x00000002) /* */
\r
10119 #define SELM_3 (0x00000003) /* */
\r
10120 #define SELM_4 (0x00000004) /* */
\r
10121 #define SELM_5 (0x00000005) /* when HFXT available, otherwise DCOCLK */
\r
10122 #define SELM_6 (0x00000006) /* when HFXT2 available, otherwise DCOCLK */
\r
10123 #define SELM__LFXTCLK (0x00000000) /* when LFXT available, otherwise REFOCLK */
\r
10124 #define SELM__VLOCLK (0x00000001) /* */
\r
10125 #define SELM__REFOCLK (0x00000002) /* */
\r
10126 #define SELM__DCOCLK (0x00000003) /* */
\r
10127 #define SELM__MODOSC (0x00000004) /* */
\r
10128 #define SELM__HFXTCLK (0x00000005) /* when HFXT available, otherwise DCOCLK */
\r
10129 #define SELM__HFXT2CLK (0x00000006) /* when HFXT2 available, otherwise DCOCLK */
\r
10130 #define SELM_7 (0x00000007) /* for future use. Defaults to DCOCLK. Not recommended for use to ensure future compatibilities. */
\r
10131 /* CSCTL1[SELS] Bits */
\r
10132 #define SELS_OFS ( 4) /* SELS Offset */
\r
10133 #define SELS_M (0x00000070) /* Selects the SMCLK and HSMCLK source */
\r
10134 #define SELS0 (0x00000010) /* Selects the SMCLK and HSMCLK source */
\r
10135 #define SELS1 (0x00000020) /* Selects the SMCLK and HSMCLK source */
\r
10136 #define SELS2 (0x00000040) /* Selects the SMCLK and HSMCLK source */
\r
10137 #define SELS_0 (0x00000000) /* when LFXT available, otherwise REFOCLK */
\r
10138 #define SELS_1 (0x00000010) /* */
\r
10139 #define SELS_2 (0x00000020) /* */
\r
10140 #define SELS_3 (0x00000030) /* */
\r
10141 #define SELS_4 (0x00000040) /* */
\r
10142 #define SELS_5 (0x00000050) /* when HFXT available, otherwise DCOCLK */
\r
10143 #define SELS_6 (0x00000060) /* when HFXT2 available, otherwise DCOCLK */
\r
10144 #define SELS__LFXTCLK (0x00000000) /* when LFXT available, otherwise REFOCLK */
\r
10145 #define SELS__VLOCLK (0x00000010) /* */
\r
10146 #define SELS__REFOCLK (0x00000020) /* */
\r
10147 #define SELS__DCOCLK (0x00000030) /* */
\r
10148 #define SELS__MODOSC (0x00000040) /* */
\r
10149 #define SELS__HFXTCLK (0x00000050) /* when HFXT available, otherwise DCOCLK */
\r
10150 #define SELS__HFXT2CLK (0x00000060) /* when HFXT2 available, otherwise DCOCLK */
\r
10151 #define SELS_7 (0x00000070) /* for furture use. Defaults to DCOCLK. Do not use to ensure future compatibilities. */
\r
10152 /* CSCTL1[SELA] Bits */
\r
10153 #define SELA_OFS ( 8) /* SELA Offset */
\r
10154 #define SELA_M (0x00000700) /* Selects the ACLK source */
\r
10155 #define SELA0 (0x00000100) /* Selects the ACLK source */
\r
10156 #define SELA1 (0x00000200) /* Selects the ACLK source */
\r
10157 #define SELA2 (0x00000400) /* Selects the ACLK source */
\r
10158 #define SELA_0 (0x00000000) /* when LFXT available, otherwise REFOCLK */
\r
10159 #define SELA_1 (0x00000100) /* */
\r
10160 #define SELA_2 (0x00000200) /* */
\r
10161 #define SELA__LFXTCLK (0x00000000) /* when LFXT available, otherwise REFOCLK */
\r
10162 #define SELA__VLOCLK (0x00000100) /* */
\r
10163 #define SELA__REFOCLK (0x00000200) /* */
\r
10164 #define SELA_3 (0x00000300) /* for future use. Defaults to REFOCLK. Not recommended for use to ensure future compatibilities. */
\r
10165 #define SELA_4 (0x00000400) /* for future use. Defaults to REFOCLK. Not recommended for use to ensure future compatibilities. */
\r
10166 #define SELA_5 (0x00000500) /* for future use. Defaults to REFOCLK. Not recommended for use to ensure future compatibilities. */
\r
10167 #define SELA_6 (0x00000600) /* for future use. Defaults to REFOCLK. Not recommended for use to ensure future compatibilities. */
\r
10168 #define SELA_7 (0x00000700) /* for future use. Defaults to REFOCLK. Not recommended for use to ensure future compatibilities. */
\r
10169 /* CSCTL1[SELB] Bits */
\r
10170 #define SELB_OFS (12) /* SELB Offset */
\r
10171 #define SELB (0x00001000) /* Selects the BCLK source */
\r
10172 /* CSCTL1[DIVM] Bits */
\r
10173 #define DIVM_OFS (16) /* DIVM Offset */
\r
10174 #define DIVM_M (0x00070000) /* MCLK source divider */
\r
10175 #define DIVM0 (0x00010000) /* MCLK source divider */
\r
10176 #define DIVM1 (0x00020000) /* MCLK source divider */
\r
10177 #define DIVM2 (0x00040000) /* MCLK source divider */
\r
10178 #define DIVM_0 (0x00000000) /* f(MCLK)/1 */
\r
10179 #define DIVM_1 (0x00010000) /* f(MCLK)/2 */
\r
10180 #define DIVM_2 (0x00020000) /* f(MCLK)/4 */
\r
10181 #define DIVM_3 (0x00030000) /* f(MCLK)/8 */
\r
10182 #define DIVM_4 (0x00040000) /* f(MCLK)/16 */
\r
10183 #define DIVM_5 (0x00050000) /* f(MCLK)/32 */
\r
10184 #define DIVM_6 (0x00060000) /* f(MCLK)/64 */
\r
10185 #define DIVM_7 (0x00070000) /* f(MCLK)/128 */
\r
10186 #define DIVM__1 (0x00000000) /* f(MCLK)/1 */
\r
10187 #define DIVM__2 (0x00010000) /* f(MCLK)/2 */
\r
10188 #define DIVM__4 (0x00020000) /* f(MCLK)/4 */
\r
10189 #define DIVM__8 (0x00030000) /* f(MCLK)/8 */
\r
10190 #define DIVM__16 (0x00040000) /* f(MCLK)/16 */
\r
10191 #define DIVM__32 (0x00050000) /* f(MCLK)/32 */
\r
10192 #define DIVM__64 (0x00060000) /* f(MCLK)/64 */
\r
10193 #define DIVM__128 (0x00070000) /* f(MCLK)/128 */
\r
10194 /* CSCTL1[DIVHS] Bits */
\r
10195 #define DIVHS_OFS (20) /* DIVHS Offset */
\r
10196 #define DIVHS_M (0x00700000) /* HSMCLK source divider */
\r
10197 #define DIVHS0 (0x00100000) /* HSMCLK source divider */
\r
10198 #define DIVHS1 (0x00200000) /* HSMCLK source divider */
\r
10199 #define DIVHS2 (0x00400000) /* HSMCLK source divider */
\r
10200 #define DIVHS_0 (0x00000000) /* f(HSMCLK)/1 */
\r
10201 #define DIVHS_1 (0x00100000) /* f(HSMCLK)/2 */
\r
10202 #define DIVHS_2 (0x00200000) /* f(HSMCLK)/4 */
\r
10203 #define DIVHS_3 (0x00300000) /* f(HSMCLK)/8 */
\r
10204 #define DIVHS_4 (0x00400000) /* f(HSMCLK)/16 */
\r
10205 #define DIVHS_5 (0x00500000) /* f(HSMCLK)/32 */
\r
10206 #define DIVHS_6 (0x00600000) /* f(HSMCLK)/64 */
\r
10207 #define DIVHS_7 (0x00700000) /* f(HSMCLK)/128 */
\r
10208 #define DIVHS__1 (0x00000000) /* f(HSMCLK)/1 */
\r
10209 #define DIVHS__2 (0x00100000) /* f(HSMCLK)/2 */
\r
10210 #define DIVHS__4 (0x00200000) /* f(HSMCLK)/4 */
\r
10211 #define DIVHS__8 (0x00300000) /* f(HSMCLK)/8 */
\r
10212 #define DIVHS__16 (0x00400000) /* f(HSMCLK)/16 */
\r
10213 #define DIVHS__32 (0x00500000) /* f(HSMCLK)/32 */
\r
10214 #define DIVHS__64 (0x00600000) /* f(HSMCLK)/64 */
\r
10215 #define DIVHS__128 (0x00700000) /* f(HSMCLK)/128 */
\r
10216 /* CSCTL1[DIVA] Bits */
\r
10217 #define DIVA_OFS (24) /* DIVA Offset */
\r
10218 #define DIVA_M (0x07000000) /* ACLK source divider */
\r
10219 #define DIVA0 (0x01000000) /* ACLK source divider */
\r
10220 #define DIVA1 (0x02000000) /* ACLK source divider */
\r
10221 #define DIVA2 (0x04000000) /* ACLK source divider */
\r
10222 #define DIVA_0 (0x00000000) /* f(ACLK)/1 */
\r
10223 #define DIVA_1 (0x01000000) /* f(ACLK)/2 */
\r
10224 #define DIVA_2 (0x02000000) /* f(ACLK)/4 */
\r
10225 #define DIVA_3 (0x03000000) /* f(ACLK)/8 */
\r
10226 #define DIVA_4 (0x04000000) /* f(ACLK)/16 */
\r
10227 #define DIVA_5 (0x05000000) /* f(ACLK)/32 */
\r
10228 #define DIVA_6 (0x06000000) /* f(ACLK)/64 */
\r
10229 #define DIVA_7 (0x07000000) /* f(ACLK)/128 */
\r
10230 #define DIVA__1 (0x00000000) /* f(ACLK)/1 */
\r
10231 #define DIVA__2 (0x01000000) /* f(ACLK)/2 */
\r
10232 #define DIVA__4 (0x02000000) /* f(ACLK)/4 */
\r
10233 #define DIVA__8 (0x03000000) /* f(ACLK)/8 */
\r
10234 #define DIVA__16 (0x04000000) /* f(ACLK)/16 */
\r
10235 #define DIVA__32 (0x05000000) /* f(ACLK)/32 */
\r
10236 #define DIVA__64 (0x06000000) /* f(ACLK)/64 */
\r
10237 #define DIVA__128 (0x07000000) /* f(ACLK)/128 */
\r
10238 /* CSCTL1[DIVS] Bits */
\r
10239 #define DIVS_OFS (28) /* DIVS Offset */
\r
10240 #define DIVS_M (0x70000000) /* SMCLK source divider */
\r
10241 #define DIVS0 (0x10000000) /* SMCLK source divider */
\r
10242 #define DIVS1 (0x20000000) /* SMCLK source divider */
\r
10243 #define DIVS2 (0x40000000) /* SMCLK source divider */
\r
10244 #define DIVS_0 (0x00000000) /* f(SMCLK)/1 */
\r
10245 #define DIVS_1 (0x10000000) /* f(SMCLK)/2 */
\r
10246 #define DIVS_2 (0x20000000) /* f(SMCLK)/4 */
\r
10247 #define DIVS_3 (0x30000000) /* f(SMCLK)/8 */
\r
10248 #define DIVS_4 (0x40000000) /* f(SMCLK)/16 */
\r
10249 #define DIVS_5 (0x50000000) /* f(SMCLK)/32 */
\r
10250 #define DIVS_6 (0x60000000) /* f(SMCLK)/64 */
\r
10251 #define DIVS_7 (0x70000000) /* f(SMCLK)/128 */
\r
10252 #define DIVS__1 (0x00000000) /* f(SMCLK)/1 */
\r
10253 #define DIVS__2 (0x10000000) /* f(SMCLK)/2 */
\r
10254 #define DIVS__4 (0x20000000) /* f(SMCLK)/4 */
\r
10255 #define DIVS__8 (0x30000000) /* f(SMCLK)/8 */
\r
10256 #define DIVS__16 (0x40000000) /* f(SMCLK)/16 */
\r
10257 #define DIVS__32 (0x50000000) /* f(SMCLK)/32 */
\r
10258 #define DIVS__64 (0x60000000) /* f(SMCLK)/64 */
\r
10259 #define DIVS__128 (0x70000000) /* f(SMCLK)/128 */
\r
10260 /* CSCTL2[LFXTDRIVE] Bits */
\r
10261 #define LFXTDRIVE_OFS ( 0) /* LFXTDRIVE Offset */
\r
10262 #define LFXTDRIVE_M (0x00000007) /* LFXT oscillator current can be adjusted to its drive needs */
\r
10263 #define LFXTDRIVE0 (0x00000001) /* LFXT oscillator current can be adjusted to its drive needs */
\r
10264 #define LFXTDRIVE1 (0x00000002) /* LFXT oscillator current can be adjusted to its drive needs */
\r
10265 #define LFXTDRIVE2 (0x00000004) /* LFXT oscillator current can be adjusted to its drive needs */
\r
10266 #define LFXTDRIVE_0 (0x00000000) /* Lowest current consumption. */
\r
10267 #define LFXTDRIVE_1 (0x00000001) /* Increased drive strength LFXT oscillator. */
\r
10268 #define LFXTDRIVE_2 (0x00000002) /* Increased drive strength LFXT oscillator. */
\r
10269 #define LFXTDRIVE_3 (0x00000003) /* Increased drive strength LFXT oscillator. */
\r
10270 #define LFXTDRIVE_4 (0x00000004) /* Increased drive strength LFXT oscillator. */
\r
10271 #define LFXTDRIVE_5 (0x00000005) /* Increased drive strength LFXT oscillator. */
\r
10272 #define LFXTDRIVE_6 (0x00000006) /* Increased drive strength LFXT oscillator. */
\r
10273 #define LFXTDRIVE_7 (0x00000007) /* Maximum drive strength LFXT oscillator. */
\r
10274 /* CSCTL2[LFXTAGCOFF] Bits */
\r
10275 #define LFXTAGCOFF_OFS ( 7) /* LFXTAGCOFF Offset */
\r
10276 #define LFXTAGCOFF (0x00000080) /* Disables the automatic gain control of the LFXT crystal */
\r
10277 /* CSCTL2[LFXT_EN] Bits */
\r
10278 #define LFXT_EN_OFS ( 8) /* LFXT_EN Offset */
\r
10279 #define LFXT_EN (0x00000100) /* Turns on the LFXT oscillator regardless if used as a clock resource */
\r
10280 /* CSCTL2[LFXTBYPASS] Bits */
\r
10281 #define LFXTBYPASS_OFS ( 9) /* LFXTBYPASS Offset */
\r
10282 #define LFXTBYPASS (0x00000200) /* LFXT bypass select */
\r
10283 /* CSCTL2[HFXTDRIVE] Bits */
\r
10284 #define HFXTDRIVE_OFS (16) /* HFXTDRIVE Offset */
\r
10285 #define HFXTDRIVE (0x00010000) /* HFXT oscillator drive selection */
\r
10286 /* CSCTL2[HFXTFREQ] Bits */
\r
10287 #define HFXTFREQ_OFS (20) /* HFXTFREQ Offset */
\r
10288 #define HFXTFREQ_M (0x00700000) /* HFXT frequency selection */
\r
10289 #define HFXTFREQ0 (0x00100000) /* HFXT frequency selection */
\r
10290 #define HFXTFREQ1 (0x00200000) /* HFXT frequency selection */
\r
10291 #define HFXTFREQ2 (0x00400000) /* HFXT frequency selection */
\r
10292 #define HFXTFREQ_0 (0x00000000) /* 1 MHz to 4 MHz */
\r
10293 #define HFXTFREQ_1 (0x00100000) /* >4 MHz to 8 MHz */
\r
10294 #define HFXTFREQ_2 (0x00200000) /* >8 MHz to 16 MHz */
\r
10295 #define HFXTFREQ_3 (0x00300000) /* >16 MHz to 24 MHz */
\r
10296 #define HFXTFREQ_4 (0x00400000) /* >24 MHz to 32 MHz */
\r
10297 #define HFXTFREQ_5 (0x00500000) /* >32 MHz to 40 MHz */
\r
10298 #define HFXTFREQ_6 (0x00600000) /* >40 MHz to 48 MHz */
\r
10299 /* CSCTL2[HFXT_EN] Bits */
\r
10300 #define HFXT_EN_OFS (24) /* HFXT_EN Offset */
\r
10301 #define HFXT_EN (0x01000000) /* Turns on the HFXT oscillator regardless if used as a clock resource */
\r
10302 /* CSCTL2[HFXTBYPASS] Bits */
\r
10303 #define HFXTBYPASS_OFS (25) /* HFXTBYPASS Offset */
\r
10304 #define HFXTBYPASS (0x02000000) /* HFXT bypass select */
\r
10305 /* CSCTL3[FCNTLF] Bits */
\r
10306 #define FCNTLF_OFS ( 0) /* FCNTLF Offset */
\r
10307 #define FCNTLF_M (0x00000003) /* Start flag counter for LFXT */
\r
10308 #define FCNTLF0 (0x00000001) /* Start flag counter for LFXT */
\r
10309 #define FCNTLF1 (0x00000002) /* Start flag counter for LFXT */
\r
10310 #define FCNTLF_0 (0x00000000) /* 4096 cycles */
\r
10311 #define FCNTLF_1 (0x00000001) /* 8192 cycles */
\r
10312 #define FCNTLF_2 (0x00000002) /* 16384 cycles */
\r
10313 #define FCNTLF_3 (0x00000003) /* 32768 cycles */
\r
10314 #define FCNTLF__4096 (0x00000000) /* 4096 cycles */
\r
10315 #define FCNTLF__8192 (0x00000001) /* 8192 cycles */
\r
10316 #define FCNTLF__16384 (0x00000002) /* 16384 cycles */
\r
10317 #define FCNTLF__32768 (0x00000003) /* 32768 cycles */
\r
10318 /* CSCTL3[RFCNTLF] Bits */
\r
10319 #define RFCNTLF_OFS ( 2) /* RFCNTLF Offset */
\r
10320 #define RFCNTLF (0x00000004) /* Reset start fault counter for LFXT */
\r
10321 /* CSCTL3[FCNTLF_EN] Bits */
\r
10322 #define FCNTLF_EN_OFS ( 3) /* FCNTLF_EN Offset */
\r
10323 #define FCNTLF_EN (0x00000008) /* Enable start fault counter for LFXT */
\r
10324 /* CSCTL3[FCNTHF] Bits */
\r
10325 #define FCNTHF_OFS ( 4) /* FCNTHF Offset */
\r
10326 #define FCNTHF_M (0x00000030) /* Start flag counter for HFXT */
\r
10327 #define FCNTHF0 (0x00000010) /* Start flag counter for HFXT */
\r
10328 #define FCNTHF1 (0x00000020) /* Start flag counter for HFXT */
\r
10329 #define FCNTHF_0 (0x00000000) /* 2048 cycles */
\r
10330 #define FCNTHF_1 (0x00000010) /* 4096 cycles */
\r
10331 #define FCNTHF_2 (0x00000020) /* 8192 cycles */
\r
10332 #define FCNTHF_3 (0x00000030) /* 16384 cycles */
\r
10333 #define FCNTHF__2048 (0x00000000) /* 2048 cycles */
\r
10334 #define FCNTHF__4096 (0x00000010) /* 4096 cycles */
\r
10335 #define FCNTHF__8192 (0x00000020) /* 8192 cycles */
\r
10336 #define FCNTHF__16384 (0x00000030) /* 16384 cycles */
\r
10337 /* CSCTL3[RFCNTHF] Bits */
\r
10338 #define RFCNTHF_OFS ( 6) /* RFCNTHF Offset */
\r
10339 #define RFCNTHF (0x00000040) /* Reset start fault counter for HFXT */
\r
10340 /* CSCTL3[FCNTHF_EN] Bits */
\r
10341 #define FCNTHF_EN_OFS ( 7) /* FCNTHF_EN Offset */
\r
10342 #define FCNTHF_EN (0x00000080) /* Enable start fault counter for HFXT */
\r
10343 /* CSCTL3[FCNTHF2] Bits */
\r
10344 #define FCNTHF2_OFS ( 8) /* FCNTHF2 Offset */
\r
10345 #define FCNTHF2_M (0x00000300) /* Start flag counter for HFXT2 */
\r
10346 #define FCNTHF20 (0x00000100) /* Start flag counter for HFXT2 */
\r
10347 #define FCNTHF21 (0x00000200) /* Start flag counter for HFXT2 */
\r
10348 #define FCNTHF2_0 (0x00000000) /* 2048 cycles */
\r
10349 #define FCNTHF2_1 (0x00000100) /* 4096 cycles */
\r
10350 #define FCNTHF2_2 (0x00000200) /* 8192 cycles */
\r
10351 #define FCNTHF2_3 (0x00000300) /* 16384 cycles */
\r
10352 #define FCNTHF2__2048 (0x00000000) /* 2048 cycles */
\r
10353 #define FCNTHF2__4096 (0x00000100) /* 4096 cycles */
\r
10354 #define FCNTHF2__8192 (0x00000200) /* 8192 cycles */
\r
10355 #define FCNTHF2__16384 (0x00000300) /* 16384 cycles */
\r
10356 /* CSCTL3[RFCNTHF2] Bits */
\r
10357 #define RFCNTHF2_OFS (10) /* RFCNTHF2 Offset */
\r
10358 #define RFCNTHF2 (0x00000400) /* Reset start fault counter for HFXT2 */
\r
10359 /* CSCTL3[FCNTHF2_EN] Bits */
\r
10360 #define FCNTHF2_EN_OFS (11) /* FCNTHF2_EN Offset */
\r
10361 #define FCNTHF2_EN (0x00000800) /* Enable start fault counter for HFXT2 */
\r
10362 /* CSCTL4[HFXT2DRIVE] Bits */
\r
10363 #define HFXT2DRIVE_OFS ( 0) /* HFXT2DRIVE Offset */
\r
10364 #define HFXT2DRIVE_M (0x00000007) /* HFXT2 oscillator current can be adjusted to its drive needs */
\r
10365 #define HFXT2DRIVE0 (0x00000001) /* HFXT2 oscillator current can be adjusted to its drive needs */
\r
10366 #define HFXT2DRIVE1 (0x00000002) /* HFXT2 oscillator current can be adjusted to its drive needs */
\r
10367 #define HFXT2DRIVE2 (0x00000004) /* HFXT2 oscillator current can be adjusted to its drive needs */
\r
10368 #define HFXT2DRIVE_0 (0x00000000) /* Lowest current consumption */
\r
10369 #define HFXT2DRIVE_1 (0x00000001) /* Increased drive strength HFXT2 oscillator */
\r
10370 #define HFXT2DRIVE_2 (0x00000002) /* Increased drive strength HFXT2 oscillator */
\r
10371 #define HFXT2DRIVE_3 (0x00000003) /* Increased drive strength HFXT2 oscillator */
\r
10372 #define HFXT2DRIVE_4 (0x00000004) /* Increased drive strength HFXT2 oscillator */
\r
10373 #define HFXT2DRIVE_5 (0x00000005) /* Increased drive strength HFXT2 oscillator */
\r
10374 #define HFXT2DRIVE_6 (0x00000006) /* Increased drive strength HFXT2 oscillator */
\r
10375 #define HFXT2DRIVE_7 (0x00000007) /* Maximum drive strength HFXT2 oscillator */
\r
10376 /* CSCTL4[HFXT2FREQ] Bits */
\r
10377 #define HFXT2FREQ_OFS ( 4) /* HFXT2FREQ Offset */
\r
10378 #define HFXT2FREQ_M (0x00000070) /* HFXT2 frequency selection */
\r
10379 /* CSCTL4[HFXT2_EN] Bits */
\r
10380 #define HFXT2_EN_OFS ( 8) /* HFXT2_EN Offset */
\r
10381 #define HFXT2_EN (0x00000100) /* Turns on the HFXT2 oscillator */
\r
10382 /* CSCTL4[HFXT2BYPASS] Bits */
\r
10383 #define HFXT2BYPASS_OFS ( 9) /* HFXT2BYPASS Offset */
\r
10384 #define HFXT2BYPASS (0x00000200) /* HFXT2 bypass select */
\r
10385 /* CSCTL5[REFCNTSEL] Bits */
\r
10386 #define REFCNTSEL_OFS ( 0) /* REFCNTSEL Offset */
\r
10387 #define REFCNTSEL_M (0x00000007) /* Reference counter source select */
\r
10388 /* CSCTL5[REFCNTPS] Bits */
\r
10389 #define REFCNTPS_OFS ( 3) /* REFCNTPS Offset */
\r
10390 #define REFCNTPS_M (0x00000038) /* Reference clock prescaler */
\r
10391 /* CSCTL5[CALSTART] Bits */
\r
10392 #define CALSTART_OFS ( 7) /* CALSTART Offset */
\r
10393 #define CALSTART (0x00000080) /* Start clock calibration counters */
\r
10394 /* CSCTL5[PERCNTSEL] Bits */
\r
10395 #define PERCNTSEL_OFS ( 8) /* PERCNTSEL Offset */
\r
10396 #define PERCNTSEL_M (0x00000700) /* Period counter source select */
\r
10397 /* CSCTL6[PERCNT] Bits */
\r
10398 #define PERCNT_OFS ( 0) /* PERCNT Offset */
\r
10399 #define PERCNT_M (0x0000ffff) /* Calibration period counter */
\r
10400 /* CSCTL7[REFCNT] Bits */
\r
10401 #define REFCNT_OFS ( 0) /* REFCNT Offset */
\r
10402 #define REFCNT_M (0x0000ffff) /* Calibration reference period counter */
\r
10403 /* CSCLKEN[ACLK_EN] Bits */
\r
10404 #define ACLK_EN_OFS ( 0) /* ACLK_EN Offset */
\r
10405 #define ACLK_EN (0x00000001) /* ACLK system clock conditional request enable */
\r
10406 /* CSCLKEN[MCLK_EN] Bits */
\r
10407 #define MCLK_EN_OFS ( 1) /* MCLK_EN Offset */
\r
10408 #define MCLK_EN (0x00000002) /* MCLK system clock conditional request enable */
\r
10409 /* CSCLKEN[HSMCLK_EN] Bits */
\r
10410 #define HSMCLK_EN_OFS ( 2) /* HSMCLK_EN Offset */
\r
10411 #define HSMCLK_EN (0x00000004) /* HSMCLK system clock conditional request enable */
\r
10412 /* CSCLKEN[SMCLK_EN] Bits */
\r
10413 #define SMCLK_EN_OFS ( 3) /* SMCLK_EN Offset */
\r
10414 #define SMCLK_EN (0x00000008) /* SMCLK system clock conditional request enable */
\r
10415 /* CSCLKEN[VLO_EN] Bits */
\r
10416 #define VLO_EN_OFS ( 8) /* VLO_EN Offset */
\r
10417 #define VLO_EN (0x00000100) /* Turns on the VLO oscillator */
\r
10418 /* CSCLKEN[REFO_EN] Bits */
\r
10419 #define REFO_EN_OFS ( 9) /* REFO_EN Offset */
\r
10420 #define REFO_EN (0x00000200) /* Turns on the REFO oscillator */
\r
10421 /* CSCLKEN[MODOSC_EN] Bits */
\r
10422 #define MODOSC_EN_OFS (10) /* MODOSC_EN Offset */
\r
10423 #define MODOSC_EN (0x00000400) /* Turns on the MODOSC oscillator */
\r
10424 /* CSCLKEN[REFOFSEL] Bits */
\r
10425 #define REFOFSEL_OFS (15) /* REFOFSEL Offset */
\r
10426 #define REFOFSEL (0x00008000) /* Selects REFO nominal frequency */
\r
10427 /* CSSTAT[DCO_ON] Bits */
\r
10428 #define DCO_ON_OFS ( 0) /* DCO_ON Offset */
\r
10429 #define DCO_ON (0x00000001) /* DCO status */
\r
10430 /* CSSTAT[DCOBIAS_ON] Bits */
\r
10431 #define DCOBIAS_ON_OFS ( 1) /* DCOBIAS_ON Offset */
\r
10432 #define DCOBIAS_ON (0x00000002) /* DCO bias status */
\r
10433 /* CSSTAT[HFXT_ON] Bits */
\r
10434 #define HFXT_ON_OFS ( 2) /* HFXT_ON Offset */
\r
10435 #define HFXT_ON (0x00000004) /* HFXT status */
\r
10436 /* CSSTAT[HFXT2_ON] Bits */
\r
10437 #define HFXT2_ON_OFS ( 3) /* HFXT2_ON Offset */
\r
10438 #define HFXT2_ON (0x00000008) /* HFXT2 status */
\r
10439 /* CSSTAT[MODOSC_ON] Bits */
\r
10440 #define MODOSC_ON_OFS ( 4) /* MODOSC_ON Offset */
\r
10441 #define MODOSC_ON (0x00000010) /* MODOSC status */
\r
10442 /* CSSTAT[VLO_ON] Bits */
\r
10443 #define VLO_ON_OFS ( 5) /* VLO_ON Offset */
\r
10444 #define VLO_ON (0x00000020) /* VLO status */
\r
10445 /* CSSTAT[LFXT_ON] Bits */
\r
10446 #define LFXT_ON_OFS ( 6) /* LFXT_ON Offset */
\r
10447 #define LFXT_ON (0x00000040) /* LFXT status */
\r
10448 /* CSSTAT[REFO_ON] Bits */
\r
10449 #define REFO_ON_OFS ( 7) /* REFO_ON Offset */
\r
10450 #define REFO_ON (0x00000080) /* REFO status */
\r
10451 /* CSSTAT[ACLK_ON] Bits */
\r
10452 #define ACLK_ON_OFS (16) /* ACLK_ON Offset */
\r
10453 #define ACLK_ON (0x00010000) /* ACLK system clock status */
\r
10454 /* CSSTAT[MCLK_ON] Bits */
\r
10455 #define MCLK_ON_OFS (17) /* MCLK_ON Offset */
\r
10456 #define MCLK_ON (0x00020000) /* MCLK system clock status */
\r
10457 /* CSSTAT[HSMCLK_ON] Bits */
\r
10458 #define HSMCLK_ON_OFS (18) /* HSMCLK_ON Offset */
\r
10459 #define HSMCLK_ON (0x00040000) /* HSMCLK system clock status */
\r
10460 /* CSSTAT[SMCLK_ON] Bits */
\r
10461 #define SMCLK_ON_OFS (19) /* SMCLK_ON Offset */
\r
10462 #define SMCLK_ON (0x00080000) /* SMCLK system clock status */
\r
10463 /* CSSTAT[MODCLK_ON] Bits */
\r
10464 #define MODCLK_ON_OFS (20) /* MODCLK_ON Offset */
\r
10465 #define MODCLK_ON (0x00100000) /* MODCLK system clock status */
\r
10466 /* CSSTAT[VLOCLK_ON] Bits */
\r
10467 #define VLOCLK_ON_OFS (21) /* VLOCLK_ON Offset */
\r
10468 #define VLOCLK_ON (0x00200000) /* VLOCLK system clock status */
\r
10469 /* CSSTAT[LFXTCLK_ON] Bits */
\r
10470 #define LFXTCLK_ON_OFS (22) /* LFXTCLK_ON Offset */
\r
10471 #define LFXTCLK_ON (0x00400000) /* LFXTCLK system clock status */
\r
10472 /* CSSTAT[REFOCLK_ON] Bits */
\r
10473 #define REFOCLK_ON_OFS (23) /* REFOCLK_ON Offset */
\r
10474 #define REFOCLK_ON (0x00800000) /* REFOCLK system clock status */
\r
10475 /* CSSTAT[ACLK_READY] Bits */
\r
10476 #define ACLK_READY_OFS (24) /* ACLK_READY Offset */
\r
10477 #define ACLK_READY (0x01000000) /* ACLK Ready status */
\r
10478 /* CSSTAT[MCLK_READY] Bits */
\r
10479 #define MCLK_READY_OFS (25) /* MCLK_READY Offset */
\r
10480 #define MCLK_READY (0x02000000) /* MCLK Ready status */
\r
10481 /* CSSTAT[HSMCLK_READY] Bits */
\r
10482 #define HSMCLK_READY_OFS (26) /* HSMCLK_READY Offset */
\r
10483 #define HSMCLK_READY (0x04000000) /* HSMCLK Ready status */
\r
10484 /* CSSTAT[SMCLK_READY] Bits */
\r
10485 #define SMCLK_READY_OFS (27) /* SMCLK_READY Offset */
\r
10486 #define SMCLK_READY (0x08000000) /* SMCLK Ready status */
\r
10487 /* CSSTAT[BCLK_READY] Bits */
\r
10488 #define BCLK_READY_OFS (28) /* BCLK_READY Offset */
\r
10489 #define BCLK_READY (0x10000000) /* BCLK Ready status */
\r
10490 /* CSIE[LFXTIE] Bits */
\r
10491 #define LFXTIE_OFS ( 0) /* LFXTIE Offset */
\r
10492 #define LFXTIE (0x00000001) /* LFXT oscillator fault flag interrupt enable */
\r
10493 /* CSIE[HFXTIE] Bits */
\r
10494 #define HFXTIE_OFS ( 1) /* HFXTIE Offset */
\r
10495 #define HFXTIE (0x00000002) /* HFXT oscillator fault flag interrupt enable */
\r
10496 /* CSIE[HFXT2IE] Bits */
\r
10497 #define HFXT2IE_OFS ( 2) /* HFXT2IE Offset */
\r
10498 #define HFXT2IE (0x00000004) /* HFXT2 oscillator fault flag interrupt enable */
\r
10499 /* CSIE[DCOMINIE] Bits */
\r
10500 #define DCOMINIE_OFS ( 4) /* DCOMINIE Offset */
\r
10501 #define DCOMINIE (0x00000010) /* DCO minimum fault flag interrupt enable */
\r
10502 /* CSIE[DCOMAXIE] Bits */
\r
10503 #define DCOMAXIE_OFS ( 5) /* DCOMAXIE Offset */
\r
10504 #define DCOMAXIE (0x00000020) /* DCO maximum fault flag interrupt enable */
\r
10505 /* CSIE[DCORIE] Bits */
\r
10506 #define DCORIE_OFS ( 6) /* DCORIE Offset */
\r
10507 #define DCORIE (0x00000040) /* DCO external resistor fault flag interrupt enable */
\r
10508 /* CSIE[FCNTLFIE] Bits */
\r
10509 #define FCNTLFIE_OFS ( 8) /* FCNTLFIE Offset */
\r
10510 #define FCNTLFIE (0x00000100) /* Start fault counter interrupt enable LFXT */
\r
10511 /* CSIE[FCNTHFIE] Bits */
\r
10512 #define FCNTHFIE_OFS ( 9) /* FCNTHFIE Offset */
\r
10513 #define FCNTHFIE (0x00000200) /* Start fault counter interrupt enable HFXT */
\r
10514 /* CSIE[FCNTHF2IE] Bits */
\r
10515 #define FCNTHF2IE_OFS (10) /* FCNTHF2IE Offset */
\r
10516 #define FCNTHF2IE (0x00000400) /* Start fault counter interrupt enable HFXT2 */
\r
10517 /* CSIE[PLLOOLIE] Bits */
\r
10518 #define PLLOOLIE_OFS (12) /* PLLOOLIE Offset */
\r
10519 #define PLLOOLIE (0x00001000) /* PLL out-of-lock interrupt enable */
\r
10520 /* CSIE[PLLLOSIE] Bits */
\r
10521 #define PLLLOSIE_OFS (13) /* PLLLOSIE Offset */
\r
10522 #define PLLLOSIE (0x00002000) /* PLL loss-of-signal interrupt enable */
\r
10523 /* CSIE[PLLOORIE] Bits */
\r
10524 #define PLLOORIE_OFS (14) /* PLLOORIE Offset */
\r
10525 #define PLLOORIE (0x00004000) /* PLL out-of-range interrupt enable */
\r
10526 /* CSIE[CALIE] Bits */
\r
10527 #define CALIE_OFS (15) /* CALIE Offset */
\r
10528 #define CALIE (0x00008000) /* REFCNT period counter interrupt enable */
\r
10529 /* CSIFG[LFXTIFG] Bits */
\r
10530 #define LFXTIFG_OFS ( 0) /* LFXTIFG Offset */
\r
10531 #define LFXTIFG (0x00000001) /* LFXT oscillator fault flag */
\r
10532 /* CSIFG[HFXTIFG] Bits */
\r
10533 #define HFXTIFG_OFS ( 1) /* HFXTIFG Offset */
\r
10534 #define HFXTIFG (0x00000002) /* HFXT oscillator fault flag */
\r
10535 /* CSIFG[HFXT2IFG] Bits */
\r
10536 #define HFXT2IFG_OFS ( 2) /* HFXT2IFG Offset */
\r
10537 #define HFXT2IFG (0x00000004) /* HFXT2 oscillator fault flag */
\r
10538 /* CSIFG[DCOMINIFG] Bits */
\r
10539 #define DCOMINIFG_OFS ( 4) /* DCOMINIFG Offset */
\r
10540 #define DCOMINIFG (0x00000010) /* DCO minimum fault flag */
\r
10541 /* CSIFG[DCOMAXIFG] Bits */
\r
10542 #define DCOMAXIFG_OFS ( 5) /* DCOMAXIFG Offset */
\r
10543 #define DCOMAXIFG (0x00000020) /* DCO maximum fault flag */
\r
10544 /* CSIFG[DCORIFG] Bits */
\r
10545 #define DCORIFG_OFS ( 6) /* DCORIFG Offset */
\r
10546 #define DCORIFG (0x00000040) /* DCO external resistor fault flag */
\r
10547 /* CSIFG[FCNTLFIFG] Bits */
\r
10548 #define FCNTLFIFG_OFS ( 8) /* FCNTLFIFG Offset */
\r
10549 #define FCNTLFIFG (0x00000100) /* Start fault counter interrupt flag LFXT */
\r
10550 /* CSIFG[FCNTHFIFG] Bits */
\r
10551 #define FCNTHFIFG_OFS ( 9) /* FCNTHFIFG Offset */
\r
10552 #define FCNTHFIFG (0x00000200) /* Start fault counter interrupt flag HFXT */
\r
10553 /* CSIFG[FCNTHF2IFG] Bits */
\r
10554 #define FCNTHF2IFG_OFS (11) /* FCNTHF2IFG Offset */
\r
10555 #define FCNTHF2IFG (0x00000800) /* Start fault counter interrupt flag HFXT2 */
\r
10556 /* CSIFG[PLLOOLIFG] Bits */
\r
10557 #define PLLOOLIFG_OFS (12) /* PLLOOLIFG Offset */
\r
10558 #define PLLOOLIFG (0x00001000) /* PLL out-of-lock interrupt flag */
\r
10559 /* CSIFG[PLLLOSIFG] Bits */
\r
10560 #define PLLLOSIFG_OFS (13) /* PLLLOSIFG Offset */
\r
10561 #define PLLLOSIFG (0x00002000) /* PLL loss-of-signal interrupt flag */
\r
10562 /* CSIFG[PLLOORIFG] Bits */
\r
10563 #define PLLOORIFG_OFS (14) /* PLLOORIFG Offset */
\r
10564 #define PLLOORIFG (0x00004000) /* PLL out-of-range interrupt flag */
\r
10565 /* CSIFG[CALIFG] Bits */
\r
10566 #define CALIFG_OFS (15) /* CALIFG Offset */
\r
10567 #define CALIFG (0x00008000) /* REFCNT period counter expired */
\r
10568 /* CSCLRIFG[CLR_LFXTIFG] Bits */
\r
10569 #define CLR_LFXTIFG_OFS ( 0) /* CLR_LFXTIFG Offset */
\r
10570 #define CLR_LFXTIFG (0x00000001) /* Clear LFXT oscillator fault interrupt flag */
\r
10571 /* CSCLRIFG[CLR_HFXTIFG] Bits */
\r
10572 #define CLR_HFXTIFG_OFS ( 1) /* CLR_HFXTIFG Offset */
\r
10573 #define CLR_HFXTIFG (0x00000002) /* Clear HFXT oscillator fault interrupt flag */
\r
10574 /* CSCLRIFG[CLR_HFXT2IFG] Bits */
\r
10575 #define CLR_HFXT2IFG_OFS ( 2) /* CLR_HFXT2IFG Offset */
\r
10576 #define CLR_HFXT2IFG (0x00000004) /* Clear HFXT2 oscillator fault interrupt flag */
\r
10577 /* CSCLRIFG[CLR_DCOMAXIFG] Bits */
\r
10578 #define CLR_DCOMAXIFG_OFS ( 5) /* CLR_DCOMAXIFG Offset */
\r
10579 #define CLR_DCOMAXIFG (0x00000020) /* Clear DCO maximum fault interrupt flag */
\r
10580 /* CSCLRIFG[CLR_DCORIFG] Bits */
\r
10581 #define CLR_DCORIFG_OFS ( 6) /* CLR_DCORIFG Offset */
\r
10582 #define CLR_DCORIFG (0x00000040) /* Clear DCO external resistor fault interrupt flag */
\r
10583 /* CSCLRIFG[CLR_CALIFG] Bits */
\r
10584 #define CLR_CALIFG_OFS ( 7) /* CLR_CALIFG Offset */
\r
10585 #define CLR_CALIFG (0x00000080) /* REFCNT period counter clear interrupt flag */
\r
10586 /* CSCLRIFG[CLR_DCOMINIFG] Bits */
\r
10587 #define CLR_DCOMINIFG_OFS ( 4) /* CLR_DCOMINIFG Offset */
\r
10588 #define CLR_DCOMINIFG (0x00000010) /* Clear DCO minimum fault interrupt flag */
\r
10589 /* CSCLRIFG[CLR_FCNTLFIFG] Bits */
\r
10590 #define CLR_FCNTLFIFG_OFS ( 8) /* CLR_FCNTLFIFG Offset */
\r
10591 #define CLR_FCNTLFIFG (0x00000100) /* Start fault counter clear interrupt flag LFXT */
\r
10592 /* CSCLRIFG[CLR_FCNTHFIFG] Bits */
\r
10593 #define CLR_FCNTHFIFG_OFS ( 9) /* CLR_FCNTHFIFG Offset */
\r
10594 #define CLR_FCNTHFIFG (0x00000200) /* Start fault counter clear interrupt flag HFXT */
\r
10595 /* CSCLRIFG[CLR_FCNTHF2IFG] Bits */
\r
10596 #define CLR_FCNTHF2IFG_OFS (10) /* CLR_FCNTHF2IFG Offset */
\r
10597 #define CLR_FCNTHF2IFG (0x00000400) /* Start fault counter clear interrupt flag HFXT2 */
\r
10598 /* CSCLRIFG[CLR_PLLOOLIFG] Bits */
\r
10599 #define CLR_PLLOOLIFG_OFS (12) /* CLR_PLLOOLIFG Offset */
\r
10600 #define CLR_PLLOOLIFG (0x00001000) /* PLL out-of-lock clear interrupt flag */
\r
10601 /* CSCLRIFG[CLR_PLLLOSIFG] Bits */
\r
10602 #define CLR_PLLLOSIFG_OFS (13) /* CLR_PLLLOSIFG Offset */
\r
10603 #define CLR_PLLLOSIFG (0x00002000) /* PLL loss-of-signal clear interrupt flag */
\r
10604 /* CSCLRIFG[CLR_PLLOORIFG] Bits */
\r
10605 #define CLR_PLLOORIFG_OFS (14) /* CLR_PLLOORIFG Offset */
\r
10606 #define CLR_PLLOORIFG (0x00004000) /* PLL out-of-range clear interrupt flag */
\r
10607 /* CSSETIFG[SET_LFXTIFG] Bits */
\r
10608 #define SET_LFXTIFG_OFS ( 0) /* SET_LFXTIFG Offset */
\r
10609 #define SET_LFXTIFG (0x00000001) /* Set LFXT oscillator fault interrupt flag */
\r
10610 /* CSSETIFG[SET_HFXTIFG] Bits */
\r
10611 #define SET_HFXTIFG_OFS ( 1) /* SET_HFXTIFG Offset */
\r
10612 #define SET_HFXTIFG (0x00000002) /* Set HFXT oscillator fault interrupt flag */
\r
10613 /* CSSETIFG[SET_HFXT2IFG] Bits */
\r
10614 #define SET_HFXT2IFG_OFS ( 2) /* SET_HFXT2IFG Offset */
\r
10615 #define SET_HFXT2IFG (0x00000004) /* Set HFXT2 oscillator fault interrupt flag */
\r
10616 /* CSSETIFG[SET_DCOMINIFG] Bits */
\r
10617 #define SET_DCOMINIFG_OFS ( 4) /* SET_DCOMINIFG Offset */
\r
10618 #define SET_DCOMINIFG (0x00000010) /* Set DCO minimum fault interrupt flag */
\r
10619 /* CSSETIFG[SET_DCOMAXIFG] Bits */
\r
10620 #define SET_DCOMAXIFG_OFS ( 5) /* SET_DCOMAXIFG Offset */
\r
10621 #define SET_DCOMAXIFG (0x00000020) /* Set DCO maximum fault interrupt flag */
\r
10622 /* CSSETIFG[SET_DCORIFG] Bits */
\r
10623 #define SET_DCORIFG_OFS ( 6) /* SET_DCORIFG Offset */
\r
10624 #define SET_DCORIFG (0x00000040) /* Set DCO external resistor fault interrupt flag */
\r
10625 /* CSSETIFG[SET_CALIFG] Bits */
\r
10626 #define SET_CALIFG_OFS ( 7) /* SET_CALIFG Offset */
\r
10627 #define SET_CALIFG (0x00000080) /* REFCNT period counter set interrupt flag */
\r
10628 /* CSSETIFG[SET_FCNTHFIFG] Bits */
\r
10629 #define SET_FCNTHFIFG_OFS ( 9) /* SET_FCNTHFIFG Offset */
\r
10630 #define SET_FCNTHFIFG (0x00000200) /* Start fault counter set interrupt flag HFXT */
\r
10631 /* CSSETIFG[SET_FCNTHF2IFG] Bits */
\r
10632 #define SET_FCNTHF2IFG_OFS (10) /* SET_FCNTHF2IFG Offset */
\r
10633 #define SET_FCNTHF2IFG (0x00000400) /* Start fault counter set interrupt flag HFXT2 */
\r
10634 /* CSSETIFG[SET_FCNTLFIFG] Bits */
\r
10635 #define SET_FCNTLFIFG_OFS ( 8) /* SET_FCNTLFIFG Offset */
\r
10636 #define SET_FCNTLFIFG (0x00000100) /* Start fault counter set interrupt flag LFXT */
\r
10637 /* CSSETIFG[SET_PLLOOLIFG] Bits */
\r
10638 #define SET_PLLOOLIFG_OFS (12) /* SET_PLLOOLIFG Offset */
\r
10639 #define SET_PLLOOLIFG (0x00001000) /* PLL out-of-lock set interrupt flag */
\r
10640 /* CSSETIFG[SET_PLLLOSIFG] Bits */
\r
10641 #define SET_PLLLOSIFG_OFS (13) /* SET_PLLLOSIFG Offset */
\r
10642 #define SET_PLLLOSIFG (0x00002000) /* PLL loss-of-signal set interrupt flag */
\r
10643 /* CSSETIFG[SET_PLLOORIFG] Bits */
\r
10644 #define SET_PLLOORIFG_OFS (14) /* SET_PLLOORIFG Offset */
\r
10645 #define SET_PLLOORIFG (0x00004000) /* PLL out-of-range set interrupt flag */
\r
10646 /* CSDCOERCAL[DCO_TCTRIM] Bits */
\r
10647 #define DCO_TCTRIM_OFS ( 0) /* DCO_TCTRIM Offset */
\r
10648 #define DCO_TCTRIM_M (0x00000003) /* DCO Temperature compensation Trim */
\r
10649 /* CSDCOERCAL[DCO_FTRIM] Bits */
\r
10650 #define DCO_FTRIM_OFS (16) /* DCO_FTRIM Offset */
\r
10651 #define DCO_FTRIM_M (0x07ff0000) /* DCO frequency trim */
\r
10653 /* Pre-defined bitfield values */
\r
10654 #define CSKEY_VAL (0x0000695A) /* CS control key value */
\r
10657 //*****************************************************************************
\r
10659 //*****************************************************************************
\r
10660 /* PAIN[P1IN] Bits */
\r
10661 #define P1IN_OFS ( 0) /* P1IN Offset */
\r
10662 #define P1IN_M (0x00ff) /* Port 1 Input */
\r
10663 /* PAIN[P2IN] Bits */
\r
10664 #define P2IN_OFS ( 8) /* P2IN Offset */
\r
10665 #define P2IN_M (0xff00) /* Port 2 Input */
\r
10666 /* PAOUT[P2OUT] Bits */
\r
10667 #define P2OUT_OFS ( 8) /* P2OUT Offset */
\r
10668 #define P2OUT_M (0xff00) /* Port 2 Output */
\r
10669 /* PAOUT[P1OUT] Bits */
\r
10670 #define P1OUT_OFS ( 0) /* P1OUT Offset */
\r
10671 #define P1OUT_M (0x00ff) /* Port 1 Output */
\r
10672 /* PADIR[P1DIR] Bits */
\r
10673 #define P1DIR_OFS ( 0) /* P1DIR Offset */
\r
10674 #define P1DIR_M (0x00ff) /* Port 1 Direction */
\r
10675 /* PADIR[P2DIR] Bits */
\r
10676 #define P2DIR_OFS ( 8) /* P2DIR Offset */
\r
10677 #define P2DIR_M (0xff00) /* Port 2 Direction */
\r
10678 /* PAREN[P1REN] Bits */
\r
10679 #define P1REN_OFS ( 0) /* P1REN Offset */
\r
10680 #define P1REN_M (0x00ff) /* Port 1 Resistor Enable */
\r
10681 /* PAREN[P2REN] Bits */
\r
10682 #define P2REN_OFS ( 8) /* P2REN Offset */
\r
10683 #define P2REN_M (0xff00) /* Port 2 Resistor Enable */
\r
10684 /* PADS[P1DS] Bits */
\r
10685 #define P1DS_OFS ( 0) /* P1DS Offset */
\r
10686 #define P1DS_M (0x00ff) /* Port 1 Drive Strength */
\r
10687 /* PADS[P2DS] Bits */
\r
10688 #define P2DS_OFS ( 8) /* P2DS Offset */
\r
10689 #define P2DS_M (0xff00) /* Port 2 Drive Strength */
\r
10690 /* PASEL0[P1SEL0] Bits */
\r
10691 #define P1SEL0_OFS ( 0) /* P1SEL0 Offset */
\r
10692 #define P1SEL0_M (0x00ff) /* Port 1 Select 0 */
\r
10693 /* PASEL0[P2SEL0] Bits */
\r
10694 #define P2SEL0_OFS ( 8) /* P2SEL0 Offset */
\r
10695 #define P2SEL0_M (0xff00) /* Port 2 Select 0 */
\r
10696 /* PASEL1[P1SEL1] Bits */
\r
10697 #define P1SEL1_OFS ( 0) /* P1SEL1 Offset */
\r
10698 #define P1SEL1_M (0x00ff) /* Port 1 Select 1 */
\r
10699 /* PASEL1[P2SEL1] Bits */
\r
10700 #define P2SEL1_OFS ( 8) /* P2SEL1 Offset */
\r
10701 #define P2SEL1_M (0xff00) /* Port 2 Select 1 */
\r
10702 /* P1IV[P1IV] Bits */
\r
10703 #define P1IV_OFS ( 0) /* P1IV Offset */
\r
10704 #define P1IV_M (0x001f) /* Port 1 interrupt vector value */
\r
10705 #define P1IV0 (0x0001) /* Port 1 interrupt vector value */
\r
10706 #define P1IV1 (0x0002) /* Port 1 interrupt vector value */
\r
10707 #define P1IV2 (0x0004) /* Port 1 interrupt vector value */
\r
10708 #define P1IV3 (0x0008) /* Port 1 interrupt vector value */
\r
10709 #define P1IV4 (0x0010) /* Port 1 interrupt vector value */
\r
10710 #define P1IV_0 (0x0000) /* No interrupt pending */
\r
10711 #define P1IV_2 (0x0002) /* Interrupt Source: Port 1.0 interrupt; Interrupt Flag: P1IFG0; Interrupt Priority: Highest */
\r
10712 #define P1IV_4 (0x0004) /* Interrupt Source: Port 1.1 interrupt; Interrupt Flag: P1IFG1 */
\r
10713 #define P1IV_6 (0x0006) /* Interrupt Source: Port 1.2 interrupt; Interrupt Flag: P1IFG2 */
\r
10714 #define P1IV_8 (0x0008) /* Interrupt Source: Port 1.3 interrupt; Interrupt Flag: P1IFG3 */
\r
10715 #define P1IV_10 (0x000a) /* Interrupt Source: Port 1.4 interrupt; Interrupt Flag: P1IFG4 */
\r
10716 #define P1IV_12 (0x000c) /* Interrupt Source: Port 1.5 interrupt; Interrupt Flag: P1IFG5 */
\r
10717 #define P1IV_14 (0x000e) /* Interrupt Source: Port 1.6 interrupt; Interrupt Flag: P1IFG6 */
\r
10718 #define P1IV_16 (0x0010) /* Interrupt Source: Port 1.7 interrupt; Interrupt Flag: P1IFG7; Interrupt Priority: Lowest */
\r
10719 #define P1IV__NONE (0x0000) /* No interrupt pending */
\r
10720 #define P1IV__P1IFG0 (0x0002) /* Interrupt Source: Port 1.0 interrupt; Interrupt Flag: P1IFG0; Interrupt Priority: Highest */
\r
10721 #define P1IV__P1IFG1 (0x0004) /* Interrupt Source: Port 1.1 interrupt; Interrupt Flag: P1IFG1 */
\r
10722 #define P1IV__P1IFG2 (0x0006) /* Interrupt Source: Port 1.2 interrupt; Interrupt Flag: P1IFG2 */
\r
10723 #define P1IV__P1IFG3 (0x0008) /* Interrupt Source: Port 1.3 interrupt; Interrupt Flag: P1IFG3 */
\r
10724 #define P1IV__P1IFG4 (0x000a) /* Interrupt Source: Port 1.4 interrupt; Interrupt Flag: P1IFG4 */
\r
10725 #define P1IV__P1IFG5 (0x000c) /* Interrupt Source: Port 1.5 interrupt; Interrupt Flag: P1IFG5 */
\r
10726 #define P1IV__P1IFG6 (0x000e) /* Interrupt Source: Port 1.6 interrupt; Interrupt Flag: P1IFG6 */
\r
10727 #define P1IV__P1IFG7 (0x0010) /* Interrupt Source: Port 1.7 interrupt; Interrupt Flag: P1IFG7; Interrupt Priority: Lowest */
\r
10728 /* PASELC[P1SELC] Bits */
\r
10729 #define P1SELC_OFS ( 0) /* P1SELC Offset */
\r
10730 #define P1SELC_M (0x00ff) /* Port 1 Complement Select */
\r
10731 /* PASELC[P2SELC] Bits */
\r
10732 #define P2SELC_OFS ( 8) /* P2SELC Offset */
\r
10733 #define P2SELC_M (0xff00) /* Port 2 Complement Select */
\r
10734 /* PAIES[P1IES] Bits */
\r
10735 #define P1IES_OFS ( 0) /* P1IES Offset */
\r
10736 #define P1IES_M (0x00ff) /* Port 1 Interrupt Edge Select */
\r
10737 /* PAIES[P2IES] Bits */
\r
10738 #define P2IES_OFS ( 8) /* P2IES Offset */
\r
10739 #define P2IES_M (0xff00) /* Port 2 Interrupt Edge Select */
\r
10740 /* PAIE[P1IE] Bits */
\r
10741 #define P1IE_OFS ( 0) /* P1IE Offset */
\r
10742 #define P1IE_M (0x00ff) /* Port 1 Interrupt Enable */
\r
10743 /* PAIE[P2IE] Bits */
\r
10744 #define P2IE_OFS ( 8) /* P2IE Offset */
\r
10745 #define P2IE_M (0xff00) /* Port 2 Interrupt Enable */
\r
10746 /* PAIFG[P1IFG] Bits */
\r
10747 #define P1IFG_OFS ( 0) /* P1IFG Offset */
\r
10748 #define P1IFG_M (0x00ff) /* Port 1 Interrupt Flag */
\r
10749 /* PAIFG[P2IFG] Bits */
\r
10750 #define P2IFG_OFS ( 8) /* P2IFG Offset */
\r
10751 #define P2IFG_M (0xff00) /* Port 2 Interrupt Flag */
\r
10752 /* P2IV[P2IV] Bits */
\r
10753 #define P2IV_OFS ( 0) /* P2IV Offset */
\r
10754 #define P2IV_M (0x001f) /* Port 2 interrupt vector value */
\r
10755 #define P2IV0 (0x0001) /* Port 2 interrupt vector value */
\r
10756 #define P2IV1 (0x0002) /* Port 2 interrupt vector value */
\r
10757 #define P2IV2 (0x0004) /* Port 2 interrupt vector value */
\r
10758 #define P2IV3 (0x0008) /* Port 2 interrupt vector value */
\r
10759 #define P2IV4 (0x0010) /* Port 2 interrupt vector value */
\r
10760 #define P2IV_0 (0x0000) /* No interrupt pending */
\r
10761 #define P2IV_2 (0x0002) /* Interrupt Source: Port 2.0 interrupt; Interrupt Flag: P2IFG0; Interrupt Priority: Highest */
\r
10762 #define P2IV_4 (0x0004) /* Interrupt Source: Port 2.1 interrupt; Interrupt Flag: P2IFG1 */
\r
10763 #define P2IV_6 (0x0006) /* Interrupt Source: Port 2.2 interrupt; Interrupt Flag: P2IFG2 */
\r
10764 #define P2IV_8 (0x0008) /* Interrupt Source: Port 2.3 interrupt; Interrupt Flag: P2IFG3 */
\r
10765 #define P2IV_10 (0x000a) /* Interrupt Source: Port 2.4 interrupt; Interrupt Flag: P2IFG4 */
\r
10766 #define P2IV_12 (0x000c) /* Interrupt Source: Port 2.5 interrupt; Interrupt Flag: P2IFG5 */
\r
10767 #define P2IV_14 (0x000e) /* Interrupt Source: Port 2.6 interrupt; Interrupt Flag: P2IFG6 */
\r
10768 #define P2IV_16 (0x0010) /* Interrupt Source: Port 2.7 interrupt; Interrupt Flag: P2IFG7; Interrupt Priority: Lowest */
\r
10769 #define P2IV__NONE (0x0000) /* No interrupt pending */
\r
10770 #define P2IV__P2IFG0 (0x0002) /* Interrupt Source: Port 2.0 interrupt; Interrupt Flag: P2IFG0; Interrupt Priority: Highest */
\r
10771 #define P2IV__P2IFG1 (0x0004) /* Interrupt Source: Port 2.1 interrupt; Interrupt Flag: P2IFG1 */
\r
10772 #define P2IV__P2IFG2 (0x0006) /* Interrupt Source: Port 2.2 interrupt; Interrupt Flag: P2IFG2 */
\r
10773 #define P2IV__P2IFG3 (0x0008) /* Interrupt Source: Port 2.3 interrupt; Interrupt Flag: P2IFG3 */
\r
10774 #define P2IV__P2IFG4 (0x000a) /* Interrupt Source: Port 2.4 interrupt; Interrupt Flag: P2IFG4 */
\r
10775 #define P2IV__P2IFG5 (0x000c) /* Interrupt Source: Port 2.5 interrupt; Interrupt Flag: P2IFG5 */
\r
10776 #define P2IV__P2IFG6 (0x000e) /* Interrupt Source: Port 2.6 interrupt; Interrupt Flag: P2IFG6 */
\r
10777 #define P2IV__P2IFG7 (0x0010) /* Interrupt Source: Port 2.7 interrupt; Interrupt Flag: P2IFG7; Interrupt Priority: Lowest */
\r
10778 /* PBIN[P3IN] Bits */
\r
10779 #define P3IN_OFS ( 0) /* P3IN Offset */
\r
10780 #define P3IN_M (0x00ff) /* Port 3 Input */
\r
10781 /* PBIN[P4IN] Bits */
\r
10782 #define P4IN_OFS ( 8) /* P4IN Offset */
\r
10783 #define P4IN_M (0xff00) /* Port 4 Input */
\r
10784 /* PBOUT[P3OUT] Bits */
\r
10785 #define P3OUT_OFS ( 0) /* P3OUT Offset */
\r
10786 #define P3OUT_M (0x00ff) /* Port 3 Output */
\r
10787 /* PBOUT[P4OUT] Bits */
\r
10788 #define P4OUT_OFS ( 8) /* P4OUT Offset */
\r
10789 #define P4OUT_M (0xff00) /* Port 4 Output */
\r
10790 /* PBDIR[P3DIR] Bits */
\r
10791 #define P3DIR_OFS ( 0) /* P3DIR Offset */
\r
10792 #define P3DIR_M (0x00ff) /* Port 3 Direction */
\r
10793 /* PBDIR[P4DIR] Bits */
\r
10794 #define P4DIR_OFS ( 8) /* P4DIR Offset */
\r
10795 #define P4DIR_M (0xff00) /* Port 4 Direction */
\r
10796 /* PBREN[P3REN] Bits */
\r
10797 #define P3REN_OFS ( 0) /* P3REN Offset */
\r
10798 #define P3REN_M (0x00ff) /* Port 3 Resistor Enable */
\r
10799 /* PBREN[P4REN] Bits */
\r
10800 #define P4REN_OFS ( 8) /* P4REN Offset */
\r
10801 #define P4REN_M (0xff00) /* Port 4 Resistor Enable */
\r
10802 /* PBDS[P3DS] Bits */
\r
10803 #define P3DS_OFS ( 0) /* P3DS Offset */
\r
10804 #define P3DS_M (0x00ff) /* Port 3 Drive Strength */
\r
10805 /* PBDS[P4DS] Bits */
\r
10806 #define P4DS_OFS ( 8) /* P4DS Offset */
\r
10807 #define P4DS_M (0xff00) /* Port 4 Drive Strength */
\r
10808 /* PBSEL0[P4SEL0] Bits */
\r
10809 #define P4SEL0_OFS ( 8) /* P4SEL0 Offset */
\r
10810 #define P4SEL0_M (0xff00) /* Port 4 Select 0 */
\r
10811 /* PBSEL0[P3SEL0] Bits */
\r
10812 #define P3SEL0_OFS ( 0) /* P3SEL0 Offset */
\r
10813 #define P3SEL0_M (0x00ff) /* Port 3 Select 0 */
\r
10814 /* PBSEL1[P3SEL1] Bits */
\r
10815 #define P3SEL1_OFS ( 0) /* P3SEL1 Offset */
\r
10816 #define P3SEL1_M (0x00ff) /* Port 3 Select 1 */
\r
10817 /* PBSEL1[P4SEL1] Bits */
\r
10818 #define P4SEL1_OFS ( 8) /* P4SEL1 Offset */
\r
10819 #define P4SEL1_M (0xff00) /* Port 4 Select 1 */
\r
10820 /* P3IV[P3IV] Bits */
\r
10821 #define P3IV_OFS ( 0) /* P3IV Offset */
\r
10822 #define P3IV_M (0x001f) /* Port 3 interrupt vector value */
\r
10823 #define P3IV0 (0x0001) /* Port 3 interrupt vector value */
\r
10824 #define P3IV1 (0x0002) /* Port 3 interrupt vector value */
\r
10825 #define P3IV2 (0x0004) /* Port 3 interrupt vector value */
\r
10826 #define P3IV3 (0x0008) /* Port 3 interrupt vector value */
\r
10827 #define P3IV4 (0x0010) /* Port 3 interrupt vector value */
\r
10828 #define P3IV_0 (0x0000) /* No interrupt pending */
\r
10829 #define P3IV_2 (0x0002) /* Interrupt Source: Port 3.0 interrupt; Interrupt Flag: P3IFG0; Interrupt Priority: Highest */
\r
10830 #define P3IV_4 (0x0004) /* Interrupt Source: Port 3.1 interrupt; Interrupt Flag: P3IFG1 */
\r
10831 #define P3IV_6 (0x0006) /* Interrupt Source: Port 3.2 interrupt; Interrupt Flag: P3IFG2 */
\r
10832 #define P3IV_8 (0x0008) /* Interrupt Source: Port 3.3 interrupt; Interrupt Flag: P3IFG3 */
\r
10833 #define P3IV_10 (0x000a) /* Interrupt Source: Port 3.4 interrupt; Interrupt Flag: P3IFG4 */
\r
10834 #define P3IV_12 (0x000c) /* Interrupt Source: Port 3.5 interrupt; Interrupt Flag: P3IFG5 */
\r
10835 #define P3IV_14 (0x000e) /* Interrupt Source: Port 3.6 interrupt; Interrupt Flag: P3IFG6 */
\r
10836 #define P3IV_16 (0x0010) /* Interrupt Source: Port 3.7 interrupt; Interrupt Flag: P3IFG7; Interrupt Priority: Lowest */
\r
10837 #define P3IV__NONE (0x0000) /* No interrupt pending */
\r
10838 #define P3IV__P3IFG0 (0x0002) /* Interrupt Source: Port 3.0 interrupt; Interrupt Flag: P3IFG0; Interrupt Priority: Highest */
\r
10839 #define P3IV__P3IFG1 (0x0004) /* Interrupt Source: Port 3.1 interrupt; Interrupt Flag: P3IFG1 */
\r
10840 #define P3IV__P3IFG2 (0x0006) /* Interrupt Source: Port 3.2 interrupt; Interrupt Flag: P3IFG2 */
\r
10841 #define P3IV__P3IFG3 (0x0008) /* Interrupt Source: Port 3.3 interrupt; Interrupt Flag: P3IFG3 */
\r
10842 #define P3IV__P3IFG4 (0x000a) /* Interrupt Source: Port 3.4 interrupt; Interrupt Flag: P3IFG4 */
\r
10843 #define P3IV__P3IFG5 (0x000c) /* Interrupt Source: Port 3.5 interrupt; Interrupt Flag: P3IFG5 */
\r
10844 #define P3IV__P3IFG6 (0x000e) /* Interrupt Source: Port 3.6 interrupt; Interrupt Flag: P3IFG6 */
\r
10845 #define P3IV__P3IFG7 (0x0010) /* Interrupt Source: Port 3.7 interrupt; Interrupt Flag: P3IFG7; Interrupt Priority: Lowest */
\r
10846 /* PBSELC[P3SELC] Bits */
\r
10847 #define P3SELC_OFS ( 0) /* P3SELC Offset */
\r
10848 #define P3SELC_M (0x00ff) /* Port 3 Complement Select */
\r
10849 /* PBSELC[P4SELC] Bits */
\r
10850 #define P4SELC_OFS ( 8) /* P4SELC Offset */
\r
10851 #define P4SELC_M (0xff00) /* Port 4 Complement Select */
\r
10852 /* PBIES[P3IES] Bits */
\r
10853 #define P3IES_OFS ( 0) /* P3IES Offset */
\r
10854 #define P3IES_M (0x00ff) /* Port 3 Interrupt Edge Select */
\r
10855 /* PBIES[P4IES] Bits */
\r
10856 #define P4IES_OFS ( 8) /* P4IES Offset */
\r
10857 #define P4IES_M (0xff00) /* Port 4 Interrupt Edge Select */
\r
10858 /* PBIE[P3IE] Bits */
\r
10859 #define P3IE_OFS ( 0) /* P3IE Offset */
\r
10860 #define P3IE_M (0x00ff) /* Port 3 Interrupt Enable */
\r
10861 /* PBIE[P4IE] Bits */
\r
10862 #define P4IE_OFS ( 8) /* P4IE Offset */
\r
10863 #define P4IE_M (0xff00) /* Port 4 Interrupt Enable */
\r
10864 /* PBIFG[P3IFG] Bits */
\r
10865 #define P3IFG_OFS ( 0) /* P3IFG Offset */
\r
10866 #define P3IFG_M (0x00ff) /* Port 3 Interrupt Flag */
\r
10867 /* PBIFG[P4IFG] Bits */
\r
10868 #define P4IFG_OFS ( 8) /* P4IFG Offset */
\r
10869 #define P4IFG_M (0xff00) /* Port 4 Interrupt Flag */
\r
10870 /* P4IV[P4IV] Bits */
\r
10871 #define P4IV_OFS ( 0) /* P4IV Offset */
\r
10872 #define P4IV_M (0x001f) /* Port 4 interrupt vector value */
\r
10873 #define P4IV0 (0x0001) /* Port 4 interrupt vector value */
\r
10874 #define P4IV1 (0x0002) /* Port 4 interrupt vector value */
\r
10875 #define P4IV2 (0x0004) /* Port 4 interrupt vector value */
\r
10876 #define P4IV3 (0x0008) /* Port 4 interrupt vector value */
\r
10877 #define P4IV4 (0x0010) /* Port 4 interrupt vector value */
\r
10878 #define P4IV_0 (0x0000) /* No interrupt pending */
\r
10879 #define P4IV_2 (0x0002) /* Interrupt Source: Port 4.0 interrupt; Interrupt Flag: P4IFG0; Interrupt Priority: Highest */
\r
10880 #define P4IV_4 (0x0004) /* Interrupt Source: Port 4.1 interrupt; Interrupt Flag: P4IFG1 */
\r
10881 #define P4IV_6 (0x0006) /* Interrupt Source: Port 4.2 interrupt; Interrupt Flag: P4IFG2 */
\r
10882 #define P4IV_8 (0x0008) /* Interrupt Source: Port 4.3 interrupt; Interrupt Flag: P4IFG3 */
\r
10883 #define P4IV_10 (0x000a) /* Interrupt Source: Port 4.4 interrupt; Interrupt Flag: P4IFG4 */
\r
10884 #define P4IV_12 (0x000c) /* Interrupt Source: Port 4.5 interrupt; Interrupt Flag: P4IFG5 */
\r
10885 #define P4IV_14 (0x000e) /* Interrupt Source: Port 4.6 interrupt; Interrupt Flag: P4IFG6 */
\r
10886 #define P4IV_16 (0x0010) /* Interrupt Source: Port 4.7 interrupt; Interrupt Flag: P4IFG7; Interrupt Priority: Lowest */
\r
10887 #define P4IV__NONE (0x0000) /* No interrupt pending */
\r
10888 #define P4IV__P4IFG0 (0x0002) /* Interrupt Source: Port 4.0 interrupt; Interrupt Flag: P4IFG0; Interrupt Priority: Highest */
\r
10889 #define P4IV__P4IFG1 (0x0004) /* Interrupt Source: Port 4.1 interrupt; Interrupt Flag: P4IFG1 */
\r
10890 #define P4IV__P4IFG2 (0x0006) /* Interrupt Source: Port 4.2 interrupt; Interrupt Flag: P4IFG2 */
\r
10891 #define P4IV__P4IFG3 (0x0008) /* Interrupt Source: Port 4.3 interrupt; Interrupt Flag: P4IFG3 */
\r
10892 #define P4IV__P4IFG4 (0x000a) /* Interrupt Source: Port 4.4 interrupt; Interrupt Flag: P4IFG4 */
\r
10893 #define P4IV__P4IFG5 (0x000c) /* Interrupt Source: Port 4.5 interrupt; Interrupt Flag: P4IFG5 */
\r
10894 #define P4IV__P4IFG6 (0x000e) /* Interrupt Source: Port 4.6 interrupt; Interrupt Flag: P4IFG6 */
\r
10895 #define P4IV__P4IFG7 (0x0010) /* Interrupt Source: Port 4.7 interrupt; Interrupt Flag: P4IFG7; Interrupt Priority: Lowest */
\r
10896 /* PCIN[P5IN] Bits */
\r
10897 #define P5IN_OFS ( 0) /* P5IN Offset */
\r
10898 #define P5IN_M (0x00ff) /* Port 5 Input */
\r
10899 /* PCIN[P6IN] Bits */
\r
10900 #define P6IN_OFS ( 8) /* P6IN Offset */
\r
10901 #define P6IN_M (0xff00) /* Port 6 Input */
\r
10902 /* PCOUT[P5OUT] Bits */
\r
10903 #define P5OUT_OFS ( 0) /* P5OUT Offset */
\r
10904 #define P5OUT_M (0x00ff) /* Port 5 Output */
\r
10905 /* PCOUT[P6OUT] Bits */
\r
10906 #define P6OUT_OFS ( 8) /* P6OUT Offset */
\r
10907 #define P6OUT_M (0xff00) /* Port 6 Output */
\r
10908 /* PCDIR[P5DIR] Bits */
\r
10909 #define P5DIR_OFS ( 0) /* P5DIR Offset */
\r
10910 #define P5DIR_M (0x00ff) /* Port 5 Direction */
\r
10911 /* PCDIR[P6DIR] Bits */
\r
10912 #define P6DIR_OFS ( 8) /* P6DIR Offset */
\r
10913 #define P6DIR_M (0xff00) /* Port 6 Direction */
\r
10914 /* PCREN[P5REN] Bits */
\r
10915 #define P5REN_OFS ( 0) /* P5REN Offset */
\r
10916 #define P5REN_M (0x00ff) /* Port 5 Resistor Enable */
\r
10917 /* PCREN[P6REN] Bits */
\r
10918 #define P6REN_OFS ( 8) /* P6REN Offset */
\r
10919 #define P6REN_M (0xff00) /* Port 6 Resistor Enable */
\r
10920 /* PCDS[P5DS] Bits */
\r
10921 #define P5DS_OFS ( 0) /* P5DS Offset */
\r
10922 #define P5DS_M (0x00ff) /* Port 5 Drive Strength */
\r
10923 /* PCDS[P6DS] Bits */
\r
10924 #define P6DS_OFS ( 8) /* P6DS Offset */
\r
10925 #define P6DS_M (0xff00) /* Port 6 Drive Strength */
\r
10926 /* PCSEL0[P5SEL0] Bits */
\r
10927 #define P5SEL0_OFS ( 0) /* P5SEL0 Offset */
\r
10928 #define P5SEL0_M (0x00ff) /* Port 5 Select 0 */
\r
10929 /* PCSEL0[P6SEL0] Bits */
\r
10930 #define P6SEL0_OFS ( 8) /* P6SEL0 Offset */
\r
10931 #define P6SEL0_M (0xff00) /* Port 6 Select 0 */
\r
10932 /* PCSEL1[P5SEL1] Bits */
\r
10933 #define P5SEL1_OFS ( 0) /* P5SEL1 Offset */
\r
10934 #define P5SEL1_M (0x00ff) /* Port 5 Select 1 */
\r
10935 /* PCSEL1[P6SEL1] Bits */
\r
10936 #define P6SEL1_OFS ( 8) /* P6SEL1 Offset */
\r
10937 #define P6SEL1_M (0xff00) /* Port 6 Select 1 */
\r
10938 /* P5IV[P5IV] Bits */
\r
10939 #define P5IV_OFS ( 0) /* P5IV Offset */
\r
10940 #define P5IV_M (0x001f) /* Port 5 interrupt vector value */
\r
10941 #define P5IV0 (0x0001) /* Port 5 interrupt vector value */
\r
10942 #define P5IV1 (0x0002) /* Port 5 interrupt vector value */
\r
10943 #define P5IV2 (0x0004) /* Port 5 interrupt vector value */
\r
10944 #define P5IV3 (0x0008) /* Port 5 interrupt vector value */
\r
10945 #define P5IV4 (0x0010) /* Port 5 interrupt vector value */
\r
10946 #define P5IV_0 (0x0000) /* No interrupt pending */
\r
10947 #define P5IV_2 (0x0002) /* Interrupt Source: Port 5.0 interrupt; Interrupt Flag: P5IFG0; Interrupt Priority: Highest */
\r
10948 #define P5IV_4 (0x0004) /* Interrupt Source: Port 5.1 interrupt; Interrupt Flag: P5IFG1 */
\r
10949 #define P5IV_6 (0x0006) /* Interrupt Source: Port 5.2 interrupt; Interrupt Flag: P5IFG2 */
\r
10950 #define P5IV_8 (0x0008) /* Interrupt Source: Port 5.3 interrupt; Interrupt Flag: P5IFG3 */
\r
10951 #define P5IV_10 (0x000a) /* Interrupt Source: Port 5.4 interrupt; Interrupt Flag: P5IFG4 */
\r
10952 #define P5IV_12 (0x000c) /* Interrupt Source: Port 5.5 interrupt; Interrupt Flag: P5IFG5 */
\r
10953 #define P5IV_14 (0x000e) /* Interrupt Source: Port 5.6 interrupt; Interrupt Flag: P5IFG6 */
\r
10954 #define P5IV_16 (0x0010) /* Interrupt Source: Port 5.7 interrupt; Interrupt Flag: P5IFG7; Interrupt Priority: Lowest */
\r
10955 #define P5IV__NONE (0x0000) /* No interrupt pending */
\r
10956 #define P5IV__P5IFG0 (0x0002) /* Interrupt Source: Port 5.0 interrupt; Interrupt Flag: P5IFG0; Interrupt Priority: Highest */
\r
10957 #define P5IV__P5IFG1 (0x0004) /* Interrupt Source: Port 5.1 interrupt; Interrupt Flag: P5IFG1 */
\r
10958 #define P5IV__P5IFG2 (0x0006) /* Interrupt Source: Port 5.2 interrupt; Interrupt Flag: P5IFG2 */
\r
10959 #define P5IV__P5IFG3 (0x0008) /* Interrupt Source: Port 5.3 interrupt; Interrupt Flag: P5IFG3 */
\r
10960 #define P5IV__P5IFG4 (0x000a) /* Interrupt Source: Port 5.4 interrupt; Interrupt Flag: P5IFG4 */
\r
10961 #define P5IV__P5IFG5 (0x000c) /* Interrupt Source: Port 5.5 interrupt; Interrupt Flag: P5IFG5 */
\r
10962 #define P5IV__P5IFG6 (0x000e) /* Interrupt Source: Port 5.6 interrupt; Interrupt Flag: P5IFG6 */
\r
10963 #define P5IV__P5IFG7 (0x0010) /* Interrupt Source: Port 5.7 interrupt; Interrupt Flag: P5IFG7; Interrupt Priority: Lowest */
\r
10964 /* PCSELC[P5SELC] Bits */
\r
10965 #define P5SELC_OFS ( 0) /* P5SELC Offset */
\r
10966 #define P5SELC_M (0x00ff) /* Port 5 Complement Select */
\r
10967 /* PCSELC[P6SELC] Bits */
\r
10968 #define P6SELC_OFS ( 8) /* P6SELC Offset */
\r
10969 #define P6SELC_M (0xff00) /* Port 6 Complement Select */
\r
10970 /* PCIES[P5IES] Bits */
\r
10971 #define P5IES_OFS ( 0) /* P5IES Offset */
\r
10972 #define P5IES_M (0x00ff) /* Port 5 Interrupt Edge Select */
\r
10973 /* PCIES[P6IES] Bits */
\r
10974 #define P6IES_OFS ( 8) /* P6IES Offset */
\r
10975 #define P6IES_M (0xff00) /* Port 6 Interrupt Edge Select */
\r
10976 /* PCIE[P5IE] Bits */
\r
10977 #define P5IE_OFS ( 0) /* P5IE Offset */
\r
10978 #define P5IE_M (0x00ff) /* Port 5 Interrupt Enable */
\r
10979 /* PCIE[P6IE] Bits */
\r
10980 #define P6IE_OFS ( 8) /* P6IE Offset */
\r
10981 #define P6IE_M (0xff00) /* Port 6 Interrupt Enable */
\r
10982 /* PCIFG[P5IFG] Bits */
\r
10983 #define P5IFG_OFS ( 0) /* P5IFG Offset */
\r
10984 #define P5IFG_M (0x00ff) /* Port 5 Interrupt Flag */
\r
10985 /* PCIFG[P6IFG] Bits */
\r
10986 #define P6IFG_OFS ( 8) /* P6IFG Offset */
\r
10987 #define P6IFG_M (0xff00) /* Port 6 Interrupt Flag */
\r
10988 /* P6IV[P6IV] Bits */
\r
10989 #define P6IV_OFS ( 0) /* P6IV Offset */
\r
10990 #define P6IV_M (0x001f) /* Port 6 interrupt vector value */
\r
10991 #define P6IV0 (0x0001) /* Port 6 interrupt vector value */
\r
10992 #define P6IV1 (0x0002) /* Port 6 interrupt vector value */
\r
10993 #define P6IV2 (0x0004) /* Port 6 interrupt vector value */
\r
10994 #define P6IV3 (0x0008) /* Port 6 interrupt vector value */
\r
10995 #define P6IV4 (0x0010) /* Port 6 interrupt vector value */
\r
10996 #define P6IV_0 (0x0000) /* No interrupt pending */
\r
10997 #define P6IV_2 (0x0002) /* Interrupt Source: Port 6.0 interrupt; Interrupt Flag: P6IFG0; Interrupt Priority: Highest */
\r
10998 #define P6IV_4 (0x0004) /* Interrupt Source: Port 6.1 interrupt; Interrupt Flag: P6IFG1 */
\r
10999 #define P6IV_6 (0x0006) /* Interrupt Source: Port 6.2 interrupt; Interrupt Flag: P6IFG2 */
\r
11000 #define P6IV_8 (0x0008) /* Interrupt Source: Port 6.3 interrupt; Interrupt Flag: P6IFG3 */
\r
11001 #define P6IV_10 (0x000a) /* Interrupt Source: Port 6.4 interrupt; Interrupt Flag: P6IFG4 */
\r
11002 #define P6IV_12 (0x000c) /* Interrupt Source: Port 6.5 interrupt; Interrupt Flag: P6IFG5 */
\r
11003 #define P6IV_14 (0x000e) /* Interrupt Source: Port 6.6 interrupt; Interrupt Flag: P6IFG6 */
\r
11004 #define P6IV_16 (0x0010) /* Interrupt Source: Port 6.7 interrupt; Interrupt Flag: P6IFG7; Interrupt Priority: Lowest */
\r
11005 #define P6IV__NONE (0x0000) /* No interrupt pending */
\r
11006 #define P6IV__P6IFG0 (0x0002) /* Interrupt Source: Port 6.0 interrupt; Interrupt Flag: P6IFG0; Interrupt Priority: Highest */
\r
11007 #define P6IV__P6IFG1 (0x0004) /* Interrupt Source: Port 6.1 interrupt; Interrupt Flag: P6IFG1 */
\r
11008 #define P6IV__P6IFG2 (0x0006) /* Interrupt Source: Port 6.2 interrupt; Interrupt Flag: P6IFG2 */
\r
11009 #define P6IV__P6IFG3 (0x0008) /* Interrupt Source: Port 6.3 interrupt; Interrupt Flag: P6IFG3 */
\r
11010 #define P6IV__P6IFG4 (0x000a) /* Interrupt Source: Port 6.4 interrupt; Interrupt Flag: P6IFG4 */
\r
11011 #define P6IV__P6IFG5 (0x000c) /* Interrupt Source: Port 6.5 interrupt; Interrupt Flag: P6IFG5 */
\r
11012 #define P6IV__P6IFG6 (0x000e) /* Interrupt Source: Port 6.6 interrupt; Interrupt Flag: P6IFG6 */
\r
11013 #define P6IV__P6IFG7 (0x0010) /* Interrupt Source: Port 6.7 interrupt; Interrupt Flag: P6IFG7; Interrupt Priority: Lowest */
\r
11014 /* PDIN[P7IN] Bits */
\r
11015 #define P7IN_OFS ( 0) /* P7IN Offset */
\r
11016 #define P7IN_M (0x00ff) /* Port 7 Input */
\r
11017 /* PDIN[P8IN] Bits */
\r
11018 #define P8IN_OFS ( 8) /* P8IN Offset */
\r
11019 #define P8IN_M (0xff00) /* Port 8 Input */
\r
11020 /* PDOUT[P7OUT] Bits */
\r
11021 #define P7OUT_OFS ( 0) /* P7OUT Offset */
\r
11022 #define P7OUT_M (0x00ff) /* Port 7 Output */
\r
11023 /* PDOUT[P8OUT] Bits */
\r
11024 #define P8OUT_OFS ( 8) /* P8OUT Offset */
\r
11025 #define P8OUT_M (0xff00) /* Port 8 Output */
\r
11026 /* PDDIR[P7DIR] Bits */
\r
11027 #define P7DIR_OFS ( 0) /* P7DIR Offset */
\r
11028 #define P7DIR_M (0x00ff) /* Port 7 Direction */
\r
11029 /* PDDIR[P8DIR] Bits */
\r
11030 #define P8DIR_OFS ( 8) /* P8DIR Offset */
\r
11031 #define P8DIR_M (0xff00) /* Port 8 Direction */
\r
11032 /* PDREN[P7REN] Bits */
\r
11033 #define P7REN_OFS ( 0) /* P7REN Offset */
\r
11034 #define P7REN_M (0x00ff) /* Port 7 Resistor Enable */
\r
11035 /* PDREN[P8REN] Bits */
\r
11036 #define P8REN_OFS ( 8) /* P8REN Offset */
\r
11037 #define P8REN_M (0xff00) /* Port 8 Resistor Enable */
\r
11038 /* PDDS[P7DS] Bits */
\r
11039 #define P7DS_OFS ( 0) /* P7DS Offset */
\r
11040 #define P7DS_M (0x00ff) /* Port 7 Drive Strength */
\r
11041 /* PDDS[P8DS] Bits */
\r
11042 #define P8DS_OFS ( 8) /* P8DS Offset */
\r
11043 #define P8DS_M (0xff00) /* Port 8 Drive Strength */
\r
11044 /* PDSEL0[P7SEL0] Bits */
\r
11045 #define P7SEL0_OFS ( 0) /* P7SEL0 Offset */
\r
11046 #define P7SEL0_M (0x00ff) /* Port 7 Select 0 */
\r
11047 /* PDSEL0[P8SEL0] Bits */
\r
11048 #define P8SEL0_OFS ( 8) /* P8SEL0 Offset */
\r
11049 #define P8SEL0_M (0xff00) /* Port 8 Select 0 */
\r
11050 /* PDSEL1[P7SEL1] Bits */
\r
11051 #define P7SEL1_OFS ( 0) /* P7SEL1 Offset */
\r
11052 #define P7SEL1_M (0x00ff) /* Port 7 Select 1 */
\r
11053 /* PDSEL1[P8SEL1] Bits */
\r
11054 #define P8SEL1_OFS ( 8) /* P8SEL1 Offset */
\r
11055 #define P8SEL1_M (0xff00) /* Port 8 Select 1 */
\r
11056 /* P7IV[P7IV] Bits */
\r
11057 #define P7IV_OFS ( 0) /* P7IV Offset */
\r
11058 #define P7IV_M (0x001f) /* Port 7 interrupt vector value */
\r
11059 #define P7IV0 (0x0001) /* Port 7 interrupt vector value */
\r
11060 #define P7IV1 (0x0002) /* Port 7 interrupt vector value */
\r
11061 #define P7IV2 (0x0004) /* Port 7 interrupt vector value */
\r
11062 #define P7IV3 (0x0008) /* Port 7 interrupt vector value */
\r
11063 #define P7IV4 (0x0010) /* Port 7 interrupt vector value */
\r
11064 #define P7IV_0 (0x0000) /* No interrupt pending */
\r
11065 #define P7IV_2 (0x0002) /* Interrupt Source: Port 7.0 interrupt; Interrupt Flag: P7IFG0; Interrupt Priority: Highest */
\r
11066 #define P7IV_4 (0x0004) /* Interrupt Source: Port 7.1 interrupt; Interrupt Flag: P7IFG1 */
\r
11067 #define P7IV_6 (0x0006) /* Interrupt Source: Port 7.2 interrupt; Interrupt Flag: P7IFG2 */
\r
11068 #define P7IV_8 (0x0008) /* Interrupt Source: Port 7.3 interrupt; Interrupt Flag: P7IFG3 */
\r
11069 #define P7IV_10 (0x000a) /* Interrupt Source: Port 7.4 interrupt; Interrupt Flag: P7IFG4 */
\r
11070 #define P7IV_12 (0x000c) /* Interrupt Source: Port 7.5 interrupt; Interrupt Flag: P7IFG5 */
\r
11071 #define P7IV_14 (0x000e) /* Interrupt Source: Port 7.6 interrupt; Interrupt Flag: P7IFG6 */
\r
11072 #define P7IV_16 (0x0010) /* Interrupt Source: Port 7.7 interrupt; Interrupt Flag: P7IFG7; Interrupt Priority: Lowest */
\r
11073 #define P7IV__NONE (0x0000) /* No interrupt pending */
\r
11074 #define P7IV__P7IFG0 (0x0002) /* Interrupt Source: Port 7.0 interrupt; Interrupt Flag: P7IFG0; Interrupt Priority: Highest */
\r
11075 #define P7IV__P7IFG1 (0x0004) /* Interrupt Source: Port 7.1 interrupt; Interrupt Flag: P7IFG1 */
\r
11076 #define P7IV__P7IFG2 (0x0006) /* Interrupt Source: Port 7.2 interrupt; Interrupt Flag: P7IFG2 */
\r
11077 #define P7IV__P7IFG3 (0x0008) /* Interrupt Source: Port 7.3 interrupt; Interrupt Flag: P7IFG3 */
\r
11078 #define P7IV__P7IFG4 (0x000a) /* Interrupt Source: Port 7.4 interrupt; Interrupt Flag: P7IFG4 */
\r
11079 #define P7IV__P7IFG5 (0x000c) /* Interrupt Source: Port 7.5 interrupt; Interrupt Flag: P7IFG5 */
\r
11080 #define P7IV__P7IFG6 (0x000e) /* Interrupt Source: Port 7.6 interrupt; Interrupt Flag: P7IFG6 */
\r
11081 #define P7IV__P7IFG7 (0x0010) /* Interrupt Source: Port 7.7 interrupt; Interrupt Flag: P7IFG7; Interrupt Priority: Lowest */
\r
11082 /* PDSELC[P7SELC] Bits */
\r
11083 #define P7SELC_OFS ( 0) /* P7SELC Offset */
\r
11084 #define P7SELC_M (0x00ff) /* Port 7 Complement Select */
\r
11085 /* PDSELC[P8SELC] Bits */
\r
11086 #define P8SELC_OFS ( 8) /* P8SELC Offset */
\r
11087 #define P8SELC_M (0xff00) /* Port 8 Complement Select */
\r
11088 /* PDIES[P7IES] Bits */
\r
11089 #define P7IES_OFS ( 0) /* P7IES Offset */
\r
11090 #define P7IES_M (0x00ff) /* Port 7 Interrupt Edge Select */
\r
11091 /* PDIES[P8IES] Bits */
\r
11092 #define P8IES_OFS ( 8) /* P8IES Offset */
\r
11093 #define P8IES_M (0xff00) /* Port 8 Interrupt Edge Select */
\r
11094 /* PDIE[P7IE] Bits */
\r
11095 #define P7IE_OFS ( 0) /* P7IE Offset */
\r
11096 #define P7IE_M (0x00ff) /* Port 7 Interrupt Enable */
\r
11097 /* PDIE[P8IE] Bits */
\r
11098 #define P8IE_OFS ( 8) /* P8IE Offset */
\r
11099 #define P8IE_M (0xff00) /* Port 8 Interrupt Enable */
\r
11100 /* PDIFG[P7IFG] Bits */
\r
11101 #define P7IFG_OFS ( 0) /* P7IFG Offset */
\r
11102 #define P7IFG_M (0x00ff) /* Port 7 Interrupt Flag */
\r
11103 /* PDIFG[P8IFG] Bits */
\r
11104 #define P8IFG_OFS ( 8) /* P8IFG Offset */
\r
11105 #define P8IFG_M (0xff00) /* Port 8 Interrupt Flag */
\r
11106 /* P8IV[P8IV] Bits */
\r
11107 #define P8IV_OFS ( 0) /* P8IV Offset */
\r
11108 #define P8IV_M (0x001f) /* Port 8 interrupt vector value */
\r
11109 #define P8IV0 (0x0001) /* Port 8 interrupt vector value */
\r
11110 #define P8IV1 (0x0002) /* Port 8 interrupt vector value */
\r
11111 #define P8IV2 (0x0004) /* Port 8 interrupt vector value */
\r
11112 #define P8IV3 (0x0008) /* Port 8 interrupt vector value */
\r
11113 #define P8IV4 (0x0010) /* Port 8 interrupt vector value */
\r
11114 #define P8IV_0 (0x0000) /* No interrupt pending */
\r
11115 #define P8IV_2 (0x0002) /* Interrupt Source: Port 8.0 interrupt; Interrupt Flag: P8IFG0; Interrupt Priority: Highest */
\r
11116 #define P8IV_4 (0x0004) /* Interrupt Source: Port 8.1 interrupt; Interrupt Flag: P8IFG1 */
\r
11117 #define P8IV_6 (0x0006) /* Interrupt Source: Port 8.2 interrupt; Interrupt Flag: P8IFG2 */
\r
11118 #define P8IV_8 (0x0008) /* Interrupt Source: Port 8.3 interrupt; Interrupt Flag: P8IFG3 */
\r
11119 #define P8IV_10 (0x000a) /* Interrupt Source: Port 8.4 interrupt; Interrupt Flag: P8IFG4 */
\r
11120 #define P8IV_12 (0x000c) /* Interrupt Source: Port 8.5 interrupt; Interrupt Flag: P8IFG5 */
\r
11121 #define P8IV_14 (0x000e) /* Interrupt Source: Port 8.6 interrupt; Interrupt Flag: P8IFG6 */
\r
11122 #define P8IV_16 (0x0010) /* Interrupt Source: Port 8.7 interrupt; Interrupt Flag: P8IFG7; Interrupt Priority: Lowest */
\r
11123 #define P8IV__NONE (0x0000) /* No interrupt pending */
\r
11124 #define P8IV__P8IFG0 (0x0002) /* Interrupt Source: Port 8.0 interrupt; Interrupt Flag: P8IFG0; Interrupt Priority: Highest */
\r
11125 #define P8IV__P8IFG1 (0x0004) /* Interrupt Source: Port 8.1 interrupt; Interrupt Flag: P8IFG1 */
\r
11126 #define P8IV__P8IFG2 (0x0006) /* Interrupt Source: Port 8.2 interrupt; Interrupt Flag: P8IFG2 */
\r
11127 #define P8IV__P8IFG3 (0x0008) /* Interrupt Source: Port 8.3 interrupt; Interrupt Flag: P8IFG3 */
\r
11128 #define P8IV__P8IFG4 (0x000a) /* Interrupt Source: Port 8.4 interrupt; Interrupt Flag: P8IFG4 */
\r
11129 #define P8IV__P8IFG5 (0x000c) /* Interrupt Source: Port 8.5 interrupt; Interrupt Flag: P8IFG5 */
\r
11130 #define P8IV__P8IFG6 (0x000e) /* Interrupt Source: Port 8.6 interrupt; Interrupt Flag: P8IFG6 */
\r
11131 #define P8IV__P8IFG7 (0x0010) /* Interrupt Source: Port 8.7 interrupt; Interrupt Flag: P8IFG7; Interrupt Priority: Lowest */
\r
11132 /* PEIN[P9IN] Bits */
\r
11133 #define P9IN_OFS ( 0) /* P9IN Offset */
\r
11134 #define P9IN_M (0x00ff) /* Port 9 Input */
\r
11135 /* PEIN[P10IN] Bits */
\r
11136 #define P10IN_OFS ( 8) /* P10IN Offset */
\r
11137 #define P10IN_M (0xff00) /* Port 10 Input */
\r
11138 /* PEOUT[P9OUT] Bits */
\r
11139 #define P9OUT_OFS ( 0) /* P9OUT Offset */
\r
11140 #define P9OUT_M (0x00ff) /* Port 9 Output */
\r
11141 /* PEOUT[P10OUT] Bits */
\r
11142 #define P10OUT_OFS ( 8) /* P10OUT Offset */
\r
11143 #define P10OUT_M (0xff00) /* Port 10 Output */
\r
11144 /* PEDIR[P9DIR] Bits */
\r
11145 #define P9DIR_OFS ( 0) /* P9DIR Offset */
\r
11146 #define P9DIR_M (0x00ff) /* Port 9 Direction */
\r
11147 /* PEDIR[P10DIR] Bits */
\r
11148 #define P10DIR_OFS ( 8) /* P10DIR Offset */
\r
11149 #define P10DIR_M (0xff00) /* Port 10 Direction */
\r
11150 /* PEREN[P9REN] Bits */
\r
11151 #define P9REN_OFS ( 0) /* P9REN Offset */
\r
11152 #define P9REN_M (0x00ff) /* Port 9 Resistor Enable */
\r
11153 /* PEREN[P10REN] Bits */
\r
11154 #define P10REN_OFS ( 8) /* P10REN Offset */
\r
11155 #define P10REN_M (0xff00) /* Port 10 Resistor Enable */
\r
11156 /* PEDS[P9DS] Bits */
\r
11157 #define P9DS_OFS ( 0) /* P9DS Offset */
\r
11158 #define P9DS_M (0x00ff) /* Port 9 Drive Strength */
\r
11159 /* PEDS[P10DS] Bits */
\r
11160 #define P10DS_OFS ( 8) /* P10DS Offset */
\r
11161 #define P10DS_M (0xff00) /* Port 10 Drive Strength */
\r
11162 /* PESEL0[P9SEL0] Bits */
\r
11163 #define P9SEL0_OFS ( 0) /* P9SEL0 Offset */
\r
11164 #define P9SEL0_M (0x00ff) /* Port 9 Select 0 */
\r
11165 /* PESEL0[P10SEL0] Bits */
\r
11166 #define P10SEL0_OFS ( 8) /* P10SEL0 Offset */
\r
11167 #define P10SEL0_M (0xff00) /* Port 10 Select 0 */
\r
11168 /* PESEL1[P9SEL1] Bits */
\r
11169 #define P9SEL1_OFS ( 0) /* P9SEL1 Offset */
\r
11170 #define P9SEL1_M (0x00ff) /* Port 9 Select 1 */
\r
11171 /* PESEL1[P10SEL1] Bits */
\r
11172 #define P10SEL1_OFS ( 8) /* P10SEL1 Offset */
\r
11173 #define P10SEL1_M (0xff00) /* Port 10 Select 1 */
\r
11174 /* P9IV[P9IV] Bits */
\r
11175 #define P9IV_OFS ( 0) /* P9IV Offset */
\r
11176 #define P9IV_M (0x001f) /* Port 9 interrupt vector value */
\r
11177 #define P9IV0 (0x0001) /* Port 9 interrupt vector value */
\r
11178 #define P9IV1 (0x0002) /* Port 9 interrupt vector value */
\r
11179 #define P9IV2 (0x0004) /* Port 9 interrupt vector value */
\r
11180 #define P9IV3 (0x0008) /* Port 9 interrupt vector value */
\r
11181 #define P9IV4 (0x0010) /* Port 9 interrupt vector value */
\r
11182 #define P9IV_0 (0x0000) /* No interrupt pending */
\r
11183 #define P9IV_2 (0x0002) /* Interrupt Source: Port 9.0 interrupt; Interrupt Flag: P9IFG0; Interrupt Priority: Highest */
\r
11184 #define P9IV_4 (0x0004) /* Interrupt Source: Port 9.1 interrupt; Interrupt Flag: P9IFG1 */
\r
11185 #define P9IV_6 (0x0006) /* Interrupt Source: Port 9.2 interrupt; Interrupt Flag: P9IFG2 */
\r
11186 #define P9IV_8 (0x0008) /* Interrupt Source: Port 9.3 interrupt; Interrupt Flag: P9IFG3 */
\r
11187 #define P9IV_10 (0x000a) /* Interrupt Source: Port 9.4 interrupt; Interrupt Flag: P9IFG4 */
\r
11188 #define P9IV_12 (0x000c) /* Interrupt Source: Port 9.5 interrupt; Interrupt Flag: P9IFG5 */
\r
11189 #define P9IV_14 (0x000e) /* Interrupt Source: Port 9.6 interrupt; Interrupt Flag: P9IFG6 */
\r
11190 #define P9IV_16 (0x0010) /* Interrupt Source: Port 9.7 interrupt; Interrupt Flag: P9IFG7; Interrupt Priority: Lowest */
\r
11191 #define P9IV__NONE (0x0000) /* No interrupt pending */
\r
11192 #define P9IV__P9IFG0 (0x0002) /* Interrupt Source: Port 9.0 interrupt; Interrupt Flag: P9IFG0; Interrupt Priority: Highest */
\r
11193 #define P9IV__P9IFG1 (0x0004) /* Interrupt Source: Port 9.1 interrupt; Interrupt Flag: P9IFG1 */
\r
11194 #define P9IV__P9IFG2 (0x0006) /* Interrupt Source: Port 9.2 interrupt; Interrupt Flag: P9IFG2 */
\r
11195 #define P9IV__P9IFG3 (0x0008) /* Interrupt Source: Port 9.3 interrupt; Interrupt Flag: P9IFG3 */
\r
11196 #define P9IV__P9IFG4 (0x000a) /* Interrupt Source: Port 9.4 interrupt; Interrupt Flag: P9IFG4 */
\r
11197 #define P9IV__P9IFG5 (0x000c) /* Interrupt Source: Port 9.5 interrupt; Interrupt Flag: P9IFG5 */
\r
11198 #define P9IV__P9IFG6 (0x000e) /* Interrupt Source: Port 9.6 interrupt; Interrupt Flag: P9IFG6 */
\r
11199 #define P9IV__P9IFG7 (0x0010) /* Interrupt Source: Port 9.7 interrupt; Interrupt Flag: P9IFG7; Interrupt Priority: Lowest */
\r
11200 /* PESELC[P9SELC] Bits */
\r
11201 #define P9SELC_OFS ( 0) /* P9SELC Offset */
\r
11202 #define P9SELC_M (0x00ff) /* Port 9 Complement Select */
\r
11203 /* PESELC[P10SELC] Bits */
\r
11204 #define P10SELC_OFS ( 8) /* P10SELC Offset */
\r
11205 #define P10SELC_M (0xff00) /* Port 10 Complement Select */
\r
11206 /* PEIES[P9IES] Bits */
\r
11207 #define P9IES_OFS ( 0) /* P9IES Offset */
\r
11208 #define P9IES_M (0x00ff) /* Port 9 Interrupt Edge Select */
\r
11209 /* PEIES[P10IES] Bits */
\r
11210 #define P10IES_OFS ( 8) /* P10IES Offset */
\r
11211 #define P10IES_M (0xff00) /* Port 10 Interrupt Edge Select */
\r
11212 /* PEIE[P9IE] Bits */
\r
11213 #define P9IE_OFS ( 0) /* P9IE Offset */
\r
11214 #define P9IE_M (0x00ff) /* Port 9 Interrupt Enable */
\r
11215 /* PEIE[P10IE] Bits */
\r
11216 #define P10IE_OFS ( 8) /* P10IE Offset */
\r
11217 #define P10IE_M (0xff00) /* Port 10 Interrupt Enable */
\r
11218 /* PEIFG[P9IFG] Bits */
\r
11219 #define P9IFG_OFS ( 0) /* P9IFG Offset */
\r
11220 #define P9IFG_M (0x00ff) /* Port 9 Interrupt Flag */
\r
11221 /* PEIFG[P10IFG] Bits */
\r
11222 #define P10IFG_OFS ( 8) /* P10IFG Offset */
\r
11223 #define P10IFG_M (0xff00) /* Port 10 Interrupt Flag */
\r
11224 /* P10IV[P10IV] Bits */
\r
11225 #define P10IV_OFS ( 0) /* P10IV Offset */
\r
11226 #define P10IV_M (0x001f) /* Port 10 interrupt vector value */
\r
11227 #define P10IV0 (0x0001) /* Port 10 interrupt vector value */
\r
11228 #define P10IV1 (0x0002) /* Port 10 interrupt vector value */
\r
11229 #define P10IV2 (0x0004) /* Port 10 interrupt vector value */
\r
11230 #define P10IV3 (0x0008) /* Port 10 interrupt vector value */
\r
11231 #define P10IV4 (0x0010) /* Port 10 interrupt vector value */
\r
11232 #define P10IV_0 (0x0000) /* No interrupt pending */
\r
11233 #define P10IV_2 (0x0002) /* Interrupt Source: Port 10.0 interrupt; Interrupt Flag: P10IFG0; Interrupt Priority: Highest */
\r
11234 #define P10IV_4 (0x0004) /* Interrupt Source: Port 10.1 interrupt; Interrupt Flag: P10IFG1 */
\r
11235 #define P10IV_6 (0x0006) /* Interrupt Source: Port 10.2 interrupt; Interrupt Flag: P10IFG2 */
\r
11236 #define P10IV_8 (0x0008) /* Interrupt Source: Port 10.3 interrupt; Interrupt Flag: P10IFG3 */
\r
11237 #define P10IV_10 (0x000a) /* Interrupt Source: Port 10.4 interrupt; Interrupt Flag: P10IFG4 */
\r
11238 #define P10IV_12 (0x000c) /* Interrupt Source: Port 10.5 interrupt; Interrupt Flag: P10IFG5 */
\r
11239 #define P10IV_14 (0x000e) /* Interrupt Source: Port 10.6 interrupt; Interrupt Flag: P10IFG6 */
\r
11240 #define P10IV_16 (0x0010) /* Interrupt Source: Port 10.7 interrupt; Interrupt Flag: P10IFG7; Interrupt Priority: Lowest */
\r
11241 #define P10IV__NONE (0x0000) /* No interrupt pending */
\r
11242 #define P10IV__P10IFG0 (0x0002) /* Interrupt Source: Port 10.0 interrupt; Interrupt Flag: P10IFG0; Interrupt Priority: Highest */
\r
11243 #define P10IV__P10IFG1 (0x0004) /* Interrupt Source: Port 10.1 interrupt; Interrupt Flag: P10IFG1 */
\r
11244 #define P10IV__P10IFG2 (0x0006) /* Interrupt Source: Port 10.2 interrupt; Interrupt Flag: P10IFG2 */
\r
11245 #define P10IV__P10IFG3 (0x0008) /* Interrupt Source: Port 10.3 interrupt; Interrupt Flag: P10IFG3 */
\r
11246 #define P10IV__P10IFG4 (0x000a) /* Interrupt Source: Port 10.4 interrupt; Interrupt Flag: P10IFG4 */
\r
11247 #define P10IV__P10IFG5 (0x000c) /* Interrupt Source: Port 10.5 interrupt; Interrupt Flag: P10IFG5 */
\r
11248 #define P10IV__P10IFG6 (0x000e) /* Interrupt Source: Port 10.6 interrupt; Interrupt Flag: P10IFG6 */
\r
11249 #define P10IV__P10IFG7 (0x0010) /* Interrupt Source: Port 10.7 interrupt; Interrupt Flag: P10IFG7; Interrupt Priority: Lowest */
\r
11252 //*****************************************************************************
\r
11254 //*****************************************************************************
\r
11255 /* DMA_DEVICE_CFG[DMA_DEVICE_CFG_NUM_DMA_CHANNELS] Bits */
\r
11256 #define DMA_DEVICE_CFG_NUM_DMA_CHANNELS_OFS ( 0) /* NUM_DMA_CHANNELS Offset */
\r
11257 #define DMA_DEVICE_CFG_NUM_DMA_CHANNELS_M (0x000000ff) /* Number of DMA channels available */
\r
11258 /* DMA_DEVICE_CFG[DMA_DEVICE_CFG_NUM_SRC_PER_CHANNEL] Bits */
\r
11259 #define DMA_DEVICE_CFG_NUM_SRC_PER_CHANNEL_OFS ( 8) /* NUM_SRC_PER_CHANNEL Offset */
\r
11260 #define DMA_DEVICE_CFG_NUM_SRC_PER_CHANNEL_M (0x0000ff00) /* Number of DMA sources per channel */
\r
11261 /* DMA_SW_CHTRIG[DMA_SW_CHTRIG_CH0] Bits */
\r
11262 #define DMA_SW_CHTRIG_CH0_OFS ( 0) /* CH0 Offset */
\r
11263 #define DMA_SW_CHTRIG_CH0 (0x00000001) /* Write 1, triggers DMA_CHANNEL0 */
\r
11264 /* DMA_SW_CHTRIG[DMA_SW_CHTRIG_CH1] Bits */
\r
11265 #define DMA_SW_CHTRIG_CH1_OFS ( 1) /* CH1 Offset */
\r
11266 #define DMA_SW_CHTRIG_CH1 (0x00000002) /* Write 1, triggers DMA_CHANNEL1 */
\r
11267 /* DMA_SW_CHTRIG[DMA_SW_CHTRIG_CH2] Bits */
\r
11268 #define DMA_SW_CHTRIG_CH2_OFS ( 2) /* CH2 Offset */
\r
11269 #define DMA_SW_CHTRIG_CH2 (0x00000004) /* Write 1, triggers DMA_CHANNEL2 */
\r
11270 /* DMA_SW_CHTRIG[DMA_SW_CHTRIG_CH3] Bits */
\r
11271 #define DMA_SW_CHTRIG_CH3_OFS ( 3) /* CH3 Offset */
\r
11272 #define DMA_SW_CHTRIG_CH3 (0x00000008) /* Write 1, triggers DMA_CHANNEL3 */
\r
11273 /* DMA_SW_CHTRIG[DMA_SW_CHTRIG_CH4] Bits */
\r
11274 #define DMA_SW_CHTRIG_CH4_OFS ( 4) /* CH4 Offset */
\r
11275 #define DMA_SW_CHTRIG_CH4 (0x00000010) /* Write 1, triggers DMA_CHANNEL4 */
\r
11276 /* DMA_SW_CHTRIG[DMA_SW_CHTRIG_CH5] Bits */
\r
11277 #define DMA_SW_CHTRIG_CH5_OFS ( 5) /* CH5 Offset */
\r
11278 #define DMA_SW_CHTRIG_CH5 (0x00000020) /* Write 1, triggers DMA_CHANNEL5 */
\r
11279 /* DMA_SW_CHTRIG[DMA_SW_CHTRIG_CH6] Bits */
\r
11280 #define DMA_SW_CHTRIG_CH6_OFS ( 6) /* CH6 Offset */
\r
11281 #define DMA_SW_CHTRIG_CH6 (0x00000040) /* Write 1, triggers DMA_CHANNEL6 */
\r
11282 /* DMA_SW_CHTRIG[DMA_SW_CHTRIG_CH7] Bits */
\r
11283 #define DMA_SW_CHTRIG_CH7_OFS ( 7) /* CH7 Offset */
\r
11284 #define DMA_SW_CHTRIG_CH7 (0x00000080) /* Write 1, triggers DMA_CHANNEL7 */
\r
11285 /* DMA_SW_CHTRIG[DMA_SW_CHTRIG_CH8] Bits */
\r
11286 #define DMA_SW_CHTRIG_CH8_OFS ( 8) /* CH8 Offset */
\r
11287 #define DMA_SW_CHTRIG_CH8 (0x00000100) /* Write 1, triggers DMA_CHANNEL8 */
\r
11288 /* DMA_SW_CHTRIG[DMA_SW_CHTRIG_CH9] Bits */
\r
11289 #define DMA_SW_CHTRIG_CH9_OFS ( 9) /* CH9 Offset */
\r
11290 #define DMA_SW_CHTRIG_CH9 (0x00000200) /* Write 1, triggers DMA_CHANNEL9 */
\r
11291 /* DMA_SW_CHTRIG[DMA_SW_CHTRIG_CH10] Bits */
\r
11292 #define DMA_SW_CHTRIG_CH10_OFS (10) /* CH10 Offset */
\r
11293 #define DMA_SW_CHTRIG_CH10 (0x00000400) /* Write 1, triggers DMA_CHANNEL10 */
\r
11294 /* DMA_SW_CHTRIG[DMA_SW_CHTRIG_CH11] Bits */
\r
11295 #define DMA_SW_CHTRIG_CH11_OFS (11) /* CH11 Offset */
\r
11296 #define DMA_SW_CHTRIG_CH11 (0x00000800) /* Write 1, triggers DMA_CHANNEL11 */
\r
11297 /* DMA_SW_CHTRIG[DMA_SW_CHTRIG_CH12] Bits */
\r
11298 #define DMA_SW_CHTRIG_CH12_OFS (12) /* CH12 Offset */
\r
11299 #define DMA_SW_CHTRIG_CH12 (0x00001000) /* Write 1, triggers DMA_CHANNEL12 */
\r
11300 /* DMA_SW_CHTRIG[DMA_SW_CHTRIG_CH13] Bits */
\r
11301 #define DMA_SW_CHTRIG_CH13_OFS (13) /* CH13 Offset */
\r
11302 #define DMA_SW_CHTRIG_CH13 (0x00002000) /* Write 1, triggers DMA_CHANNEL13 */
\r
11303 /* DMA_SW_CHTRIG[DMA_SW_CHTRIG_CH14] Bits */
\r
11304 #define DMA_SW_CHTRIG_CH14_OFS (14) /* CH14 Offset */
\r
11305 #define DMA_SW_CHTRIG_CH14 (0x00004000) /* Write 1, triggers DMA_CHANNEL14 */
\r
11306 /* DMA_SW_CHTRIG[DMA_SW_CHTRIG_CH15] Bits */
\r
11307 #define DMA_SW_CHTRIG_CH15_OFS (15) /* CH15 Offset */
\r
11308 #define DMA_SW_CHTRIG_CH15 (0x00008000) /* Write 1, triggers DMA_CHANNEL15 */
\r
11309 /* DMA_SW_CHTRIG[DMA_SW_CHTRIG_CH16] Bits */
\r
11310 #define DMA_SW_CHTRIG_CH16_OFS (16) /* CH16 Offset */
\r
11311 #define DMA_SW_CHTRIG_CH16 (0x00010000) /* Write 1, triggers DMA_CHANNEL16 */
\r
11312 /* DMA_SW_CHTRIG[DMA_SW_CHTRIG_CH17] Bits */
\r
11313 #define DMA_SW_CHTRIG_CH17_OFS (17) /* CH17 Offset */
\r
11314 #define DMA_SW_CHTRIG_CH17 (0x00020000) /* Write 1, triggers DMA_CHANNEL17 */
\r
11315 /* DMA_SW_CHTRIG[DMA_SW_CHTRIG_CH18] Bits */
\r
11316 #define DMA_SW_CHTRIG_CH18_OFS (18) /* CH18 Offset */
\r
11317 #define DMA_SW_CHTRIG_CH18 (0x00040000) /* Write 1, triggers DMA_CHANNEL18 */
\r
11318 /* DMA_SW_CHTRIG[DMA_SW_CHTRIG_CH19] Bits */
\r
11319 #define DMA_SW_CHTRIG_CH19_OFS (19) /* CH19 Offset */
\r
11320 #define DMA_SW_CHTRIG_CH19 (0x00080000) /* Write 1, triggers DMA_CHANNEL19 */
\r
11321 /* DMA_SW_CHTRIG[DMA_SW_CHTRIG_CH20] Bits */
\r
11322 #define DMA_SW_CHTRIG_CH20_OFS (20) /* CH20 Offset */
\r
11323 #define DMA_SW_CHTRIG_CH20 (0x00100000) /* Write 1, triggers DMA_CHANNEL20 */
\r
11324 /* DMA_SW_CHTRIG[DMA_SW_CHTRIG_CH21] Bits */
\r
11325 #define DMA_SW_CHTRIG_CH21_OFS (21) /* CH21 Offset */
\r
11326 #define DMA_SW_CHTRIG_CH21 (0x00200000) /* Write 1, triggers DMA_CHANNEL21 */
\r
11327 /* DMA_SW_CHTRIG[DMA_SW_CHTRIG_CH22] Bits */
\r
11328 #define DMA_SW_CHTRIG_CH22_OFS (22) /* CH22 Offset */
\r
11329 #define DMA_SW_CHTRIG_CH22 (0x00400000) /* Write 1, triggers DMA_CHANNEL22 */
\r
11330 /* DMA_SW_CHTRIG[DMA_SW_CHTRIG_CH23] Bits */
\r
11331 #define DMA_SW_CHTRIG_CH23_OFS (23) /* CH23 Offset */
\r
11332 #define DMA_SW_CHTRIG_CH23 (0x00800000) /* Write 1, triggers DMA_CHANNEL23 */
\r
11333 /* DMA_SW_CHTRIG[DMA_SW_CHTRIG_CH24] Bits */
\r
11334 #define DMA_SW_CHTRIG_CH24_OFS (24) /* CH24 Offset */
\r
11335 #define DMA_SW_CHTRIG_CH24 (0x01000000) /* Write 1, triggers DMA_CHANNEL24 */
\r
11336 /* DMA_SW_CHTRIG[DMA_SW_CHTRIG_CH25] Bits */
\r
11337 #define DMA_SW_CHTRIG_CH25_OFS (25) /* CH25 Offset */
\r
11338 #define DMA_SW_CHTRIG_CH25 (0x02000000) /* Write 1, triggers DMA_CHANNEL25 */
\r
11339 /* DMA_SW_CHTRIG[DMA_SW_CHTRIG_CH26] Bits */
\r
11340 #define DMA_SW_CHTRIG_CH26_OFS (26) /* CH26 Offset */
\r
11341 #define DMA_SW_CHTRIG_CH26 (0x04000000) /* Write 1, triggers DMA_CHANNEL26 */
\r
11342 /* DMA_SW_CHTRIG[DMA_SW_CHTRIG_CH27] Bits */
\r
11343 #define DMA_SW_CHTRIG_CH27_OFS (27) /* CH27 Offset */
\r
11344 #define DMA_SW_CHTRIG_CH27 (0x08000000) /* Write 1, triggers DMA_CHANNEL27 */
\r
11345 /* DMA_SW_CHTRIG[DMA_SW_CHTRIG_CH28] Bits */
\r
11346 #define DMA_SW_CHTRIG_CH28_OFS (28) /* CH28 Offset */
\r
11347 #define DMA_SW_CHTRIG_CH28 (0x10000000) /* Write 1, triggers DMA_CHANNEL28 */
\r
11348 /* DMA_SW_CHTRIG[DMA_SW_CHTRIG_CH29] Bits */
\r
11349 #define DMA_SW_CHTRIG_CH29_OFS (29) /* CH29 Offset */
\r
11350 #define DMA_SW_CHTRIG_CH29 (0x20000000) /* Write 1, triggers DMA_CHANNEL29 */
\r
11351 /* DMA_SW_CHTRIG[DMA_SW_CHTRIG_CH30] Bits */
\r
11352 #define DMA_SW_CHTRIG_CH30_OFS (30) /* CH30 Offset */
\r
11353 #define DMA_SW_CHTRIG_CH30 (0x40000000) /* Write 1, triggers DMA_CHANNEL30 */
\r
11354 /* DMA_SW_CHTRIG[DMA_SW_CHTRIG_CH31] Bits */
\r
11355 #define DMA_SW_CHTRIG_CH31_OFS (31) /* CH31 Offset */
\r
11356 #define DMA_SW_CHTRIG_CH31 (0x80000000) /* Write 1, triggers DMA_CHANNEL31 */
\r
11357 /* DMA_CH_SRCCFG[DMA_CHN_SRCCFG_DMA_SRC] Bits */
\r
11358 #define DMA_CHN_SRCCFG_DMA_SRC_OFS ( 0) /* DMA_SRC Offset */
\r
11359 #define DMA_CHN_SRCCFG_DMA_SRC_M (0x000000ff) /* Device level DMA source mapping to channel input */
\r
11360 /* DMA_INT1_SRCCFG[DMA_INT1_SRCCFG_INT_SRC] Bits */
\r
11361 #define DMA_INT1_SRCCFG_INT_SRC_OFS ( 0) /* INT_SRC Offset */
\r
11362 #define DMA_INT1_SRCCFG_INT_SRC_M (0x0000001f) /* Controls which channel's completion event is mapped as a source of this Interrupt */
\r
11363 /* DMA_INT1_SRCCFG[DMA_INT1_SRCCFG_EN] Bits */
\r
11364 #define DMA_INT1_SRCCFG_EN_OFS ( 5) /* EN Offset */
\r
11365 #define DMA_INT1_SRCCFG_EN (0x00000020) /* Enables DMA_INT1 mapping */
\r
11366 /* DMA_INT2_SRCCFG[DMA_INT2_SRCCFG_INT_SRC] Bits */
\r
11367 #define DMA_INT2_SRCCFG_INT_SRC_OFS ( 0) /* INT_SRC Offset */
\r
11368 #define DMA_INT2_SRCCFG_INT_SRC_M (0x0000001f) /* Controls which channel's completion event is mapped as a source of this Interrupt */
\r
11369 /* DMA_INT2_SRCCFG[DMA_INT2_SRCCFG_EN] Bits */
\r
11370 #define DMA_INT2_SRCCFG_EN_OFS ( 5) /* EN Offset */
\r
11371 #define DMA_INT2_SRCCFG_EN (0x00000020) /* Enables DMA_INT2 mapping */
\r
11372 /* DMA_INT3_SRCCFG[DMA_INT3_SRCCFG_INT_SRC] Bits */
\r
11373 #define DMA_INT3_SRCCFG_INT_SRC_OFS ( 0) /* INT_SRC Offset */
\r
11374 #define DMA_INT3_SRCCFG_INT_SRC_M (0x0000001f) /* Controls which channel's completion event is mapped as a source of this Interrupt */
\r
11375 /* DMA_INT3_SRCCFG[DMA_INT3_SRCCFG_EN] Bits */
\r
11376 #define DMA_INT3_SRCCFG_EN_OFS ( 5) /* EN Offset */
\r
11377 #define DMA_INT3_SRCCFG_EN (0x00000020) /* Enables DMA_INT3 mapping */
\r
11378 /* DMA_INT0_SRCFLG[DMA_INT0_SRCFLG_CH0] Bits */
\r
11379 #define DMA_INT0_SRCFLG_CH0_OFS ( 0) /* CH0 Offset */
\r
11380 #define DMA_INT0_SRCFLG_CH0 (0x00000001) /* Channel 0 was the source of DMA_INT0 */
\r
11381 /* DMA_INT0_SRCFLG[DMA_INT0_SRCFLG_CH1] Bits */
\r
11382 #define DMA_INT0_SRCFLG_CH1_OFS ( 1) /* CH1 Offset */
\r
11383 #define DMA_INT0_SRCFLG_CH1 (0x00000002) /* Channel 1 was the source of DMA_INT0 */
\r
11384 /* DMA_INT0_SRCFLG[DMA_INT0_SRCFLG_CH2] Bits */
\r
11385 #define DMA_INT0_SRCFLG_CH2_OFS ( 2) /* CH2 Offset */
\r
11386 #define DMA_INT0_SRCFLG_CH2 (0x00000004) /* Channel 2 was the source of DMA_INT0 */
\r
11387 /* DMA_INT0_SRCFLG[DMA_INT0_SRCFLG_CH3] Bits */
\r
11388 #define DMA_INT0_SRCFLG_CH3_OFS ( 3) /* CH3 Offset */
\r
11389 #define DMA_INT0_SRCFLG_CH3 (0x00000008) /* Channel 3 was the source of DMA_INT0 */
\r
11390 /* DMA_INT0_SRCFLG[DMA_INT0_SRCFLG_CH4] Bits */
\r
11391 #define DMA_INT0_SRCFLG_CH4_OFS ( 4) /* CH4 Offset */
\r
11392 #define DMA_INT0_SRCFLG_CH4 (0x00000010) /* Channel 4 was the source of DMA_INT0 */
\r
11393 /* DMA_INT0_SRCFLG[DMA_INT0_SRCFLG_CH5] Bits */
\r
11394 #define DMA_INT0_SRCFLG_CH5_OFS ( 5) /* CH5 Offset */
\r
11395 #define DMA_INT0_SRCFLG_CH5 (0x00000020) /* Channel 5 was the source of DMA_INT0 */
\r
11396 /* DMA_INT0_SRCFLG[DMA_INT0_SRCFLG_CH6] Bits */
\r
11397 #define DMA_INT0_SRCFLG_CH6_OFS ( 6) /* CH6 Offset */
\r
11398 #define DMA_INT0_SRCFLG_CH6 (0x00000040) /* Channel 6 was the source of DMA_INT0 */
\r
11399 /* DMA_INT0_SRCFLG[DMA_INT0_SRCFLG_CH7] Bits */
\r
11400 #define DMA_INT0_SRCFLG_CH7_OFS ( 7) /* CH7 Offset */
\r
11401 #define DMA_INT0_SRCFLG_CH7 (0x00000080) /* Channel 7 was the source of DMA_INT0 */
\r
11402 /* DMA_INT0_SRCFLG[DMA_INT0_SRCFLG_CH8] Bits */
\r
11403 #define DMA_INT0_SRCFLG_CH8_OFS ( 8) /* CH8 Offset */
\r
11404 #define DMA_INT0_SRCFLG_CH8 (0x00000100) /* Channel 8 was the source of DMA_INT0 */
\r
11405 /* DMA_INT0_SRCFLG[DMA_INT0_SRCFLG_CH9] Bits */
\r
11406 #define DMA_INT0_SRCFLG_CH9_OFS ( 9) /* CH9 Offset */
\r
11407 #define DMA_INT0_SRCFLG_CH9 (0x00000200) /* Channel 9 was the source of DMA_INT0 */
\r
11408 /* DMA_INT0_SRCFLG[DMA_INT0_SRCFLG_CH10] Bits */
\r
11409 #define DMA_INT0_SRCFLG_CH10_OFS (10) /* CH10 Offset */
\r
11410 #define DMA_INT0_SRCFLG_CH10 (0x00000400) /* Channel 10 was the source of DMA_INT0 */
\r
11411 /* DMA_INT0_SRCFLG[DMA_INT0_SRCFLG_CH11] Bits */
\r
11412 #define DMA_INT0_SRCFLG_CH11_OFS (11) /* CH11 Offset */
\r
11413 #define DMA_INT0_SRCFLG_CH11 (0x00000800) /* Channel 11 was the source of DMA_INT0 */
\r
11414 /* DMA_INT0_SRCFLG[DMA_INT0_SRCFLG_CH12] Bits */
\r
11415 #define DMA_INT0_SRCFLG_CH12_OFS (12) /* CH12 Offset */
\r
11416 #define DMA_INT0_SRCFLG_CH12 (0x00001000) /* Channel 12 was the source of DMA_INT0 */
\r
11417 /* DMA_INT0_SRCFLG[DMA_INT0_SRCFLG_CH13] Bits */
\r
11418 #define DMA_INT0_SRCFLG_CH13_OFS (13) /* CH13 Offset */
\r
11419 #define DMA_INT0_SRCFLG_CH13 (0x00002000) /* Channel 13 was the source of DMA_INT0 */
\r
11420 /* DMA_INT0_SRCFLG[DMA_INT0_SRCFLG_CH14] Bits */
\r
11421 #define DMA_INT0_SRCFLG_CH14_OFS (14) /* CH14 Offset */
\r
11422 #define DMA_INT0_SRCFLG_CH14 (0x00004000) /* Channel 14 was the source of DMA_INT0 */
\r
11423 /* DMA_INT0_SRCFLG[DMA_INT0_SRCFLG_CH15] Bits */
\r
11424 #define DMA_INT0_SRCFLG_CH15_OFS (15) /* CH15 Offset */
\r
11425 #define DMA_INT0_SRCFLG_CH15 (0x00008000) /* Channel 15 was the source of DMA_INT0 */
\r
11426 /* DMA_INT0_SRCFLG[DMA_INT0_SRCFLG_CH16] Bits */
\r
11427 #define DMA_INT0_SRCFLG_CH16_OFS (16) /* CH16 Offset */
\r
11428 #define DMA_INT0_SRCFLG_CH16 (0x00010000) /* Channel 16 was the source of DMA_INT0 */
\r
11429 /* DMA_INT0_SRCFLG[DMA_INT0_SRCFLG_CH17] Bits */
\r
11430 #define DMA_INT0_SRCFLG_CH17_OFS (17) /* CH17 Offset */
\r
11431 #define DMA_INT0_SRCFLG_CH17 (0x00020000) /* Channel 17 was the source of DMA_INT0 */
\r
11432 /* DMA_INT0_SRCFLG[DMA_INT0_SRCFLG_CH18] Bits */
\r
11433 #define DMA_INT0_SRCFLG_CH18_OFS (18) /* CH18 Offset */
\r
11434 #define DMA_INT0_SRCFLG_CH18 (0x00040000) /* Channel 18 was the source of DMA_INT0 */
\r
11435 /* DMA_INT0_SRCFLG[DMA_INT0_SRCFLG_CH19] Bits */
\r
11436 #define DMA_INT0_SRCFLG_CH19_OFS (19) /* CH19 Offset */
\r
11437 #define DMA_INT0_SRCFLG_CH19 (0x00080000) /* Channel 19 was the source of DMA_INT0 */
\r
11438 /* DMA_INT0_SRCFLG[DMA_INT0_SRCFLG_CH20] Bits */
\r
11439 #define DMA_INT0_SRCFLG_CH20_OFS (20) /* CH20 Offset */
\r
11440 #define DMA_INT0_SRCFLG_CH20 (0x00100000) /* Channel 20 was the source of DMA_INT0 */
\r
11441 /* DMA_INT0_SRCFLG[DMA_INT0_SRCFLG_CH21] Bits */
\r
11442 #define DMA_INT0_SRCFLG_CH21_OFS (21) /* CH21 Offset */
\r
11443 #define DMA_INT0_SRCFLG_CH21 (0x00200000) /* Channel 21 was the source of DMA_INT0 */
\r
11444 /* DMA_INT0_SRCFLG[DMA_INT0_SRCFLG_CH22] Bits */
\r
11445 #define DMA_INT0_SRCFLG_CH22_OFS (22) /* CH22 Offset */
\r
11446 #define DMA_INT0_SRCFLG_CH22 (0x00400000) /* Channel 22 was the source of DMA_INT0 */
\r
11447 /* DMA_INT0_SRCFLG[DMA_INT0_SRCFLG_CH23] Bits */
\r
11448 #define DMA_INT0_SRCFLG_CH23_OFS (23) /* CH23 Offset */
\r
11449 #define DMA_INT0_SRCFLG_CH23 (0x00800000) /* Channel 23 was the source of DMA_INT0 */
\r
11450 /* DMA_INT0_SRCFLG[DMA_INT0_SRCFLG_CH24] Bits */
\r
11451 #define DMA_INT0_SRCFLG_CH24_OFS (24) /* CH24 Offset */
\r
11452 #define DMA_INT0_SRCFLG_CH24 (0x01000000) /* Channel 24 was the source of DMA_INT0 */
\r
11453 /* DMA_INT0_SRCFLG[DMA_INT0_SRCFLG_CH25] Bits */
\r
11454 #define DMA_INT0_SRCFLG_CH25_OFS (25) /* CH25 Offset */
\r
11455 #define DMA_INT0_SRCFLG_CH25 (0x02000000) /* Channel 25 was the source of DMA_INT0 */
\r
11456 /* DMA_INT0_SRCFLG[DMA_INT0_SRCFLG_CH26] Bits */
\r
11457 #define DMA_INT0_SRCFLG_CH26_OFS (26) /* CH26 Offset */
\r
11458 #define DMA_INT0_SRCFLG_CH26 (0x04000000) /* Channel 26 was the source of DMA_INT0 */
\r
11459 /* DMA_INT0_SRCFLG[DMA_INT0_SRCFLG_CH27] Bits */
\r
11460 #define DMA_INT0_SRCFLG_CH27_OFS (27) /* CH27 Offset */
\r
11461 #define DMA_INT0_SRCFLG_CH27 (0x08000000) /* Channel 27 was the source of DMA_INT0 */
\r
11462 /* DMA_INT0_SRCFLG[DMA_INT0_SRCFLG_CH28] Bits */
\r
11463 #define DMA_INT0_SRCFLG_CH28_OFS (28) /* CH28 Offset */
\r
11464 #define DMA_INT0_SRCFLG_CH28 (0x10000000) /* Channel 28 was the source of DMA_INT0 */
\r
11465 /* DMA_INT0_SRCFLG[DMA_INT0_SRCFLG_CH29] Bits */
\r
11466 #define DMA_INT0_SRCFLG_CH29_OFS (29) /* CH29 Offset */
\r
11467 #define DMA_INT0_SRCFLG_CH29 (0x20000000) /* Channel 29 was the source of DMA_INT0 */
\r
11468 /* DMA_INT0_SRCFLG[DMA_INT0_SRCFLG_CH30] Bits */
\r
11469 #define DMA_INT0_SRCFLG_CH30_OFS (30) /* CH30 Offset */
\r
11470 #define DMA_INT0_SRCFLG_CH30 (0x40000000) /* Channel 30 was the source of DMA_INT0 */
\r
11471 /* DMA_INT0_SRCFLG[DMA_INT0_SRCFLG_CH31] Bits */
\r
11472 #define DMA_INT0_SRCFLG_CH31_OFS (31) /* CH31 Offset */
\r
11473 #define DMA_INT0_SRCFLG_CH31 (0x80000000) /* Channel 31 was the source of DMA_INT0 */
\r
11474 /* DMA_INT0_CLRFLG[DMA_INT0_CLRFLG_CH0] Bits */
\r
11475 #define DMA_INT0_CLRFLG_CH0_OFS ( 0) /* CH0 Offset */
\r
11476 #define DMA_INT0_CLRFLG_CH0 (0x00000001) /* Clear corresponding DMA_INT0_SRCFLG_REG */
\r
11477 /* DMA_INT0_CLRFLG[DMA_INT0_CLRFLG_CH1] Bits */
\r
11478 #define DMA_INT0_CLRFLG_CH1_OFS ( 1) /* CH1 Offset */
\r
11479 #define DMA_INT0_CLRFLG_CH1 (0x00000002) /* Clear corresponding DMA_INT0_SRCFLG_REG */
\r
11480 /* DMA_INT0_CLRFLG[DMA_INT0_CLRFLG_CH2] Bits */
\r
11481 #define DMA_INT0_CLRFLG_CH2_OFS ( 2) /* CH2 Offset */
\r
11482 #define DMA_INT0_CLRFLG_CH2 (0x00000004) /* Clear corresponding DMA_INT0_SRCFLG_REG */
\r
11483 /* DMA_INT0_CLRFLG[DMA_INT0_CLRFLG_CH3] Bits */
\r
11484 #define DMA_INT0_CLRFLG_CH3_OFS ( 3) /* CH3 Offset */
\r
11485 #define DMA_INT0_CLRFLG_CH3 (0x00000008) /* Clear corresponding DMA_INT0_SRCFLG_REG */
\r
11486 /* DMA_INT0_CLRFLG[DMA_INT0_CLRFLG_CH4] Bits */
\r
11487 #define DMA_INT0_CLRFLG_CH4_OFS ( 4) /* CH4 Offset */
\r
11488 #define DMA_INT0_CLRFLG_CH4 (0x00000010) /* Clear corresponding DMA_INT0_SRCFLG_REG */
\r
11489 /* DMA_INT0_CLRFLG[DMA_INT0_CLRFLG_CH5] Bits */
\r
11490 #define DMA_INT0_CLRFLG_CH5_OFS ( 5) /* CH5 Offset */
\r
11491 #define DMA_INT0_CLRFLG_CH5 (0x00000020) /* Clear corresponding DMA_INT0_SRCFLG_REG */
\r
11492 /* DMA_INT0_CLRFLG[DMA_INT0_CLRFLG_CH6] Bits */
\r
11493 #define DMA_INT0_CLRFLG_CH6_OFS ( 6) /* CH6 Offset */
\r
11494 #define DMA_INT0_CLRFLG_CH6 (0x00000040) /* Clear corresponding DMA_INT0_SRCFLG_REG */
\r
11495 /* DMA_INT0_CLRFLG[DMA_INT0_CLRFLG_CH7] Bits */
\r
11496 #define DMA_INT0_CLRFLG_CH7_OFS ( 7) /* CH7 Offset */
\r
11497 #define DMA_INT0_CLRFLG_CH7 (0x00000080) /* Clear corresponding DMA_INT0_SRCFLG_REG */
\r
11498 /* DMA_INT0_CLRFLG[DMA_INT0_CLRFLG_CH8] Bits */
\r
11499 #define DMA_INT0_CLRFLG_CH8_OFS ( 8) /* CH8 Offset */
\r
11500 #define DMA_INT0_CLRFLG_CH8 (0x00000100) /* Clear corresponding DMA_INT0_SRCFLG_REG */
\r
11501 /* DMA_INT0_CLRFLG[DMA_INT0_CLRFLG_CH9] Bits */
\r
11502 #define DMA_INT0_CLRFLG_CH9_OFS ( 9) /* CH9 Offset */
\r
11503 #define DMA_INT0_CLRFLG_CH9 (0x00000200) /* Clear corresponding DMA_INT0_SRCFLG_REG */
\r
11504 /* DMA_INT0_CLRFLG[DMA_INT0_CLRFLG_CH10] Bits */
\r
11505 #define DMA_INT0_CLRFLG_CH10_OFS (10) /* CH10 Offset */
\r
11506 #define DMA_INT0_CLRFLG_CH10 (0x00000400) /* Clear corresponding DMA_INT0_SRCFLG_REG */
\r
11507 /* DMA_INT0_CLRFLG[DMA_INT0_CLRFLG_CH11] Bits */
\r
11508 #define DMA_INT0_CLRFLG_CH11_OFS (11) /* CH11 Offset */
\r
11509 #define DMA_INT0_CLRFLG_CH11 (0x00000800) /* Clear corresponding DMA_INT0_SRCFLG_REG */
\r
11510 /* DMA_INT0_CLRFLG[DMA_INT0_CLRFLG_CH12] Bits */
\r
11511 #define DMA_INT0_CLRFLG_CH12_OFS (12) /* CH12 Offset */
\r
11512 #define DMA_INT0_CLRFLG_CH12 (0x00001000) /* Clear corresponding DMA_INT0_SRCFLG_REG */
\r
11513 /* DMA_INT0_CLRFLG[DMA_INT0_CLRFLG_CH13] Bits */
\r
11514 #define DMA_INT0_CLRFLG_CH13_OFS (13) /* CH13 Offset */
\r
11515 #define DMA_INT0_CLRFLG_CH13 (0x00002000) /* Clear corresponding DMA_INT0_SRCFLG_REG */
\r
11516 /* DMA_INT0_CLRFLG[DMA_INT0_CLRFLG_CH14] Bits */
\r
11517 #define DMA_INT0_CLRFLG_CH14_OFS (14) /* CH14 Offset */
\r
11518 #define DMA_INT0_CLRFLG_CH14 (0x00004000) /* Clear corresponding DMA_INT0_SRCFLG_REG */
\r
11519 /* DMA_INT0_CLRFLG[DMA_INT0_CLRFLG_CH15] Bits */
\r
11520 #define DMA_INT0_CLRFLG_CH15_OFS (15) /* CH15 Offset */
\r
11521 #define DMA_INT0_CLRFLG_CH15 (0x00008000) /* Clear corresponding DMA_INT0_SRCFLG_REG */
\r
11522 /* DMA_INT0_CLRFLG[DMA_INT0_CLRFLG_CH16] Bits */
\r
11523 #define DMA_INT0_CLRFLG_CH16_OFS (16) /* CH16 Offset */
\r
11524 #define DMA_INT0_CLRFLG_CH16 (0x00010000) /* Clear corresponding DMA_INT0_SRCFLG_REG */
\r
11525 /* DMA_INT0_CLRFLG[DMA_INT0_CLRFLG_CH17] Bits */
\r
11526 #define DMA_INT0_CLRFLG_CH17_OFS (17) /* CH17 Offset */
\r
11527 #define DMA_INT0_CLRFLG_CH17 (0x00020000) /* Clear corresponding DMA_INT0_SRCFLG_REG */
\r
11528 /* DMA_INT0_CLRFLG[DMA_INT0_CLRFLG_CH18] Bits */
\r
11529 #define DMA_INT0_CLRFLG_CH18_OFS (18) /* CH18 Offset */
\r
11530 #define DMA_INT0_CLRFLG_CH18 (0x00040000) /* Clear corresponding DMA_INT0_SRCFLG_REG */
\r
11531 /* DMA_INT0_CLRFLG[DMA_INT0_CLRFLG_CH19] Bits */
\r
11532 #define DMA_INT0_CLRFLG_CH19_OFS (19) /* CH19 Offset */
\r
11533 #define DMA_INT0_CLRFLG_CH19 (0x00080000) /* Clear corresponding DMA_INT0_SRCFLG_REG */
\r
11534 /* DMA_INT0_CLRFLG[DMA_INT0_CLRFLG_CH20] Bits */
\r
11535 #define DMA_INT0_CLRFLG_CH20_OFS (20) /* CH20 Offset */
\r
11536 #define DMA_INT0_CLRFLG_CH20 (0x00100000) /* Clear corresponding DMA_INT0_SRCFLG_REG */
\r
11537 /* DMA_INT0_CLRFLG[DMA_INT0_CLRFLG_CH21] Bits */
\r
11538 #define DMA_INT0_CLRFLG_CH21_OFS (21) /* CH21 Offset */
\r
11539 #define DMA_INT0_CLRFLG_CH21 (0x00200000) /* Clear corresponding DMA_INT0_SRCFLG_REG */
\r
11540 /* DMA_INT0_CLRFLG[DMA_INT0_CLRFLG_CH22] Bits */
\r
11541 #define DMA_INT0_CLRFLG_CH22_OFS (22) /* CH22 Offset */
\r
11542 #define DMA_INT0_CLRFLG_CH22 (0x00400000) /* Clear corresponding DMA_INT0_SRCFLG_REG */
\r
11543 /* DMA_INT0_CLRFLG[DMA_INT0_CLRFLG_CH23] Bits */
\r
11544 #define DMA_INT0_CLRFLG_CH23_OFS (23) /* CH23 Offset */
\r
11545 #define DMA_INT0_CLRFLG_CH23 (0x00800000) /* Clear corresponding DMA_INT0_SRCFLG_REG */
\r
11546 /* DMA_INT0_CLRFLG[DMA_INT0_CLRFLG_CH24] Bits */
\r
11547 #define DMA_INT0_CLRFLG_CH24_OFS (24) /* CH24 Offset */
\r
11548 #define DMA_INT0_CLRFLG_CH24 (0x01000000) /* Clear corresponding DMA_INT0_SRCFLG_REG */
\r
11549 /* DMA_INT0_CLRFLG[DMA_INT0_CLRFLG_CH25] Bits */
\r
11550 #define DMA_INT0_CLRFLG_CH25_OFS (25) /* CH25 Offset */
\r
11551 #define DMA_INT0_CLRFLG_CH25 (0x02000000) /* Clear corresponding DMA_INT0_SRCFLG_REG */
\r
11552 /* DMA_INT0_CLRFLG[DMA_INT0_CLRFLG_CH26] Bits */
\r
11553 #define DMA_INT0_CLRFLG_CH26_OFS (26) /* CH26 Offset */
\r
11554 #define DMA_INT0_CLRFLG_CH26 (0x04000000) /* Clear corresponding DMA_INT0_SRCFLG_REG */
\r
11555 /* DMA_INT0_CLRFLG[DMA_INT0_CLRFLG_CH27] Bits */
\r
11556 #define DMA_INT0_CLRFLG_CH27_OFS (27) /* CH27 Offset */
\r
11557 #define DMA_INT0_CLRFLG_CH27 (0x08000000) /* Clear corresponding DMA_INT0_SRCFLG_REG */
\r
11558 /* DMA_INT0_CLRFLG[DMA_INT0_CLRFLG_CH28] Bits */
\r
11559 #define DMA_INT0_CLRFLG_CH28_OFS (28) /* CH28 Offset */
\r
11560 #define DMA_INT0_CLRFLG_CH28 (0x10000000) /* Clear corresponding DMA_INT0_SRCFLG_REG */
\r
11561 /* DMA_INT0_CLRFLG[DMA_INT0_CLRFLG_CH29] Bits */
\r
11562 #define DMA_INT0_CLRFLG_CH29_OFS (29) /* CH29 Offset */
\r
11563 #define DMA_INT0_CLRFLG_CH29 (0x20000000) /* Clear corresponding DMA_INT0_SRCFLG_REG */
\r
11564 /* DMA_INT0_CLRFLG[DMA_INT0_CLRFLG_CH30] Bits */
\r
11565 #define DMA_INT0_CLRFLG_CH30_OFS (30) /* CH30 Offset */
\r
11566 #define DMA_INT0_CLRFLG_CH30 (0x40000000) /* Clear corresponding DMA_INT0_SRCFLG_REG */
\r
11567 /* DMA_INT0_CLRFLG[DMA_INT0_CLRFLG_CH31] Bits */
\r
11568 #define DMA_INT0_CLRFLG_CH31_OFS (31) /* CH31 Offset */
\r
11569 #define DMA_INT0_CLRFLG_CH31 (0x80000000) /* Clear corresponding DMA_INT0_SRCFLG_REG */
\r
11570 /* DMA_STAT[DMA_STAT_MASTEN] Bits */
\r
11571 #define DMA_STAT_MASTEN_OFS ( 0) /* MASTEN Offset */
\r
11572 #define DMA_STAT_MASTEN (0x00000001) /* */
\r
11573 /* DMA_STAT[DMA_STAT_] Bits */
\r
11574 #define DMA_STAT__OFS ( 4) /* STATE Offset */
\r
11575 #define DMA_STAT__M (0x000000f0) /* */
\r
11576 #define DMA_STAT_0 (0x00000010) /* */
\r
11577 #define DMA_STAT_1 (0x00000020) /* */
\r
11578 #define DMA_STAT_2 (0x00000040) /* */
\r
11579 #define DMA_STAT_3 (0x00000080) /* */
\r
11580 #define DMA_STAT__0 (0x00000000) /* idle */
\r
11581 #define DMA_STAT__1 (0x00000010) /* reading channel controller data */
\r
11582 #define DMA_STAT__2 (0x00000020) /* reading source data end pointer */
\r
11583 #define DMA_STAT__3 (0x00000030) /* reading destination data end pointer */
\r
11584 #define DMA_STAT__4 (0x00000040) /* reading source data */
\r
11585 #define DMA_STAT__5 (0x00000050) /* writing destination data */
\r
11586 #define DMA_STAT__6 (0x00000060) /* waiting for DMA request to clear */
\r
11587 #define DMA_STAT__7 (0x00000070) /* writing channel controller data */
\r
11588 #define DMA_STAT__8 (0x00000080) /* stalled */
\r
11589 #define DMA_STAT__9 (0x00000090) /* done */
\r
11590 #define DMA_STAT__10 (0x000000a0) /* peripheral scatter-gather transition */
\r
11591 #define DMA_STAT__11 (0x000000b0) /* Reserved */
\r
11592 #define DMA_STAT__12 (0x000000c0) /* Reserved */
\r
11593 #define DMA_STAT__13 (0x000000d0) /* Reserved */
\r
11594 #define DMA_STAT__14 (0x000000e0) /* Reserved */
\r
11595 #define DMA_STAT__15 (0x000000f0) /* Reserved */
\r
11596 /* DMA_STAT[DMA_STAT_] Bits */
\r
11597 //#define DMA_STAT__OFS (16) /* DMACHANS Offset */
\r
11598 //#define DMA_STAT__M (0x001f0000) /* */
\r
11599 //#define DMA_STAT_0 (0x00010000) /* */
\r
11600 //#define DMA_STAT_1 (0x00020000) /* */
\r
11601 //#define DMA_STAT_2 (0x00040000) /* */
\r
11602 //#define DMA_STAT_3 (0x00080000) /* */
\r
11603 #define DMA_STAT_4 (0x00100000) /* */
\r
11604 //#define DMA_STAT__0 (0x00000000) /* Controller configured to use 1 DMA channel */
\r
11605 //#define DMA_STAT__1 (0x00010000) /* Controller configured to use 2 DMA channels */
\r
11606 #define DMA_STAT__30 (0x001e0000) /* Controller configured to use 31 DMA channels */
\r
11607 #define DMA_STAT__31 (0x001f0000) /* Controller configured to use 32 DMA channels */
\r
11608 /* DMA_STAT[DMA_STAT_] Bits */
\r
11609 //#define DMA_STAT__OFS (28) /* TESTSTAT Offset */
\r
11610 //#define DMA_STAT__M (0xf0000000) /* */
\r
11611 //#define DMA_STAT_0 (0x10000000) /* */
\r
11612 //#define DMA_STAT_1 (0x20000000) /* */
\r
11613 //#define DMA_STAT_2 (0x40000000) /* */
\r
11614 //#define DMA_STAT_3 (0x80000000) /* */
\r
11615 //#define DMA_STAT__0 (0x00000000) /* Controller does not include the integration test logic */
\r
11616 //#define DMA_STAT__1 (0x10000000) /* Controller includes the integration test logic */
\r
11617 /* DMA_CFG[DMA_CFG_] Bits */
\r
11618 #define DMA_CFG__OFS ( 0) /* MASTEN Offset */
\r
11619 #define DMA_CFG_ (0x00000001) /* */
\r
11620 /* DMA_CFG[DMA_CFG_] Bits */
\r
11621 //#define DMA_CFG__OFS ( 5) /* CHPROTCTRL Offset */
\r
11622 #define DMA_CFG__M (0x000000e0) /* */
\r
11623 /* DMA_CTLBASE[DMA_CTLBASE_] Bits */
\r
11624 #define DMA_CTLBASE__OFS ( 5) /* ADDR Offset */
\r
11625 #define DMA_CTLBASE__M (0xffffffe0) /* */
\r
11626 /* DMA_ERRCLR[DMA_ERRCLR_] Bits */
\r
11627 #define DMA_ERRCLR__OFS ( 0) /* ERRCLR Offset */
\r
11628 #define DMA_ERRCLR_ (0x00000001) /* */
\r
11630 /* UDMA_STAT Control Bits */
\r
11631 #define UDMA_STAT_DMACHANS_M 0x001F0000 /* Available uDMA Channels Minus 1 */
\r
11632 #define UDMA_STAT_STATE_M 0x000000F0 /* Control State Machine Status */
\r
11633 #define UDMA_STAT_STATE_IDLE 0x00000000 /* Idle */
\r
11634 #define UDMA_STAT_STATE_RD_CTRL 0x00000010 /* Reading channel controller data */
\r
11635 #define UDMA_STAT_STATE_RD_SRCENDP 0x00000020 /* Reading source end pointer */
\r
11636 #define UDMA_STAT_STATE_RD_DSTENDP 0x00000030 /* Reading destination end pointer */
\r
11637 #define UDMA_STAT_STATE_RD_SRCDAT 0x00000040 /* Reading source data */
\r
11638 #define UDMA_STAT_STATE_WR_DSTDAT 0x00000050 /* Writing destination data */
\r
11639 #define UDMA_STAT_STATE_WAIT 0x00000060 /* Waiting for uDMA request to */
\r
11641 #define UDMA_STAT_STATE_WR_CTRL 0x00000070 /* Writing channel controller data */
\r
11642 #define UDMA_STAT_STATE_STALL 0x00000080 /* Stalled */
\r
11643 #define UDMA_STAT_STATE_DONE 0x00000090 /* Done */
\r
11644 #define UDMA_STAT_STATE_UNDEF 0x000000A0 /* Undefined */
\r
11645 #define UDMA_STAT_MASTEN 0x00000001 /* Master Enable Status */
\r
11646 #define UDMA_STAT_DMACHANS_S 16
\r
11648 /* UDMA_CFG Control Bits */
\r
11649 #define UDMA_CFG_MASTEN 0x00000001 /* Controller Master Enable */
\r
11651 /* UDMA_CTLBASE Control Bits */
\r
11652 #define UDMA_CTLBASE_ADDR_M 0xFFFFFC00 /* Channel Control Base Address */
\r
11653 #define UDMA_CTLBASE_ADDR_S 10
\r
11655 /* UDMA_ALTBASE Control Bits */
\r
11656 #define UDMA_ALTBASE_ADDR_M 0xFFFFFFFF /* Alternate Channel Address Pointer */
\r
11657 #define UDMA_ALTBASE_ADDR_S 0
\r
11659 /* UDMA_WAITSTAT Control Bits */
\r
11660 #define UDMA_WAITSTAT_WAITREQ_M 0xFFFFFFFF /* Channel [n] Wait Status */
\r
11662 /* UDMA_SWREQ Control Bits */
\r
11663 #define UDMA_SWREQ_M 0xFFFFFFFF /* Channel [n] Software Request */
\r
11665 /* UDMA_USEBURSTSET Control Bits */
\r
11666 #define UDMA_USEBURSTSET_SET_M 0xFFFFFFFF /* Channel [n] Useburst Set */
\r
11668 /* UDMA_USEBURSTCLR Control Bits */
\r
11669 #define UDMA_USEBURSTCLR_CLR_M 0xFFFFFFFF /* Channel [n] Useburst Clear */
\r
11671 /* UDMA_REQMASKSET Control Bits */
\r
11672 #define UDMA_REQMASKSET_SET_M 0xFFFFFFFF /* Channel [n] Request Mask Set */
\r
11674 /* UDMA_REQMASKCLR Control Bits */
\r
11675 #define UDMA_REQMASKCLR_CLR_M 0xFFFFFFFF /* Channel [n] Request Mask Clear */
\r
11677 /* UDMA_ENASET Control Bits */
\r
11678 #define UDMA_ENASET_SET_M 0xFFFFFFFF /* Channel [n] Enable Set */
\r
11680 /* UDMA_ENACLR Control Bits */
\r
11681 #define UDMA_ENACLR_CLR_M 0xFFFFFFFF /* Clear Channel [n] Enable Clear */
\r
11683 /* UDMA_ALTSET Control Bits */
\r
11684 #define UDMA_ALTSET_SET_M 0xFFFFFFFF /* Channel [n] Alternate Set */
\r
11686 /* UDMA_ALTCLR Control Bits */
\r
11687 #define UDMA_ALTCLR_CLR_M 0xFFFFFFFF /* Channel [n] Alternate Clear */
\r
11689 /* UDMA_PRIOSET Control Bits */
\r
11690 #define UDMA_PRIOSET_SET_M 0xFFFFFFFF /* Channel [n] Priority Set */
\r
11692 /* UDMA_PRIOCLR Control Bits */
\r
11693 #define UDMA_PRIOCLR_CLR_M 0xFFFFFFFF /* Channel [n] Priority Clear */
\r
11695 /* UDMA_ERRCLR Control Bits */
\r
11696 #define UDMA_ERRCLR_ERRCLR 0x00000001 /* uDMA Bus Error Status */
\r
11698 /* UDMA_CHASGN Control Bits */
\r
11699 #define UDMA_CHASGN_M 0xFFFFFFFF /* Channel [n] Assignment Select */
\r
11700 #define UDMA_CHASGN_PRIMARY 0x00000000 /* Use the primary channel */
\r
11702 #define UDMA_CHASGN_SECONDARY 0x00000001 /* Use the secondary channel */
\r
11705 /* Micro Direct Memory Access (uDMA) offsets */
\r
11706 #define UDMA_O_SRCENDP 0x00000000 /* DMA Channel Source Address End */
\r
11708 #define UDMA_O_DSTENDP 0x00000004 /* DMA Channel Destination Address */
\r
11709 /* End Pointer */
\r
11710 #define UDMA_O_CHCTL 0x00000008 /* DMA Channel Control Word */
\r
11712 /* UDMA_O_SRCENDP Control Bits */
\r
11713 #define UDMA_SRCENDP_ADDR_M 0xFFFFFFFF /* Source Address End Pointer */
\r
11714 #define UDMA_SRCENDP_ADDR_S 0
\r
11716 /* UDMA_O_DSTENDP Control Bits */
\r
11717 #define UDMA_DSTENDP_ADDR_M 0xFFFFFFFF /* Destination Address End Pointer */
\r
11718 #define UDMA_DSTENDP_ADDR_S 0
\r
11720 /* UDMA_O_CHCTL Control Bits */
\r
11721 #define UDMA_CHCTL_DSTINC_M 0xC0000000 /* Destination Address Increment */
\r
11722 #define UDMA_CHCTL_DSTINC_8 0x00000000 /* Byte */
\r
11723 #define UDMA_CHCTL_DSTINC_16 0x40000000 /* Half-word */
\r
11724 #define UDMA_CHCTL_DSTINC_32 0x80000000 /* Word */
\r
11725 #define UDMA_CHCTL_DSTINC_NONE 0xC0000000 /* No increment */
\r
11726 #define UDMA_CHCTL_DSTSIZE_M 0x30000000 /* Destination Data Size */
\r
11727 #define UDMA_CHCTL_DSTSIZE_8 0x00000000 /* Byte */
\r
11728 #define UDMA_CHCTL_DSTSIZE_16 0x10000000 /* Half-word */
\r
11729 #define UDMA_CHCTL_DSTSIZE_32 0x20000000 /* Word */
\r
11730 #define UDMA_CHCTL_SRCINC_M 0x0C000000 /* Source Address Increment */
\r
11731 #define UDMA_CHCTL_SRCINC_8 0x00000000 /* Byte */
\r
11732 #define UDMA_CHCTL_SRCINC_16 0x04000000 /* Half-word */
\r
11733 #define UDMA_CHCTL_SRCINC_32 0x08000000 /* Word */
\r
11734 #define UDMA_CHCTL_SRCINC_NONE 0x0C000000 /* No increment */
\r
11735 #define UDMA_CHCTL_SRCSIZE_M 0x03000000 /* Source Data Size */
\r
11736 #define UDMA_CHCTL_SRCSIZE_8 0x00000000 /* Byte */
\r
11737 #define UDMA_CHCTL_SRCSIZE_16 0x01000000 /* Half-word */
\r
11738 #define UDMA_CHCTL_SRCSIZE_32 0x02000000 /* Word */
\r
11739 #define UDMA_CHCTL_ARBSIZE_M 0x0003C000 /* Arbitration Size */
\r
11740 #define UDMA_CHCTL_ARBSIZE_1 0x00000000 /* 1 Transfer */
\r
11741 #define UDMA_CHCTL_ARBSIZE_2 0x00004000 /* 2 Transfers */
\r
11742 #define UDMA_CHCTL_ARBSIZE_4 0x00008000 /* 4 Transfers */
\r
11743 #define UDMA_CHCTL_ARBSIZE_8 0x0000C000 /* 8 Transfers */
\r
11744 #define UDMA_CHCTL_ARBSIZE_16 0x00010000 /* 16 Transfers */
\r
11745 #define UDMA_CHCTL_ARBSIZE_32 0x00014000 /* 32 Transfers */
\r
11746 #define UDMA_CHCTL_ARBSIZE_64 0x00018000 /* 64 Transfers */
\r
11747 #define UDMA_CHCTL_ARBSIZE_128 0x0001C000 /* 128 Transfers */
\r
11748 #define UDMA_CHCTL_ARBSIZE_256 0x00020000 /* 256 Transfers */
\r
11749 #define UDMA_CHCTL_ARBSIZE_512 0x00024000 /* 512 Transfers */
\r
11750 #define UDMA_CHCTL_ARBSIZE_1024 0x00028000 /* 1024 Transfers */
\r
11751 #define UDMA_CHCTL_XFERSIZE_M 0x00003FF0 /* Transfer Size (minus 1) */
\r
11752 #define UDMA_CHCTL_NXTUSEBURST 0x00000008 /* Next Useburst */
\r
11753 #define UDMA_CHCTL_XFERMODE_M 0x00000007 /* uDMA Transfer Mode */
\r
11754 #define UDMA_CHCTL_XFERMODE_STOP 0x00000000 /* Stop */
\r
11755 #define UDMA_CHCTL_XFERMODE_BASIC 0x00000001 /* Basic */
\r
11756 #define UDMA_CHCTL_XFERMODE_AUTO 0x00000002 /* Auto-Request */
\r
11757 #define UDMA_CHCTL_XFERMODE_PINGPONG 0x00000003 /* Ping-Pong */
\r
11758 #define UDMA_CHCTL_XFERMODE_MEM_SG 0x00000004 /* Memory Scatter-Gather */
\r
11759 #define UDMA_CHCTL_XFERMODE_MEM_SGA 0x00000005 /* Alternate Memory Scatter-Gather */
\r
11760 #define UDMA_CHCTL_XFERMODE_PER_SG 0x00000006 /* Peripheral Scatter-Gather */
\r
11761 #define UDMA_CHCTL_XFERMODE_PER_SGA 0x00000007 /* Alternate Peripheral */
\r
11762 /* Scatter-Gather */
\r
11763 #define UDMA_CHCTL_XFERSIZE_S 4
\r
11766 //*****************************************************************************
\r
11768 //*****************************************************************************
\r
11769 /* DWT_CTRL[DWT_CTRL_CYCCNTENA] Bits */
\r
11770 #define DWT_CTRL_CYCCNTENA_OFS ( 0) /* CYCCNTENA Offset */
\r
11771 #define DWT_CTRL_CYCCNTENA (0x00000001) /* */
\r
11772 /* DWT_CTRL[DWT_CTRL_POSTPRESET] Bits */
\r
11773 #define DWT_CTRL_POSTPRESET_OFS ( 1) /* POSTPRESET Offset */
\r
11774 #define DWT_CTRL_POSTPRESET_M (0x0000001e) /* */
\r
11775 /* DWT_CTRL[DWT_CTRL_POSTCNT] Bits */
\r
11776 #define DWT_CTRL_POSTCNT_OFS ( 5) /* POSTCNT Offset */
\r
11777 #define DWT_CTRL_POSTCNT_M (0x000001e0) /* */
\r
11778 /* DWT_CTRL[DWT_CTRL_CYCTAP] Bits */
\r
11779 #define DWT_CTRL_CYCTAP_OFS ( 9) /* CYCTAP Offset */
\r
11780 #define DWT_CTRL_CYCTAP (0x00000200) /* */
\r
11781 /* DWT_CTRL[DWT_CTRL_SYNCTAP] Bits */
\r
11782 #define DWT_CTRL_SYNCTAP_OFS (10) /* SYNCTAP Offset */
\r
11783 #define DWT_CTRL_SYNCTAP_M (0x00000c00) /* */
\r
11784 #define DWT_CTRL_SYNCTAP0 (0x00000400) /* */
\r
11785 #define DWT_CTRL_SYNCTAP1 (0x00000800) /* */
\r
11786 #define DWT_CTRL_SYNCTAP_0 (0x00000000) /* Disabled. No synch counting. */
\r
11787 #define DWT_CTRL_SYNCTAP_1 (0x00000400) /* Tap at CYCCNT bit 24. */
\r
11788 #define DWT_CTRL_SYNCTAP_2 (0x00000800) /* Tap at CYCCNT bit 26. */
\r
11789 #define DWT_CTRL_SYNCTAP_3 (0x00000c00) /* Tap at CYCCNT bit 28. */
\r
11790 /* DWT_CTRL[DWT_CTRL_PCSAMPLEENA] Bits */
\r
11791 #define DWT_CTRL_PCSAMPLEENA_OFS (12) /* PCSAMPLEENA Offset */
\r
11792 #define DWT_CTRL_PCSAMPLEENA (0x00001000) /* */
\r
11793 /* DWT_CTRL[DWT_CTRL_EXCTRCENA] Bits */
\r
11794 #define DWT_CTRL_EXCTRCENA_OFS (16) /* EXCTRCENA Offset */
\r
11795 #define DWT_CTRL_EXCTRCENA (0x00010000) /* */
\r
11796 /* DWT_CTRL[DWT_CTRL_CPIEVTENA] Bits */
\r
11797 #define DWT_CTRL_CPIEVTENA_OFS (17) /* CPIEVTENA Offset */
\r
11798 #define DWT_CTRL_CPIEVTENA (0x00020000) /* */
\r
11799 /* DWT_CTRL[DWT_CTRL_EXCEVTENA] Bits */
\r
11800 #define DWT_CTRL_EXCEVTENA_OFS (18) /* EXCEVTENA Offset */
\r
11801 #define DWT_CTRL_EXCEVTENA (0x00040000) /* */
\r
11802 /* DWT_CTRL[DWT_CTRL_SLEEPEVTENA] Bits */
\r
11803 #define DWT_CTRL_SLEEPEVTENA_OFS (19) /* SLEEPEVTENA Offset */
\r
11804 #define DWT_CTRL_SLEEPEVTENA (0x00080000) /* */
\r
11805 /* DWT_CTRL[DWT_CTRL_LSUEVTENA] Bits */
\r
11806 #define DWT_CTRL_LSUEVTENA_OFS (20) /* LSUEVTENA Offset */
\r
11807 #define DWT_CTRL_LSUEVTENA (0x00100000) /* */
\r
11808 /* DWT_CTRL[DWT_CTRL_FOLDEVTENA] Bits */
\r
11809 #define DWT_CTRL_FOLDEVTENA_OFS (21) /* FOLDEVTENA Offset */
\r
11810 #define DWT_CTRL_FOLDEVTENA (0x00200000) /* */
\r
11811 /* DWT_CTRL[DWT_CTRL_CYCEVTENA] Bits */
\r
11812 #define DWT_CTRL_CYCEVTENA_OFS (22) /* CYCEVTENA Offset */
\r
11813 #define DWT_CTRL_CYCEVTENA (0x00400000) /* */
\r
11814 /* DWT_CTRL[DWT_CTRL_NOPRFCNT] Bits */
\r
11815 #define DWT_CTRL_NOPRFCNT_OFS (24) /* NOPRFCNT Offset */
\r
11816 #define DWT_CTRL_NOPRFCNT (0x01000000) /* */
\r
11817 /* DWT_CTRL[DWT_CTRL_NOCYCCNT] Bits */
\r
11818 #define DWT_CTRL_NOCYCCNT_OFS (25) /* NOCYCCNT Offset */
\r
11819 #define DWT_CTRL_NOCYCCNT (0x02000000) /* */
\r
11820 /* DWT_CPICNT[DWT_CPICNT_CPICNT] Bits */
\r
11821 #define DWT_CPICNT_CPICNT_OFS ( 0) /* CPICNT Offset */
\r
11822 #define DWT_CPICNT_CPICNT_M (0x000000ff) /* */
\r
11823 /* DWT_EXCCNT[DWT_EXCCNT_EXCCNT] Bits */
\r
11824 #define DWT_EXCCNT_EXCCNT_OFS ( 0) /* EXCCNT Offset */
\r
11825 #define DWT_EXCCNT_EXCCNT_M (0x000000ff) /* */
\r
11826 /* DWT_SLEEPCNT[DWT_SLEEPCNT_SLEEPCNT] Bits */
\r
11827 #define DWT_SLEEPCNT_SLEEPCNT_OFS ( 0) /* SLEEPCNT Offset */
\r
11828 #define DWT_SLEEPCNT_SLEEPCNT_M (0x000000ff) /* */
\r
11829 /* DWT_LSUCNT[DWT_LSUCNT_LSUCNT] Bits */
\r
11830 #define DWT_LSUCNT_LSUCNT_OFS ( 0) /* LSUCNT Offset */
\r
11831 #define DWT_LSUCNT_LSUCNT_M (0x000000ff) /* */
\r
11832 /* DWT_FOLDCNT[DWT_FOLDCNT_FOLDCNT] Bits */
\r
11833 #define DWT_FOLDCNT_FOLDCNT_OFS ( 0) /* FOLDCNT Offset */
\r
11834 #define DWT_FOLDCNT_FOLDCNT_M (0x000000ff) /* */
\r
11835 /* DWT_MASK0[DWT_MASK0_MASK] Bits */
\r
11836 #define DWT_MASK0_MASK_OFS ( 0) /* MASK Offset */
\r
11837 #define DWT_MASK0_MASK_M (0x0000000f) /* */
\r
11838 /* DWT_FUNCTION0[DWT_FUNCTION0_FUNCTION] Bits */
\r
11839 #define DWT_FUNCTION0_FUNCTION_OFS ( 0) /* FUNCTION Offset */
\r
11840 #define DWT_FUNCTION0_FUNCTION_M (0x0000000f) /* */
\r
11841 #define DWT_FUNCTION0_FUNCTION0 (0x00000001) /* */
\r
11842 #define DWT_FUNCTION0_FUNCTION1 (0x00000002) /* */
\r
11843 #define DWT_FUNCTION0_FUNCTION2 (0x00000004) /* */
\r
11844 #define DWT_FUNCTION0_FUNCTION3 (0x00000008) /* */
\r
11845 #define DWT_FUNCTION0_FUNCTION_0 (0x00000000) /* Disabled */
\r
11846 #define DWT_FUNCTION0_FUNCTION_1 (0x00000001) /* EMITRANGE = 0, sample and emit PC through ITM. EMITRANGE = 1, emit address offset through ITM */
\r
11847 #define DWT_FUNCTION0_FUNCTION_2 (0x00000002) /* EMITRANGE = 0, emit data through ITM on read and write. EMITRANGE = 1, emit data and address offset through ITM on read or write. */
\r
11848 #define DWT_FUNCTION0_FUNCTION_3 (0x00000003) /* EMITRANGE = 0, sample PC and data value through ITM on read or write. EMITRANGE = 1, emit address offset and data value through ITM on read or write. */
\r
11849 #define DWT_FUNCTION0_FUNCTION_4 (0x00000004) /* Watchpoint on PC match. */
\r
11850 #define DWT_FUNCTION0_FUNCTION_5 (0x00000005) /* Watchpoint on read. */
\r
11851 #define DWT_FUNCTION0_FUNCTION_6 (0x00000006) /* Watchpoint on write. */
\r
11852 #define DWT_FUNCTION0_FUNCTION_7 (0x00000007) /* Watchpoint on read or write. */
\r
11853 #define DWT_FUNCTION0_FUNCTION_8 (0x00000008) /* ETM trigger on PC match */
\r
11854 #define DWT_FUNCTION0_FUNCTION_9 (0x00000009) /* ETM trigger on read */
\r
11855 #define DWT_FUNCTION0_FUNCTION_10 (0x0000000a) /* ETM trigger on write */
\r
11856 #define DWT_FUNCTION0_FUNCTION_11 (0x0000000b) /* ETM trigger on read or write */
\r
11857 #define DWT_FUNCTION0_FUNCTION_12 (0x0000000c) /* EMITRANGE = 0, sample data for read transfers. EMITRANGE = 1, sample Daddr [15:0] for read transfers */
\r
11858 #define DWT_FUNCTION0_FUNCTION_13 (0x0000000d) /* EMITRANGE = 0, sample data for write transfers. EMITRANGE = 1, sample Daddr [15:0] for write transfers */
\r
11859 #define DWT_FUNCTION0_FUNCTION_14 (0x0000000e) /* EMITRANGE = 0, sample PC + data for read transfers. EMITRANGE = 1, sample Daddr [15:0] + data for read transfers */
\r
11860 #define DWT_FUNCTION0_FUNCTION_15 (0x0000000f) /* EMITRANGE = 0, sample PC + data for write transfers. EMITRANGE = 1, sample Daddr [15:0] + data for write transfers */
\r
11861 /* DWT_FUNCTION0[DWT_FUNCTION0_EMITRANGE] Bits */
\r
11862 #define DWT_FUNCTION0_EMITRANGE_OFS ( 5) /* EMITRANGE Offset */
\r
11863 #define DWT_FUNCTION0_EMITRANGE (0x00000020) /* */
\r
11864 /* DWT_FUNCTION0[DWT_FUNCTION0_DATAVMATCH] Bits */
\r
11865 #define DWT_FUNCTION0_DATAVMATCH_OFS ( 8) /* DATAVMATCH Offset */
\r
11866 #define DWT_FUNCTION0_DATAVMATCH (0x00000100) /* */
\r
11867 /* DWT_FUNCTION0[DWT_FUNCTION0_LNK1ENA] Bits */
\r
11868 #define DWT_FUNCTION0_LNK1ENA_OFS ( 9) /* LNK1ENA Offset */
\r
11869 #define DWT_FUNCTION0_LNK1ENA (0x00000200) /* */
\r
11870 /* DWT_FUNCTION0[DWT_FUNCTION0_DATAVSIZE] Bits */
\r
11871 #define DWT_FUNCTION0_DATAVSIZE_OFS (10) /* DATAVSIZE Offset */
\r
11872 #define DWT_FUNCTION0_DATAVSIZE_M (0x00000c00) /* */
\r
11873 #define DWT_FUNCTION0_DATAVSIZE0 (0x00000400) /* */
\r
11874 #define DWT_FUNCTION0_DATAVSIZE1 (0x00000800) /* */
\r
11875 #define DWT_FUNCTION0_DATAVSIZE_0 (0x00000000) /* byte */
\r
11876 #define DWT_FUNCTION0_DATAVSIZE_1 (0x00000400) /* halfword */
\r
11877 #define DWT_FUNCTION0_DATAVSIZE_2 (0x00000800) /* word */
\r
11878 #define DWT_FUNCTION0_DATAVSIZE_3 (0x00000c00) /* Unpredictable. */
\r
11879 /* DWT_FUNCTION0[DWT_FUNCTION0_DATAVADDR0] Bits */
\r
11880 #define DWT_FUNCTION0_DATAVADDR0_OFS (12) /* DATAVADDR0 Offset */
\r
11881 #define DWT_FUNCTION0_DATAVADDR0_M (0x0000f000) /* */
\r
11882 /* DWT_FUNCTION0[DWT_FUNCTION0_DATAVADDR1] Bits */
\r
11883 #define DWT_FUNCTION0_DATAVADDR1_OFS (16) /* DATAVADDR1 Offset */
\r
11884 #define DWT_FUNCTION0_DATAVADDR1_M (0x000f0000) /* */
\r
11885 /* DWT_FUNCTION0[DWT_FUNCTION0_MATCHED] Bits */
\r
11886 #define DWT_FUNCTION0_MATCHED_OFS (24) /* MATCHED Offset */
\r
11887 #define DWT_FUNCTION0_MATCHED (0x01000000) /* */
\r
11888 /* DWT_MASK1[DWT_MASK1_MASK] Bits */
\r
11889 #define DWT_MASK1_MASK_OFS ( 0) /* MASK Offset */
\r
11890 #define DWT_MASK1_MASK_M (0x0000000f) /* */
\r
11891 /* DWT_FUNCTION1[DWT_FUNCTION1_FUNCTION] Bits */
\r
11892 #define DWT_FUNCTION1_FUNCTION_OFS ( 0) /* FUNCTION Offset */
\r
11893 #define DWT_FUNCTION1_FUNCTION_M (0x0000000f) /* */
\r
11894 #define DWT_FUNCTION1_FUNCTION0 (0x00000001) /* */
\r
11895 #define DWT_FUNCTION1_FUNCTION1 (0x00000002) /* */
\r
11896 #define DWT_FUNCTION1_FUNCTION2 (0x00000004) /* */
\r
11897 #define DWT_FUNCTION1_FUNCTION3 (0x00000008) /* */
\r
11898 #define DWT_FUNCTION1_FUNCTION_0 (0x00000000) /* Disabled */
\r
11899 #define DWT_FUNCTION1_FUNCTION_1 (0x00000001) /* EMITRANGE = 0, sample and emit PC through ITM. EMITRANGE = 1, emit address offset through ITM */
\r
11900 #define DWT_FUNCTION1_FUNCTION_2 (0x00000002) /* EMITRANGE = 0, emit data through ITM on read and write. EMITRANGE = 1, emit data and address offset through ITM on read or write. */
\r
11901 #define DWT_FUNCTION1_FUNCTION_3 (0x00000003) /* EMITRANGE = 0, sample PC and data value through ITM on read or write. EMITRANGE = 1, emit address offset and data value through ITM on read or write. */
\r
11902 #define DWT_FUNCTION1_FUNCTION_4 (0x00000004) /* Watchpoint on PC match. */
\r
11903 #define DWT_FUNCTION1_FUNCTION_5 (0x00000005) /* Watchpoint on read. */
\r
11904 #define DWT_FUNCTION1_FUNCTION_6 (0x00000006) /* Watchpoint on write. */
\r
11905 #define DWT_FUNCTION1_FUNCTION_7 (0x00000007) /* Watchpoint on read or write. */
\r
11906 #define DWT_FUNCTION1_FUNCTION_8 (0x00000008) /* ETM trigger on PC match */
\r
11907 #define DWT_FUNCTION1_FUNCTION_9 (0x00000009) /* ETM trigger on read */
\r
11908 #define DWT_FUNCTION1_FUNCTION_10 (0x0000000a) /* ETM trigger on write */
\r
11909 #define DWT_FUNCTION1_FUNCTION_11 (0x0000000b) /* ETM trigger on read or write */
\r
11910 #define DWT_FUNCTION1_FUNCTION_12 (0x0000000c) /* EMITRANGE = 0, sample data for read transfers. EMITRANGE = 1, sample Daddr [15:0] for read transfers */
\r
11911 #define DWT_FUNCTION1_FUNCTION_13 (0x0000000d) /* EMITRANGE = 0, sample data for write transfers. EMITRANGE = 1, sample Daddr [15:0] for write transfers */
\r
11912 #define DWT_FUNCTION1_FUNCTION_14 (0x0000000e) /* EMITRANGE = 0, sample PC + data for read transfers. EMITRANGE = 1, sample Daddr [15:0] + data for read transfers */
\r
11913 #define DWT_FUNCTION1_FUNCTION_15 (0x0000000f) /* EMITRANGE = 0, sample PC + data for write transfers. EMITRANGE = 1, sample Daddr [15:0] + data for write transfers */
\r
11914 /* DWT_FUNCTION1[DWT_FUNCTION1_EMITRANGE] Bits */
\r
11915 #define DWT_FUNCTION1_EMITRANGE_OFS ( 5) /* EMITRANGE Offset */
\r
11916 #define DWT_FUNCTION1_EMITRANGE (0x00000020) /* */
\r
11917 /* DWT_FUNCTION1[DWT_FUNCTION1_CYCMATCH] Bits */
\r
11918 #define DWT_FUNCTION1_CYCMATCH_OFS ( 7) /* CYCMATCH Offset */
\r
11919 #define DWT_FUNCTION1_CYCMATCH (0x00000080) /* */
\r
11920 /* DWT_FUNCTION1[DWT_FUNCTION1_DATAVMATCH] Bits */
\r
11921 #define DWT_FUNCTION1_DATAVMATCH_OFS ( 8) /* DATAVMATCH Offset */
\r
11922 #define DWT_FUNCTION1_DATAVMATCH (0x00000100) /* */
\r
11923 /* DWT_FUNCTION1[DWT_FUNCTION1_LNK1ENA] Bits */
\r
11924 #define DWT_FUNCTION1_LNK1ENA_OFS ( 9) /* LNK1ENA Offset */
\r
11925 #define DWT_FUNCTION1_LNK1ENA (0x00000200) /* */
\r
11926 /* DWT_FUNCTION1[DWT_FUNCTION1_DATAVSIZE] Bits */
\r
11927 #define DWT_FUNCTION1_DATAVSIZE_OFS (10) /* DATAVSIZE Offset */
\r
11928 #define DWT_FUNCTION1_DATAVSIZE_M (0x00000c00) /* */
\r
11929 #define DWT_FUNCTION1_DATAVSIZE0 (0x00000400) /* */
\r
11930 #define DWT_FUNCTION1_DATAVSIZE1 (0x00000800) /* */
\r
11931 #define DWT_FUNCTION1_DATAVSIZE_0 (0x00000000) /* byte */
\r
11932 #define DWT_FUNCTION1_DATAVSIZE_1 (0x00000400) /* halfword */
\r
11933 #define DWT_FUNCTION1_DATAVSIZE_2 (0x00000800) /* word */
\r
11934 #define DWT_FUNCTION1_DATAVSIZE_3 (0x00000c00) /* Unpredictable. */
\r
11935 /* DWT_FUNCTION1[DWT_FUNCTION1_DATAVADDR0] Bits */
\r
11936 #define DWT_FUNCTION1_DATAVADDR0_OFS (12) /* DATAVADDR0 Offset */
\r
11937 #define DWT_FUNCTION1_DATAVADDR0_M (0x0000f000) /* */
\r
11938 /* DWT_FUNCTION1[DWT_FUNCTION1_DATAVADDR1] Bits */
\r
11939 #define DWT_FUNCTION1_DATAVADDR1_OFS (16) /* DATAVADDR1 Offset */
\r
11940 #define DWT_FUNCTION1_DATAVADDR1_M (0x000f0000) /* */
\r
11941 /* DWT_FUNCTION1[DWT_FUNCTION1_MATCHED] Bits */
\r
11942 #define DWT_FUNCTION1_MATCHED_OFS (24) /* MATCHED Offset */
\r
11943 #define DWT_FUNCTION1_MATCHED (0x01000000) /* */
\r
11944 /* DWT_MASK2[DWT_MASK2_MASK] Bits */
\r
11945 #define DWT_MASK2_MASK_OFS ( 0) /* MASK Offset */
\r
11946 #define DWT_MASK2_MASK_M (0x0000000f) /* */
\r
11947 /* DWT_FUNCTION2[DWT_FUNCTION2_FUNCTION] Bits */
\r
11948 #define DWT_FUNCTION2_FUNCTION_OFS ( 0) /* FUNCTION Offset */
\r
11949 #define DWT_FUNCTION2_FUNCTION_M (0x0000000f) /* */
\r
11950 #define DWT_FUNCTION2_FUNCTION0 (0x00000001) /* */
\r
11951 #define DWT_FUNCTION2_FUNCTION1 (0x00000002) /* */
\r
11952 #define DWT_FUNCTION2_FUNCTION2 (0x00000004) /* */
\r
11953 #define DWT_FUNCTION2_FUNCTION3 (0x00000008) /* */
\r
11954 #define DWT_FUNCTION2_FUNCTION_0 (0x00000000) /* Disabled */
\r
11955 #define DWT_FUNCTION2_FUNCTION_1 (0x00000001) /* EMITRANGE = 0, sample and emit PC through ITM. EMITRANGE = 1, emit address offset through ITM */
\r
11956 #define DWT_FUNCTION2_FUNCTION_2 (0x00000002) /* EMITRANGE = 0, emit data through ITM on read and write. EMITRANGE = 1, emit data and address offset through ITM on read or write. */
\r
11957 #define DWT_FUNCTION2_FUNCTION_3 (0x00000003) /* EMITRANGE = 0, sample PC and data value through ITM on read or write. EMITRANGE = 1, emit address offset and data value through ITM on read or write. */
\r
11958 #define DWT_FUNCTION2_FUNCTION_4 (0x00000004) /* Watchpoint on PC match. */
\r
11959 #define DWT_FUNCTION2_FUNCTION_5 (0x00000005) /* Watchpoint on read. */
\r
11960 #define DWT_FUNCTION2_FUNCTION_6 (0x00000006) /* Watchpoint on write. */
\r
11961 #define DWT_FUNCTION2_FUNCTION_7 (0x00000007) /* Watchpoint on read or write. */
\r
11962 #define DWT_FUNCTION2_FUNCTION_8 (0x00000008) /* ETM trigger on PC match */
\r
11963 #define DWT_FUNCTION2_FUNCTION_9 (0x00000009) /* ETM trigger on read */
\r
11964 #define DWT_FUNCTION2_FUNCTION_10 (0x0000000a) /* ETM trigger on write */
\r
11965 #define DWT_FUNCTION2_FUNCTION_11 (0x0000000b) /* ETM trigger on read or write */
\r
11966 #define DWT_FUNCTION2_FUNCTION_12 (0x0000000c) /* EMITRANGE = 0, sample data for read transfers. EMITRANGE = 1, sample Daddr [15:0] for read transfers */
\r
11967 #define DWT_FUNCTION2_FUNCTION_13 (0x0000000d) /* EMITRANGE = 0, sample data for write transfers. EMITRANGE = 1, sample Daddr [15:0] for write transfers */
\r
11968 #define DWT_FUNCTION2_FUNCTION_14 (0x0000000e) /* EMITRANGE = 0, sample PC + data for read transfers. EMITRANGE = 1, sample Daddr [15:0] + data for read transfers */
\r
11969 #define DWT_FUNCTION2_FUNCTION_15 (0x0000000f) /* EMITRANGE = 0, sample PC + data for write transfers. EMITRANGE = 1, sample Daddr [15:0] + data for write transfers */
\r
11970 /* DWT_FUNCTION2[DWT_FUNCTION2_EMITRANGE] Bits */
\r
11971 #define DWT_FUNCTION2_EMITRANGE_OFS ( 5) /* EMITRANGE Offset */
\r
11972 #define DWT_FUNCTION2_EMITRANGE (0x00000020) /* */
\r
11973 /* DWT_FUNCTION2[DWT_FUNCTION2_DATAVMATCH] Bits */
\r
11974 #define DWT_FUNCTION2_DATAVMATCH_OFS ( 8) /* DATAVMATCH Offset */
\r
11975 #define DWT_FUNCTION2_DATAVMATCH (0x00000100) /* */
\r
11976 /* DWT_FUNCTION2[DWT_FUNCTION2_LNK1ENA] Bits */
\r
11977 #define DWT_FUNCTION2_LNK1ENA_OFS ( 9) /* LNK1ENA Offset */
\r
11978 #define DWT_FUNCTION2_LNK1ENA (0x00000200) /* */
\r
11979 /* DWT_FUNCTION2[DWT_FUNCTION2_DATAVSIZE] Bits */
\r
11980 #define DWT_FUNCTION2_DATAVSIZE_OFS (10) /* DATAVSIZE Offset */
\r
11981 #define DWT_FUNCTION2_DATAVSIZE_M (0x00000c00) /* */
\r
11982 #define DWT_FUNCTION2_DATAVSIZE0 (0x00000400) /* */
\r
11983 #define DWT_FUNCTION2_DATAVSIZE1 (0x00000800) /* */
\r
11984 #define DWT_FUNCTION2_DATAVSIZE_0 (0x00000000) /* byte */
\r
11985 #define DWT_FUNCTION2_DATAVSIZE_1 (0x00000400) /* halfword */
\r
11986 #define DWT_FUNCTION2_DATAVSIZE_2 (0x00000800) /* word */
\r
11987 #define DWT_FUNCTION2_DATAVSIZE_3 (0x00000c00) /* Unpredictable. */
\r
11988 /* DWT_FUNCTION2[DWT_FUNCTION2_DATAVADDR0] Bits */
\r
11989 #define DWT_FUNCTION2_DATAVADDR0_OFS (12) /* DATAVADDR0 Offset */
\r
11990 #define DWT_FUNCTION2_DATAVADDR0_M (0x0000f000) /* */
\r
11991 /* DWT_FUNCTION2[DWT_FUNCTION2_DATAVADDR1] Bits */
\r
11992 #define DWT_FUNCTION2_DATAVADDR1_OFS (16) /* DATAVADDR1 Offset */
\r
11993 #define DWT_FUNCTION2_DATAVADDR1_M (0x000f0000) /* */
\r
11994 /* DWT_FUNCTION2[DWT_FUNCTION2_MATCHED] Bits */
\r
11995 #define DWT_FUNCTION2_MATCHED_OFS (24) /* MATCHED Offset */
\r
11996 #define DWT_FUNCTION2_MATCHED (0x01000000) /* */
\r
11997 /* DWT_MASK3[DWT_MASK3_MASK] Bits */
\r
11998 #define DWT_MASK3_MASK_OFS ( 0) /* MASK Offset */
\r
11999 #define DWT_MASK3_MASK_M (0x0000000f) /* */
\r
12000 /* DWT_FUNCTION3[DWT_FUNCTION3_FUNCTION] Bits */
\r
12001 #define DWT_FUNCTION3_FUNCTION_OFS ( 0) /* FUNCTION Offset */
\r
12002 #define DWT_FUNCTION3_FUNCTION_M (0x0000000f) /* */
\r
12003 #define DWT_FUNCTION3_FUNCTION0 (0x00000001) /* */
\r
12004 #define DWT_FUNCTION3_FUNCTION1 (0x00000002) /* */
\r
12005 #define DWT_FUNCTION3_FUNCTION2 (0x00000004) /* */
\r
12006 #define DWT_FUNCTION3_FUNCTION3 (0x00000008) /* */
\r
12007 #define DWT_FUNCTION3_FUNCTION_0 (0x00000000) /* Disabled */
\r
12008 #define DWT_FUNCTION3_FUNCTION_1 (0x00000001) /* EMITRANGE = 0, sample and emit PC through ITM. EMITRANGE = 1, emit address offset through ITM */
\r
12009 #define DWT_FUNCTION3_FUNCTION_2 (0x00000002) /* EMITRANGE = 0, emit data through ITM on read and write. EMITRANGE = 1, emit data and address offset through ITM on read or write. */
\r
12010 #define DWT_FUNCTION3_FUNCTION_3 (0x00000003) /* EMITRANGE = 0, sample PC and data value through ITM on read or write. EMITRANGE = 1, emit address offset and data value through ITM on read or write. */
\r
12011 #define DWT_FUNCTION3_FUNCTION_4 (0x00000004) /* Watchpoint on PC match. */
\r
12012 #define DWT_FUNCTION3_FUNCTION_5 (0x00000005) /* Watchpoint on read. */
\r
12013 #define DWT_FUNCTION3_FUNCTION_6 (0x00000006) /* Watchpoint on write. */
\r
12014 #define DWT_FUNCTION3_FUNCTION_7 (0x00000007) /* Watchpoint on read or write. */
\r
12015 #define DWT_FUNCTION3_FUNCTION_8 (0x00000008) /* ETM trigger on PC match */
\r
12016 #define DWT_FUNCTION3_FUNCTION_9 (0x00000009) /* ETM trigger on read */
\r
12017 #define DWT_FUNCTION3_FUNCTION_10 (0x0000000a) /* ETM trigger on write */
\r
12018 #define DWT_FUNCTION3_FUNCTION_11 (0x0000000b) /* ETM trigger on read or write */
\r
12019 #define DWT_FUNCTION3_FUNCTION_12 (0x0000000c) /* EMITRANGE = 0, sample data for read transfers. EMITRANGE = 1, sample Daddr [15:0] for read transfers */
\r
12020 #define DWT_FUNCTION3_FUNCTION_13 (0x0000000d) /* EMITRANGE = 0, sample data for write transfers. EMITRANGE = 1, sample Daddr [15:0] for write transfers */
\r
12021 #define DWT_FUNCTION3_FUNCTION_14 (0x0000000e) /* EMITRANGE = 0, sample PC + data for read transfers. EMITRANGE = 1, sample Daddr [15:0] + data for read transfers */
\r
12022 #define DWT_FUNCTION3_FUNCTION_15 (0x0000000f) /* EMITRANGE = 0, sample PC + data for write transfers. EMITRANGE = 1, sample Daddr [15:0] + data for write transfers */
\r
12023 /* DWT_FUNCTION3[DWT_FUNCTION3_EMITRANGE] Bits */
\r
12024 #define DWT_FUNCTION3_EMITRANGE_OFS ( 5) /* EMITRANGE Offset */
\r
12025 #define DWT_FUNCTION3_EMITRANGE (0x00000020) /* */
\r
12026 /* DWT_FUNCTION3[DWT_FUNCTION3_DATAVMATCH] Bits */
\r
12027 #define DWT_FUNCTION3_DATAVMATCH_OFS ( 8) /* DATAVMATCH Offset */
\r
12028 #define DWT_FUNCTION3_DATAVMATCH (0x00000100) /* */
\r
12029 /* DWT_FUNCTION3[DWT_FUNCTION3_LNK1ENA] Bits */
\r
12030 #define DWT_FUNCTION3_LNK1ENA_OFS ( 9) /* LNK1ENA Offset */
\r
12031 #define DWT_FUNCTION3_LNK1ENA (0x00000200) /* */
\r
12032 /* DWT_FUNCTION3[DWT_FUNCTION3_DATAVSIZE] Bits */
\r
12033 #define DWT_FUNCTION3_DATAVSIZE_OFS (10) /* DATAVSIZE Offset */
\r
12034 #define DWT_FUNCTION3_DATAVSIZE_M (0x00000c00) /* */
\r
12035 #define DWT_FUNCTION3_DATAVSIZE0 (0x00000400) /* */
\r
12036 #define DWT_FUNCTION3_DATAVSIZE1 (0x00000800) /* */
\r
12037 #define DWT_FUNCTION3_DATAVSIZE_0 (0x00000000) /* byte */
\r
12038 #define DWT_FUNCTION3_DATAVSIZE_1 (0x00000400) /* halfword */
\r
12039 #define DWT_FUNCTION3_DATAVSIZE_2 (0x00000800) /* word */
\r
12040 #define DWT_FUNCTION3_DATAVSIZE_3 (0x00000c00) /* Unpredictable. */
\r
12041 /* DWT_FUNCTION3[DWT_FUNCTION3_DATAVADDR0] Bits */
\r
12042 #define DWT_FUNCTION3_DATAVADDR0_OFS (12) /* DATAVADDR0 Offset */
\r
12043 #define DWT_FUNCTION3_DATAVADDR0_M (0x0000f000) /* */
\r
12044 /* DWT_FUNCTION3[DWT_FUNCTION3_DATAVADDR1] Bits */
\r
12045 #define DWT_FUNCTION3_DATAVADDR1_OFS (16) /* DATAVADDR1 Offset */
\r
12046 #define DWT_FUNCTION3_DATAVADDR1_M (0x000f0000) /* */
\r
12047 /* DWT_FUNCTION3[DWT_FUNCTION3_MATCHED] Bits */
\r
12048 #define DWT_FUNCTION3_MATCHED_OFS (24) /* MATCHED Offset */
\r
12049 #define DWT_FUNCTION3_MATCHED (0x01000000) /* */
\r
12052 //*****************************************************************************
\r
12054 //*****************************************************************************
\r
12055 /* UCA0CTLW0[UCSWRST] Bits */
\r
12056 #define UCSWRST_OFS ( 0) /* UCSWRST Offset */
\r
12057 #define UCSWRST (0x0001) /* Software reset enable */
\r
12058 /* UCA0CTLW0[UCTXBRK] Bits */
\r
12059 #define UCTXBRK_OFS ( 1) /* UCTXBRK Offset */
\r
12060 #define UCTXBRK (0x0002) /* Transmit break */
\r
12061 /* UCA0CTLW0[UCTXADDR] Bits */
\r
12062 #define UCTXADDR_OFS ( 2) /* UCTXADDR Offset */
\r
12063 #define UCTXADDR (0x0004) /* Transmit address */
\r
12064 /* UCA0CTLW0[UCDORM] Bits */
\r
12065 #define UCDORM_OFS ( 3) /* UCDORM Offset */
\r
12066 #define UCDORM (0x0008) /* Dormant */
\r
12067 /* UCA0CTLW0[UCBRKIE] Bits */
\r
12068 #define UCBRKIE_OFS ( 4) /* UCBRKIE Offset */
\r
12069 #define UCBRKIE (0x0010) /* Receive break character interrupt enable */
\r
12070 /* UCA0CTLW0[UCRXEIE] Bits */
\r
12071 #define UCRXEIE_OFS ( 5) /* UCRXEIE Offset */
\r
12072 #define UCRXEIE (0x0020) /* Receive erroneous-character interrupt enable */
\r
12073 /* UCA0CTLW0[UCSSEL] Bits */
\r
12074 #define UCSSEL_OFS ( 6) /* UCSSEL Offset */
\r
12075 #define UCSSEL_M (0x00c0) /* eUSCI_A clock source select */
\r
12076 #define UCSSEL0 (0x0040) /* eUSCI_A clock source select */
\r
12077 #define UCSSEL1 (0x0080) /* eUSCI_A clock source select */
\r
12078 #define UCSSEL_0 (0x0000) /* UCLK */
\r
12079 #define UCSSEL_1 (0x0040) /* ACLK */
\r
12080 #define UCSSEL_2 (0x0080) /* SMCLK */
\r
12081 #define UCSSEL__UCLK (0x0000) /* UCLK */
\r
12082 #define UCSSEL__ACLK (0x0040) /* ACLK */
\r
12083 #define UCSSEL__SMCLK (0x0080) /* SMCLK */
\r
12084 /* UCA0CTLW0[UCSYNC] Bits */
\r
12085 #define UCSYNC_OFS ( 8) /* UCSYNC Offset */
\r
12086 #define UCSYNC (0x0100) /* Synchronous mode enable */
\r
12087 /* UCA0CTLW0[UCMODE] Bits */
\r
12088 #define UCMODE_OFS ( 9) /* UCMODE Offset */
\r
12089 #define UCMODE_M (0x0600) /* eUSCI_A mode */
\r
12090 #define UCMODE0 (0x0200) /* eUSCI_A mode */
\r
12091 #define UCMODE1 (0x0400) /* eUSCI_A mode */
\r
12092 #define UCMODE_0 (0x0000) /* UART mode */
\r
12093 #define UCMODE_1 (0x0200) /* Idle-line multiprocessor mode */
\r
12094 #define UCMODE_2 (0x0400) /* Address-bit multiprocessor mode */
\r
12095 #define UCMODE_3 (0x0600) /* UART mode with automatic baud-rate detection */
\r
12096 /* UCA0CTLW0[UCSPB] Bits */
\r
12097 #define UCSPB_OFS (11) /* UCSPB Offset */
\r
12098 #define UCSPB (0x0800) /* Stop bit select */
\r
12099 /* UCA0CTLW0[UC7BIT] Bits */
\r
12100 #define UC7BIT_OFS (12) /* UC7BIT Offset */
\r
12101 #define UC7BIT (0x1000) /* Character length */
\r
12102 /* UCA0CTLW0[UCMSB] Bits */
\r
12103 #define UCMSB_OFS (13) /* UCMSB Offset */
\r
12104 #define UCMSB (0x2000) /* MSB first select */
\r
12105 /* UCA0CTLW0[UCPAR] Bits */
\r
12106 #define UCPAR_OFS (14) /* UCPAR Offset */
\r
12107 #define UCPAR (0x4000) /* Parity select */
\r
12108 /* UCA0CTLW0[UCPEN] Bits */
\r
12109 #define UCPEN_OFS (15) /* UCPEN Offset */
\r
12110 #define UCPEN (0x8000) /* Parity enable */
\r
12111 /* UCA0CTLW0_SPI[UCSWRST] Bits */
\r
12112 //#define UCSWRST_OFS ( 0) /* UCSWRST Offset */
\r
12113 //#define UCSWRST (0x0001) /* Software reset enable */
\r
12114 /* UCA0CTLW0_SPI[UCSTEM] Bits */
\r
12115 #define UCSTEM_OFS ( 1) /* UCSTEM Offset */
\r
12116 #define UCSTEM (0x0002) /* STE mode select in master mode. */
\r
12117 /* UCA0CTLW0_SPI[UCSSEL] Bits */
\r
12118 //#define UCSSEL_OFS ( 6) /* UCSSEL Offset */
\r
12119 //#define UCSSEL_M (0x00c0) /* eUSCI_A clock source select */
\r
12120 //#define UCSSEL0 (0x0040) /* eUSCI_A clock source select */
\r
12121 //#define UCSSEL1 (0x0080) /* eUSCI_A clock source select */
\r
12122 //#define UCSSEL_1 (0x0040) /* ACLK */
\r
12123 //#define UCSSEL_2 (0x0080) /* SMCLK */
\r
12124 //#define UCSSEL_0 (0x0000) /* Reserved */
\r
12125 //#define UCSSEL__ACLK (0x0040) /* ACLK */
\r
12126 //#define UCSSEL__SMCLK (0x0080) /* SMCLK */
\r
12127 /* UCA0CTLW0_SPI[UCSYNC] Bits */
\r
12128 //#define UCSYNC_OFS ( 8) /* UCSYNC Offset */
\r
12129 //#define UCSYNC (0x0100) /* Synchronous mode enable */
\r
12130 /* UCA0CTLW0_SPI[UCMODE] Bits */
\r
12131 //#define UCMODE_OFS ( 9) /* UCMODE Offset */
\r
12132 //#define UCMODE_M (0x0600) /* eUSCI mode */
\r
12133 //#define UCMODE0 (0x0200) /* eUSCI mode */
\r
12134 //#define UCMODE1 (0x0400) /* eUSCI mode */
\r
12135 //#define UCMODE_0 (0x0000) /* 3-pin SPI */
\r
12136 //#define UCMODE_1 (0x0200) /* 4-pin SPI with UCxSTE active high: Slave enabled when UCxSTE = 1 */
\r
12137 //#define UCMODE_2 (0x0400) /* 4-pin SPI with UCxSTE active low: Slave enabled when UCxSTE = 0 */
\r
12138 /* UCA0CTLW0_SPI[UCMST] Bits */
\r
12139 #define UCMST_OFS (11) /* UCMST Offset */
\r
12140 #define UCMST (0x0800) /* Master mode select */
\r
12141 /* UCA0CTLW0_SPI[UC7BIT] Bits */
\r
12142 //#define UC7BIT_OFS (12) /* UC7BIT Offset */
\r
12143 //#define UC7BIT (0x1000) /* Character length */
\r
12144 /* UCA0CTLW0_SPI[UCMSB] Bits */
\r
12145 //#define UCMSB_OFS (13) /* UCMSB Offset */
\r
12146 //#define UCMSB (0x2000) /* MSB first select */
\r
12147 /* UCA0CTLW0_SPI[UCCKPL] Bits */
\r
12148 #define UCCKPL_OFS (14) /* UCCKPL Offset */
\r
12149 #define UCCKPL (0x4000) /* Clock polarity select */
\r
12150 /* UCA0CTLW0_SPI[UCCKPH] Bits */
\r
12151 #define UCCKPH_OFS (15) /* UCCKPH Offset */
\r
12152 #define UCCKPH (0x8000) /* Clock phase select */
\r
12153 /* UCA0CTLW1[UCGLIT] Bits */
\r
12154 #define UCGLIT_OFS ( 0) /* UCGLIT Offset */
\r
12155 #define UCGLIT_M (0x0003) /* Deglitch time */
\r
12156 #define UCGLIT0 (0x0001) /* Deglitch time */
\r
12157 #define UCGLIT1 (0x0002) /* Deglitch time */
\r
12158 #define UCGLIT_0 (0x0000) /* Approximately 2 ns (equivalent of 1 delay element) */
\r
12159 #define UCGLIT_1 (0x0001) /* Approximately 50 ns */
\r
12160 #define UCGLIT_2 (0x0002) /* Approximately 100 ns */
\r
12161 #define UCGLIT_3 (0x0003) /* Approximately 200 ns */
\r
12162 /* UCA0MCTLW[UCOS16] Bits */
\r
12163 #define UCOS16_OFS ( 0) /* UCOS16 Offset */
\r
12164 #define UCOS16 (0x0001) /* Oversampling mode enabled */
\r
12165 /* UCA0MCTLW[UCBRF] Bits */
\r
12166 #define UCBRF_OFS ( 4) /* UCBRF Offset */
\r
12167 #define UCBRF_M (0x00f0) /* First modulation stage select */
\r
12168 /* UCA0MCTLW[UCBRS] Bits */
\r
12169 #define UCBRS_OFS ( 8) /* UCBRS Offset */
\r
12170 #define UCBRS_M (0xff00) /* Second modulation stage select */
\r
12171 /* UCA0STATW[UCBUSY] Bits */
\r
12172 #define UCBUSY_OFS ( 0) /* UCBUSY Offset */
\r
12173 #define UCBUSY (0x0001) /* eUSCI_A busy */
\r
12174 /* UCA0STATW[UCADDR_UCIDLE] Bits */
\r
12175 #define UCADDR_UCIDLE_OFS ( 1) /* UCADDR_UCIDLE Offset */
\r
12176 #define UCADDR_UCIDLE (0x0002) /* Address received / Idle line detected */
\r
12177 /* UCA0STATW[UCRXERR] Bits */
\r
12178 #define UCRXERR_OFS ( 2) /* UCRXERR Offset */
\r
12179 #define UCRXERR (0x0004) /* Receive error flag */
\r
12180 /* UCA0STATW[UCBRK] Bits */
\r
12181 #define UCBRK_OFS ( 3) /* UCBRK Offset */
\r
12182 #define UCBRK (0x0008) /* Break detect flag */
\r
12183 /* UCA0STATW[UCPE] Bits */
\r
12184 #define UCPE_OFS ( 4) /* UCPE Offset */
\r
12185 #define UCPE (0x0010) /* */
\r
12186 /* UCA0STATW[UCOE] Bits */
\r
12187 #define UCOE_OFS ( 5) /* UCOE Offset */
\r
12188 #define UCOE (0x0020) /* Overrun error flag */
\r
12189 /* UCA0STATW[UCFE] Bits */
\r
12190 #define UCFE_OFS ( 6) /* UCFE Offset */
\r
12191 #define UCFE (0x0040) /* Framing error flag */
\r
12192 /* UCA0STATW[UCLISTEN] Bits */
\r
12193 #define UCLISTEN_OFS ( 7) /* UCLISTEN Offset */
\r
12194 #define UCLISTEN (0x0080) /* Listen enable */
\r
12195 /* UCA0STATW_SPI[UCBUSY] Bits */
\r
12196 //#define UCBUSY_OFS ( 0) /* UCBUSY Offset */
\r
12197 //#define UCBUSY (0x0001) /* eUSCI_A busy */
\r
12198 /* UCA0STATW_SPI[UCOE] Bits */
\r
12199 //#define UCOE_OFS ( 5) /* UCOE Offset */
\r
12200 //#define UCOE (0x0020) /* Overrun error flag */
\r
12201 /* UCA0STATW_SPI[UCFE] Bits */
\r
12202 //#define UCFE_OFS ( 6) /* UCFE Offset */
\r
12203 //#define UCFE (0x0040) /* Framing error flag */
\r
12204 /* UCA0STATW_SPI[UCLISTEN] Bits */
\r
12205 //#define UCLISTEN_OFS ( 7) /* UCLISTEN Offset */
\r
12206 //#define UCLISTEN (0x0080) /* Listen enable */
\r
12207 /* UCA0RXBUF[UCRXBUF] Bits */
\r
12208 #define UCRXBUF_OFS ( 0) /* UCRXBUF Offset */
\r
12209 #define UCRXBUF_M (0x00ff) /* Receive data buffer */
\r
12210 /* UCA0RXBUF_SPI[UCRXBUF] Bits */
\r
12211 //#define UCRXBUF_OFS ( 0) /* UCRXBUF Offset */
\r
12212 //#define UCRXBUF_M (0x00ff) /* Receive data buffer */
\r
12213 /* UCA0TXBUF[UCTXBUF] Bits */
\r
12214 #define UCTXBUF_OFS ( 0) /* UCTXBUF Offset */
\r
12215 #define UCTXBUF_M (0x00ff) /* Transmit data buffer */
\r
12216 /* UCA0TXBUF_SPI[UCTXBUF] Bits */
\r
12217 //#define UCTXBUF_OFS ( 0) /* UCTXBUF Offset */
\r
12218 //#define UCTXBUF_M (0x00ff) /* Transmit data buffer */
\r
12219 /* UCA0ABCTL[UCABDEN] Bits */
\r
12220 #define UCABDEN_OFS ( 0) /* UCABDEN Offset */
\r
12221 #define UCABDEN (0x0001) /* Automatic baud-rate detect enable */
\r
12222 /* UCA0ABCTL[UCBTOE] Bits */
\r
12223 #define UCBTOE_OFS ( 2) /* UCBTOE Offset */
\r
12224 #define UCBTOE (0x0004) /* Break time out error */
\r
12225 /* UCA0ABCTL[UCSTOE] Bits */
\r
12226 #define UCSTOE_OFS ( 3) /* UCSTOE Offset */
\r
12227 #define UCSTOE (0x0008) /* Synch field time out error */
\r
12228 /* UCA0ABCTL[UCDELIM] Bits */
\r
12229 #define UCDELIM_OFS ( 4) /* UCDELIM Offset */
\r
12230 #define UCDELIM_M (0x0030) /* Break/synch delimiter length */
\r
12231 #define UCDELIM0 (0x0010) /* Break/synch delimiter length */
\r
12232 #define UCDELIM1 (0x0020) /* Break/synch delimiter length */
\r
12233 #define UCDELIM_0 (0x0000) /* 1 bit time */
\r
12234 #define UCDELIM_1 (0x0010) /* 2 bit times */
\r
12235 #define UCDELIM_2 (0x0020) /* 3 bit times */
\r
12236 #define UCDELIM_3 (0x0030) /* 4 bit times */
\r
12237 /* UCA0IRCTL[UCIREN] Bits */
\r
12238 #define UCIREN_OFS ( 0) /* UCIREN Offset */
\r
12239 #define UCIREN (0x0001) /* IrDA encoder/decoder enable */
\r
12240 /* UCA0IRCTL[UCIRTXCLK] Bits */
\r
12241 #define UCIRTXCLK_OFS ( 1) /* UCIRTXCLK Offset */
\r
12242 #define UCIRTXCLK (0x0002) /* IrDA transmit pulse clock select */
\r
12243 /* UCA0IRCTL[UCIRTXPL] Bits */
\r
12244 #define UCIRTXPL_OFS ( 2) /* UCIRTXPL Offset */
\r
12245 #define UCIRTXPL_M (0x00fc) /* Transmit pulse length */
\r
12246 /* UCA0IRCTL[UCIRRXFE] Bits */
\r
12247 #define UCIRRXFE_OFS ( 8) /* UCIRRXFE Offset */
\r
12248 #define UCIRRXFE (0x0100) /* IrDA receive filter enabled */
\r
12249 /* UCA0IRCTL[UCIRRXPL] Bits */
\r
12250 #define UCIRRXPL_OFS ( 9) /* UCIRRXPL Offset */
\r
12251 #define UCIRRXPL (0x0200) /* IrDA receive input UCAxRXD polarity */
\r
12252 /* UCA0IRCTL[UCIRRXFL] Bits */
\r
12253 #define UCIRRXFL_OFS (10) /* UCIRRXFL Offset */
\r
12254 #define UCIRRXFL_M (0x3c00) /* Receive filter length */
\r
12255 /* UCA0IE[UCRXIE] Bits */
\r
12256 #define UCRXIE_OFS ( 0) /* UCRXIE Offset */
\r
12257 #define UCRXIE (0x0001) /* Receive interrupt enable */
\r
12258 /* UCA0IE[UCTXIE] Bits */
\r
12259 #define UCTXIE_OFS ( 1) /* UCTXIE Offset */
\r
12260 #define UCTXIE (0x0002) /* Transmit interrupt enable */
\r
12261 /* UCA0IE[UCSTTIE] Bits */
\r
12262 #define UCSTTIE_OFS ( 2) /* UCSTTIE Offset */
\r
12263 #define UCSTTIE (0x0004) /* Start bit interrupt enable */
\r
12264 /* UCA0IE[UCTXCPTIE] Bits */
\r
12265 #define UCTXCPTIE_OFS ( 3) /* UCTXCPTIE Offset */
\r
12266 #define UCTXCPTIE (0x0008) /* Transmit complete interrupt enable */
\r
12267 /* UCA0IE_SPI[UCRXIE] Bits */
\r
12268 //#define UCRXIE_OFS ( 0) /* UCRXIE Offset */
\r
12269 //#define UCRXIE (0x0001) /* Receive interrupt enable */
\r
12270 /* UCA0IE_SPI[UCTXIE] Bits */
\r
12271 //#define UCTXIE_OFS ( 1) /* UCTXIE Offset */
\r
12272 //#define UCTXIE (0x0002) /* Transmit interrupt enable */
\r
12273 /* UCA0IFG[UCRXIFG] Bits */
\r
12274 #define UCRXIFG_OFS ( 0) /* UCRXIFG Offset */
\r
12275 #define UCRXIFG (0x0001) /* Receive interrupt flag */
\r
12276 /* UCA0IFG[UCTXIFG] Bits */
\r
12277 #define UCTXIFG_OFS ( 1) /* UCTXIFG Offset */
\r
12278 #define UCTXIFG (0x0002) /* Transmit interrupt flag */
\r
12279 /* UCA0IFG[UCSTTIFG] Bits */
\r
12280 #define UCSTTIFG_OFS ( 2) /* UCSTTIFG Offset */
\r
12281 #define UCSTTIFG (0x0004) /* Start bit interrupt flag */
\r
12282 /* UCA0IFG[UCTXCPTIFG] Bits */
\r
12283 #define UCTXCPTIFG_OFS ( 3) /* UCTXCPTIFG Offset */
\r
12284 #define UCTXCPTIFG (0x0008) /* Transmit ready interrupt enable */
\r
12285 /* UCA0IFG_SPI[UCRXIFG] Bits */
\r
12286 //#define UCRXIFG_OFS ( 0) /* UCRXIFG Offset */
\r
12287 //#define UCRXIFG (0x0001) /* Receive interrupt flag */
\r
12288 /* UCA0IFG_SPI[UCTXIFG] Bits */
\r
12289 //#define UCTXIFG_OFS ( 1) /* UCTXIFG Offset */
\r
12290 //#define UCTXIFG (0x0002) /* Transmit interrupt flag */
\r
12293 //*****************************************************************************
\r
12295 //*****************************************************************************
\r
12296 /* UCA1CTLW0[UCSWRST] Bits */
\r
12297 //#define UCSWRST_OFS ( 0) /* UCSWRST Offset */
\r
12298 //#define UCSWRST (0x0001) /* Software reset enable */
\r
12299 /* UCA1CTLW0[UCTXBRK] Bits */
\r
12300 //#define UCTXBRK_OFS ( 1) /* UCTXBRK Offset */
\r
12301 //#define UCTXBRK (0x0002) /* Transmit break */
\r
12302 /* UCA1CTLW0[UCTXADDR] Bits */
\r
12303 //#define UCTXADDR_OFS ( 2) /* UCTXADDR Offset */
\r
12304 //#define UCTXADDR (0x0004) /* Transmit address */
\r
12305 /* UCA1CTLW0[UCDORM] Bits */
\r
12306 //#define UCDORM_OFS ( 3) /* UCDORM Offset */
\r
12307 //#define UCDORM (0x0008) /* Dormant */
\r
12308 /* UCA1CTLW0[UCBRKIE] Bits */
\r
12309 //#define UCBRKIE_OFS ( 4) /* UCBRKIE Offset */
\r
12310 //#define UCBRKIE (0x0010) /* Receive break character interrupt enable */
\r
12311 /* UCA1CTLW0[UCRXEIE] Bits */
\r
12312 //#define UCRXEIE_OFS ( 5) /* UCRXEIE Offset */
\r
12313 //#define UCRXEIE (0x0020) /* Receive erroneous-character interrupt enable */
\r
12314 /* UCA1CTLW0[UCSSEL] Bits */
\r
12315 //#define UCSSEL_OFS ( 6) /* UCSSEL Offset */
\r
12316 //#define UCSSEL_M (0x00c0) /* eUSCI_A clock source select */
\r
12317 //#define UCSSEL0 (0x0040) /* eUSCI_A clock source select */
\r
12318 //#define UCSSEL1 (0x0080) /* eUSCI_A clock source select */
\r
12319 //#define UCSSEL_0 (0x0000) /* UCLK */
\r
12320 //#define UCSSEL_1 (0x0040) /* ACLK */
\r
12321 //#define UCSSEL_2 (0x0080) /* SMCLK */
\r
12322 //#define UCSSEL__UCLK (0x0000) /* UCLK */
\r
12323 //#define UCSSEL__ACLK (0x0040) /* ACLK */
\r
12324 //#define UCSSEL__SMCLK (0x0080) /* SMCLK */
\r
12325 /* UCA1CTLW0[UCSYNC] Bits */
\r
12326 //#define UCSYNC_OFS ( 8) /* UCSYNC Offset */
\r
12327 //#define UCSYNC (0x0100) /* Synchronous mode enable */
\r
12328 /* UCA1CTLW0[UCMODE] Bits */
\r
12329 //#define UCMODE_OFS ( 9) /* UCMODE Offset */
\r
12330 //#define UCMODE_M (0x0600) /* eUSCI_A mode */
\r
12331 //#define UCMODE0 (0x0200) /* eUSCI_A mode */
\r
12332 //#define UCMODE1 (0x0400) /* eUSCI_A mode */
\r
12333 //#define UCMODE_0 (0x0000) /* UART mode */
\r
12334 //#define UCMODE_1 (0x0200) /* Idle-line multiprocessor mode */
\r
12335 //#define UCMODE_2 (0x0400) /* Address-bit multiprocessor mode */
\r
12336 //#define UCMODE_3 (0x0600) /* UART mode with automatic baud-rate detection */
\r
12337 /* UCA1CTLW0[UCSPB] Bits */
\r
12338 //#define UCSPB_OFS (11) /* UCSPB Offset */
\r
12339 //#define UCSPB (0x0800) /* Stop bit select */
\r
12340 /* UCA1CTLW0[UC7BIT] Bits */
\r
12341 //#define UC7BIT_OFS (12) /* UC7BIT Offset */
\r
12342 //#define UC7BIT (0x1000) /* Character length */
\r
12343 /* UCA1CTLW0[UCMSB] Bits */
\r
12344 //#define UCMSB_OFS (13) /* UCMSB Offset */
\r
12345 //#define UCMSB (0x2000) /* MSB first select */
\r
12346 /* UCA1CTLW0[UCPAR] Bits */
\r
12347 //#define UCPAR_OFS (14) /* UCPAR Offset */
\r
12348 //#define UCPAR (0x4000) /* Parity select */
\r
12349 /* UCA1CTLW0[UCPEN] Bits */
\r
12350 //#define UCPEN_OFS (15) /* UCPEN Offset */
\r
12351 //#define UCPEN (0x8000) /* Parity enable */
\r
12352 /* UCA1CTLW0_SPI[UCSWRST] Bits */
\r
12353 //#define UCSWRST_OFS ( 0) /* UCSWRST Offset */
\r
12354 //#define UCSWRST (0x0001) /* Software reset enable */
\r
12355 /* UCA1CTLW0_SPI[UCSTEM] Bits */
\r
12356 //#define UCSTEM_OFS ( 1) /* UCSTEM Offset */
\r
12357 //#define UCSTEM (0x0002) /* STE mode select in master mode. */
\r
12358 /* UCA1CTLW0_SPI[UCSSEL] Bits */
\r
12359 //#define UCSSEL_OFS ( 6) /* UCSSEL Offset */
\r
12360 //#define UCSSEL_M (0x00c0) /* eUSCI_A clock source select */
\r
12361 //#define UCSSEL0 (0x0040) /* eUSCI_A clock source select */
\r
12362 //#define UCSSEL1 (0x0080) /* eUSCI_A clock source select */
\r
12363 //#define UCSSEL_1 (0x0040) /* ACLK */
\r
12364 //#define UCSSEL_2 (0x0080) /* SMCLK */
\r
12365 //#define UCSSEL_0 (0x0000) /* Reserved */
\r
12366 //#define UCSSEL__ACLK (0x0040) /* ACLK */
\r
12367 //#define UCSSEL__SMCLK (0x0080) /* SMCLK */
\r
12368 /* UCA1CTLW0_SPI[UCSYNC] Bits */
\r
12369 //#define UCSYNC_OFS ( 8) /* UCSYNC Offset */
\r
12370 //#define UCSYNC (0x0100) /* Synchronous mode enable */
\r
12371 /* UCA1CTLW0_SPI[UCMODE] Bits */
\r
12372 //#define UCMODE_OFS ( 9) /* UCMODE Offset */
\r
12373 //#define UCMODE_M (0x0600) /* eUSCI mode */
\r
12374 //#define UCMODE0 (0x0200) /* eUSCI mode */
\r
12375 //#define UCMODE1 (0x0400) /* eUSCI mode */
\r
12376 //#define UCMODE_0 (0x0000) /* 3-pin SPI */
\r
12377 //#define UCMODE_1 (0x0200) /* 4-pin SPI with UCxSTE active high: Slave enabled when UCxSTE = 1 */
\r
12378 //#define UCMODE_2 (0x0400) /* 4-pin SPI with UCxSTE active low: Slave enabled when UCxSTE = 0 */
\r
12379 /* UCA1CTLW0_SPI[UCMST] Bits */
\r
12380 //#define UCMST_OFS (11) /* UCMST Offset */
\r
12381 //#define UCMST (0x0800) /* Master mode select */
\r
12382 /* UCA1CTLW0_SPI[UC7BIT] Bits */
\r
12383 //#define UC7BIT_OFS (12) /* UC7BIT Offset */
\r
12384 //#define UC7BIT (0x1000) /* Character length */
\r
12385 /* UCA1CTLW0_SPI[UCMSB] Bits */
\r
12386 //#define UCMSB_OFS (13) /* UCMSB Offset */
\r
12387 //#define UCMSB (0x2000) /* MSB first select */
\r
12388 /* UCA1CTLW0_SPI[UCCKPL] Bits */
\r
12389 //#define UCCKPL_OFS (14) /* UCCKPL Offset */
\r
12390 //#define UCCKPL (0x4000) /* Clock polarity select */
\r
12391 /* UCA1CTLW0_SPI[UCCKPH] Bits */
\r
12392 //#define UCCKPH_OFS (15) /* UCCKPH Offset */
\r
12393 //#define UCCKPH (0x8000) /* Clock phase select */
\r
12394 /* UCA1CTLW1[UCGLIT] Bits */
\r
12395 //#define UCGLIT_OFS ( 0) /* UCGLIT Offset */
\r
12396 //#define UCGLIT_M (0x0003) /* Deglitch time */
\r
12397 //#define UCGLIT0 (0x0001) /* Deglitch time */
\r
12398 //#define UCGLIT1 (0x0002) /* Deglitch time */
\r
12399 //#define UCGLIT_0 (0x0000) /* Approximately 2 ns (equivalent of 1 delay element) */
\r
12400 //#define UCGLIT_1 (0x0001) /* Approximately 50 ns */
\r
12401 //#define UCGLIT_2 (0x0002) /* Approximately 100 ns */
\r
12402 //#define UCGLIT_3 (0x0003) /* Approximately 200 ns */
\r
12403 /* UCA1MCTLW[UCOS16] Bits */
\r
12404 //#define UCOS16_OFS ( 0) /* UCOS16 Offset */
\r
12405 //#define UCOS16 (0x0001) /* Oversampling mode enabled */
\r
12406 /* UCA1MCTLW[UCBRF] Bits */
\r
12407 //#define UCBRF_OFS ( 4) /* UCBRF Offset */
\r
12408 //#define UCBRF_M (0x00f0) /* First modulation stage select */
\r
12409 /* UCA1MCTLW[UCBRS] Bits */
\r
12410 //#define UCBRS_OFS ( 8) /* UCBRS Offset */
\r
12411 //#define UCBRS_M (0xff00) /* Second modulation stage select */
\r
12412 /* UCA1STATW[UCBUSY] Bits */
\r
12413 //#define UCBUSY_OFS ( 0) /* UCBUSY Offset */
\r
12414 //#define UCBUSY (0x0001) /* eUSCI_A busy */
\r
12415 /* UCA1STATW[UCADDR_UCIDLE] Bits */
\r
12416 //#define UCADDR_UCIDLE_OFS ( 1) /* UCADDR_UCIDLE Offset */
\r
12417 //#define UCADDR_UCIDLE (0x0002) /* Address received / Idle line detected */
\r
12418 /* UCA1STATW[UCRXERR] Bits */
\r
12419 //#define UCRXERR_OFS ( 2) /* UCRXERR Offset */
\r
12420 //#define UCRXERR (0x0004) /* Receive error flag */
\r
12421 /* UCA1STATW[UCBRK] Bits */
\r
12422 //#define UCBRK_OFS ( 3) /* UCBRK Offset */
\r
12423 //#define UCBRK (0x0008) /* Break detect flag */
\r
12424 /* UCA1STATW[UCPE] Bits */
\r
12425 //#define UCPE_OFS ( 4) /* UCPE Offset */
\r
12426 //#define UCPE (0x0010) /* */
\r
12427 /* UCA1STATW[UCOE] Bits */
\r
12428 //#define UCOE_OFS ( 5) /* UCOE Offset */
\r
12429 //#define UCOE (0x0020) /* Overrun error flag */
\r
12430 /* UCA1STATW[UCFE] Bits */
\r
12431 //#define UCFE_OFS ( 6) /* UCFE Offset */
\r
12432 //#define UCFE (0x0040) /* Framing error flag */
\r
12433 /* UCA1STATW[UCLISTEN] Bits */
\r
12434 //#define UCLISTEN_OFS ( 7) /* UCLISTEN Offset */
\r
12435 //#define UCLISTEN (0x0080) /* Listen enable */
\r
12436 /* UCA1STATW_SPI[UCBUSY] Bits */
\r
12437 //#define UCBUSY_OFS ( 0) /* UCBUSY Offset */
\r
12438 //#define UCBUSY (0x0001) /* eUSCI_A busy */
\r
12439 /* UCA1STATW_SPI[UCOE] Bits */
\r
12440 //#define UCOE_OFS ( 5) /* UCOE Offset */
\r
12441 //#define UCOE (0x0020) /* Overrun error flag */
\r
12442 /* UCA1STATW_SPI[UCFE] Bits */
\r
12443 //#define UCFE_OFS ( 6) /* UCFE Offset */
\r
12444 //#define UCFE (0x0040) /* Framing error flag */
\r
12445 /* UCA1STATW_SPI[UCLISTEN] Bits */
\r
12446 //#define UCLISTEN_OFS ( 7) /* UCLISTEN Offset */
\r
12447 //#define UCLISTEN (0x0080) /* Listen enable */
\r
12448 /* UCA1RXBUF[UCRXBUF] Bits */
\r
12449 //#define UCRXBUF_OFS ( 0) /* UCRXBUF Offset */
\r
12450 //#define UCRXBUF_M (0x00ff) /* Receive data buffer */
\r
12451 /* UCA1RXBUF_SPI[UCRXBUF] Bits */
\r
12452 //#define UCRXBUF_OFS ( 0) /* UCRXBUF Offset */
\r
12453 //#define UCRXBUF_M (0x00ff) /* Receive data buffer */
\r
12454 /* UCA1TXBUF[UCTXBUF] Bits */
\r
12455 //#define UCTXBUF_OFS ( 0) /* UCTXBUF Offset */
\r
12456 //#define UCTXBUF_M (0x00ff) /* Transmit data buffer */
\r
12457 /* UCA1TXBUF_SPI[UCTXBUF] Bits */
\r
12458 //#define UCTXBUF_OFS ( 0) /* UCTXBUF Offset */
\r
12459 //#define UCTXBUF_M (0x00ff) /* Transmit data buffer */
\r
12460 /* UCA1ABCTL[UCABDEN] Bits */
\r
12461 //#define UCABDEN_OFS ( 0) /* UCABDEN Offset */
\r
12462 //#define UCABDEN (0x0001) /* Automatic baud-rate detect enable */
\r
12463 /* UCA1ABCTL[UCBTOE] Bits */
\r
12464 //#define UCBTOE_OFS ( 2) /* UCBTOE Offset */
\r
12465 //#define UCBTOE (0x0004) /* Break time out error */
\r
12466 /* UCA1ABCTL[UCSTOE] Bits */
\r
12467 //#define UCSTOE_OFS ( 3) /* UCSTOE Offset */
\r
12468 //#define UCSTOE (0x0008) /* Synch field time out error */
\r
12469 /* UCA1ABCTL[UCDELIM] Bits */
\r
12470 //#define UCDELIM_OFS ( 4) /* UCDELIM Offset */
\r
12471 //#define UCDELIM_M (0x0030) /* Break/synch delimiter length */
\r
12472 //#define UCDELIM0 (0x0010) /* Break/synch delimiter length */
\r
12473 //#define UCDELIM1 (0x0020) /* Break/synch delimiter length */
\r
12474 //#define UCDELIM_0 (0x0000) /* 1 bit time */
\r
12475 //#define UCDELIM_1 (0x0010) /* 2 bit times */
\r
12476 //#define UCDELIM_2 (0x0020) /* 3 bit times */
\r
12477 //#define UCDELIM_3 (0x0030) /* 4 bit times */
\r
12478 /* UCA1IRCTL[UCIREN] Bits */
\r
12479 //#define UCIREN_OFS ( 0) /* UCIREN Offset */
\r
12480 //#define UCIREN (0x0001) /* IrDA encoder/decoder enable */
\r
12481 /* UCA1IRCTL[UCIRTXCLK] Bits */
\r
12482 //#define UCIRTXCLK_OFS ( 1) /* UCIRTXCLK Offset */
\r
12483 //#define UCIRTXCLK (0x0002) /* IrDA transmit pulse clock select */
\r
12484 /* UCA1IRCTL[UCIRTXPL] Bits */
\r
12485 //#define UCIRTXPL_OFS ( 2) /* UCIRTXPL Offset */
\r
12486 //#define UCIRTXPL_M (0x00fc) /* Transmit pulse length */
\r
12487 /* UCA1IRCTL[UCIRRXFE] Bits */
\r
12488 //#define UCIRRXFE_OFS ( 8) /* UCIRRXFE Offset */
\r
12489 //#define UCIRRXFE (0x0100) /* IrDA receive filter enabled */
\r
12490 /* UCA1IRCTL[UCIRRXPL] Bits */
\r
12491 //#define UCIRRXPL_OFS ( 9) /* UCIRRXPL Offset */
\r
12492 //#define UCIRRXPL (0x0200) /* IrDA receive input UCAxRXD polarity */
\r
12493 /* UCA1IRCTL[UCIRRXFL] Bits */
\r
12494 //#define UCIRRXFL_OFS (10) /* UCIRRXFL Offset */
\r
12495 //#define UCIRRXFL_M (0x3c00) /* Receive filter length */
\r
12496 /* UCA1IE[UCRXIE] Bits */
\r
12497 //#define UCRXIE_OFS ( 0) /* UCRXIE Offset */
\r
12498 //#define UCRXIE (0x0001) /* Receive interrupt enable */
\r
12499 /* UCA1IE[UCTXIE] Bits */
\r
12500 //#define UCTXIE_OFS ( 1) /* UCTXIE Offset */
\r
12501 //#define UCTXIE (0x0002) /* Transmit interrupt enable */
\r
12502 /* UCA1IE[UCSTTIE] Bits */
\r
12503 //#define UCSTTIE_OFS ( 2) /* UCSTTIE Offset */
\r
12504 //#define UCSTTIE (0x0004) /* Start bit interrupt enable */
\r
12505 /* UCA1IE[UCTXCPTIE] Bits */
\r
12506 //#define UCTXCPTIE_OFS ( 3) /* UCTXCPTIE Offset */
\r
12507 //#define UCTXCPTIE (0x0008) /* Transmit complete interrupt enable */
\r
12508 /* UCA1IE_SPI[UCRXIE] Bits */
\r
12509 //#define UCRXIE_OFS ( 0) /* UCRXIE Offset */
\r
12510 //#define UCRXIE (0x0001) /* Receive interrupt enable */
\r
12511 /* UCA1IE_SPI[UCTXIE] Bits */
\r
12512 //#define UCTXIE_OFS ( 1) /* UCTXIE Offset */
\r
12513 //#define UCTXIE (0x0002) /* Transmit interrupt enable */
\r
12514 /* UCA1IFG[UCRXIFG] Bits */
\r
12515 //#define UCRXIFG_OFS ( 0) /* UCRXIFG Offset */
\r
12516 //#define UCRXIFG (0x0001) /* Receive interrupt flag */
\r
12517 /* UCA1IFG[UCTXIFG] Bits */
\r
12518 //#define UCTXIFG_OFS ( 1) /* UCTXIFG Offset */
\r
12519 //#define UCTXIFG (0x0002) /* Transmit interrupt flag */
\r
12520 /* UCA1IFG[UCSTTIFG] Bits */
\r
12521 //#define UCSTTIFG_OFS ( 2) /* UCSTTIFG Offset */
\r
12522 //#define UCSTTIFG (0x0004) /* Start bit interrupt flag */
\r
12523 /* UCA1IFG[UCTXCPTIFG] Bits */
\r
12524 //#define UCTXCPTIFG_OFS ( 3) /* UCTXCPTIFG Offset */
\r
12525 //#define UCTXCPTIFG (0x0008) /* Transmit ready interrupt enable */
\r
12526 /* UCA1IFG_SPI[UCRXIFG] Bits */
\r
12527 //#define UCRXIFG_OFS ( 0) /* UCRXIFG Offset */
\r
12528 //#define UCRXIFG (0x0001) /* Receive interrupt flag */
\r
12529 /* UCA1IFG_SPI[UCTXIFG] Bits */
\r
12530 //#define UCTXIFG_OFS ( 1) /* UCTXIFG Offset */
\r
12531 //#define UCTXIFG (0x0002) /* Transmit interrupt flag */
\r
12534 //*****************************************************************************
\r
12536 //*****************************************************************************
\r
12537 /* UCA2CTLW0[UCSWRST] Bits */
\r
12538 //#define UCSWRST_OFS ( 0) /* UCSWRST Offset */
\r
12539 //#define UCSWRST (0x0001) /* Software reset enable */
\r
12540 /* UCA2CTLW0[UCTXBRK] Bits */
\r
12541 //#define UCTXBRK_OFS ( 1) /* UCTXBRK Offset */
\r
12542 //#define UCTXBRK (0x0002) /* Transmit break */
\r
12543 /* UCA2CTLW0[UCTXADDR] Bits */
\r
12544 //#define UCTXADDR_OFS ( 2) /* UCTXADDR Offset */
\r
12545 //#define UCTXADDR (0x0004) /* Transmit address */
\r
12546 /* UCA2CTLW0[UCDORM] Bits */
\r
12547 //#define UCDORM_OFS ( 3) /* UCDORM Offset */
\r
12548 //#define UCDORM (0x0008) /* Dormant */
\r
12549 /* UCA2CTLW0[UCBRKIE] Bits */
\r
12550 //#define UCBRKIE_OFS ( 4) /* UCBRKIE Offset */
\r
12551 //#define UCBRKIE (0x0010) /* Receive break character interrupt enable */
\r
12552 /* UCA2CTLW0[UCRXEIE] Bits */
\r
12553 //#define UCRXEIE_OFS ( 5) /* UCRXEIE Offset */
\r
12554 //#define UCRXEIE (0x0020) /* Receive erroneous-character interrupt enable */
\r
12555 /* UCA2CTLW0[UCSSEL] Bits */
\r
12556 //#define UCSSEL_OFS ( 6) /* UCSSEL Offset */
\r
12557 //#define UCSSEL_M (0x00c0) /* eUSCI_A clock source select */
\r
12558 //#define UCSSEL0 (0x0040) /* eUSCI_A clock source select */
\r
12559 //#define UCSSEL1 (0x0080) /* eUSCI_A clock source select */
\r
12560 //#define UCSSEL_0 (0x0000) /* UCLK */
\r
12561 //#define UCSSEL_1 (0x0040) /* ACLK */
\r
12562 //#define UCSSEL_2 (0x0080) /* SMCLK */
\r
12563 //#define UCSSEL__UCLK (0x0000) /* UCLK */
\r
12564 //#define UCSSEL__ACLK (0x0040) /* ACLK */
\r
12565 //#define UCSSEL__SMCLK (0x0080) /* SMCLK */
\r
12566 /* UCA2CTLW0[UCSYNC] Bits */
\r
12567 //#define UCSYNC_OFS ( 8) /* UCSYNC Offset */
\r
12568 //#define UCSYNC (0x0100) /* Synchronous mode enable */
\r
12569 /* UCA2CTLW0[UCMODE] Bits */
\r
12570 //#define UCMODE_OFS ( 9) /* UCMODE Offset */
\r
12571 //#define UCMODE_M (0x0600) /* eUSCI_A mode */
\r
12572 //#define UCMODE0 (0x0200) /* eUSCI_A mode */
\r
12573 //#define UCMODE1 (0x0400) /* eUSCI_A mode */
\r
12574 //#define UCMODE_0 (0x0000) /* UART mode */
\r
12575 //#define UCMODE_1 (0x0200) /* Idle-line multiprocessor mode */
\r
12576 //#define UCMODE_2 (0x0400) /* Address-bit multiprocessor mode */
\r
12577 //#define UCMODE_3 (0x0600) /* UART mode with automatic baud-rate detection */
\r
12578 /* UCA2CTLW0[UCSPB] Bits */
\r
12579 //#define UCSPB_OFS (11) /* UCSPB Offset */
\r
12580 //#define UCSPB (0x0800) /* Stop bit select */
\r
12581 /* UCA2CTLW0[UC7BIT] Bits */
\r
12582 //#define UC7BIT_OFS (12) /* UC7BIT Offset */
\r
12583 //#define UC7BIT (0x1000) /* Character length */
\r
12584 /* UCA2CTLW0[UCMSB] Bits */
\r
12585 //#define UCMSB_OFS (13) /* UCMSB Offset */
\r
12586 //#define UCMSB (0x2000) /* MSB first select */
\r
12587 /* UCA2CTLW0[UCPAR] Bits */
\r
12588 //#define UCPAR_OFS (14) /* UCPAR Offset */
\r
12589 //#define UCPAR (0x4000) /* Parity select */
\r
12590 /* UCA2CTLW0[UCPEN] Bits */
\r
12591 //#define UCPEN_OFS (15) /* UCPEN Offset */
\r
12592 //#define UCPEN (0x8000) /* Parity enable */
\r
12593 /* UCA2CTLW0_SPI[UCSWRST] Bits */
\r
12594 //#define UCSWRST_OFS ( 0) /* UCSWRST Offset */
\r
12595 //#define UCSWRST (0x0001) /* Software reset enable */
\r
12596 /* UCA2CTLW0_SPI[UCSTEM] Bits */
\r
12597 //#define UCSTEM_OFS ( 1) /* UCSTEM Offset */
\r
12598 //#define UCSTEM (0x0002) /* STE mode select in master mode. */
\r
12599 /* UCA2CTLW0_SPI[UCSSEL] Bits */
\r
12600 //#define UCSSEL_OFS ( 6) /* UCSSEL Offset */
\r
12601 //#define UCSSEL_M (0x00c0) /* eUSCI_A clock source select */
\r
12602 //#define UCSSEL0 (0x0040) /* eUSCI_A clock source select */
\r
12603 //#define UCSSEL1 (0x0080) /* eUSCI_A clock source select */
\r
12604 //#define UCSSEL_1 (0x0040) /* ACLK */
\r
12605 //#define UCSSEL_2 (0x0080) /* SMCLK */
\r
12606 //#define UCSSEL_0 (0x0000) /* Reserved */
\r
12607 //#define UCSSEL__ACLK (0x0040) /* ACLK */
\r
12608 //#define UCSSEL__SMCLK (0x0080) /* SMCLK */
\r
12609 /* UCA2CTLW0_SPI[UCSYNC] Bits */
\r
12610 //#define UCSYNC_OFS ( 8) /* UCSYNC Offset */
\r
12611 //#define UCSYNC (0x0100) /* Synchronous mode enable */
\r
12612 /* UCA2CTLW0_SPI[UCMODE] Bits */
\r
12613 //#define UCMODE_OFS ( 9) /* UCMODE Offset */
\r
12614 //#define UCMODE_M (0x0600) /* eUSCI mode */
\r
12615 //#define UCMODE0 (0x0200) /* eUSCI mode */
\r
12616 //#define UCMODE1 (0x0400) /* eUSCI mode */
\r
12617 //#define UCMODE_0 (0x0000) /* 3-pin SPI */
\r
12618 //#define UCMODE_1 (0x0200) /* 4-pin SPI with UCxSTE active high: Slave enabled when UCxSTE = 1 */
\r
12619 //#define UCMODE_2 (0x0400) /* 4-pin SPI with UCxSTE active low: Slave enabled when UCxSTE = 0 */
\r
12620 /* UCA2CTLW0_SPI[UCMST] Bits */
\r
12621 //#define UCMST_OFS (11) /* UCMST Offset */
\r
12622 //#define UCMST (0x0800) /* Master mode select */
\r
12623 /* UCA2CTLW0_SPI[UC7BIT] Bits */
\r
12624 //#define UC7BIT_OFS (12) /* UC7BIT Offset */
\r
12625 //#define UC7BIT (0x1000) /* Character length */
\r
12626 /* UCA2CTLW0_SPI[UCMSB] Bits */
\r
12627 //#define UCMSB_OFS (13) /* UCMSB Offset */
\r
12628 //#define UCMSB (0x2000) /* MSB first select */
\r
12629 /* UCA2CTLW0_SPI[UCCKPL] Bits */
\r
12630 //#define UCCKPL_OFS (14) /* UCCKPL Offset */
\r
12631 //#define UCCKPL (0x4000) /* Clock polarity select */
\r
12632 /* UCA2CTLW0_SPI[UCCKPH] Bits */
\r
12633 //#define UCCKPH_OFS (15) /* UCCKPH Offset */
\r
12634 //#define UCCKPH (0x8000) /* Clock phase select */
\r
12635 /* UCA2CTLW1[UCGLIT] Bits */
\r
12636 //#define UCGLIT_OFS ( 0) /* UCGLIT Offset */
\r
12637 //#define UCGLIT_M (0x0003) /* Deglitch time */
\r
12638 //#define UCGLIT0 (0x0001) /* Deglitch time */
\r
12639 //#define UCGLIT1 (0x0002) /* Deglitch time */
\r
12640 //#define UCGLIT_0 (0x0000) /* Approximately 2 ns (equivalent of 1 delay element) */
\r
12641 //#define UCGLIT_1 (0x0001) /* Approximately 50 ns */
\r
12642 //#define UCGLIT_2 (0x0002) /* Approximately 100 ns */
\r
12643 //#define UCGLIT_3 (0x0003) /* Approximately 200 ns */
\r
12644 /* UCA2MCTLW[UCOS16] Bits */
\r
12645 //#define UCOS16_OFS ( 0) /* UCOS16 Offset */
\r
12646 //#define UCOS16 (0x0001) /* Oversampling mode enabled */
\r
12647 /* UCA2MCTLW[UCBRF] Bits */
\r
12648 //#define UCBRF_OFS ( 4) /* UCBRF Offset */
\r
12649 //#define UCBRF_M (0x00f0) /* First modulation stage select */
\r
12650 /* UCA2MCTLW[UCBRS] Bits */
\r
12651 //#define UCBRS_OFS ( 8) /* UCBRS Offset */
\r
12652 //#define UCBRS_M (0xff00) /* Second modulation stage select */
\r
12653 /* UCA2STATW[UCBUSY] Bits */
\r
12654 //#define UCBUSY_OFS ( 0) /* UCBUSY Offset */
\r
12655 //#define UCBUSY (0x0001) /* eUSCI_A busy */
\r
12656 /* UCA2STATW[UCADDR_UCIDLE] Bits */
\r
12657 //#define UCADDR_UCIDLE_OFS ( 1) /* UCADDR_UCIDLE Offset */
\r
12658 //#define UCADDR_UCIDLE (0x0002) /* Address received / Idle line detected */
\r
12659 /* UCA2STATW[UCRXERR] Bits */
\r
12660 //#define UCRXERR_OFS ( 2) /* UCRXERR Offset */
\r
12661 //#define UCRXERR (0x0004) /* Receive error flag */
\r
12662 /* UCA2STATW[UCBRK] Bits */
\r
12663 //#define UCBRK_OFS ( 3) /* UCBRK Offset */
\r
12664 //#define UCBRK (0x0008) /* Break detect flag */
\r
12665 /* UCA2STATW[UCPE] Bits */
\r
12666 //#define UCPE_OFS ( 4) /* UCPE Offset */
\r
12667 //#define UCPE (0x0010) /* */
\r
12668 /* UCA2STATW[UCOE] Bits */
\r
12669 //#define UCOE_OFS ( 5) /* UCOE Offset */
\r
12670 //#define UCOE (0x0020) /* Overrun error flag */
\r
12671 /* UCA2STATW[UCFE] Bits */
\r
12672 //#define UCFE_OFS ( 6) /* UCFE Offset */
\r
12673 //#define UCFE (0x0040) /* Framing error flag */
\r
12674 /* UCA2STATW[UCLISTEN] Bits */
\r
12675 //#define UCLISTEN_OFS ( 7) /* UCLISTEN Offset */
\r
12676 //#define UCLISTEN (0x0080) /* Listen enable */
\r
12677 /* UCA2STATW_SPI[UCBUSY] Bits */
\r
12678 //#define UCBUSY_OFS ( 0) /* UCBUSY Offset */
\r
12679 //#define UCBUSY (0x0001) /* eUSCI_A busy */
\r
12680 /* UCA2STATW_SPI[UCOE] Bits */
\r
12681 //#define UCOE_OFS ( 5) /* UCOE Offset */
\r
12682 //#define UCOE (0x0020) /* Overrun error flag */
\r
12683 /* UCA2STATW_SPI[UCFE] Bits */
\r
12684 //#define UCFE_OFS ( 6) /* UCFE Offset */
\r
12685 //#define UCFE (0x0040) /* Framing error flag */
\r
12686 /* UCA2STATW_SPI[UCLISTEN] Bits */
\r
12687 //#define UCLISTEN_OFS ( 7) /* UCLISTEN Offset */
\r
12688 //#define UCLISTEN (0x0080) /* Listen enable */
\r
12689 /* UCA2RXBUF[UCRXBUF] Bits */
\r
12690 //#define UCRXBUF_OFS ( 0) /* UCRXBUF Offset */
\r
12691 //#define UCRXBUF_M (0x00ff) /* Receive data buffer */
\r
12692 /* UCA2RXBUF_SPI[UCRXBUF] Bits */
\r
12693 //#define UCRXBUF_OFS ( 0) /* UCRXBUF Offset */
\r
12694 //#define UCRXBUF_M (0x00ff) /* Receive data buffer */
\r
12695 /* UCA2TXBUF[UCTXBUF] Bits */
\r
12696 //#define UCTXBUF_OFS ( 0) /* UCTXBUF Offset */
\r
12697 //#define UCTXBUF_M (0x00ff) /* Transmit data buffer */
\r
12698 /* UCA2TXBUF_SPI[UCTXBUF] Bits */
\r
12699 //#define UCTXBUF_OFS ( 0) /* UCTXBUF Offset */
\r
12700 //#define UCTXBUF_M (0x00ff) /* Transmit data buffer */
\r
12701 /* UCA2ABCTL[UCABDEN] Bits */
\r
12702 //#define UCABDEN_OFS ( 0) /* UCABDEN Offset */
\r
12703 //#define UCABDEN (0x0001) /* Automatic baud-rate detect enable */
\r
12704 /* UCA2ABCTL[UCBTOE] Bits */
\r
12705 //#define UCBTOE_OFS ( 2) /* UCBTOE Offset */
\r
12706 //#define UCBTOE (0x0004) /* Break time out error */
\r
12707 /* UCA2ABCTL[UCSTOE] Bits */
\r
12708 //#define UCSTOE_OFS ( 3) /* UCSTOE Offset */
\r
12709 //#define UCSTOE (0x0008) /* Synch field time out error */
\r
12710 /* UCA2ABCTL[UCDELIM] Bits */
\r
12711 //#define UCDELIM_OFS ( 4) /* UCDELIM Offset */
\r
12712 //#define UCDELIM_M (0x0030) /* Break/synch delimiter length */
\r
12713 //#define UCDELIM0 (0x0010) /* Break/synch delimiter length */
\r
12714 //#define UCDELIM1 (0x0020) /* Break/synch delimiter length */
\r
12715 //#define UCDELIM_0 (0x0000) /* 1 bit time */
\r
12716 //#define UCDELIM_1 (0x0010) /* 2 bit times */
\r
12717 //#define UCDELIM_2 (0x0020) /* 3 bit times */
\r
12718 //#define UCDELIM_3 (0x0030) /* 4 bit times */
\r
12719 /* UCA2IRCTL[UCIREN] Bits */
\r
12720 //#define UCIREN_OFS ( 0) /* UCIREN Offset */
\r
12721 //#define UCIREN (0x0001) /* IrDA encoder/decoder enable */
\r
12722 /* UCA2IRCTL[UCIRTXCLK] Bits */
\r
12723 //#define UCIRTXCLK_OFS ( 1) /* UCIRTXCLK Offset */
\r
12724 //#define UCIRTXCLK (0x0002) /* IrDA transmit pulse clock select */
\r
12725 /* UCA2IRCTL[UCIRTXPL] Bits */
\r
12726 //#define UCIRTXPL_OFS ( 2) /* UCIRTXPL Offset */
\r
12727 //#define UCIRTXPL_M (0x00fc) /* Transmit pulse length */
\r
12728 /* UCA2IRCTL[UCIRRXFE] Bits */
\r
12729 //#define UCIRRXFE_OFS ( 8) /* UCIRRXFE Offset */
\r
12730 //#define UCIRRXFE (0x0100) /* IrDA receive filter enabled */
\r
12731 /* UCA2IRCTL[UCIRRXPL] Bits */
\r
12732 //#define UCIRRXPL_OFS ( 9) /* UCIRRXPL Offset */
\r
12733 //#define UCIRRXPL (0x0200) /* IrDA receive input UCAxRXD polarity */
\r
12734 /* UCA2IRCTL[UCIRRXFL] Bits */
\r
12735 //#define UCIRRXFL_OFS (10) /* UCIRRXFL Offset */
\r
12736 //#define UCIRRXFL_M (0x3c00) /* Receive filter length */
\r
12737 /* UCA2IE[UCRXIE] Bits */
\r
12738 //#define UCRXIE_OFS ( 0) /* UCRXIE Offset */
\r
12739 //#define UCRXIE (0x0001) /* Receive interrupt enable */
\r
12740 /* UCA2IE[UCTXIE] Bits */
\r
12741 //#define UCTXIE_OFS ( 1) /* UCTXIE Offset */
\r
12742 //#define UCTXIE (0x0002) /* Transmit interrupt enable */
\r
12743 /* UCA2IE[UCSTTIE] Bits */
\r
12744 //#define UCSTTIE_OFS ( 2) /* UCSTTIE Offset */
\r
12745 //#define UCSTTIE (0x0004) /* Start bit interrupt enable */
\r
12746 /* UCA2IE[UCTXCPTIE] Bits */
\r
12747 //#define UCTXCPTIE_OFS ( 3) /* UCTXCPTIE Offset */
\r
12748 //#define UCTXCPTIE (0x0008) /* Transmit complete interrupt enable */
\r
12749 /* UCA2IE_SPI[UCRXIE] Bits */
\r
12750 //#define UCRXIE_OFS ( 0) /* UCRXIE Offset */
\r
12751 //#define UCRXIE (0x0001) /* Receive interrupt enable */
\r
12752 /* UCA2IE_SPI[UCTXIE] Bits */
\r
12753 //#define UCTXIE_OFS ( 1) /* UCTXIE Offset */
\r
12754 //#define UCTXIE (0x0002) /* Transmit interrupt enable */
\r
12755 /* UCA2IFG[UCRXIFG] Bits */
\r
12756 //#define UCRXIFG_OFS ( 0) /* UCRXIFG Offset */
\r
12757 //#define UCRXIFG (0x0001) /* Receive interrupt flag */
\r
12758 /* UCA2IFG[UCTXIFG] Bits */
\r
12759 //#define UCTXIFG_OFS ( 1) /* UCTXIFG Offset */
\r
12760 //#define UCTXIFG (0x0002) /* Transmit interrupt flag */
\r
12761 /* UCA2IFG[UCSTTIFG] Bits */
\r
12762 //#define UCSTTIFG_OFS ( 2) /* UCSTTIFG Offset */
\r
12763 //#define UCSTTIFG (0x0004) /* Start bit interrupt flag */
\r
12764 /* UCA2IFG[UCTXCPTIFG] Bits */
\r
12765 //#define UCTXCPTIFG_OFS ( 3) /* UCTXCPTIFG Offset */
\r
12766 //#define UCTXCPTIFG (0x0008) /* Transmit ready interrupt enable */
\r
12767 /* UCA2IFG_SPI[UCRXIFG] Bits */
\r
12768 //#define UCRXIFG_OFS ( 0) /* UCRXIFG Offset */
\r
12769 //#define UCRXIFG (0x0001) /* Receive interrupt flag */
\r
12770 /* UCA2IFG_SPI[UCTXIFG] Bits */
\r
12771 //#define UCTXIFG_OFS ( 1) /* UCTXIFG Offset */
\r
12772 //#define UCTXIFG (0x0002) /* Transmit interrupt flag */
\r
12775 //*****************************************************************************
\r
12777 //*****************************************************************************
\r
12778 /* UCA3CTLW0[UCSWRST] Bits */
\r
12779 //#define UCSWRST_OFS ( 0) /* UCSWRST Offset */
\r
12780 //#define UCSWRST (0x0001) /* Software reset enable */
\r
12781 /* UCA3CTLW0[UCTXBRK] Bits */
\r
12782 //#define UCTXBRK_OFS ( 1) /* UCTXBRK Offset */
\r
12783 //#define UCTXBRK (0x0002) /* Transmit break */
\r
12784 /* UCA3CTLW0[UCTXADDR] Bits */
\r
12785 //#define UCTXADDR_OFS ( 2) /* UCTXADDR Offset */
\r
12786 //#define UCTXADDR (0x0004) /* Transmit address */
\r
12787 /* UCA3CTLW0[UCDORM] Bits */
\r
12788 //#define UCDORM_OFS ( 3) /* UCDORM Offset */
\r
12789 //#define UCDORM (0x0008) /* Dormant */
\r
12790 /* UCA3CTLW0[UCBRKIE] Bits */
\r
12791 //#define UCBRKIE_OFS ( 4) /* UCBRKIE Offset */
\r
12792 //#define UCBRKIE (0x0010) /* Receive break character interrupt enable */
\r
12793 /* UCA3CTLW0[UCRXEIE] Bits */
\r
12794 //#define UCRXEIE_OFS ( 5) /* UCRXEIE Offset */
\r
12795 //#define UCRXEIE (0x0020) /* Receive erroneous-character interrupt enable */
\r
12796 /* UCA3CTLW0[UCSSEL] Bits */
\r
12797 //#define UCSSEL_OFS ( 6) /* UCSSEL Offset */
\r
12798 //#define UCSSEL_M (0x00c0) /* eUSCI_A clock source select */
\r
12799 //#define UCSSEL0 (0x0040) /* eUSCI_A clock source select */
\r
12800 //#define UCSSEL1 (0x0080) /* eUSCI_A clock source select */
\r
12801 //#define UCSSEL_0 (0x0000) /* UCLK */
\r
12802 //#define UCSSEL_1 (0x0040) /* ACLK */
\r
12803 //#define UCSSEL_2 (0x0080) /* SMCLK */
\r
12804 //#define UCSSEL__UCLK (0x0000) /* UCLK */
\r
12805 //#define UCSSEL__ACLK (0x0040) /* ACLK */
\r
12806 //#define UCSSEL__SMCLK (0x0080) /* SMCLK */
\r
12807 /* UCA3CTLW0[UCSYNC] Bits */
\r
12808 //#define UCSYNC_OFS ( 8) /* UCSYNC Offset */
\r
12809 //#define UCSYNC (0x0100) /* Synchronous mode enable */
\r
12810 /* UCA3CTLW0[UCMODE] Bits */
\r
12811 //#define UCMODE_OFS ( 9) /* UCMODE Offset */
\r
12812 //#define UCMODE_M (0x0600) /* eUSCI_A mode */
\r
12813 //#define UCMODE0 (0x0200) /* eUSCI_A mode */
\r
12814 //#define UCMODE1 (0x0400) /* eUSCI_A mode */
\r
12815 //#define UCMODE_0 (0x0000) /* UART mode */
\r
12816 //#define UCMODE_1 (0x0200) /* Idle-line multiprocessor mode */
\r
12817 //#define UCMODE_2 (0x0400) /* Address-bit multiprocessor mode */
\r
12818 //#define UCMODE_3 (0x0600) /* UART mode with automatic baud-rate detection */
\r
12819 /* UCA3CTLW0[UCSPB] Bits */
\r
12820 //#define UCSPB_OFS (11) /* UCSPB Offset */
\r
12821 //#define UCSPB (0x0800) /* Stop bit select */
\r
12822 /* UCA3CTLW0[UC7BIT] Bits */
\r
12823 //#define UC7BIT_OFS (12) /* UC7BIT Offset */
\r
12824 //#define UC7BIT (0x1000) /* Character length */
\r
12825 /* UCA3CTLW0[UCMSB] Bits */
\r
12826 //#define UCMSB_OFS (13) /* UCMSB Offset */
\r
12827 //#define UCMSB (0x2000) /* MSB first select */
\r
12828 /* UCA3CTLW0[UCPAR] Bits */
\r
12829 //#define UCPAR_OFS (14) /* UCPAR Offset */
\r
12830 //#define UCPAR (0x4000) /* Parity select */
\r
12831 /* UCA3CTLW0[UCPEN] Bits */
\r
12832 //#define UCPEN_OFS (15) /* UCPEN Offset */
\r
12833 //#define UCPEN (0x8000) /* Parity enable */
\r
12834 /* UCA3CTLW0_SPI[UCSWRST] Bits */
\r
12835 //#define UCSWRST_OFS ( 0) /* UCSWRST Offset */
\r
12836 //#define UCSWRST (0x0001) /* Software reset enable */
\r
12837 /* UCA3CTLW0_SPI[UCSTEM] Bits */
\r
12838 //#define UCSTEM_OFS ( 1) /* UCSTEM Offset */
\r
12839 //#define UCSTEM (0x0002) /* STE mode select in master mode. */
\r
12840 /* UCA3CTLW0_SPI[UCSSEL] Bits */
\r
12841 //#define UCSSEL_OFS ( 6) /* UCSSEL Offset */
\r
12842 //#define UCSSEL_M (0x00c0) /* eUSCI_A clock source select */
\r
12843 //#define UCSSEL0 (0x0040) /* eUSCI_A clock source select */
\r
12844 //#define UCSSEL1 (0x0080) /* eUSCI_A clock source select */
\r
12845 //#define UCSSEL_1 (0x0040) /* ACLK */
\r
12846 //#define UCSSEL_2 (0x0080) /* SMCLK */
\r
12847 //#define UCSSEL_0 (0x0000) /* Reserved */
\r
12848 //#define UCSSEL__ACLK (0x0040) /* ACLK */
\r
12849 //#define UCSSEL__SMCLK (0x0080) /* SMCLK */
\r
12850 /* UCA3CTLW0_SPI[UCSYNC] Bits */
\r
12851 //#define UCSYNC_OFS ( 8) /* UCSYNC Offset */
\r
12852 //#define UCSYNC (0x0100) /* Synchronous mode enable */
\r
12853 /* UCA3CTLW0_SPI[UCMODE] Bits */
\r
12854 //#define UCMODE_OFS ( 9) /* UCMODE Offset */
\r
12855 //#define UCMODE_M (0x0600) /* eUSCI mode */
\r
12856 //#define UCMODE0 (0x0200) /* eUSCI mode */
\r
12857 //#define UCMODE1 (0x0400) /* eUSCI mode */
\r
12858 //#define UCMODE_0 (0x0000) /* 3-pin SPI */
\r
12859 //#define UCMODE_1 (0x0200) /* 4-pin SPI with UCxSTE active high: Slave enabled when UCxSTE = 1 */
\r
12860 //#define UCMODE_2 (0x0400) /* 4-pin SPI with UCxSTE active low: Slave enabled when UCxSTE = 0 */
\r
12861 /* UCA3CTLW0_SPI[UCMST] Bits */
\r
12862 //#define UCMST_OFS (11) /* UCMST Offset */
\r
12863 //#define UCMST (0x0800) /* Master mode select */
\r
12864 /* UCA3CTLW0_SPI[UC7BIT] Bits */
\r
12865 //#define UC7BIT_OFS (12) /* UC7BIT Offset */
\r
12866 //#define UC7BIT (0x1000) /* Character length */
\r
12867 /* UCA3CTLW0_SPI[UCMSB] Bits */
\r
12868 //#define UCMSB_OFS (13) /* UCMSB Offset */
\r
12869 //#define UCMSB (0x2000) /* MSB first select */
\r
12870 /* UCA3CTLW0_SPI[UCCKPL] Bits */
\r
12871 //#define UCCKPL_OFS (14) /* UCCKPL Offset */
\r
12872 //#define UCCKPL (0x4000) /* Clock polarity select */
\r
12873 /* UCA3CTLW0_SPI[UCCKPH] Bits */
\r
12874 //#define UCCKPH_OFS (15) /* UCCKPH Offset */
\r
12875 //#define UCCKPH (0x8000) /* Clock phase select */
\r
12876 /* UCA3CTLW1[UCGLIT] Bits */
\r
12877 //#define UCGLIT_OFS ( 0) /* UCGLIT Offset */
\r
12878 //#define UCGLIT_M (0x0003) /* Deglitch time */
\r
12879 //#define UCGLIT0 (0x0001) /* Deglitch time */
\r
12880 //#define UCGLIT1 (0x0002) /* Deglitch time */
\r
12881 //#define UCGLIT_0 (0x0000) /* Approximately 2 ns (equivalent of 1 delay element) */
\r
12882 //#define UCGLIT_1 (0x0001) /* Approximately 50 ns */
\r
12883 //#define UCGLIT_2 (0x0002) /* Approximately 100 ns */
\r
12884 //#define UCGLIT_3 (0x0003) /* Approximately 200 ns */
\r
12885 /* UCA3MCTLW[UCOS16] Bits */
\r
12886 //#define UCOS16_OFS ( 0) /* UCOS16 Offset */
\r
12887 //#define UCOS16 (0x0001) /* Oversampling mode enabled */
\r
12888 /* UCA3MCTLW[UCBRF] Bits */
\r
12889 //#define UCBRF_OFS ( 4) /* UCBRF Offset */
\r
12890 //#define UCBRF_M (0x00f0) /* First modulation stage select */
\r
12891 /* UCA3MCTLW[UCBRS] Bits */
\r
12892 //#define UCBRS_OFS ( 8) /* UCBRS Offset */
\r
12893 //#define UCBRS_M (0xff00) /* Second modulation stage select */
\r
12894 /* UCA3STATW[UCBUSY] Bits */
\r
12895 //#define UCBUSY_OFS ( 0) /* UCBUSY Offset */
\r
12896 //#define UCBUSY (0x0001) /* eUSCI_A busy */
\r
12897 /* UCA3STATW[UCADDR_UCIDLE] Bits */
\r
12898 //#define UCADDR_UCIDLE_OFS ( 1) /* UCADDR_UCIDLE Offset */
\r
12899 //#define UCADDR_UCIDLE (0x0002) /* Address received / Idle line detected */
\r
12900 /* UCA3STATW[UCRXERR] Bits */
\r
12901 //#define UCRXERR_OFS ( 2) /* UCRXERR Offset */
\r
12902 //#define UCRXERR (0x0004) /* Receive error flag */
\r
12903 /* UCA3STATW[UCBRK] Bits */
\r
12904 //#define UCBRK_OFS ( 3) /* UCBRK Offset */
\r
12905 //#define UCBRK (0x0008) /* Break detect flag */
\r
12906 /* UCA3STATW[UCPE] Bits */
\r
12907 //#define UCPE_OFS ( 4) /* UCPE Offset */
\r
12908 //#define UCPE (0x0010) /* */
\r
12909 /* UCA3STATW[UCOE] Bits */
\r
12910 //#define UCOE_OFS ( 5) /* UCOE Offset */
\r
12911 //#define UCOE (0x0020) /* Overrun error flag */
\r
12912 /* UCA3STATW[UCFE] Bits */
\r
12913 //#define UCFE_OFS ( 6) /* UCFE Offset */
\r
12914 //#define UCFE (0x0040) /* Framing error flag */
\r
12915 /* UCA3STATW[UCLISTEN] Bits */
\r
12916 //#define UCLISTEN_OFS ( 7) /* UCLISTEN Offset */
\r
12917 //#define UCLISTEN (0x0080) /* Listen enable */
\r
12918 /* UCA3STATW_SPI[UCBUSY] Bits */
\r
12919 //#define UCBUSY_OFS ( 0) /* UCBUSY Offset */
\r
12920 //#define UCBUSY (0x0001) /* eUSCI_A busy */
\r
12921 /* UCA3STATW_SPI[UCOE] Bits */
\r
12922 //#define UCOE_OFS ( 5) /* UCOE Offset */
\r
12923 //#define UCOE (0x0020) /* Overrun error flag */
\r
12924 /* UCA3STATW_SPI[UCFE] Bits */
\r
12925 //#define UCFE_OFS ( 6) /* UCFE Offset */
\r
12926 //#define UCFE (0x0040) /* Framing error flag */
\r
12927 /* UCA3STATW_SPI[UCLISTEN] Bits */
\r
12928 //#define UCLISTEN_OFS ( 7) /* UCLISTEN Offset */
\r
12929 //#define UCLISTEN (0x0080) /* Listen enable */
\r
12930 /* UCA3RXBUF[UCRXBUF] Bits */
\r
12931 //#define UCRXBUF_OFS ( 0) /* UCRXBUF Offset */
\r
12932 //#define UCRXBUF_M (0x00ff) /* Receive data buffer */
\r
12933 /* UCA3RXBUF_SPI[UCRXBUF] Bits */
\r
12934 //#define UCRXBUF_OFS ( 0) /* UCRXBUF Offset */
\r
12935 //#define UCRXBUF_M (0x00ff) /* Receive data buffer */
\r
12936 /* UCA3TXBUF[UCTXBUF] Bits */
\r
12937 //#define UCTXBUF_OFS ( 0) /* UCTXBUF Offset */
\r
12938 //#define UCTXBUF_M (0x00ff) /* Transmit data buffer */
\r
12939 /* UCA3TXBUF_SPI[UCTXBUF] Bits */
\r
12940 //#define UCTXBUF_OFS ( 0) /* UCTXBUF Offset */
\r
12941 //#define UCTXBUF_M (0x00ff) /* Transmit data buffer */
\r
12942 /* UCA3ABCTL[UCABDEN] Bits */
\r
12943 //#define UCABDEN_OFS ( 0) /* UCABDEN Offset */
\r
12944 //#define UCABDEN (0x0001) /* Automatic baud-rate detect enable */
\r
12945 /* UCA3ABCTL[UCBTOE] Bits */
\r
12946 //#define UCBTOE_OFS ( 2) /* UCBTOE Offset */
\r
12947 //#define UCBTOE (0x0004) /* Break time out error */
\r
12948 /* UCA3ABCTL[UCSTOE] Bits */
\r
12949 //#define UCSTOE_OFS ( 3) /* UCSTOE Offset */
\r
12950 //#define UCSTOE (0x0008) /* Synch field time out error */
\r
12951 /* UCA3ABCTL[UCDELIM] Bits */
\r
12952 //#define UCDELIM_OFS ( 4) /* UCDELIM Offset */
\r
12953 //#define UCDELIM_M (0x0030) /* Break/synch delimiter length */
\r
12954 //#define UCDELIM0 (0x0010) /* Break/synch delimiter length */
\r
12955 //#define UCDELIM1 (0x0020) /* Break/synch delimiter length */
\r
12956 //#define UCDELIM_0 (0x0000) /* 1 bit time */
\r
12957 //#define UCDELIM_1 (0x0010) /* 2 bit times */
\r
12958 //#define UCDELIM_2 (0x0020) /* 3 bit times */
\r
12959 //#define UCDELIM_3 (0x0030) /* 4 bit times */
\r
12960 /* UCA3IRCTL[UCIREN] Bits */
\r
12961 //#define UCIREN_OFS ( 0) /* UCIREN Offset */
\r
12962 //#define UCIREN (0x0001) /* IrDA encoder/decoder enable */
\r
12963 /* UCA3IRCTL[UCIRTXCLK] Bits */
\r
12964 //#define UCIRTXCLK_OFS ( 1) /* UCIRTXCLK Offset */
\r
12965 //#define UCIRTXCLK (0x0002) /* IrDA transmit pulse clock select */
\r
12966 /* UCA3IRCTL[UCIRTXPL] Bits */
\r
12967 //#define UCIRTXPL_OFS ( 2) /* UCIRTXPL Offset */
\r
12968 //#define UCIRTXPL_M (0x00fc) /* Transmit pulse length */
\r
12969 /* UCA3IRCTL[UCIRRXFE] Bits */
\r
12970 //#define UCIRRXFE_OFS ( 8) /* UCIRRXFE Offset */
\r
12971 //#define UCIRRXFE (0x0100) /* IrDA receive filter enabled */
\r
12972 /* UCA3IRCTL[UCIRRXPL] Bits */
\r
12973 //#define UCIRRXPL_OFS ( 9) /* UCIRRXPL Offset */
\r
12974 //#define UCIRRXPL (0x0200) /* IrDA receive input UCAxRXD polarity */
\r
12975 /* UCA3IRCTL[UCIRRXFL] Bits */
\r
12976 //#define UCIRRXFL_OFS (10) /* UCIRRXFL Offset */
\r
12977 //#define UCIRRXFL_M (0x3c00) /* Receive filter length */
\r
12978 /* UCA3IE[UCRXIE] Bits */
\r
12979 //#define UCRXIE_OFS ( 0) /* UCRXIE Offset */
\r
12980 //#define UCRXIE (0x0001) /* Receive interrupt enable */
\r
12981 /* UCA3IE[UCTXIE] Bits */
\r
12982 //#define UCTXIE_OFS ( 1) /* UCTXIE Offset */
\r
12983 //#define UCTXIE (0x0002) /* Transmit interrupt enable */
\r
12984 /* UCA3IE[UCSTTIE] Bits */
\r
12985 //#define UCSTTIE_OFS ( 2) /* UCSTTIE Offset */
\r
12986 //#define UCSTTIE (0x0004) /* Start bit interrupt enable */
\r
12987 /* UCA3IE[UCTXCPTIE] Bits */
\r
12988 //#define UCTXCPTIE_OFS ( 3) /* UCTXCPTIE Offset */
\r
12989 //#define UCTXCPTIE (0x0008) /* Transmit complete interrupt enable */
\r
12990 /* UCA3IE_SPI[UCRXIE] Bits */
\r
12991 //#define UCRXIE_OFS ( 0) /* UCRXIE Offset */
\r
12992 //#define UCRXIE (0x0001) /* Receive interrupt enable */
\r
12993 /* UCA3IE_SPI[UCTXIE] Bits */
\r
12994 //#define UCTXIE_OFS ( 1) /* UCTXIE Offset */
\r
12995 //#define UCTXIE (0x0002) /* Transmit interrupt enable */
\r
12996 /* UCA3IFG[UCRXIFG] Bits */
\r
12997 //#define UCRXIFG_OFS ( 0) /* UCRXIFG Offset */
\r
12998 //#define UCRXIFG (0x0001) /* Receive interrupt flag */
\r
12999 /* UCA3IFG[UCTXIFG] Bits */
\r
13000 //#define UCTXIFG_OFS ( 1) /* UCTXIFG Offset */
\r
13001 //#define UCTXIFG (0x0002) /* Transmit interrupt flag */
\r
13002 /* UCA3IFG[UCSTTIFG] Bits */
\r
13003 //#define UCSTTIFG_OFS ( 2) /* UCSTTIFG Offset */
\r
13004 //#define UCSTTIFG (0x0004) /* Start bit interrupt flag */
\r
13005 /* UCA3IFG[UCTXCPTIFG] Bits */
\r
13006 //#define UCTXCPTIFG_OFS ( 3) /* UCTXCPTIFG Offset */
\r
13007 //#define UCTXCPTIFG (0x0008) /* Transmit ready interrupt enable */
\r
13008 /* UCA3IFG_SPI[UCRXIFG] Bits */
\r
13009 //#define UCRXIFG_OFS ( 0) /* UCRXIFG Offset */
\r
13010 //#define UCRXIFG (0x0001) /* Receive interrupt flag */
\r
13011 /* UCA3IFG_SPI[UCTXIFG] Bits */
\r
13012 //#define UCTXIFG_OFS ( 1) /* UCTXIFG Offset */
\r
13013 //#define UCTXIFG (0x0002) /* Transmit interrupt flag */
\r
13016 //*****************************************************************************
\r
13018 //*****************************************************************************
\r
13019 /* UCB0CTLW0[UCSWRST] Bits */
\r
13020 //#define UCSWRST_OFS ( 0) /* UCSWRST Offset */
\r
13021 //#define UCSWRST (0x0001) /* Software reset enable */
\r
13022 /* UCB0CTLW0[UCTXSTT] Bits */
\r
13023 #define UCTXSTT_OFS ( 1) /* UCTXSTT Offset */
\r
13024 #define UCTXSTT (0x0002) /* Transmit START condition in master mode */
\r
13025 /* UCB0CTLW0[UCTXSTP] Bits */
\r
13026 #define UCTXSTP_OFS ( 2) /* UCTXSTP Offset */
\r
13027 #define UCTXSTP (0x0004) /* Transmit STOP condition in master mode */
\r
13028 /* UCB0CTLW0[UCTXNACK] Bits */
\r
13029 #define UCTXNACK_OFS ( 3) /* UCTXNACK Offset */
\r
13030 #define UCTXNACK (0x0008) /* Transmit a NACK */
\r
13031 /* UCB0CTLW0[UCTR] Bits */
\r
13032 #define UCTR_OFS ( 4) /* UCTR Offset */
\r
13033 #define UCTR (0x0010) /* Transmitter/receiver */
\r
13034 /* UCB0CTLW0[UCTXACK] Bits */
\r
13035 #define UCTXACK_OFS ( 5) /* UCTXACK Offset */
\r
13036 #define UCTXACK (0x0020) /* Transmit ACK condition in slave mode */
\r
13037 /* UCB0CTLW0[UCSSEL] Bits */
\r
13038 //#define UCSSEL_OFS ( 6) /* UCSSEL Offset */
\r
13039 //#define UCSSEL_M (0x00c0) /* eUSCI_B clock source select */
\r
13040 //#define UCSSEL0 (0x0040) /* eUSCI_B clock source select */
\r
13041 //#define UCSSEL1 (0x0080) /* eUSCI_B clock source select */
\r
13042 //#define UCSSEL_0 (0x0000) /* UCLKI */
\r
13043 //#define UCSSEL_1 (0x0040) /* ACLK */
\r
13044 //#define UCSSEL_2 (0x0080) /* SMCLK */
\r
13045 #define UCSSEL__UCLKI (0x0000) /* UCLKI */
\r
13046 //#define UCSSEL__ACLK (0x0040) /* ACLK */
\r
13047 //#define UCSSEL__SMCLK (0x0080) /* SMCLK */
\r
13048 #define UCSSEL_3 (0x00c0) /* SMCLK */
\r
13049 /* UCB0CTLW0[UCSYNC] Bits */
\r
13050 //#define UCSYNC_OFS ( 8) /* UCSYNC Offset */
\r
13051 //#define UCSYNC (0x0100) /* Synchronous mode enable */
\r
13052 /* UCB0CTLW0[UCMODE] Bits */
\r
13053 //#define UCMODE_OFS ( 9) /* UCMODE Offset */
\r
13054 //#define UCMODE_M (0x0600) /* eUSCI_B mode */
\r
13055 //#define UCMODE0 (0x0200) /* eUSCI_B mode */
\r
13056 //#define UCMODE1 (0x0400) /* eUSCI_B mode */
\r
13057 //#define UCMODE_0 (0x0000) /* 3-pin SPI */
\r
13058 //#define UCMODE_1 (0x0200) /* 4-pin SPI (master or slave enabled if STE = 1) */
\r
13059 //#define UCMODE_2 (0x0400) /* 4-pin SPI (master or slave enabled if STE = 0) */
\r
13060 //#define UCMODE_3 (0x0600) /* I2C mode */
\r
13061 /* UCB0CTLW0[UCMST] Bits */
\r
13062 //#define UCMST_OFS (11) /* UCMST Offset */
\r
13063 //#define UCMST (0x0800) /* Master mode select */
\r
13064 /* UCB0CTLW0[UCMM] Bits */
\r
13065 #define UCMM_OFS (13) /* UCMM Offset */
\r
13066 #define UCMM (0x2000) /* Multi-master environment select */
\r
13067 /* UCB0CTLW0[UCSLA10] Bits */
\r
13068 #define UCSLA10_OFS (14) /* UCSLA10 Offset */
\r
13069 #define UCSLA10 (0x4000) /* Slave addressing mode select */
\r
13070 /* UCB0CTLW0[UCA10] Bits */
\r
13071 #define UCA10_OFS (15) /* UCA10 Offset */
\r
13072 #define UCA10 (0x8000) /* Own addressing mode select */
\r
13073 /* UCB0CTLW0_SPI[UCSWRST] Bits */
\r
13074 //#define UCSWRST_OFS ( 0) /* UCSWRST Offset */
\r
13075 //#define UCSWRST (0x0001) /* Software reset enable */
\r
13076 /* UCB0CTLW0_SPI[UCSTEM] Bits */
\r
13077 //#define UCSTEM_OFS ( 1) /* UCSTEM Offset */
\r
13078 //#define UCSTEM (0x0002) /* STE mode select in master mode. */
\r
13079 /* UCB0CTLW0_SPI[UCSSEL] Bits */
\r
13080 //#define UCSSEL_OFS ( 6) /* UCSSEL Offset */
\r
13081 //#define UCSSEL_M (0x00c0) /* eUSCI_B clock source select */
\r
13082 //#define UCSSEL0 (0x0040) /* eUSCI_B clock source select */
\r
13083 //#define UCSSEL1 (0x0080) /* eUSCI_B clock source select */
\r
13084 //#define UCSSEL_1 (0x0040) /* ACLK */
\r
13085 //#define UCSSEL_2 (0x0080) /* SMCLK */
\r
13086 //#define UCSSEL_0 (0x0000) /* Reserved */
\r
13087 //#define UCSSEL__ACLK (0x0040) /* ACLK */
\r
13088 //#define UCSSEL__SMCLK (0x0080) /* SMCLK */
\r
13089 //#define UCSSEL_3 (0x00c0) /* SMCLK */
\r
13090 /* UCB0CTLW0_SPI[UCSYNC] Bits */
\r
13091 //#define UCSYNC_OFS ( 8) /* UCSYNC Offset */
\r
13092 //#define UCSYNC (0x0100) /* Synchronous mode enable */
\r
13093 /* UCB0CTLW0_SPI[UCMODE] Bits */
\r
13094 //#define UCMODE_OFS ( 9) /* UCMODE Offset */
\r
13095 //#define UCMODE_M (0x0600) /* eUSCI mode */
\r
13096 //#define UCMODE0 (0x0200) /* eUSCI mode */
\r
13097 //#define UCMODE1 (0x0400) /* eUSCI mode */
\r
13098 //#define UCMODE_0 (0x0000) /* 3-pin SPI */
\r
13099 //#define UCMODE_1 (0x0200) /* 4-pin SPI with UCxSTE active high: Slave enabled when UCxSTE = 1 */
\r
13100 //#define UCMODE_2 (0x0400) /* 4-pin SPI with UCxSTE active low: Slave enabled when UCxSTE = 0 */
\r
13101 //#define UCMODE_3 (0x0600) /* I2C mode */
\r
13102 /* UCB0CTLW0_SPI[UCMST] Bits */
\r
13103 //#define UCMST_OFS (11) /* UCMST Offset */
\r
13104 //#define UCMST (0x0800) /* Master mode select */
\r
13105 /* UCB0CTLW0_SPI[UC7BIT] Bits */
\r
13106 //#define UC7BIT_OFS (12) /* UC7BIT Offset */
\r
13107 //#define UC7BIT (0x1000) /* Character length */
\r
13108 /* UCB0CTLW0_SPI[UCMSB] Bits */
\r
13109 //#define UCMSB_OFS (13) /* UCMSB Offset */
\r
13110 //#define UCMSB (0x2000) /* MSB first select */
\r
13111 /* UCB0CTLW0_SPI[UCCKPL] Bits */
\r
13112 //#define UCCKPL_OFS (14) /* UCCKPL Offset */
\r
13113 //#define UCCKPL (0x4000) /* Clock polarity select */
\r
13114 /* UCB0CTLW0_SPI[UCCKPH] Bits */
\r
13115 //#define UCCKPH_OFS (15) /* UCCKPH Offset */
\r
13116 //#define UCCKPH (0x8000) /* Clock phase select */
\r
13117 /* UCB0CTLW1[UCGLIT] Bits */
\r
13118 //#define UCGLIT_OFS ( 0) /* UCGLIT Offset */
\r
13119 //#define UCGLIT_M (0x0003) /* Deglitch time */
\r
13120 //#define UCGLIT0 (0x0001) /* Deglitch time */
\r
13121 //#define UCGLIT1 (0x0002) /* Deglitch time */
\r
13122 //#define UCGLIT_0 (0x0000) /* 50 ns */
\r
13123 //#define UCGLIT_1 (0x0001) /* 25 ns */
\r
13124 //#define UCGLIT_2 (0x0002) /* 12.5 ns */
\r
13125 //#define UCGLIT_3 (0x0003) /* 6.25 ns */
\r
13126 /* UCB0CTLW1[UCASTP] Bits */
\r
13127 #define UCASTP_OFS ( 2) /* UCASTP Offset */
\r
13128 #define UCASTP_M (0x000c) /* Automatic STOP condition generation */
\r
13129 #define UCASTP0 (0x0004) /* Automatic STOP condition generation */
\r
13130 #define UCASTP1 (0x0008) /* Automatic STOP condition generation */
\r
13131 #define UCASTP_0 (0x0000) /* No automatic STOP generation. The STOP condition is generated after the user sets the UCTXSTP bit. The value in UCBxTBCNT is a don't care. */
\r
13132 #define UCASTP_1 (0x0004) /* UCBCNTIFG is set with the byte counter reaches the threshold defined in UCBxTBCNT */
\r
13133 #define UCASTP_2 (0x0008) /* A STOP condition is generated automatically after the byte counter value reached UCBxTBCNT. UCBCNTIFG is set with the byte counter reaching the threshold */
\r
13134 /* UCB0CTLW1[UCSWACK] Bits */
\r
13135 #define UCSWACK_OFS ( 4) /* UCSWACK Offset */
\r
13136 #define UCSWACK (0x0010) /* SW or HW ACK control */
\r
13137 /* UCB0CTLW1[UCSTPNACK] Bits */
\r
13138 #define UCSTPNACK_OFS ( 5) /* UCSTPNACK Offset */
\r
13139 #define UCSTPNACK (0x0020) /* ACK all master bytes */
\r
13140 /* UCB0CTLW1[UCCLTO] Bits */
\r
13141 #define UCCLTO_OFS ( 6) /* UCCLTO Offset */
\r
13142 #define UCCLTO_M (0x00c0) /* Clock low timeout select */
\r
13143 #define UCCLTO0 (0x0040) /* Clock low timeout select */
\r
13144 #define UCCLTO1 (0x0080) /* Clock low timeout select */
\r
13145 #define UCCLTO_0 (0x0000) /* Disable clock low timeout counter */
\r
13146 #define UCCLTO_1 (0x0040) /* 135 000 SYSCLK cycles (approximately 28 ms) */
\r
13147 #define UCCLTO_2 (0x0080) /* 150 000 SYSCLK cycles (approximately 31 ms) */
\r
13148 #define UCCLTO_3 (0x00c0) /* 165 000 SYSCLK cycles (approximately 34 ms) */
\r
13149 /* UCB0CTLW1[UCETXINT] Bits */
\r
13150 #define UCETXINT_OFS ( 8) /* UCETXINT Offset */
\r
13151 #define UCETXINT (0x0100) /* Early UCTXIFG0 */
\r
13152 /* UCB0STATW[UCBBUSY] Bits */
\r
13153 #define UCBBUSY_OFS ( 4) /* UCBBUSY Offset */
\r
13154 #define UCBBUSY (0x0010) /* Bus busy */
\r
13155 /* UCB0STATW[UCGC] Bits */
\r
13156 #define UCGC_OFS ( 5) /* UCGC Offset */
\r
13157 #define UCGC (0x0020) /* General call address received */
\r
13158 /* UCB0STATW[UCSCLLOW] Bits */
\r
13159 #define UCSCLLOW_OFS ( 6) /* UCSCLLOW Offset */
\r
13160 #define UCSCLLOW (0x0040) /* SCL low */
\r
13161 /* UCB0STATW[UCBCNT] Bits */
\r
13162 #define UCBCNT_OFS ( 8) /* UCBCNT Offset */
\r
13163 #define UCBCNT_M (0xff00) /* Hardware byte counter value */
\r
13164 /* UCB0STATW_SPI[UCBUSY] Bits */
\r
13165 //#define UCBUSY_OFS ( 0) /* UCBUSY Offset */
\r
13166 //#define UCBUSY (0x0001) /* eUSCI_B busy */
\r
13167 /* UCB0STATW_SPI[UCOE] Bits */
\r
13168 //#define UCOE_OFS ( 5) /* UCOE Offset */
\r
13169 //#define UCOE (0x0020) /* Overrun error flag */
\r
13170 /* UCB0STATW_SPI[UCFE] Bits */
\r
13171 //#define UCFE_OFS ( 6) /* UCFE Offset */
\r
13172 //#define UCFE (0x0040) /* Framing error flag */
\r
13173 /* UCB0STATW_SPI[UCLISTEN] Bits */
\r
13174 //#define UCLISTEN_OFS ( 7) /* UCLISTEN Offset */
\r
13175 //#define UCLISTEN (0x0080) /* Listen enable */
\r
13176 /* UCB0TBCNT[UCTBCNT] Bits */
\r
13177 #define UCTBCNT_OFS ( 0) /* UCTBCNT Offset */
\r
13178 #define UCTBCNT_M (0x00ff) /* Byte counter threshold value */
\r
13179 /* UCB0RXBUF[UCRXBUF] Bits */
\r
13180 //#define UCRXBUF_OFS ( 0) /* UCRXBUF Offset */
\r
13181 //#define UCRXBUF_M (0x00ff) /* Receive data buffer */
\r
13182 /* UCB0RXBUF_SPI[UCRXBUF] Bits */
\r
13183 //#define UCRXBUF_OFS ( 0) /* UCRXBUF Offset */
\r
13184 //#define UCRXBUF_M (0x00ff) /* Receive data buffer */
\r
13185 /* UCB0TXBUF[UCTXBUF] Bits */
\r
13186 //#define UCTXBUF_OFS ( 0) /* UCTXBUF Offset */
\r
13187 //#define UCTXBUF_M (0x00ff) /* Transmit data buffer */
\r
13188 /* UCB0TXBUF_SPI[UCTXBUF] Bits */
\r
13189 //#define UCTXBUF_OFS ( 0) /* UCTXBUF Offset */
\r
13190 //#define UCTXBUF_M (0x00ff) /* Transmit data buffer */
\r
13191 /* UCB0I2COA0[I2COA0] Bits */
\r
13192 #define I2COA0_OFS ( 0) /* I2COA0 Offset */
\r
13193 #define I2COA0_M (0x03ff) /* I2C own address */
\r
13194 /* UCB0I2COA0[UCOAEN] Bits */
\r
13195 #define UCOAEN_OFS (10) /* UCOAEN Offset */
\r
13196 #define UCOAEN (0x0400) /* Own Address enable register */
\r
13197 /* UCB0I2COA0[UCGCEN] Bits */
\r
13198 #define UCGCEN_OFS (15) /* UCGCEN Offset */
\r
13199 #define UCGCEN (0x8000) /* General call response enable */
\r
13200 /* UCB0I2COA1[I2COA1] Bits */
\r
13201 #define I2COA1_OFS ( 0) /* I2COA1 Offset */
\r
13202 #define I2COA1_M (0x03ff) /* I2C own address */
\r
13203 /* UCB0I2COA1[UCOAEN] Bits */
\r
13204 //#define UCOAEN_OFS (10) /* UCOAEN Offset */
\r
13205 //#define UCOAEN (0x0400) /* Own Address enable register */
\r
13206 /* UCB0I2COA2[I2COA2] Bits */
\r
13207 #define I2COA2_OFS ( 0) /* I2COA2 Offset */
\r
13208 #define I2COA2_M (0x03ff) /* I2C own address */
\r
13209 /* UCB0I2COA2[UCOAEN] Bits */
\r
13210 //#define UCOAEN_OFS (10) /* UCOAEN Offset */
\r
13211 //#define UCOAEN (0x0400) /* Own Address enable register */
\r
13212 /* UCB0I2COA3[I2COA3] Bits */
\r
13213 #define I2COA3_OFS ( 0) /* I2COA3 Offset */
\r
13214 #define I2COA3_M (0x03ff) /* I2C own address */
\r
13215 /* UCB0I2COA3[UCOAEN] Bits */
\r
13216 //#define UCOAEN_OFS (10) /* UCOAEN Offset */
\r
13217 //#define UCOAEN (0x0400) /* Own Address enable register */
\r
13218 /* UCB0ADDRX[ADDRX] Bits */
\r
13219 #define ADDRX_OFS ( 0) /* ADDRX Offset */
\r
13220 #define ADDRX_M (0x03ff) /* Received Address Register */
\r
13221 /* UCB0ADDMASK[ADDMASK] Bits */
\r
13222 #define ADDMASK_OFS ( 0) /* ADDMASK Offset */
\r
13223 #define ADDMASK_M (0x03ff) /* */
\r
13224 /* UCB0I2CSA[I2CSA] Bits */
\r
13225 #define I2CSA_OFS ( 0) /* I2CSA Offset */
\r
13226 #define I2CSA_M (0x03ff) /* I2C slave address */
\r
13227 /* UCB0IE[UCRXIE0] Bits */
\r
13228 #define UCRXIE0_OFS ( 0) /* UCRXIE0 Offset */
\r
13229 #define UCRXIE0 (0x0001) /* Receive interrupt enable 0 */
\r
13230 /* UCB0IE[UCTXIE0] Bits */
\r
13231 #define UCTXIE0_OFS ( 1) /* UCTXIE0 Offset */
\r
13232 #define UCTXIE0 (0x0002) /* Transmit interrupt enable 0 */
\r
13233 /* UCB0IE[UCSTTIE] Bits */
\r
13234 //#define UCSTTIE_OFS ( 2) /* UCSTTIE Offset */
\r
13235 //#define UCSTTIE (0x0004) /* START condition interrupt enable */
\r
13236 /* UCB0IE[UCSTPIE] Bits */
\r
13237 #define UCSTPIE_OFS ( 3) /* UCSTPIE Offset */
\r
13238 #define UCSTPIE (0x0008) /* STOP condition interrupt enable */
\r
13239 /* UCB0IE[UCALIE] Bits */
\r
13240 #define UCALIE_OFS ( 4) /* UCALIE Offset */
\r
13241 #define UCALIE (0x0010) /* Arbitration lost interrupt enable */
\r
13242 /* UCB0IE[UCNACKIE] Bits */
\r
13243 #define UCNACKIE_OFS ( 5) /* UCNACKIE Offset */
\r
13244 #define UCNACKIE (0x0020) /* Not-acknowledge interrupt enable */
\r
13245 /* UCB0IE[UCBCNTIE] Bits */
\r
13246 #define UCBCNTIE_OFS ( 6) /* UCBCNTIE Offset */
\r
13247 #define UCBCNTIE (0x0040) /* Byte counter interrupt enable */
\r
13248 /* UCB0IE[UCCLTOIE] Bits */
\r
13249 #define UCCLTOIE_OFS ( 7) /* UCCLTOIE Offset */
\r
13250 #define UCCLTOIE (0x0080) /* Clock low timeout interrupt enable */
\r
13251 /* UCB0IE[UCRXIE1] Bits */
\r
13252 #define UCRXIE1_OFS ( 8) /* UCRXIE1 Offset */
\r
13253 #define UCRXIE1 (0x0100) /* Receive interrupt enable 1 */
\r
13254 /* UCB0IE[UCTXIE1] Bits */
\r
13255 #define UCTXIE1_OFS ( 9) /* UCTXIE1 Offset */
\r
13256 #define UCTXIE1 (0x0200) /* Transmit interrupt enable 1 */
\r
13257 /* UCB0IE[UCRXIE2] Bits */
\r
13258 #define UCRXIE2_OFS (10) /* UCRXIE2 Offset */
\r
13259 #define UCRXIE2 (0x0400) /* Receive interrupt enable 2 */
\r
13260 /* UCB0IE[UCTXIE2] Bits */
\r
13261 #define UCTXIE2_OFS (11) /* UCTXIE2 Offset */
\r
13262 #define UCTXIE2 (0x0800) /* Transmit interrupt enable 2 */
\r
13263 /* UCB0IE[UCRXIE3] Bits */
\r
13264 #define UCRXIE3_OFS (12) /* UCRXIE3 Offset */
\r
13265 #define UCRXIE3 (0x1000) /* Receive interrupt enable 3 */
\r
13266 /* UCB0IE[UCTXIE3] Bits */
\r
13267 #define UCTXIE3_OFS (13) /* UCTXIE3 Offset */
\r
13268 #define UCTXIE3 (0x2000) /* Transmit interrupt enable 3 */
\r
13269 /* UCB0IE[UCBIT9IE] Bits */
\r
13270 #define UCBIT9IE_OFS (14) /* UCBIT9IE Offset */
\r
13271 #define UCBIT9IE (0x4000) /* Bit position 9 interrupt enable */
\r
13272 /* UCB0IE_SPI[UCRXIE] Bits */
\r
13273 //#define UCRXIE_OFS ( 0) /* UCRXIE Offset */
\r
13274 //#define UCRXIE (0x0001) /* Receive interrupt enable */
\r
13275 /* UCB0IE_SPI[UCTXIE] Bits */
\r
13276 //#define UCTXIE_OFS ( 1) /* UCTXIE Offset */
\r
13277 //#define UCTXIE (0x0002) /* Transmit interrupt enable */
\r
13278 /* UCB0IFG[UCRXIFG0] Bits */
\r
13279 #define UCRXIFG0_OFS ( 0) /* UCRXIFG0 Offset */
\r
13280 #define UCRXIFG0 (0x0001) /* eUSCI_B receive interrupt flag 0 */
\r
13281 /* UCB0IFG[UCTXIFG0] Bits */
\r
13282 #define UCTXIFG0_OFS ( 1) /* UCTXIFG0 Offset */
\r
13283 #define UCTXIFG0 (0x0002) /* eUSCI_B transmit interrupt flag 0 */
\r
13284 /* UCB0IFG[UCSTTIFG] Bits */
\r
13285 //#define UCSTTIFG_OFS ( 2) /* UCSTTIFG Offset */
\r
13286 //#define UCSTTIFG (0x0004) /* START condition interrupt flag */
\r
13287 /* UCB0IFG[UCSTPIFG] Bits */
\r
13288 #define UCSTPIFG_OFS ( 3) /* UCSTPIFG Offset */
\r
13289 #define UCSTPIFG (0x0008) /* STOP condition interrupt flag */
\r
13290 /* UCB0IFG[UCALIFG] Bits */
\r
13291 #define UCALIFG_OFS ( 4) /* UCALIFG Offset */
\r
13292 #define UCALIFG (0x0010) /* Arbitration lost interrupt flag */
\r
13293 /* UCB0IFG[UCNACKIFG] Bits */
\r
13294 #define UCNACKIFG_OFS ( 5) /* UCNACKIFG Offset */
\r
13295 #define UCNACKIFG (0x0020) /* Not-acknowledge received interrupt flag */
\r
13296 /* UCB0IFG[UCBCNTIFG] Bits */
\r
13297 #define UCBCNTIFG_OFS ( 6) /* UCBCNTIFG Offset */
\r
13298 #define UCBCNTIFG (0x0040) /* Byte counter interrupt flag */
\r
13299 /* UCB0IFG[UCCLTOIFG] Bits */
\r
13300 #define UCCLTOIFG_OFS ( 7) /* UCCLTOIFG Offset */
\r
13301 #define UCCLTOIFG (0x0080) /* Clock low timeout interrupt flag */
\r
13302 /* UCB0IFG[UCRXIFG1] Bits */
\r
13303 #define UCRXIFG1_OFS ( 8) /* UCRXIFG1 Offset */
\r
13304 #define UCRXIFG1 (0x0100) /* eUSCI_B receive interrupt flag 1 */
\r
13305 /* UCB0IFG[UCTXIFG1] Bits */
\r
13306 #define UCTXIFG1_OFS ( 9) /* UCTXIFG1 Offset */
\r
13307 #define UCTXIFG1 (0x0200) /* eUSCI_B transmit interrupt flag 1 */
\r
13308 /* UCB0IFG[UCRXIFG2] Bits */
\r
13309 #define UCRXIFG2_OFS (10) /* UCRXIFG2 Offset */
\r
13310 #define UCRXIFG2 (0x0400) /* eUSCI_B receive interrupt flag 2 */
\r
13311 /* UCB0IFG[UCTXIFG2] Bits */
\r
13312 #define UCTXIFG2_OFS (11) /* UCTXIFG2 Offset */
\r
13313 #define UCTXIFG2 (0x0800) /* eUSCI_B transmit interrupt flag 2 */
\r
13314 /* UCB0IFG[UCRXIFG3] Bits */
\r
13315 #define UCRXIFG3_OFS (12) /* UCRXIFG3 Offset */
\r
13316 #define UCRXIFG3 (0x1000) /* eUSCI_B receive interrupt flag 3 */
\r
13317 /* UCB0IFG[UCTXIFG3] Bits */
\r
13318 #define UCTXIFG3_OFS (13) /* UCTXIFG3 Offset */
\r
13319 #define UCTXIFG3 (0x2000) /* eUSCI_B transmit interrupt flag 3 */
\r
13320 /* UCB0IFG[UCBIT9IFG] Bits */
\r
13321 #define UCBIT9IFG_OFS (14) /* UCBIT9IFG Offset */
\r
13322 #define UCBIT9IFG (0x4000) /* Bit position 9 interrupt flag */
\r
13323 /* UCB0IFG_SPI[UCRXIFG] Bits */
\r
13324 //#define UCRXIFG_OFS ( 0) /* UCRXIFG Offset */
\r
13325 //#define UCRXIFG (0x0001) /* Receive interrupt flag */
\r
13326 /* UCB0IFG_SPI[UCTXIFG] Bits */
\r
13327 //#define UCTXIFG_OFS ( 1) /* UCTXIFG Offset */
\r
13328 //#define UCTXIFG (0x0002) /* Transmit interrupt flag */
\r
13331 //*****************************************************************************
\r
13333 //*****************************************************************************
\r
13334 /* UCB1CTLW0[UCSWRST] Bits */
\r
13335 //#define UCSWRST_OFS ( 0) /* UCSWRST Offset */
\r
13336 //#define UCSWRST (0x0001) /* Software reset enable */
\r
13337 /* UCB1CTLW0[UCTXSTT] Bits */
\r
13338 //#define UCTXSTT_OFS ( 1) /* UCTXSTT Offset */
\r
13339 //#define UCTXSTT (0x0002) /* Transmit START condition in master mode */
\r
13340 /* UCB1CTLW0[UCTXSTP] Bits */
\r
13341 //#define UCTXSTP_OFS ( 2) /* UCTXSTP Offset */
\r
13342 //#define UCTXSTP (0x0004) /* Transmit STOP condition in master mode */
\r
13343 /* UCB1CTLW0[UCTXNACK] Bits */
\r
13344 //#define UCTXNACK_OFS ( 3) /* UCTXNACK Offset */
\r
13345 //#define UCTXNACK (0x0008) /* Transmit a NACK */
\r
13346 /* UCB1CTLW0[UCTR] Bits */
\r
13347 //#define UCTR_OFS ( 4) /* UCTR Offset */
\r
13348 //#define UCTR (0x0010) /* Transmitter/receiver */
\r
13349 /* UCB1CTLW0[UCTXACK] Bits */
\r
13350 //#define UCTXACK_OFS ( 5) /* UCTXACK Offset */
\r
13351 //#define UCTXACK (0x0020) /* Transmit ACK condition in slave mode */
\r
13352 /* UCB1CTLW0[UCSSEL] Bits */
\r
13353 //#define UCSSEL_OFS ( 6) /* UCSSEL Offset */
\r
13354 //#define UCSSEL_M (0x00c0) /* eUSCI_B clock source select */
\r
13355 //#define UCSSEL0 (0x0040) /* eUSCI_B clock source select */
\r
13356 //#define UCSSEL1 (0x0080) /* eUSCI_B clock source select */
\r
13357 //#define UCSSEL_0 (0x0000) /* UCLKI */
\r
13358 //#define UCSSEL_1 (0x0040) /* ACLK */
\r
13359 //#define UCSSEL_2 (0x0080) /* SMCLK */
\r
13360 //#define UCSSEL__UCLKI (0x0000) /* UCLKI */
\r
13361 //#define UCSSEL__ACLK (0x0040) /* ACLK */
\r
13362 //#define UCSSEL__SMCLK (0x0080) /* SMCLK */
\r
13363 //#define UCSSEL_3 (0x00c0) /* SMCLK */
\r
13364 /* UCB1CTLW0[UCSYNC] Bits */
\r
13365 //#define UCSYNC_OFS ( 8) /* UCSYNC Offset */
\r
13366 //#define UCSYNC (0x0100) /* Synchronous mode enable */
\r
13367 /* UCB1CTLW0[UCMODE] Bits */
\r
13368 //#define UCMODE_OFS ( 9) /* UCMODE Offset */
\r
13369 //#define UCMODE_M (0x0600) /* eUSCI_B mode */
\r
13370 //#define UCMODE0 (0x0200) /* eUSCI_B mode */
\r
13371 //#define UCMODE1 (0x0400) /* eUSCI_B mode */
\r
13372 //#define UCMODE_0 (0x0000) /* 3-pin SPI */
\r
13373 //#define UCMODE_1 (0x0200) /* 4-pin SPI (master or slave enabled if STE = 1) */
\r
13374 //#define UCMODE_2 (0x0400) /* 4-pin SPI (master or slave enabled if STE = 0) */
\r
13375 //#define UCMODE_3 (0x0600) /* I2C mode */
\r
13376 /* UCB1CTLW0[UCMST] Bits */
\r
13377 //#define UCMST_OFS (11) /* UCMST Offset */
\r
13378 //#define UCMST (0x0800) /* Master mode select */
\r
13379 /* UCB1CTLW0[UCMM] Bits */
\r
13380 //#define UCMM_OFS (13) /* UCMM Offset */
\r
13381 //#define UCMM (0x2000) /* Multi-master environment select */
\r
13382 /* UCB1CTLW0[UCSLA10] Bits */
\r
13383 //#define UCSLA10_OFS (14) /* UCSLA10 Offset */
\r
13384 //#define UCSLA10 (0x4000) /* Slave addressing mode select */
\r
13385 /* UCB1CTLW0[UCA10] Bits */
\r
13386 //#define UCA10_OFS (15) /* UCA10 Offset */
\r
13387 //#define UCA10 (0x8000) /* Own addressing mode select */
\r
13388 /* UCB1CTLW0_SPI[UCSWRST] Bits */
\r
13389 //#define UCSWRST_OFS ( 0) /* UCSWRST Offset */
\r
13390 //#define UCSWRST (0x0001) /* Software reset enable */
\r
13391 /* UCB1CTLW0_SPI[UCSTEM] Bits */
\r
13392 //#define UCSTEM_OFS ( 1) /* UCSTEM Offset */
\r
13393 //#define UCSTEM (0x0002) /* STE mode select in master mode. */
\r
13394 /* UCB1CTLW0_SPI[UCSSEL] Bits */
\r
13395 //#define UCSSEL_OFS ( 6) /* UCSSEL Offset */
\r
13396 //#define UCSSEL_M (0x00c0) /* eUSCI_B clock source select */
\r
13397 //#define UCSSEL0 (0x0040) /* eUSCI_B clock source select */
\r
13398 //#define UCSSEL1 (0x0080) /* eUSCI_B clock source select */
\r
13399 //#define UCSSEL_1 (0x0040) /* ACLK */
\r
13400 //#define UCSSEL_2 (0x0080) /* SMCLK */
\r
13401 //#define UCSSEL_0 (0x0000) /* Reserved */
\r
13402 //#define UCSSEL__ACLK (0x0040) /* ACLK */
\r
13403 //#define UCSSEL__SMCLK (0x0080) /* SMCLK */
\r
13404 //#define UCSSEL_3 (0x00c0) /* SMCLK */
\r
13405 /* UCB1CTLW0_SPI[UCSYNC] Bits */
\r
13406 //#define UCSYNC_OFS ( 8) /* UCSYNC Offset */
\r
13407 //#define UCSYNC (0x0100) /* Synchronous mode enable */
\r
13408 /* UCB1CTLW0_SPI[UCMODE] Bits */
\r
13409 //#define UCMODE_OFS ( 9) /* UCMODE Offset */
\r
13410 //#define UCMODE_M (0x0600) /* eUSCI mode */
\r
13411 //#define UCMODE0 (0x0200) /* eUSCI mode */
\r
13412 //#define UCMODE1 (0x0400) /* eUSCI mode */
\r
13413 //#define UCMODE_0 (0x0000) /* 3-pin SPI */
\r
13414 //#define UCMODE_1 (0x0200) /* 4-pin SPI with UCxSTE active high: Slave enabled when UCxSTE = 1 */
\r
13415 //#define UCMODE_2 (0x0400) /* 4-pin SPI with UCxSTE active low: Slave enabled when UCxSTE = 0 */
\r
13416 //#define UCMODE_3 (0x0600) /* I2C mode */
\r
13417 /* UCB1CTLW0_SPI[UCMST] Bits */
\r
13418 //#define UCMST_OFS (11) /* UCMST Offset */
\r
13419 //#define UCMST (0x0800) /* Master mode select */
\r
13420 /* UCB1CTLW0_SPI[UC7BIT] Bits */
\r
13421 //#define UC7BIT_OFS (12) /* UC7BIT Offset */
\r
13422 //#define UC7BIT (0x1000) /* Character length */
\r
13423 /* UCB1CTLW0_SPI[UCMSB] Bits */
\r
13424 //#define UCMSB_OFS (13) /* UCMSB Offset */
\r
13425 //#define UCMSB (0x2000) /* MSB first select */
\r
13426 /* UCB1CTLW0_SPI[UCCKPL] Bits */
\r
13427 //#define UCCKPL_OFS (14) /* UCCKPL Offset */
\r
13428 //#define UCCKPL (0x4000) /* Clock polarity select */
\r
13429 /* UCB1CTLW0_SPI[UCCKPH] Bits */
\r
13430 //#define UCCKPH_OFS (15) /* UCCKPH Offset */
\r
13431 //#define UCCKPH (0x8000) /* Clock phase select */
\r
13432 /* UCB1CTLW1[UCGLIT] Bits */
\r
13433 //#define UCGLIT_OFS ( 0) /* UCGLIT Offset */
\r
13434 //#define UCGLIT_M (0x0003) /* Deglitch time */
\r
13435 //#define UCGLIT0 (0x0001) /* Deglitch time */
\r
13436 //#define UCGLIT1 (0x0002) /* Deglitch time */
\r
13437 //#define UCGLIT_0 (0x0000) /* 50 ns */
\r
13438 //#define UCGLIT_1 (0x0001) /* 25 ns */
\r
13439 //#define UCGLIT_2 (0x0002) /* 12.5 ns */
\r
13440 //#define UCGLIT_3 (0x0003) /* 6.25 ns */
\r
13441 /* UCB1CTLW1[UCASTP] Bits */
\r
13442 //#define UCASTP_OFS ( 2) /* UCASTP Offset */
\r
13443 //#define UCASTP_M (0x000c) /* Automatic STOP condition generation */
\r
13444 //#define UCASTP0 (0x0004) /* Automatic STOP condition generation */
\r
13445 //#define UCASTP1 (0x0008) /* Automatic STOP condition generation */
\r
13446 //#define UCASTP_0 (0x0000) /* No automatic STOP generation. The STOP condition is generated after the user sets the UCTXSTP bit. The value in UCBxTBCNT is a don't care. */
\r
13447 //#define UCASTP_1 (0x0004) /* UCBCNTIFG is set with the byte counter reaches the threshold defined in UCBxTBCNT */
\r
13448 //#define UCASTP_2 (0x0008) /* A STOP condition is generated automatically after the byte counter value reached UCBxTBCNT. UCBCNTIFG is set with the byte counter reaching the threshold */
\r
13449 /* UCB1CTLW1[UCSWACK] Bits */
\r
13450 //#define UCSWACK_OFS ( 4) /* UCSWACK Offset */
\r
13451 //#define UCSWACK (0x0010) /* SW or HW ACK control */
\r
13452 /* UCB1CTLW1[UCSTPNACK] Bits */
\r
13453 //#define UCSTPNACK_OFS ( 5) /* UCSTPNACK Offset */
\r
13454 //#define UCSTPNACK (0x0020) /* ACK all master bytes */
\r
13455 /* UCB1CTLW1[UCCLTO] Bits */
\r
13456 //#define UCCLTO_OFS ( 6) /* UCCLTO Offset */
\r
13457 //#define UCCLTO_M (0x00c0) /* Clock low timeout select */
\r
13458 //#define UCCLTO0 (0x0040) /* Clock low timeout select */
\r
13459 //#define UCCLTO1 (0x0080) /* Clock low timeout select */
\r
13460 //#define UCCLTO_0 (0x0000) /* Disable clock low timeout counter */
\r
13461 //#define UCCLTO_1 (0x0040) /* 135 000 SYSCLK cycles (approximately 28 ms) */
\r
13462 //#define UCCLTO_2 (0x0080) /* 150 000 SYSCLK cycles (approximately 31 ms) */
\r
13463 //#define UCCLTO_3 (0x00c0) /* 165 000 SYSCLK cycles (approximately 34 ms) */
\r
13464 /* UCB1CTLW1[UCETXINT] Bits */
\r
13465 //#define UCETXINT_OFS ( 8) /* UCETXINT Offset */
\r
13466 //#define UCETXINT (0x0100) /* Early UCTXIFG0 */
\r
13467 /* UCB1STATW[UCBBUSY] Bits */
\r
13468 //#define UCBBUSY_OFS ( 4) /* UCBBUSY Offset */
\r
13469 //#define UCBBUSY (0x0010) /* Bus busy */
\r
13470 /* UCB1STATW[UCGC] Bits */
\r
13471 //#define UCGC_OFS ( 5) /* UCGC Offset */
\r
13472 //#define UCGC (0x0020) /* General call address received */
\r
13473 /* UCB1STATW[UCSCLLOW] Bits */
\r
13474 //#define UCSCLLOW_OFS ( 6) /* UCSCLLOW Offset */
\r
13475 //#define UCSCLLOW (0x0040) /* SCL low */
\r
13476 /* UCB1STATW[UCBCNT] Bits */
\r
13477 //#define UCBCNT_OFS ( 8) /* UCBCNT Offset */
\r
13478 //#define UCBCNT_M (0xff00) /* Hardware byte counter value */
\r
13479 /* UCB1STATW_SPI[UCBUSY] Bits */
\r
13480 //#define UCBUSY_OFS ( 0) /* UCBUSY Offset */
\r
13481 //#define UCBUSY (0x0001) /* eUSCI_B busy */
\r
13482 /* UCB1STATW_SPI[UCOE] Bits */
\r
13483 //#define UCOE_OFS ( 5) /* UCOE Offset */
\r
13484 //#define UCOE (0x0020) /* Overrun error flag */
\r
13485 /* UCB1STATW_SPI[UCFE] Bits */
\r
13486 //#define UCFE_OFS ( 6) /* UCFE Offset */
\r
13487 //#define UCFE (0x0040) /* Framing error flag */
\r
13488 /* UCB1STATW_SPI[UCLISTEN] Bits */
\r
13489 //#define UCLISTEN_OFS ( 7) /* UCLISTEN Offset */
\r
13490 //#define UCLISTEN (0x0080) /* Listen enable */
\r
13491 /* UCB1TBCNT[UCTBCNT] Bits */
\r
13492 //#define UCTBCNT_OFS ( 0) /* UCTBCNT Offset */
\r
13493 //#define UCTBCNT_M (0x00ff) /* Byte counter threshold value */
\r
13494 /* UCB1RXBUF[UCRXBUF] Bits */
\r
13495 //#define UCRXBUF_OFS ( 0) /* UCRXBUF Offset */
\r
13496 //#define UCRXBUF_M (0x00ff) /* Receive data buffer */
\r
13497 /* UCB1RXBUF_SPI[UCRXBUF] Bits */
\r
13498 //#define UCRXBUF_OFS ( 0) /* UCRXBUF Offset */
\r
13499 //#define UCRXBUF_M (0x00ff) /* Receive data buffer */
\r
13500 /* UCB1TXBUF[UCTXBUF] Bits */
\r
13501 //#define UCTXBUF_OFS ( 0) /* UCTXBUF Offset */
\r
13502 //#define UCTXBUF_M (0x00ff) /* Transmit data buffer */
\r
13503 /* UCB1TXBUF_SPI[UCTXBUF] Bits */
\r
13504 //#define UCTXBUF_OFS ( 0) /* UCTXBUF Offset */
\r
13505 //#define UCTXBUF_M (0x00ff) /* Transmit data buffer */
\r
13506 /* UCB1I2COA0[I2COA0] Bits */
\r
13507 //#define I2COA0_OFS ( 0) /* I2COA0 Offset */
\r
13508 //#define I2COA0_M (0x03ff) /* I2C own address */
\r
13509 /* UCB1I2COA0[UCOAEN] Bits */
\r
13510 //#define UCOAEN_OFS (10) /* UCOAEN Offset */
\r
13511 //#define UCOAEN (0x0400) /* Own Address enable register */
\r
13512 /* UCB1I2COA0[UCGCEN] Bits */
\r
13513 //#define UCGCEN_OFS (15) /* UCGCEN Offset */
\r
13514 //#define UCGCEN (0x8000) /* General call response enable */
\r
13515 /* UCB1I2COA1[I2COA1] Bits */
\r
13516 //#define I2COA1_OFS ( 0) /* I2COA1 Offset */
\r
13517 //#define I2COA1_M (0x03ff) /* I2C own address */
\r
13518 /* UCB1I2COA1[UCOAEN] Bits */
\r
13519 //#define UCOAEN_OFS (10) /* UCOAEN Offset */
\r
13520 //#define UCOAEN (0x0400) /* Own Address enable register */
\r
13521 /* UCB1I2COA2[I2COA2] Bits */
\r
13522 //#define I2COA2_OFS ( 0) /* I2COA2 Offset */
\r
13523 //#define I2COA2_M (0x03ff) /* I2C own address */
\r
13524 /* UCB1I2COA2[UCOAEN] Bits */
\r
13525 //#define UCOAEN_OFS (10) /* UCOAEN Offset */
\r
13526 //#define UCOAEN (0x0400) /* Own Address enable register */
\r
13527 /* UCB1I2COA3[I2COA3] Bits */
\r
13528 //#define I2COA3_OFS ( 0) /* I2COA3 Offset */
\r
13529 //#define I2COA3_M (0x03ff) /* I2C own address */
\r
13530 /* UCB1I2COA3[UCOAEN] Bits */
\r
13531 //#define UCOAEN_OFS (10) /* UCOAEN Offset */
\r
13532 //#define UCOAEN (0x0400) /* Own Address enable register */
\r
13533 /* UCB1ADDRX[ADDRX] Bits */
\r
13534 //#define ADDRX_OFS ( 0) /* ADDRX Offset */
\r
13535 //#define ADDRX_M (0x03ff) /* Received Address Register */
\r
13536 /* UCB1ADDMASK[ADDMASK] Bits */
\r
13537 //#define ADDMASK_OFS ( 0) /* ADDMASK Offset */
\r
13538 //#define ADDMASK_M (0x03ff) /* */
\r
13539 /* UCB1I2CSA[I2CSA] Bits */
\r
13540 //#define I2CSA_OFS ( 0) /* I2CSA Offset */
\r
13541 //#define I2CSA_M (0x03ff) /* I2C slave address */
\r
13542 /* UCB1IE[UCRXIE0] Bits */
\r
13543 //#define UCRXIE0_OFS ( 0) /* UCRXIE0 Offset */
\r
13544 //#define UCRXIE0 (0x0001) /* Receive interrupt enable 0 */
\r
13545 /* UCB1IE[UCTXIE0] Bits */
\r
13546 //#define UCTXIE0_OFS ( 1) /* UCTXIE0 Offset */
\r
13547 //#define UCTXIE0 (0x0002) /* Transmit interrupt enable 0 */
\r
13548 /* UCB1IE[UCSTTIE] Bits */
\r
13549 //#define UCSTTIE_OFS ( 2) /* UCSTTIE Offset */
\r
13550 //#define UCSTTIE (0x0004) /* START condition interrupt enable */
\r
13551 /* UCB1IE[UCSTPIE] Bits */
\r
13552 //#define UCSTPIE_OFS ( 3) /* UCSTPIE Offset */
\r
13553 //#define UCSTPIE (0x0008) /* STOP condition interrupt enable */
\r
13554 /* UCB1IE[UCALIE] Bits */
\r
13555 //#define UCALIE_OFS ( 4) /* UCALIE Offset */
\r
13556 //#define UCALIE (0x0010) /* Arbitration lost interrupt enable */
\r
13557 /* UCB1IE[UCNACKIE] Bits */
\r
13558 //#define UCNACKIE_OFS ( 5) /* UCNACKIE Offset */
\r
13559 //#define UCNACKIE (0x0020) /* Not-acknowledge interrupt enable */
\r
13560 /* UCB1IE[UCBCNTIE] Bits */
\r
13561 //#define UCBCNTIE_OFS ( 6) /* UCBCNTIE Offset */
\r
13562 //#define UCBCNTIE (0x0040) /* Byte counter interrupt enable */
\r
13563 /* UCB1IE[UCCLTOIE] Bits */
\r
13564 //#define UCCLTOIE_OFS ( 7) /* UCCLTOIE Offset */
\r
13565 //#define UCCLTOIE (0x0080) /* Clock low timeout interrupt enable */
\r
13566 /* UCB1IE[UCRXIE1] Bits */
\r
13567 //#define UCRXIE1_OFS ( 8) /* UCRXIE1 Offset */
\r
13568 //#define UCRXIE1 (0x0100) /* Receive interrupt enable 1 */
\r
13569 /* UCB1IE[UCTXIE1] Bits */
\r
13570 //#define UCTXIE1_OFS ( 9) /* UCTXIE1 Offset */
\r
13571 //#define UCTXIE1 (0x0200) /* Transmit interrupt enable 1 */
\r
13572 /* UCB1IE[UCRXIE2] Bits */
\r
13573 //#define UCRXIE2_OFS (10) /* UCRXIE2 Offset */
\r
13574 //#define UCRXIE2 (0x0400) /* Receive interrupt enable 2 */
\r
13575 /* UCB1IE[UCTXIE2] Bits */
\r
13576 //#define UCTXIE2_OFS (11) /* UCTXIE2 Offset */
\r
13577 //#define UCTXIE2 (0x0800) /* Transmit interrupt enable 2 */
\r
13578 /* UCB1IE[UCRXIE3] Bits */
\r
13579 //#define UCRXIE3_OFS (12) /* UCRXIE3 Offset */
\r
13580 //#define UCRXIE3 (0x1000) /* Receive interrupt enable 3 */
\r
13581 /* UCB1IE[UCTXIE3] Bits */
\r
13582 //#define UCTXIE3_OFS (13) /* UCTXIE3 Offset */
\r
13583 //#define UCTXIE3 (0x2000) /* Transmit interrupt enable 3 */
\r
13584 /* UCB1IE[UCBIT9IE] Bits */
\r
13585 //#define UCBIT9IE_OFS (14) /* UCBIT9IE Offset */
\r
13586 //#define UCBIT9IE (0x4000) /* Bit position 9 interrupt enable */
\r
13587 /* UCB1IE_SPI[UCRXIE] Bits */
\r
13588 //#define UCRXIE_OFS ( 0) /* UCRXIE Offset */
\r
13589 //#define UCRXIE (0x0001) /* Receive interrupt enable */
\r
13590 /* UCB1IE_SPI[UCTXIE] Bits */
\r
13591 //#define UCTXIE_OFS ( 1) /* UCTXIE Offset */
\r
13592 //#define UCTXIE (0x0002) /* Transmit interrupt enable */
\r
13593 /* UCB1IFG[UCRXIFG0] Bits */
\r
13594 //#define UCRXIFG0_OFS ( 0) /* UCRXIFG0 Offset */
\r
13595 //#define UCRXIFG0 (0x0001) /* eUSCI_B receive interrupt flag 0 */
\r
13596 /* UCB1IFG[UCTXIFG0] Bits */
\r
13597 //#define UCTXIFG0_OFS ( 1) /* UCTXIFG0 Offset */
\r
13598 //#define UCTXIFG0 (0x0002) /* eUSCI_B transmit interrupt flag 0 */
\r
13599 /* UCB1IFG[UCSTTIFG] Bits */
\r
13600 //#define UCSTTIFG_OFS ( 2) /* UCSTTIFG Offset */
\r
13601 //#define UCSTTIFG (0x0004) /* START condition interrupt flag */
\r
13602 /* UCB1IFG[UCSTPIFG] Bits */
\r
13603 //#define UCSTPIFG_OFS ( 3) /* UCSTPIFG Offset */
\r
13604 //#define UCSTPIFG (0x0008) /* STOP condition interrupt flag */
\r
13605 /* UCB1IFG[UCALIFG] Bits */
\r
13606 //#define UCALIFG_OFS ( 4) /* UCALIFG Offset */
\r
13607 //#define UCALIFG (0x0010) /* Arbitration lost interrupt flag */
\r
13608 /* UCB1IFG[UCNACKIFG] Bits */
\r
13609 //#define UCNACKIFG_OFS ( 5) /* UCNACKIFG Offset */
\r
13610 //#define UCNACKIFG (0x0020) /* Not-acknowledge received interrupt flag */
\r
13611 /* UCB1IFG[UCBCNTIFG] Bits */
\r
13612 //#define UCBCNTIFG_OFS ( 6) /* UCBCNTIFG Offset */
\r
13613 //#define UCBCNTIFG (0x0040) /* Byte counter interrupt flag */
\r
13614 /* UCB1IFG[UCCLTOIFG] Bits */
\r
13615 //#define UCCLTOIFG_OFS ( 7) /* UCCLTOIFG Offset */
\r
13616 //#define UCCLTOIFG (0x0080) /* Clock low timeout interrupt flag */
\r
13617 /* UCB1IFG[UCRXIFG1] Bits */
\r
13618 //#define UCRXIFG1_OFS ( 8) /* UCRXIFG1 Offset */
\r
13619 //#define UCRXIFG1 (0x0100) /* eUSCI_B receive interrupt flag 1 */
\r
13620 /* UCB1IFG[UCTXIFG1] Bits */
\r
13621 //#define UCTXIFG1_OFS ( 9) /* UCTXIFG1 Offset */
\r
13622 //#define UCTXIFG1 (0x0200) /* eUSCI_B transmit interrupt flag 1 */
\r
13623 /* UCB1IFG[UCRXIFG2] Bits */
\r
13624 //#define UCRXIFG2_OFS (10) /* UCRXIFG2 Offset */
\r
13625 //#define UCRXIFG2 (0x0400) /* eUSCI_B receive interrupt flag 2 */
\r
13626 /* UCB1IFG[UCTXIFG2] Bits */
\r
13627 //#define UCTXIFG2_OFS (11) /* UCTXIFG2 Offset */
\r
13628 //#define UCTXIFG2 (0x0800) /* eUSCI_B transmit interrupt flag 2 */
\r
13629 /* UCB1IFG[UCRXIFG3] Bits */
\r
13630 //#define UCRXIFG3_OFS (12) /* UCRXIFG3 Offset */
\r
13631 //#define UCRXIFG3 (0x1000) /* eUSCI_B receive interrupt flag 3 */
\r
13632 /* UCB1IFG[UCTXIFG3] Bits */
\r
13633 //#define UCTXIFG3_OFS (13) /* UCTXIFG3 Offset */
\r
13634 //#define UCTXIFG3 (0x2000) /* eUSCI_B transmit interrupt flag 3 */
\r
13635 /* UCB1IFG[UCBIT9IFG] Bits */
\r
13636 //#define UCBIT9IFG_OFS (14) /* UCBIT9IFG Offset */
\r
13637 //#define UCBIT9IFG (0x4000) /* Bit position 9 interrupt flag */
\r
13638 /* UCB1IFG_SPI[UCRXIFG] Bits */
\r
13639 //#define UCRXIFG_OFS ( 0) /* UCRXIFG Offset */
\r
13640 //#define UCRXIFG (0x0001) /* Receive interrupt flag */
\r
13641 /* UCB1IFG_SPI[UCTXIFG] Bits */
\r
13642 //#define UCTXIFG_OFS ( 1) /* UCTXIFG Offset */
\r
13643 //#define UCTXIFG (0x0002) /* Transmit interrupt flag */
\r
13646 //*****************************************************************************
\r
13648 //*****************************************************************************
\r
13649 /* UCB2CTLW0[UCSWRST] Bits */
\r
13650 //#define UCSWRST_OFS ( 0) /* UCSWRST Offset */
\r
13651 //#define UCSWRST (0x0001) /* Software reset enable */
\r
13652 /* UCB2CTLW0[UCTXSTT] Bits */
\r
13653 //#define UCTXSTT_OFS ( 1) /* UCTXSTT Offset */
\r
13654 //#define UCTXSTT (0x0002) /* Transmit START condition in master mode */
\r
13655 /* UCB2CTLW0[UCTXSTP] Bits */
\r
13656 //#define UCTXSTP_OFS ( 2) /* UCTXSTP Offset */
\r
13657 //#define UCTXSTP (0x0004) /* Transmit STOP condition in master mode */
\r
13658 /* UCB2CTLW0[UCTXNACK] Bits */
\r
13659 //#define UCTXNACK_OFS ( 3) /* UCTXNACK Offset */
\r
13660 //#define UCTXNACK (0x0008) /* Transmit a NACK */
\r
13661 /* UCB2CTLW0[UCTR] Bits */
\r
13662 //#define UCTR_OFS ( 4) /* UCTR Offset */
\r
13663 //#define UCTR (0x0010) /* Transmitter/receiver */
\r
13664 /* UCB2CTLW0[UCTXACK] Bits */
\r
13665 //#define UCTXACK_OFS ( 5) /* UCTXACK Offset */
\r
13666 //#define UCTXACK (0x0020) /* Transmit ACK condition in slave mode */
\r
13667 /* UCB2CTLW0[UCSSEL] Bits */
\r
13668 //#define UCSSEL_OFS ( 6) /* UCSSEL Offset */
\r
13669 //#define UCSSEL_M (0x00c0) /* eUSCI_B clock source select */
\r
13670 //#define UCSSEL0 (0x0040) /* eUSCI_B clock source select */
\r
13671 //#define UCSSEL1 (0x0080) /* eUSCI_B clock source select */
\r
13672 //#define UCSSEL_0 (0x0000) /* UCLKI */
\r
13673 //#define UCSSEL_1 (0x0040) /* ACLK */
\r
13674 //#define UCSSEL_2 (0x0080) /* SMCLK */
\r
13675 //#define UCSSEL__UCLKI (0x0000) /* UCLKI */
\r
13676 //#define UCSSEL__ACLK (0x0040) /* ACLK */
\r
13677 //#define UCSSEL__SMCLK (0x0080) /* SMCLK */
\r
13678 //#define UCSSEL_3 (0x00c0) /* SMCLK */
\r
13679 /* UCB2CTLW0[UCSYNC] Bits */
\r
13680 //#define UCSYNC_OFS ( 8) /* UCSYNC Offset */
\r
13681 //#define UCSYNC (0x0100) /* Synchronous mode enable */
\r
13682 /* UCB2CTLW0[UCMODE] Bits */
\r
13683 //#define UCMODE_OFS ( 9) /* UCMODE Offset */
\r
13684 //#define UCMODE_M (0x0600) /* eUSCI_B mode */
\r
13685 //#define UCMODE0 (0x0200) /* eUSCI_B mode */
\r
13686 //#define UCMODE1 (0x0400) /* eUSCI_B mode */
\r
13687 //#define UCMODE_0 (0x0000) /* 3-pin SPI */
\r
13688 //#define UCMODE_1 (0x0200) /* 4-pin SPI (master or slave enabled if STE = 1) */
\r
13689 //#define UCMODE_2 (0x0400) /* 4-pin SPI (master or slave enabled if STE = 0) */
\r
13690 //#define UCMODE_3 (0x0600) /* I2C mode */
\r
13691 /* UCB2CTLW0[UCMST] Bits */
\r
13692 //#define UCMST_OFS (11) /* UCMST Offset */
\r
13693 //#define UCMST (0x0800) /* Master mode select */
\r
13694 /* UCB2CTLW0[UCMM] Bits */
\r
13695 //#define UCMM_OFS (13) /* UCMM Offset */
\r
13696 //#define UCMM (0x2000) /* Multi-master environment select */
\r
13697 /* UCB2CTLW0[UCSLA10] Bits */
\r
13698 //#define UCSLA10_OFS (14) /* UCSLA10 Offset */
\r
13699 //#define UCSLA10 (0x4000) /* Slave addressing mode select */
\r
13700 /* UCB2CTLW0[UCA10] Bits */
\r
13701 //#define UCA10_OFS (15) /* UCA10 Offset */
\r
13702 //#define UCA10 (0x8000) /* Own addressing mode select */
\r
13703 /* UCB2CTLW0_SPI[UCSWRST] Bits */
\r
13704 //#define UCSWRST_OFS ( 0) /* UCSWRST Offset */
\r
13705 //#define UCSWRST (0x0001) /* Software reset enable */
\r
13706 /* UCB2CTLW0_SPI[UCSTEM] Bits */
\r
13707 //#define UCSTEM_OFS ( 1) /* UCSTEM Offset */
\r
13708 //#define UCSTEM (0x0002) /* STE mode select in master mode. */
\r
13709 /* UCB2CTLW0_SPI[UCSSEL] Bits */
\r
13710 //#define UCSSEL_OFS ( 6) /* UCSSEL Offset */
\r
13711 //#define UCSSEL_M (0x00c0) /* eUSCI_B clock source select */
\r
13712 //#define UCSSEL0 (0x0040) /* eUSCI_B clock source select */
\r
13713 //#define UCSSEL1 (0x0080) /* eUSCI_B clock source select */
\r
13714 //#define UCSSEL_1 (0x0040) /* ACLK */
\r
13715 //#define UCSSEL_2 (0x0080) /* SMCLK */
\r
13716 //#define UCSSEL_0 (0x0000) /* Reserved */
\r
13717 //#define UCSSEL__ACLK (0x0040) /* ACLK */
\r
13718 //#define UCSSEL__SMCLK (0x0080) /* SMCLK */
\r
13719 //#define UCSSEL_3 (0x00c0) /* SMCLK */
\r
13720 /* UCB2CTLW0_SPI[UCSYNC] Bits */
\r
13721 //#define UCSYNC_OFS ( 8) /* UCSYNC Offset */
\r
13722 //#define UCSYNC (0x0100) /* Synchronous mode enable */
\r
13723 /* UCB2CTLW0_SPI[UCMODE] Bits */
\r
13724 //#define UCMODE_OFS ( 9) /* UCMODE Offset */
\r
13725 //#define UCMODE_M (0x0600) /* eUSCI mode */
\r
13726 //#define UCMODE0 (0x0200) /* eUSCI mode */
\r
13727 //#define UCMODE1 (0x0400) /* eUSCI mode */
\r
13728 //#define UCMODE_0 (0x0000) /* 3-pin SPI */
\r
13729 //#define UCMODE_1 (0x0200) /* 4-pin SPI with UCxSTE active high: Slave enabled when UCxSTE = 1 */
\r
13730 //#define UCMODE_2 (0x0400) /* 4-pin SPI with UCxSTE active low: Slave enabled when UCxSTE = 0 */
\r
13731 //#define UCMODE_3 (0x0600) /* I2C mode */
\r
13732 /* UCB2CTLW0_SPI[UCMST] Bits */
\r
13733 //#define UCMST_OFS (11) /* UCMST Offset */
\r
13734 //#define UCMST (0x0800) /* Master mode select */
\r
13735 /* UCB2CTLW0_SPI[UC7BIT] Bits */
\r
13736 //#define UC7BIT_OFS (12) /* UC7BIT Offset */
\r
13737 //#define UC7BIT (0x1000) /* Character length */
\r
13738 /* UCB2CTLW0_SPI[UCMSB] Bits */
\r
13739 //#define UCMSB_OFS (13) /* UCMSB Offset */
\r
13740 //#define UCMSB (0x2000) /* MSB first select */
\r
13741 /* UCB2CTLW0_SPI[UCCKPL] Bits */
\r
13742 //#define UCCKPL_OFS (14) /* UCCKPL Offset */
\r
13743 //#define UCCKPL (0x4000) /* Clock polarity select */
\r
13744 /* UCB2CTLW0_SPI[UCCKPH] Bits */
\r
13745 //#define UCCKPH_OFS (15) /* UCCKPH Offset */
\r
13746 //#define UCCKPH (0x8000) /* Clock phase select */
\r
13747 /* UCB2CTLW1[UCGLIT] Bits */
\r
13748 //#define UCGLIT_OFS ( 0) /* UCGLIT Offset */
\r
13749 //#define UCGLIT_M (0x0003) /* Deglitch time */
\r
13750 //#define UCGLIT0 (0x0001) /* Deglitch time */
\r
13751 //#define UCGLIT1 (0x0002) /* Deglitch time */
\r
13752 //#define UCGLIT_0 (0x0000) /* 50 ns */
\r
13753 //#define UCGLIT_1 (0x0001) /* 25 ns */
\r
13754 //#define UCGLIT_2 (0x0002) /* 12.5 ns */
\r
13755 //#define UCGLIT_3 (0x0003) /* 6.25 ns */
\r
13756 /* UCB2CTLW1[UCASTP] Bits */
\r
13757 //#define UCASTP_OFS ( 2) /* UCASTP Offset */
\r
13758 //#define UCASTP_M (0x000c) /* Automatic STOP condition generation */
\r
13759 //#define UCASTP0 (0x0004) /* Automatic STOP condition generation */
\r
13760 //#define UCASTP1 (0x0008) /* Automatic STOP condition generation */
\r
13761 //#define UCASTP_0 (0x0000) /* No automatic STOP generation. The STOP condition is generated after the user sets the UCTXSTP bit. The value in UCBxTBCNT is a don't care. */
\r
13762 //#define UCASTP_1 (0x0004) /* UCBCNTIFG is set with the byte counter reaches the threshold defined in UCBxTBCNT */
\r
13763 //#define UCASTP_2 (0x0008) /* A STOP condition is generated automatically after the byte counter value reached UCBxTBCNT. UCBCNTIFG is set with the byte counter reaching the threshold */
\r
13764 /* UCB2CTLW1[UCSWACK] Bits */
\r
13765 //#define UCSWACK_OFS ( 4) /* UCSWACK Offset */
\r
13766 //#define UCSWACK (0x0010) /* SW or HW ACK control */
\r
13767 /* UCB2CTLW1[UCSTPNACK] Bits */
\r
13768 //#define UCSTPNACK_OFS ( 5) /* UCSTPNACK Offset */
\r
13769 //#define UCSTPNACK (0x0020) /* ACK all master bytes */
\r
13770 /* UCB2CTLW1[UCCLTO] Bits */
\r
13771 //#define UCCLTO_OFS ( 6) /* UCCLTO Offset */
\r
13772 //#define UCCLTO_M (0x00c0) /* Clock low timeout select */
\r
13773 //#define UCCLTO0 (0x0040) /* Clock low timeout select */
\r
13774 //#define UCCLTO1 (0x0080) /* Clock low timeout select */
\r
13775 //#define UCCLTO_0 (0x0000) /* Disable clock low timeout counter */
\r
13776 //#define UCCLTO_1 (0x0040) /* 135 000 SYSCLK cycles (approximately 28 ms) */
\r
13777 //#define UCCLTO_2 (0x0080) /* 150 000 SYSCLK cycles (approximately 31 ms) */
\r
13778 //#define UCCLTO_3 (0x00c0) /* 165 000 SYSCLK cycles (approximately 34 ms) */
\r
13779 /* UCB2CTLW1[UCETXINT] Bits */
\r
13780 //#define UCETXINT_OFS ( 8) /* UCETXINT Offset */
\r
13781 //#define UCETXINT (0x0100) /* Early UCTXIFG0 */
\r
13782 /* UCB2STATW[UCBBUSY] Bits */
\r
13783 //#define UCBBUSY_OFS ( 4) /* UCBBUSY Offset */
\r
13784 //#define UCBBUSY (0x0010) /* Bus busy */
\r
13785 /* UCB2STATW[UCGC] Bits */
\r
13786 //#define UCGC_OFS ( 5) /* UCGC Offset */
\r
13787 //#define UCGC (0x0020) /* General call address received */
\r
13788 /* UCB2STATW[UCSCLLOW] Bits */
\r
13789 //#define UCSCLLOW_OFS ( 6) /* UCSCLLOW Offset */
\r
13790 //#define UCSCLLOW (0x0040) /* SCL low */
\r
13791 /* UCB2STATW[UCBCNT] Bits */
\r
13792 //#define UCBCNT_OFS ( 8) /* UCBCNT Offset */
\r
13793 //#define UCBCNT_M (0xff00) /* Hardware byte counter value */
\r
13794 /* UCB2STATW_SPI[UCBUSY] Bits */
\r
13795 //#define UCBUSY_OFS ( 0) /* UCBUSY Offset */
\r
13796 //#define UCBUSY (0x0001) /* eUSCI_B busy */
\r
13797 /* UCB2STATW_SPI[UCOE] Bits */
\r
13798 //#define UCOE_OFS ( 5) /* UCOE Offset */
\r
13799 //#define UCOE (0x0020) /* Overrun error flag */
\r
13800 /* UCB2STATW_SPI[UCFE] Bits */
\r
13801 //#define UCFE_OFS ( 6) /* UCFE Offset */
\r
13802 //#define UCFE (0x0040) /* Framing error flag */
\r
13803 /* UCB2STATW_SPI[UCLISTEN] Bits */
\r
13804 //#define UCLISTEN_OFS ( 7) /* UCLISTEN Offset */
\r
13805 //#define UCLISTEN (0x0080) /* Listen enable */
\r
13806 /* UCB2TBCNT[UCTBCNT] Bits */
\r
13807 //#define UCTBCNT_OFS ( 0) /* UCTBCNT Offset */
\r
13808 //#define UCTBCNT_M (0x00ff) /* Byte counter threshold value */
\r
13809 /* UCB2RXBUF[UCRXBUF] Bits */
\r
13810 //#define UCRXBUF_OFS ( 0) /* UCRXBUF Offset */
\r
13811 //#define UCRXBUF_M (0x00ff) /* Receive data buffer */
\r
13812 /* UCB2RXBUF_SPI[UCRXBUF] Bits */
\r
13813 //#define UCRXBUF_OFS ( 0) /* UCRXBUF Offset */
\r
13814 //#define UCRXBUF_M (0x00ff) /* Receive data buffer */
\r
13815 /* UCB2TXBUF[UCTXBUF] Bits */
\r
13816 //#define UCTXBUF_OFS ( 0) /* UCTXBUF Offset */
\r
13817 //#define UCTXBUF_M (0x00ff) /* Transmit data buffer */
\r
13818 /* UCB2TXBUF_SPI[UCTXBUF] Bits */
\r
13819 //#define UCTXBUF_OFS ( 0) /* UCTXBUF Offset */
\r
13820 //#define UCTXBUF_M (0x00ff) /* Transmit data buffer */
\r
13821 /* UCB2I2COA0[I2COA0] Bits */
\r
13822 //#define I2COA0_OFS ( 0) /* I2COA0 Offset */
\r
13823 //#define I2COA0_M (0x03ff) /* I2C own address */
\r
13824 /* UCB2I2COA0[UCOAEN] Bits */
\r
13825 //#define UCOAEN_OFS (10) /* UCOAEN Offset */
\r
13826 //#define UCOAEN (0x0400) /* Own Address enable register */
\r
13827 /* UCB2I2COA0[UCGCEN] Bits */
\r
13828 //#define UCGCEN_OFS (15) /* UCGCEN Offset */
\r
13829 //#define UCGCEN (0x8000) /* General call response enable */
\r
13830 /* UCB2I2COA1[I2COA1] Bits */
\r
13831 //#define I2COA1_OFS ( 0) /* I2COA1 Offset */
\r
13832 //#define I2COA1_M (0x03ff) /* I2C own address */
\r
13833 /* UCB2I2COA1[UCOAEN] Bits */
\r
13834 //#define UCOAEN_OFS (10) /* UCOAEN Offset */
\r
13835 //#define UCOAEN (0x0400) /* Own Address enable register */
\r
13836 /* UCB2I2COA2[I2COA2] Bits */
\r
13837 //#define I2COA2_OFS ( 0) /* I2COA2 Offset */
\r
13838 //#define I2COA2_M (0x03ff) /* I2C own address */
\r
13839 /* UCB2I2COA2[UCOAEN] Bits */
\r
13840 //#define UCOAEN_OFS (10) /* UCOAEN Offset */
\r
13841 //#define UCOAEN (0x0400) /* Own Address enable register */
\r
13842 /* UCB2I2COA3[I2COA3] Bits */
\r
13843 //#define I2COA3_OFS ( 0) /* I2COA3 Offset */
\r
13844 //#define I2COA3_M (0x03ff) /* I2C own address */
\r
13845 /* UCB2I2COA3[UCOAEN] Bits */
\r
13846 //#define UCOAEN_OFS (10) /* UCOAEN Offset */
\r
13847 //#define UCOAEN (0x0400) /* Own Address enable register */
\r
13848 /* UCB2ADDRX[ADDRX] Bits */
\r
13849 //#define ADDRX_OFS ( 0) /* ADDRX Offset */
\r
13850 //#define ADDRX_M (0x03ff) /* Received Address Register */
\r
13851 /* UCB2ADDMASK[ADDMASK] Bits */
\r
13852 //#define ADDMASK_OFS ( 0) /* ADDMASK Offset */
\r
13853 //#define ADDMASK_M (0x03ff) /* */
\r
13854 /* UCB2I2CSA[I2CSA] Bits */
\r
13855 //#define I2CSA_OFS ( 0) /* I2CSA Offset */
\r
13856 //#define I2CSA_M (0x03ff) /* I2C slave address */
\r
13857 /* UCB2IE[UCRXIE0] Bits */
\r
13858 //#define UCRXIE0_OFS ( 0) /* UCRXIE0 Offset */
\r
13859 //#define UCRXIE0 (0x0001) /* Receive interrupt enable 0 */
\r
13860 /* UCB2IE[UCTXIE0] Bits */
\r
13861 //#define UCTXIE0_OFS ( 1) /* UCTXIE0 Offset */
\r
13862 //#define UCTXIE0 (0x0002) /* Transmit interrupt enable 0 */
\r
13863 /* UCB2IE[UCSTTIE] Bits */
\r
13864 //#define UCSTTIE_OFS ( 2) /* UCSTTIE Offset */
\r
13865 //#define UCSTTIE (0x0004) /* START condition interrupt enable */
\r
13866 /* UCB2IE[UCSTPIE] Bits */
\r
13867 //#define UCSTPIE_OFS ( 3) /* UCSTPIE Offset */
\r
13868 //#define UCSTPIE (0x0008) /* STOP condition interrupt enable */
\r
13869 /* UCB2IE[UCALIE] Bits */
\r
13870 //#define UCALIE_OFS ( 4) /* UCALIE Offset */
\r
13871 //#define UCALIE (0x0010) /* Arbitration lost interrupt enable */
\r
13872 /* UCB2IE[UCNACKIE] Bits */
\r
13873 //#define UCNACKIE_OFS ( 5) /* UCNACKIE Offset */
\r
13874 //#define UCNACKIE (0x0020) /* Not-acknowledge interrupt enable */
\r
13875 /* UCB2IE[UCBCNTIE] Bits */
\r
13876 //#define UCBCNTIE_OFS ( 6) /* UCBCNTIE Offset */
\r
13877 //#define UCBCNTIE (0x0040) /* Byte counter interrupt enable */
\r
13878 /* UCB2IE[UCCLTOIE] Bits */
\r
13879 //#define UCCLTOIE_OFS ( 7) /* UCCLTOIE Offset */
\r
13880 //#define UCCLTOIE (0x0080) /* Clock low timeout interrupt enable */
\r
13881 /* UCB2IE[UCRXIE1] Bits */
\r
13882 //#define UCRXIE1_OFS ( 8) /* UCRXIE1 Offset */
\r
13883 //#define UCRXIE1 (0x0100) /* Receive interrupt enable 1 */
\r
13884 /* UCB2IE[UCTXIE1] Bits */
\r
13885 //#define UCTXIE1_OFS ( 9) /* UCTXIE1 Offset */
\r
13886 //#define UCTXIE1 (0x0200) /* Transmit interrupt enable 1 */
\r
13887 /* UCB2IE[UCRXIE2] Bits */
\r
13888 //#define UCRXIE2_OFS (10) /* UCRXIE2 Offset */
\r
13889 //#define UCRXIE2 (0x0400) /* Receive interrupt enable 2 */
\r
13890 /* UCB2IE[UCTXIE2] Bits */
\r
13891 //#define UCTXIE2_OFS (11) /* UCTXIE2 Offset */
\r
13892 //#define UCTXIE2 (0x0800) /* Transmit interrupt enable 2 */
\r
13893 /* UCB2IE[UCRXIE3] Bits */
\r
13894 //#define UCRXIE3_OFS (12) /* UCRXIE3 Offset */
\r
13895 //#define UCRXIE3 (0x1000) /* Receive interrupt enable 3 */
\r
13896 /* UCB2IE[UCTXIE3] Bits */
\r
13897 //#define UCTXIE3_OFS (13) /* UCTXIE3 Offset */
\r
13898 //#define UCTXIE3 (0x2000) /* Transmit interrupt enable 3 */
\r
13899 /* UCB2IE[UCBIT9IE] Bits */
\r
13900 //#define UCBIT9IE_OFS (14) /* UCBIT9IE Offset */
\r
13901 //#define UCBIT9IE (0x4000) /* Bit position 9 interrupt enable */
\r
13902 /* UCB2IE_SPI[UCRXIE] Bits */
\r
13903 //#define UCRXIE_OFS ( 0) /* UCRXIE Offset */
\r
13904 //#define UCRXIE (0x0001) /* Receive interrupt enable */
\r
13905 /* UCB2IE_SPI[UCTXIE] Bits */
\r
13906 //#define UCTXIE_OFS ( 1) /* UCTXIE Offset */
\r
13907 //#define UCTXIE (0x0002) /* Transmit interrupt enable */
\r
13908 /* UCB2IFG[UCRXIFG0] Bits */
\r
13909 //#define UCRXIFG0_OFS ( 0) /* UCRXIFG0 Offset */
\r
13910 //#define UCRXIFG0 (0x0001) /* eUSCI_B receive interrupt flag 0 */
\r
13911 /* UCB2IFG[UCTXIFG0] Bits */
\r
13912 //#define UCTXIFG0_OFS ( 1) /* UCTXIFG0 Offset */
\r
13913 //#define UCTXIFG0 (0x0002) /* eUSCI_B transmit interrupt flag 0 */
\r
13914 /* UCB2IFG[UCSTTIFG] Bits */
\r
13915 //#define UCSTTIFG_OFS ( 2) /* UCSTTIFG Offset */
\r
13916 //#define UCSTTIFG (0x0004) /* START condition interrupt flag */
\r
13917 /* UCB2IFG[UCSTPIFG] Bits */
\r
13918 //#define UCSTPIFG_OFS ( 3) /* UCSTPIFG Offset */
\r
13919 //#define UCSTPIFG (0x0008) /* STOP condition interrupt flag */
\r
13920 /* UCB2IFG[UCALIFG] Bits */
\r
13921 //#define UCALIFG_OFS ( 4) /* UCALIFG Offset */
\r
13922 //#define UCALIFG (0x0010) /* Arbitration lost interrupt flag */
\r
13923 /* UCB2IFG[UCNACKIFG] Bits */
\r
13924 //#define UCNACKIFG_OFS ( 5) /* UCNACKIFG Offset */
\r
13925 //#define UCNACKIFG (0x0020) /* Not-acknowledge received interrupt flag */
\r
13926 /* UCB2IFG[UCBCNTIFG] Bits */
\r
13927 //#define UCBCNTIFG_OFS ( 6) /* UCBCNTIFG Offset */
\r
13928 //#define UCBCNTIFG (0x0040) /* Byte counter interrupt flag */
\r
13929 /* UCB2IFG[UCCLTOIFG] Bits */
\r
13930 //#define UCCLTOIFG_OFS ( 7) /* UCCLTOIFG Offset */
\r
13931 //#define UCCLTOIFG (0x0080) /* Clock low timeout interrupt flag */
\r
13932 /* UCB2IFG[UCRXIFG1] Bits */
\r
13933 //#define UCRXIFG1_OFS ( 8) /* UCRXIFG1 Offset */
\r
13934 //#define UCRXIFG1 (0x0100) /* eUSCI_B receive interrupt flag 1 */
\r
13935 /* UCB2IFG[UCTXIFG1] Bits */
\r
13936 //#define UCTXIFG1_OFS ( 9) /* UCTXIFG1 Offset */
\r
13937 //#define UCTXIFG1 (0x0200) /* eUSCI_B transmit interrupt flag 1 */
\r
13938 /* UCB2IFG[UCRXIFG2] Bits */
\r
13939 //#define UCRXIFG2_OFS (10) /* UCRXIFG2 Offset */
\r
13940 //#define UCRXIFG2 (0x0400) /* eUSCI_B receive interrupt flag 2 */
\r
13941 /* UCB2IFG[UCTXIFG2] Bits */
\r
13942 //#define UCTXIFG2_OFS (11) /* UCTXIFG2 Offset */
\r
13943 //#define UCTXIFG2 (0x0800) /* eUSCI_B transmit interrupt flag 2 */
\r
13944 /* UCB2IFG[UCRXIFG3] Bits */
\r
13945 //#define UCRXIFG3_OFS (12) /* UCRXIFG3 Offset */
\r
13946 //#define UCRXIFG3 (0x1000) /* eUSCI_B receive interrupt flag 3 */
\r
13947 /* UCB2IFG[UCTXIFG3] Bits */
\r
13948 //#define UCTXIFG3_OFS (13) /* UCTXIFG3 Offset */
\r
13949 //#define UCTXIFG3 (0x2000) /* eUSCI_B transmit interrupt flag 3 */
\r
13950 /* UCB2IFG[UCBIT9IFG] Bits */
\r
13951 //#define UCBIT9IFG_OFS (14) /* UCBIT9IFG Offset */
\r
13952 //#define UCBIT9IFG (0x4000) /* Bit position 9 interrupt flag */
\r
13953 /* UCB2IFG_SPI[UCRXIFG] Bits */
\r
13954 //#define UCRXIFG_OFS ( 0) /* UCRXIFG Offset */
\r
13955 //#define UCRXIFG (0x0001) /* Receive interrupt flag */
\r
13956 /* UCB2IFG_SPI[UCTXIFG] Bits */
\r
13957 //#define UCTXIFG_OFS ( 1) /* UCTXIFG Offset */
\r
13958 //#define UCTXIFG (0x0002) /* Transmit interrupt flag */
\r
13961 //*****************************************************************************
\r
13963 //*****************************************************************************
\r
13964 /* UCB3CTLW0[UCSWRST] Bits */
\r
13965 //#define UCSWRST_OFS ( 0) /* UCSWRST Offset */
\r
13966 //#define UCSWRST (0x0001) /* Software reset enable */
\r
13967 /* UCB3CTLW0[UCTXSTT] Bits */
\r
13968 //#define UCTXSTT_OFS ( 1) /* UCTXSTT Offset */
\r
13969 //#define UCTXSTT (0x0002) /* Transmit START condition in master mode */
\r
13970 /* UCB3CTLW0[UCTXSTP] Bits */
\r
13971 //#define UCTXSTP_OFS ( 2) /* UCTXSTP Offset */
\r
13972 //#define UCTXSTP (0x0004) /* Transmit STOP condition in master mode */
\r
13973 /* UCB3CTLW0[UCTXNACK] Bits */
\r
13974 //#define UCTXNACK_OFS ( 3) /* UCTXNACK Offset */
\r
13975 //#define UCTXNACK (0x0008) /* Transmit a NACK */
\r
13976 /* UCB3CTLW0[UCTR] Bits */
\r
13977 //#define UCTR_OFS ( 4) /* UCTR Offset */
\r
13978 //#define UCTR (0x0010) /* Transmitter/receiver */
\r
13979 /* UCB3CTLW0[UCTXACK] Bits */
\r
13980 //#define UCTXACK_OFS ( 5) /* UCTXACK Offset */
\r
13981 //#define UCTXACK (0x0020) /* Transmit ACK condition in slave mode */
\r
13982 /* UCB3CTLW0[UCSSEL] Bits */
\r
13983 //#define UCSSEL_OFS ( 6) /* UCSSEL Offset */
\r
13984 //#define UCSSEL_M (0x00c0) /* eUSCI_B clock source select */
\r
13985 //#define UCSSEL0 (0x0040) /* eUSCI_B clock source select */
\r
13986 //#define UCSSEL1 (0x0080) /* eUSCI_B clock source select */
\r
13987 //#define UCSSEL_0 (0x0000) /* UCLKI */
\r
13988 //#define UCSSEL_1 (0x0040) /* ACLK */
\r
13989 //#define UCSSEL_2 (0x0080) /* SMCLK */
\r
13990 //#define UCSSEL__UCLKI (0x0000) /* UCLKI */
\r
13991 //#define UCSSEL__ACLK (0x0040) /* ACLK */
\r
13992 //#define UCSSEL__SMCLK (0x0080) /* SMCLK */
\r
13993 //#define UCSSEL_3 (0x00c0) /* SMCLK */
\r
13994 /* UCB3CTLW0[UCSYNC] Bits */
\r
13995 //#define UCSYNC_OFS ( 8) /* UCSYNC Offset */
\r
13996 //#define UCSYNC (0x0100) /* Synchronous mode enable */
\r
13997 /* UCB3CTLW0[UCMODE] Bits */
\r
13998 //#define UCMODE_OFS ( 9) /* UCMODE Offset */
\r
13999 //#define UCMODE_M (0x0600) /* eUSCI_B mode */
\r
14000 //#define UCMODE0 (0x0200) /* eUSCI_B mode */
\r
14001 //#define UCMODE1 (0x0400) /* eUSCI_B mode */
\r
14002 //#define UCMODE_0 (0x0000) /* 3-pin SPI */
\r
14003 //#define UCMODE_1 (0x0200) /* 4-pin SPI (master or slave enabled if STE = 1) */
\r
14004 //#define UCMODE_2 (0x0400) /* 4-pin SPI (master or slave enabled if STE = 0) */
\r
14005 //#define UCMODE_3 (0x0600) /* I2C mode */
\r
14006 /* UCB3CTLW0[UCMST] Bits */
\r
14007 //#define UCMST_OFS (11) /* UCMST Offset */
\r
14008 //#define UCMST (0x0800) /* Master mode select */
\r
14009 /* UCB3CTLW0[UCMM] Bits */
\r
14010 //#define UCMM_OFS (13) /* UCMM Offset */
\r
14011 //#define UCMM (0x2000) /* Multi-master environment select */
\r
14012 /* UCB3CTLW0[UCSLA10] Bits */
\r
14013 //#define UCSLA10_OFS (14) /* UCSLA10 Offset */
\r
14014 //#define UCSLA10 (0x4000) /* Slave addressing mode select */
\r
14015 /* UCB3CTLW0[UCA10] Bits */
\r
14016 //#define UCA10_OFS (15) /* UCA10 Offset */
\r
14017 //#define UCA10 (0x8000) /* Own addressing mode select */
\r
14018 /* UCB3CTLW0_SPI[UCSWRST] Bits */
\r
14019 //#define UCSWRST_OFS ( 0) /* UCSWRST Offset */
\r
14020 //#define UCSWRST (0x0001) /* Software reset enable */
\r
14021 /* UCB3CTLW0_SPI[UCSTEM] Bits */
\r
14022 //#define UCSTEM_OFS ( 1) /* UCSTEM Offset */
\r
14023 //#define UCSTEM (0x0002) /* STE mode select in master mode. */
\r
14024 /* UCB3CTLW0_SPI[UCSSEL] Bits */
\r
14025 //#define UCSSEL_OFS ( 6) /* UCSSEL Offset */
\r
14026 //#define UCSSEL_M (0x00c0) /* eUSCI_B clock source select */
\r
14027 //#define UCSSEL0 (0x0040) /* eUSCI_B clock source select */
\r
14028 //#define UCSSEL1 (0x0080) /* eUSCI_B clock source select */
\r
14029 //#define UCSSEL_1 (0x0040) /* ACLK */
\r
14030 //#define UCSSEL_2 (0x0080) /* SMCLK */
\r
14031 //#define UCSSEL_0 (0x0000) /* Reserved */
\r
14032 //#define UCSSEL__ACLK (0x0040) /* ACLK */
\r
14033 //#define UCSSEL__SMCLK (0x0080) /* SMCLK */
\r
14034 //#define UCSSEL_3 (0x00c0) /* SMCLK */
\r
14035 /* UCB3CTLW0_SPI[UCSYNC] Bits */
\r
14036 //#define UCSYNC_OFS ( 8) /* UCSYNC Offset */
\r
14037 //#define UCSYNC (0x0100) /* Synchronous mode enable */
\r
14038 /* UCB3CTLW0_SPI[UCMODE] Bits */
\r
14039 //#define UCMODE_OFS ( 9) /* UCMODE Offset */
\r
14040 //#define UCMODE_M (0x0600) /* eUSCI mode */
\r
14041 //#define UCMODE0 (0x0200) /* eUSCI mode */
\r
14042 //#define UCMODE1 (0x0400) /* eUSCI mode */
\r
14043 //#define UCMODE_0 (0x0000) /* 3-pin SPI */
\r
14044 //#define UCMODE_1 (0x0200) /* 4-pin SPI with UCxSTE active high: Slave enabled when UCxSTE = 1 */
\r
14045 //#define UCMODE_2 (0x0400) /* 4-pin SPI with UCxSTE active low: Slave enabled when UCxSTE = 0 */
\r
14046 //#define UCMODE_3 (0x0600) /* I2C mode */
\r
14047 /* UCB3CTLW0_SPI[UCMST] Bits */
\r
14048 //#define UCMST_OFS (11) /* UCMST Offset */
\r
14049 //#define UCMST (0x0800) /* Master mode select */
\r
14050 /* UCB3CTLW0_SPI[UC7BIT] Bits */
\r
14051 //#define UC7BIT_OFS (12) /* UC7BIT Offset */
\r
14052 //#define UC7BIT (0x1000) /* Character length */
\r
14053 /* UCB3CTLW0_SPI[UCMSB] Bits */
\r
14054 //#define UCMSB_OFS (13) /* UCMSB Offset */
\r
14055 //#define UCMSB (0x2000) /* MSB first select */
\r
14056 /* UCB3CTLW0_SPI[UCCKPL] Bits */
\r
14057 //#define UCCKPL_OFS (14) /* UCCKPL Offset */
\r
14058 //#define UCCKPL (0x4000) /* Clock polarity select */
\r
14059 /* UCB3CTLW0_SPI[UCCKPH] Bits */
\r
14060 //#define UCCKPH_OFS (15) /* UCCKPH Offset */
\r
14061 //#define UCCKPH (0x8000) /* Clock phase select */
\r
14062 /* UCB3CTLW1[UCGLIT] Bits */
\r
14063 //#define UCGLIT_OFS ( 0) /* UCGLIT Offset */
\r
14064 //#define UCGLIT_M (0x0003) /* Deglitch time */
\r
14065 //#define UCGLIT0 (0x0001) /* Deglitch time */
\r
14066 //#define UCGLIT1 (0x0002) /* Deglitch time */
\r
14067 //#define UCGLIT_0 (0x0000) /* 50 ns */
\r
14068 //#define UCGLIT_1 (0x0001) /* 25 ns */
\r
14069 //#define UCGLIT_2 (0x0002) /* 12.5 ns */
\r
14070 //#define UCGLIT_3 (0x0003) /* 6.25 ns */
\r
14071 /* UCB3CTLW1[UCASTP] Bits */
\r
14072 //#define UCASTP_OFS ( 2) /* UCASTP Offset */
\r
14073 //#define UCASTP_M (0x000c) /* Automatic STOP condition generation */
\r
14074 //#define UCASTP0 (0x0004) /* Automatic STOP condition generation */
\r
14075 //#define UCASTP1 (0x0008) /* Automatic STOP condition generation */
\r
14076 //#define UCASTP_0 (0x0000) /* No automatic STOP generation. The STOP condition is generated after the user sets the UCTXSTP bit. The value in UCBxTBCNT is a don't care. */
\r
14077 //#define UCASTP_1 (0x0004) /* UCBCNTIFG is set with the byte counter reaches the threshold defined in UCBxTBCNT */
\r
14078 //#define UCASTP_2 (0x0008) /* A STOP condition is generated automatically after the byte counter value reached UCBxTBCNT. UCBCNTIFG is set with the byte counter reaching the threshold */
\r
14079 /* UCB3CTLW1[UCSWACK] Bits */
\r
14080 //#define UCSWACK_OFS ( 4) /* UCSWACK Offset */
\r
14081 //#define UCSWACK (0x0010) /* SW or HW ACK control */
\r
14082 /* UCB3CTLW1[UCSTPNACK] Bits */
\r
14083 //#define UCSTPNACK_OFS ( 5) /* UCSTPNACK Offset */
\r
14084 //#define UCSTPNACK (0x0020) /* ACK all master bytes */
\r
14085 /* UCB3CTLW1[UCCLTO] Bits */
\r
14086 //#define UCCLTO_OFS ( 6) /* UCCLTO Offset */
\r
14087 //#define UCCLTO_M (0x00c0) /* Clock low timeout select */
\r
14088 //#define UCCLTO0 (0x0040) /* Clock low timeout select */
\r
14089 //#define UCCLTO1 (0x0080) /* Clock low timeout select */
\r
14090 //#define UCCLTO_0 (0x0000) /* Disable clock low timeout counter */
\r
14091 //#define UCCLTO_1 (0x0040) /* 135 000 SYSCLK cycles (approximately 28 ms) */
\r
14092 //#define UCCLTO_2 (0x0080) /* 150 000 SYSCLK cycles (approximately 31 ms) */
\r
14093 //#define UCCLTO_3 (0x00c0) /* 165 000 SYSCLK cycles (approximately 34 ms) */
\r
14094 /* UCB3CTLW1[UCETXINT] Bits */
\r
14095 //#define UCETXINT_OFS ( 8) /* UCETXINT Offset */
\r
14096 //#define UCETXINT (0x0100) /* Early UCTXIFG0 */
\r
14097 /* UCB3STATW[UCBBUSY] Bits */
\r
14098 //#define UCBBUSY_OFS ( 4) /* UCBBUSY Offset */
\r
14099 //#define UCBBUSY (0x0010) /* Bus busy */
\r
14100 /* UCB3STATW[UCGC] Bits */
\r
14101 //#define UCGC_OFS ( 5) /* UCGC Offset */
\r
14102 //#define UCGC (0x0020) /* General call address received */
\r
14103 /* UCB3STATW[UCSCLLOW] Bits */
\r
14104 //#define UCSCLLOW_OFS ( 6) /* UCSCLLOW Offset */
\r
14105 //#define UCSCLLOW (0x0040) /* SCL low */
\r
14106 /* UCB3STATW[UCBCNT] Bits */
\r
14107 //#define UCBCNT_OFS ( 8) /* UCBCNT Offset */
\r
14108 //#define UCBCNT_M (0xff00) /* Hardware byte counter value */
\r
14109 /* UCB3STATW_SPI[UCBUSY] Bits */
\r
14110 //#define UCBUSY_OFS ( 0) /* UCBUSY Offset */
\r
14111 //#define UCBUSY (0x0001) /* eUSCI_B busy */
\r
14112 /* UCB3STATW_SPI[UCOE] Bits */
\r
14113 //#define UCOE_OFS ( 5) /* UCOE Offset */
\r
14114 //#define UCOE (0x0020) /* Overrun error flag */
\r
14115 /* UCB3STATW_SPI[UCFE] Bits */
\r
14116 //#define UCFE_OFS ( 6) /* UCFE Offset */
\r
14117 //#define UCFE (0x0040) /* Framing error flag */
\r
14118 /* UCB3STATW_SPI[UCLISTEN] Bits */
\r
14119 //#define UCLISTEN_OFS ( 7) /* UCLISTEN Offset */
\r
14120 //#define UCLISTEN (0x0080) /* Listen enable */
\r
14121 /* UCB3TBCNT[UCTBCNT] Bits */
\r
14122 //#define UCTBCNT_OFS ( 0) /* UCTBCNT Offset */
\r
14123 //#define UCTBCNT_M (0x00ff) /* Byte counter threshold value */
\r
14124 /* UCB3RXBUF[UCRXBUF] Bits */
\r
14125 //#define UCRXBUF_OFS ( 0) /* UCRXBUF Offset */
\r
14126 //#define UCRXBUF_M (0x00ff) /* Receive data buffer */
\r
14127 /* UCB3RXBUF_SPI[UCRXBUF] Bits */
\r
14128 //#define UCRXBUF_OFS ( 0) /* UCRXBUF Offset */
\r
14129 //#define UCRXBUF_M (0x00ff) /* Receive data buffer */
\r
14130 /* UCB3TXBUF[UCTXBUF] Bits */
\r
14131 //#define UCTXBUF_OFS ( 0) /* UCTXBUF Offset */
\r
14132 //#define UCTXBUF_M (0x00ff) /* Transmit data buffer */
\r
14133 /* UCB3TXBUF_SPI[UCTXBUF] Bits */
\r
14134 //#define UCTXBUF_OFS ( 0) /* UCTXBUF Offset */
\r
14135 //#define UCTXBUF_M (0x00ff) /* Transmit data buffer */
\r
14136 /* UCB3I2COA0[I2COA0] Bits */
\r
14137 //#define I2COA0_OFS ( 0) /* I2COA0 Offset */
\r
14138 //#define I2COA0_M (0x03ff) /* I2C own address */
\r
14139 /* UCB3I2COA0[UCOAEN] Bits */
\r
14140 //#define UCOAEN_OFS (10) /* UCOAEN Offset */
\r
14141 //#define UCOAEN (0x0400) /* Own Address enable register */
\r
14142 /* UCB3I2COA0[UCGCEN] Bits */
\r
14143 //#define UCGCEN_OFS (15) /* UCGCEN Offset */
\r
14144 //#define UCGCEN (0x8000) /* General call response enable */
\r
14145 /* UCB3I2COA1[I2COA1] Bits */
\r
14146 //#define I2COA1_OFS ( 0) /* I2COA1 Offset */
\r
14147 //#define I2COA1_M (0x03ff) /* I2C own address */
\r
14148 /* UCB3I2COA1[UCOAEN] Bits */
\r
14149 //#define UCOAEN_OFS (10) /* UCOAEN Offset */
\r
14150 //#define UCOAEN (0x0400) /* Own Address enable register */
\r
14151 /* UCB3I2COA2[I2COA2] Bits */
\r
14152 //#define I2COA2_OFS ( 0) /* I2COA2 Offset */
\r
14153 //#define I2COA2_M (0x03ff) /* I2C own address */
\r
14154 /* UCB3I2COA2[UCOAEN] Bits */
\r
14155 //#define UCOAEN_OFS (10) /* UCOAEN Offset */
\r
14156 //#define UCOAEN (0x0400) /* Own Address enable register */
\r
14157 /* UCB3I2COA3[I2COA3] Bits */
\r
14158 //#define I2COA3_OFS ( 0) /* I2COA3 Offset */
\r
14159 //#define I2COA3_M (0x03ff) /* I2C own address */
\r
14160 /* UCB3I2COA3[UCOAEN] Bits */
\r
14161 //#define UCOAEN_OFS (10) /* UCOAEN Offset */
\r
14162 //#define UCOAEN (0x0400) /* Own Address enable register */
\r
14163 /* UCB3ADDRX[ADDRX] Bits */
\r
14164 //#define ADDRX_OFS ( 0) /* ADDRX Offset */
\r
14165 //#define ADDRX_M (0x03ff) /* Received Address Register */
\r
14166 /* UCB3ADDMASK[ADDMASK] Bits */
\r
14167 //#define ADDMASK_OFS ( 0) /* ADDMASK Offset */
\r
14168 //#define ADDMASK_M (0x03ff) /* */
\r
14169 /* UCB3I2CSA[I2CSA] Bits */
\r
14170 //#define I2CSA_OFS ( 0) /* I2CSA Offset */
\r
14171 //#define I2CSA_M (0x03ff) /* I2C slave address */
\r
14172 /* UCB3IE[UCRXIE0] Bits */
\r
14173 //#define UCRXIE0_OFS ( 0) /* UCRXIE0 Offset */
\r
14174 //#define UCRXIE0 (0x0001) /* Receive interrupt enable 0 */
\r
14175 /* UCB3IE[UCTXIE0] Bits */
\r
14176 //#define UCTXIE0_OFS ( 1) /* UCTXIE0 Offset */
\r
14177 //#define UCTXIE0 (0x0002) /* Transmit interrupt enable 0 */
\r
14178 /* UCB3IE[UCSTTIE] Bits */
\r
14179 //#define UCSTTIE_OFS ( 2) /* UCSTTIE Offset */
\r
14180 //#define UCSTTIE (0x0004) /* START condition interrupt enable */
\r
14181 /* UCB3IE[UCSTPIE] Bits */
\r
14182 //#define UCSTPIE_OFS ( 3) /* UCSTPIE Offset */
\r
14183 //#define UCSTPIE (0x0008) /* STOP condition interrupt enable */
\r
14184 /* UCB3IE[UCALIE] Bits */
\r
14185 //#define UCALIE_OFS ( 4) /* UCALIE Offset */
\r
14186 //#define UCALIE (0x0010) /* Arbitration lost interrupt enable */
\r
14187 /* UCB3IE[UCNACKIE] Bits */
\r
14188 //#define UCNACKIE_OFS ( 5) /* UCNACKIE Offset */
\r
14189 //#define UCNACKIE (0x0020) /* Not-acknowledge interrupt enable */
\r
14190 /* UCB3IE[UCBCNTIE] Bits */
\r
14191 //#define UCBCNTIE_OFS ( 6) /* UCBCNTIE Offset */
\r
14192 //#define UCBCNTIE (0x0040) /* Byte counter interrupt enable */
\r
14193 /* UCB3IE[UCCLTOIE] Bits */
\r
14194 //#define UCCLTOIE_OFS ( 7) /* UCCLTOIE Offset */
\r
14195 //#define UCCLTOIE (0x0080) /* Clock low timeout interrupt enable */
\r
14196 /* UCB3IE[UCRXIE1] Bits */
\r
14197 //#define UCRXIE1_OFS ( 8) /* UCRXIE1 Offset */
\r
14198 //#define UCRXIE1 (0x0100) /* Receive interrupt enable 1 */
\r
14199 /* UCB3IE[UCTXIE1] Bits */
\r
14200 //#define UCTXIE1_OFS ( 9) /* UCTXIE1 Offset */
\r
14201 //#define UCTXIE1 (0x0200) /* Transmit interrupt enable 1 */
\r
14202 /* UCB3IE[UCRXIE2] Bits */
\r
14203 //#define UCRXIE2_OFS (10) /* UCRXIE2 Offset */
\r
14204 //#define UCRXIE2 (0x0400) /* Receive interrupt enable 2 */
\r
14205 /* UCB3IE[UCTXIE2] Bits */
\r
14206 //#define UCTXIE2_OFS (11) /* UCTXIE2 Offset */
\r
14207 //#define UCTXIE2 (0x0800) /* Transmit interrupt enable 2 */
\r
14208 /* UCB3IE[UCRXIE3] Bits */
\r
14209 //#define UCRXIE3_OFS (12) /* UCRXIE3 Offset */
\r
14210 //#define UCRXIE3 (0x1000) /* Receive interrupt enable 3 */
\r
14211 /* UCB3IE[UCTXIE3] Bits */
\r
14212 //#define UCTXIE3_OFS (13) /* UCTXIE3 Offset */
\r
14213 //#define UCTXIE3 (0x2000) /* Transmit interrupt enable 3 */
\r
14214 /* UCB3IE[UCBIT9IE] Bits */
\r
14215 //#define UCBIT9IE_OFS (14) /* UCBIT9IE Offset */
\r
14216 //#define UCBIT9IE (0x4000) /* Bit position 9 interrupt enable */
\r
14217 /* UCB3IE_SPI[UCRXIE] Bits */
\r
14218 //#define UCRXIE_OFS ( 0) /* UCRXIE Offset */
\r
14219 //#define UCRXIE (0x0001) /* Receive interrupt enable */
\r
14220 /* UCB3IE_SPI[UCTXIE] Bits */
\r
14221 //#define UCTXIE_OFS ( 1) /* UCTXIE Offset */
\r
14222 //#define UCTXIE (0x0002) /* Transmit interrupt enable */
\r
14223 /* UCB3IFG[UCRXIFG0] Bits */
\r
14224 //#define UCRXIFG0_OFS ( 0) /* UCRXIFG0 Offset */
\r
14225 //#define UCRXIFG0 (0x0001) /* eUSCI_B receive interrupt flag 0 */
\r
14226 /* UCB3IFG[UCTXIFG0] Bits */
\r
14227 //#define UCTXIFG0_OFS ( 1) /* UCTXIFG0 Offset */
\r
14228 //#define UCTXIFG0 (0x0002) /* eUSCI_B transmit interrupt flag 0 */
\r
14229 /* UCB3IFG[UCSTTIFG] Bits */
\r
14230 //#define UCSTTIFG_OFS ( 2) /* UCSTTIFG Offset */
\r
14231 //#define UCSTTIFG (0x0004) /* START condition interrupt flag */
\r
14232 /* UCB3IFG[UCSTPIFG] Bits */
\r
14233 //#define UCSTPIFG_OFS ( 3) /* UCSTPIFG Offset */
\r
14234 //#define UCSTPIFG (0x0008) /* STOP condition interrupt flag */
\r
14235 /* UCB3IFG[UCALIFG] Bits */
\r
14236 //#define UCALIFG_OFS ( 4) /* UCALIFG Offset */
\r
14237 //#define UCALIFG (0x0010) /* Arbitration lost interrupt flag */
\r
14238 /* UCB3IFG[UCNACKIFG] Bits */
\r
14239 //#define UCNACKIFG_OFS ( 5) /* UCNACKIFG Offset */
\r
14240 //#define UCNACKIFG (0x0020) /* Not-acknowledge received interrupt flag */
\r
14241 /* UCB3IFG[UCBCNTIFG] Bits */
\r
14242 //#define UCBCNTIFG_OFS ( 6) /* UCBCNTIFG Offset */
\r
14243 //#define UCBCNTIFG (0x0040) /* Byte counter interrupt flag */
\r
14244 /* UCB3IFG[UCCLTOIFG] Bits */
\r
14245 //#define UCCLTOIFG_OFS ( 7) /* UCCLTOIFG Offset */
\r
14246 //#define UCCLTOIFG (0x0080) /* Clock low timeout interrupt flag */
\r
14247 /* UCB3IFG[UCRXIFG1] Bits */
\r
14248 //#define UCRXIFG1_OFS ( 8) /* UCRXIFG1 Offset */
\r
14249 //#define UCRXIFG1 (0x0100) /* eUSCI_B receive interrupt flag 1 */
\r
14250 /* UCB3IFG[UCTXIFG1] Bits */
\r
14251 //#define UCTXIFG1_OFS ( 9) /* UCTXIFG1 Offset */
\r
14252 //#define UCTXIFG1 (0x0200) /* eUSCI_B transmit interrupt flag 1 */
\r
14253 /* UCB3IFG[UCRXIFG2] Bits */
\r
14254 //#define UCRXIFG2_OFS (10) /* UCRXIFG2 Offset */
\r
14255 //#define UCRXIFG2 (0x0400) /* eUSCI_B receive interrupt flag 2 */
\r
14256 /* UCB3IFG[UCTXIFG2] Bits */
\r
14257 //#define UCTXIFG2_OFS (11) /* UCTXIFG2 Offset */
\r
14258 //#define UCTXIFG2 (0x0800) /* eUSCI_B transmit interrupt flag 2 */
\r
14259 /* UCB3IFG[UCRXIFG3] Bits */
\r
14260 //#define UCRXIFG3_OFS (12) /* UCRXIFG3 Offset */
\r
14261 //#define UCRXIFG3 (0x1000) /* eUSCI_B receive interrupt flag 3 */
\r
14262 /* UCB3IFG[UCTXIFG3] Bits */
\r
14263 //#define UCTXIFG3_OFS (13) /* UCTXIFG3 Offset */
\r
14264 //#define UCTXIFG3 (0x2000) /* eUSCI_B transmit interrupt flag 3 */
\r
14265 /* UCB3IFG[UCBIT9IFG] Bits */
\r
14266 //#define UCBIT9IFG_OFS (14) /* UCBIT9IFG Offset */
\r
14267 //#define UCBIT9IFG (0x4000) /* Bit position 9 interrupt flag */
\r
14268 /* UCB3IFG_SPI[UCRXIFG] Bits */
\r
14269 //#define UCRXIFG_OFS ( 0) /* UCRXIFG Offset */
\r
14270 //#define UCRXIFG (0x0001) /* Receive interrupt flag */
\r
14271 /* UCB3IFG_SPI[UCTXIFG] Bits */
\r
14272 //#define UCTXIFG_OFS ( 1) /* UCTXIFG Offset */
\r
14273 //#define UCTXIFG (0x0002) /* Transmit interrupt flag */
\r
14276 //*****************************************************************************
\r
14278 //*****************************************************************************
\r
14279 /* FLCTL_POWER_STAT[FLCTL_POWER_STAT_PSTAT] Bits */
\r
14280 #define FLCTL_POWER_STAT_PSTAT_OFS ( 0) /* PSTAT Offset */
\r
14281 #define FLCTL_POWER_STAT_PSTAT_M (0x00000007) /* */
\r
14282 #define FLCTL_POWER_STAT_PSTAT0 (0x00000001) /* */
\r
14283 #define FLCTL_POWER_STAT_PSTAT1 (0x00000002) /* */
\r
14284 #define FLCTL_POWER_STAT_PSTAT2 (0x00000004) /* */
\r
14285 #define FLCTL_POWER_STAT_PSTAT_0 (0x00000000) /* Flash IP in power-down mode */
\r
14286 #define FLCTL_POWER_STAT_PSTAT_1 (0x00000001) /* Flash IP Vdd domain power-up in progress */
\r
14287 #define FLCTL_POWER_STAT_PSTAT_2 (0x00000002) /* PSS LDO_GOOD, IREF_OK and VREF_OK check in progress */
\r
14288 #define FLCTL_POWER_STAT_PSTAT_3 (0x00000003) /* Flash IP SAFE_LV check in progress */
\r
14289 #define FLCTL_POWER_STAT_PSTAT_4 (0x00000004) /* Flash IP Active */
\r
14290 #define FLCTL_POWER_STAT_PSTAT_5 (0x00000005) /* Flash IP Active in Low-Frequency Active and Low-Frequency LPM0 modes. */
\r
14291 #define FLCTL_POWER_STAT_PSTAT_6 (0x00000006) /* Flash IP in Standby mode */
\r
14292 #define FLCTL_POWER_STAT_PSTAT_7 (0x00000007) /* Flash IP in Current mirror boost state */
\r
14293 /* FLCTL_POWER_STAT[FLCTL_POWER_STAT_LDOSTAT] Bits */
\r
14294 #define FLCTL_POWER_STAT_LDOSTAT_OFS ( 3) /* LDOSTAT Offset */
\r
14295 #define FLCTL_POWER_STAT_LDOSTAT (0x00000008) /* PSS FLDO GOOD status */
\r
14296 /* FLCTL_POWER_STAT[FLCTL_POWER_STAT_VREFSTAT] Bits */
\r
14297 #define FLCTL_POWER_STAT_VREFSTAT_OFS ( 4) /* VREFSTAT Offset */
\r
14298 #define FLCTL_POWER_STAT_VREFSTAT (0x00000010) /* PSS VREF stable status */
\r
14299 /* FLCTL_POWER_STAT[FLCTL_POWER_STAT_IREFSTAT] Bits */
\r
14300 #define FLCTL_POWER_STAT_IREFSTAT_OFS ( 5) /* IREFSTAT Offset */
\r
14301 #define FLCTL_POWER_STAT_IREFSTAT (0x00000020) /* PSS IREF stable status */
\r
14302 /* FLCTL_POWER_STAT[FLCTL_POWER_STAT_TRIMSTAT] Bits */
\r
14303 #define FLCTL_POWER_STAT_TRIMSTAT_OFS ( 6) /* TRIMSTAT Offset */
\r
14304 #define FLCTL_POWER_STAT_TRIMSTAT (0x00000040) /* PSS trim done status */
\r
14305 /* FLCTL_POWER_STAT[FLCTL_POWER_STAT_RD_2T] Bits */
\r
14306 #define FLCTL_POWER_STAT_RD_2T_OFS ( 7) /* RD_2T Offset */
\r
14307 #define FLCTL_POWER_STAT_RD_2T (0x00000080) /* Indicates if Flash is being accessed in 2T mode */
\r
14308 /* FLCTL_BANK0_RDCTL[FLCTL_BANK0_RDCTL_RD_MODE] Bits */
\r
14309 #define FLCTL_BANK0_RDCTL_RD_MODE_OFS ( 0) /* RD_MODE Offset */
\r
14310 #define FLCTL_BANK0_RDCTL_RD_MODE_M (0x0000000f) /* Flash read mode control setting for Bank 0 */
\r
14311 #define FLCTL_BANK0_RDCTL_RD_MODE0 (0x00000001) /* Flash read mode control setting for Bank 0 */
\r
14312 #define FLCTL_BANK0_RDCTL_RD_MODE1 (0x00000002) /* Flash read mode control setting for Bank 0 */
\r
14313 #define FLCTL_BANK0_RDCTL_RD_MODE2 (0x00000004) /* Flash read mode control setting for Bank 0 */
\r
14314 #define FLCTL_BANK0_RDCTL_RD_MODE3 (0x00000008) /* Flash read mode control setting for Bank 0 */
\r
14315 #define FLCTL_BANK0_RDCTL_RD_MODE_0 (0x00000000) /* Normal read mode */
\r
14316 #define FLCTL_BANK0_RDCTL_RD_MODE_1 (0x00000001) /* Read Margin 0 */
\r
14317 #define FLCTL_BANK0_RDCTL_RD_MODE_2 (0x00000002) /* Read Margin 1 */
\r
14318 #define FLCTL_BANK0_RDCTL_RD_MODE_3 (0x00000003) /* Program Verify */
\r
14319 #define FLCTL_BANK0_RDCTL_RD_MODE_4 (0x00000004) /* Erase Verify */
\r
14320 #define FLCTL_BANK0_RDCTL_RD_MODE_5 (0x00000005) /* Leakage Verify */
\r
14321 #define FLCTL_BANK0_RDCTL_RD_MODE_9 (0x00000009) /* Read Margin 0B */
\r
14322 #define FLCTL_BANK0_RDCTL_RD_MODE_10 (0x0000000a) /* Read Margin 1B */
\r
14323 /* FLCTL_BANK0_RDCTL[FLCTL_BANK0_RDCTL_BUFI] Bits */
\r
14324 #define FLCTL_BANK0_RDCTL_BUFI_OFS ( 4) /* BUFI Offset */
\r
14325 #define FLCTL_BANK0_RDCTL_BUFI (0x00000010) /* Enables read buffering feature for instruction fetches to this Bank */
\r
14326 /* FLCTL_BANK0_RDCTL[FLCTL_BANK0_RDCTL_BUFD] Bits */
\r
14327 #define FLCTL_BANK0_RDCTL_BUFD_OFS ( 5) /* BUFD Offset */
\r
14328 #define FLCTL_BANK0_RDCTL_BUFD (0x00000020) /* Enables read buffering feature for data reads to this Bank */
\r
14329 /* FLCTL_BANK0_RDCTL[FLCTL_BANK0_RDCTL_WAIT] Bits */
\r
14330 #define FLCTL_BANK0_RDCTL_WAIT_OFS (12) /* WAIT Offset */
\r
14331 #define FLCTL_BANK0_RDCTL_WAIT_M (0x0000f000) /* Number of wait states for read */
\r
14332 #define FLCTL_BANK0_RDCTL_WAIT0 (0x00001000) /* Number of wait states for read */
\r
14333 #define FLCTL_BANK0_RDCTL_WAIT1 (0x00002000) /* Number of wait states for read */
\r
14334 #define FLCTL_BANK0_RDCTL_WAIT2 (0x00004000) /* Number of wait states for read */
\r
14335 #define FLCTL_BANK0_RDCTL_WAIT3 (0x00008000) /* Number of wait states for read */
\r
14336 #define FLCTL_BANK0_RDCTL_WAIT_0 (0x00000000) /* 0 wait states */
\r
14337 #define FLCTL_BANK0_RDCTL_WAIT_1 (0x00001000) /* 1 wait states */
\r
14338 #define FLCTL_BANK0_RDCTL_WAIT_2 (0x00002000) /* 2 wait states */
\r
14339 #define FLCTL_BANK0_RDCTL_WAIT_3 (0x00003000) /* 3 wait states */
\r
14340 #define FLCTL_BANK0_RDCTL_WAIT_4 (0x00004000) /* 4 wait states */
\r
14341 #define FLCTL_BANK0_RDCTL_WAIT_5 (0x00005000) /* 5 wait states */
\r
14342 #define FLCTL_BANK0_RDCTL_WAIT_6 (0x00006000) /* 6 wait states */
\r
14343 #define FLCTL_BANK0_RDCTL_WAIT_7 (0x00007000) /* 7 wait states */
\r
14344 #define FLCTL_BANK0_RDCTL_WAIT_8 (0x00008000) /* 8 wait states */
\r
14345 #define FLCTL_BANK0_RDCTL_WAIT_9 (0x00009000) /* 9 wait states */
\r
14346 #define FLCTL_BANK0_RDCTL_WAIT_10 (0x0000a000) /* 10 wait states */
\r
14347 #define FLCTL_BANK0_RDCTL_WAIT_11 (0x0000b000) /* 11 wait states */
\r
14348 #define FLCTL_BANK0_RDCTL_WAIT_12 (0x0000c000) /* 12 wait states */
\r
14349 #define FLCTL_BANK0_RDCTL_WAIT_13 (0x0000d000) /* 13 wait states */
\r
14350 #define FLCTL_BANK0_RDCTL_WAIT_14 (0x0000e000) /* 14 wait states */
\r
14351 #define FLCTL_BANK0_RDCTL_WAIT_15 (0x0000f000) /* 15 wait states */
\r
14352 /* FLCTL_BANK0_RDCTL[FLCTL_BANK0_RDCTL_RD_MODE_STATUS] Bits */
\r
14353 #define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_OFS (16) /* RD_MODE_STATUS Offset */
\r
14354 #define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_M (0x000f0000) /* Read mode */
\r
14355 #define FLCTL_BANK0_RDCTL_RD_MODE_STATUS0 (0x00010000) /* Read mode */
\r
14356 #define FLCTL_BANK0_RDCTL_RD_MODE_STATUS1 (0x00020000) /* Read mode */
\r
14357 #define FLCTL_BANK0_RDCTL_RD_MODE_STATUS2 (0x00040000) /* Read mode */
\r
14358 #define FLCTL_BANK0_RDCTL_RD_MODE_STATUS3 (0x00080000) /* Read mode */
\r
14359 #define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_0 (0x00000000) /* Normal read mode */
\r
14360 #define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_1 (0x00010000) /* Read Margin 0 */
\r
14361 #define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_2 (0x00020000) /* Read Margin 1 */
\r
14362 #define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_3 (0x00030000) /* Program Verify */
\r
14363 #define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_4 (0x00040000) /* Erase Verify */
\r
14364 #define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_5 (0x00050000) /* Leakage Verify */
\r
14365 #define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_9 (0x00090000) /* Read Margin 0B */
\r
14366 #define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_10 (0x000a0000) /* Read Margin 1B */
\r
14367 /* FLCTL_BANK1_RDCTL[FLCTL_BANK1_RDCTL_RD_MODE] Bits */
\r
14368 #define FLCTL_BANK1_RDCTL_RD_MODE_OFS ( 0) /* RD_MODE Offset */
\r
14369 #define FLCTL_BANK1_RDCTL_RD_MODE_M (0x0000000f) /* Flash read mode control setting for Bank 0 */
\r
14370 #define FLCTL_BANK1_RDCTL_RD_MODE0 (0x00000001) /* Flash read mode control setting for Bank 0 */
\r
14371 #define FLCTL_BANK1_RDCTL_RD_MODE1 (0x00000002) /* Flash read mode control setting for Bank 0 */
\r
14372 #define FLCTL_BANK1_RDCTL_RD_MODE2 (0x00000004) /* Flash read mode control setting for Bank 0 */
\r
14373 #define FLCTL_BANK1_RDCTL_RD_MODE3 (0x00000008) /* Flash read mode control setting for Bank 0 */
\r
14374 #define FLCTL_BANK1_RDCTL_RD_MODE_0 (0x00000000) /* Normal read mode */
\r
14375 #define FLCTL_BANK1_RDCTL_RD_MODE_1 (0x00000001) /* Read Margin 0 */
\r
14376 #define FLCTL_BANK1_RDCTL_RD_MODE_2 (0x00000002) /* Read Margin 1 */
\r
14377 #define FLCTL_BANK1_RDCTL_RD_MODE_3 (0x00000003) /* Program Verify */
\r
14378 #define FLCTL_BANK1_RDCTL_RD_MODE_4 (0x00000004) /* Erase Verify */
\r
14379 #define FLCTL_BANK1_RDCTL_RD_MODE_5 (0x00000005) /* Leakage Verify */
\r
14380 #define FLCTL_BANK1_RDCTL_RD_MODE_9 (0x00000009) /* Read Margin 0B */
\r
14381 #define FLCTL_BANK1_RDCTL_RD_MODE_10 (0x0000000a) /* Read Margin 1B */
\r
14382 /* FLCTL_BANK1_RDCTL[FLCTL_BANK1_RDCTL_BUFI] Bits */
\r
14383 #define FLCTL_BANK1_RDCTL_BUFI_OFS ( 4) /* BUFI Offset */
\r
14384 #define FLCTL_BANK1_RDCTL_BUFI (0x00000010) /* Enables read buffering feature for instruction fetches to this Bank */
\r
14385 /* FLCTL_BANK1_RDCTL[FLCTL_BANK1_RDCTL_BUFD] Bits */
\r
14386 #define FLCTL_BANK1_RDCTL_BUFD_OFS ( 5) /* BUFD Offset */
\r
14387 #define FLCTL_BANK1_RDCTL_BUFD (0x00000020) /* Enables read buffering feature for data reads to this Bank */
\r
14388 /* FLCTL_BANK1_RDCTL[FLCTL_BANK1_RDCTL_RD_MODE_STATUS] Bits */
\r
14389 #define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_OFS (16) /* RD_MODE_STATUS Offset */
\r
14390 #define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_M (0x000f0000) /* Read mode */
\r
14391 #define FLCTL_BANK1_RDCTL_RD_MODE_STATUS0 (0x00010000) /* Read mode */
\r
14392 #define FLCTL_BANK1_RDCTL_RD_MODE_STATUS1 (0x00020000) /* Read mode */
\r
14393 #define FLCTL_BANK1_RDCTL_RD_MODE_STATUS2 (0x00040000) /* Read mode */
\r
14394 #define FLCTL_BANK1_RDCTL_RD_MODE_STATUS3 (0x00080000) /* Read mode */
\r
14395 #define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_0 (0x00000000) /* Normal read mode */
\r
14396 #define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_1 (0x00010000) /* Read Margin 0 */
\r
14397 #define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_2 (0x00020000) /* Read Margin 1 */
\r
14398 #define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_3 (0x00030000) /* Program Verify */
\r
14399 #define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_4 (0x00040000) /* Erase Verify */
\r
14400 #define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_5 (0x00050000) /* Leakage Verify */
\r
14401 #define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_9 (0x00090000) /* Read Margin 0B */
\r
14402 #define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_10 (0x000a0000) /* Read Margin 1B */
\r
14403 /* FLCTL_BANK1_RDCTL[FLCTL_BANK1_RDCTL_WAIT] Bits */
\r
14404 #define FLCTL_BANK1_RDCTL_WAIT_OFS (12) /* WAIT Offset */
\r
14405 #define FLCTL_BANK1_RDCTL_WAIT_M (0x0000f000) /* Number of wait states for read */
\r
14406 #define FLCTL_BANK1_RDCTL_WAIT0 (0x00001000) /* Number of wait states for read */
\r
14407 #define FLCTL_BANK1_RDCTL_WAIT1 (0x00002000) /* Number of wait states for read */
\r
14408 #define FLCTL_BANK1_RDCTL_WAIT2 (0x00004000) /* Number of wait states for read */
\r
14409 #define FLCTL_BANK1_RDCTL_WAIT3 (0x00008000) /* Number of wait states for read */
\r
14410 #define FLCTL_BANK1_RDCTL_WAIT_0 (0x00000000) /* 0 wait states */
\r
14411 #define FLCTL_BANK1_RDCTL_WAIT_1 (0x00001000) /* 1 wait states */
\r
14412 #define FLCTL_BANK1_RDCTL_WAIT_2 (0x00002000) /* 2 wait states */
\r
14413 #define FLCTL_BANK1_RDCTL_WAIT_3 (0x00003000) /* 3 wait states */
\r
14414 #define FLCTL_BANK1_RDCTL_WAIT_4 (0x00004000) /* 4 wait states */
\r
14415 #define FLCTL_BANK1_RDCTL_WAIT_5 (0x00005000) /* 5 wait states */
\r
14416 #define FLCTL_BANK1_RDCTL_WAIT_6 (0x00006000) /* 6 wait states */
\r
14417 #define FLCTL_BANK1_RDCTL_WAIT_7 (0x00007000) /* 7 wait states */
\r
14418 #define FLCTL_BANK1_RDCTL_WAIT_8 (0x00008000) /* 8 wait states */
\r
14419 #define FLCTL_BANK1_RDCTL_WAIT_9 (0x00009000) /* 9 wait states */
\r
14420 #define FLCTL_BANK1_RDCTL_WAIT_10 (0x0000a000) /* 10 wait states */
\r
14421 #define FLCTL_BANK1_RDCTL_WAIT_11 (0x0000b000) /* 11 wait states */
\r
14422 #define FLCTL_BANK1_RDCTL_WAIT_12 (0x0000c000) /* 12 wait states */
\r
14423 #define FLCTL_BANK1_RDCTL_WAIT_13 (0x0000d000) /* 13 wait states */
\r
14424 #define FLCTL_BANK1_RDCTL_WAIT_14 (0x0000e000) /* 14 wait states */
\r
14425 #define FLCTL_BANK1_RDCTL_WAIT_15 (0x0000f000) /* 15 wait states */
\r
14426 /* FLCTL_RDBRST_CTLSTAT[FLCTL_RDBRST_CTLSTAT_START] Bits */
\r
14427 #define FLCTL_RDBRST_CTLSTAT_START_OFS ( 0) /* START Offset */
\r
14428 #define FLCTL_RDBRST_CTLSTAT_START (0x00000001) /* Start of burst/compare operation */
\r
14429 /* FLCTL_RDBRST_CTLSTAT[FLCTL_RDBRST_CTLSTAT_MEM_TYPE] Bits */
\r
14430 #define FLCTL_RDBRST_CTLSTAT_MEM_TYPE_OFS ( 1) /* MEM_TYPE Offset */
\r
14431 #define FLCTL_RDBRST_CTLSTAT_MEM_TYPE_M (0x00000006) /* Type of memory that burst is carried out on */
\r
14432 #define FLCTL_RDBRST_CTLSTAT_MEM_TYPE0 (0x00000002) /* Type of memory that burst is carried out on */
\r
14433 #define FLCTL_RDBRST_CTLSTAT_MEM_TYPE1 (0x00000004) /* Type of memory that burst is carried out on */
\r
14434 #define FLCTL_RDBRST_CTLSTAT_MEM_TYPE_0 (0x00000000) /* Main Memory */
\r
14435 #define FLCTL_RDBRST_CTLSTAT_MEM_TYPE_1 (0x00000002) /* Information Memory */
\r
14436 #define FLCTL_RDBRST_CTLSTAT_MEM_TYPE_2 (0x00000004) /* Reserved */
\r
14437 #define FLCTL_RDBRST_CTLSTAT_MEM_TYPE_3 (0x00000006) /* Engineering Memory */
\r
14438 /* FLCTL_RDBRST_CTLSTAT[FLCTL_RDBRST_CTLSTAT_STOP_FAIL] Bits */
\r
14439 #define FLCTL_RDBRST_CTLSTAT_STOP_FAIL_OFS ( 3) /* STOP_FAIL Offset */
\r
14440 #define FLCTL_RDBRST_CTLSTAT_STOP_FAIL (0x00000008) /* Terminate burst/compare operation */
\r
14441 /* FLCTL_RDBRST_CTLSTAT[FLCTL_RDBRST_CTLSTAT_DATA_CMP] Bits */
\r
14442 #define FLCTL_RDBRST_CTLSTAT_DATA_CMP_OFS ( 4) /* DATA_CMP Offset */
\r
14443 #define FLCTL_RDBRST_CTLSTAT_DATA_CMP (0x00000010) /* Data pattern used for comparison against memory read data */
\r
14444 /* FLCTL_RDBRST_CTLSTAT[FLCTL_RDBRST_CTLSTAT_TEST_EN] Bits */
\r
14445 #define FLCTL_RDBRST_CTLSTAT_TEST_EN_OFS ( 6) /* TEST_EN Offset */
\r
14446 #define FLCTL_RDBRST_CTLSTAT_TEST_EN (0x00000040) /* Enable comparison against test data compare registers */
\r
14447 /* FLCTL_RDBRST_CTLSTAT[FLCTL_RDBRST_CTLSTAT_BRST_STAT] Bits */
\r
14448 #define FLCTL_RDBRST_CTLSTAT_BRST_STAT_OFS (16) /* BRST_STAT Offset */
\r
14449 #define FLCTL_RDBRST_CTLSTAT_BRST_STAT_M (0x00030000) /* Status of Burst/Compare operation */
\r
14450 #define FLCTL_RDBRST_CTLSTAT_BRST_STAT0 (0x00010000) /* Status of Burst/Compare operation */
\r
14451 #define FLCTL_RDBRST_CTLSTAT_BRST_STAT1 (0x00020000) /* Status of Burst/Compare operation */
\r
14452 #define FLCTL_RDBRST_CTLSTAT_BRST_STAT_0 (0x00000000) /* Idle */
\r
14453 #define FLCTL_RDBRST_CTLSTAT_BRST_STAT_1 (0x00010000) /* Burst/Compare START bit written, but operation pending */
\r
14454 #define FLCTL_RDBRST_CTLSTAT_BRST_STAT_2 (0x00020000) /* Burst/Compare in progress */
\r
14455 #define FLCTL_RDBRST_CTLSTAT_BRST_STAT_3 (0x00030000) /* Burst complete (status of completed burst remains in this state unless explicitly cleared by SW) */
\r
14456 /* FLCTL_RDBRST_CTLSTAT[FLCTL_RDBRST_CTLSTAT_CMP_ERR] Bits */
\r
14457 #define FLCTL_RDBRST_CTLSTAT_CMP_ERR_OFS (18) /* CMP_ERR Offset */
\r
14458 #define FLCTL_RDBRST_CTLSTAT_CMP_ERR (0x00040000) /* Burst/Compare Operation encountered atleast one data */
\r
14459 /* FLCTL_RDBRST_CTLSTAT[FLCTL_RDBRST_CTLSTAT_ADDR_ERR] Bits */
\r
14460 #define FLCTL_RDBRST_CTLSTAT_ADDR_ERR_OFS (19) /* ADDR_ERR Offset */
\r
14461 #define FLCTL_RDBRST_CTLSTAT_ADDR_ERR (0x00080000) /* Burst/Compare Operation was terminated due to access to */
\r
14462 /* FLCTL_RDBRST_CTLSTAT[FLCTL_RDBRST_CTLSTAT_CLR_STAT] Bits */
\r
14463 #define FLCTL_RDBRST_CTLSTAT_CLR_STAT_OFS (23) /* CLR_STAT Offset */
\r
14464 #define FLCTL_RDBRST_CTLSTAT_CLR_STAT (0x00800000) /* Clear status bits 19-16 of this register */
\r
14465 /* FLCTL_RDBRST_STARTADDR[FLCTL_RDBRST_STARTADDR_START_ADDRESS] Bits */
\r
14466 #define FLCTL_RDBRST_STARTADDR_START_ADDRESS_OFS ( 0) /* START_ADDRESS Offset */
\r
14467 #define FLCTL_RDBRST_STARTADDR_START_ADDRESS_M (0x001fffff) /* Start Address of Burst Operation */
\r
14468 /* FLCTL_RDBRST_LEN[FLCTL_RDBRST_LEN_BURST_LENGTH] Bits */
\r
14469 #define FLCTL_RDBRST_LEN_BURST_LENGTH_OFS ( 0) /* BURST_LENGTH Offset */
\r
14470 #define FLCTL_RDBRST_LEN_BURST_LENGTH_M (0x001fffff) /* Length of Burst Operation */
\r
14471 /* FLCTL_RDBRST_FAILADDR[FLCTL_RDBRST_FAILADDR_FAIL_ADDRESS] Bits */
\r
14472 #define FLCTL_RDBRST_FAILADDR_FAIL_ADDRESS_OFS ( 0) /* FAIL_ADDRESS Offset */
\r
14473 #define FLCTL_RDBRST_FAILADDR_FAIL_ADDRESS_M (0x001fffff) /* Reflects address of last failed compare */
\r
14474 /* FLCTL_RDBRST_FAILCNT[FLCTL_RDBRST_FAILCNT_FAIL_COUNT] Bits */
\r
14475 #define FLCTL_RDBRST_FAILCNT_FAIL_COUNT_OFS ( 0) /* FAIL_COUNT Offset */
\r
14476 #define FLCTL_RDBRST_FAILCNT_FAIL_COUNT_M (0x0001ffff) /* Number of failures encountered in burst operation */
\r
14477 /* FLCTL_PRG_CTLSTAT[FLCTL_PRG_CTLSTAT_ENABLE] Bits */
\r
14478 #define FLCTL_PRG_CTLSTAT_ENABLE_OFS ( 0) /* ENABLE Offset */
\r
14479 #define FLCTL_PRG_CTLSTAT_ENABLE (0x00000001) /* Master control for all word program operations */
\r
14480 /* FLCTL_PRG_CTLSTAT[FLCTL_PRG_CTLSTAT_MODE] Bits */
\r
14481 #define FLCTL_PRG_CTLSTAT_MODE_OFS ( 1) /* MODE Offset */
\r
14482 #define FLCTL_PRG_CTLSTAT_MODE (0x00000002) /* Write mode */
\r
14483 /* FLCTL_PRG_CTLSTAT[FLCTL_PRG_CTLSTAT_VER_PRE] Bits */
\r
14484 #define FLCTL_PRG_CTLSTAT_VER_PRE_OFS ( 2) /* VER_PRE Offset */
\r
14485 #define FLCTL_PRG_CTLSTAT_VER_PRE (0x00000004) /* Controls automatic pre program verify operations */
\r
14486 /* FLCTL_PRG_CTLSTAT[FLCTL_PRG_CTLSTAT_VER_PST] Bits */
\r
14487 #define FLCTL_PRG_CTLSTAT_VER_PST_OFS ( 3) /* VER_PST Offset */
\r
14488 #define FLCTL_PRG_CTLSTAT_VER_PST (0x00000008) /* Controls automatic post program verify operations */
\r
14489 /* FLCTL_PRG_CTLSTAT[FLCTL_PRG_CTLSTAT_STATUS] Bits */
\r
14490 #define FLCTL_PRG_CTLSTAT_STATUS_OFS (16) /* STATUS Offset */
\r
14491 #define FLCTL_PRG_CTLSTAT_STATUS_M (0x00030000) /* Status of program operations in the Flash memory */
\r
14492 #define FLCTL_PRG_CTLSTAT_STATUS0 (0x00010000) /* Status of program operations in the Flash memory */
\r
14493 #define FLCTL_PRG_CTLSTAT_STATUS1 (0x00020000) /* Status of program operations in the Flash memory */
\r
14494 #define FLCTL_PRG_CTLSTAT_STATUS_0 (0x00000000) /* Idle (no program operation currently active) */
\r
14495 #define FLCTL_PRG_CTLSTAT_STATUS_1 (0x00010000) /* Single word program operation triggered, but pending */
\r
14496 #define FLCTL_PRG_CTLSTAT_STATUS_2 (0x00020000) /* Single word program in progress */
\r
14497 #define FLCTL_PRG_CTLSTAT_STATUS_3 (0x00030000) /* Reserved (Idle) */
\r
14498 /* FLCTL_PRG_CTLSTAT[FLCTL_PRG_CTLSTAT_BNK_ACT] Bits */
\r
14499 #define FLCTL_PRG_CTLSTAT_BNK_ACT_OFS (18) /* BNK_ACT Offset */
\r
14500 #define FLCTL_PRG_CTLSTAT_BNK_ACT (0x00040000) /* Bank active */
\r
14501 /* FLCTL_PRGBRST_CTLSTAT[FLCTL_PRGBRST_CTLSTAT_START] Bits */
\r
14502 #define FLCTL_PRGBRST_CTLSTAT_START_OFS ( 0) /* START Offset */
\r
14503 #define FLCTL_PRGBRST_CTLSTAT_START (0x00000001) /* Trigger start of burst program operation */
\r
14504 /* FLCTL_PRGBRST_CTLSTAT[FLCTL_PRGBRST_CTLSTAT_TYPE] Bits */
\r
14505 #define FLCTL_PRGBRST_CTLSTAT_TYPE_OFS ( 1) /* TYPE Offset */
\r
14506 #define FLCTL_PRGBRST_CTLSTAT_TYPE_M (0x00000006) /* Type of memory that burst program is carried out on */
\r
14507 #define FLCTL_PRGBRST_CTLSTAT_TYPE0 (0x00000002) /* Type of memory that burst program is carried out on */
\r
14508 #define FLCTL_PRGBRST_CTLSTAT_TYPE1 (0x00000004) /* Type of memory that burst program is carried out on */
\r
14509 #define FLCTL_PRGBRST_CTLSTAT_TYPE_0 (0x00000000) /* Main Memory */
\r
14510 #define FLCTL_PRGBRST_CTLSTAT_TYPE_1 (0x00000002) /* Information Memory */
\r
14511 #define FLCTL_PRGBRST_CTLSTAT_TYPE_2 (0x00000004) /* Reserved */
\r
14512 #define FLCTL_PRGBRST_CTLSTAT_TYPE_3 (0x00000006) /* Engineering Memory */
\r
14513 /* FLCTL_PRGBRST_CTLSTAT[FLCTL_PRGBRST_CTLSTAT_LEN] Bits */
\r
14514 #define FLCTL_PRGBRST_CTLSTAT_LEN_OFS ( 3) /* LEN Offset */
\r
14515 #define FLCTL_PRGBRST_CTLSTAT_LEN_M (0x00000038) /* Length of burst */
\r
14516 #define FLCTL_PRGBRST_CTLSTAT_LEN0 (0x00000008) /* Length of burst */
\r
14517 #define FLCTL_PRGBRST_CTLSTAT_LEN1 (0x00000010) /* Length of burst */
\r
14518 #define FLCTL_PRGBRST_CTLSTAT_LEN2 (0x00000020) /* Length of burst */
\r
14519 #define FLCTL_PRGBRST_CTLSTAT_LEN_0 (0x00000000) /* No burst operation */
\r
14520 #define FLCTL_PRGBRST_CTLSTAT_LEN_1 (0x00000008) /* 1 word burst of 128 bits, starting with address in the FLCTL_PRGBRST_STARTADDR Register */
\r
14521 #define FLCTL_PRGBRST_CTLSTAT_LEN_2 (0x00000010) /* 2*128 bits burst write, starting with address in the FLCTL_PRGBRST_STARTADDR Register */
\r
14522 #define FLCTL_PRGBRST_CTLSTAT_LEN_3 (0x00000018) /* 3*128 bits burst write, starting with address in the FLCTL_PRGBRST_STARTADDR Register */
\r
14523 #define FLCTL_PRGBRST_CTLSTAT_LEN_4 (0x00000020) /* 4*128 bits burst write, starting with address in the FLCTL_PRGBRST_STARTADDR Register */
\r
14524 /* FLCTL_PRGBRST_CTLSTAT[FLCTL_PRGBRST_CTLSTAT_AUTO_PRE] Bits */
\r
14525 #define FLCTL_PRGBRST_CTLSTAT_AUTO_PRE_OFS ( 6) /* AUTO_PRE Offset */
\r
14526 #define FLCTL_PRGBRST_CTLSTAT_AUTO_PRE (0x00000040) /* Auto-Verify operation before the Burst Program */
\r
14527 /* FLCTL_PRGBRST_CTLSTAT[FLCTL_PRGBRST_CTLSTAT_AUTO_PST] Bits */
\r
14528 #define FLCTL_PRGBRST_CTLSTAT_AUTO_PST_OFS ( 7) /* AUTO_PST Offset */
\r
14529 #define FLCTL_PRGBRST_CTLSTAT_AUTO_PST (0x00000080) /* Auto-Verify operation after the Burst Program */
\r
14530 /* FLCTL_PRGBRST_CTLSTAT[FLCTL_PRGBRST_CTLSTAT_BURST_STATUS] Bits */
\r
14531 #define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_OFS (16) /* BURST_STATUS Offset */
\r
14532 #define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_M (0x00070000) /* Status of a Burst Operation */
\r
14533 #define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS0 (0x00010000) /* Status of a Burst Operation */
\r
14534 #define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS1 (0x00020000) /* Status of a Burst Operation */
\r
14535 #define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS2 (0x00040000) /* Status of a Burst Operation */
\r
14536 #define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_0 (0x00000000) /* Idle (Burst not active) */
\r
14537 #define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_1 (0x00010000) /* Burst program started but pending */
\r
14538 #define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_2 (0x00020000) /* Burst active, with 1st 128 bit word being written into Flash */
\r
14539 #define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_3 (0x00030000) /* Burst active, with 2nd 128 bit word being written into Flash */
\r
14540 #define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_4 (0x00040000) /* Burst active, with 3rd 128 bit word being written into Flash */
\r
14541 #define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_5 (0x00050000) /* Burst active, with 4th 128 bit word being written into Flash */
\r
14542 #define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_6 (0x00060000) /* Reserved (Idle) */
\r
14543 #define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_7 (0x00070000) /* Burst Complete (status of completed burst remains in this state unless explicitly cleared by SW) */
\r
14544 /* FLCTL_PRGBRST_CTLSTAT[FLCTL_PRGBRST_CTLSTAT_PRE_ERR] Bits */
\r
14545 #define FLCTL_PRGBRST_CTLSTAT_PRE_ERR_OFS (19) /* PRE_ERR Offset */
\r
14546 #define FLCTL_PRGBRST_CTLSTAT_PRE_ERR (0x00080000) /* Burst Operation encountered preprogram auto-verify errors */
\r
14547 /* FLCTL_PRGBRST_CTLSTAT[FLCTL_PRGBRST_CTLSTAT_PST_ERR] Bits */
\r
14548 #define FLCTL_PRGBRST_CTLSTAT_PST_ERR_OFS (20) /* PST_ERR Offset */
\r
14549 #define FLCTL_PRGBRST_CTLSTAT_PST_ERR (0x00100000) /* Burst Operation encountered postprogram auto-verify errors */
\r
14550 /* FLCTL_PRGBRST_CTLSTAT[FLCTL_PRGBRST_CTLSTAT_ADDR_ERR] Bits */
\r
14551 #define FLCTL_PRGBRST_CTLSTAT_ADDR_ERR_OFS (21) /* ADDR_ERR Offset */
\r
14552 #define FLCTL_PRGBRST_CTLSTAT_ADDR_ERR (0x00200000) /* Burst Operation was terminated due to attempted program of reserved memory */
\r
14553 /* FLCTL_PRGBRST_CTLSTAT[FLCTL_PRGBRST_CTLSTAT_CLR_STAT] Bits */
\r
14554 #define FLCTL_PRGBRST_CTLSTAT_CLR_STAT_OFS (23) /* CLR_STAT Offset */
\r
14555 #define FLCTL_PRGBRST_CTLSTAT_CLR_STAT (0x00800000) /* Clear status bits 21-16 of this register */
\r
14556 /* FLCTL_PRGBRST_STARTADDR[FLCTL_PRGBRST_STARTADDR_START_ADDRESS] Bits */
\r
14557 #define FLCTL_PRGBRST_STARTADDR_START_ADDRESS_OFS ( 0) /* START_ADDRESS Offset */
\r
14558 #define FLCTL_PRGBRST_STARTADDR_START_ADDRESS_M (0x003fffff) /* Start Address of Program Burst Operation */
\r
14559 /* FLCTL_ERASE_CTLSTAT[FLCTL_ERASE_CTLSTAT_START] Bits */
\r
14560 #define FLCTL_ERASE_CTLSTAT_START_OFS ( 0) /* START Offset */
\r
14561 #define FLCTL_ERASE_CTLSTAT_START (0x00000001) /* Start of Erase operation */
\r
14562 /* FLCTL_ERASE_CTLSTAT[FLCTL_ERASE_CTLSTAT_MODE] Bits */
\r
14563 #define FLCTL_ERASE_CTLSTAT_MODE_OFS ( 1) /* MODE Offset */
\r
14564 #define FLCTL_ERASE_CTLSTAT_MODE (0x00000002) /* Erase mode selected by application */
\r
14565 /* FLCTL_ERASE_CTLSTAT[FLCTL_ERASE_CTLSTAT_TYPE] Bits */
\r
14566 #define FLCTL_ERASE_CTLSTAT_TYPE_OFS ( 2) /* TYPE Offset */
\r
14567 #define FLCTL_ERASE_CTLSTAT_TYPE_M (0x0000000c) /* Type of memory that erase operation is carried out on */
\r
14568 #define FLCTL_ERASE_CTLSTAT_TYPE0 (0x00000004) /* Type of memory that erase operation is carried out on */
\r
14569 #define FLCTL_ERASE_CTLSTAT_TYPE1 (0x00000008) /* Type of memory that erase operation is carried out on */
\r
14570 #define FLCTL_ERASE_CTLSTAT_TYPE_0 (0x00000000) /* Main Memory */
\r
14571 #define FLCTL_ERASE_CTLSTAT_TYPE_1 (0x00000004) /* Information Memory */
\r
14572 #define FLCTL_ERASE_CTLSTAT_TYPE_2 (0x00000008) /* Reserved */
\r
14573 #define FLCTL_ERASE_CTLSTAT_TYPE_3 (0x0000000c) /* Engineering Memory */
\r
14574 /* FLCTL_ERASE_CTLSTAT[FLCTL_ERASE_CTLSTAT_STATUS] Bits */
\r
14575 #define FLCTL_ERASE_CTLSTAT_STATUS_OFS (16) /* STATUS Offset */
\r
14576 #define FLCTL_ERASE_CTLSTAT_STATUS_M (0x00030000) /* Status of erase operations in the Flash memory */
\r
14577 #define FLCTL_ERASE_CTLSTAT_STATUS0 (0x00010000) /* Status of erase operations in the Flash memory */
\r
14578 #define FLCTL_ERASE_CTLSTAT_STATUS1 (0x00020000) /* Status of erase operations in the Flash memory */
\r
14579 #define FLCTL_ERASE_CTLSTAT_STATUS_0 (0x00000000) /* Idle (no program operation currently active) */
\r
14580 #define FLCTL_ERASE_CTLSTAT_STATUS_1 (0x00010000) /* Erase operation triggered to START but pending */
\r
14581 #define FLCTL_ERASE_CTLSTAT_STATUS_2 (0x00020000) /* Erase operation in progress */
\r
14582 #define FLCTL_ERASE_CTLSTAT_STATUS_3 (0x00030000) /* Erase operation completed (status of completed erase remains in this state unless explicitly cleared by SW) */
\r
14583 /* FLCTL_ERASE_CTLSTAT[FLCTL_ERASE_CTLSTAT_ADDR_ERR] Bits */
\r
14584 #define FLCTL_ERASE_CTLSTAT_ADDR_ERR_OFS (18) /* ADDR_ERR Offset */
\r
14585 #define FLCTL_ERASE_CTLSTAT_ADDR_ERR (0x00040000) /* Erase Operation was terminated due to attempted erase of reserved memory address */
\r
14586 /* FLCTL_ERASE_CTLSTAT[FLCTL_ERASE_CTLSTAT_CLR_STAT] Bits */
\r
14587 #define FLCTL_ERASE_CTLSTAT_CLR_STAT_OFS (19) /* CLR_STAT Offset */
\r
14588 #define FLCTL_ERASE_CTLSTAT_CLR_STAT (0x00080000) /* Clear status bits 18-16 of this register */
\r
14589 /* FLCTL_ERASE_SECTADDR[FLCTL_ERASE_SECTADDR_SECT_ADDRESS] Bits */
\r
14590 #define FLCTL_ERASE_SECTADDR_SECT_ADDRESS_OFS ( 0) /* SECT_ADDRESS Offset */
\r
14591 #define FLCTL_ERASE_SECTADDR_SECT_ADDRESS_M (0x003fffff) /* Address of Sector being Erased */
\r
14592 /* FLCTL_BANK0_INFO_WEPROT[FLCTL_BANK0_INFO_WEPROT_PROT0] Bits */
\r
14593 #define FLCTL_BANK0_INFO_WEPROT_PROT0_OFS ( 0) /* PROT0 Offset */
\r
14594 #define FLCTL_BANK0_INFO_WEPROT_PROT0 (0x00000001) /* Protects Sector 0 from program or erase */
\r
14595 /* FLCTL_BANK0_INFO_WEPROT[FLCTL_BANK0_INFO_WEPROT_PROT1] Bits */
\r
14596 #define FLCTL_BANK0_INFO_WEPROT_PROT1_OFS ( 1) /* PROT1 Offset */
\r
14597 #define FLCTL_BANK0_INFO_WEPROT_PROT1 (0x00000002) /* Protects Sector 1 from program or erase */
\r
14598 /* FLCTL_BANK0_MAIN_WEPROT[FLCTL_BANK0_MAIN_WEPROT_PROT0] Bits */
\r
14599 #define FLCTL_BANK0_MAIN_WEPROT_PROT0_OFS ( 0) /* PROT0 Offset */
\r
14600 #define FLCTL_BANK0_MAIN_WEPROT_PROT0 (0x00000001) /* Protects Sector 0 from program or erase */
\r
14601 /* FLCTL_BANK0_MAIN_WEPROT[FLCTL_BANK0_MAIN_WEPROT_PROT1] Bits */
\r
14602 #define FLCTL_BANK0_MAIN_WEPROT_PROT1_OFS ( 1) /* PROT1 Offset */
\r
14603 #define FLCTL_BANK0_MAIN_WEPROT_PROT1 (0x00000002) /* Protects Sector 1 from program or erase */
\r
14604 /* FLCTL_BANK0_MAIN_WEPROT[FLCTL_BANK0_MAIN_WEPROT_PROT2] Bits */
\r
14605 #define FLCTL_BANK0_MAIN_WEPROT_PROT2_OFS ( 2) /* PROT2 Offset */
\r
14606 #define FLCTL_BANK0_MAIN_WEPROT_PROT2 (0x00000004) /* Protects Sector 2 from program or erase */
\r
14607 /* FLCTL_BANK0_MAIN_WEPROT[FLCTL_BANK0_MAIN_WEPROT_PROT3] Bits */
\r
14608 #define FLCTL_BANK0_MAIN_WEPROT_PROT3_OFS ( 3) /* PROT3 Offset */
\r
14609 #define FLCTL_BANK0_MAIN_WEPROT_PROT3 (0x00000008) /* Protects Sector 3 from program or erase */
\r
14610 /* FLCTL_BANK0_MAIN_WEPROT[FLCTL_BANK0_MAIN_WEPROT_PROT4] Bits */
\r
14611 #define FLCTL_BANK0_MAIN_WEPROT_PROT4_OFS ( 4) /* PROT4 Offset */
\r
14612 #define FLCTL_BANK0_MAIN_WEPROT_PROT4 (0x00000010) /* Protects Sector 4 from program or erase */
\r
14613 /* FLCTL_BANK0_MAIN_WEPROT[FLCTL_BANK0_MAIN_WEPROT_PROT5] Bits */
\r
14614 #define FLCTL_BANK0_MAIN_WEPROT_PROT5_OFS ( 5) /* PROT5 Offset */
\r
14615 #define FLCTL_BANK0_MAIN_WEPROT_PROT5 (0x00000020) /* Protects Sector 5 from program or erase */
\r
14616 /* FLCTL_BANK0_MAIN_WEPROT[FLCTL_BANK0_MAIN_WEPROT_PROT6] Bits */
\r
14617 #define FLCTL_BANK0_MAIN_WEPROT_PROT6_OFS ( 6) /* PROT6 Offset */
\r
14618 #define FLCTL_BANK0_MAIN_WEPROT_PROT6 (0x00000040) /* Protects Sector 6 from program or erase */
\r
14619 /* FLCTL_BANK0_MAIN_WEPROT[FLCTL_BANK0_MAIN_WEPROT_PROT7] Bits */
\r
14620 #define FLCTL_BANK0_MAIN_WEPROT_PROT7_OFS ( 7) /* PROT7 Offset */
\r
14621 #define FLCTL_BANK0_MAIN_WEPROT_PROT7 (0x00000080) /* Protects Sector 7 from program or erase */
\r
14622 /* FLCTL_BANK0_MAIN_WEPROT[FLCTL_BANK0_MAIN_WEPROT_PROT8] Bits */
\r
14623 #define FLCTL_BANK0_MAIN_WEPROT_PROT8_OFS ( 8) /* PROT8 Offset */
\r
14624 #define FLCTL_BANK0_MAIN_WEPROT_PROT8 (0x00000100) /* Protects Sector 8 from program or erase */
\r
14625 /* FLCTL_BANK0_MAIN_WEPROT[FLCTL_BANK0_MAIN_WEPROT_PROT9] Bits */
\r
14626 #define FLCTL_BANK0_MAIN_WEPROT_PROT9_OFS ( 9) /* PROT9 Offset */
\r
14627 #define FLCTL_BANK0_MAIN_WEPROT_PROT9 (0x00000200) /* Protects Sector 9 from program or erase */
\r
14628 /* FLCTL_BANK0_MAIN_WEPROT[FLCTL_BANK0_MAIN_WEPROT_PROT10] Bits */
\r
14629 #define FLCTL_BANK0_MAIN_WEPROT_PROT10_OFS (10) /* PROT10 Offset */
\r
14630 #define FLCTL_BANK0_MAIN_WEPROT_PROT10 (0x00000400) /* Protects Sector 10 from program or erase */
\r
14631 /* FLCTL_BANK0_MAIN_WEPROT[FLCTL_BANK0_MAIN_WEPROT_PROT11] Bits */
\r
14632 #define FLCTL_BANK0_MAIN_WEPROT_PROT11_OFS (11) /* PROT11 Offset */
\r
14633 #define FLCTL_BANK0_MAIN_WEPROT_PROT11 (0x00000800) /* Protects Sector 11 from program or erase */
\r
14634 /* FLCTL_BANK0_MAIN_WEPROT[FLCTL_BANK0_MAIN_WEPROT_PROT12] Bits */
\r
14635 #define FLCTL_BANK0_MAIN_WEPROT_PROT12_OFS (12) /* PROT12 Offset */
\r
14636 #define FLCTL_BANK0_MAIN_WEPROT_PROT12 (0x00001000) /* Protects Sector 12 from program or erase */
\r
14637 /* FLCTL_BANK0_MAIN_WEPROT[FLCTL_BANK0_MAIN_WEPROT_PROT13] Bits */
\r
14638 #define FLCTL_BANK0_MAIN_WEPROT_PROT13_OFS (13) /* PROT13 Offset */
\r
14639 #define FLCTL_BANK0_MAIN_WEPROT_PROT13 (0x00002000) /* Protects Sector 13 from program or erase */
\r
14640 /* FLCTL_BANK0_MAIN_WEPROT[FLCTL_BANK0_MAIN_WEPROT_PROT14] Bits */
\r
14641 #define FLCTL_BANK0_MAIN_WEPROT_PROT14_OFS (14) /* PROT14 Offset */
\r
14642 #define FLCTL_BANK0_MAIN_WEPROT_PROT14 (0x00004000) /* Protects Sector 14 from program or erase */
\r
14643 /* FLCTL_BANK0_MAIN_WEPROT[FLCTL_BANK0_MAIN_WEPROT_PROT15] Bits */
\r
14644 #define FLCTL_BANK0_MAIN_WEPROT_PROT15_OFS (15) /* PROT15 Offset */
\r
14645 #define FLCTL_BANK0_MAIN_WEPROT_PROT15 (0x00008000) /* Protects Sector 15 from program or erase */
\r
14646 /* FLCTL_BANK0_MAIN_WEPROT[FLCTL_BANK0_MAIN_WEPROT_PROT16] Bits */
\r
14647 #define FLCTL_BANK0_MAIN_WEPROT_PROT16_OFS (16) /* PROT16 Offset */
\r
14648 #define FLCTL_BANK0_MAIN_WEPROT_PROT16 (0x00010000) /* Protects Sector 16 from program or erase */
\r
14649 /* FLCTL_BANK0_MAIN_WEPROT[FLCTL_BANK0_MAIN_WEPROT_PROT17] Bits */
\r
14650 #define FLCTL_BANK0_MAIN_WEPROT_PROT17_OFS (17) /* PROT17 Offset */
\r
14651 #define FLCTL_BANK0_MAIN_WEPROT_PROT17 (0x00020000) /* Protects Sector 17 from program or erase */
\r
14652 /* FLCTL_BANK0_MAIN_WEPROT[FLCTL_BANK0_MAIN_WEPROT_PROT18] Bits */
\r
14653 #define FLCTL_BANK0_MAIN_WEPROT_PROT18_OFS (18) /* PROT18 Offset */
\r
14654 #define FLCTL_BANK0_MAIN_WEPROT_PROT18 (0x00040000) /* Protects Sector 18 from program or erase */
\r
14655 /* FLCTL_BANK0_MAIN_WEPROT[FLCTL_BANK0_MAIN_WEPROT_PROT19] Bits */
\r
14656 #define FLCTL_BANK0_MAIN_WEPROT_PROT19_OFS (19) /* PROT19 Offset */
\r
14657 #define FLCTL_BANK0_MAIN_WEPROT_PROT19 (0x00080000) /* Protects Sector 19 from program or erase */
\r
14658 /* FLCTL_BANK0_MAIN_WEPROT[FLCTL_BANK0_MAIN_WEPROT_PROT20] Bits */
\r
14659 #define FLCTL_BANK0_MAIN_WEPROT_PROT20_OFS (20) /* PROT20 Offset */
\r
14660 #define FLCTL_BANK0_MAIN_WEPROT_PROT20 (0x00100000) /* Protects Sector 20 from program or erase */
\r
14661 /* FLCTL_BANK0_MAIN_WEPROT[FLCTL_BANK0_MAIN_WEPROT_PROT21] Bits */
\r
14662 #define FLCTL_BANK0_MAIN_WEPROT_PROT21_OFS (21) /* PROT21 Offset */
\r
14663 #define FLCTL_BANK0_MAIN_WEPROT_PROT21 (0x00200000) /* Protects Sector 21 from program or erase */
\r
14664 /* FLCTL_BANK0_MAIN_WEPROT[FLCTL_BANK0_MAIN_WEPROT_PROT22] Bits */
\r
14665 #define FLCTL_BANK0_MAIN_WEPROT_PROT22_OFS (22) /* PROT22 Offset */
\r
14666 #define FLCTL_BANK0_MAIN_WEPROT_PROT22 (0x00400000) /* Protects Sector 22 from program or erase */
\r
14667 /* FLCTL_BANK0_MAIN_WEPROT[FLCTL_BANK0_MAIN_WEPROT_PROT23] Bits */
\r
14668 #define FLCTL_BANK0_MAIN_WEPROT_PROT23_OFS (23) /* PROT23 Offset */
\r
14669 #define FLCTL_BANK0_MAIN_WEPROT_PROT23 (0x00800000) /* Protects Sector 23 from program or erase */
\r
14670 /* FLCTL_BANK0_MAIN_WEPROT[FLCTL_BANK0_MAIN_WEPROT_PROT24] Bits */
\r
14671 #define FLCTL_BANK0_MAIN_WEPROT_PROT24_OFS (24) /* PROT24 Offset */
\r
14672 #define FLCTL_BANK0_MAIN_WEPROT_PROT24 (0x01000000) /* Protects Sector 24 from program or erase */
\r
14673 /* FLCTL_BANK0_MAIN_WEPROT[FLCTL_BANK0_MAIN_WEPROT_PROT25] Bits */
\r
14674 #define FLCTL_BANK0_MAIN_WEPROT_PROT25_OFS (25) /* PROT25 Offset */
\r
14675 #define FLCTL_BANK0_MAIN_WEPROT_PROT25 (0x02000000) /* Protects Sector 25 from program or erase */
\r
14676 /* FLCTL_BANK0_MAIN_WEPROT[FLCTL_BANK0_MAIN_WEPROT_PROT26] Bits */
\r
14677 #define FLCTL_BANK0_MAIN_WEPROT_PROT26_OFS (26) /* PROT26 Offset */
\r
14678 #define FLCTL_BANK0_MAIN_WEPROT_PROT26 (0x04000000) /* Protects Sector 26 from program or erase */
\r
14679 /* FLCTL_BANK0_MAIN_WEPROT[FLCTL_BANK0_MAIN_WEPROT_PROT27] Bits */
\r
14680 #define FLCTL_BANK0_MAIN_WEPROT_PROT27_OFS (27) /* PROT27 Offset */
\r
14681 #define FLCTL_BANK0_MAIN_WEPROT_PROT27 (0x08000000) /* Protects Sector 27 from program or erase */
\r
14682 /* FLCTL_BANK0_MAIN_WEPROT[FLCTL_BANK0_MAIN_WEPROT_PROT28] Bits */
\r
14683 #define FLCTL_BANK0_MAIN_WEPROT_PROT28_OFS (28) /* PROT28 Offset */
\r
14684 #define FLCTL_BANK0_MAIN_WEPROT_PROT28 (0x10000000) /* Protects Sector 28 from program or erase */
\r
14685 /* FLCTL_BANK0_MAIN_WEPROT[FLCTL_BANK0_MAIN_WEPROT_PROT29] Bits */
\r
14686 #define FLCTL_BANK0_MAIN_WEPROT_PROT29_OFS (29) /* PROT29 Offset */
\r
14687 #define FLCTL_BANK0_MAIN_WEPROT_PROT29 (0x20000000) /* Protects Sector 29 from program or erase */
\r
14688 /* FLCTL_BANK0_MAIN_WEPROT[FLCTL_BANK0_MAIN_WEPROT_PROT30] Bits */
\r
14689 #define FLCTL_BANK0_MAIN_WEPROT_PROT30_OFS (30) /* PROT30 Offset */
\r
14690 #define FLCTL_BANK0_MAIN_WEPROT_PROT30 (0x40000000) /* Protects Sector 30 from program or erase */
\r
14691 /* FLCTL_BANK0_MAIN_WEPROT[FLCTL_BANK0_MAIN_WEPROT_PROT31] Bits */
\r
14692 #define FLCTL_BANK0_MAIN_WEPROT_PROT31_OFS (31) /* PROT31 Offset */
\r
14693 #define FLCTL_BANK0_MAIN_WEPROT_PROT31 (0x80000000) /* Protects Sector 31 from program or erase */
\r
14694 /* FLCTL_BANK1_INFO_WEPROT[FLCTL_BANK1_INFO_WEPROT_PROT0] Bits */
\r
14695 #define FLCTL_BANK1_INFO_WEPROT_PROT0_OFS ( 0) /* PROT0 Offset */
\r
14696 #define FLCTL_BANK1_INFO_WEPROT_PROT0 (0x00000001) /* Protects Sector 0 from program or erase operations */
\r
14697 /* FLCTL_BANK1_INFO_WEPROT[FLCTL_BANK1_INFO_WEPROT_PROT1] Bits */
\r
14698 #define FLCTL_BANK1_INFO_WEPROT_PROT1_OFS ( 1) /* PROT1 Offset */
\r
14699 #define FLCTL_BANK1_INFO_WEPROT_PROT1 (0x00000002) /* Protects Sector 1 from program or erase operations */
\r
14700 /* FLCTL_BANK1_MAIN_WEPROT[FLCTL_BANK1_MAIN_WEPROT_PROT0] Bits */
\r
14701 #define FLCTL_BANK1_MAIN_WEPROT_PROT0_OFS ( 0) /* PROT0 Offset */
\r
14702 #define FLCTL_BANK1_MAIN_WEPROT_PROT0 (0x00000001) /* Protects Sector 0 from program or erase operations */
\r
14703 /* FLCTL_BANK1_MAIN_WEPROT[FLCTL_BANK1_MAIN_WEPROT_PROT1] Bits */
\r
14704 #define FLCTL_BANK1_MAIN_WEPROT_PROT1_OFS ( 1) /* PROT1 Offset */
\r
14705 #define FLCTL_BANK1_MAIN_WEPROT_PROT1 (0x00000002) /* Protects Sector 1 from program or erase operations */
\r
14706 /* FLCTL_BANK1_MAIN_WEPROT[FLCTL_BANK1_MAIN_WEPROT_PROT2] Bits */
\r
14707 #define FLCTL_BANK1_MAIN_WEPROT_PROT2_OFS ( 2) /* PROT2 Offset */
\r
14708 #define FLCTL_BANK1_MAIN_WEPROT_PROT2 (0x00000004) /* Protects Sector 2 from program or erase operations */
\r
14709 /* FLCTL_BANK1_MAIN_WEPROT[FLCTL_BANK1_MAIN_WEPROT_PROT3] Bits */
\r
14710 #define FLCTL_BANK1_MAIN_WEPROT_PROT3_OFS ( 3) /* PROT3 Offset */
\r
14711 #define FLCTL_BANK1_MAIN_WEPROT_PROT3 (0x00000008) /* Protects Sector 3 from program or erase operations */
\r
14712 /* FLCTL_BANK1_MAIN_WEPROT[FLCTL_BANK1_MAIN_WEPROT_PROT4] Bits */
\r
14713 #define FLCTL_BANK1_MAIN_WEPROT_PROT4_OFS ( 4) /* PROT4 Offset */
\r
14714 #define FLCTL_BANK1_MAIN_WEPROT_PROT4 (0x00000010) /* Protects Sector 4 from program or erase operations */
\r
14715 /* FLCTL_BANK1_MAIN_WEPROT[FLCTL_BANK1_MAIN_WEPROT_PROT5] Bits */
\r
14716 #define FLCTL_BANK1_MAIN_WEPROT_PROT5_OFS ( 5) /* PROT5 Offset */
\r
14717 #define FLCTL_BANK1_MAIN_WEPROT_PROT5 (0x00000020) /* Protects Sector 5 from program or erase operations */
\r
14718 /* FLCTL_BANK1_MAIN_WEPROT[FLCTL_BANK1_MAIN_WEPROT_PROT6] Bits */
\r
14719 #define FLCTL_BANK1_MAIN_WEPROT_PROT6_OFS ( 6) /* PROT6 Offset */
\r
14720 #define FLCTL_BANK1_MAIN_WEPROT_PROT6 (0x00000040) /* Protects Sector 6 from program or erase operations */
\r
14721 /* FLCTL_BANK1_MAIN_WEPROT[FLCTL_BANK1_MAIN_WEPROT_PROT7] Bits */
\r
14722 #define FLCTL_BANK1_MAIN_WEPROT_PROT7_OFS ( 7) /* PROT7 Offset */
\r
14723 #define FLCTL_BANK1_MAIN_WEPROT_PROT7 (0x00000080) /* Protects Sector 7 from program or erase operations */
\r
14724 /* FLCTL_BANK1_MAIN_WEPROT[FLCTL_BANK1_MAIN_WEPROT_PROT8] Bits */
\r
14725 #define FLCTL_BANK1_MAIN_WEPROT_PROT8_OFS ( 8) /* PROT8 Offset */
\r
14726 #define FLCTL_BANK1_MAIN_WEPROT_PROT8 (0x00000100) /* Protects Sector 8 from program or erase operations */
\r
14727 /* FLCTL_BANK1_MAIN_WEPROT[FLCTL_BANK1_MAIN_WEPROT_PROT9] Bits */
\r
14728 #define FLCTL_BANK1_MAIN_WEPROT_PROT9_OFS ( 9) /* PROT9 Offset */
\r
14729 #define FLCTL_BANK1_MAIN_WEPROT_PROT9 (0x00000200) /* Protects Sector 9 from program or erase operations */
\r
14730 /* FLCTL_BANK1_MAIN_WEPROT[FLCTL_BANK1_MAIN_WEPROT_PROT10] Bits */
\r
14731 #define FLCTL_BANK1_MAIN_WEPROT_PROT10_OFS (10) /* PROT10 Offset */
\r
14732 #define FLCTL_BANK1_MAIN_WEPROT_PROT10 (0x00000400) /* Protects Sector 10 from program or erase operations */
\r
14733 /* FLCTL_BANK1_MAIN_WEPROT[FLCTL_BANK1_MAIN_WEPROT_PROT11] Bits */
\r
14734 #define FLCTL_BANK1_MAIN_WEPROT_PROT11_OFS (11) /* PROT11 Offset */
\r
14735 #define FLCTL_BANK1_MAIN_WEPROT_PROT11 (0x00000800) /* Protects Sector 11 from program or erase operations */
\r
14736 /* FLCTL_BANK1_MAIN_WEPROT[FLCTL_BANK1_MAIN_WEPROT_PROT12] Bits */
\r
14737 #define FLCTL_BANK1_MAIN_WEPROT_PROT12_OFS (12) /* PROT12 Offset */
\r
14738 #define FLCTL_BANK1_MAIN_WEPROT_PROT12 (0x00001000) /* Protects Sector 12 from program or erase operations */
\r
14739 /* FLCTL_BANK1_MAIN_WEPROT[FLCTL_BANK1_MAIN_WEPROT_PROT13] Bits */
\r
14740 #define FLCTL_BANK1_MAIN_WEPROT_PROT13_OFS (13) /* PROT13 Offset */
\r
14741 #define FLCTL_BANK1_MAIN_WEPROT_PROT13 (0x00002000) /* Protects Sector 13 from program or erase operations */
\r
14742 /* FLCTL_BANK1_MAIN_WEPROT[FLCTL_BANK1_MAIN_WEPROT_PROT14] Bits */
\r
14743 #define FLCTL_BANK1_MAIN_WEPROT_PROT14_OFS (14) /* PROT14 Offset */
\r
14744 #define FLCTL_BANK1_MAIN_WEPROT_PROT14 (0x00004000) /* Protects Sector 14 from program or erase operations */
\r
14745 /* FLCTL_BANK1_MAIN_WEPROT[FLCTL_BANK1_MAIN_WEPROT_PROT15] Bits */
\r
14746 #define FLCTL_BANK1_MAIN_WEPROT_PROT15_OFS (15) /* PROT15 Offset */
\r
14747 #define FLCTL_BANK1_MAIN_WEPROT_PROT15 (0x00008000) /* Protects Sector 15 from program or erase operations */
\r
14748 /* FLCTL_BANK1_MAIN_WEPROT[FLCTL_BANK1_MAIN_WEPROT_PROT16] Bits */
\r
14749 #define FLCTL_BANK1_MAIN_WEPROT_PROT16_OFS (16) /* PROT16 Offset */
\r
14750 #define FLCTL_BANK1_MAIN_WEPROT_PROT16 (0x00010000) /* Protects Sector 16 from program or erase operations */
\r
14751 /* FLCTL_BANK1_MAIN_WEPROT[FLCTL_BANK1_MAIN_WEPROT_PROT17] Bits */
\r
14752 #define FLCTL_BANK1_MAIN_WEPROT_PROT17_OFS (17) /* PROT17 Offset */
\r
14753 #define FLCTL_BANK1_MAIN_WEPROT_PROT17 (0x00020000) /* Protects Sector 17 from program or erase operations */
\r
14754 /* FLCTL_BANK1_MAIN_WEPROT[FLCTL_BANK1_MAIN_WEPROT_PROT18] Bits */
\r
14755 #define FLCTL_BANK1_MAIN_WEPROT_PROT18_OFS (18) /* PROT18 Offset */
\r
14756 #define FLCTL_BANK1_MAIN_WEPROT_PROT18 (0x00040000) /* Protects Sector 18 from program or erase operations */
\r
14757 /* FLCTL_BANK1_MAIN_WEPROT[FLCTL_BANK1_MAIN_WEPROT_PROT19] Bits */
\r
14758 #define FLCTL_BANK1_MAIN_WEPROT_PROT19_OFS (19) /* PROT19 Offset */
\r
14759 #define FLCTL_BANK1_MAIN_WEPROT_PROT19 (0x00080000) /* Protects Sector 19 from program or erase operations */
\r
14760 /* FLCTL_BANK1_MAIN_WEPROT[FLCTL_BANK1_MAIN_WEPROT_PROT20] Bits */
\r
14761 #define FLCTL_BANK1_MAIN_WEPROT_PROT20_OFS (20) /* PROT20 Offset */
\r
14762 #define FLCTL_BANK1_MAIN_WEPROT_PROT20 (0x00100000) /* Protects Sector 20 from program or erase operations */
\r
14763 /* FLCTL_BANK1_MAIN_WEPROT[FLCTL_BANK1_MAIN_WEPROT_PROT21] Bits */
\r
14764 #define FLCTL_BANK1_MAIN_WEPROT_PROT21_OFS (21) /* PROT21 Offset */
\r
14765 #define FLCTL_BANK1_MAIN_WEPROT_PROT21 (0x00200000) /* Protects Sector 21 from program or erase operations */
\r
14766 /* FLCTL_BANK1_MAIN_WEPROT[FLCTL_BANK1_MAIN_WEPROT_PROT22] Bits */
\r
14767 #define FLCTL_BANK1_MAIN_WEPROT_PROT22_OFS (22) /* PROT22 Offset */
\r
14768 #define FLCTL_BANK1_MAIN_WEPROT_PROT22 (0x00400000) /* Protects Sector 22 from program or erase operations */
\r
14769 /* FLCTL_BANK1_MAIN_WEPROT[FLCTL_BANK1_MAIN_WEPROT_PROT23] Bits */
\r
14770 #define FLCTL_BANK1_MAIN_WEPROT_PROT23_OFS (23) /* PROT23 Offset */
\r
14771 #define FLCTL_BANK1_MAIN_WEPROT_PROT23 (0x00800000) /* Protects Sector 23 from program or erase operations */
\r
14772 /* FLCTL_BANK1_MAIN_WEPROT[FLCTL_BANK1_MAIN_WEPROT_PROT24] Bits */
\r
14773 #define FLCTL_BANK1_MAIN_WEPROT_PROT24_OFS (24) /* PROT24 Offset */
\r
14774 #define FLCTL_BANK1_MAIN_WEPROT_PROT24 (0x01000000) /* Protects Sector 24 from program or erase operations */
\r
14775 /* FLCTL_BANK1_MAIN_WEPROT[FLCTL_BANK1_MAIN_WEPROT_PROT25] Bits */
\r
14776 #define FLCTL_BANK1_MAIN_WEPROT_PROT25_OFS (25) /* PROT25 Offset */
\r
14777 #define FLCTL_BANK1_MAIN_WEPROT_PROT25 (0x02000000) /* Protects Sector 25 from program or erase operations */
\r
14778 /* FLCTL_BANK1_MAIN_WEPROT[FLCTL_BANK1_MAIN_WEPROT_PROT26] Bits */
\r
14779 #define FLCTL_BANK1_MAIN_WEPROT_PROT26_OFS (26) /* PROT26 Offset */
\r
14780 #define FLCTL_BANK1_MAIN_WEPROT_PROT26 (0x04000000) /* Protects Sector 26 from program or erase operations */
\r
14781 /* FLCTL_BANK1_MAIN_WEPROT[FLCTL_BANK1_MAIN_WEPROT_PROT27] Bits */
\r
14782 #define FLCTL_BANK1_MAIN_WEPROT_PROT27_OFS (27) /* PROT27 Offset */
\r
14783 #define FLCTL_BANK1_MAIN_WEPROT_PROT27 (0x08000000) /* Protects Sector 27 from program or erase operations */
\r
14784 /* FLCTL_BANK1_MAIN_WEPROT[FLCTL_BANK1_MAIN_WEPROT_PROT28] Bits */
\r
14785 #define FLCTL_BANK1_MAIN_WEPROT_PROT28_OFS (28) /* PROT28 Offset */
\r
14786 #define FLCTL_BANK1_MAIN_WEPROT_PROT28 (0x10000000) /* Protects Sector 28 from program or erase operations */
\r
14787 /* FLCTL_BANK1_MAIN_WEPROT[FLCTL_BANK1_MAIN_WEPROT_PROT29] Bits */
\r
14788 #define FLCTL_BANK1_MAIN_WEPROT_PROT29_OFS (29) /* PROT29 Offset */
\r
14789 #define FLCTL_BANK1_MAIN_WEPROT_PROT29 (0x20000000) /* Protects Sector 29 from program or erase operations */
\r
14790 /* FLCTL_BANK1_MAIN_WEPROT[FLCTL_BANK1_MAIN_WEPROT_PROT30] Bits */
\r
14791 #define FLCTL_BANK1_MAIN_WEPROT_PROT30_OFS (30) /* PROT30 Offset */
\r
14792 #define FLCTL_BANK1_MAIN_WEPROT_PROT30 (0x40000000) /* Protects Sector 30 from program or erase operations */
\r
14793 /* FLCTL_BANK1_MAIN_WEPROT[FLCTL_BANK1_MAIN_WEPROT_PROT31] Bits */
\r
14794 #define FLCTL_BANK1_MAIN_WEPROT_PROT31_OFS (31) /* PROT31 Offset */
\r
14795 #define FLCTL_BANK1_MAIN_WEPROT_PROT31 (0x80000000) /* Protects Sector 31 from program or erase operations */
\r
14796 /* FLCTL_BMRK_CTLSTAT[FLCTL_BMRK_CTLSTAT_I_BMRK] Bits */
\r
14797 #define FLCTL_BMRK_CTLSTAT_I_BMRK_OFS ( 0) /* I_BMRK Offset */
\r
14798 #define FLCTL_BMRK_CTLSTAT_I_BMRK (0x00000001) /* */
\r
14799 /* FLCTL_BMRK_CTLSTAT[FLCTL_BMRK_CTLSTAT_D_BMRK] Bits */
\r
14800 #define FLCTL_BMRK_CTLSTAT_D_BMRK_OFS ( 1) /* D_BMRK Offset */
\r
14801 #define FLCTL_BMRK_CTLSTAT_D_BMRK (0x00000002) /* */
\r
14802 /* FLCTL_BMRK_CTLSTAT[FLCTL_BMRK_CTLSTAT_CMP_EN] Bits */
\r
14803 #define FLCTL_BMRK_CTLSTAT_CMP_EN_OFS ( 2) /* CMP_EN Offset */
\r
14804 #define FLCTL_BMRK_CTLSTAT_CMP_EN (0x00000004) /* */
\r
14805 /* FLCTL_BMRK_CTLSTAT[FLCTL_BMRK_CTLSTAT_CMP_SEL] Bits */
\r
14806 #define FLCTL_BMRK_CTLSTAT_CMP_SEL_OFS ( 3) /* CMP_SEL Offset */
\r
14807 #define FLCTL_BMRK_CTLSTAT_CMP_SEL (0x00000008) /* */
\r
14808 /* FLCTL_IFG[FLCTL_IFG_RDBRST] Bits */
\r
14809 #define FLCTL_IFG_RDBRST_OFS ( 0) /* RDBRST Offset */
\r
14810 #define FLCTL_IFG_RDBRST (0x00000001) /* */
\r
14811 /* FLCTL_IFG[FLCTL_IFG_AVPRE] Bits */
\r
14812 #define FLCTL_IFG_AVPRE_OFS ( 1) /* AVPRE Offset */
\r
14813 #define FLCTL_IFG_AVPRE (0x00000002) /* */
\r
14814 /* FLCTL_IFG[FLCTL_IFG_AVPST] Bits */
\r
14815 #define FLCTL_IFG_AVPST_OFS ( 2) /* AVPST Offset */
\r
14816 #define FLCTL_IFG_AVPST (0x00000004) /* */
\r
14817 /* FLCTL_IFG[FLCTL_IFG_PRG] Bits */
\r
14818 #define FLCTL_IFG_PRG_OFS ( 3) /* PRG Offset */
\r
14819 #define FLCTL_IFG_PRG (0x00000008) /* */
\r
14820 /* FLCTL_IFG[FLCTL_IFG_PRGB] Bits */
\r
14821 #define FLCTL_IFG_PRGB_OFS ( 4) /* PRGB Offset */
\r
14822 #define FLCTL_IFG_PRGB (0x00000010) /* */
\r
14823 /* FLCTL_IFG[FLCTL_IFG_ERASE] Bits */
\r
14824 #define FLCTL_IFG_ERASE_OFS ( 5) /* ERASE Offset */
\r
14825 #define FLCTL_IFG_ERASE (0x00000020) /* */
\r
14826 /* FLCTL_IFG[FLCTL_IFG_BMRK] Bits */
\r
14827 #define FLCTL_IFG_BMRK_OFS ( 8) /* BMRK Offset */
\r
14828 #define FLCTL_IFG_BMRK (0x00000100) /* */
\r
14829 /* FLCTL_IFG[FLCTL_IFG_PRG_ERR] Bits */
\r
14830 #define FLCTL_IFG_PRG_ERR_OFS ( 9) /* PRG_ERR Offset */
\r
14831 #define FLCTL_IFG_PRG_ERR (0x00000200) /* */
\r
14832 /* FLCTL_IE[FLCTL_IE_RDBRST] Bits */
\r
14833 #define FLCTL_IE_RDBRST_OFS ( 0) /* RDBRST Offset */
\r
14834 #define FLCTL_IE_RDBRST (0x00000001) /* */
\r
14835 /* FLCTL_IE[FLCTL_IE_AVPRE] Bits */
\r
14836 #define FLCTL_IE_AVPRE_OFS ( 1) /* AVPRE Offset */
\r
14837 #define FLCTL_IE_AVPRE (0x00000002) /* */
\r
14838 /* FLCTL_IE[FLCTL_IE_AVPST] Bits */
\r
14839 #define FLCTL_IE_AVPST_OFS ( 2) /* AVPST Offset */
\r
14840 #define FLCTL_IE_AVPST (0x00000004) /* */
\r
14841 /* FLCTL_IE[FLCTL_IE_PRG] Bits */
\r
14842 #define FLCTL_IE_PRG_OFS ( 3) /* PRG Offset */
\r
14843 #define FLCTL_IE_PRG (0x00000008) /* */
\r
14844 /* FLCTL_IE[FLCTL_IE_PRGB] Bits */
\r
14845 #define FLCTL_IE_PRGB_OFS ( 4) /* PRGB Offset */
\r
14846 #define FLCTL_IE_PRGB (0x00000010) /* */
\r
14847 /* FLCTL_IE[FLCTL_IE_ERASE] Bits */
\r
14848 #define FLCTL_IE_ERASE_OFS ( 5) /* ERASE Offset */
\r
14849 #define FLCTL_IE_ERASE (0x00000020) /* */
\r
14850 /* FLCTL_IE[FLCTL_IE_BMRK] Bits */
\r
14851 #define FLCTL_IE_BMRK_OFS ( 8) /* BMRK Offset */
\r
14852 #define FLCTL_IE_BMRK (0x00000100) /* */
\r
14853 /* FLCTL_IE[FLCTL_IE_PRG_ERR] Bits */
\r
14854 #define FLCTL_IE_PRG_ERR_OFS ( 9) /* PRG_ERR Offset */
\r
14855 #define FLCTL_IE_PRG_ERR (0x00000200) /* */
\r
14856 /* FLCTL_CLRIFG[FLCTL_CLRIFG_RDBRST] Bits */
\r
14857 #define FLCTL_CLRIFG_RDBRST_OFS ( 0) /* RDBRST Offset */
\r
14858 #define FLCTL_CLRIFG_RDBRST (0x00000001) /* */
\r
14859 /* FLCTL_CLRIFG[FLCTL_CLRIFG_AVPRE] Bits */
\r
14860 #define FLCTL_CLRIFG_AVPRE_OFS ( 1) /* AVPRE Offset */
\r
14861 #define FLCTL_CLRIFG_AVPRE (0x00000002) /* */
\r
14862 /* FLCTL_CLRIFG[FLCTL_CLRIFG_AVPST] Bits */
\r
14863 #define FLCTL_CLRIFG_AVPST_OFS ( 2) /* AVPST Offset */
\r
14864 #define FLCTL_CLRIFG_AVPST (0x00000004) /* */
\r
14865 /* FLCTL_CLRIFG[FLCTL_CLRIFG_PRG] Bits */
\r
14866 #define FLCTL_CLRIFG_PRG_OFS ( 3) /* PRG Offset */
\r
14867 #define FLCTL_CLRIFG_PRG (0x00000008) /* */
\r
14868 /* FLCTL_CLRIFG[FLCTL_CLRIFG_PRGB] Bits */
\r
14869 #define FLCTL_CLRIFG_PRGB_OFS ( 4) /* PRGB Offset */
\r
14870 #define FLCTL_CLRIFG_PRGB (0x00000010) /* */
\r
14871 /* FLCTL_CLRIFG[FLCTL_CLRIFG_ERASE] Bits */
\r
14872 #define FLCTL_CLRIFG_ERASE_OFS ( 5) /* ERASE Offset */
\r
14873 #define FLCTL_CLRIFG_ERASE (0x00000020) /* */
\r
14874 /* FLCTL_CLRIFG[FLCTL_CLRIFG_BMRK] Bits */
\r
14875 #define FLCTL_CLRIFG_BMRK_OFS ( 8) /* BMRK Offset */
\r
14876 #define FLCTL_CLRIFG_BMRK (0x00000100) /* */
\r
14877 /* FLCTL_CLRIFG[FLCTL_CLRIFG_PRG_ERR] Bits */
\r
14878 #define FLCTL_CLRIFG_PRG_ERR_OFS ( 9) /* PRG_ERR Offset */
\r
14879 #define FLCTL_CLRIFG_PRG_ERR (0x00000200) /* */
\r
14880 /* FLCTL_SETIFG[FLCTL_SETIFG_RDBRST] Bits */
\r
14881 #define FLCTL_SETIFG_RDBRST_OFS ( 0) /* RDBRST Offset */
\r
14882 #define FLCTL_SETIFG_RDBRST (0x00000001) /* */
\r
14883 /* FLCTL_SETIFG[FLCTL_SETIFG_AVPRE] Bits */
\r
14884 #define FLCTL_SETIFG_AVPRE_OFS ( 1) /* AVPRE Offset */
\r
14885 #define FLCTL_SETIFG_AVPRE (0x00000002) /* */
\r
14886 /* FLCTL_SETIFG[FLCTL_SETIFG_AVPST] Bits */
\r
14887 #define FLCTL_SETIFG_AVPST_OFS ( 2) /* AVPST Offset */
\r
14888 #define FLCTL_SETIFG_AVPST (0x00000004) /* */
\r
14889 /* FLCTL_SETIFG[FLCTL_SETIFG_PRG] Bits */
\r
14890 #define FLCTL_SETIFG_PRG_OFS ( 3) /* PRG Offset */
\r
14891 #define FLCTL_SETIFG_PRG (0x00000008) /* */
\r
14892 /* FLCTL_SETIFG[FLCTL_SETIFG_PRGB] Bits */
\r
14893 #define FLCTL_SETIFG_PRGB_OFS ( 4) /* PRGB Offset */
\r
14894 #define FLCTL_SETIFG_PRGB (0x00000010) /* */
\r
14895 /* FLCTL_SETIFG[FLCTL_SETIFG_ERASE] Bits */
\r
14896 #define FLCTL_SETIFG_ERASE_OFS ( 5) /* ERASE Offset */
\r
14897 #define FLCTL_SETIFG_ERASE (0x00000020) /* */
\r
14898 /* FLCTL_SETIFG[FLCTL_SETIFG_BMRK] Bits */
\r
14899 #define FLCTL_SETIFG_BMRK_OFS ( 8) /* BMRK Offset */
\r
14900 #define FLCTL_SETIFG_BMRK (0x00000100) /* */
\r
14901 /* FLCTL_SETIFG[FLCTL_SETIFG_PRG_ERR] Bits */
\r
14902 #define FLCTL_SETIFG_PRG_ERR_OFS ( 9) /* PRG_ERR Offset */
\r
14903 #define FLCTL_SETIFG_PRG_ERR (0x00000200) /* */
\r
14904 /* FLCTL_READ_TIMCTL[FLCTL_READ_TIMCTL_SETUP] Bits */
\r
14905 #define FLCTL_READ_TIMCTL_SETUP_OFS ( 0) /* SETUP Offset */
\r
14906 #define FLCTL_READ_TIMCTL_SETUP_M (0x000000ff) /* */
\r
14907 /* FLCTL_READ_TIMCTL[FLCTL_READ_TIMCTL_HOLD] Bits */
\r
14908 #define FLCTL_READ_TIMCTL_HOLD_OFS ( 8) /* HOLD Offset */
\r
14909 #define FLCTL_READ_TIMCTL_HOLD_M (0x00000f00) /* */
\r
14910 /* FLCTL_READ_TIMCTL[FLCTL_READ_TIMCTL_IREF_BOOST1] Bits */
\r
14911 #define FLCTL_READ_TIMCTL_IREF_BOOST1_OFS (12) /* IREF_BOOST1 Offset */
\r
14912 #define FLCTL_READ_TIMCTL_IREF_BOOST1_M (0x0000f000) /* */
\r
14913 /* FLCTL_READ_TIMCTL[FLCTL_READ_TIMCTL_SETUP_LONG] Bits */
\r
14914 #define FLCTL_READ_TIMCTL_SETUP_LONG_OFS (16) /* SETUP_LONG Offset */
\r
14915 #define FLCTL_READ_TIMCTL_SETUP_LONG_M (0x00ff0000) /* */
\r
14916 /* FLCTL_READMARGIN_TIMCTL[FLCTL_READMARGIN_TIMCTL_SETUP] Bits */
\r
14917 #define FLCTL_READMARGIN_TIMCTL_SETUP_OFS ( 0) /* SETUP Offset */
\r
14918 #define FLCTL_READMARGIN_TIMCTL_SETUP_M (0x000000ff) /* */
\r
14919 /* FLCTL_READMARGIN_TIMCTL[FLCTL_READMARGIN_TIMCTL_HOLD] Bits */
\r
14920 #define FLCTL_READMARGIN_TIMCTL_HOLD_OFS ( 8) /* HOLD Offset */
\r
14921 #define FLCTL_READMARGIN_TIMCTL_HOLD_M (0x00000f00) /* */
\r
14922 /* FLCTL_PRGVER_TIMCTL[FLCTL_PRGVER_TIMCTL_SETUP] Bits */
\r
14923 #define FLCTL_PRGVER_TIMCTL_SETUP_OFS ( 0) /* SETUP Offset */
\r
14924 #define FLCTL_PRGVER_TIMCTL_SETUP_M (0x000000ff) /* */
\r
14925 /* FLCTL_PRGVER_TIMCTL[FLCTL_PRGVER_TIMCTL_ACTIVE] Bits */
\r
14926 #define FLCTL_PRGVER_TIMCTL_ACTIVE_OFS ( 8) /* ACTIVE Offset */
\r
14927 #define FLCTL_PRGVER_TIMCTL_ACTIVE_M (0x00000f00) /* */
\r
14928 /* FLCTL_PRGVER_TIMCTL[FLCTL_PRGVER_TIMCTL_HOLD] Bits */
\r
14929 #define FLCTL_PRGVER_TIMCTL_HOLD_OFS (12) /* HOLD Offset */
\r
14930 #define FLCTL_PRGVER_TIMCTL_HOLD_M (0x0000f000) /* */
\r
14931 /* FLCTL_ERSVER_TIMCTL[FLCTL_ERSVER_TIMCTL_SETUP] Bits */
\r
14932 #define FLCTL_ERSVER_TIMCTL_SETUP_OFS ( 0) /* SETUP Offset */
\r
14933 #define FLCTL_ERSVER_TIMCTL_SETUP_M (0x000000ff) /* */
\r
14934 /* FLCTL_ERSVER_TIMCTL[FLCTL_ERSVER_TIMCTL_HOLD] Bits */
\r
14935 #define FLCTL_ERSVER_TIMCTL_HOLD_OFS ( 8) /* HOLD Offset */
\r
14936 #define FLCTL_ERSVER_TIMCTL_HOLD_M (0x00000f00) /* */
\r
14937 /* FLCTL_LKGVER_TIMCTL[FLCTL_LKGVER_TIMCTL_SETUP] Bits */
\r
14938 #define FLCTL_LKGVER_TIMCTL_SETUP_OFS ( 0) /* SETUP Offset */
\r
14939 #define FLCTL_LKGVER_TIMCTL_SETUP_M (0x000000ff) /* */
\r
14940 /* FLCTL_LKGVER_TIMCTL[FLCTL_LKGVER_TIMCTL_HOLD] Bits */
\r
14941 #define FLCTL_LKGVER_TIMCTL_HOLD_OFS ( 8) /* HOLD Offset */
\r
14942 #define FLCTL_LKGVER_TIMCTL_HOLD_M (0x00000f00) /* */
\r
14943 /* FLCTL_PROGRAM_TIMCTL[FLCTL_PROGRAM_TIMCTL_SETUP] Bits */
\r
14944 #define FLCTL_PROGRAM_TIMCTL_SETUP_OFS ( 0) /* SETUP Offset */
\r
14945 #define FLCTL_PROGRAM_TIMCTL_SETUP_M (0x000000ff) /* */
\r
14946 /* FLCTL_PROGRAM_TIMCTL[FLCTL_PROGRAM_TIMCTL_ACTIVE] Bits */
\r
14947 #define FLCTL_PROGRAM_TIMCTL_ACTIVE_OFS ( 8) /* ACTIVE Offset */
\r
14948 #define FLCTL_PROGRAM_TIMCTL_ACTIVE_M (0x0fffff00) /* */
\r
14949 /* FLCTL_PROGRAM_TIMCTL[FLCTL_PROGRAM_TIMCTL_HOLD] Bits */
\r
14950 #define FLCTL_PROGRAM_TIMCTL_HOLD_OFS (28) /* HOLD Offset */
\r
14951 #define FLCTL_PROGRAM_TIMCTL_HOLD_M (0xf0000000) /* */
\r
14952 /* FLCTL_ERASE_TIMCTL[FLCTL_ERASE_TIMCTL_SETUP] Bits */
\r
14953 #define FLCTL_ERASE_TIMCTL_SETUP_OFS ( 0) /* SETUP Offset */
\r
14954 #define FLCTL_ERASE_TIMCTL_SETUP_M (0x000000ff) /* */
\r
14955 /* FLCTL_ERASE_TIMCTL[FLCTL_ERASE_TIMCTL_ACTIVE] Bits */
\r
14956 #define FLCTL_ERASE_TIMCTL_ACTIVE_OFS ( 8) /* ACTIVE Offset */
\r
14957 #define FLCTL_ERASE_TIMCTL_ACTIVE_M (0x0fffff00) /* */
\r
14958 /* FLCTL_ERASE_TIMCTL[FLCTL_ERASE_TIMCTL_HOLD] Bits */
\r
14959 #define FLCTL_ERASE_TIMCTL_HOLD_OFS (28) /* HOLD Offset */
\r
14960 #define FLCTL_ERASE_TIMCTL_HOLD_M (0xf0000000) /* */
\r
14961 /* FLCTL_MASSERASE_TIMCTL[FLCTL_MASSERASE_TIMCTL_BOOST_ACTIVE] Bits */
\r
14962 #define FLCTL_MASSERASE_TIMCTL_BOOST_ACTIVE_OFS ( 0) /* BOOST_ACTIVE Offset */
\r
14963 #define FLCTL_MASSERASE_TIMCTL_BOOST_ACTIVE_M (0x000000ff) /* */
\r
14964 /* FLCTL_MASSERASE_TIMCTL[FLCTL_MASSERASE_TIMCTL_BOOST_HOLD] Bits */
\r
14965 #define FLCTL_MASSERASE_TIMCTL_BOOST_HOLD_OFS ( 8) /* BOOST_HOLD Offset */
\r
14966 #define FLCTL_MASSERASE_TIMCTL_BOOST_HOLD_M (0x0000ff00) /* */
\r
14967 /* FLCTL_BURSTPRG_TIMCTL[FLCTL_BURSTPRG_TIMCTL_ACTIVE] Bits */
\r
14968 #define FLCTL_BURSTPRG_TIMCTL_ACTIVE_OFS ( 8) /* ACTIVE Offset */
\r
14969 #define FLCTL_BURSTPRG_TIMCTL_ACTIVE_M (0x0fffff00) /* */
\r
14972 //*****************************************************************************
\r
14974 //*****************************************************************************
\r
14975 /* FPB_FP_CTRL[FPB_FP_CTRL_ENABLE] Bits */
\r
14976 #define FPB_FP_CTRL_ENABLE_OFS ( 0) /* ENABLE Offset */
\r
14977 #define FPB_FP_CTRL_ENABLE (0x00000001) /* */
\r
14978 /* FPB_FP_CTRL[FPB_FP_CTRL_KEY] Bits */
\r
14979 #define FPB_FP_CTRL_KEY_OFS ( 1) /* KEY Offset */
\r
14980 #define FPB_FP_CTRL_KEY (0x00000002) /* */
\r
14981 /* FPB_FP_CTRL[FPB_FP_CTRL_NUM_CODE1] Bits */
\r
14982 #define FPB_FP_CTRL_NUM_CODE1_OFS ( 4) /* NUM_CODE1 Offset */
\r
14983 #define FPB_FP_CTRL_NUM_CODE1_M (0x000000f0) /* */
\r
14984 #define FPB_FP_CTRL_NUM_CODE10 (0x00000010) /* */
\r
14985 #define FPB_FP_CTRL_NUM_CODE11 (0x00000020) /* */
\r
14986 #define FPB_FP_CTRL_NUM_CODE12 (0x00000040) /* */
\r
14987 #define FPB_FP_CTRL_NUM_CODE13 (0x00000080) /* */
\r
14988 #define FPB_FP_CTRL_NUM_CODE1_0 (0x00000000) /* no code slots */
\r
14989 #define FPB_FP_CTRL_NUM_CODE1_2 (0x00000020) /* two code slots */
\r
14990 #define FPB_FP_CTRL_NUM_CODE1_6 (0x00000060) /* six code slots */
\r
14991 /* FPB_FP_CTRL[FPB_FP_CTRL_NUM_LIT] Bits */
\r
14992 #define FPB_FP_CTRL_NUM_LIT_OFS ( 8) /* NUM_LIT Offset */
\r
14993 #define FPB_FP_CTRL_NUM_LIT_M (0x00000f00) /* */
\r
14994 #define FPB_FP_CTRL_NUM_LIT0 (0x00000100) /* */
\r
14995 #define FPB_FP_CTRL_NUM_LIT1 (0x00000200) /* */
\r
14996 #define FPB_FP_CTRL_NUM_LIT2 (0x00000400) /* */
\r
14997 #define FPB_FP_CTRL_NUM_LIT3 (0x00000800) /* */
\r
14998 #define FPB_FP_CTRL_NUM_LIT_0 (0x00000000) /* no literal slots */
\r
14999 #define FPB_FP_CTRL_NUM_LIT_2 (0x00000200) /* two literal slots */
\r
15000 /* FPB_FP_CTRL[FPB_FP_CTRL_NUM_CODE2] Bits */
\r
15001 #define FPB_FP_CTRL_NUM_CODE2_OFS (12) /* NUM_CODE2 Offset */
\r
15002 #define FPB_FP_CTRL_NUM_CODE2_M (0x00003000) /* */
\r
15003 /* FPB_FP_REMAP[FPB_FP_REMAP_REMAP] Bits */
\r
15004 #define FPB_FP_REMAP_REMAP_OFS ( 5) /* REMAP Offset */
\r
15005 #define FPB_FP_REMAP_REMAP_M (0x1fffffe0) /* */
\r
15006 /* FPB_FP_COMP0[FPB_FP_COMP0_ENABLE] Bits */
\r
15007 #define FPB_FP_COMP0_ENABLE_OFS ( 0) /* ENABLE Offset */
\r
15008 #define FPB_FP_COMP0_ENABLE (0x00000001) /* */
\r
15009 /* FPB_FP_COMP0[FPB_FP_COMP0_COMP] Bits */
\r
15010 #define FPB_FP_COMP0_COMP_OFS ( 2) /* COMP Offset */
\r
15011 #define FPB_FP_COMP0_COMP_M (0x1ffffffc) /* */
\r
15012 /* FPB_FP_COMP0[FPB_FP_COMP0_REPLACE] Bits */
\r
15013 #define FPB_FP_COMP0_REPLACE_OFS (30) /* REPLACE Offset */
\r
15014 #define FPB_FP_COMP0_REPLACE_M (0xc0000000) /* */
\r
15015 #define FPB_FP_COMP0_REPLACE0 (0x40000000) /* */
\r
15016 #define FPB_FP_COMP0_REPLACE1 (0x80000000) /* */
\r
15017 #define FPB_FP_COMP0_REPLACE_0 (0x00000000) /* remap to remap address. See FP_REMAP */
\r
15018 #define FPB_FP_COMP0_REPLACE_1 (0x40000000) /* set BKPT on lower halfword, upper is unaffected */
\r
15019 #define FPB_FP_COMP0_REPLACE_2 (0x80000000) /* set BKPT on upper halfword, lower is unaffected */
\r
15020 #define FPB_FP_COMP0_REPLACE_3 (0xc0000000) /* set BKPT on both lower and upper halfwords. */
\r
15021 /* FPB_FP_COMP1[FPB_FP_COMP1_ENABLE] Bits */
\r
15022 #define FPB_FP_COMP1_ENABLE_OFS ( 0) /* ENABLE Offset */
\r
15023 #define FPB_FP_COMP1_ENABLE (0x00000001) /* */
\r
15024 /* FPB_FP_COMP1[FPB_FP_COMP1_COMP] Bits */
\r
15025 #define FPB_FP_COMP1_COMP_OFS ( 2) /* COMP Offset */
\r
15026 #define FPB_FP_COMP1_COMP_M (0x1ffffffc) /* */
\r
15027 /* FPB_FP_COMP1[FPB_FP_COMP1_REPLACE] Bits */
\r
15028 #define FPB_FP_COMP1_REPLACE_OFS (30) /* REPLACE Offset */
\r
15029 #define FPB_FP_COMP1_REPLACE_M (0xc0000000) /* */
\r
15030 #define FPB_FP_COMP1_REPLACE0 (0x40000000) /* */
\r
15031 #define FPB_FP_COMP1_REPLACE1 (0x80000000) /* */
\r
15032 #define FPB_FP_COMP1_REPLACE_0 (0x00000000) /* remap to remap address. See FP_REMAP */
\r
15033 #define FPB_FP_COMP1_REPLACE_1 (0x40000000) /* set BKPT on lower halfword, upper is unaffected */
\r
15034 #define FPB_FP_COMP1_REPLACE_2 (0x80000000) /* set BKPT on upper halfword, lower is unaffected */
\r
15035 #define FPB_FP_COMP1_REPLACE_3 (0xc0000000) /* set BKPT on both lower and upper halfwords. */
\r
15036 /* FPB_FP_COMP2[FPB_FP_COMP2_ENABLE] Bits */
\r
15037 #define FPB_FP_COMP2_ENABLE_OFS ( 0) /* ENABLE Offset */
\r
15038 #define FPB_FP_COMP2_ENABLE (0x00000001) /* */
\r
15039 /* FPB_FP_COMP2[FPB_FP_COMP2_COMP] Bits */
\r
15040 #define FPB_FP_COMP2_COMP_OFS ( 2) /* COMP Offset */
\r
15041 #define FPB_FP_COMP2_COMP_M (0x1ffffffc) /* */
\r
15042 /* FPB_FP_COMP2[FPB_FP_COMP2_REPLACE] Bits */
\r
15043 #define FPB_FP_COMP2_REPLACE_OFS (30) /* REPLACE Offset */
\r
15044 #define FPB_FP_COMP2_REPLACE_M (0xc0000000) /* */
\r
15045 #define FPB_FP_COMP2_REPLACE0 (0x40000000) /* */
\r
15046 #define FPB_FP_COMP2_REPLACE1 (0x80000000) /* */
\r
15047 #define FPB_FP_COMP2_REPLACE_0 (0x00000000) /* remap to remap address. See FP_REMAP */
\r
15048 #define FPB_FP_COMP2_REPLACE_1 (0x40000000) /* set BKPT on lower halfword, upper is unaffected */
\r
15049 #define FPB_FP_COMP2_REPLACE_2 (0x80000000) /* set BKPT on upper halfword, lower is unaffected */
\r
15050 #define FPB_FP_COMP2_REPLACE_3 (0xc0000000) /* set BKPT on both lower and upper halfwords. */
\r
15051 /* FPB_FP_COMP3[FPB_FP_COMP3_ENABLE] Bits */
\r
15052 #define FPB_FP_COMP3_ENABLE_OFS ( 0) /* ENABLE Offset */
\r
15053 #define FPB_FP_COMP3_ENABLE (0x00000001) /* */
\r
15054 /* FPB_FP_COMP3[FPB_FP_COMP3_COMP] Bits */
\r
15055 #define FPB_FP_COMP3_COMP_OFS ( 2) /* COMP Offset */
\r
15056 #define FPB_FP_COMP3_COMP_M (0x1ffffffc) /* */
\r
15057 /* FPB_FP_COMP3[FPB_FP_COMP3_REPLACE] Bits */
\r
15058 #define FPB_FP_COMP3_REPLACE_OFS (30) /* REPLACE Offset */
\r
15059 #define FPB_FP_COMP3_REPLACE_M (0xc0000000) /* */
\r
15060 #define FPB_FP_COMP3_REPLACE0 (0x40000000) /* */
\r
15061 #define FPB_FP_COMP3_REPLACE1 (0x80000000) /* */
\r
15062 #define FPB_FP_COMP3_REPLACE_0 (0x00000000) /* remap to remap address. See FP_REMAP */
\r
15063 #define FPB_FP_COMP3_REPLACE_1 (0x40000000) /* set BKPT on lower halfword, upper is unaffected */
\r
15064 #define FPB_FP_COMP3_REPLACE_2 (0x80000000) /* set BKPT on upper halfword, lower is unaffected */
\r
15065 #define FPB_FP_COMP3_REPLACE_3 (0xc0000000) /* set BKPT on both lower and upper halfwords. */
\r
15066 /* FPB_FP_COMP4[FPB_FP_COMP4_ENABLE] Bits */
\r
15067 #define FPB_FP_COMP4_ENABLE_OFS ( 0) /* ENABLE Offset */
\r
15068 #define FPB_FP_COMP4_ENABLE (0x00000001) /* */
\r
15069 /* FPB_FP_COMP4[FPB_FP_COMP4_COMP] Bits */
\r
15070 #define FPB_FP_COMP4_COMP_OFS ( 2) /* COMP Offset */
\r
15071 #define FPB_FP_COMP4_COMP_M (0x1ffffffc) /* */
\r
15072 /* FPB_FP_COMP4[FPB_FP_COMP4_REPLACE] Bits */
\r
15073 #define FPB_FP_COMP4_REPLACE_OFS (30) /* REPLACE Offset */
\r
15074 #define FPB_FP_COMP4_REPLACE_M (0xc0000000) /* */
\r
15075 #define FPB_FP_COMP4_REPLACE0 (0x40000000) /* */
\r
15076 #define FPB_FP_COMP4_REPLACE1 (0x80000000) /* */
\r
15077 #define FPB_FP_COMP4_REPLACE_0 (0x00000000) /* remap to remap address. See FP_REMAP */
\r
15078 #define FPB_FP_COMP4_REPLACE_1 (0x40000000) /* set BKPT on lower halfword, upper is unaffected */
\r
15079 #define FPB_FP_COMP4_REPLACE_2 (0x80000000) /* set BKPT on upper halfword, lower is unaffected */
\r
15080 #define FPB_FP_COMP4_REPLACE_3 (0xc0000000) /* set BKPT on both lower and upper halfwords. */
\r
15081 /* FPB_FP_COMP5[FPB_FP_COMP5_ENABLE] Bits */
\r
15082 #define FPB_FP_COMP5_ENABLE_OFS ( 0) /* ENABLE Offset */
\r
15083 #define FPB_FP_COMP5_ENABLE (0x00000001) /* */
\r
15084 /* FPB_FP_COMP5[FPB_FP_COMP5_COMP] Bits */
\r
15085 #define FPB_FP_COMP5_COMP_OFS ( 2) /* COMP Offset */
\r
15086 #define FPB_FP_COMP5_COMP_M (0x1ffffffc) /* */
\r
15087 /* FPB_FP_COMP5[FPB_FP_COMP5_REPLACE] Bits */
\r
15088 #define FPB_FP_COMP5_REPLACE_OFS (30) /* REPLACE Offset */
\r
15089 #define FPB_FP_COMP5_REPLACE_M (0xc0000000) /* */
\r
15090 #define FPB_FP_COMP5_REPLACE0 (0x40000000) /* */
\r
15091 #define FPB_FP_COMP5_REPLACE1 (0x80000000) /* */
\r
15092 #define FPB_FP_COMP5_REPLACE_0 (0x00000000) /* remap to remap address. See FP_REMAP */
\r
15093 #define FPB_FP_COMP5_REPLACE_1 (0x40000000) /* set BKPT on lower halfword, upper is unaffected */
\r
15094 #define FPB_FP_COMP5_REPLACE_2 (0x80000000) /* set BKPT on upper halfword, lower is unaffected */
\r
15095 #define FPB_FP_COMP5_REPLACE_3 (0xc0000000) /* set BKPT on both lower and upper halfwords. */
\r
15096 /* FPB_FP_COMP6[FPB_FP_COMP6_ENABLE] Bits */
\r
15097 #define FPB_FP_COMP6_ENABLE_OFS ( 0) /* ENABLE Offset */
\r
15098 #define FPB_FP_COMP6_ENABLE (0x00000001) /* */
\r
15099 /* FPB_FP_COMP6[FPB_FP_COMP6_COMP] Bits */
\r
15100 #define FPB_FP_COMP6_COMP_OFS ( 2) /* COMP Offset */
\r
15101 #define FPB_FP_COMP6_COMP_M (0x1ffffffc) /* */
\r
15102 /* FPB_FP_COMP6[FPB_FP_COMP6_REPLACE] Bits */
\r
15103 #define FPB_FP_COMP6_REPLACE_OFS (30) /* REPLACE Offset */
\r
15104 #define FPB_FP_COMP6_REPLACE_M (0xc0000000) /* */
\r
15105 #define FPB_FP_COMP6_REPLACE0 (0x40000000) /* */
\r
15106 #define FPB_FP_COMP6_REPLACE1 (0x80000000) /* */
\r
15107 #define FPB_FP_COMP6_REPLACE_0 (0x00000000) /* remap to remap address. See FP_REMAP */
\r
15108 #define FPB_FP_COMP6_REPLACE_1 (0x40000000) /* set BKPT on lower halfword, upper is unaffected */
\r
15109 #define FPB_FP_COMP6_REPLACE_2 (0x80000000) /* set BKPT on upper halfword, lower is unaffected */
\r
15110 #define FPB_FP_COMP6_REPLACE_3 (0xc0000000) /* set BKPT on both lower and upper halfwords. */
\r
15111 /* FPB_FP_COMP7[FPB_FP_COMP7_ENABLE] Bits */
\r
15112 #define FPB_FP_COMP7_ENABLE_OFS ( 0) /* ENABLE Offset */
\r
15113 #define FPB_FP_COMP7_ENABLE (0x00000001) /* */
\r
15114 /* FPB_FP_COMP7[FPB_FP_COMP7_COMP] Bits */
\r
15115 #define FPB_FP_COMP7_COMP_OFS ( 2) /* COMP Offset */
\r
15116 #define FPB_FP_COMP7_COMP_M (0x1ffffffc) /* */
\r
15117 /* FPB_FP_COMP7[FPB_FP_COMP7_REPLACE] Bits */
\r
15118 #define FPB_FP_COMP7_REPLACE_OFS (30) /* REPLACE Offset */
\r
15119 #define FPB_FP_COMP7_REPLACE_M (0xc0000000) /* */
\r
15120 #define FPB_FP_COMP7_REPLACE0 (0x40000000) /* */
\r
15121 #define FPB_FP_COMP7_REPLACE1 (0x80000000) /* */
\r
15122 #define FPB_FP_COMP7_REPLACE_0 (0x00000000) /* remap to remap address. See FP_REMAP */
\r
15123 #define FPB_FP_COMP7_REPLACE_1 (0x40000000) /* set BKPT on lower halfword, upper is unaffected */
\r
15124 #define FPB_FP_COMP7_REPLACE_2 (0x80000000) /* set BKPT on upper halfword, lower is unaffected */
\r
15125 #define FPB_FP_COMP7_REPLACE_3 (0xc0000000) /* set BKPT on both lower and upper halfwords. */
\r
15128 //*****************************************************************************
\r
15130 //*****************************************************************************
\r
15131 /* FPU_FPCCR[FPU_FPCCR_ASPEN] Bits */
\r
15132 #define FPU_FPCCR_ASPEN_OFS (31) /* ASPEN Offset */
\r
15133 #define FPU_FPCCR_ASPEN (0x80000000) /* */
\r
15134 /* FPU_FPCCR[FPU_FPCCR_LSPEN] Bits */
\r
15135 #define FPU_FPCCR_LSPEN_OFS (30) /* LSPEN Offset */
\r
15136 #define FPU_FPCCR_LSPEN (0x40000000) /* */
\r
15137 /* FPU_FPCCR[FPU_FPCCR_MONRDY] Bits */
\r
15138 #define FPU_FPCCR_MONRDY_OFS ( 8) /* MONRDY Offset */
\r
15139 #define FPU_FPCCR_MONRDY (0x00000100) /* */
\r
15140 /* FPU_FPCCR[FPU_FPCCR_BFRDY] Bits */
\r
15141 #define FPU_FPCCR_BFRDY_OFS ( 6) /* BFRDY Offset */
\r
15142 #define FPU_FPCCR_BFRDY (0x00000040) /* */
\r
15143 /* FPU_FPCCR[FPU_FPCCR_MMRDY] Bits */
\r
15144 #define FPU_FPCCR_MMRDY_OFS ( 5) /* MMRDY Offset */
\r
15145 #define FPU_FPCCR_MMRDY (0x00000020) /* */
\r
15146 /* FPU_FPCCR[FPU_FPCCR_HFRDY] Bits */
\r
15147 #define FPU_FPCCR_HFRDY_OFS ( 4) /* HFRDY Offset */
\r
15148 #define FPU_FPCCR_HFRDY (0x00000010) /* */
\r
15149 /* FPU_FPCCR[FPU_FPCCR_THREAD] Bits */
\r
15150 #define FPU_FPCCR_THREAD_OFS ( 3) /* THREAD Offset */
\r
15151 #define FPU_FPCCR_THREAD (0x00000008) /* */
\r
15152 /* FPU_FPCCR[FPU_FPCCR_USER] Bits */
\r
15153 #define FPU_FPCCR_USER_OFS ( 1) /* USER Offset */
\r
15154 #define FPU_FPCCR_USER (0x00000002) /* */
\r
15155 /* FPU_FPCCR[FPU_FPCCR_LSPACT] Bits */
\r
15156 #define FPU_FPCCR_LSPACT_OFS ( 0) /* LSPACT Offset */
\r
15157 #define FPU_FPCCR_LSPACT (0x00000001) /* */
\r
15158 /* FPU_FPCAR[FPU_FPCAR_ADDRESS] Bits */
\r
15159 #define FPU_FPCAR_ADDRESS_OFS ( 2) /* ADDRESS Offset */
\r
15160 #define FPU_FPCAR_ADDRESS_M (0x7ffffffc) /* */
\r
15161 /* FPU_FPDSCR[FPU_FPDSCR_AHP] Bits */
\r
15162 #define FPU_FPDSCR_AHP_OFS (26) /* AHP Offset */
\r
15163 #define FPU_FPDSCR_AHP (0x04000000) /* */
\r
15164 /* FPU_FPDSCR[FPU_FPDSCR_DN] Bits */
\r
15165 #define FPU_FPDSCR_DN_OFS (25) /* DN Offset */
\r
15166 #define FPU_FPDSCR_DN (0x02000000) /* */
\r
15167 /* FPU_FPDSCR[FPU_FPDSCR_FZ] Bits */
\r
15168 #define FPU_FPDSCR_FZ_OFS (24) /* FZ Offset */
\r
15169 #define FPU_FPDSCR_FZ (0x01000000) /* */
\r
15170 /* FPU_FPDSCR[FPU_FPDSCR_RMODE] Bits */
\r
15171 #define FPU_FPDSCR_RMODE_OFS (22) /* RMODE Offset */
\r
15172 #define FPU_FPDSCR_RMODE_M (0x00c00000) /* */
\r
15173 /* FPU_MVFR0[FPU_MVFR0_FP_ROUNDING_MODES] Bits */
\r
15174 #define FPU_MVFR0_FP_ROUNDING_MODES_OFS (28) /* FP_ROUNDING_MODES Offset */
\r
15175 #define FPU_MVFR0_FP_ROUNDING_MODES_M (0xf0000000) /* */
\r
15176 /* FPU_MVFR0[FPU_MVFR0_SHORT_VECTORS] Bits */
\r
15177 #define FPU_MVFR0_SHORT_VECTORS_OFS (24) /* SHORT_VECTORS Offset */
\r
15178 #define FPU_MVFR0_SHORT_VECTORS_M (0x0f000000) /* */
\r
15179 /* FPU_MVFR0[FPU_MVFR0_SQUARE_ROOT] Bits */
\r
15180 #define FPU_MVFR0_SQUARE_ROOT_OFS (20) /* SQUARE_ROOT Offset */
\r
15181 #define FPU_MVFR0_SQUARE_ROOT_M (0x00f00000) /* */
\r
15182 /* FPU_MVFR0[FPU_MVFR0_DIVIDE] Bits */
\r
15183 #define FPU_MVFR0_DIVIDE_OFS (16) /* DIVIDE Offset */
\r
15184 #define FPU_MVFR0_DIVIDE_M (0x000f0000) /* */
\r
15185 /* FPU_MVFR0[FPU_MVFR0_FP_ECEPTION_TRAPPING] Bits */
\r
15186 #define FPU_MVFR0_FP_ECEPTION_TRAPPING_OFS (12) /* FP_EXCEPTION_TRAPPING Offset */
\r
15187 #define FPU_MVFR0_FP_ECEPTION_TRAPPING_M (0x0000f000) /* */
\r
15188 /* FPU_MVFR0[FPU_MVFR0_DOUBLE_PRECISION] Bits */
\r
15189 #define FPU_MVFR0_DOUBLE_PRECISION_OFS ( 8) /* DOUBLE_PRECISION Offset */
\r
15190 #define FPU_MVFR0_DOUBLE_PRECISION_M (0x00000f00) /* */
\r
15191 /* FPU_MVFR0[FPU_MVFR0_SINGLE_PRECISION] Bits */
\r
15192 #define FPU_MVFR0_SINGLE_PRECISION_OFS ( 4) /* SINGLE_PRECISION Offset */
\r
15193 #define FPU_MVFR0_SINGLE_PRECISION_M (0x000000f0) /* */
\r
15194 /* FPU_MVFR0[FPU_MVFR0_A_SIMD_REGISTERS] Bits */
\r
15195 #define FPU_MVFR0_A_SIMD_REGISTERS_OFS ( 0) /* A_SIMD_REGISTERS Offset */
\r
15196 #define FPU_MVFR0_A_SIMD_REGISTERS_M (0x0000000f) /* */
\r
15197 /* FPU_MVFR1[FPU_MVFR1_FP_FUSED_MAC] Bits */
\r
15198 #define FPU_MVFR1_FP_FUSED_MAC_OFS (28) /* FP_FUSED_MAC Offset */
\r
15199 #define FPU_MVFR1_FP_FUSED_MAC_M (0xf0000000) /* */
\r
15200 /* FPU_MVFR1[FPU_MVFR1_FP_HPFP] Bits */
\r
15201 #define FPU_MVFR1_FP_HPFP_OFS (24) /* FP_HPFP Offset */
\r
15202 #define FPU_MVFR1_FP_HPFP_M (0x0f000000) /* */
\r
15203 /* FPU_MVFR1[FPU_MVFR1_D_NAN_MODE] Bits */
\r
15204 #define FPU_MVFR1_D_NAN_MODE_OFS ( 4) /* D_NAN_MODE Offset */
\r
15205 #define FPU_MVFR1_D_NAN_MODE_M (0x000000f0) /* */
\r
15206 /* FPU_MVFR1[FPU_MVFR1_FTZ_MODE] Bits */
\r
15207 #define FPU_MVFR1_FTZ_MODE_OFS ( 0) /* FTZ_MODE Offset */
\r
15208 #define FPU_MVFR1_FTZ_MODE_M (0x0000000f) /* */
\r
15211 //*****************************************************************************
\r
15213 //*****************************************************************************
\r
15214 /* ITM_TPR[ITM_TPR_PRIVMASK] Bits */
\r
15215 #define ITM_TPR_PRIVMASK_OFS ( 0) /* PRIVMASK Offset */
\r
15216 #define ITM_TPR_PRIVMASK_M (0x0000000f) /* */
\r
15217 /* ITM_TCR[ITM_TCR_ITMENA] Bits */
\r
15218 #define ITM_TCR_ITMENA_OFS ( 0) /* ITMENA Offset */
\r
15219 #define ITM_TCR_ITMENA (0x00000001) /* */
\r
15220 /* ITM_TCR[ITM_TCR_TSENA] Bits */
\r
15221 #define ITM_TCR_TSENA_OFS ( 1) /* TSENA Offset */
\r
15222 #define ITM_TCR_TSENA (0x00000002) /* */
\r
15223 /* ITM_TCR[ITM_TCR_SYNCENA] Bits */
\r
15224 #define ITM_TCR_SYNCENA_OFS ( 2) /* SYNCENA Offset */
\r
15225 #define ITM_TCR_SYNCENA (0x00000004) /* */
\r
15226 /* ITM_TCR[ITM_TCR_DWTENA] Bits */
\r
15227 #define ITM_TCR_DWTENA_OFS ( 3) /* DWTENA Offset */
\r
15228 #define ITM_TCR_DWTENA (0x00000008) /* */
\r
15229 /* ITM_TCR[ITM_TCR_SWOENA] Bits */
\r
15230 #define ITM_TCR_SWOENA_OFS ( 4) /* SWOENA Offset */
\r
15231 #define ITM_TCR_SWOENA (0x00000010) /* */
\r
15232 /* ITM_TCR[ITM_TCR_TSPRESCALE] Bits */
\r
15233 #define ITM_TCR_TSPRESCALE_OFS ( 8) /* TSPRESCALE Offset */
\r
15234 #define ITM_TCR_TSPRESCALE_M (0x00000300) /* */
\r
15235 #define ITM_TCR_TSPRESCALE0 (0x00000100) /* */
\r
15236 #define ITM_TCR_TSPRESCALE1 (0x00000200) /* */
\r
15237 #define ITM_TCR_TSPRESCALE_0 (0x00000000) /* no prescaling */
\r
15238 #define ITM_TCR_TSPRESCALE_1 (0x00000100) /* divide by 4 */
\r
15239 #define ITM_TCR_TSPRESCALE_2 (0x00000200) /* divide by 16 */
\r
15240 #define ITM_TCR_TSPRESCALE_3 (0x00000300) /* divide by 64 */
\r
15241 /* ITM_TCR[ITM_TCR_ATBID] Bits */
\r
15242 #define ITM_TCR_ATBID_OFS (16) /* ATBID Offset */
\r
15243 #define ITM_TCR_ATBID_M (0x007f0000) /* */
\r
15244 /* ITM_TCR[ITM_TCR_BUSY] Bits */
\r
15245 #define ITM_TCR_BUSY_OFS (23) /* BUSY Offset */
\r
15246 #define ITM_TCR_BUSY (0x00800000) /* */
\r
15247 /* ITM_IWR[ITM_IWR_ATVALIDM] Bits */
\r
15248 #define ITM_IWR_ATVALIDM_OFS ( 0) /* ATVALIDM Offset */
\r
15249 #define ITM_IWR_ATVALIDM (0x00000001) /* */
\r
15250 /* ITM_IMCR[ITM_IMCR_INTEGRATION] Bits */
\r
15251 #define ITM_IMCR_INTEGRATION_OFS ( 0) /* INTEGRATION Offset */
\r
15252 #define ITM_IMCR_INTEGRATION (0x00000001) /* */
\r
15253 /* ITM_LSR[ITM_LSR_PRESENT] Bits */
\r
15254 #define ITM_LSR_PRESENT_OFS ( 0) /* PRESENT Offset */
\r
15255 #define ITM_LSR_PRESENT (0x00000001) /* */
\r
15256 /* ITM_LSR[ITM_LSR_ACCESS] Bits */
\r
15257 #define ITM_LSR_ACCESS_OFS ( 1) /* ACCESS Offset */
\r
15258 #define ITM_LSR_ACCESS (0x00000002) /* */
\r
15259 /* ITM_LSR[ITM_LSR_BYTEACC] Bits */
\r
15260 #define ITM_LSR_BYTEACC_OFS ( 2) /* BYTEACC Offset */
\r
15261 #define ITM_LSR_BYTEACC (0x00000004) /* */
\r
15264 //*****************************************************************************
\r
15266 //*****************************************************************************
\r
15267 /* MPU_TYPE[MPU_TYPE_SEPARATE] Bits */
\r
15268 #define MPU_TYPE_SEPARATE_OFS ( 0) /* SEPARATE Offset */
\r
15269 #define MPU_TYPE_SEPARATE (0x00000001) /* */
\r
15270 /* MPU_TYPE[MPU_TYPE_DREGION] Bits */
\r
15271 #define MPU_TYPE_DREGION_OFS ( 8) /* DREGION Offset */
\r
15272 #define MPU_TYPE_DREGION_M (0x0000ff00) /* */
\r
15273 /* MPU_TYPE[MPU_TYPE_IREGION] Bits */
\r
15274 #define MPU_TYPE_IREGION_OFS (16) /* IREGION Offset */
\r
15275 #define MPU_TYPE_IREGION_M (0x00ff0000) /* */
\r
15276 /* MPU_CTRL[MPU_CTRL_ENABLE] Bits */
\r
15277 #define MPU_CTRL_ENABLE_OFS ( 0) /* ENABLE Offset */
\r
15278 #define MPU_CTRL_ENABLE (0x00000001) /* */
\r
15279 /* MPU_CTRL[MPU_CTRL_HFNMIENA] Bits */
\r
15280 #define MPU_CTRL_HFNMIENA_OFS ( 1) /* HFNMIENA Offset */
\r
15281 #define MPU_CTRL_HFNMIENA (0x00000002) /* */
\r
15282 /* MPU_CTRL[MPU_CTRL_PRIVDEFENA] Bits */
\r
15283 #define MPU_CTRL_PRIVDEFENA_OFS ( 2) /* PRIVDEFENA Offset */
\r
15284 #define MPU_CTRL_PRIVDEFENA (0x00000004) /* */
\r
15285 /* MPU_RNR[MPU_RNR_REGION] Bits */
\r
15286 #define MPU_RNR_REGION_OFS ( 0) /* REGION Offset */
\r
15287 #define MPU_RNR_REGION_M (0x000000ff) /* */
\r
15288 /* MPU_RBAR[MPU_RBAR_REGION] Bits */
\r
15289 #define MPU_RBAR_REGION_OFS ( 0) /* REGION Offset */
\r
15290 #define MPU_RBAR_REGION_M (0x0000000f) /* */
\r
15291 /* MPU_RBAR[MPU_RBAR_VALID] Bits */
\r
15292 #define MPU_RBAR_VALID_OFS ( 4) /* VALID Offset */
\r
15293 #define MPU_RBAR_VALID (0x00000010) /* */
\r
15294 /* MPU_RBAR[MPU_RBAR_ADDR] Bits */
\r
15295 #define MPU_RBAR_ADDR_OFS ( 5) /* ADDR Offset */
\r
15296 #define MPU_RBAR_ADDR_M (0xffffffe0) /* */
\r
15297 /* MPU_RASR[MPU_RASR_ENABLE] Bits */
\r
15298 #define MPU_RASR_ENABLE_OFS ( 0) /* ENABLE Offset */
\r
15299 #define MPU_RASR_ENABLE (0x00000001) /* */
\r
15300 /* MPU_RASR[MPU_RASR_SIZE] Bits */
\r
15301 #define MPU_RASR_SIZE_OFS ( 1) /* SIZE Offset */
\r
15302 #define MPU_RASR_SIZE_M (0x0000003e) /* */
\r
15303 #define MPU_RASR_SIZE0 (0x00000002) /* */
\r
15304 #define MPU_RASR_SIZE1 (0x00000004) /* */
\r
15305 #define MPU_RASR_SIZE2 (0x00000008) /* */
\r
15306 #define MPU_RASR_SIZE3 (0x00000010) /* */
\r
15307 #define MPU_RASR_SIZE4 (0x00000020) /* */
\r
15308 #define MPU_RASR_SIZE_0 (0x00000000) /* 4KB */
\r
15309 #define MPU_RASR_SIZE_1 (0x00000002) /* 256MB */
\r
15310 #define MPU_RASR_SIZE_4 (0x00000008) /* 32B */
\r
15311 #define MPU_RASR_SIZE_5 (0x0000000a) /* 64B */
\r
15312 #define MPU_RASR_SIZE_6 (0x0000000c) /* 128B */
\r
15313 #define MPU_RASR_SIZE_7 (0x0000000e) /* 256B */
\r
15314 #define MPU_RASR_SIZE_8 (0x00000010) /* 512B */
\r
15315 #define MPU_RASR_SIZE_9 (0x00000012) /* 1KB */
\r
15316 #define MPU_RASR_SIZE_10 (0x00000014) /* 2KB */
\r
15317 #define MPU_RASR_SIZE_12 (0x00000018) /* 8KB */
\r
15318 #define MPU_RASR_SIZE_13 (0x0000001a) /* 16KB */
\r
15319 #define MPU_RASR_SIZE_14 (0x0000001c) /* 32KB */
\r
15320 #define MPU_RASR_SIZE_15 (0x0000001e) /* 64KB */
\r
15321 #define MPU_RASR_SIZE_16 (0x00000020) /* 128KB */
\r
15322 #define MPU_RASR_SIZE_17 (0x00000022) /* 256KB */
\r
15323 #define MPU_RASR_SIZE_18 (0x00000024) /* 512KB */
\r
15324 #define MPU_RASR_SIZE_19 (0x00000026) /* 1MB */
\r
15325 #define MPU_RASR_SIZE_20 (0x00000028) /* 2MB */
\r
15326 #define MPU_RASR_SIZE_21 (0x0000002a) /* 4MB */
\r
15327 #define MPU_RASR_SIZE_22 (0x0000002c) /* 8MB */
\r
15328 #define MPU_RASR_SIZE_23 (0x0000002e) /* 16MB */
\r
15329 #define MPU_RASR_SIZE_24 (0x00000030) /* 32MB */
\r
15330 #define MPU_RASR_SIZE_25 (0x00000032) /* 64MB */
\r
15331 #define MPU_RASR_SIZE_26 (0x00000034) /* 128MB */
\r
15332 #define MPU_RASR_SIZE_28 (0x00000038) /* 512MB */
\r
15333 #define MPU_RASR_SIZE_29 (0x0000003a) /* 1GB */
\r
15334 #define MPU_RASR_SIZE_30 (0x0000003c) /* 2GB */
\r
15335 #define MPU_RASR_SIZE_31 (0x0000003e) /* 4GB */
\r
15336 /* MPU_RASR[MPU_RASR_SRD] Bits */
\r
15337 #define MPU_RASR_SRD_OFS ( 8) /* SRD Offset */
\r
15338 #define MPU_RASR_SRD_M (0x0000ff00) /* */
\r
15339 /* MPU_RASR[MPU_RASR_B] Bits */
\r
15340 #define MPU_RASR_B_OFS (16) /* B Offset */
\r
15341 #define MPU_RASR_B (0x00010000) /* */
\r
15342 /* MPU_RASR[MPU_RASR_C] Bits */
\r
15343 #define MPU_RASR_C_OFS (17) /* C Offset */
\r
15344 #define MPU_RASR_C (0x00020000) /* */
\r
15345 /* MPU_RASR[MPU_RASR_S] Bits */
\r
15346 #define MPU_RASR_S_OFS (18) /* S Offset */
\r
15347 #define MPU_RASR_S (0x00040000) /* */
\r
15348 /* MPU_RASR[MPU_RASR_TEX] Bits */
\r
15349 #define MPU_RASR_TEX_OFS (19) /* TEX Offset */
\r
15350 #define MPU_RASR_TEX_M (0x00380000) /* */
\r
15351 /* MPU_RASR[MPU_RASR_AP] Bits */
\r
15352 #define MPU_RASR_AP_OFS (24) /* AP Offset */
\r
15353 #define MPU_RASR_AP_M (0x07000000) /* */
\r
15354 #define MPU_RASR_AP0 (0x01000000) /* */
\r
15355 #define MPU_RASR_AP1 (0x02000000) /* */
\r
15356 #define MPU_RASR_AP2 (0x04000000) /* */
\r
15357 #define MPU_RASR_AP_0 (0x00000000) /* Priviliged permissions: No access. User permissions: No access. */
\r
15358 #define MPU_RASR_AP_1 (0x01000000) /* Priviliged permissions: Read-write. User permissions: No access. */
\r
15359 #define MPU_RASR_AP_2 (0x02000000) /* Priviliged permissions: Read-write. User permissions: Read-only. */
\r
15360 #define MPU_RASR_AP_3 (0x03000000) /* Priviliged permissions: Read-write. User permissions: Read-write. */
\r
15361 #define MPU_RASR_AP_5 (0x05000000) /* Priviliged permissions: Read-only. User permissions: No access. */
\r
15362 #define MPU_RASR_AP_6 (0x06000000) /* Priviliged permissions: Read-only. User permissions: Read-only. */
\r
15363 #define MPU_RASR_AP_7 (0x07000000) /* Priviliged permissions: Read-only. User permissions: Read-only. */
\r
15364 /* MPU_RASR[MPU_RASR_XN] Bits */
\r
15365 #define MPU_RASR_XN_OFS (28) /* XN Offset */
\r
15366 #define MPU_RASR_XN (0x10000000) /* */
\r
15368 /* Pre-defined bitfield values */
\r
15370 /* MPU_RASR_SIZE Bitfield Bits */
\r
15371 #define MPU_RASR_SIZE__4 (0x00000008) /* 64B */
\r
15372 #define MPU_RASR_SIZE__32B (0x00000008) /* 32B */
\r
15373 #define MPU_RASR_SIZE__64B (0x0000000c) /* 128B */
\r
15374 #define MPU_RASR_SIZE__256B (0x0000000e) /* 256B */
\r
15375 #define MPU_RASR_SIZE__512B (0x00000010) /* 512B */
\r
15376 #define MPU_RASR_SIZE__1K (0x00000012) /* 1KB */
\r
15377 #define MPU_RASR_SIZE__2K (0x00000014) /* 2KB */
\r
15378 #define MPU_RASR_SIZE__4K (0x00000016) /* 4KB */
\r
15379 #define MPU_RASR_SIZE__8K (0x00000018) /* 8KB */
\r
15380 #define MPU_RASR_SIZE__16K (0x0000001a) /* 16KB */
\r
15381 #define MPU_RASR_SIZE__32K (0x0000001c) /* 32KB */
\r
15382 #define MPU_RASR_SIZE__64K (0x0000001e) /* 64KB */
\r
15383 #define MPU_RASR_SIZE__128K (0x00000020) /* 128KB */
\r
15384 #define MPU_RASR_SIZE__256K (0x00000022) /* 256KB */
\r
15385 #define MPU_RASR_SIZE__512K (0x00000024) /* 512KB */
\r
15386 #define MPU_RASR_SIZE__1M (0x00000026) /* 1MB */
\r
15387 #define MPU_RASR_SIZE__2M (0x00000028) /* 2MB */
\r
15388 #define MPU_RASR_SIZE__4M (0x0000002a) /* 4MB */
\r
15389 #define MPU_RASR_SIZE__8M (0x0000002c) /* 8MB */
\r
15390 #define MPU_RASR_SIZE__16M (0x0000002e) /* 16MB */
\r
15391 #define MPU_RASR_SIZE__32M (0x00000030) /* 32MB */
\r
15392 #define MPU_RASR_SIZE__64M (0x00000032) /* 64MB */
\r
15393 #define MPU_RASR_SIZE__128M (0x00000034) /* 128MB */
\r
15394 #define MPU_RASR_SIZE__256M (0x00000036) /* 256MB */
\r
15395 #define MPU_RASR_SIZE__512M (0x00000038) /* 512MB */
\r
15396 #define MPU_RASR_SIZE__1G (0x0000003a) /* 1GB */
\r
15397 #define MPU_RASR_SIZE__2G (0x0000003c) /* 2GB */
\r
15398 #define MPU_RASR_SIZE__4G (0x0000003e) /* 4GB */
\r
15400 /* MPU_RASR_AP Bitfield Bits */
\r
15401 #define MPU_RASR_AP_PRV_NO_USR_NO (0x00000000) /* Priviliged permissions: No access. User permissions: No access. */
\r
15402 #define MPU_RASR_AP_PRV_RW_USR_NO (0x01000000) /* Priviliged permissions: Read-write. User permissions: No access. */
\r
15403 #define MPU_RASR_AP_PRV_RW_USR_RO (0x02000000) /* Priviliged permissions: Read-write. User permissions: Read-only. */
\r
15404 #define MPU_RASR_AP_PRV_RW_USR_RW (0x03000000) /* Priviliged permissions: Read-write. User permissions: Read-write. */
\r
15405 #define MPU_RASR_AP_PRV_RO_USR_NO (0x05000000) /* Priviliged permissions: Read-only. User permissions: No access. */
\r
15406 #define MPU_RASR_AP_PRV_RO_USR_RO (0x06000000) /* Priviliged permissions: Read-only. User permissions: Read-only. */
\r
15408 /* MPU_RASR_XN Bitfield Bits */
\r
15409 #define MPU_RASR_AP_EXEC (0x00000000) /* Instruction access enabled */
\r
15410 #define MPU_RASR_AP_NOEXEC (0x10000000) /* Instruction access disabled */
\r
15413 //*****************************************************************************
\r
15415 //*****************************************************************************
\r
15416 /* NVIC_IPR0[NVIC_IPR0_PRI_0] Bits */
\r
15417 #define NVIC_IPR0_PRI_0_OFS ( 0) /* PRI_0 Offset */
\r
15418 #define NVIC_IPR0_PRI_0_M (0x000000ff) /* */
\r
15419 /* NVIC_IPR0[NVIC_IPR0_PRI_1] Bits */
\r
15420 #define NVIC_IPR0_PRI_1_OFS ( 8) /* PRI_1 Offset */
\r
15421 #define NVIC_IPR0_PRI_1_M (0x0000ff00) /* */
\r
15422 /* NVIC_IPR0[NVIC_IPR0_PRI_2] Bits */
\r
15423 #define NVIC_IPR0_PRI_2_OFS (16) /* PRI_2 Offset */
\r
15424 #define NVIC_IPR0_PRI_2_M (0x00ff0000) /* */
\r
15425 /* NVIC_IPR0[NVIC_IPR0_PRI_3] Bits */
\r
15426 #define NVIC_IPR0_PRI_3_OFS (24) /* PRI_3 Offset */
\r
15427 #define NVIC_IPR0_PRI_3_M (0xff000000) /* */
\r
15428 /* NVIC_IPR1[NVIC_IPR1_PRI_4] Bits */
\r
15429 #define NVIC_IPR1_PRI_4_OFS ( 0) /* PRI_4 Offset */
\r
15430 #define NVIC_IPR1_PRI_4_M (0x000000ff) /* */
\r
15431 /* NVIC_IPR1[NVIC_IPR1_PRI_5] Bits */
\r
15432 #define NVIC_IPR1_PRI_5_OFS ( 8) /* PRI_5 Offset */
\r
15433 #define NVIC_IPR1_PRI_5_M (0x0000ff00) /* */
\r
15434 /* NVIC_IPR1[NVIC_IPR1_PRI_6] Bits */
\r
15435 #define NVIC_IPR1_PRI_6_OFS (16) /* PRI_6 Offset */
\r
15436 #define NVIC_IPR1_PRI_6_M (0x00ff0000) /* */
\r
15437 /* NVIC_IPR1[NVIC_IPR1_PRI_7] Bits */
\r
15438 #define NVIC_IPR1_PRI_7_OFS (24) /* PRI_7 Offset */
\r
15439 #define NVIC_IPR1_PRI_7_M (0xff000000) /* */
\r
15440 /* NVIC_IPR2[NVIC_IPR2_PRI_8] Bits */
\r
15441 #define NVIC_IPR2_PRI_8_OFS ( 0) /* PRI_8 Offset */
\r
15442 #define NVIC_IPR2_PRI_8_M (0x000000ff) /* */
\r
15443 /* NVIC_IPR2[NVIC_IPR2_PRI_9] Bits */
\r
15444 #define NVIC_IPR2_PRI_9_OFS ( 8) /* PRI_9 Offset */
\r
15445 #define NVIC_IPR2_PRI_9_M (0x0000ff00) /* */
\r
15446 /* NVIC_IPR2[NVIC_IPR2_PRI_10] Bits */
\r
15447 #define NVIC_IPR2_PRI_10_OFS (16) /* PRI_10 Offset */
\r
15448 #define NVIC_IPR2_PRI_10_M (0x00ff0000) /* */
\r
15449 /* NVIC_IPR2[NVIC_IPR2_PRI_11] Bits */
\r
15450 #define NVIC_IPR2_PRI_11_OFS (24) /* PRI_11 Offset */
\r
15451 #define NVIC_IPR2_PRI_11_M (0xff000000) /* */
\r
15452 /* NVIC_IPR3[NVIC_IPR3_PRI_12] Bits */
\r
15453 #define NVIC_IPR3_PRI_12_OFS ( 0) /* PRI_12 Offset */
\r
15454 #define NVIC_IPR3_PRI_12_M (0x000000ff) /* */
\r
15455 /* NVIC_IPR3[NVIC_IPR3_PRI_13] Bits */
\r
15456 #define NVIC_IPR3_PRI_13_OFS ( 8) /* PRI_13 Offset */
\r
15457 #define NVIC_IPR3_PRI_13_M (0x0000ff00) /* */
\r
15458 /* NVIC_IPR3[NVIC_IPR3_PRI_14] Bits */
\r
15459 #define NVIC_IPR3_PRI_14_OFS (16) /* PRI_14 Offset */
\r
15460 #define NVIC_IPR3_PRI_14_M (0x00ff0000) /* */
\r
15461 /* NVIC_IPR3[NVIC_IPR3_PRI_15] Bits */
\r
15462 #define NVIC_IPR3_PRI_15_OFS (24) /* PRI_15 Offset */
\r
15463 #define NVIC_IPR3_PRI_15_M (0xff000000) /* */
\r
15464 /* NVIC_IPR4[NVIC_IPR4_PRI_16] Bits */
\r
15465 #define NVIC_IPR4_PRI_16_OFS ( 0) /* PRI_16 Offset */
\r
15466 #define NVIC_IPR4_PRI_16_M (0x000000ff) /* */
\r
15467 /* NVIC_IPR4[NVIC_IPR4_PRI_17] Bits */
\r
15468 #define NVIC_IPR4_PRI_17_OFS ( 8) /* PRI_17 Offset */
\r
15469 #define NVIC_IPR4_PRI_17_M (0x0000ff00) /* */
\r
15470 /* NVIC_IPR4[NVIC_IPR4_PRI_18] Bits */
\r
15471 #define NVIC_IPR4_PRI_18_OFS (16) /* PRI_18 Offset */
\r
15472 #define NVIC_IPR4_PRI_18_M (0x00ff0000) /* */
\r
15473 /* NVIC_IPR4[NVIC_IPR4_PRI_19] Bits */
\r
15474 #define NVIC_IPR4_PRI_19_OFS (24) /* PRI_19 Offset */
\r
15475 #define NVIC_IPR4_PRI_19_M (0xff000000) /* */
\r
15476 /* NVIC_IPR5[NVIC_IPR5_PRI_20] Bits */
\r
15477 #define NVIC_IPR5_PRI_20_OFS ( 0) /* PRI_20 Offset */
\r
15478 #define NVIC_IPR5_PRI_20_M (0x000000ff) /* */
\r
15479 /* NVIC_IPR5[NVIC_IPR5_PRI_21] Bits */
\r
15480 #define NVIC_IPR5_PRI_21_OFS ( 8) /* PRI_21 Offset */
\r
15481 #define NVIC_IPR5_PRI_21_M (0x0000ff00) /* */
\r
15482 /* NVIC_IPR5[NVIC_IPR5_PRI_22] Bits */
\r
15483 #define NVIC_IPR5_PRI_22_OFS (16) /* PRI_22 Offset */
\r
15484 #define NVIC_IPR5_PRI_22_M (0x00ff0000) /* */
\r
15485 /* NVIC_IPR5[NVIC_IPR5_PRI_23] Bits */
\r
15486 #define NVIC_IPR5_PRI_23_OFS (24) /* PRI_23 Offset */
\r
15487 #define NVIC_IPR5_PRI_23_M (0xff000000) /* */
\r
15488 /* NVIC_IPR6[NVIC_IPR6_PRI_24] Bits */
\r
15489 #define NVIC_IPR6_PRI_24_OFS ( 0) /* PRI_24 Offset */
\r
15490 #define NVIC_IPR6_PRI_24_M (0x000000ff) /* */
\r
15491 /* NVIC_IPR6[NVIC_IPR6_PRI_25] Bits */
\r
15492 #define NVIC_IPR6_PRI_25_OFS ( 8) /* PRI_25 Offset */
\r
15493 #define NVIC_IPR6_PRI_25_M (0x0000ff00) /* */
\r
15494 /* NVIC_IPR6[NVIC_IPR6_PRI_26] Bits */
\r
15495 #define NVIC_IPR6_PRI_26_OFS (16) /* PRI_26 Offset */
\r
15496 #define NVIC_IPR6_PRI_26_M (0x00ff0000) /* */
\r
15497 /* NVIC_IPR6[NVIC_IPR6_PRI_27] Bits */
\r
15498 #define NVIC_IPR6_PRI_27_OFS (24) /* PRI_27 Offset */
\r
15499 #define NVIC_IPR6_PRI_27_M (0xff000000) /* */
\r
15500 /* NVIC_IPR7[NVIC_IPR7_PRI_28] Bits */
\r
15501 #define NVIC_IPR7_PRI_28_OFS ( 0) /* PRI_28 Offset */
\r
15502 #define NVIC_IPR7_PRI_28_M (0x000000ff) /* */
\r
15503 /* NVIC_IPR7[NVIC_IPR7_PRI_29] Bits */
\r
15504 #define NVIC_IPR7_PRI_29_OFS ( 8) /* PRI_29 Offset */
\r
15505 #define NVIC_IPR7_PRI_29_M (0x0000ff00) /* */
\r
15506 /* NVIC_IPR7[NVIC_IPR7_PRI_30] Bits */
\r
15507 #define NVIC_IPR7_PRI_30_OFS (16) /* PRI_30 Offset */
\r
15508 #define NVIC_IPR7_PRI_30_M (0x00ff0000) /* */
\r
15509 /* NVIC_IPR7[NVIC_IPR7_PRI_31] Bits */
\r
15510 #define NVIC_IPR7_PRI_31_OFS (24) /* PRI_31 Offset */
\r
15511 #define NVIC_IPR7_PRI_31_M (0xff000000) /* */
\r
15512 /* NVIC_IPR8[NVIC_IPR8_PRI_32] Bits */
\r
15513 #define NVIC_IPR8_PRI_32_OFS ( 0) /* PRI_32 Offset */
\r
15514 #define NVIC_IPR8_PRI_32_M (0x000000ff) /* */
\r
15515 /* NVIC_IPR8[NVIC_IPR8_PRI_33] Bits */
\r
15516 #define NVIC_IPR8_PRI_33_OFS ( 8) /* PRI_33 Offset */
\r
15517 #define NVIC_IPR8_PRI_33_M (0x0000ff00) /* */
\r
15518 /* NVIC_IPR8[NVIC_IPR8_PRI_34] Bits */
\r
15519 #define NVIC_IPR8_PRI_34_OFS (16) /* PRI_34 Offset */
\r
15520 #define NVIC_IPR8_PRI_34_M (0x00ff0000) /* */
\r
15521 /* NVIC_IPR8[NVIC_IPR8_PRI_35] Bits */
\r
15522 #define NVIC_IPR8_PRI_35_OFS (24) /* PRI_35 Offset */
\r
15523 #define NVIC_IPR8_PRI_35_M (0xff000000) /* */
\r
15524 /* NVIC_IPR9[NVIC_IPR9_PRI_36] Bits */
\r
15525 #define NVIC_IPR9_PRI_36_OFS ( 0) /* PRI_36 Offset */
\r
15526 #define NVIC_IPR9_PRI_36_M (0x000000ff) /* */
\r
15527 /* NVIC_IPR9[NVIC_IPR9_PRI_37] Bits */
\r
15528 #define NVIC_IPR9_PRI_37_OFS ( 8) /* PRI_37 Offset */
\r
15529 #define NVIC_IPR9_PRI_37_M (0x0000ff00) /* */
\r
15530 /* NVIC_IPR9[NVIC_IPR9_PRI_38] Bits */
\r
15531 #define NVIC_IPR9_PRI_38_OFS (16) /* PRI_38 Offset */
\r
15532 #define NVIC_IPR9_PRI_38_M (0x00ff0000) /* */
\r
15533 /* NVIC_IPR9[NVIC_IPR9_PRI_39] Bits */
\r
15534 #define NVIC_IPR9_PRI_39_OFS (24) /* PRI_39 Offset */
\r
15535 #define NVIC_IPR9_PRI_39_M (0xff000000) /* */
\r
15536 /* NVIC_IPR10[NVIC_IPR10_PRI_40] Bits */
\r
15537 #define NVIC_IPR10_PRI_40_OFS ( 0) /* PRI_40 Offset */
\r
15538 #define NVIC_IPR10_PRI_40_M (0x000000ff) /* */
\r
15539 /* NVIC_IPR10[NVIC_IPR10_PRI_41] Bits */
\r
15540 #define NVIC_IPR10_PRI_41_OFS ( 8) /* PRI_41 Offset */
\r
15541 #define NVIC_IPR10_PRI_41_M (0x0000ff00) /* */
\r
15542 /* NVIC_IPR10[NVIC_IPR10_PRI_42] Bits */
\r
15543 #define NVIC_IPR10_PRI_42_OFS (16) /* PRI_42 Offset */
\r
15544 #define NVIC_IPR10_PRI_42_M (0x00ff0000) /* */
\r
15545 /* NVIC_IPR10[NVIC_IPR10_PRI_43] Bits */
\r
15546 #define NVIC_IPR10_PRI_43_OFS (24) /* PRI_43 Offset */
\r
15547 #define NVIC_IPR10_PRI_43_M (0xff000000) /* */
\r
15548 /* NVIC_IPR11[NVIC_IPR11_PRI_44] Bits */
\r
15549 #define NVIC_IPR11_PRI_44_OFS ( 0) /* PRI_44 Offset */
\r
15550 #define NVIC_IPR11_PRI_44_M (0x000000ff) /* */
\r
15551 /* NVIC_IPR11[NVIC_IPR11_PRI_45] Bits */
\r
15552 #define NVIC_IPR11_PRI_45_OFS ( 8) /* PRI_45 Offset */
\r
15553 #define NVIC_IPR11_PRI_45_M (0x0000ff00) /* */
\r
15554 /* NVIC_IPR11[NVIC_IPR11_PRI_46] Bits */
\r
15555 #define NVIC_IPR11_PRI_46_OFS (16) /* PRI_46 Offset */
\r
15556 #define NVIC_IPR11_PRI_46_M (0x00ff0000) /* */
\r
15557 /* NVIC_IPR11[NVIC_IPR11_PRI_47] Bits */
\r
15558 #define NVIC_IPR11_PRI_47_OFS (24) /* PRI_47 Offset */
\r
15559 #define NVIC_IPR11_PRI_47_M (0xff000000) /* */
\r
15560 /* NVIC_IPR12[NVIC_IPR12_PRI_48] Bits */
\r
15561 #define NVIC_IPR12_PRI_48_OFS ( 0) /* PRI_48 Offset */
\r
15562 #define NVIC_IPR12_PRI_48_M (0x000000ff) /* */
\r
15563 /* NVIC_IPR12[NVIC_IPR12_PRI_49] Bits */
\r
15564 #define NVIC_IPR12_PRI_49_OFS ( 8) /* PRI_49 Offset */
\r
15565 #define NVIC_IPR12_PRI_49_M (0x0000ff00) /* */
\r
15566 /* NVIC_IPR12[NVIC_IPR12_PRI_50] Bits */
\r
15567 #define NVIC_IPR12_PRI_50_OFS (16) /* PRI_50 Offset */
\r
15568 #define NVIC_IPR12_PRI_50_M (0x00ff0000) /* */
\r
15569 /* NVIC_IPR12[NVIC_IPR12_PRI_51] Bits */
\r
15570 #define NVIC_IPR12_PRI_51_OFS (24) /* PRI_51 Offset */
\r
15571 #define NVIC_IPR12_PRI_51_M (0xff000000) /* */
\r
15572 /* NVIC_IPR13[NVIC_IPR13_PRI_52] Bits */
\r
15573 #define NVIC_IPR13_PRI_52_OFS ( 0) /* PRI_52 Offset */
\r
15574 #define NVIC_IPR13_PRI_52_M (0x000000ff) /* */
\r
15575 /* NVIC_IPR13[NVIC_IPR13_PRI_53] Bits */
\r
15576 #define NVIC_IPR13_PRI_53_OFS ( 8) /* PRI_53 Offset */
\r
15577 #define NVIC_IPR13_PRI_53_M (0x0000ff00) /* */
\r
15578 /* NVIC_IPR13[NVIC_IPR13_PRI_54] Bits */
\r
15579 #define NVIC_IPR13_PRI_54_OFS (16) /* PRI_54 Offset */
\r
15580 #define NVIC_IPR13_PRI_54_M (0x00ff0000) /* */
\r
15581 /* NVIC_IPR13[NVIC_IPR13_PRI_55] Bits */
\r
15582 #define NVIC_IPR13_PRI_55_OFS (24) /* PRI_55 Offset */
\r
15583 #define NVIC_IPR13_PRI_55_M (0xff000000) /* */
\r
15584 /* NVIC_IPR14[NVIC_IPR14_PRI_56] Bits */
\r
15585 #define NVIC_IPR14_PRI_56_OFS ( 0) /* PRI_56 Offset */
\r
15586 #define NVIC_IPR14_PRI_56_M (0x000000ff) /* */
\r
15587 /* NVIC_IPR14[NVIC_IPR14_PRI_57] Bits */
\r
15588 #define NVIC_IPR14_PRI_57_OFS ( 8) /* PRI_57 Offset */
\r
15589 #define NVIC_IPR14_PRI_57_M (0x0000ff00) /* */
\r
15590 /* NVIC_IPR14[NVIC_IPR14_PRI_58] Bits */
\r
15591 #define NVIC_IPR14_PRI_58_OFS (16) /* PRI_58 Offset */
\r
15592 #define NVIC_IPR14_PRI_58_M (0x00ff0000) /* */
\r
15593 /* NVIC_IPR14[NVIC_IPR14_PRI_59] Bits */
\r
15594 #define NVIC_IPR14_PRI_59_OFS (24) /* PRI_59 Offset */
\r
15595 #define NVIC_IPR14_PRI_59_M (0xff000000) /* */
\r
15596 /* NVIC_IPR15[NVIC_IPR15_PRI_60] Bits */
\r
15597 #define NVIC_IPR15_PRI_60_OFS ( 0) /* PRI_60 Offset */
\r
15598 #define NVIC_IPR15_PRI_60_M (0x000000ff) /* */
\r
15599 /* NVIC_IPR15[NVIC_IPR15_PRI_61] Bits */
\r
15600 #define NVIC_IPR15_PRI_61_OFS ( 8) /* PRI_61 Offset */
\r
15601 #define NVIC_IPR15_PRI_61_M (0x0000ff00) /* */
\r
15602 /* NVIC_IPR15[NVIC_IPR15_PRI_62] Bits */
\r
15603 #define NVIC_IPR15_PRI_62_OFS (16) /* PRI_62 Offset */
\r
15604 #define NVIC_IPR15_PRI_62_M (0x00ff0000) /* */
\r
15605 /* NVIC_IPR15[NVIC_IPR15_PRI_63] Bits */
\r
15606 #define NVIC_IPR15_PRI_63_OFS (24) /* PRI_63 Offset */
\r
15607 #define NVIC_IPR15_PRI_63_M (0xff000000) /* */
\r
15608 /* NVIC_STIR[NVIC_STIR_INTID] Bits */
\r
15609 #define NVIC_STIR_INTID_OFS ( 0) /* INTID Offset */
\r
15610 #define NVIC_STIR_INTID_M (0x000001ff) /* */
\r
15613 //*****************************************************************************
\r
15615 //*****************************************************************************
\r
15616 /* PCMCTL0[AMR] Bits */
\r
15617 #define AMR_OFS ( 0) /* AMR Offset */
\r
15618 #define AMR_M (0x0000000f) /* Active Mode Request */
\r
15619 #define AMR0 (0x00000001) /* Active Mode Request */
\r
15620 #define AMR1 (0x00000002) /* Active Mode Request */
\r
15621 #define AMR2 (0x00000004) /* Active Mode Request */
\r
15622 #define AMR3 (0x00000008) /* Active Mode Request */
\r
15623 #define AMR_0 (0x00000000) /* LDO based Active Mode at Core voltage setting 0. */
\r
15624 #define AMR_1 (0x00000001) /* LDO based Active Mode at Core voltage setting 1. */
\r
15625 #define AMR_4 (0x00000004) /* DC-DC based Active Mode at Core voltage setting 0. */
\r
15626 #define AMR_5 (0x00000005) /* DC-DC based Active Mode at Core voltage setting 1. */
\r
15627 #define AMR_8 (0x00000008) /* Low-Frequency Active Mode at Core voltage setting 0. */
\r
15628 #define AMR_9 (0x00000009) /* Low-Frequency Active Mode at Core voltage setting 1. */
\r
15629 #define AMR__AM_LDO_VCORE0 (0x00000000) /* LDO based Active Mode at Core voltage setting 0. */
\r
15630 #define AMR__AM_LDO_VCORE1 (0x00000001) /* LDO based Active Mode at Core voltage setting 1. */
\r
15631 #define AMR__AM_DCDC_VCORE0 (0x00000004) /* DC-DC based Active Mode at Core voltage setting 0. */
\r
15632 #define AMR__AM_DCDC_VCORE1 (0x00000005) /* DC-DC based Active Mode at Core voltage setting 1. */
\r
15633 #define AMR__AM_LF_VCORE0 (0x00000008) /* Low-Frequency Active Mode at Core voltage setting 0. */
\r
15634 #define AMR__AM_LF_VCORE1 (0x00000009) /* Low-Frequency Active Mode at Core voltage setting 1. */
\r
15635 /* PCMCTL0[LPMR] Bits */
\r
15636 #define LPMR_OFS ( 4) /* LPMR Offset */
\r
15637 #define LPMR_M (0x000000f0) /* Low Power Mode Request */
\r
15638 #define LPMR0 (0x00000010) /* Low Power Mode Request */
\r
15639 #define LPMR1 (0x00000020) /* Low Power Mode Request */
\r
15640 #define LPMR2 (0x00000040) /* Low Power Mode Request */
\r
15641 #define LPMR3 (0x00000080) /* Low Power Mode Request */
\r
15642 #define LPMR_0 (0x00000000) /* LPM3. Core voltage setting is similar to the mode from which LPM3 is entered. */
\r
15643 #define LPMR_10 (0x000000a0) /* LPM3.5. Core voltage setting 0. */
\r
15644 #define LPMR_12 (0x000000c0) /* LPM4.5 */
\r
15645 #define LPMR__LPM3 (0x00000000) /* LPM3. Core voltage setting is similar to the mode from which LPM3 is entered. */
\r
15646 #define LPMR__LPM35 (0x000000a0) /* LPM3.5. Core voltage setting 0. */
\r
15647 #define LPMR__LPM45 (0x000000c0) /* LPM4.5 */
\r
15648 /* PCMCTL0[CPM] Bits */
\r
15649 #define CPM_OFS ( 8) /* CPM Offset */
\r
15650 #define CPM_M (0x00003f00) /* Current Power Mode */
\r
15651 #define CPM0 (0x00000100) /* Current Power Mode */
\r
15652 #define CPM1 (0x00000200) /* Current Power Mode */
\r
15653 #define CPM2 (0x00000400) /* Current Power Mode */
\r
15654 #define CPM3 (0x00000800) /* Current Power Mode */
\r
15655 #define CPM4 (0x00001000) /* Current Power Mode */
\r
15656 #define CPM5 (0x00002000) /* Current Power Mode */
\r
15657 #define CPM_0 (0x00000000) /* LDO based Active Mode at Core voltage setting 0. */
\r
15658 #define CPM_1 (0x00000100) /* LDO based Active Mode at Core voltage setting 1. */
\r
15659 #define CPM_4 (0x00000400) /* DC-DC based Active Mode at Core voltage setting 0. */
\r
15660 #define CPM_5 (0x00000500) /* DC-DC based Active Mode at Core voltage setting 1. */
\r
15661 #define CPM_8 (0x00000800) /* Low-Frequency Active Mode at Core voltage setting 0. */
\r
15662 #define CPM_9 (0x00000900) /* Low-Frequency Active Mode at Core voltage setting 1. */
\r
15663 #define CPM_16 (0x00001000) /* LDO based LPM0 at Core voltage setting 0. */
\r
15664 #define CPM_17 (0x00001100) /* LDO based LPM0 at Core voltage setting 1. */
\r
15665 #define CPM_20 (0x00001400) /* DC-DC based LPM0 at Core voltage setting 0. */
\r
15666 #define CPM_21 (0x00001500) /* DC-DC based LPM0 at Core voltage setting 1. */
\r
15667 #define CPM_24 (0x00001800) /* Low-Frequency LPM0 at Core voltage setting 0. */
\r
15668 #define CPM_25 (0x00001900) /* Low-Frequency LPM0 at Core voltage setting 1. */
\r
15669 #define CPM_32 (0x00002000) /* LPM3 */
\r
15670 #define CPM__AM_LDO_VCORE0 (0x00000000) /* LDO based Active Mode at Core voltage setting 0. */
\r
15671 #define CPM__AM_LDO_VCORE1 (0x00000100) /* LDO based Active Mode at Core voltage setting 1. */
\r
15672 #define CPM__AM_DCDC_VCORE0 (0x00000400) /* DC-DC based Active Mode at Core voltage setting 0. */
\r
15673 #define CPM__AM_DCDC_VCORE1 (0x00000500) /* DC-DC based Active Mode at Core voltage setting 1. */
\r
15674 #define CPM__AM_LF_VCORE0 (0x00000800) /* Low-Frequency Active Mode at Core voltage setting 0. */
\r
15675 #define CPM__AM_LF_VCORE1 (0x00000900) /* Low-Frequency Active Mode at Core voltage setting 1. */
\r
15676 #define CPM__LPM0_LDO_VCORE0 (0x00001000) /* LDO based LPM0 at Core voltage setting 0. */
\r
15677 #define CPM__LPM0_LDO_VCORE1 (0x00001100) /* LDO based LPM0 at Core voltage setting 1. */
\r
15678 #define CPM__LPM0_DCDC_VCORE0 (0x00001400) /* DC-DC based LPM0 at Core voltage setting 0. */
\r
15679 #define CPM__LPM0_DCDC_VCORE1 (0x00001500) /* DC-DC based LPM0 at Core voltage setting 1. */
\r
15680 #define CPM__LPM0_LF_VCORE0 (0x00001800) /* Low-Frequency LPM0 at Core voltage setting 0. */
\r
15681 #define CPM__LPM0_LF_VCORE1 (0x00001900) /* Low-Frequency LPM0 at Core voltage setting 1. */
\r
15682 #define CPM__LPM3 (0x00002000) /* LPM3 */
\r
15683 /* PCMCTL0[PCMKEY] Bits */
\r
15684 #define PCMKEY_OFS (16) /* PCMKEY Offset */
\r
15685 #define PCMKEY_M (0xffff0000) /* PCM key */
\r
15686 /* PCMCTL1[LOCKLPM5] Bits */
\r
15687 #define LOCKLPM5_OFS ( 0) /* LOCKLPM5 Offset */
\r
15688 #define LOCKLPM5 (0x00000001) /* Lock LPM5 */
\r
15689 /* PCMCTL1[LOCKBKUP] Bits */
\r
15690 #define LOCKBKUP_OFS ( 1) /* LOCKBKUP Offset */
\r
15691 #define LOCKBKUP (0x00000002) /* Lock Backup */
\r
15692 /* PCMCTL1[FORCE_LPM_ENTRY] Bits */
\r
15693 #define FORCE_LPM_ENTRY_OFS ( 2) /* FORCE_LPM_ENTRY Offset */
\r
15694 #define FORCE_LPM_ENTRY (0x00000004) /* Force LPM entry */
\r
15695 /* PCMCTL1[PMR_BUSY] Bits */
\r
15696 #define PMR_BUSY_OFS ( 8) /* PMR_BUSY Offset */
\r
15697 #define PMR_BUSY (0x00000100) /* Power mode request busy flag */
\r
15698 /* PCMCTL1[PCMKEY] Bits */
\r
15699 //#define PCMKEY_OFS (16) /* PCMKEY Offset */
\r
15700 //#define PCMKEY_M (0xffff0000) /* PCM key */
\r
15701 /* PCMIE[LPM_INVALID_TR_IE] Bits */
\r
15702 #define LPM_INVALID_TR_IE_OFS ( 0) /* LPM_INVALID_TR_IE Offset */
\r
15703 #define LPM_INVALID_TR_IE (0x00000001) /* LPM invalid transition interrupt enable */
\r
15704 /* PCMIE[LPM_INVALID_CLK_IE] Bits */
\r
15705 #define LPM_INVALID_CLK_IE_OFS ( 1) /* LPM_INVALID_CLK_IE Offset */
\r
15706 #define LPM_INVALID_CLK_IE (0x00000002) /* LPM invalid clock interrupt enable */
\r
15707 /* PCMIE[AM_INVALID_TR_IE] Bits */
\r
15708 #define AM_INVALID_TR_IE_OFS ( 2) /* AM_INVALID_TR_IE Offset */
\r
15709 #define AM_INVALID_TR_IE (0x00000004) /* Active mode invalid transition interrupt enable */
\r
15710 /* PCMIE[DCDC_ERROR_IE] Bits */
\r
15711 #define DCDC_ERROR_IE_OFS ( 6) /* DCDC_ERROR_IE Offset */
\r
15712 #define DCDC_ERROR_IE (0x00000040) /* DC-DC error interrupt enable */
\r
15713 /* PCMIFG[LPM_INVALID_TR_IFG] Bits */
\r
15714 #define LPM_INVALID_TR_IFG_OFS ( 0) /* LPM_INVALID_TR_IFG Offset */
\r
15715 #define LPM_INVALID_TR_IFG (0x00000001) /* LPM invalid transition flag */
\r
15716 /* PCMIFG[LPM_INVALID_CLK_IFG] Bits */
\r
15717 #define LPM_INVALID_CLK_IFG_OFS ( 1) /* LPM_INVALID_CLK_IFG Offset */
\r
15718 #define LPM_INVALID_CLK_IFG (0x00000002) /* LPM invalid clock flag */
\r
15719 /* PCMIFG[AM_INVALID_TR_IFG] Bits */
\r
15720 #define AM_INVALID_TR_IFG_OFS ( 2) /* AM_INVALID_TR_IFG Offset */
\r
15721 #define AM_INVALID_TR_IFG (0x00000004) /* Active mode invalid transition flag */
\r
15722 /* PCMIFG[DCDC_ERROR_IFG] Bits */
\r
15723 #define DCDC_ERROR_IFG_OFS ( 6) /* DCDC_ERROR_IFG Offset */
\r
15724 #define DCDC_ERROR_IFG (0x00000040) /* DC-DC error flag */
\r
15725 /* PCMCLRIFG[CLR_LPM_INVALID_TR_IFG] Bits */
\r
15726 #define CLR_LPM_INVALID_TR_IFG_OFS ( 0) /* CLR_LPM_INVALID_TR_IFG Offset */
\r
15727 #define CLR_LPM_INVALID_TR_IFG (0x00000001) /* Clear LPM invalid transition flag */
\r
15728 /* PCMCLRIFG[CLR_LPM_INVALID_CLK_IFG] Bits */
\r
15729 #define CLR_LPM_INVALID_CLK_IFG_OFS ( 1) /* CLR_LPM_INVALID_CLK_IFG Offset */
\r
15730 #define CLR_LPM_INVALID_CLK_IFG (0x00000002) /* Clear LPM invalid clock flag */
\r
15731 /* PCMCLRIFG[CLR_AM_INVALID_TR_IFG] Bits */
\r
15732 #define CLR_AM_INVALID_TR_IFG_OFS ( 2) /* CLR_AM_INVALID_TR_IFG Offset */
\r
15733 #define CLR_AM_INVALID_TR_IFG (0x00000004) /* Clear active mode invalid transition flag */
\r
15734 /* PCMCLRIFG[CLR_DCDC_ERROR_IFG] Bits */
\r
15735 #define CLR_DCDC_ERROR_IFG_OFS ( 6) /* CLR_DCDC_ERROR_IFG Offset */
\r
15736 #define CLR_DCDC_ERROR_IFG (0x00000040) /* Clear DC-DC error flag */
\r
15738 /* Pre-defined bitfield values */
\r
15739 #define PCM_PMR_KEY_VAL (0x695A0000) /* PCM key value */
\r
15740 #define PCM_CTL_KEY_VAL (0x695A0000) /* PCM key value */
\r
15743 //*****************************************************************************
\r
15745 //*****************************************************************************
\r
15746 /* PMAPCTL[PMAPLOCKED] Bits */
\r
15747 #define PMAPLOCKED_OFS ( 0) /* PMAPLOCKED Offset */
\r
15748 #define PMAPLOCKED (0x0001) /* Port mapping lock bit */
\r
15749 /* PMAPCTL[PMAPRECFG] Bits */
\r
15750 #define PMAPRECFG_OFS ( 1) /* PMAPRECFG Offset */
\r
15751 #define PMAPRECFG (0x0002) /* Port mapping reconfiguration control bit */
\r
15753 /* Pre-defined bitfield values */
\r
15754 #define PM_NONE 0
\r
15755 #define PM_UCA0CLK 1
\r
15756 #define PM_UCA0RXD 2
\r
15757 #define PM_UCA0SOMI 2
\r
15758 #define PM_UCA0TXD 3
\r
15759 #define PM_UCA0SIMO 3
\r
15760 #define PM_UCB0CLK 4
\r
15761 #define PM_UCB0SDA 5
\r
15762 #define PM_UCB0SIMO 5
\r
15763 #define PM_UCB0SCL 6
\r
15764 #define PM_UCB0SOMI 6
\r
15765 #define PM_UCA1STE 7
\r
15766 #define PM_UCA1CLK 8
\r
15767 #define PM_UCA1RXD 9
\r
15768 #define PM_UCA1SOMI 9
\r
15769 #define PM_UCA1TXD 10
\r
15770 #define PM_UCA1SIMO 10
\r
15771 #define PM_UCA2STE 11
\r
15772 #define PM_UCA2CLK 12
\r
15773 #define PM_UCA2RXD 13
\r
15774 #define PM_UCA2SOMI 13
\r
15775 #define PM_UCA2TXD 14
\r
15776 #define PM_UCA2SIMO 14
\r
15777 #define PM_UCB2STE 15
\r
15778 #define PM_UCB2CLK 16
\r
15779 #define PM_UCB2SDA 17
\r
15780 #define PM_UCB2SIMO 17
\r
15781 #define PM_UCB2SCL 18
\r
15782 #define PM_UCB2SOMI 18
\r
15783 #define PM_TA0CCR0A 19
\r
15784 #define PM_TA0CCR1A 20
\r
15785 #define PM_TA0CCR2A 21
\r
15786 #define PM_TA0CCR3A 22
\r
15787 #define PM_TA0CCR4A 23
\r
15788 #define PM_TA1CCR1A 24
\r
15789 #define PM_TA1CCR2A 25
\r
15790 #define PM_TA1CCR3A 26
\r
15791 #define PM_TA1CCR4A 27
\r
15792 #define PM_TA0CLK 28
\r
15793 #define PM_CE0OUT 28
\r
15794 #define PM_TA1CLK 29
\r
15795 #define PM_CE1OUT 29
\r
15796 #define PM_DMAE0 30
\r
15797 #define PM_SMCLK 30
\r
15798 #define PM_ANALOG 31
\r
15800 #define PMAP_KEYID_VAL (0x2D52) /* Port mapping controller write access key */
\r
15803 //*****************************************************************************
\r
15805 //*****************************************************************************
\r
15806 /* PSSKEY[PSSKEY] Bits */
\r
15807 #define PSSKEY_OFS ( 0) /* PSSKEY Offset */
\r
15808 #define PSSKEY_M (0x0000ffff) /* PSS control key */
\r
15809 /* PSSCTL0[SVSMHOFF] Bits */
\r
15810 #define SVSMHOFF_OFS ( 0) /* SVSMHOFF Offset */
\r
15811 #define SVSMHOFF (0x00000001) /* SVSM high-side off */
\r
15812 /* PSSCTL0[SVSMHLP] Bits */
\r
15813 #define SVSMHLP_OFS ( 1) /* SVSMHLP Offset */
\r
15814 #define SVSMHLP (0x00000002) /* SVSM high-side low power normal performance mode */
\r
15815 /* PSSCTL0[SVSMHS] Bits */
\r
15816 #define SVSMHS_OFS ( 2) /* SVSMHS Offset */
\r
15817 #define SVSMHS (0x00000004) /* Supply supervisor or monitor selection for the high-side */
\r
15818 /* PSSCTL0[SVSMHTH] Bits */
\r
15819 #define SVSMHTH_OFS ( 3) /* SVSMHTH Offset */
\r
15820 #define SVSMHTH_M (0x00000038) /* SVSM high-side reset voltage level */
\r
15821 /* PSSCTL0[SVMHOE] Bits */
\r
15822 #define SVMHOE_OFS ( 6) /* SVMHOE Offset */
\r
15823 #define SVMHOE (0x00000040) /* SVSM high-side output enable */
\r
15824 /* PSSCTL0[SVMHOUTPOLAL] Bits */
\r
15825 #define SVMHOUTPOLAL_OFS ( 7) /* SVMHOUTPOLAL Offset */
\r
15826 #define SVMHOUTPOLAL (0x00000080) /* SVMHOUT pin polarity active low */
\r
15827 /* PSSCTL0[SVSLOFF] Bits */
\r
15828 #define SVSLOFF_OFS ( 8) /* SVSLOFF Offset */
\r
15829 #define SVSLOFF (0x00000100) /* SVS low-side off */
\r
15830 /* PSSCTL0[SVSLLP] Bits */
\r
15831 #define SVSLLP_OFS ( 9) /* SVSLLP Offset */
\r
15832 #define SVSLLP (0x00000200) /* SVS low-side low power normal performance mode */
\r
15833 /* PSSCTL0[DCDC_FORCE] Bits */
\r
15834 #define DCDC_FORCE_OFS (10) /* DCDC_FORCE Offset */
\r
15835 #define DCDC_FORCE (0x00000400) /* Disables automatic supply voltage detection */
\r
15836 /* PSSCTL0[VCORETRAN] Bits */
\r
15837 #define VCORETRAN_OFS (12) /* VCORETRAN Offset */
\r
15838 #define VCORETRAN_M (0x00003000) /* Controls VCORE Level Transition time */
\r
15839 #define VCORETRAN0 (0x00001000) /* Controls VCORE Level Transition time */
\r
15840 #define VCORETRAN1 (0x00002000) /* Controls VCORE Level Transition time */
\r
15841 #define VCORETRAN_0 (0x00000000) /* 32 ?s / 100 mV */
\r
15842 #define VCORETRAN_1 (0x00001000) /* 64 ?s / 100 mV */
\r
15843 #define VCORETRAN_2 (0x00002000) /* 128 ?s / 100 mV (default) */
\r
15844 #define VCORETRAN_3 (0x00003000) /* 256 ?s / 100 mV */
\r
15845 #define VCORETRAN__32 (0x00000000) /* 32 ?s / 100 mV */
\r
15846 #define VCORETRAN__64 (0x00001000) /* 64 ?s / 100 mV */
\r
15847 #define VCORETRAN__128 (0x00002000) /* 128 ?s / 100 mV (default) */
\r
15848 #define VCORETRAN__256 (0x00003000) /* 256 ?s / 100 mV */
\r
15849 /* PSSIE[SVSMHIE] Bits */
\r
15850 #define SVSMHIE_OFS ( 1) /* SVSMHIE Offset */
\r
15851 #define SVSMHIE (0x00000002) /* High-side SVSM interrupt enable */
\r
15852 /* PSSIFG[SVSMHIFG] Bits */
\r
15853 #define SVSMHIFG_OFS ( 1) /* SVSMHIFG Offset */
\r
15854 #define SVSMHIFG (0x00000002) /* High-side SVSM interrupt flag */
\r
15855 /* PSSCLRIFG[CLRSVSMHIFG] Bits */
\r
15856 #define CLRSVSMHIFG_OFS ( 1) /* CLRSVSMHIFG Offset */
\r
15857 #define CLRSVSMHIFG (0x00000002) /* SVSMH clear interrupt flag */
\r
15859 /* Pre-defined bitfield values */
\r
15860 #define PSS_KEY_KEY_VAL (0x0000695A) /* PSS control key value */
\r
15863 //*****************************************************************************
\r
15865 //*****************************************************************************
\r
15866 /* REFCTL0[REFON] Bits */
\r
15867 #define REFON_OFS ( 0) /* REFON Offset */
\r
15868 #define REFON (0x0001) /* Reference enable */
\r
15869 /* REFCTL0[REFOUT] Bits */
\r
15870 #define REFOUT_OFS ( 1) /* REFOUT Offset */
\r
15871 #define REFOUT (0x0002) /* Reference output buffer */
\r
15872 /* REFCTL0[REFTCOFF] Bits */
\r
15873 #define REFTCOFF_OFS ( 3) /* REFTCOFF Offset */
\r
15874 #define REFTCOFF (0x0008) /* Temperature sensor disabled */
\r
15875 /* REFCTL0[REFVSEL] Bits */
\r
15876 #define REFVSEL_OFS ( 4) /* REFVSEL Offset */
\r
15877 #define REFVSEL_M (0x0030) /* Reference voltage level select */
\r
15878 #define REFVSEL0 (0x0010) /* Reference voltage level select */
\r
15879 #define REFVSEL1 (0x0020) /* Reference voltage level select */
\r
15880 #define REFVSEL_0 (0x0000) /* 1.2 V available when reference requested or REFON = 1 */
\r
15881 #define REFVSEL_1 (0x0010) /* 1.45 V available when reference requested or REFON = 1 */
\r
15882 #define REFVSEL_3 (0x0030) /* 2.5 V available when reference requested or REFON = 1 */
\r
15883 /* REFCTL0[REFGENOT] Bits */
\r
15884 #define REFGENOT_OFS ( 6) /* REFGENOT Offset */
\r
15885 #define REFGENOT (0x0040) /* Reference generator one-time trigger */
\r
15886 /* REFCTL0[REFBGOT] Bits */
\r
15887 #define REFBGOT_OFS ( 7) /* REFBGOT Offset */
\r
15888 #define REFBGOT (0x0080) /* Bandgap and bandgap buffer one-time trigger */
\r
15889 /* REFCTL0[REFGENACT] Bits */
\r
15890 #define REFGENACT_OFS ( 8) /* REFGENACT Offset */
\r
15891 #define REFGENACT (0x0100) /* Reference generator active */
\r
15892 /* REFCTL0[REFBGACT] Bits */
\r
15893 #define REFBGACT_OFS ( 9) /* REFBGACT Offset */
\r
15894 #define REFBGACT (0x0200) /* Reference bandgap active */
\r
15895 /* REFCTL0[REFGENBUSY] Bits */
\r
15896 #define REFGENBUSY_OFS (10) /* REFGENBUSY Offset */
\r
15897 #define REFGENBUSY (0x0400) /* Reference generator busy */
\r
15898 /* REFCTL0[BGMODE] Bits */
\r
15899 #define BGMODE_OFS (11) /* BGMODE Offset */
\r
15900 #define BGMODE (0x0800) /* Bandgap mode */
\r
15901 /* REFCTL0[REFGENRDY] Bits */
\r
15902 #define REFGENRDY_OFS (12) /* REFGENRDY Offset */
\r
15903 #define REFGENRDY (0x1000) /* Variable reference voltage ready status */
\r
15904 /* REFCTL0[REFBGRDY] Bits */
\r
15905 #define REFBGRDY_OFS (13) /* REFBGRDY Offset */
\r
15906 #define REFBGRDY (0x2000) /* Buffered bandgap voltage ready status */
\r
15909 //*****************************************************************************
\r
15911 //*****************************************************************************
\r
15912 /* RSTCTL_RESET_REQ[RSTCTL_RESET_REQ_SOFT_REQ] Bits */
\r
15913 #define RSTCTL_RESET_REQ_SOFT_REQ_OFS ( 0) /* SOFT_REQ Offset */
\r
15914 #define RSTCTL_RESET_REQ_SOFT_REQ (0x00000001) /* Soft Reset request */
\r
15915 /* RSTCTL_RESET_REQ[RSTCTL_RESET_REQ_HARD_REQ] Bits */
\r
15916 #define RSTCTL_RESET_REQ_HARD_REQ_OFS ( 1) /* HARD_REQ Offset */
\r
15917 #define RSTCTL_RESET_REQ_HARD_REQ (0x00000002) /* Hard Reset request */
\r
15918 /* RSTCTL_RESET_REQ[RSTCTL_RESET_REQ_RSTKEY] Bits */
\r
15919 #define RSTCTL_RESET_REQ_RSTKEY_OFS ( 8) /* RSTKEY Offset */
\r
15920 #define RSTCTL_RESET_REQ_RSTKEY_M (0x0000ff00) /* Write key to unlock reset request bits */
\r
15921 /* RSTCTL_HARDRESET_CLR[RSTCTL_HARDRESET_CLR_SRC0] Bits */
\r
15922 #define RSTCTL_HARDRESET_CLR_SRC0_OFS ( 0) /* SRC0 Offset */
\r
15923 #define RSTCTL_HARDRESET_CLR_SRC0 (0x00000001) /* Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */
\r
15924 /* RSTCTL_HARDRESET_CLR[RSTCTL_HARDRESET_CLR_SRC1] Bits */
\r
15925 #define RSTCTL_HARDRESET_CLR_SRC1_OFS ( 1) /* SRC1 Offset */
\r
15926 #define RSTCTL_HARDRESET_CLR_SRC1 (0x00000002) /* Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */
\r
15927 /* RSTCTL_HARDRESET_CLR[RSTCTL_HARDRESET_CLR_SRC2] Bits */
\r
15928 #define RSTCTL_HARDRESET_CLR_SRC2_OFS ( 2) /* SRC2 Offset */
\r
15929 #define RSTCTL_HARDRESET_CLR_SRC2 (0x00000004) /* Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */
\r
15930 /* RSTCTL_HARDRESET_CLR[RSTCTL_HARDRESET_CLR_SRC3] Bits */
\r
15931 #define RSTCTL_HARDRESET_CLR_SRC3_OFS ( 3) /* SRC3 Offset */
\r
15932 #define RSTCTL_HARDRESET_CLR_SRC3 (0x00000008) /* Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */
\r
15933 /* RSTCTL_HARDRESET_CLR[RSTCTL_HARDRESET_CLR_SRC4] Bits */
\r
15934 #define RSTCTL_HARDRESET_CLR_SRC4_OFS ( 4) /* SRC4 Offset */
\r
15935 #define RSTCTL_HARDRESET_CLR_SRC4 (0x00000010) /* Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */
\r
15936 /* RSTCTL_HARDRESET_CLR[RSTCTL_HARDRESET_CLR_SRC5] Bits */
\r
15937 #define RSTCTL_HARDRESET_CLR_SRC5_OFS ( 5) /* SRC5 Offset */
\r
15938 #define RSTCTL_HARDRESET_CLR_SRC5 (0x00000020) /* Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */
\r
15939 /* RSTCTL_HARDRESET_CLR[RSTCTL_HARDRESET_CLR_SRC6] Bits */
\r
15940 #define RSTCTL_HARDRESET_CLR_SRC6_OFS ( 6) /* SRC6 Offset */
\r
15941 #define RSTCTL_HARDRESET_CLR_SRC6 (0x00000040) /* Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */
\r
15942 /* RSTCTL_HARDRESET_CLR[RSTCTL_HARDRESET_CLR_SRC7] Bits */
\r
15943 #define RSTCTL_HARDRESET_CLR_SRC7_OFS ( 7) /* SRC7 Offset */
\r
15944 #define RSTCTL_HARDRESET_CLR_SRC7 (0x00000080) /* Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */
\r
15945 /* RSTCTL_HARDRESET_CLR[RSTCTL_HARDRESET_CLR_SRC8] Bits */
\r
15946 #define RSTCTL_HARDRESET_CLR_SRC8_OFS ( 8) /* SRC8 Offset */
\r
15947 #define RSTCTL_HARDRESET_CLR_SRC8 (0x00000100) /* Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */
\r
15948 /* RSTCTL_HARDRESET_CLR[RSTCTL_HARDRESET_CLR_SRC9] Bits */
\r
15949 #define RSTCTL_HARDRESET_CLR_SRC9_OFS ( 9) /* SRC9 Offset */
\r
15950 #define RSTCTL_HARDRESET_CLR_SRC9 (0x00000200) /* Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */
\r
15951 /* RSTCTL_HARDRESET_CLR[RSTCTL_HARDRESET_CLR_SRC10] Bits */
\r
15952 #define RSTCTL_HARDRESET_CLR_SRC10_OFS (10) /* SRC10 Offset */
\r
15953 #define RSTCTL_HARDRESET_CLR_SRC10 (0x00000400) /* Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */
\r
15954 /* RSTCTL_HARDRESET_CLR[RSTCTL_HARDRESET_CLR_SRC11] Bits */
\r
15955 #define RSTCTL_HARDRESET_CLR_SRC11_OFS (11) /* SRC11 Offset */
\r
15956 #define RSTCTL_HARDRESET_CLR_SRC11 (0x00000800) /* Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */
\r
15957 /* RSTCTL_HARDRESET_CLR[RSTCTL_HARDRESET_CLR_SRC12] Bits */
\r
15958 #define RSTCTL_HARDRESET_CLR_SRC12_OFS (12) /* SRC12 Offset */
\r
15959 #define RSTCTL_HARDRESET_CLR_SRC12 (0x00001000) /* Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */
\r
15960 /* RSTCTL_HARDRESET_CLR[RSTCTL_HARDRESET_CLR_SRC13] Bits */
\r
15961 #define RSTCTL_HARDRESET_CLR_SRC13_OFS (13) /* SRC13 Offset */
\r
15962 #define RSTCTL_HARDRESET_CLR_SRC13 (0x00002000) /* Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */
\r
15963 /* RSTCTL_HARDRESET_CLR[RSTCTL_HARDRESET_CLR_SRC14] Bits */
\r
15964 #define RSTCTL_HARDRESET_CLR_SRC14_OFS (14) /* SRC14 Offset */
\r
15965 #define RSTCTL_HARDRESET_CLR_SRC14 (0x00004000) /* Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */
\r
15966 /* RSTCTL_HARDRESET_CLR[RSTCTL_HARDRESET_CLR_SRC15] Bits */
\r
15967 #define RSTCTL_HARDRESET_CLR_SRC15_OFS (15) /* SRC15 Offset */
\r
15968 #define RSTCTL_HARDRESET_CLR_SRC15 (0x00008000) /* Write 1 clears the corresponding bit in the RSTCTL_HRDRESETSTAT_REG */
\r
15969 /* RSTCTL_HARDRESET_SET[RSTCTL_HARDRESET_SET_SRC0] Bits */
\r
15970 #define RSTCTL_HARDRESET_SET_SRC0_OFS ( 0) /* SRC0 Offset */
\r
15971 #define RSTCTL_HARDRESET_SET_SRC0 (0x00000001) /* Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset) */
\r
15972 /* RSTCTL_HARDRESET_SET[RSTCTL_HARDRESET_SET_SRC1] Bits */
\r
15973 #define RSTCTL_HARDRESET_SET_SRC1_OFS ( 1) /* SRC1 Offset */
\r
15974 #define RSTCTL_HARDRESET_SET_SRC1 (0x00000002) /* Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset) */
\r
15975 /* RSTCTL_HARDRESET_SET[RSTCTL_HARDRESET_SET_SRC2] Bits */
\r
15976 #define RSTCTL_HARDRESET_SET_SRC2_OFS ( 2) /* SRC2 Offset */
\r
15977 #define RSTCTL_HARDRESET_SET_SRC2 (0x00000004) /* Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset) */
\r
15978 /* RSTCTL_HARDRESET_SET[RSTCTL_HARDRESET_SET_SRC3] Bits */
\r
15979 #define RSTCTL_HARDRESET_SET_SRC3_OFS ( 3) /* SRC3 Offset */
\r
15980 #define RSTCTL_HARDRESET_SET_SRC3 (0x00000008) /* Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset) */
\r
15981 /* RSTCTL_HARDRESET_SET[RSTCTL_HARDRESET_SET_SRC4] Bits */
\r
15982 #define RSTCTL_HARDRESET_SET_SRC4_OFS ( 4) /* SRC4 Offset */
\r
15983 #define RSTCTL_HARDRESET_SET_SRC4 (0x00000010) /* Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset) */
\r
15984 /* RSTCTL_HARDRESET_SET[RSTCTL_HARDRESET_SET_SRC5] Bits */
\r
15985 #define RSTCTL_HARDRESET_SET_SRC5_OFS ( 5) /* SRC5 Offset */
\r
15986 #define RSTCTL_HARDRESET_SET_SRC5 (0x00000020) /* Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset) */
\r
15987 /* RSTCTL_HARDRESET_SET[RSTCTL_HARDRESET_SET_SRC6] Bits */
\r
15988 #define RSTCTL_HARDRESET_SET_SRC6_OFS ( 6) /* SRC6 Offset */
\r
15989 #define RSTCTL_HARDRESET_SET_SRC6 (0x00000040) /* Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset) */
\r
15990 /* RSTCTL_HARDRESET_SET[RSTCTL_HARDRESET_SET_SRC7] Bits */
\r
15991 #define RSTCTL_HARDRESET_SET_SRC7_OFS ( 7) /* SRC7 Offset */
\r
15992 #define RSTCTL_HARDRESET_SET_SRC7 (0x00000080) /* Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset) */
\r
15993 /* RSTCTL_HARDRESET_SET[RSTCTL_HARDRESET_SET_SRC8] Bits */
\r
15994 #define RSTCTL_HARDRESET_SET_SRC8_OFS ( 8) /* SRC8 Offset */
\r
15995 #define RSTCTL_HARDRESET_SET_SRC8 (0x00000100) /* Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset) */
\r
15996 /* RSTCTL_HARDRESET_SET[RSTCTL_HARDRESET_SET_SRC9] Bits */
\r
15997 #define RSTCTL_HARDRESET_SET_SRC9_OFS ( 9) /* SRC9 Offset */
\r
15998 #define RSTCTL_HARDRESET_SET_SRC9 (0x00000200) /* Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset) */
\r
15999 /* RSTCTL_HARDRESET_SET[RSTCTL_HARDRESET_SET_SRC10] Bits */
\r
16000 #define RSTCTL_HARDRESET_SET_SRC10_OFS (10) /* SRC10 Offset */
\r
16001 #define RSTCTL_HARDRESET_SET_SRC10 (0x00000400) /* Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset) */
\r
16002 /* RSTCTL_HARDRESET_SET[RSTCTL_HARDRESET_SET_SRC11] Bits */
\r
16003 #define RSTCTL_HARDRESET_SET_SRC11_OFS (11) /* SRC11 Offset */
\r
16004 #define RSTCTL_HARDRESET_SET_SRC11 (0x00000800) /* Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset) */
\r
16005 /* RSTCTL_HARDRESET_SET[RSTCTL_HARDRESET_SET_SRC12] Bits */
\r
16006 #define RSTCTL_HARDRESET_SET_SRC12_OFS (12) /* SRC12 Offset */
\r
16007 #define RSTCTL_HARDRESET_SET_SRC12 (0x00001000) /* Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset) */
\r
16008 /* RSTCTL_HARDRESET_SET[RSTCTL_HARDRESET_SET_SRC13] Bits */
\r
16009 #define RSTCTL_HARDRESET_SET_SRC13_OFS (13) /* SRC13 Offset */
\r
16010 #define RSTCTL_HARDRESET_SET_SRC13 (0x00002000) /* Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset) */
\r
16011 /* RSTCTL_HARDRESET_SET[RSTCTL_HARDRESET_SET_SRC14] Bits */
\r
16012 #define RSTCTL_HARDRESET_SET_SRC14_OFS (14) /* SRC14 Offset */
\r
16013 #define RSTCTL_HARDRESET_SET_SRC14 (0x00004000) /* Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset) */
\r
16014 /* RSTCTL_HARDRESET_SET[RSTCTL_HARDRESET_SET_SRC15] Bits */
\r
16015 #define RSTCTL_HARDRESET_SET_SRC15_OFS (15) /* SRC15 Offset */
\r
16016 #define RSTCTL_HARDRESET_SET_SRC15 (0x00008000) /* Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset) */
\r
16017 /* RSTCTL_SOFTRESET_STAT[RSTCTL_SOFTRESET_STAT_SRC0] Bits */
\r
16018 #define RSTCTL_SOFTRESET_STAT_SRC0_OFS ( 0) /* SRC0 Offset */
\r
16019 #define RSTCTL_SOFTRESET_STAT_SRC0 (0x00000001) /* If 1, indicates that SRC0 was the source of the Soft Reset */
\r
16020 /* RSTCTL_SOFTRESET_STAT[RSTCTL_SOFTRESET_STAT_SRC1] Bits */
\r
16021 #define RSTCTL_SOFTRESET_STAT_SRC1_OFS ( 1) /* SRC1 Offset */
\r
16022 #define RSTCTL_SOFTRESET_STAT_SRC1 (0x00000002) /* If 1, indicates that SRC1 was the source of the Soft Reset */
\r
16023 /* RSTCTL_SOFTRESET_STAT[RSTCTL_SOFTRESET_STAT_SRC2] Bits */
\r
16024 #define RSTCTL_SOFTRESET_STAT_SRC2_OFS ( 2) /* SRC2 Offset */
\r
16025 #define RSTCTL_SOFTRESET_STAT_SRC2 (0x00000004) /* If 1, indicates that SRC2 was the source of the Soft Reset */
\r
16026 /* RSTCTL_SOFTRESET_STAT[RSTCTL_SOFTRESET_STAT_SRC3] Bits */
\r
16027 #define RSTCTL_SOFTRESET_STAT_SRC3_OFS ( 3) /* SRC3 Offset */
\r
16028 #define RSTCTL_SOFTRESET_STAT_SRC3 (0x00000008) /* If 1, indicates that SRC3 was the source of the Soft Reset */
\r
16029 /* RSTCTL_SOFTRESET_STAT[RSTCTL_SOFTRESET_STAT_SRC4] Bits */
\r
16030 #define RSTCTL_SOFTRESET_STAT_SRC4_OFS ( 4) /* SRC4 Offset */
\r
16031 #define RSTCTL_SOFTRESET_STAT_SRC4 (0x00000010) /* If 1, indicates that SRC4 was the source of the Soft Reset */
\r
16032 /* RSTCTL_SOFTRESET_STAT[RSTCTL_SOFTRESET_STAT_SRC5] Bits */
\r
16033 #define RSTCTL_SOFTRESET_STAT_SRC5_OFS ( 5) /* SRC5 Offset */
\r
16034 #define RSTCTL_SOFTRESET_STAT_SRC5 (0x00000020) /* If 1, indicates that SRC5 was the source of the Soft Reset */
\r
16035 /* RSTCTL_SOFTRESET_STAT[RSTCTL_SOFTRESET_STAT_SRC6] Bits */
\r
16036 #define RSTCTL_SOFTRESET_STAT_SRC6_OFS ( 6) /* SRC6 Offset */
\r
16037 #define RSTCTL_SOFTRESET_STAT_SRC6 (0x00000040) /* If 1, indicates that SRC6 was the source of the Soft Reset */
\r
16038 /* RSTCTL_SOFTRESET_STAT[RSTCTL_SOFTRESET_STAT_SRC7] Bits */
\r
16039 #define RSTCTL_SOFTRESET_STAT_SRC7_OFS ( 7) /* SRC7 Offset */
\r
16040 #define RSTCTL_SOFTRESET_STAT_SRC7 (0x00000080) /* If 1, indicates that SRC7 was the source of the Soft Reset */
\r
16041 /* RSTCTL_SOFTRESET_STAT[RSTCTL_SOFTRESET_STAT_SRC8] Bits */
\r
16042 #define RSTCTL_SOFTRESET_STAT_SRC8_OFS ( 8) /* SRC8 Offset */
\r
16043 #define RSTCTL_SOFTRESET_STAT_SRC8 (0x00000100) /* If 1, indicates that SRC8 was the source of the Soft Reset */
\r
16044 /* RSTCTL_SOFTRESET_STAT[RSTCTL_SOFTRESET_STAT_SRC9] Bits */
\r
16045 #define RSTCTL_SOFTRESET_STAT_SRC9_OFS ( 9) /* SRC9 Offset */
\r
16046 #define RSTCTL_SOFTRESET_STAT_SRC9 (0x00000200) /* If 1, indicates that SRC9 was the source of the Soft Reset */
\r
16047 /* RSTCTL_SOFTRESET_STAT[RSTCTL_SOFTRESET_STAT_SRC10] Bits */
\r
16048 #define RSTCTL_SOFTRESET_STAT_SRC10_OFS (10) /* SRC10 Offset */
\r
16049 #define RSTCTL_SOFTRESET_STAT_SRC10 (0x00000400) /* If 1, indicates that SRC10 was the source of the Soft Reset */
\r
16050 /* RSTCTL_SOFTRESET_STAT[RSTCTL_SOFTRESET_STAT_SRC11] Bits */
\r
16051 #define RSTCTL_SOFTRESET_STAT_SRC11_OFS (11) /* SRC11 Offset */
\r
16052 #define RSTCTL_SOFTRESET_STAT_SRC11 (0x00000800) /* If 1, indicates that SRC11 was the source of the Soft Reset */
\r
16053 /* RSTCTL_SOFTRESET_STAT[RSTCTL_SOFTRESET_STAT_SRC12] Bits */
\r
16054 #define RSTCTL_SOFTRESET_STAT_SRC12_OFS (12) /* SRC12 Offset */
\r
16055 #define RSTCTL_SOFTRESET_STAT_SRC12 (0x00001000) /* If 1, indicates that SRC12 was the source of the Soft Reset */
\r
16056 /* RSTCTL_SOFTRESET_STAT[RSTCTL_SOFTRESET_STAT_SRC13] Bits */
\r
16057 #define RSTCTL_SOFTRESET_STAT_SRC13_OFS (13) /* SRC13 Offset */
\r
16058 #define RSTCTL_SOFTRESET_STAT_SRC13 (0x00002000) /* If 1, indicates that SRC13 was the source of the Soft Reset */
\r
16059 /* RSTCTL_SOFTRESET_STAT[RSTCTL_SOFTRESET_STAT_SRC14] Bits */
\r
16060 #define RSTCTL_SOFTRESET_STAT_SRC14_OFS (14) /* SRC14 Offset */
\r
16061 #define RSTCTL_SOFTRESET_STAT_SRC14 (0x00004000) /* If 1, indicates that SRC14 was the source of the Soft Reset */
\r
16062 /* RSTCTL_SOFTRESET_STAT[RSTCTL_SOFTRESET_STAT_SRC15] Bits */
\r
16063 #define RSTCTL_SOFTRESET_STAT_SRC15_OFS (15) /* SRC15 Offset */
\r
16064 #define RSTCTL_SOFTRESET_STAT_SRC15 (0x00008000) /* If 1, indicates that SRC15 was the source of the Soft Reset */
\r
16065 /* RSTCTL_SOFTRESET_CLR[RSTCTL_SOFTRESET_CLR_SRC0] Bits */
\r
16066 #define RSTCTL_SOFTRESET_CLR_SRC0_OFS ( 0) /* SRC0 Offset */
\r
16067 #define RSTCTL_SOFTRESET_CLR_SRC0 (0x00000001) /* Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */
\r
16068 /* RSTCTL_SOFTRESET_CLR[RSTCTL_SOFTRESET_CLR_SRC1] Bits */
\r
16069 #define RSTCTL_SOFTRESET_CLR_SRC1_OFS ( 1) /* SRC1 Offset */
\r
16070 #define RSTCTL_SOFTRESET_CLR_SRC1 (0x00000002) /* Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */
\r
16071 /* RSTCTL_SOFTRESET_CLR[RSTCTL_SOFTRESET_CLR_SRC2] Bits */
\r
16072 #define RSTCTL_SOFTRESET_CLR_SRC2_OFS ( 2) /* SRC2 Offset */
\r
16073 #define RSTCTL_SOFTRESET_CLR_SRC2 (0x00000004) /* Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */
\r
16074 /* RSTCTL_SOFTRESET_CLR[RSTCTL_SOFTRESET_CLR_SRC3] Bits */
\r
16075 #define RSTCTL_SOFTRESET_CLR_SRC3_OFS ( 3) /* SRC3 Offset */
\r
16076 #define RSTCTL_SOFTRESET_CLR_SRC3 (0x00000008) /* Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */
\r
16077 /* RSTCTL_SOFTRESET_CLR[RSTCTL_SOFTRESET_CLR_SRC4] Bits */
\r
16078 #define RSTCTL_SOFTRESET_CLR_SRC4_OFS ( 4) /* SRC4 Offset */
\r
16079 #define RSTCTL_SOFTRESET_CLR_SRC4 (0x00000010) /* Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */
\r
16080 /* RSTCTL_SOFTRESET_CLR[RSTCTL_SOFTRESET_CLR_SRC5] Bits */
\r
16081 #define RSTCTL_SOFTRESET_CLR_SRC5_OFS ( 5) /* SRC5 Offset */
\r
16082 #define RSTCTL_SOFTRESET_CLR_SRC5 (0x00000020) /* Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */
\r
16083 /* RSTCTL_SOFTRESET_CLR[RSTCTL_SOFTRESET_CLR_SRC6] Bits */
\r
16084 #define RSTCTL_SOFTRESET_CLR_SRC6_OFS ( 6) /* SRC6 Offset */
\r
16085 #define RSTCTL_SOFTRESET_CLR_SRC6 (0x00000040) /* Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */
\r
16086 /* RSTCTL_SOFTRESET_CLR[RSTCTL_SOFTRESET_CLR_SRC7] Bits */
\r
16087 #define RSTCTL_SOFTRESET_CLR_SRC7_OFS ( 7) /* SRC7 Offset */
\r
16088 #define RSTCTL_SOFTRESET_CLR_SRC7 (0x00000080) /* Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */
\r
16089 /* RSTCTL_SOFTRESET_CLR[RSTCTL_SOFTRESET_CLR_SRC8] Bits */
\r
16090 #define RSTCTL_SOFTRESET_CLR_SRC8_OFS ( 8) /* SRC8 Offset */
\r
16091 #define RSTCTL_SOFTRESET_CLR_SRC8 (0x00000100) /* Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */
\r
16092 /* RSTCTL_SOFTRESET_CLR[RSTCTL_SOFTRESET_CLR_SRC9] Bits */
\r
16093 #define RSTCTL_SOFTRESET_CLR_SRC9_OFS ( 9) /* SRC9 Offset */
\r
16094 #define RSTCTL_SOFTRESET_CLR_SRC9 (0x00000200) /* Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */
\r
16095 /* RSTCTL_SOFTRESET_CLR[RSTCTL_SOFTRESET_CLR_SRC10] Bits */
\r
16096 #define RSTCTL_SOFTRESET_CLR_SRC10_OFS (10) /* SRC10 Offset */
\r
16097 #define RSTCTL_SOFTRESET_CLR_SRC10 (0x00000400) /* Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */
\r
16098 /* RSTCTL_SOFTRESET_CLR[RSTCTL_SOFTRESET_CLR_SRC11] Bits */
\r
16099 #define RSTCTL_SOFTRESET_CLR_SRC11_OFS (11) /* SRC11 Offset */
\r
16100 #define RSTCTL_SOFTRESET_CLR_SRC11 (0x00000800) /* Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */
\r
16101 /* RSTCTL_SOFTRESET_CLR[RSTCTL_SOFTRESET_CLR_SRC12] Bits */
\r
16102 #define RSTCTL_SOFTRESET_CLR_SRC12_OFS (12) /* SRC12 Offset */
\r
16103 #define RSTCTL_SOFTRESET_CLR_SRC12 (0x00001000) /* Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */
\r
16104 /* RSTCTL_SOFTRESET_CLR[RSTCTL_SOFTRESET_CLR_SRC13] Bits */
\r
16105 #define RSTCTL_SOFTRESET_CLR_SRC13_OFS (13) /* SRC13 Offset */
\r
16106 #define RSTCTL_SOFTRESET_CLR_SRC13 (0x00002000) /* Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */
\r
16107 /* RSTCTL_SOFTRESET_CLR[RSTCTL_SOFTRESET_CLR_SRC14] Bits */
\r
16108 #define RSTCTL_SOFTRESET_CLR_SRC14_OFS (14) /* SRC14 Offset */
\r
16109 #define RSTCTL_SOFTRESET_CLR_SRC14 (0x00004000) /* Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */
\r
16110 /* RSTCTL_SOFTRESET_CLR[RSTCTL_SOFTRESET_CLR_SRC15] Bits */
\r
16111 #define RSTCTL_SOFTRESET_CLR_SRC15_OFS (15) /* SRC15 Offset */
\r
16112 #define RSTCTL_SOFTRESET_CLR_SRC15 (0x00008000) /* Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */
\r
16113 /* RSTCTL_SOFTRESET_SET[RSTCTL_SOFTRESET_SET_SRC0] Bits */
\r
16114 #define RSTCTL_SOFTRESET_SET_SRC0_OFS ( 0) /* SRC0 Offset */
\r
16115 #define RSTCTL_SOFTRESET_SET_SRC0 (0x00000001) /* Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset) */
\r
16116 /* RSTCTL_SOFTRESET_SET[RSTCTL_SOFTRESET_SET_SRC1] Bits */
\r
16117 #define RSTCTL_SOFTRESET_SET_SRC1_OFS ( 1) /* SRC1 Offset */
\r
16118 #define RSTCTL_SOFTRESET_SET_SRC1 (0x00000002) /* Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset) */
\r
16119 /* RSTCTL_SOFTRESET_SET[RSTCTL_SOFTRESET_SET_SRC2] Bits */
\r
16120 #define RSTCTL_SOFTRESET_SET_SRC2_OFS ( 2) /* SRC2 Offset */
\r
16121 #define RSTCTL_SOFTRESET_SET_SRC2 (0x00000004) /* Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset) */
\r
16122 /* RSTCTL_SOFTRESET_SET[RSTCTL_SOFTRESET_SET_SRC3] Bits */
\r
16123 #define RSTCTL_SOFTRESET_SET_SRC3_OFS ( 3) /* SRC3 Offset */
\r
16124 #define RSTCTL_SOFTRESET_SET_SRC3 (0x00000008) /* Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset) */
\r
16125 /* RSTCTL_SOFTRESET_SET[RSTCTL_SOFTRESET_SET_SRC4] Bits */
\r
16126 #define RSTCTL_SOFTRESET_SET_SRC4_OFS ( 4) /* SRC4 Offset */
\r
16127 #define RSTCTL_SOFTRESET_SET_SRC4 (0x00000010) /* Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset) */
\r
16128 /* RSTCTL_SOFTRESET_SET[RSTCTL_SOFTRESET_SET_SRC5] Bits */
\r
16129 #define RSTCTL_SOFTRESET_SET_SRC5_OFS ( 5) /* SRC5 Offset */
\r
16130 #define RSTCTL_SOFTRESET_SET_SRC5 (0x00000020) /* Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset) */
\r
16131 /* RSTCTL_SOFTRESET_SET[RSTCTL_SOFTRESET_SET_SRC6] Bits */
\r
16132 #define RSTCTL_SOFTRESET_SET_SRC6_OFS ( 6) /* SRC6 Offset */
\r
16133 #define RSTCTL_SOFTRESET_SET_SRC6 (0x00000040) /* Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset) */
\r
16134 /* RSTCTL_SOFTRESET_SET[RSTCTL_SOFTRESET_SET_SRC7] Bits */
\r
16135 #define RSTCTL_SOFTRESET_SET_SRC7_OFS ( 7) /* SRC7 Offset */
\r
16136 #define RSTCTL_SOFTRESET_SET_SRC7 (0x00000080) /* Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset) */
\r
16137 /* RSTCTL_SOFTRESET_SET[RSTCTL_SOFTRESET_SET_SRC8] Bits */
\r
16138 #define RSTCTL_SOFTRESET_SET_SRC8_OFS ( 8) /* SRC8 Offset */
\r
16139 #define RSTCTL_SOFTRESET_SET_SRC8 (0x00000100) /* Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset) */
\r
16140 /* RSTCTL_SOFTRESET_SET[RSTCTL_SOFTRESET_SET_SRC9] Bits */
\r
16141 #define RSTCTL_SOFTRESET_SET_SRC9_OFS ( 9) /* SRC9 Offset */
\r
16142 #define RSTCTL_SOFTRESET_SET_SRC9 (0x00000200) /* Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset) */
\r
16143 /* RSTCTL_SOFTRESET_SET[RSTCTL_SOFTRESET_SET_SRC10] Bits */
\r
16144 #define RSTCTL_SOFTRESET_SET_SRC10_OFS (10) /* SRC10 Offset */
\r
16145 #define RSTCTL_SOFTRESET_SET_SRC10 (0x00000400) /* Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset) */
\r
16146 /* RSTCTL_SOFTRESET_SET[RSTCTL_SOFTRESET_SET_SRC11] Bits */
\r
16147 #define RSTCTL_SOFTRESET_SET_SRC11_OFS (11) /* SRC11 Offset */
\r
16148 #define RSTCTL_SOFTRESET_SET_SRC11 (0x00000800) /* Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset) */
\r
16149 /* RSTCTL_SOFTRESET_SET[RSTCTL_SOFTRESET_SET_SRC12] Bits */
\r
16150 #define RSTCTL_SOFTRESET_SET_SRC12_OFS (12) /* SRC12 Offset */
\r
16151 #define RSTCTL_SOFTRESET_SET_SRC12 (0x00001000) /* Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset) */
\r
16152 /* RSTCTL_SOFTRESET_SET[RSTCTL_SOFTRESET_SET_SRC13] Bits */
\r
16153 #define RSTCTL_SOFTRESET_SET_SRC13_OFS (13) /* SRC13 Offset */
\r
16154 #define RSTCTL_SOFTRESET_SET_SRC13 (0x00002000) /* Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset) */
\r
16155 /* RSTCTL_SOFTRESET_SET[RSTCTL_SOFTRESET_SET_SRC14] Bits */
\r
16156 #define RSTCTL_SOFTRESET_SET_SRC14_OFS (14) /* SRC14 Offset */
\r
16157 #define RSTCTL_SOFTRESET_SET_SRC14 (0x00004000) /* Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset) */
\r
16158 /* RSTCTL_SOFTRESET_SET[RSTCTL_SOFTRESET_SET_SRC15] Bits */
\r
16159 #define RSTCTL_SOFTRESET_SET_SRC15_OFS (15) /* SRC15 Offset */
\r
16160 #define RSTCTL_SOFTRESET_SET_SRC15 (0x00008000) /* Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset) */
\r
16161 /* RSTCTL_PSSRESET_STAT[RSTCTL_PSSRESET_STAT_SVSL] Bits */
\r
16162 #define RSTCTL_PSSRESET_STAT_SVSL_OFS ( 0) /* SVSL Offset */
\r
16163 #define RSTCTL_PSSRESET_STAT_SVSL (0x00000001) /* Indicates if POR was caused by an SVSL trip condition in the PSS */
\r
16164 /* RSTCTL_PSSRESET_STAT[RSTCTL_PSSRESET_STAT_SVSMH] Bits */
\r
16165 #define RSTCTL_PSSRESET_STAT_SVSMH_OFS ( 1) /* SVSMH Offset */
\r
16166 #define RSTCTL_PSSRESET_STAT_SVSMH (0x00000002) /* Indicates if POR was caused by an SVSMH trip condition int the PSS */
\r
16167 /* RSTCTL_PSSRESET_STAT[RSTCTL_PSSRESET_STAT_BGREF] Bits */
\r
16168 #define RSTCTL_PSSRESET_STAT_BGREF_OFS ( 2) /* BGREF Offset */
\r
16169 #define RSTCTL_PSSRESET_STAT_BGREF (0x00000004) /* Indicates if POR was caused by a BGREF not okay condition in the PSS */
\r
16170 /* RSTCTL_PSSRESET_STAT[RSTCTL_PSSRESET_STAT_VCCDET] Bits */
\r
16171 #define RSTCTL_PSSRESET_STAT_VCCDET_OFS ( 3) /* VCCDET Offset */
\r
16172 #define RSTCTL_PSSRESET_STAT_VCCDET (0x00000008) /* Indicates if POR was caused by a VCCDET trip condition in the PSS */
\r
16173 /* RSTCTL_PSSRESET_CLR[RSTCTL_PSSRESET_CLR_CLR] Bits */
\r
16174 #define RSTCTL_PSSRESET_CLR_CLR_OFS ( 0) /* CLR Offset */
\r
16175 #define RSTCTL_PSSRESET_CLR_CLR (0x00000001) /* Write 1 clears all PSS Reset Flags in the RSTCTL_PSSRESET_STAT */
\r
16176 /* RSTCTL_PCMRESET_STAT[RSTCTL_PCMRESET_STAT_LPM35] Bits */
\r
16177 #define RSTCTL_PCMRESET_STAT_LPM35_OFS ( 0) /* LPM35 Offset */
\r
16178 #define RSTCTL_PCMRESET_STAT_LPM35 (0x00000001) /* Indicates if POR was caused by PCM due to an exit from LPM3.5 */
\r
16179 /* RSTCTL_PCMRESET_STAT[RSTCTL_PCMRESET_STAT_LPM45] Bits */
\r
16180 #define RSTCTL_PCMRESET_STAT_LPM45_OFS ( 1) /* LPM45 Offset */
\r
16181 #define RSTCTL_PCMRESET_STAT_LPM45 (0x00000002) /* Indicates if POR was caused by PCM due to an exit from LPM4.5 */
\r
16182 /* RSTCTL_PCMRESET_CLR[RSTCTL_PCMRESET_CLR_CLR] Bits */
\r
16183 #define RSTCTL_PCMRESET_CLR_CLR_OFS ( 0) /* CLR Offset */
\r
16184 #define RSTCTL_PCMRESET_CLR_CLR (0x00000001) /* Write 1 clears all PCM Reset Flags in the RSTCTL_PCMRESET_STAT */
\r
16185 /* RSTCTL_PINRESET_STAT[RSTCTL_PINRESET_STAT_RSTNMI] Bits */
\r
16186 #define RSTCTL_PINRESET_STAT_RSTNMI_OFS ( 0) /* RSTNMI Offset */
\r
16187 #define RSTCTL_PINRESET_STAT_RSTNMI (0x00000001) /* POR was caused by RSTn/NMI pin based reset event */
\r
16188 /* RSTCTL_PINRESET_CLR[RSTCTL_PINRESET_CLR_CLR] Bits */
\r
16189 #define RSTCTL_PINRESET_CLR_CLR_OFS ( 0) /* CLR Offset */
\r
16190 #define RSTCTL_PINRESET_CLR_CLR (0x00000001) /* Write 1 clears the RSTn/NMI Pin Reset Flag in RSTCTL_PINRESET_STAT */
\r
16191 /* RSTCTL_REBOOTRESET_STAT[RSTCTL_REBOOTRESET_STAT_REBOOT] Bits */
\r
16192 #define RSTCTL_REBOOTRESET_STAT_REBOOT_OFS ( 0) /* REBOOT Offset */
\r
16193 #define RSTCTL_REBOOTRESET_STAT_REBOOT (0x00000001) /* Indicates if Reboot reset was caused by the SYSCTL module. */
\r
16194 /* RSTCTL_REBOOTRESET_CLR[RSTCTL_REBOOTRESET_CLR_CLR] Bits */
\r
16195 #define RSTCTL_REBOOTRESET_CLR_CLR_OFS ( 0) /* CLR Offset */
\r
16196 #define RSTCTL_REBOOTRESET_CLR_CLR (0x00000001) /* Write 1 clears the Reboot Reset Flag in RSTCTL_REBOOTRESET_STAT */
\r
16198 /* Pre-defined bitfield values */
\r
16199 #define RSTCTL_RESETREQ_RSTKEY_VAL (0x00006900) /* Key value to enable writes to bits 1-0 */
\r
16202 //*****************************************************************************
\r
16204 //*****************************************************************************
\r
16205 /* RTCCTL0[RTCRDYIFG] Bits */
\r
16206 #define RTCRDYIFG_OFS ( 0) /* RTCRDYIFG Offset */
\r
16207 #define RTCRDYIFG (0x0001) /* Real-time clock ready interrupt flag */
\r
16208 /* RTCCTL0[RTCAIFG] Bits */
\r
16209 #define RTCAIFG_OFS ( 1) /* RTCAIFG Offset */
\r
16210 #define RTCAIFG (0x0002) /* Real-time clock alarm interrupt flag */
\r
16211 /* RTCCTL0[RTCTEVIFG] Bits */
\r
16212 #define RTCTEVIFG_OFS ( 2) /* RTCTEVIFG Offset */
\r
16213 #define RTCTEVIFG (0x0004) /* Real-time clock time event interrupt flag */
\r
16214 /* RTCCTL0[RTCOFIFG] Bits */
\r
16215 #define RTCOFIFG_OFS ( 3) /* RTCOFIFG Offset */
\r
16216 #define RTCOFIFG (0x0008) /* 32-kHz crystal oscillator fault interrupt flag */
\r
16217 /* RTCCTL0[RTCRDYIE] Bits */
\r
16218 #define RTCRDYIE_OFS ( 4) /* RTCRDYIE Offset */
\r
16219 #define RTCRDYIE (0x0010) /* Real-time clock ready interrupt enable */
\r
16220 /* RTCCTL0[RTCAIE] Bits */
\r
16221 #define RTCAIE_OFS ( 5) /* RTCAIE Offset */
\r
16222 #define RTCAIE (0x0020) /* Real-time clock alarm interrupt enable */
\r
16223 /* RTCCTL0[RTCTEVIE] Bits */
\r
16224 #define RTCTEVIE_OFS ( 6) /* RTCTEVIE Offset */
\r
16225 #define RTCTEVIE (0x0040) /* Real-time clock time event interrupt enable */
\r
16226 /* RTCCTL0[RTCOFIE] Bits */
\r
16227 #define RTCOFIE_OFS ( 7) /* RTCOFIE Offset */
\r
16228 #define RTCOFIE (0x0080) /* 32-kHz crystal oscillator fault interrupt enable */
\r
16229 /* RTCCTL0[RTCKEY] Bits */
\r
16230 #define RTCKEY_OFS ( 8) /* RTCKEY Offset */
\r
16231 #define RTCKEY_M (0xff00) /* Real-time clock key */
\r
16232 /* RTCCTL13[RTCTEV] Bits */
\r
16233 #define RTCTEV_OFS ( 0) /* RTCTEV Offset */
\r
16234 #define RTCTEV_M (0x0003) /* Real-time clock time event */
\r
16235 #define RTCTEV0 (0x0001) /* Real-time clock time event */
\r
16236 #define RTCTEV1 (0x0002) /* Real-time clock time event */
\r
16237 #define RTCTEV_0 (0x0000) /* Minute changed */
\r
16238 #define RTCTEV_1 (0x0001) /* Hour changed */
\r
16239 #define RTCTEV_2 (0x0002) /* Every day at midnight (00:00) */
\r
16240 #define RTCTEV_3 (0x0003) /* Every day at noon (12:00) */
\r
16241 /* RTCCTL13[RTCSSEL] Bits */
\r
16242 #define RTCSSEL_OFS ( 2) /* RTCSSEL Offset */
\r
16243 #define RTCSSEL_M (0x000c) /* Real-time clock source select */
\r
16244 #define RTCSSEL0 (0x0004) /* Real-time clock source select */
\r
16245 #define RTCSSEL1 (0x0008) /* Real-time clock source select */
\r
16246 #define RTCSSEL_0 (0x0000) /* BCLK */
\r
16247 #define RTCSSEL__BCLK (0x0000) /* BCLK */
\r
16248 /* RTCCTL13[RTCRDY] Bits */
\r
16249 #define RTCRDY_OFS ( 4) /* RTCRDY Offset */
\r
16250 #define RTCRDY (0x0010) /* Real-time clock ready */
\r
16251 /* RTCCTL13[RTCMODE] Bits */
\r
16252 #define RTCMODE_OFS ( 5) /* RTCMODE Offset */
\r
16253 #define RTCMODE (0x0020) /* */
\r
16254 /* RTCCTL13[RTCHOLD] Bits */
\r
16255 #define RTCHOLD_OFS ( 6) /* RTCHOLD Offset */
\r
16256 #define RTCHOLD (0x0040) /* Real-time clock hold */
\r
16257 /* RTCCTL13[RTCBCD] Bits */
\r
16258 #define RTCBCD_OFS ( 7) /* RTCBCD Offset */
\r
16259 #define RTCBCD (0x0080) /* Real-time clock BCD select */
\r
16260 /* RTCCTL13[RTCCALF] Bits */
\r
16261 #define RTCCALF_OFS ( 8) /* RTCCALF Offset */
\r
16262 #define RTCCALF_M (0x0300) /* Real-time clock calibration frequency */
\r
16263 #define RTCCALF0 (0x0100) /* Real-time clock calibration frequency */
\r
16264 #define RTCCALF1 (0x0200) /* Real-time clock calibration frequency */
\r
16265 #define RTCCALF_0 (0x0000) /* No frequency output to RTCCLK pin */
\r
16266 #define RTCCALF_1 (0x0100) /* 512 Hz */
\r
16267 #define RTCCALF_2 (0x0200) /* 256 Hz */
\r
16268 #define RTCCALF_3 (0x0300) /* 1 Hz */
\r
16269 #define RTCCALF__NONE (0x0000) /* No frequency output to RTCCLK pin */
\r
16270 #define RTCCALF__512 (0x0100) /* 512 Hz */
\r
16271 #define RTCCALF__256 (0x0200) /* 256 Hz */
\r
16272 #define RTCCALF__1 (0x0300) /* 1 Hz */
\r
16273 /* RTCOCAL[RTCOCAL] Bits */
\r
16274 #define RTCOCAL_OFS ( 0) /* RTCOCAL Offset */
\r
16275 #define RTCOCAL_M (0x00ff) /* Real-time clock offset error calibration */
\r
16276 /* RTCOCAL[RTCOCALS] Bits */
\r
16277 #define RTCOCALS_OFS (15) /* RTCOCALS Offset */
\r
16278 #define RTCOCALS (0x8000) /* Real-time clock offset error calibration sign */
\r
16279 /* RTCTCMP[RTCTCMP] Bits */
\r
16280 #define RTCTCMP_OFS ( 0) /* RTCTCMP Offset */
\r
16281 #define RTCTCMP_M (0x00ff) /* Real-time clock temperature compensation */
\r
16282 /* RTCTCMP[RTCTCOK] Bits */
\r
16283 #define RTCTCOK_OFS (13) /* RTCTCOK Offset */
\r
16284 #define RTCTCOK (0x2000) /* Real-time clock temperature compensation write OK */
\r
16285 /* RTCTCMP[RTCTCRDY] Bits */
\r
16286 #define RTCTCRDY_OFS (14) /* RTCTCRDY Offset */
\r
16287 #define RTCTCRDY (0x4000) /* Real-time clock temperature compensation ready */
\r
16288 /* RTCTCMP[RTCTCMPS] Bits */
\r
16289 #define RTCTCMPS_OFS (15) /* RTCTCMPS Offset */
\r
16290 #define RTCTCMPS (0x8000) /* Real-time clock temperature compensation sign */
\r
16291 /* RTCPS0CTL[RT0PSIFG] Bits */
\r
16292 #define RT0PSIFG_OFS ( 0) /* RT0PSIFG Offset */
\r
16293 #define RT0PSIFG (0x0001) /* Prescale timer 0 interrupt flag */
\r
16294 /* RTCPS0CTL[RT0PSIE] Bits */
\r
16295 #define RT0PSIE_OFS ( 1) /* RT0PSIE Offset */
\r
16296 #define RT0PSIE (0x0002) /* Prescale timer 0 interrupt enable */
\r
16297 /* RTCPS0CTL[RT0IP] Bits */
\r
16298 #define RT0IP_OFS ( 2) /* RT0IP Offset */
\r
16299 #define RT0IP_M (0x001c) /* Prescale timer 0 interrupt interval */
\r
16300 #define RT0IP0 (0x0004) /* Prescale timer 0 interrupt interval */
\r
16301 #define RT0IP1 (0x0008) /* Prescale timer 0 interrupt interval */
\r
16302 #define RT0IP2 (0x0010) /* Prescale timer 0 interrupt interval */
\r
16303 #define RT0IP_0 (0x0000) /* Divide by 2 */
\r
16304 #define RT0IP_1 (0x0004) /* Divide by 4 */
\r
16305 #define RT0IP_2 (0x0008) /* Divide by 8 */
\r
16306 #define RT0IP_3 (0x000c) /* Divide by 16 */
\r
16307 #define RT0IP_4 (0x0010) /* Divide by 32 */
\r
16308 #define RT0IP_5 (0x0014) /* Divide by 64 */
\r
16309 #define RT0IP_6 (0x0018) /* Divide by 128 */
\r
16310 #define RT0IP_7 (0x001c) /* Divide by 256 */
\r
16311 #define RT0IP__2 (0x0000) /* Divide by 2 */
\r
16312 #define RT0IP__4 (0x0004) /* Divide by 4 */
\r
16313 #define RT0IP__8 (0x0008) /* Divide by 8 */
\r
16314 #define RT0IP__16 (0x000c) /* Divide by 16 */
\r
16315 #define RT0IP__32 (0x0010) /* Divide by 32 */
\r
16316 #define RT0IP__64 (0x0014) /* Divide by 64 */
\r
16317 #define RT0IP__128 (0x0018) /* Divide by 128 */
\r
16318 #define RT0IP__256 (0x001c) /* Divide by 256 */
\r
16319 /* RTCPS1CTL[RT1PSIFG] Bits */
\r
16320 #define RT1PSIFG_OFS ( 0) /* RT1PSIFG Offset */
\r
16321 #define RT1PSIFG (0x0001) /* Prescale timer 1 interrupt flag */
\r
16322 /* RTCPS1CTL[RT1PSIE] Bits */
\r
16323 #define RT1PSIE_OFS ( 1) /* RT1PSIE Offset */
\r
16324 #define RT1PSIE (0x0002) /* Prescale timer 1 interrupt enable */
\r
16325 /* RTCPS1CTL[RT1IP] Bits */
\r
16326 #define RT1IP_OFS ( 2) /* RT1IP Offset */
\r
16327 #define RT1IP_M (0x001c) /* Prescale timer 1 interrupt interval */
\r
16328 #define RT1IP0 (0x0004) /* Prescale timer 1 interrupt interval */
\r
16329 #define RT1IP1 (0x0008) /* Prescale timer 1 interrupt interval */
\r
16330 #define RT1IP2 (0x0010) /* Prescale timer 1 interrupt interval */
\r
16331 #define RT1IP_0 (0x0000) /* Divide by 2 */
\r
16332 #define RT1IP_1 (0x0004) /* Divide by 4 */
\r
16333 #define RT1IP_2 (0x0008) /* Divide by 8 */
\r
16334 #define RT1IP_3 (0x000c) /* Divide by 16 */
\r
16335 #define RT1IP_4 (0x0010) /* Divide by 32 */
\r
16336 #define RT1IP_5 (0x0014) /* Divide by 64 */
\r
16337 #define RT1IP_6 (0x0018) /* Divide by 128 */
\r
16338 #define RT1IP_7 (0x001c) /* Divide by 256 */
\r
16339 #define RT1IP__2 (0x0000) /* Divide by 2 */
\r
16340 #define RT1IP__4 (0x0004) /* Divide by 4 */
\r
16341 #define RT1IP__8 (0x0008) /* Divide by 8 */
\r
16342 #define RT1IP__16 (0x000c) /* Divide by 16 */
\r
16343 #define RT1IP__32 (0x0010) /* Divide by 32 */
\r
16344 #define RT1IP__64 (0x0014) /* Divide by 64 */
\r
16345 #define RT1IP__128 (0x0018) /* Divide by 128 */
\r
16346 #define RT1IP__256 (0x001c) /* Divide by 256 */
\r
16347 /* RTCPS[RT0PS] Bits */
\r
16348 #define RT0PS_OFS ( 0) /* RT0PS Offset */
\r
16349 #define RT0PS_M (0x00ff) /* Prescale timer 0 counter value */
\r
16350 /* RTCPS[RT1PS] Bits */
\r
16351 #define RT1PS_OFS ( 8) /* RT1PS Offset */
\r
16352 #define RT1PS_M (0xff00) /* Prescale timer 1 counter value */
\r
16353 /* RTCTIM0[SECONDS] Bits */
\r
16354 #define SECONDS_OFS ( 0) /* Seconds Offset */
\r
16355 #define SECONDS_M (0x003f) /* Seconds (0 to 59) */
\r
16356 /* RTCTIM0[MINUTES] Bits */
\r
16357 #define MINUTES_OFS ( 8) /* Minutes Offset */
\r
16358 #define MINUTES_M (0x3f00) /* Minutes (0 to 59) */
\r
16359 /* RTCTIM0_BCD[SECONDSLOWDIGIT] Bits */
\r
16360 #define SECONDSLOWDIGIT_OFS ( 0) /* SecondsLowDigit Offset */
\r
16361 #define SECONDSLOWDIGIT_M (0x000f) /* Seconds ? low digit (0 to 9) */
\r
16362 /* RTCTIM0_BCD[SECONDSHIGHDIGIT] Bits */
\r
16363 #define SECONDSHIGHDIGIT_OFS ( 4) /* SecondsHighDigit Offset */
\r
16364 #define SECONDSHIGHDIGIT_M (0x0070) /* Seconds ? high digit (0 to 5) */
\r
16365 /* RTCTIM0_BCD[MINUTESLOWDIGIT] Bits */
\r
16366 #define MINUTESLOWDIGIT_OFS ( 8) /* MinutesLowDigit Offset */
\r
16367 #define MINUTESLOWDIGIT_M (0x0f00) /* Minutes ? low digit (0 to 9) */
\r
16368 /* RTCTIM0_BCD[MINUTESHIGHDIGIT] Bits */
\r
16369 #define MINUTESHIGHDIGIT_OFS (12) /* MinutesHighDigit Offset */
\r
16370 #define MINUTESHIGHDIGIT_M (0x7000) /* Minutes ? high digit (0 to 5) */
\r
16371 /* RTCTIM1[HOURS] Bits */
\r
16372 #define HOURS_OFS ( 0) /* Hours Offset */
\r
16373 #define HOURS_M (0x001f) /* Hours (0 to 23) */
\r
16374 /* RTCTIM1[DAYOFWEEK] Bits */
\r
16375 #define DAYOFWEEK_OFS ( 8) /* DayofWeek Offset */
\r
16376 #define DAYOFWEEK_M (0x0700) /* Day of week (0 to 6) */
\r
16377 /* RTCTIM1_BCD[HOURSLOWDIGIT] Bits */
\r
16378 #define HOURSLOWDIGIT_OFS ( 0) /* HoursLowDigit Offset */
\r
16379 #define HOURSLOWDIGIT_M (0x000f) /* Hours ? low digit (0 to 9) */
\r
16380 /* RTCTIM1_BCD[HOURSHIGHDIGIT] Bits */
\r
16381 #define HOURSHIGHDIGIT_OFS ( 4) /* HoursHighDigit Offset */
\r
16382 #define HOURSHIGHDIGIT_M (0x0030) /* Hours ? high digit (0 to 2) */
\r
16383 /* RTCTIM1_BCD[DAYOFWEEK] Bits */
\r
16384 //#define DAYOFWEEK_OFS ( 8) /* DayofWeek Offset */
\r
16385 //#define DAYOFWEEK_M (0x0700) /* Day of week (0 to 6) */
\r
16386 /* RTCDATE[DAY] Bits */
\r
16387 #define DAY_OFS ( 0) /* Day Offset */
\r
16388 #define DAY_M (0x001f) /* Day of month (1 to 28, 29, 30, 31) */
\r
16389 /* RTCDATE[MONTH] Bits */
\r
16390 #define MONTH_OFS ( 8) /* Month Offset */
\r
16391 #define MONTH_M (0x0f00) /* Month (1 to 12) */
\r
16392 /* RTCDATE_BCD[DAYLOWDIGIT] Bits */
\r
16393 #define DAYLOWDIGIT_OFS ( 0) /* DayLowDigit Offset */
\r
16394 #define DAYLOWDIGIT_M (0x000f) /* Day of month ? low digit (0 to 9) */
\r
16395 /* RTCDATE_BCD[DAYHIGHDIGIT] Bits */
\r
16396 #define DAYHIGHDIGIT_OFS ( 4) /* DayHighDigit Offset */
\r
16397 #define DAYHIGHDIGIT_M (0x0030) /* Day of month ? high digit (0 to 3) */
\r
16398 /* RTCDATE_BCD[MONTHLOWDIGIT] Bits */
\r
16399 #define MONTHLOWDIGIT_OFS ( 8) /* MonthLowDigit Offset */
\r
16400 #define MONTHLOWDIGIT_M (0x0f00) /* Month ? low digit (0 to 9) */
\r
16401 /* RTCDATE_BCD[MONTHHIGHDIGIT] Bits */
\r
16402 #define MONTHHIGHDIGIT_OFS (12) /* MonthHighDigit Offset */
\r
16403 #define MONTHHIGHDIGIT (0x1000) /* Month ? high digit (0 or 1) */
\r
16404 /* RTCYEAR[YEARLOWBYTE] Bits */
\r
16405 #define YEARLOWBYTE_OFS ( 0) /* YearLowByte Offset */
\r
16406 #define YEARLOWBYTE_M (0x00ff) /* Year ? low byte. Valid values for Year are 0 to 4095. */
\r
16407 /* RTCYEAR[YEARHIGHBYTE] Bits */
\r
16408 #define YEARHIGHBYTE_OFS ( 8) /* YearHighByte Offset */
\r
16409 #define YEARHIGHBYTE_M (0x0f00) /* Year ? high byte. Valid values for Year are 0 to 4095. */
\r
16410 /* RTCYEAR_BCD[YEAR] Bits */
\r
16411 #define YEAR_OFS ( 0) /* Year Offset */
\r
16412 #define YEAR_M (0x000f) /* Year ? lowest digit (0 to 9) */
\r
16413 /* RTCYEAR_BCD[DECADE] Bits */
\r
16414 #define DECADE_OFS ( 4) /* Decade Offset */
\r
16415 #define DECADE_M (0x00f0) /* Decade (0 to 9) */
\r
16416 /* RTCYEAR_BCD[CENTURYLOWDIGIT] Bits */
\r
16417 #define CENTURYLOWDIGIT_OFS ( 8) /* CenturyLowDigit Offset */
\r
16418 #define CENTURYLOWDIGIT_M (0x0f00) /* Century ? low digit (0 to 9) */
\r
16419 /* RTCYEAR_BCD[CENTURYHIGHDIGIT] Bits */
\r
16420 #define CENTURYHIGHDIGIT_OFS (12) /* CenturyHighDigit Offset */
\r
16421 #define CENTURYHIGHDIGIT_M (0x7000) /* Century ? high digit (0 to 4) */
\r
16422 /* RTCAMINHR[MINUTES] Bits */
\r
16423 //#define MINUTES_OFS ( 0) /* Minutes Offset */
\r
16424 //#define MINUTES_M (0x003f) /* Minutes (0 to 59) */
\r
16425 /* RTCAMINHR[MINAE] Bits */
\r
16426 #define MINAE_OFS ( 7) /* MINAE Offset */
\r
16427 #define MINAE (0x0080) /* Alarm enable */
\r
16428 /* RTCAMINHR[HOURS] Bits */
\r
16429 //#define HOURS_OFS ( 8) /* Hours Offset */
\r
16430 //#define HOURS_M (0x1f00) /* Hours (0 to 23) */
\r
16431 /* RTCAMINHR[HOURAE] Bits */
\r
16432 #define HOURAE_OFS (15) /* HOURAE Offset */
\r
16433 #define HOURAE (0x8000) /* Alarm enable */
\r
16434 /* RTCAMINHR_BCD[MINUTESLOWDIGIT] Bits */
\r
16435 //#define MINUTESLOWDIGIT_OFS ( 0) /* MinutesLowDigit Offset */
\r
16436 //#define MINUTESLOWDIGIT_M (0x000f) /* Minutes ? low digit (0 to 9) */
\r
16437 /* RTCAMINHR_BCD[MINUTESHIGHDIGIT] Bits */
\r
16438 //#define MINUTESHIGHDIGIT_OFS ( 4) /* MinutesHighDigit Offset */
\r
16439 //#define MINUTESHIGHDIGIT_M (0x0070) /* Minutes ? high digit (0 to 5) */
\r
16440 /* RTCAMINHR_BCD[MINAE] Bits */
\r
16441 //#define MINAE_OFS ( 7) /* MINAE Offset */
\r
16442 //#define MINAE (0x0080) /* Alarm enable */
\r
16443 /* RTCAMINHR_BCD[HOURSLOWDIGIT] Bits */
\r
16444 //#define HOURSLOWDIGIT_OFS ( 8) /* HoursLowDigit Offset */
\r
16445 //#define HOURSLOWDIGIT_M (0x0f00) /* Hours ? low digit (0 to 9) */
\r
16446 /* RTCAMINHR_BCD[HOURSHIGHDIGIT] Bits */
\r
16447 //#define HOURSHIGHDIGIT_OFS (12) /* HoursHighDigit Offset */
\r
16448 //#define HOURSHIGHDIGIT_M (0x3000) /* Hours ? high digit (0 to 2) */
\r
16449 /* RTCAMINHR_BCD[HOURAE] Bits */
\r
16450 //#define HOURAE_OFS (15) /* HOURAE Offset */
\r
16451 //#define HOURAE (0x8000) /* Alarm enable */
\r
16452 /* RTCADOWDAY[DAYOFWEEK] Bits */
\r
16453 //#define DAYOFWEEK_OFS ( 0) /* DayofWeek Offset */
\r
16454 //#define DAYOFWEEK_M (0x0007) /* Day of week (0 to 6) */
\r
16455 /* RTCADOWDAY[DOWAE] Bits */
\r
16456 #define DOWAE_OFS ( 7) /* DOWAE Offset */
\r
16457 #define DOWAE (0x0080) /* Alarm enable */
\r
16458 /* RTCADOWDAY[DAYOFMONTH] Bits */
\r
16459 #define DAYOFMONTH_OFS ( 8) /* DayofMonth Offset */
\r
16460 #define DAYOFMONTH_M (0x1f00) /* Day of month (1 to 28, 29, 30, 31) */
\r
16461 /* RTCADOWDAY[DAYAE] Bits */
\r
16462 #define DAYAE_OFS (15) /* DAYAE Offset */
\r
16463 #define DAYAE (0x8000) /* Alarm enable */
\r
16464 /* RTCADOWDAY_BCD[DAYOFWEEK] Bits */
\r
16465 //#define DAYOFWEEK_OFS ( 0) /* DayofWeek Offset */
\r
16466 //#define DAYOFWEEK_M (0x0007) /* Day of week (0 to 6) */
\r
16467 /* RTCADOWDAY_BCD[DOWAE] Bits */
\r
16468 //#define DOWAE_OFS ( 7) /* DOWAE Offset */
\r
16469 //#define DOWAE (0x0080) /* Alarm enable */
\r
16470 /* RTCADOWDAY_BCD[DAYLOWDIGIT] Bits */
\r
16471 //#define DAYLOWDIGIT_OFS ( 8) /* DayLowDigit Offset */
\r
16472 //#define DAYLOWDIGIT_M (0x0f00) /* Day of month ? low digit (0 to 9) */
\r
16473 /* RTCADOWDAY_BCD[DAYHIGHDIGIT] Bits */
\r
16474 //#define DAYHIGHDIGIT_OFS (12) /* DayHighDigit Offset */
\r
16475 //#define DAYHIGHDIGIT_M (0x3000) /* Day of month ? high digit (0 to 3) */
\r
16476 /* RTCADOWDAY_BCD[DAYAE] Bits */
\r
16477 //#define DAYAE_OFS (15) /* DAYAE Offset */
\r
16478 //#define DAYAE (0x8000) /* Alarm enable */
\r
16480 /* Pre-defined bitfield values */
\r
16481 #define RTCKEY (0xA500) /* RTC_C Key Value for RTC_C write access */
\r
16482 #define RTCKEY_H (0x00A5) /* RTC_C Key Value for RTC_C write access */
\r
16483 #define RTCKEY_VAL (0xA500) /* RTC_C Key Value for RTC_C write access */
\r
16486 //*****************************************************************************
\r
16488 //*****************************************************************************
\r
16489 /* SCB_CPUID[SCB_CPUID_REVISION] Bits */
\r
16490 #define SCB_CPUID_REVISION_OFS ( 0) /* REVISION Offset */
\r
16491 #define SCB_CPUID_REVISION_M (0x0000000f) /* */
\r
16492 /* SCB_CPUID[SCB_CPUID_PARTNO] Bits */
\r
16493 #define SCB_CPUID_PARTNO_OFS ( 4) /* PARTNO Offset */
\r
16494 #define SCB_CPUID_PARTNO_M (0x0000fff0) /* */
\r
16495 /* SCB_CPUID[SCB_CPUID_CONSTANT] Bits */
\r
16496 #define SCB_CPUID_CONSTANT_OFS (16) /* CONSTANT Offset */
\r
16497 #define SCB_CPUID_CONSTANT_M (0x000f0000) /* */
\r
16498 /* SCB_CPUID[SCB_CPUID_VARIANT] Bits */
\r
16499 #define SCB_CPUID_VARIANT_OFS (20) /* VARIANT Offset */
\r
16500 #define SCB_CPUID_VARIANT_M (0x00f00000) /* */
\r
16501 /* SCB_CPUID[SCB_CPUID_IMPLEMENTER] Bits */
\r
16502 #define SCB_CPUID_IMPLEMENTER_OFS (24) /* IMPLEMENTER Offset */
\r
16503 #define SCB_CPUID_IMPLEMENTER_M (0xff000000) /* */
\r
16504 /* SCB_ICSR[SCB_ICSR_VECTACTIVE] Bits */
\r
16505 #define SCB_ICSR_VECTACTIVE_OFS ( 0) /* VECTACTIVE Offset */
\r
16506 #define SCB_ICSR_VECTACTIVE_M (0x000001ff) /* */
\r
16507 /* SCB_ICSR[SCB_ICSR_RETTOBASE] Bits */
\r
16508 #define SCB_ICSR_RETTOBASE_OFS (11) /* RETTOBASE Offset */
\r
16509 #define SCB_ICSR_RETTOBASE (0x00000800) /* */
\r
16510 /* SCB_ICSR[SCB_ICSR_VECTPENDING] Bits */
\r
16511 #define SCB_ICSR_VECTPENDING_OFS (12) /* VECTPENDING Offset */
\r
16512 #define SCB_ICSR_VECTPENDING_M (0x0003f000) /* */
\r
16513 /* SCB_ICSR[SCB_ICSR_ISRPENDING] Bits */
\r
16514 #define SCB_ICSR_ISRPENDING_OFS (22) /* ISRPENDING Offset */
\r
16515 #define SCB_ICSR_ISRPENDING (0x00400000) /* */
\r
16516 /* SCB_ICSR[SCB_ICSR_ISRPREEMPT] Bits */
\r
16517 #define SCB_ICSR_ISRPREEMPT_OFS (23) /* ISRPREEMPT Offset */
\r
16518 #define SCB_ICSR_ISRPREEMPT (0x00800000) /* */
\r
16519 /* SCB_ICSR[SCB_ICSR_PENDSTCLR] Bits */
\r
16520 #define SCB_ICSR_PENDSTCLR_OFS (25) /* PENDSTCLR Offset */
\r
16521 #define SCB_ICSR_PENDSTCLR (0x02000000) /* */
\r
16522 /* SCB_ICSR[SCB_ICSR_PENDSTSET] Bits */
\r
16523 #define SCB_ICSR_PENDSTSET_OFS (26) /* PENDSTSET Offset */
\r
16524 #define SCB_ICSR_PENDSTSET (0x04000000) /* */
\r
16525 /* SCB_ICSR[SCB_ICSR_PENDSVCLR] Bits */
\r
16526 #define SCB_ICSR_PENDSVCLR_OFS (27) /* PENDSVCLR Offset */
\r
16527 #define SCB_ICSR_PENDSVCLR (0x08000000) /* */
\r
16528 /* SCB_ICSR[SCB_ICSR_PENDSVSET] Bits */
\r
16529 #define SCB_ICSR_PENDSVSET_OFS (28) /* PENDSVSET Offset */
\r
16530 #define SCB_ICSR_PENDSVSET (0x10000000) /* */
\r
16531 /* SCB_ICSR[SCB_ICSR_NMIPENDSET] Bits */
\r
16532 #define SCB_ICSR_NMIPENDSET_OFS (31) /* NMIPENDSET Offset */
\r
16533 #define SCB_ICSR_NMIPENDSET (0x80000000) /* */
\r
16534 /* SCB_VTOR[SCB_VTOR_TBLOFF] Bits */
\r
16535 #define SCB_VTOR_TBLOFF_OFS ( 7) /* TBLOFF Offset */
\r
16536 #define SCB_VTOR_TBLOFF_M (0x1fffff80) /* */
\r
16537 /* SCB_VTOR[SCB_VTOR_TBLBASE] Bits */
\r
16538 #define SCB_VTOR_TBLBASE_OFS (29) /* TBLBASE Offset */
\r
16539 #define SCB_VTOR_TBLBASE (0x20000000) /* */
\r
16540 /* SCB_AIRCR[SCB_AIRCR_VECTRESET] Bits */
\r
16541 #define SCB_AIRCR_VECTRESET_OFS ( 0) /* VECTRESET Offset */
\r
16542 #define SCB_AIRCR_VECTRESET (0x00000001) /* */
\r
16543 /* SCB_AIRCR[SCB_AIRCR_VECTCLRACTIVE] Bits */
\r
16544 #define SCB_AIRCR_VECTCLRACTIVE_OFS ( 1) /* VECTCLRACTIVE Offset */
\r
16545 #define SCB_AIRCR_VECTCLRACTIVE (0x00000002) /* */
\r
16546 /* SCB_AIRCR[SCB_AIRCR_SYSRESETREQ] Bits */
\r
16547 #define SCB_AIRCR_SYSRESETREQ_OFS ( 2) /* SYSRESETREQ Offset */
\r
16548 #define SCB_AIRCR_SYSRESETREQ (0x00000004) /* */
\r
16549 /* SCB_AIRCR[SCB_AIRCR_PRIGROUP] Bits */
\r
16550 #define SCB_AIRCR_PRIGROUP_OFS ( 8) /* PRIGROUP Offset */
\r
16551 #define SCB_AIRCR_PRIGROUP_M (0x00000700) /* */
\r
16552 /* SCB_AIRCR[SCB_AIRCR_ENDIANESS] Bits */
\r
16553 #define SCB_AIRCR_ENDIANESS_OFS (15) /* ENDIANESS Offset */
\r
16554 #define SCB_AIRCR_ENDIANESS (0x00008000) /* */
\r
16555 /* SCB_AIRCR[SCB_AIRCR_VECTKEY] Bits */
\r
16556 #define SCB_AIRCR_VECTKEY_OFS (16) /* VECTKEY Offset */
\r
16557 #define SCB_AIRCR_VECTKEY_M (0xffff0000) /* */
\r
16558 /* SCB_SCR[SCB_SCR_SLEEPONEXIT] Bits */
\r
16559 #define SCB_SCR_SLEEPONEXIT_OFS ( 1) /* SLEEPONEXIT Offset */
\r
16560 #define SCB_SCR_SLEEPONEXIT (0x00000002) /* */
\r
16561 /* SCB_SCR[SCB_SCR_SLEEPDEEP] Bits */
\r
16562 #define SCB_SCR_SLEEPDEEP_OFS ( 2) /* SLEEPDEEP Offset */
\r
16563 #define SCB_SCR_SLEEPDEEP (0x00000004) /* */
\r
16564 /* SCB_SCR[SCB_SCR_SEVONPEND] Bits */
\r
16565 #define SCB_SCR_SEVONPEND_OFS ( 4) /* SEVONPEND Offset */
\r
16566 #define SCB_SCR_SEVONPEND (0x00000010) /* */
\r
16567 /* SCB_CCR[SCB_CCR_NONBASETHREDENA] Bits */
\r
16568 #define SCB_CCR_NONBASETHREDENA_OFS ( 0) /* NONBASETHREDENA Offset */
\r
16569 #define SCB_CCR_NONBASETHREDENA (0x00000001) /* */
\r
16570 /* SCB_CCR[SCB_CCR_USERSETMPEND] Bits */
\r
16571 #define SCB_CCR_USERSETMPEND_OFS ( 1) /* USERSETMPEND Offset */
\r
16572 #define SCB_CCR_USERSETMPEND (0x00000002) /* */
\r
16573 /* SCB_CCR[SCB_CCR_UNALIGN_TRP] Bits */
\r
16574 #define SCB_CCR_UNALIGN_TRP_OFS ( 3) /* UNALIGN_TRP Offset */
\r
16575 #define SCB_CCR_UNALIGN_TRP (0x00000008) /* */
\r
16576 /* SCB_CCR[SCB_CCR_DIV_0_TRP] Bits */
\r
16577 #define SCB_CCR_DIV_0_TRP_OFS ( 4) /* DIV_0_TRP Offset */
\r
16578 #define SCB_CCR_DIV_0_TRP (0x00000010) /* */
\r
16579 /* SCB_CCR[SCB_CCR_BFHFNMIGN] Bits */
\r
16580 #define SCB_CCR_BFHFNMIGN_OFS ( 8) /* BFHFNMIGN Offset */
\r
16581 #define SCB_CCR_BFHFNMIGN (0x00000100) /* */
\r
16582 /* SCB_CCR[SCB_CCR_STKALIGN] Bits */
\r
16583 #define SCB_CCR_STKALIGN_OFS ( 9) /* STKALIGN Offset */
\r
16584 #define SCB_CCR_STKALIGN (0x00000200) /* */
\r
16585 /* SCB_SHPR1[SCB_SHPR1_PRI_4] Bits */
\r
16586 #define SCB_SHPR1_PRI_4_OFS ( 0) /* PRI_4 Offset */
\r
16587 #define SCB_SHPR1_PRI_4_M (0x000000ff) /* */
\r
16588 /* SCB_SHPR1[SCB_SHPR1_PRI_5] Bits */
\r
16589 #define SCB_SHPR1_PRI_5_OFS ( 8) /* PRI_5 Offset */
\r
16590 #define SCB_SHPR1_PRI_5_M (0x0000ff00) /* */
\r
16591 /* SCB_SHPR1[SCB_SHPR1_PRI_6] Bits */
\r
16592 #define SCB_SHPR1_PRI_6_OFS (16) /* PRI_6 Offset */
\r
16593 #define SCB_SHPR1_PRI_6_M (0x00ff0000) /* */
\r
16594 /* SCB_SHPR1[SCB_SHPR1_PRI_7] Bits */
\r
16595 #define SCB_SHPR1_PRI_7_OFS (24) /* PRI_7 Offset */
\r
16596 #define SCB_SHPR1_PRI_7_M (0xff000000) /* */
\r
16597 /* SCB_SHPR2[SCB_SHPR2_PRI_8] Bits */
\r
16598 #define SCB_SHPR2_PRI_8_OFS ( 0) /* PRI_8 Offset */
\r
16599 #define SCB_SHPR2_PRI_8_M (0x000000ff) /* */
\r
16600 /* SCB_SHPR2[SCB_SHPR2_PRI_9] Bits */
\r
16601 #define SCB_SHPR2_PRI_9_OFS ( 8) /* PRI_9 Offset */
\r
16602 #define SCB_SHPR2_PRI_9_M (0x0000ff00) /* */
\r
16603 /* SCB_SHPR2[SCB_SHPR2_PRI_10] Bits */
\r
16604 #define SCB_SHPR2_PRI_10_OFS (16) /* PRI_10 Offset */
\r
16605 #define SCB_SHPR2_PRI_10_M (0x00ff0000) /* */
\r
16606 /* SCB_SHPR2[SCB_SHPR2_PRI_11] Bits */
\r
16607 #define SCB_SHPR2_PRI_11_OFS (24) /* PRI_11 Offset */
\r
16608 #define SCB_SHPR2_PRI_11_M (0xff000000) /* */
\r
16609 /* SCB_SHPR3[SCB_SHPR3_PRI_12] Bits */
\r
16610 #define SCB_SHPR3_PRI_12_OFS ( 0) /* PRI_12 Offset */
\r
16611 #define SCB_SHPR3_PRI_12_M (0x000000ff) /* */
\r
16612 /* SCB_SHPR3[SCB_SHPR3_PRI_13] Bits */
\r
16613 #define SCB_SHPR3_PRI_13_OFS ( 8) /* PRI_13 Offset */
\r
16614 #define SCB_SHPR3_PRI_13_M (0x0000ff00) /* */
\r
16615 /* SCB_SHPR3[SCB_SHPR3_PRI_14] Bits */
\r
16616 #define SCB_SHPR3_PRI_14_OFS (16) /* PRI_14 Offset */
\r
16617 #define SCB_SHPR3_PRI_14_M (0x00ff0000) /* */
\r
16618 /* SCB_SHPR3[SCB_SHPR3_PRI_15] Bits */
\r
16619 #define SCB_SHPR3_PRI_15_OFS (24) /* PRI_15 Offset */
\r
16620 #define SCB_SHPR3_PRI_15_M (0xff000000) /* */
\r
16621 /* SCB_SHCSR[SCB_SHCSR_MEMFAULTACT] Bits */
\r
16622 #define SCB_SHCSR_MEMFAULTACT_OFS ( 0) /* MEMFAULTACT Offset */
\r
16623 #define SCB_SHCSR_MEMFAULTACT (0x00000001) /* */
\r
16624 /* SCB_SHCSR[SCB_SHCSR_BUSFAULTACT] Bits */
\r
16625 #define SCB_SHCSR_BUSFAULTACT_OFS ( 1) /* BUSFAULTACT Offset */
\r
16626 #define SCB_SHCSR_BUSFAULTACT (0x00000002) /* */
\r
16627 /* SCB_SHCSR[SCB_SHCSR_USGFAULTACT] Bits */
\r
16628 #define SCB_SHCSR_USGFAULTACT_OFS ( 3) /* USGFAULTACT Offset */
\r
16629 #define SCB_SHCSR_USGFAULTACT (0x00000008) /* */
\r
16630 /* SCB_SHCSR[SCB_SHCSR_SVCALLACT] Bits */
\r
16631 #define SCB_SHCSR_SVCALLACT_OFS ( 7) /* SVCALLACT Offset */
\r
16632 #define SCB_SHCSR_SVCALLACT (0x00000080) /* */
\r
16633 /* SCB_SHCSR[SCB_SHCSR_MONITORACT] Bits */
\r
16634 #define SCB_SHCSR_MONITORACT_OFS ( 8) /* MONITORACT Offset */
\r
16635 #define SCB_SHCSR_MONITORACT (0x00000100) /* */
\r
16636 /* SCB_SHCSR[SCB_SHCSR_PENDSVACT] Bits */
\r
16637 #define SCB_SHCSR_PENDSVACT_OFS (10) /* PENDSVACT Offset */
\r
16638 #define SCB_SHCSR_PENDSVACT (0x00000400) /* */
\r
16639 /* SCB_SHCSR[SCB_SHCSR_SYSTICKACT] Bits */
\r
16640 #define SCB_SHCSR_SYSTICKACT_OFS (11) /* SYSTICKACT Offset */
\r
16641 #define SCB_SHCSR_SYSTICKACT (0x00000800) /* */
\r
16642 /* SCB_SHCSR[SCB_SHCSR_USGFAULTPENDED] Bits */
\r
16643 #define SCB_SHCSR_USGFAULTPENDED_OFS (12) /* USGFAULTPENDED Offset */
\r
16644 #define SCB_SHCSR_USGFAULTPENDED (0x00001000) /* */
\r
16645 /* SCB_SHCSR[SCB_SHCSR_MEMFAULTPENDED] Bits */
\r
16646 #define SCB_SHCSR_MEMFAULTPENDED_OFS (13) /* MEMFAULTPENDED Offset */
\r
16647 #define SCB_SHCSR_MEMFAULTPENDED (0x00002000) /* */
\r
16648 /* SCB_SHCSR[SCB_SHCSR_BUSFAULTPENDED] Bits */
\r
16649 #define SCB_SHCSR_BUSFAULTPENDED_OFS (14) /* BUSFAULTPENDED Offset */
\r
16650 #define SCB_SHCSR_BUSFAULTPENDED (0x00004000) /* */
\r
16651 /* SCB_SHCSR[SCB_SHCSR_SVCALLPENDED] Bits */
\r
16652 #define SCB_SHCSR_SVCALLPENDED_OFS (15) /* SVCALLPENDED Offset */
\r
16653 #define SCB_SHCSR_SVCALLPENDED (0x00008000) /* */
\r
16654 /* SCB_SHCSR[SCB_SHCSR_MEMFAULTENA] Bits */
\r
16655 #define SCB_SHCSR_MEMFAULTENA_OFS (16) /* MEMFAULTENA Offset */
\r
16656 #define SCB_SHCSR_MEMFAULTENA (0x00010000) /* */
\r
16657 /* SCB_SHCSR[SCB_SHCSR_BUSFAULTENA] Bits */
\r
16658 #define SCB_SHCSR_BUSFAULTENA_OFS (17) /* BUSFAULTENA Offset */
\r
16659 #define SCB_SHCSR_BUSFAULTENA (0x00020000) /* */
\r
16660 /* SCB_SHCSR[SCB_SHCSR_USGFAULTENA] Bits */
\r
16661 #define SCB_SHCSR_USGFAULTENA_OFS (18) /* USGFAULTENA Offset */
\r
16662 #define SCB_SHCSR_USGFAULTENA (0x00040000) /* */
\r
16663 /* SCB_CFSR[SCB_CFSR_IACCVIOL] Bits */
\r
16664 #define SCB_CFSR_IACCVIOL_OFS ( 0) /* IACCVIOL Offset */
\r
16665 #define SCB_CFSR_IACCVIOL (0x00000001) /* */
\r
16666 /* SCB_CFSR[SCB_CFSR_DACCVIOL] Bits */
\r
16667 #define SCB_CFSR_DACCVIOL_OFS ( 1) /* DACCVIOL Offset */
\r
16668 #define SCB_CFSR_DACCVIOL (0x00000002) /* */
\r
16669 /* SCB_CFSR[SCB_CFSR_MUNSTKERR] Bits */
\r
16670 #define SCB_CFSR_MUNSTKERR_OFS ( 3) /* MUNSTKERR Offset */
\r
16671 #define SCB_CFSR_MUNSTKERR (0x00000008) /* */
\r
16672 /* SCB_CFSR[SCB_CFSR_MSTKERR] Bits */
\r
16673 #define SCB_CFSR_MSTKERR_OFS ( 4) /* MSTKERR Offset */
\r
16674 #define SCB_CFSR_MSTKERR (0x00000010) /* */
\r
16675 /* SCB_CFSR[SCB_CFSR_MMARVALID] Bits */
\r
16676 #define SCB_CFSR_MMARVALID_OFS ( 7) /* MMARVALID Offset */
\r
16677 #define SCB_CFSR_MMARVALID (0x00000080) /* */
\r
16678 /* SCB_CFSR[SCB_CFSR_IBUSERR] Bits */
\r
16679 #define SCB_CFSR_IBUSERR_OFS ( 8) /* IBUSERR Offset */
\r
16680 #define SCB_CFSR_IBUSERR (0x00000100) /* */
\r
16681 /* SCB_CFSR[SCB_CFSR_PRECISERR] Bits */
\r
16682 #define SCB_CFSR_PRECISERR_OFS ( 9) /* PRECISERR Offset */
\r
16683 #define SCB_CFSR_PRECISERR (0x00000200) /* */
\r
16684 /* SCB_CFSR[SCB_CFSR_IMPRECISERR] Bits */
\r
16685 #define SCB_CFSR_IMPRECISERR_OFS (10) /* IMPRECISERR Offset */
\r
16686 #define SCB_CFSR_IMPRECISERR (0x00000400) /* */
\r
16687 /* SCB_CFSR[SCB_CFSR_UNSTKERR] Bits */
\r
16688 #define SCB_CFSR_UNSTKERR_OFS (11) /* UNSTKERR Offset */
\r
16689 #define SCB_CFSR_UNSTKERR (0x00000800) /* */
\r
16690 /* SCB_CFSR[SCB_CFSR_STKERR] Bits */
\r
16691 #define SCB_CFSR_STKERR_OFS (12) /* STKERR Offset */
\r
16692 #define SCB_CFSR_STKERR (0x00001000) /* */
\r
16693 /* SCB_CFSR[SCB_CFSR_BFARVALID] Bits */
\r
16694 #define SCB_CFSR_BFARVALID_OFS (15) /* BFARVALID Offset */
\r
16695 #define SCB_CFSR_BFARVALID (0x00008000) /* */
\r
16696 /* SCB_CFSR[SCB_CFSR_UNDEFINSTR] Bits */
\r
16697 #define SCB_CFSR_UNDEFINSTR_OFS (16) /* UNDEFINSTR Offset */
\r
16698 #define SCB_CFSR_UNDEFINSTR (0x00010000) /* */
\r
16699 /* SCB_CFSR[SCB_CFSR_INVSTATE] Bits */
\r
16700 #define SCB_CFSR_INVSTATE_OFS (17) /* INVSTATE Offset */
\r
16701 #define SCB_CFSR_INVSTATE (0x00020000) /* */
\r
16702 /* SCB_CFSR[SCB_CFSR_INVPC] Bits */
\r
16703 #define SCB_CFSR_INVPC_OFS (18) /* INVPC Offset */
\r
16704 #define SCB_CFSR_INVPC (0x00040000) /* */
\r
16705 /* SCB_CFSR[SCB_CFSR_NOCP] Bits */
\r
16706 #define SCB_CFSR_NOCP_OFS (19) /* NOCP Offset */
\r
16707 #define SCB_CFSR_NOCP (0x00080000) /* */
\r
16708 /* SCB_CFSR[SCB_CFSR_UNALIGNED] Bits */
\r
16709 #define SCB_CFSR_UNALIGNED_OFS (24) /* UNALIGNED Offset */
\r
16710 #define SCB_CFSR_UNALIGNED (0x01000000) /* */
\r
16711 /* SCB_CFSR[SCB_CFSR_DIVBYZERO] Bits */
\r
16712 #define SCB_CFSR_DIVBYZERO_OFS (25) /* DIVBYZERO Offset */
\r
16713 #define SCB_CFSR_DIVBYZERO (0x02000000) /* */
\r
16714 /* SCB_CFSR[SCB_CFSR_MLSPERR] Bits */
\r
16715 #define SCB_CFSR_MLSPERR_OFS ( 5) /* MLSPERR Offset */
\r
16716 #define SCB_CFSR_MLSPERR (0x00000020) /* */
\r
16717 /* SCB_CFSR[SCB_CFSR_LSPERR] Bits */
\r
16718 #define SCB_CFSR_LSPERR_OFS (13) /* LSPERR Offset */
\r
16719 #define SCB_CFSR_LSPERR (0x00002000) /* */
\r
16720 /* SCB_HFSR[SCB_HFSR_VECTTBL] Bits */
\r
16721 #define SCB_HFSR_VECTTBL_OFS ( 1) /* VECTTBL Offset */
\r
16722 #define SCB_HFSR_VECTTBL (0x00000002) /* */
\r
16723 /* SCB_HFSR[SCB_HFSR_FORCED] Bits */
\r
16724 #define SCB_HFSR_FORCED_OFS (30) /* FORCED Offset */
\r
16725 #define SCB_HFSR_FORCED (0x40000000) /* */
\r
16726 /* SCB_HFSR[SCB_HFSR_DEBUGEVT] Bits */
\r
16727 #define SCB_HFSR_DEBUGEVT_OFS (31) /* DEBUGEVT Offset */
\r
16728 #define SCB_HFSR_DEBUGEVT (0x80000000) /* */
\r
16729 /* SCB_DFSR[SCB_DFSR_HALTED] Bits */
\r
16730 #define SCB_DFSR_HALTED_OFS ( 0) /* HALTED Offset */
\r
16731 #define SCB_DFSR_HALTED (0x00000001) /* */
\r
16732 /* SCB_DFSR[SCB_DFSR_BKPT] Bits */
\r
16733 #define SCB_DFSR_BKPT_OFS ( 1) /* BKPT Offset */
\r
16734 #define SCB_DFSR_BKPT (0x00000002) /* */
\r
16735 /* SCB_DFSR[SCB_DFSR_DWTTRAP] Bits */
\r
16736 #define SCB_DFSR_DWTTRAP_OFS ( 2) /* DWTTRAP Offset */
\r
16737 #define SCB_DFSR_DWTTRAP (0x00000004) /* */
\r
16738 /* SCB_DFSR[SCB_DFSR_VCATCH] Bits */
\r
16739 #define SCB_DFSR_VCATCH_OFS ( 3) /* VCATCH Offset */
\r
16740 #define SCB_DFSR_VCATCH (0x00000008) /* */
\r
16741 /* SCB_DFSR[SCB_DFSR_EXTERNAL] Bits */
\r
16742 #define SCB_DFSR_EXTERNAL_OFS ( 4) /* EXTERNAL Offset */
\r
16743 #define SCB_DFSR_EXTERNAL (0x00000010) /* */
\r
16744 /* SCB_PFR0[SCB_PFR0_STATE0] Bits */
\r
16745 #define SCB_PFR0_STATE0_OFS ( 0) /* STATE0 Offset */
\r
16746 #define SCB_PFR0_STATE0_M (0x0000000f) /* */
\r
16747 #define SCB_PFR0_STATE00 (0x00000001) /* */
\r
16748 #define SCB_PFR0_STATE01 (0x00000002) /* */
\r
16749 #define SCB_PFR0_STATE02 (0x00000004) /* */
\r
16750 #define SCB_PFR0_STATE03 (0x00000008) /* */
\r
16751 #define SCB_PFR0_STATE0_0 (0x00000000) /* no ARM encoding */
\r
16752 #define SCB_PFR0_STATE0_1 (0x00000001) /* N/A */
\r
16753 /* SCB_PFR0[SCB_PFR0_STATE1] Bits */
\r
16754 #define SCB_PFR0_STATE1_OFS ( 4) /* STATE1 Offset */
\r
16755 #define SCB_PFR0_STATE1_M (0x000000f0) /* */
\r
16756 #define SCB_PFR0_STATE10 (0x00000010) /* */
\r
16757 #define SCB_PFR0_STATE11 (0x00000020) /* */
\r
16758 #define SCB_PFR0_STATE12 (0x00000040) /* */
\r
16759 #define SCB_PFR0_STATE13 (0x00000080) /* */
\r
16760 #define SCB_PFR0_STATE1_0 (0x00000000) /* N/A */
\r
16761 #define SCB_PFR0_STATE1_1 (0x00000010) /* N/A */
\r
16762 #define SCB_PFR0_STATE1_2 (0x00000020) /* Thumb-2 encoding with the 16-bit basic instructions plus 32-bit Buncond/BL but no other 32-bit basic instructions (Note non-basic 32-bit instructions can be added using the appropriate instruction attribute, but other 32-bit basic instructions cannot.) */
\r
16763 #define SCB_PFR0_STATE1_3 (0x00000030) /* Thumb-2 encoding with all Thumb-2 basic instructions */
\r
16764 /* SCB_PFR1[SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL] Bits */
\r
16765 #define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL_OFS ( 8) /* MICROCONTROLLER_PROGRAMMERS_MODEL Offset */
\r
16766 #define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL_M (0x00000f00) /* */
\r
16767 #define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL0 (0x00000100) /* */
\r
16768 #define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL1 (0x00000200) /* */
\r
16769 #define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL2 (0x00000400) /* */
\r
16770 #define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL3 (0x00000800) /* */
\r
16771 #define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL_0 (0x00000000) /* not supported */
\r
16772 #define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL_2 (0x00000200) /* two-stack support */
\r
16773 /* SCB_DFR0[SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL] Bits */
\r
16774 #define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL_OFS (20) /* MICROCONTROLLER_DEBUG_MODEL Offset */
\r
16775 #define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL_M (0x00f00000) /* */
\r
16776 #define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL0 (0x00100000) /* */
\r
16777 #define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL1 (0x00200000) /* */
\r
16778 #define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL2 (0x00400000) /* */
\r
16779 #define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL3 (0x00800000) /* */
\r
16780 #define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL_0 (0x00000000) /* not supported */
\r
16781 #define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL_1 (0x00100000) /* Microcontroller debug v1 (ITMv1, DWTv1, optional ETM) */
\r
16782 /* SCB_MMFR0[SCB_MMFR0_PMSA_SUPPORT] Bits */
\r
16783 #define SCB_MMFR0_PMSA_SUPPORT_OFS ( 4) /* PMSA_SUPPORT Offset */
\r
16784 #define SCB_MMFR0_PMSA_SUPPORT_M (0x000000f0) /* */
\r
16785 #define SCB_MMFR0_PMSA_SUPPORT0 (0x00000010) /* */
\r
16786 #define SCB_MMFR0_PMSA_SUPPORT1 (0x00000020) /* */
\r
16787 #define SCB_MMFR0_PMSA_SUPPORT2 (0x00000040) /* */
\r
16788 #define SCB_MMFR0_PMSA_SUPPORT3 (0x00000080) /* */
\r
16789 #define SCB_MMFR0_PMSA_SUPPORT_0 (0x00000000) /* not supported */
\r
16790 #define SCB_MMFR0_PMSA_SUPPORT_1 (0x00000010) /* IMPLEMENTATION DEFINED (N/A) */
\r
16791 #define SCB_MMFR0_PMSA_SUPPORT_2 (0x00000020) /* PMSA base (features as defined for ARMv6) (N/A) */
\r
16792 #define SCB_MMFR0_PMSA_SUPPORT_3 (0x00000030) /* PMSAv7 (base plus subregion support) */
\r
16793 /* SCB_MMFR0[SCB_MMFR0_CACHE_COHERENCE_SUPPORT] Bits */
\r
16794 #define SCB_MMFR0_CACHE_COHERENCE_SUPPORT_OFS ( 8) /* CACHE_COHERENCE_SUPPORT Offset */
\r
16795 #define SCB_MMFR0_CACHE_COHERENCE_SUPPORT_M (0x00000f00) /* */
\r
16796 #define SCB_MMFR0_CACHE_COHERENCE_SUPPORT0 (0x00000100) /* */
\r
16797 #define SCB_MMFR0_CACHE_COHERENCE_SUPPORT1 (0x00000200) /* */
\r
16798 #define SCB_MMFR0_CACHE_COHERENCE_SUPPORT2 (0x00000400) /* */
\r
16799 #define SCB_MMFR0_CACHE_COHERENCE_SUPPORT3 (0x00000800) /* */
\r
16800 #define SCB_MMFR0_CACHE_COHERENCE_SUPPORT_0 (0x00000000) /* no shared support */
\r
16801 #define SCB_MMFR0_CACHE_COHERENCE_SUPPORT_1 (0x00000100) /* partial-inner-shared coherency (coherency amongst some - but not all - of the entities within an inner-coherent domain) */
\r
16802 #define SCB_MMFR0_CACHE_COHERENCE_SUPPORT_2 (0x00000200) /* full-inner-shared coherency (coherency amongst all of the entities within an inner-coherent domain) */
\r
16803 #define SCB_MMFR0_CACHE_COHERENCE_SUPPORT_3 (0x00000300) /* full coherency (coherency amongst all of the entities) */
\r
16804 /* SCB_MMFR0[SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT] Bits */
\r
16805 #define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT_OFS (12) /* OUTER_NON_SHARABLE_SUPPORT Offset */
\r
16806 #define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT_M (0x0000f000) /* */
\r
16807 #define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT0 (0x00001000) /* */
\r
16808 #define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT1 (0x00002000) /* */
\r
16809 #define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT2 (0x00004000) /* */
\r
16810 #define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT3 (0x00008000) /* */
\r
16811 #define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT_0 (0x00000000) /* Outer non-sharable not supported */
\r
16812 #define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT_1 (0x00001000) /* Outer sharable supported */
\r
16813 /* SCB_MMFR0[SCB_MMFR0_AUILIARY_REGISTER_SUPPORT] Bits */
\r
16814 #define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT_OFS (20) /* AUXILIARY_REGISTER_SUPPORT Offset */
\r
16815 #define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT_M (0x00f00000) /* */
\r
16816 #define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT0 (0x00100000) /* */
\r
16817 #define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT1 (0x00200000) /* */
\r
16818 #define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT2 (0x00400000) /* */
\r
16819 #define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT3 (0x00800000) /* */
\r
16820 #define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT_0 (0x00000000) /* not supported */
\r
16821 #define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT_1 (0x00100000) /* Auxiliary control register */
\r
16822 /* SCB_MMFR2[SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING] Bits */
\r
16823 #define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING_OFS (24) /* WAIT_FOR_INTERRUPT_STALLING Offset */
\r
16824 #define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING_M (0x0f000000) /* */
\r
16825 #define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING0 (0x01000000) /* */
\r
16826 #define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING1 (0x02000000) /* */
\r
16827 #define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING2 (0x04000000) /* */
\r
16828 #define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING3 (0x08000000) /* */
\r
16829 #define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING_0 (0x00000000) /* not supported */
\r
16830 #define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING_1 (0x01000000) /* wait for interrupt supported */
\r
16831 /* SCB_ISAR0[SCB_ISAR0_BITCOUNT_INSTRS] Bits */
\r
16832 #define SCB_ISAR0_BITCOUNT_INSTRS_OFS ( 4) /* BITCOUNT_INSTRS Offset */
\r
16833 #define SCB_ISAR0_BITCOUNT_INSTRS_M (0x000000f0) /* */
\r
16834 #define SCB_ISAR0_BITCOUNT_INSTRS0 (0x00000010) /* */
\r
16835 #define SCB_ISAR0_BITCOUNT_INSTRS1 (0x00000020) /* */
\r
16836 #define SCB_ISAR0_BITCOUNT_INSTRS2 (0x00000040) /* */
\r
16837 #define SCB_ISAR0_BITCOUNT_INSTRS3 (0x00000080) /* */
\r
16838 #define SCB_ISAR0_BITCOUNT_INSTRS_0 (0x00000000) /* no bit-counting instructions present */
\r
16839 #define SCB_ISAR0_BITCOUNT_INSTRS_1 (0x00000010) /* adds CLZ */
\r
16840 /* SCB_ISAR0[SCB_ISAR0_BITFIELD_INSTRS] Bits */
\r
16841 #define SCB_ISAR0_BITFIELD_INSTRS_OFS ( 8) /* BITFIELD_INSTRS Offset */
\r
16842 #define SCB_ISAR0_BITFIELD_INSTRS_M (0x00000f00) /* */
\r
16843 #define SCB_ISAR0_BITFIELD_INSTRS0 (0x00000100) /* */
\r
16844 #define SCB_ISAR0_BITFIELD_INSTRS1 (0x00000200) /* */
\r
16845 #define SCB_ISAR0_BITFIELD_INSTRS2 (0x00000400) /* */
\r
16846 #define SCB_ISAR0_BITFIELD_INSTRS3 (0x00000800) /* */
\r
16847 #define SCB_ISAR0_BITFIELD_INSTRS_0 (0x00000000) /* no bitfield instructions present */
\r
16848 #define SCB_ISAR0_BITFIELD_INSTRS_1 (0x00000100) /* adds BFC, BFI, SBFX, UBFX */
\r
16849 /* SCB_ISAR0[SCB_ISAR0_CMPBRANCH_INSTRS] Bits */
\r
16850 #define SCB_ISAR0_CMPBRANCH_INSTRS_OFS (12) /* CMPBRANCH_INSTRS Offset */
\r
16851 #define SCB_ISAR0_CMPBRANCH_INSTRS_M (0x0000f000) /* */
\r
16852 #define SCB_ISAR0_CMPBRANCH_INSTRS0 (0x00001000) /* */
\r
16853 #define SCB_ISAR0_CMPBRANCH_INSTRS1 (0x00002000) /* */
\r
16854 #define SCB_ISAR0_CMPBRANCH_INSTRS2 (0x00004000) /* */
\r
16855 #define SCB_ISAR0_CMPBRANCH_INSTRS3 (0x00008000) /* */
\r
16856 #define SCB_ISAR0_CMPBRANCH_INSTRS_0 (0x00000000) /* no combined compare-and-branch instructions present */
\r
16857 #define SCB_ISAR0_CMPBRANCH_INSTRS_1 (0x00001000) /* adds CB{N}Z */
\r
16858 /* SCB_ISAR0[SCB_ISAR0_COPROC_INSTRS] Bits */
\r
16859 #define SCB_ISAR0_COPROC_INSTRS_OFS (16) /* COPROC_INSTRS Offset */
\r
16860 #define SCB_ISAR0_COPROC_INSTRS_M (0x000f0000) /* */
\r
16861 #define SCB_ISAR0_COPROC_INSTRS0 (0x00010000) /* */
\r
16862 #define SCB_ISAR0_COPROC_INSTRS1 (0x00020000) /* */
\r
16863 #define SCB_ISAR0_COPROC_INSTRS2 (0x00040000) /* */
\r
16864 #define SCB_ISAR0_COPROC_INSTRS3 (0x00080000) /* */
\r
16865 #define SCB_ISAR0_COPROC_INSTRS_0 (0x00000000) /* no coprocessor support, other than for separately attributed architectures such as CP15 or VFP */
\r
16866 #define SCB_ISAR0_COPROC_INSTRS_1 (0x00010000) /* adds generic CDP, LDC, MCR, MRC, STC */
\r
16867 #define SCB_ISAR0_COPROC_INSTRS_2 (0x00020000) /* adds generic CDP2, LDC2, MCR2, MRC2, STC2 */
\r
16868 #define SCB_ISAR0_COPROC_INSTRS_3 (0x00030000) /* adds generic MCRR, MRRC */
\r
16869 #define SCB_ISAR0_COPROC_INSTRS_4 (0x00040000) /* adds generic MCRR2, MRRC2 */
\r
16870 /* SCB_ISAR0[SCB_ISAR0_DEBUG_INSTRS] Bits */
\r
16871 #define SCB_ISAR0_DEBUG_INSTRS_OFS (20) /* DEBUG_INSTRS Offset */
\r
16872 #define SCB_ISAR0_DEBUG_INSTRS_M (0x00f00000) /* */
\r
16873 #define SCB_ISAR0_DEBUG_INSTRS0 (0x00100000) /* */
\r
16874 #define SCB_ISAR0_DEBUG_INSTRS1 (0x00200000) /* */
\r
16875 #define SCB_ISAR0_DEBUG_INSTRS2 (0x00400000) /* */
\r
16876 #define SCB_ISAR0_DEBUG_INSTRS3 (0x00800000) /* */
\r
16877 #define SCB_ISAR0_DEBUG_INSTRS_0 (0x00000000) /* no debug instructions present */
\r
16878 #define SCB_ISAR0_DEBUG_INSTRS_1 (0x00100000) /* adds BKPT */
\r
16879 /* SCB_ISAR0[SCB_ISAR0_DIVIDE_INSTRS] Bits */
\r
16880 #define SCB_ISAR0_DIVIDE_INSTRS_OFS (24) /* DIVIDE_INSTRS Offset */
\r
16881 #define SCB_ISAR0_DIVIDE_INSTRS_M (0x0f000000) /* */
\r
16882 #define SCB_ISAR0_DIVIDE_INSTRS0 (0x01000000) /* */
\r
16883 #define SCB_ISAR0_DIVIDE_INSTRS1 (0x02000000) /* */
\r
16884 #define SCB_ISAR0_DIVIDE_INSTRS2 (0x04000000) /* */
\r
16885 #define SCB_ISAR0_DIVIDE_INSTRS3 (0x08000000) /* */
\r
16886 #define SCB_ISAR0_DIVIDE_INSTRS_0 (0x00000000) /* no divide instructions present */
\r
16887 #define SCB_ISAR0_DIVIDE_INSTRS_1 (0x01000000) /* adds SDIV, UDIV (v1 quotient only result) */
\r
16888 /* SCB_ISAR1[SCB_ISAR1_ETEND_INSRS] Bits */
\r
16889 #define SCB_ISAR1_ETEND_INSRS_OFS (12) /* EXTEND_INSRS Offset */
\r
16890 #define SCB_ISAR1_ETEND_INSRS_M (0x0000f000) /* */
\r
16891 #define SCB_ISAR1_ETEND_INSRS0 (0x00001000) /* */
\r
16892 #define SCB_ISAR1_ETEND_INSRS1 (0x00002000) /* */
\r
16893 #define SCB_ISAR1_ETEND_INSRS2 (0x00004000) /* */
\r
16894 #define SCB_ISAR1_ETEND_INSRS3 (0x00008000) /* */
\r
16895 #define SCB_ISAR1_ETEND_INSRS_0 (0x00000000) /* no scalar (i.e. non-SIMD) sign/zero-extend instructions present */
\r
16896 #define SCB_ISAR1_ETEND_INSRS_1 (0x00001000) /* adds SXTB, SXTH, UXTB, UXTH */
\r
16897 #define SCB_ISAR1_ETEND_INSRS_2 (0x00002000) /* N/A */
\r
16898 /* SCB_ISAR1[SCB_ISAR1_IFTHEN_INSTRS] Bits */
\r
16899 #define SCB_ISAR1_IFTHEN_INSTRS_OFS (16) /* IFTHEN_INSTRS Offset */
\r
16900 #define SCB_ISAR1_IFTHEN_INSTRS_M (0x000f0000) /* */
\r
16901 #define SCB_ISAR1_IFTHEN_INSTRS0 (0x00010000) /* */
\r
16902 #define SCB_ISAR1_IFTHEN_INSTRS1 (0x00020000) /* */
\r
16903 #define SCB_ISAR1_IFTHEN_INSTRS2 (0x00040000) /* */
\r
16904 #define SCB_ISAR1_IFTHEN_INSTRS3 (0x00080000) /* */
\r
16905 #define SCB_ISAR1_IFTHEN_INSTRS_0 (0x00000000) /* IT instructions not present */
\r
16906 #define SCB_ISAR1_IFTHEN_INSTRS_1 (0x00010000) /* adds IT instructions (and IT bits in PSRs) */
\r
16907 /* SCB_ISAR1[SCB_ISAR1_IMMEDIATE_INSTRS] Bits */
\r
16908 #define SCB_ISAR1_IMMEDIATE_INSTRS_OFS (20) /* IMMEDIATE_INSTRS Offset */
\r
16909 #define SCB_ISAR1_IMMEDIATE_INSTRS_M (0x00f00000) /* */
\r
16910 #define SCB_ISAR1_IMMEDIATE_INSTRS0 (0x00100000) /* */
\r
16911 #define SCB_ISAR1_IMMEDIATE_INSTRS1 (0x00200000) /* */
\r
16912 #define SCB_ISAR1_IMMEDIATE_INSTRS2 (0x00400000) /* */
\r
16913 #define SCB_ISAR1_IMMEDIATE_INSTRS3 (0x00800000) /* */
\r
16914 #define SCB_ISAR1_IMMEDIATE_INSTRS_0 (0x00000000) /* no special immediate-generating instructions present */
\r
16915 #define SCB_ISAR1_IMMEDIATE_INSTRS_1 (0x00100000) /* adds ADDW, MOVW, MOVT, SUBW */
\r
16916 /* SCB_ISAR1[SCB_ISAR1_INTERWORK_INSTRS] Bits */
\r
16917 #define SCB_ISAR1_INTERWORK_INSTRS_OFS (24) /* INTERWORK_INSTRS Offset */
\r
16918 #define SCB_ISAR1_INTERWORK_INSTRS_M (0x0f000000) /* */
\r
16919 #define SCB_ISAR1_INTERWORK_INSTRS0 (0x01000000) /* */
\r
16920 #define SCB_ISAR1_INTERWORK_INSTRS1 (0x02000000) /* */
\r
16921 #define SCB_ISAR1_INTERWORK_INSTRS2 (0x04000000) /* */
\r
16922 #define SCB_ISAR1_INTERWORK_INSTRS3 (0x08000000) /* */
\r
16923 #define SCB_ISAR1_INTERWORK_INSTRS_0 (0x00000000) /* no interworking instructions supported */
\r
16924 #define SCB_ISAR1_INTERWORK_INSTRS_1 (0x01000000) /* adds BX (and T bit in PSRs) */
\r
16925 #define SCB_ISAR1_INTERWORK_INSTRS_2 (0x02000000) /* adds BLX, and PC loads have BX-like behavior */
\r
16926 #define SCB_ISAR1_INTERWORK_INSTRS_3 (0x03000000) /* N/A */
\r
16927 /* SCB_ISAR2[SCB_ISAR2_LOADSTORE_INSTRS] Bits */
\r
16928 #define SCB_ISAR2_LOADSTORE_INSTRS_OFS ( 0) /* LOADSTORE_INSTRS Offset */
\r
16929 #define SCB_ISAR2_LOADSTORE_INSTRS_M (0x0000000f) /* */
\r
16930 #define SCB_ISAR2_LOADSTORE_INSTRS0 (0x00000001) /* */
\r
16931 #define SCB_ISAR2_LOADSTORE_INSTRS1 (0x00000002) /* */
\r
16932 #define SCB_ISAR2_LOADSTORE_INSTRS2 (0x00000004) /* */
\r
16933 #define SCB_ISAR2_LOADSTORE_INSTRS3 (0x00000008) /* */
\r
16934 #define SCB_ISAR2_LOADSTORE_INSTRS_0 (0x00000000) /* no additional normal load/store instructions present */
\r
16935 #define SCB_ISAR2_LOADSTORE_INSTRS_1 (0x00000001) /* adds LDRD/STRD */
\r
16936 /* SCB_ISAR2[SCB_ISAR2_MEMHINT_INSTRS] Bits */
\r
16937 #define SCB_ISAR2_MEMHINT_INSTRS_OFS ( 4) /* MEMHINT_INSTRS Offset */
\r
16938 #define SCB_ISAR2_MEMHINT_INSTRS_M (0x000000f0) /* */
\r
16939 #define SCB_ISAR2_MEMHINT_INSTRS0 (0x00000010) /* */
\r
16940 #define SCB_ISAR2_MEMHINT_INSTRS1 (0x00000020) /* */
\r
16941 #define SCB_ISAR2_MEMHINT_INSTRS2 (0x00000040) /* */
\r
16942 #define SCB_ISAR2_MEMHINT_INSTRS3 (0x00000080) /* */
\r
16943 #define SCB_ISAR2_MEMHINT_INSTRS_0 (0x00000000) /* no memory hint instructions presen */
\r
16944 #define SCB_ISAR2_MEMHINT_INSTRS_1 (0x00000010) /* adds PLD */
\r
16945 #define SCB_ISAR2_MEMHINT_INSTRS_2 (0x00000020) /* adds PLD (ie a repeat on value 1) */
\r
16946 #define SCB_ISAR2_MEMHINT_INSTRS_3 (0x00000030) /* adds PLI */
\r
16947 /* SCB_ISAR2[SCB_ISAR2_MULTIACCESSINT_INSTRS] Bits */
\r
16948 #define SCB_ISAR2_MULTIACCESSINT_INSTRS_OFS ( 8) /* MULTIACCESSINT_INSTRS Offset */
\r
16949 #define SCB_ISAR2_MULTIACCESSINT_INSTRS_M (0x00000f00) /* */
\r
16950 #define SCB_ISAR2_MULTIACCESSINT_INSTRS0 (0x00000100) /* */
\r
16951 #define SCB_ISAR2_MULTIACCESSINT_INSTRS1 (0x00000200) /* */
\r
16952 #define SCB_ISAR2_MULTIACCESSINT_INSTRS2 (0x00000400) /* */
\r
16953 #define SCB_ISAR2_MULTIACCESSINT_INSTRS3 (0x00000800) /* */
\r
16954 #define SCB_ISAR2_MULTIACCESSINT_INSTRS_0 (0x00000000) /* the (LDM/STM) instructions are non-interruptible */
\r
16955 #define SCB_ISAR2_MULTIACCESSINT_INSTRS_1 (0x00000100) /* the (LDM/STM) instructions are restartable */
\r
16956 #define SCB_ISAR2_MULTIACCESSINT_INSTRS_2 (0x00000200) /* the (LDM/STM) instructions are continuable */
\r
16957 /* SCB_ISAR2[SCB_ISAR2_MULT_INSTRS] Bits */
\r
16958 #define SCB_ISAR2_MULT_INSTRS_OFS (12) /* MULT_INSTRS Offset */
\r
16959 #define SCB_ISAR2_MULT_INSTRS_M (0x0000f000) /* */
\r
16960 #define SCB_ISAR2_MULT_INSTRS0 (0x00001000) /* */
\r
16961 #define SCB_ISAR2_MULT_INSTRS1 (0x00002000) /* */
\r
16962 #define SCB_ISAR2_MULT_INSTRS2 (0x00004000) /* */
\r
16963 #define SCB_ISAR2_MULT_INSTRS3 (0x00008000) /* */
\r
16964 #define SCB_ISAR2_MULT_INSTRS_0 (0x00000000) /* only MUL present */
\r
16965 #define SCB_ISAR2_MULT_INSTRS_1 (0x00001000) /* adds MLA */
\r
16966 #define SCB_ISAR2_MULT_INSTRS_2 (0x00002000) /* adds MLS */
\r
16967 /* SCB_ISAR2[SCB_ISAR2_MULTS_INSTRS] Bits */
\r
16968 #define SCB_ISAR2_MULTS_INSTRS_OFS (16) /* MULTS_INSTRS Offset */
\r
16969 #define SCB_ISAR2_MULTS_INSTRS_M (0x000f0000) /* */
\r
16970 #define SCB_ISAR2_MULTS_INSTRS0 (0x00010000) /* */
\r
16971 #define SCB_ISAR2_MULTS_INSTRS1 (0x00020000) /* */
\r
16972 #define SCB_ISAR2_MULTS_INSTRS2 (0x00040000) /* */
\r
16973 #define SCB_ISAR2_MULTS_INSTRS3 (0x00080000) /* */
\r
16974 #define SCB_ISAR2_MULTS_INSTRS_0 (0x00000000) /* no signed multiply instructions present */
\r
16975 #define SCB_ISAR2_MULTS_INSTRS_1 (0x00010000) /* adds SMULL, SMLAL */
\r
16976 #define SCB_ISAR2_MULTS_INSTRS_2 (0x00020000) /* N/A */
\r
16977 #define SCB_ISAR2_MULTS_INSTRS_3 (0x00030000) /* N/A */
\r
16978 /* SCB_ISAR2[SCB_ISAR2_MULTU_INSTRS] Bits */
\r
16979 #define SCB_ISAR2_MULTU_INSTRS_OFS (20) /* MULTU_INSTRS Offset */
\r
16980 #define SCB_ISAR2_MULTU_INSTRS_M (0x00f00000) /* */
\r
16981 #define SCB_ISAR2_MULTU_INSTRS0 (0x00100000) /* */
\r
16982 #define SCB_ISAR2_MULTU_INSTRS1 (0x00200000) /* */
\r
16983 #define SCB_ISAR2_MULTU_INSTRS2 (0x00400000) /* */
\r
16984 #define SCB_ISAR2_MULTU_INSTRS3 (0x00800000) /* */
\r
16985 #define SCB_ISAR2_MULTU_INSTRS_0 (0x00000000) /* no unsigned multiply instructions present */
\r
16986 #define SCB_ISAR2_MULTU_INSTRS_1 (0x00100000) /* adds UMULL, UMLAL */
\r
16987 #define SCB_ISAR2_MULTU_INSTRS_2 (0x00200000) /* N/A */
\r
16988 /* SCB_ISAR2[SCB_ISAR2_REVERSAL_INSTRS] Bits */
\r
16989 #define SCB_ISAR2_REVERSAL_INSTRS_OFS (28) /* REVERSAL_INSTRS Offset */
\r
16990 #define SCB_ISAR2_REVERSAL_INSTRS_M (0xf0000000) /* */
\r
16991 #define SCB_ISAR2_REVERSAL_INSTRS0 (0x10000000) /* */
\r
16992 #define SCB_ISAR2_REVERSAL_INSTRS1 (0x20000000) /* */
\r
16993 #define SCB_ISAR2_REVERSAL_INSTRS2 (0x40000000) /* */
\r
16994 #define SCB_ISAR2_REVERSAL_INSTRS3 (0x80000000) /* */
\r
16995 #define SCB_ISAR2_REVERSAL_INSTRS_0 (0x00000000) /* no reversal instructions present */
\r
16996 #define SCB_ISAR2_REVERSAL_INSTRS_1 (0x10000000) /* adds REV, REV16, REVSH */
\r
16997 #define SCB_ISAR2_REVERSAL_INSTRS_2 (0x20000000) /* adds RBIT */
\r
16998 /* SCB_ISAR3[SCB_ISAR3_SATRUATE_INSTRS] Bits */
\r
16999 #define SCB_ISAR3_SATRUATE_INSTRS_OFS ( 0) /* SATRUATE_INSTRS Offset */
\r
17000 #define SCB_ISAR3_SATRUATE_INSTRS_M (0x0000000f) /* */
\r
17001 #define SCB_ISAR3_SATRUATE_INSTRS0 (0x00000001) /* */
\r
17002 #define SCB_ISAR3_SATRUATE_INSTRS1 (0x00000002) /* */
\r
17003 #define SCB_ISAR3_SATRUATE_INSTRS2 (0x00000004) /* */
\r
17004 #define SCB_ISAR3_SATRUATE_INSTRS3 (0x00000008) /* */
\r
17005 #define SCB_ISAR3_SATRUATE_INSTRS_0 (0x00000000) /* no non-SIMD saturate instructions present */
\r
17006 #define SCB_ISAR3_SATRUATE_INSTRS_1 (0x00000001) /* N/A */
\r
17007 /* SCB_ISAR3[SCB_ISAR3_SIMD_INSTRS] Bits */
\r
17008 #define SCB_ISAR3_SIMD_INSTRS_OFS ( 4) /* SIMD_INSTRS Offset */
\r
17009 #define SCB_ISAR3_SIMD_INSTRS_M (0x000000f0) /* */
\r
17010 #define SCB_ISAR3_SIMD_INSTRS0 (0x00000010) /* */
\r
17011 #define SCB_ISAR3_SIMD_INSTRS1 (0x00000020) /* */
\r
17012 #define SCB_ISAR3_SIMD_INSTRS2 (0x00000040) /* */
\r
17013 #define SCB_ISAR3_SIMD_INSTRS3 (0x00000080) /* */
\r
17014 #define SCB_ISAR3_SIMD_INSTRS_0 (0x00000000) /* no SIMD instructions present */
\r
17015 #define SCB_ISAR3_SIMD_INSTRS_1 (0x00000010) /* adds SSAT, USAT (and the Q flag in the PSRs) */
\r
17016 #define SCB_ISAR3_SIMD_INSTRS_3 (0x00000030) /* N/A */
\r
17017 /* SCB_ISAR3[SCB_ISAR3_SVC_INSTRS] Bits */
\r
17018 #define SCB_ISAR3_SVC_INSTRS_OFS ( 8) /* SVC_INSTRS Offset */
\r
17019 #define SCB_ISAR3_SVC_INSTRS_M (0x00000f00) /* */
\r
17020 #define SCB_ISAR3_SVC_INSTRS0 (0x00000100) /* */
\r
17021 #define SCB_ISAR3_SVC_INSTRS1 (0x00000200) /* */
\r
17022 #define SCB_ISAR3_SVC_INSTRS2 (0x00000400) /* */
\r
17023 #define SCB_ISAR3_SVC_INSTRS3 (0x00000800) /* */
\r
17024 #define SCB_ISAR3_SVC_INSTRS_0 (0x00000000) /* no SVC (SWI) instructions present */
\r
17025 #define SCB_ISAR3_SVC_INSTRS_1 (0x00000100) /* adds SVC (SWI) */
\r
17026 /* SCB_ISAR3[SCB_ISAR3_SYNCPRIM_INSTRS] Bits */
\r
17027 #define SCB_ISAR3_SYNCPRIM_INSTRS_OFS (12) /* SYNCPRIM_INSTRS Offset */
\r
17028 #define SCB_ISAR3_SYNCPRIM_INSTRS_M (0x0000f000) /* */
\r
17029 #define SCB_ISAR3_SYNCPRIM_INSTRS0 (0x00001000) /* */
\r
17030 #define SCB_ISAR3_SYNCPRIM_INSTRS1 (0x00002000) /* */
\r
17031 #define SCB_ISAR3_SYNCPRIM_INSTRS2 (0x00004000) /* */
\r
17032 #define SCB_ISAR3_SYNCPRIM_INSTRS3 (0x00008000) /* */
\r
17033 #define SCB_ISAR3_SYNCPRIM_INSTRS_0 (0x00000000) /* no synchronization primitives present */
\r
17034 #define SCB_ISAR3_SYNCPRIM_INSTRS_1 (0x00001000) /* adds LDREX, STREX */
\r
17035 #define SCB_ISAR3_SYNCPRIM_INSTRS_2 (0x00002000) /* adds LDREXB, LDREXH, LDREXD, STREXB, STREXH, STREXD, CLREX(N/A) */
\r
17036 /* SCB_ISAR3[SCB_ISAR3_TABBRANCH_INSTRS] Bits */
\r
17037 #define SCB_ISAR3_TABBRANCH_INSTRS_OFS (16) /* TABBRANCH_INSTRS Offset */
\r
17038 #define SCB_ISAR3_TABBRANCH_INSTRS_M (0x000f0000) /* */
\r
17039 #define SCB_ISAR3_TABBRANCH_INSTRS0 (0x00010000) /* */
\r
17040 #define SCB_ISAR3_TABBRANCH_INSTRS1 (0x00020000) /* */
\r
17041 #define SCB_ISAR3_TABBRANCH_INSTRS2 (0x00040000) /* */
\r
17042 #define SCB_ISAR3_TABBRANCH_INSTRS3 (0x00080000) /* */
\r
17043 #define SCB_ISAR3_TABBRANCH_INSTRS_0 (0x00000000) /* no table-branch instructions present */
\r
17044 #define SCB_ISAR3_TABBRANCH_INSTRS_1 (0x00010000) /* adds TBB, TBH */
\r
17045 /* SCB_ISAR3[SCB_ISAR3_THUMBCOPY_INSTRS] Bits */
\r
17046 #define SCB_ISAR3_THUMBCOPY_INSTRS_OFS (20) /* THUMBCOPY_INSTRS Offset */
\r
17047 #define SCB_ISAR3_THUMBCOPY_INSTRS_M (0x00f00000) /* */
\r
17048 #define SCB_ISAR3_THUMBCOPY_INSTRS0 (0x00100000) /* */
\r
17049 #define SCB_ISAR3_THUMBCOPY_INSTRS1 (0x00200000) /* */
\r
17050 #define SCB_ISAR3_THUMBCOPY_INSTRS2 (0x00400000) /* */
\r
17051 #define SCB_ISAR3_THUMBCOPY_INSTRS3 (0x00800000) /* */
\r
17052 #define SCB_ISAR3_THUMBCOPY_INSTRS_0 (0x00000000) /* Thumb MOV(register) instruction does not allow low reg -> low reg */
\r
17053 #define SCB_ISAR3_THUMBCOPY_INSTRS_1 (0x00100000) /* adds Thumb MOV(register) low reg -> low reg and the CPY alias */
\r
17054 /* SCB_ISAR3[SCB_ISAR3_TRUENOP_INSTRS] Bits */
\r
17055 #define SCB_ISAR3_TRUENOP_INSTRS_OFS (24) /* TRUENOP_INSTRS Offset */
\r
17056 #define SCB_ISAR3_TRUENOP_INSTRS_M (0x0f000000) /* */
\r
17057 #define SCB_ISAR3_TRUENOP_INSTRS0 (0x01000000) /* */
\r
17058 #define SCB_ISAR3_TRUENOP_INSTRS1 (0x02000000) /* */
\r
17059 #define SCB_ISAR3_TRUENOP_INSTRS2 (0x04000000) /* */
\r
17060 #define SCB_ISAR3_TRUENOP_INSTRS3 (0x08000000) /* */
\r
17061 #define SCB_ISAR3_TRUENOP_INSTRS_0 (0x00000000) /* true NOP instructions not present - that is, NOP instructions with no register dependencies */
\r
17062 #define SCB_ISAR3_TRUENOP_INSTRS_1 (0x01000000) /* adds "true NOP", and the capability of additional "NOP compatible hints" */
\r
17063 /* SCB_ISAR4[SCB_ISAR4_UNPRIV_INSTRS] Bits */
\r
17064 #define SCB_ISAR4_UNPRIV_INSTRS_OFS ( 0) /* UNPRIV_INSTRS Offset */
\r
17065 #define SCB_ISAR4_UNPRIV_INSTRS_M (0x0000000f) /* */
\r
17066 #define SCB_ISAR4_UNPRIV_INSTRS0 (0x00000001) /* */
\r
17067 #define SCB_ISAR4_UNPRIV_INSTRS1 (0x00000002) /* */
\r
17068 #define SCB_ISAR4_UNPRIV_INSTRS2 (0x00000004) /* */
\r
17069 #define SCB_ISAR4_UNPRIV_INSTRS3 (0x00000008) /* */
\r
17070 #define SCB_ISAR4_UNPRIV_INSTRS_0 (0x00000000) /* no "T variant" instructions exist */
\r
17071 #define SCB_ISAR4_UNPRIV_INSTRS_1 (0x00000001) /* adds LDRBT, LDRT, STRBT, STRT */
\r
17072 #define SCB_ISAR4_UNPRIV_INSTRS_2 (0x00000002) /* adds LDRHT, LDRSBT, LDRSHT, STRHT */
\r
17073 /* SCB_ISAR4[SCB_ISAR4_WITHSHIFTS_INSTRS] Bits */
\r
17074 #define SCB_ISAR4_WITHSHIFTS_INSTRS_OFS ( 4) /* WITHSHIFTS_INSTRS Offset */
\r
17075 #define SCB_ISAR4_WITHSHIFTS_INSTRS_M (0x000000f0) /* */
\r
17076 #define SCB_ISAR4_WITHSHIFTS_INSTRS0 (0x00000010) /* */
\r
17077 #define SCB_ISAR4_WITHSHIFTS_INSTRS1 (0x00000020) /* */
\r
17078 #define SCB_ISAR4_WITHSHIFTS_INSTRS2 (0x00000040) /* */
\r
17079 #define SCB_ISAR4_WITHSHIFTS_INSTRS3 (0x00000080) /* */
\r
17080 #define SCB_ISAR4_WITHSHIFTS_INSTRS_0 (0x00000000) /* non-zero shifts only support MOV and shift instructions (see notes) */
\r
17081 #define SCB_ISAR4_WITHSHIFTS_INSTRS_1 (0x00000010) /* shifts of loads/stores over the range LSL 0-3 */
\r
17082 #define SCB_ISAR4_WITHSHIFTS_INSTRS_3 (0x00000030) /* adds other constant shift options. */
\r
17083 #define SCB_ISAR4_WITHSHIFTS_INSTRS_4 (0x00000040) /* adds register-controlled shift options. */
\r
17084 /* SCB_ISAR4[SCB_ISAR4_WRITEBACK_INSTRS] Bits */
\r
17085 #define SCB_ISAR4_WRITEBACK_INSTRS_OFS ( 8) /* WRITEBACK_INSTRS Offset */
\r
17086 #define SCB_ISAR4_WRITEBACK_INSTRS_M (0x00000f00) /* */
\r
17087 #define SCB_ISAR4_WRITEBACK_INSTRS0 (0x00000100) /* */
\r
17088 #define SCB_ISAR4_WRITEBACK_INSTRS1 (0x00000200) /* */
\r
17089 #define SCB_ISAR4_WRITEBACK_INSTRS2 (0x00000400) /* */
\r
17090 #define SCB_ISAR4_WRITEBACK_INSTRS3 (0x00000800) /* */
\r
17091 #define SCB_ISAR4_WRITEBACK_INSTRS_0 (0x00000000) /* only non-writeback addressing modes present, except that LDMIA/STMDB/PUSH/POP instructions support writeback addressing. */
\r
17092 #define SCB_ISAR4_WRITEBACK_INSTRS_1 (0x00000100) /* adds all currently-defined writeback addressing modes (ARMv7, Thumb-2) */
\r
17093 /* SCB_ISAR4[SCB_ISAR4_BARRIER_INSTRS] Bits */
\r
17094 #define SCB_ISAR4_BARRIER_INSTRS_OFS (16) /* BARRIER_INSTRS Offset */
\r
17095 #define SCB_ISAR4_BARRIER_INSTRS_M (0x000f0000) /* */
\r
17096 #define SCB_ISAR4_BARRIER_INSTRS0 (0x00010000) /* */
\r
17097 #define SCB_ISAR4_BARRIER_INSTRS1 (0x00020000) /* */
\r
17098 #define SCB_ISAR4_BARRIER_INSTRS2 (0x00040000) /* */
\r
17099 #define SCB_ISAR4_BARRIER_INSTRS3 (0x00080000) /* */
\r
17100 #define SCB_ISAR4_BARRIER_INSTRS_0 (0x00000000) /* no barrier instructions supported */
\r
17101 #define SCB_ISAR4_BARRIER_INSTRS_1 (0x00010000) /* adds DMB, DSB, ISB barrier instructions */
\r
17102 /* SCB_ISAR4[SCB_ISAR4_SYNCPRIM_INSTRS_FRAC] Bits */
\r
17103 #define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC_OFS (20) /* SYNCPRIM_INSTRS_FRAC Offset */
\r
17104 #define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC_M (0x00f00000) /* */
\r
17105 #define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC0 (0x00100000) /* */
\r
17106 #define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC1 (0x00200000) /* */
\r
17107 #define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC2 (0x00400000) /* */
\r
17108 #define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC3 (0x00800000) /* */
\r
17109 #define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC_0 (0x00000000) /* no additional support */
\r
17110 #define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC_3 (0x00300000) /* adds CLREX, LDREXB, STREXB, LDREXH, STREXH */
\r
17111 /* SCB_ISAR4[SCB_ISAR4_PSR_M_INSTRS] Bits */
\r
17112 #define SCB_ISAR4_PSR_M_INSTRS_OFS (24) /* PSR_M_INSTRS Offset */
\r
17113 #define SCB_ISAR4_PSR_M_INSTRS_M (0x0f000000) /* */
\r
17114 #define SCB_ISAR4_PSR_M_INSTRS0 (0x01000000) /* */
\r
17115 #define SCB_ISAR4_PSR_M_INSTRS1 (0x02000000) /* */
\r
17116 #define SCB_ISAR4_PSR_M_INSTRS2 (0x04000000) /* */
\r
17117 #define SCB_ISAR4_PSR_M_INSTRS3 (0x08000000) /* */
\r
17118 #define SCB_ISAR4_PSR_M_INSTRS_0 (0x00000000) /* instructions not present */
\r
17119 #define SCB_ISAR4_PSR_M_INSTRS_1 (0x01000000) /* adds CPS, MRS, and MSR instructions (M-profile forms) */
\r
17120 /* SCB_CPACR[SCB_CPACR_CP11] Bits */
\r
17121 #define SCB_CPACR_CP11_OFS (22) /* CP11 Offset */
\r
17122 #define SCB_CPACR_CP11_M (0x00c00000) /* */
\r
17123 /* SCB_CPACR[SCB_CPACR_CP10] Bits */
\r
17124 #define SCB_CPACR_CP10_OFS (20) /* CP10 Offset */
\r
17125 #define SCB_CPACR_CP10_M (0x00300000) /* */
\r
17128 //*****************************************************************************
\r
17130 //*****************************************************************************
\r
17131 /* SCSCB_ICTR[SCNSCB_ICTR_INTLINESNUM] Bits */
\r
17132 #define SCNSCB_ICTR_INTLINESNUM_OFS ( 0) /* INTLINESNUM Offset */
\r
17133 #define SCNSCB_ICTR_INTLINESNUM_M (0x0000001f) /* */
\r
17134 /* SCSCB_ACTLR[SCNSCB_ACTLR_DISMCYCINT] Bits */
\r
17135 #define SCNSCB_ACTLR_DISMCYCINT_OFS ( 0) /* DISMCYCINT Offset */
\r
17136 #define SCNSCB_ACTLR_DISMCYCINT (0x00000001) /* */
\r
17137 /* SCSCB_ACTLR[SCNSCB_ACTLR_DISDEFWBUF] Bits */
\r
17138 #define SCNSCB_ACTLR_DISDEFWBUF_OFS ( 1) /* DISDEFWBUF Offset */
\r
17139 #define SCNSCB_ACTLR_DISDEFWBUF (0x00000002) /* */
\r
17140 /* SCSCB_ACTLR[SCNSCB_ACTLR_DISFOLD] Bits */
\r
17141 #define SCNSCB_ACTLR_DISFOLD_OFS ( 2) /* DISFOLD Offset */
\r
17142 #define SCNSCB_ACTLR_DISFOLD (0x00000004) /* */
\r
17145 //*****************************************************************************
\r
17147 //*****************************************************************************
\r
17148 /* SYSCTL_REBOOT_CTL[SYSCTL_REBOOT_CTL_REBOOT] Bits */
\r
17149 #define SYSCTL_REBOOT_CTL_REBOOT_OFS ( 0) /* REBOOT Offset */
\r
17150 #define SYSCTL_REBOOT_CTL_REBOOT (0x00000001) /* Write 1 initiates a Reboot of the device */
\r
17151 /* SYSCTL_REBOOT_CTL[SYSCTL_REBOOT_CTL_WKEY] Bits */
\r
17152 #define SYSCTL_REBOOT_CTL_WKEY_OFS ( 8) /* WKEY Offset */
\r
17153 #define SYSCTL_REBOOT_CTL_WKEY_M (0x0000ff00) /* Key to enable writes to bit 0 */
\r
17154 /* SYSCTL_NMI_CTLSTAT[SYSCTL_NMI_CTLSTAT_CS_SRC] Bits */
\r
17155 #define SYSCTL_NMI_CTLSTAT_CS_SRC_OFS ( 0) /* CS_SRC Offset */
\r
17156 #define SYSCTL_NMI_CTLSTAT_CS_SRC (0x00000001) /* CS interrupt as a source of NMI */
\r
17157 /* SYSCTL_NMI_CTLSTAT[SYSCTL_NMI_CTLSTAT_PSS_SRC] Bits */
\r
17158 #define SYSCTL_NMI_CTLSTAT_PSS_SRC_OFS ( 1) /* PSS_SRC Offset */
\r
17159 #define SYSCTL_NMI_CTLSTAT_PSS_SRC (0x00000002) /* PSS interrupt as a source of NMI */
\r
17160 /* SYSCTL_NMI_CTLSTAT[SYSCTL_NMI_CTLSTAT_PCM_SRC] Bits */
\r
17161 #define SYSCTL_NMI_CTLSTAT_PCM_SRC_OFS ( 2) /* PCM_SRC Offset */
\r
17162 #define SYSCTL_NMI_CTLSTAT_PCM_SRC (0x00000004) /* PCM interrupt as a source of NMI */
\r
17163 /* SYSCTL_NMI_CTLSTAT[SYSCTL_NMI_CTLSTAT_PIN_SRC] Bits */
\r
17164 #define SYSCTL_NMI_CTLSTAT_PIN_SRC_OFS ( 3) /* PIN_SRC Offset */
\r
17165 #define SYSCTL_NMI_CTLSTAT_PIN_SRC (0x00000008) /* */
\r
17166 /* SYSCTL_NMI_CTLSTAT[SYSCTL_NMI_CTLSTAT_CS_FLG] Bits */
\r
17167 #define SYSCTL_NMI_CTLSTAT_CS_FLG_OFS (16) /* CS_FLG Offset */
\r
17168 #define SYSCTL_NMI_CTLSTAT_CS_FLG (0x00010000) /* CS interrupt was the source of NMI */
\r
17169 /* SYSCTL_NMI_CTLSTAT[SYSCTL_NMI_CTLSTAT_PSS_FLG] Bits */
\r
17170 #define SYSCTL_NMI_CTLSTAT_PSS_FLG_OFS (17) /* PSS_FLG Offset */
\r
17171 #define SYSCTL_NMI_CTLSTAT_PSS_FLG (0x00020000) /* PSS interrupt was the source of NMI */
\r
17172 /* SYSCTL_NMI_CTLSTAT[SYSCTL_NMI_CTLSTAT_PCM_FLG] Bits */
\r
17173 #define SYSCTL_NMI_CTLSTAT_PCM_FLG_OFS (18) /* PCM_FLG Offset */
\r
17174 #define SYSCTL_NMI_CTLSTAT_PCM_FLG (0x00040000) /* PCM interrupt was the source of NMI */
\r
17175 /* SYSCTL_NMI_CTLSTAT[SYSCTL_NMI_CTLSTAT_PIN_FLG] Bits */
\r
17176 #define SYSCTL_NMI_CTLSTAT_PIN_FLG_OFS (19) /* PIN_FLG Offset */
\r
17177 #define SYSCTL_NMI_CTLSTAT_PIN_FLG (0x00080000) /* RSTn/NMI pin was the source of NMI */
\r
17178 /* SYSCTL_WDTRESET_CTL[SYSCTL_WDTRESET_CTL_TIMEOUT] Bits */
\r
17179 #define SYSCTL_WDTRESET_CTL_TIMEOUT_OFS ( 0) /* TIMEOUT Offset */
\r
17180 #define SYSCTL_WDTRESET_CTL_TIMEOUT (0x00000001) /* WDT timeout reset type */
\r
17181 /* SYSCTL_WDTRESET_CTL[SYSCTL_WDTRESET_CTL_VIOLATION] Bits */
\r
17182 #define SYSCTL_WDTRESET_CTL_VIOLATION_OFS ( 1) /* VIOLATION Offset */
\r
17183 #define SYSCTL_WDTRESET_CTL_VIOLATION (0x00000002) /* WDT password violation reset type */
\r
17184 /* SYSCTL_PERIHALT_CTL[SYSCTL_PERIHALT_CTL_T16_0] Bits */
\r
17185 #define SYSCTL_PERIHALT_CTL_T16_0_OFS ( 0) /* T16_0 Offset */
\r
17186 #define SYSCTL_PERIHALT_CTL_T16_0 (0x00000001) /* Freezes IP operation when CPU is halted */
\r
17187 /* SYSCTL_PERIHALT_CTL[SYSCTL_PERIHALT_CTL_T16_1] Bits */
\r
17188 #define SYSCTL_PERIHALT_CTL_T16_1_OFS ( 1) /* T16_1 Offset */
\r
17189 #define SYSCTL_PERIHALT_CTL_T16_1 (0x00000002) /* Freezes IP operation when CPU is halted */
\r
17190 /* SYSCTL_PERIHALT_CTL[SYSCTL_PERIHALT_CTL_T16_2] Bits */
\r
17191 #define SYSCTL_PERIHALT_CTL_T16_2_OFS ( 2) /* T16_2 Offset */
\r
17192 #define SYSCTL_PERIHALT_CTL_T16_2 (0x00000004) /* Freezes IP operation when CPU is halted */
\r
17193 /* SYSCTL_PERIHALT_CTL[SYSCTL_PERIHALT_CTL_T16_3] Bits */
\r
17194 #define SYSCTL_PERIHALT_CTL_T16_3_OFS ( 3) /* T16_3 Offset */
\r
17195 #define SYSCTL_PERIHALT_CTL_T16_3 (0x00000008) /* Freezes IP operation when CPU is halted */
\r
17196 /* SYSCTL_PERIHALT_CTL[SYSCTL_PERIHALT_CTL_T32_0] Bits */
\r
17197 #define SYSCTL_PERIHALT_CTL_T32_0_OFS ( 4) /* T32_0 Offset */
\r
17198 #define SYSCTL_PERIHALT_CTL_T32_0 (0x00000010) /* Freezes IP operation when CPU is halted */
\r
17199 /* SYSCTL_PERIHALT_CTL[SYSCTL_PERIHALT_CTL_EUA0] Bits */
\r
17200 #define SYSCTL_PERIHALT_CTL_EUA0_OFS ( 5) /* eUA0 Offset */
\r
17201 #define SYSCTL_PERIHALT_CTL_EUA0 (0x00000020) /* Freezes IP operation when CPU is halted */
\r
17202 /* SYSCTL_PERIHALT_CTL[SYSCTL_PERIHALT_CTL_EUA1] Bits */
\r
17203 #define SYSCTL_PERIHALT_CTL_EUA1_OFS ( 6) /* eUA1 Offset */
\r
17204 #define SYSCTL_PERIHALT_CTL_EUA1 (0x00000040) /* Freezes IP operation when CPU is halted */
\r
17205 /* SYSCTL_PERIHALT_CTL[SYSCTL_PERIHALT_CTL_EUA2] Bits */
\r
17206 #define SYSCTL_PERIHALT_CTL_EUA2_OFS ( 7) /* eUA2 Offset */
\r
17207 #define SYSCTL_PERIHALT_CTL_EUA2 (0x00000080) /* Freezes IP operation when CPU is halted */
\r
17208 /* SYSCTL_PERIHALT_CTL[SYSCTL_PERIHALT_CTL_EUA3] Bits */
\r
17209 #define SYSCTL_PERIHALT_CTL_EUA3_OFS ( 8) /* eUA3 Offset */
\r
17210 #define SYSCTL_PERIHALT_CTL_EUA3 (0x00000100) /* Freezes IP operation when CPU is halted */
\r
17211 /* SYSCTL_PERIHALT_CTL[SYSCTL_PERIHALT_CTL_EUB0] Bits */
\r
17212 #define SYSCTL_PERIHALT_CTL_EUB0_OFS ( 9) /* eUB0 Offset */
\r
17213 #define SYSCTL_PERIHALT_CTL_EUB0 (0x00000200) /* Freezes IP operation when CPU is halted */
\r
17214 /* SYSCTL_PERIHALT_CTL[SYSCTL_PERIHALT_CTL_EUB1] Bits */
\r
17215 #define SYSCTL_PERIHALT_CTL_EUB1_OFS (10) /* eUB1 Offset */
\r
17216 #define SYSCTL_PERIHALT_CTL_EUB1 (0x00000400) /* Freezes IP operation when CPU is halted */
\r
17217 /* SYSCTL_PERIHALT_CTL[SYSCTL_PERIHALT_CTL_EUB2] Bits */
\r
17218 #define SYSCTL_PERIHALT_CTL_EUB2_OFS (11) /* eUB2 Offset */
\r
17219 #define SYSCTL_PERIHALT_CTL_EUB2 (0x00000800) /* Freezes IP operation when CPU is halted */
\r
17220 /* SYSCTL_PERIHALT_CTL[SYSCTL_PERIHALT_CTL_EUB3] Bits */
\r
17221 #define SYSCTL_PERIHALT_CTL_EUB3_OFS (12) /* eUB3 Offset */
\r
17222 #define SYSCTL_PERIHALT_CTL_EUB3 (0x00001000) /* Freezes IP operation when CPU is halted */
\r
17223 /* SYSCTL_PERIHALT_CTL[SYSCTL_PERIHALT_CTL_ADC] Bits */
\r
17224 #define SYSCTL_PERIHALT_CTL_ADC_OFS (13) /* ADC Offset */
\r
17225 #define SYSCTL_PERIHALT_CTL_ADC (0x00002000) /* Freezes IP operation when CPU is halted */
\r
17226 /* SYSCTL_PERIHALT_CTL[SYSCTL_PERIHALT_CTL_WDT] Bits */
\r
17227 #define SYSCTL_PERIHALT_CTL_WDT_OFS (14) /* WDT Offset */
\r
17228 #define SYSCTL_PERIHALT_CTL_WDT (0x00004000) /* Freezes IP operation when CPU is halted */
\r
17229 /* SYSCTL_PERIHALT_CTL[SYSCTL_PERIHALT_CTL_DMA] Bits */
\r
17230 #define SYSCTL_PERIHALT_CTL_DMA_OFS (15) /* DMA Offset */
\r
17231 #define SYSCTL_PERIHALT_CTL_DMA (0x00008000) /* Freezes IP operation when CPU is halted */
\r
17232 /* SYSCTL_SRAM_BANKEN[SYSCTL_SRAM_BANKEN_BNK0_EN] Bits */
\r
17233 #define SYSCTL_SRAM_BANKEN_BNK0_EN_OFS ( 0) /* BNK0_EN Offset */
\r
17234 #define SYSCTL_SRAM_BANKEN_BNK0_EN (0x00000001) /* SRAM Bank0 enable */
\r
17235 /* SYSCTL_SRAM_BANKEN[SYSCTL_SRAM_BANKEN_BNK1_EN] Bits */
\r
17236 #define SYSCTL_SRAM_BANKEN_BNK1_EN_OFS ( 1) /* BNK1_EN Offset */
\r
17237 #define SYSCTL_SRAM_BANKEN_BNK1_EN (0x00000002) /* SRAM Bank1 enable */
\r
17238 /* SYSCTL_SRAM_BANKEN[SYSCTL_SRAM_BANKEN_BNK2_EN] Bits */
\r
17239 #define SYSCTL_SRAM_BANKEN_BNK2_EN_OFS ( 2) /* BNK2_EN Offset */
\r
17240 #define SYSCTL_SRAM_BANKEN_BNK2_EN (0x00000004) /* SRAM Bank1 enable */
\r
17241 /* SYSCTL_SRAM_BANKEN[SYSCTL_SRAM_BANKEN_BNK3_EN] Bits */
\r
17242 #define SYSCTL_SRAM_BANKEN_BNK3_EN_OFS ( 3) /* BNK3_EN Offset */
\r
17243 #define SYSCTL_SRAM_BANKEN_BNK3_EN (0x00000008) /* SRAM Bank1 enable */
\r
17244 /* SYSCTL_SRAM_BANKEN[SYSCTL_SRAM_BANKEN_BNK4_EN] Bits */
\r
17245 #define SYSCTL_SRAM_BANKEN_BNK4_EN_OFS ( 4) /* BNK4_EN Offset */
\r
17246 #define SYSCTL_SRAM_BANKEN_BNK4_EN (0x00000010) /* SRAM Bank1 enable */
\r
17247 /* SYSCTL_SRAM_BANKEN[SYSCTL_SRAM_BANKEN_BNK5_EN] Bits */
\r
17248 #define SYSCTL_SRAM_BANKEN_BNK5_EN_OFS ( 5) /* BNK5_EN Offset */
\r
17249 #define SYSCTL_SRAM_BANKEN_BNK5_EN (0x00000020) /* SRAM Bank1 enable */
\r
17250 /* SYSCTL_SRAM_BANKEN[SYSCTL_SRAM_BANKEN_BNK6_EN] Bits */
\r
17251 #define SYSCTL_SRAM_BANKEN_BNK6_EN_OFS ( 6) /* BNK6_EN Offset */
\r
17252 #define SYSCTL_SRAM_BANKEN_BNK6_EN (0x00000040) /* SRAM Bank1 enable */
\r
17253 /* SYSCTL_SRAM_BANKEN[SYSCTL_SRAM_BANKEN_BNK7_EN] Bits */
\r
17254 #define SYSCTL_SRAM_BANKEN_BNK7_EN_OFS ( 7) /* BNK7_EN Offset */
\r
17255 #define SYSCTL_SRAM_BANKEN_BNK7_EN (0x00000080) /* SRAM Bank1 enable */
\r
17256 /* SYSCTL_SRAM_BANKEN[SYSCTL_SRAM_BANKEN_SRAM_RDY] Bits */
\r
17257 #define SYSCTL_SRAM_BANKEN_SRAM_RDY_OFS (16) /* SRAM_RDY Offset */
\r
17258 #define SYSCTL_SRAM_BANKEN_SRAM_RDY (0x00010000) /* SRAM ready */
\r
17259 /* SYSCTL_SRAM_BANKRET[SYSCTL_SRAM_BANKRET_BNK0_RET] Bits */
\r
17260 #define SYSCTL_SRAM_BANKRET_BNK0_RET_OFS ( 0) /* BNK0_RET Offset */
\r
17261 #define SYSCTL_SRAM_BANKRET_BNK0_RET (0x00000001) /* Bank0 retention */
\r
17262 /* SYSCTL_SRAM_BANKRET[SYSCTL_SRAM_BANKRET_BNK1_RET] Bits */
\r
17263 #define SYSCTL_SRAM_BANKRET_BNK1_RET_OFS ( 1) /* BNK1_RET Offset */
\r
17264 #define SYSCTL_SRAM_BANKRET_BNK1_RET (0x00000002) /* Bank1 retention */
\r
17265 /* SYSCTL_SRAM_BANKRET[SYSCTL_SRAM_BANKRET_BNK2_RET] Bits */
\r
17266 #define SYSCTL_SRAM_BANKRET_BNK2_RET_OFS ( 2) /* BNK2_RET Offset */
\r
17267 #define SYSCTL_SRAM_BANKRET_BNK2_RET (0x00000004) /* Bank2 retention */
\r
17268 /* SYSCTL_SRAM_BANKRET[SYSCTL_SRAM_BANKRET_BNK3_RET] Bits */
\r
17269 #define SYSCTL_SRAM_BANKRET_BNK3_RET_OFS ( 3) /* BNK3_RET Offset */
\r
17270 #define SYSCTL_SRAM_BANKRET_BNK3_RET (0x00000008) /* Bank3 retention */
\r
17271 /* SYSCTL_SRAM_BANKRET[SYSCTL_SRAM_BANKRET_BNK4_RET] Bits */
\r
17272 #define SYSCTL_SRAM_BANKRET_BNK4_RET_OFS ( 4) /* BNK4_RET Offset */
\r
17273 #define SYSCTL_SRAM_BANKRET_BNK4_RET (0x00000010) /* Bank4 retention */
\r
17274 /* SYSCTL_SRAM_BANKRET[SYSCTL_SRAM_BANKRET_BNK5_RET] Bits */
\r
17275 #define SYSCTL_SRAM_BANKRET_BNK5_RET_OFS ( 5) /* BNK5_RET Offset */
\r
17276 #define SYSCTL_SRAM_BANKRET_BNK5_RET (0x00000020) /* Bank5 retention */
\r
17277 /* SYSCTL_SRAM_BANKRET[SYSCTL_SRAM_BANKRET_BNK6_RET] Bits */
\r
17278 #define SYSCTL_SRAM_BANKRET_BNK6_RET_OFS ( 6) /* BNK6_RET Offset */
\r
17279 #define SYSCTL_SRAM_BANKRET_BNK6_RET (0x00000040) /* Bank6 retention */
\r
17280 /* SYSCTL_SRAM_BANKRET[SYSCTL_SRAM_BANKRET_BNK7_RET] Bits */
\r
17281 #define SYSCTL_SRAM_BANKRET_BNK7_RET_OFS ( 7) /* BNK7_RET Offset */
\r
17282 #define SYSCTL_SRAM_BANKRET_BNK7_RET (0x00000080) /* Bank7 retention */
\r
17283 /* SYSCTL_SRAM_BANKRET[SYSCTL_SRAM_BANKRET_SRAM_RDY] Bits */
\r
17284 #define SYSCTL_SRAM_BANKRET_SRAM_RDY_OFS (16) /* SRAM_RDY Offset */
\r
17285 #define SYSCTL_SRAM_BANKRET_SRAM_RDY (0x00010000) /* SRAM ready */
\r
17286 /* SYSCTL_DIO_GLTFLT_CTL[SYSCTL_DIO_GLTFLT_CTL_GLTCH_EN] Bits */
\r
17287 #define SYSCTL_DIO_GLTFLT_CTL_GLTCH_EN_OFS ( 0) /* GLTCH_EN Offset */
\r
17288 #define SYSCTL_DIO_GLTFLT_CTL_GLTCH_EN (0x00000001) /* Glitch filter enable */
\r
17289 /* SYSCTL_SECDATA_UNLOCK[SYSCTL_SECDATA_UNLOCK_UNLKEY] Bits */
\r
17290 #define SYSCTL_SECDATA_UNLOCK_UNLKEY_OFS ( 0) /* UNLKEY Offset */
\r
17291 #define SYSCTL_SECDATA_UNLOCK_UNLKEY_M (0x0000ffff) /* Unlock key */
\r
17292 /* SYSCTL_MASTER_UNLOCK[SYSCTL_MASTER_UNLOCK_UNLKEY] Bits */
\r
17293 #define SYSCTL_MASTER_UNLOCK_UNLKEY_OFS ( 0) /* UNLKEY Offset */
\r
17294 #define SYSCTL_MASTER_UNLOCK_UNLKEY_M (0x0000ffff) /* Unlock Key */
\r
17295 /* SYSCTL_RESET_REQ[SYSCTL_RESET_REQ_POR] Bits */
\r
17296 #define SYSCTL_RESET_REQ_POR_OFS ( 0) /* POR Offset */
\r
17297 #define SYSCTL_RESET_REQ_POR (0x00000001) /* Generate POR */
\r
17298 /* SYSCTL_RESET_REQ[SYSCTL_RESET_REQ_REBOOT] Bits */
\r
17299 #define SYSCTL_RESET_REQ_REBOOT_OFS ( 1) /* REBOOT Offset */
\r
17300 #define SYSCTL_RESET_REQ_REBOOT (0x00000002) /* Generate Reboot_Reset */
\r
17301 /* SYSCTL_RESET_REQ[SYSCTL_RESET_REQ_WKEY] Bits */
\r
17302 #define SYSCTL_RESET_REQ_WKEY_OFS ( 8) /* WKEY Offset */
\r
17303 #define SYSCTL_RESET_REQ_WKEY_M (0x0000ff00) /* Write key */
\r
17304 /* SYSCTL_RESET_STATOVER[SYSCTL_RESET_STATOVER_SOFT] Bits */
\r
17305 #define SYSCTL_RESET_STATOVER_SOFT_OFS ( 0) /* SOFT Offset */
\r
17306 #define SYSCTL_RESET_STATOVER_SOFT (0x00000001) /* Indicates if SOFT Reset is active */
\r
17307 /* SYSCTL_RESET_STATOVER[SYSCTL_RESET_STATOVER_HARD] Bits */
\r
17308 #define SYSCTL_RESET_STATOVER_HARD_OFS ( 1) /* HARD Offset */
\r
17309 #define SYSCTL_RESET_STATOVER_HARD (0x00000002) /* Indicates if HARD Reset is active */
\r
17310 /* SYSCTL_RESET_STATOVER[SYSCTL_RESET_STATOVER_REBOOT] Bits */
\r
17311 #define SYSCTL_RESET_STATOVER_REBOOT_OFS ( 2) /* REBOOT Offset */
\r
17312 #define SYSCTL_RESET_STATOVER_REBOOT (0x00000004) /* Indicates if Reboot Reset is active */
\r
17313 /* SYSCTL_RESET_STATOVER[SYSCTL_RESET_STATOVER_SOFT_OVER] Bits */
\r
17314 #define SYSCTL_RESET_STATOVER_SOFT_OVER_OFS ( 8) /* SOFT_OVER Offset */
\r
17315 #define SYSCTL_RESET_STATOVER_SOFT_OVER (0x00000100) /* SOFT_Reset overwrite request */
\r
17316 /* SYSCTL_RESET_STATOVER[SYSCTL_RESET_STATOVER_HARD_OVER] Bits */
\r
17317 #define SYSCTL_RESET_STATOVER_HARD_OVER_OFS ( 9) /* HARD_OVER Offset */
\r
17318 #define SYSCTL_RESET_STATOVER_HARD_OVER (0x00000200) /* HARD_Reset overwrite request */
\r
17319 /* SYSCTL_RESET_STATOVER[SYSCTL_RESET_STATOVER_RBT_OVER] Bits */
\r
17320 #define SYSCTL_RESET_STATOVER_RBT_OVER_OFS (10) /* RBT_OVER Offset */
\r
17321 #define SYSCTL_RESET_STATOVER_RBT_OVER (0x00000400) /* Reboot Reset overwrite request */
\r
17322 /* SYSCTL_SYSTEM_STAT[SYSCTL_SYSTEM_STAT_DBG_SEC_ACT] Bits */
\r
17323 #define SYSCTL_SYSTEM_STAT_DBG_SEC_ACT_OFS ( 3) /* DBG_SEC_ACT Offset */
\r
17324 #define SYSCTL_SYSTEM_STAT_DBG_SEC_ACT (0x00000008) /* Debug Security active */
\r
17325 /* SYSCTL_SYSTEM_STAT[SYSCTL_SYSTEM_STAT_JTAG_SWD_LOCK_ACT] Bits */
\r
17326 #define SYSCTL_SYSTEM_STAT_JTAG_SWD_LOCK_ACT_OFS ( 4) /* JTAG_SWD_LOCK_ACT Offset */
\r
17327 #define SYSCTL_SYSTEM_STAT_JTAG_SWD_LOCK_ACT (0x00000010) /* Indicates if JTAG and SWD Lock is active */
\r
17328 /* SYSCTL_SYSTEM_STAT[SYSCTL_SYSTEM_STAT_IP_PROT_ACT] Bits */
\r
17329 #define SYSCTL_SYSTEM_STAT_IP_PROT_ACT_OFS ( 5) /* IP_PROT_ACT Offset */
\r
17330 #define SYSCTL_SYSTEM_STAT_IP_PROT_ACT (0x00000020) /* Indicates if IP protection is active */
\r
17332 /* Pre-defined bitfield values */
\r
17333 #define SYSCTL_REBOOT_CTL_WKEY_VAL (0x00006900) /* Key value to enable writes to bit 0 */
\r
17336 //*****************************************************************************
\r
17338 //*****************************************************************************
\r
17339 /* SYSTICK_STCSR[SYSTICK_STCSR_ENABLE] Bits */
\r
17340 #define SYSTICK_STCSR_ENABLE_OFS ( 0) /* ENABLE Offset */
\r
17341 #define SYSTICK_STCSR_ENABLE (0x00000001) /* */
\r
17342 /* SYSTICK_STCSR[SYSTICK_STCSR_TICKINT] Bits */
\r
17343 #define SYSTICK_STCSR_TICKINT_OFS ( 1) /* TICKINT Offset */
\r
17344 #define SYSTICK_STCSR_TICKINT (0x00000002) /* */
\r
17345 /* SYSTICK_STCSR[SYSTICK_STCSR_CLKSOURCE] Bits */
\r
17346 #define SYSTICK_STCSR_CLKSOURCE_OFS ( 2) /* CLKSOURCE Offset */
\r
17347 #define SYSTICK_STCSR_CLKSOURCE (0x00000004) /* */
\r
17348 /* SYSTICK_STCSR[SYSTICK_STCSR_COUNTFLAG] Bits */
\r
17349 #define SYSTICK_STCSR_COUNTFLAG_OFS (16) /* COUNTFLAG Offset */
\r
17350 #define SYSTICK_STCSR_COUNTFLAG (0x00010000) /* */
\r
17351 /* SYSTICK_STRVR[SYSTICK_STRVR_RELOAD] Bits */
\r
17352 #define SYSTICK_STRVR_RELOAD_OFS ( 0) /* RELOAD Offset */
\r
17353 #define SYSTICK_STRVR_RELOAD_M (0x00ffffff) /* */
\r
17354 /* SYSTICK_STCVR[SYSTICK_STCVR_CURRENT] Bits */
\r
17355 #define SYSTICK_STCVR_CURRENT_OFS ( 0) /* CURRENT Offset */
\r
17356 #define SYSTICK_STCVR_CURRENT_M (0x00ffffff) /* */
\r
17357 /* SYSTICK_STCR[SYSTICK_STCR_TENMS] Bits */
\r
17358 #define SYSTICK_STCR_TENMS_OFS ( 0) /* TENMS Offset */
\r
17359 #define SYSTICK_STCR_TENMS_M (0x00ffffff) /* */
\r
17360 /* SYSTICK_STCR[SYSTICK_STCR_SKEW] Bits */
\r
17361 #define SYSTICK_STCR_SKEW_OFS (30) /* SKEW Offset */
\r
17362 #define SYSTICK_STCR_SKEW (0x40000000) /* */
\r
17363 /* SYSTICK_STCR[SYSTICK_STCR_NOREF] Bits */
\r
17364 #define SYSTICK_STCR_NOREF_OFS (31) /* NOREF Offset */
\r
17365 #define SYSTICK_STCR_NOREF (0x80000000) /* */
\r
17368 //*****************************************************************************
\r
17370 //*****************************************************************************
\r
17371 /* TIMER32_CONTROL1[TIMER32_CONTROL1_ONESHOT] Bits */
\r
17372 #define TIMER32_CONTROL1_ONESHOT_OFS ( 0) /* ONESHOT Offset */
\r
17373 #define TIMER32_CONTROL1_ONESHOT (0x00000001) /* Selects one-shot or wrapping counter mode */
\r
17374 /* TIMER32_CONTROL1[TIMER32_CONTROL1_SIZE] Bits */
\r
17375 #define TIMER32_CONTROL1_SIZE_OFS ( 1) /* SIZE Offset */
\r
17376 #define TIMER32_CONTROL1_SIZE (0x00000002) /* Selects 16 or 32 bit counter operation */
\r
17377 /* TIMER32_CONTROL1[TIMER32_CONTROL1_PRESCALE] Bits */
\r
17378 #define TIMER32_CONTROL1_PRESCALE_OFS ( 2) /* PRESCALE Offset */
\r
17379 #define TIMER32_CONTROL1_PRESCALE_M (0x0000000c) /* Prescale bits */
\r
17380 #define TIMER32_CONTROL1_PRESCALE0 (0x00000004) /* Prescale bits */
\r
17381 #define TIMER32_CONTROL1_PRESCALE1 (0x00000008) /* Prescale bits */
\r
17382 #define TIMER32_CONTROL1_PRESCALE_0 (0x00000000) /* 0 stages of prescale, clock is divided by 1 */
\r
17383 #define TIMER32_CONTROL1_PRESCALE_1 (0x00000004) /* 4 stages of prescale, clock is divided by 16 */
\r
17384 #define TIMER32_CONTROL1_PRESCALE_2 (0x00000008) /* 8 stages of prescale, clock is divided by 256 */
\r
17385 /* TIMER32_CONTROL1[TIMER32_CONTROL1_IE] Bits */
\r
17386 #define TIMER32_CONTROL1_IE_OFS ( 5) /* IE Offset */
\r
17387 #define TIMER32_CONTROL1_IE (0x00000020) /* Interrupt enable bit */
\r
17388 /* TIMER32_CONTROL1[TIMER32_CONTROL1_MODE] Bits */
\r
17389 #define TIMER32_CONTROL1_MODE_OFS ( 6) /* MODE Offset */
\r
17390 #define TIMER32_CONTROL1_MODE (0x00000040) /* Mode bit */
\r
17391 /* TIMER32_CONTROL1[TIMER32_CONTROL1_ENABLE] Bits */
\r
17392 #define TIMER32_CONTROL1_ENABLE_OFS ( 7) /* ENABLE Offset */
\r
17393 #define TIMER32_CONTROL1_ENABLE (0x00000080) /* */
\r
17394 /* TIMER32_RIS1[TIMER32_RIS1_RAW_IFG] Bits */
\r
17395 #define TIMER32_RIS1_RAW_IFG_OFS ( 0) /* RAW_IFG Offset */
\r
17396 #define TIMER32_RIS1_RAW_IFG (0x00000001) /* Raw interrupt status */
\r
17397 /* TIMER32_MIS1[TIMER32_MIS1_] Bits */
\r
17398 #define TIMER32_MIS1__OFS ( 0) /* IFG Offset */
\r
17399 #define TIMER32_MIS1_ (0x00000001) /* Enabled interrupt status */
\r
17400 /* TIMER32_CONTROL2[TIMER32_CONTROL2_ONESHOT] Bits */
\r
17401 #define TIMER32_CONTROL2_ONESHOT_OFS ( 0) /* ONESHOT Offset */
\r
17402 #define TIMER32_CONTROL2_ONESHOT (0x00000001) /* Selects one-shot or wrapping counter mode */
\r
17403 /* TIMER32_CONTROL2[TIMER32_CONTROL2_SIZE] Bits */
\r
17404 #define TIMER32_CONTROL2_SIZE_OFS ( 1) /* SIZE Offset */
\r
17405 #define TIMER32_CONTROL2_SIZE (0x00000002) /* Selects 16 or 32 bit counter operation */
\r
17406 /* TIMER32_CONTROL2[TIMER32_CONTROL2_PRESCALE] Bits */
\r
17407 #define TIMER32_CONTROL2_PRESCALE_OFS ( 2) /* PRESCALE Offset */
\r
17408 #define TIMER32_CONTROL2_PRESCALE_M (0x0000000c) /* Prescale bits */
\r
17409 #define TIMER32_CONTROL2_PRESCALE0 (0x00000004) /* Prescale bits */
\r
17410 #define TIMER32_CONTROL2_PRESCALE1 (0x00000008) /* Prescale bits */
\r
17411 #define TIMER32_CONTROL2_PRESCALE_0 (0x00000000) /* 0 stages of prescale, clock is divided by 1 */
\r
17412 #define TIMER32_CONTROL2_PRESCALE_1 (0x00000004) /* 4 stages of prescale, clock is divided by 16 */
\r
17413 #define TIMER32_CONTROL2_PRESCALE_2 (0x00000008) /* 8 stages of prescale, clock is divided by 256 */
\r
17414 /* TIMER32_CONTROL2[TIMER32_CONTROL2_IE] Bits */
\r
17415 #define TIMER32_CONTROL2_IE_OFS ( 5) /* IE Offset */
\r
17416 #define TIMER32_CONTROL2_IE (0x00000020) /* Interrupt enable bit */
\r
17417 /* TIMER32_CONTROL2[TIMER32_CONTROL2_MODE] Bits */
\r
17418 #define TIMER32_CONTROL2_MODE_OFS ( 6) /* MODE Offset */
\r
17419 #define TIMER32_CONTROL2_MODE (0x00000040) /* Mode bit */
\r
17420 /* TIMER32_CONTROL2[TIMER32_CONTROL2_ENABLE] Bits */
\r
17421 #define TIMER32_CONTROL2_ENABLE_OFS ( 7) /* ENABLE Offset */
\r
17422 #define TIMER32_CONTROL2_ENABLE (0x00000080) /* */
\r
17423 /* TIMER32_RIS2[TIMER32_RIS2_RAW_IFG] Bits */
\r
17424 #define TIMER32_RIS2_RAW_IFG_OFS ( 0) /* RAW_IFG Offset */
\r
17425 #define TIMER32_RIS2_RAW_IFG (0x00000001) /* Raw interrupt status */
\r
17426 /* TIMER32_MIS2[TIMER32_MIS2_IFG] Bits */
\r
17427 #define TIMER32_MIS2_IFG_OFS ( 0) /* IFG Offset */
\r
17428 #define TIMER32_MIS2_IFG (0x00000001) /* Enabled interrupt status */
\r
17431 //*****************************************************************************
\r
17433 //*****************************************************************************
\r
17434 /* TA0CTL[TAIFG] Bits */
\r
17435 #define TAIFG_OFS ( 0) /* TAIFG Offset */
\r
17436 #define TAIFG (0x0001) /* TimerA interrupt flag */
\r
17437 /* TA0CTL[TAIE] Bits */
\r
17438 #define TAIE_OFS ( 1) /* TAIE Offset */
\r
17439 #define TAIE (0x0002) /* TimerA interrupt enable */
\r
17440 /* TA0CTL[TACLR] Bits */
\r
17441 #define TACLR_OFS ( 2) /* TACLR Offset */
\r
17442 #define TACLR (0x0004) /* TimerA clear */
\r
17443 /* TA0CTL[MC] Bits */
\r
17444 #define MC_OFS ( 4) /* MC Offset */
\r
17445 #define MC_M (0x0030) /* Mode control */
\r
17446 #define MC0 (0x0010) /* Mode control */
\r
17447 #define MC1 (0x0020) /* Mode control */
\r
17448 #define MC_0 (0x0000) /* Stop mode: Timer is halted */
\r
17449 #define MC_1 (0x0010) /* Up mode: Timer counts up to TAxCCR0 */
\r
17450 #define MC_2 (0x0020) /* Continuous mode: Timer counts up to 0FFFFh */
\r
17451 #define MC_3 (0x0030) /* Up/down mode: Timer counts up to TAxCCR0 then down to 0000h */
\r
17452 #define MC__STOP (0x0000) /* Stop mode: Timer is halted */
\r
17453 #define MC__UP (0x0010) /* Up mode: Timer counts up to TAxCCR0 */
\r
17454 #define MC__CONTINUOUS (0x0020) /* Continuous mode: Timer counts up to 0FFFFh */
\r
17455 #define MC__UPDOWN (0x0030) /* Up/down mode: Timer counts up to TAxCCR0 then down to 0000h */
\r
17456 /* TA0CTL[ID] Bits */
\r
17457 #define ID_OFS ( 6) /* ID Offset */
\r
17458 #define ID_M (0x00c0) /* Input divider */
\r
17459 #define ID0 (0x0040) /* Input divider */
\r
17460 #define ID1 (0x0080) /* Input divider */
\r
17461 #define ID_0 (0x0000) /* /1 */
\r
17462 #define ID_1 (0x0040) /* /2 */
\r
17463 #define ID_2 (0x0080) /* /4 */
\r
17464 #define ID_3 (0x00c0) /* /8 */
\r
17465 #define ID__1 (0x0000) /* /1 */
\r
17466 #define ID__2 (0x0040) /* /2 */
\r
17467 #define ID__4 (0x0080) /* /4 */
\r
17468 #define ID__8 (0x00c0) /* /8 */
\r
17469 /* TA0CTL[TASSEL] Bits */
\r
17470 #define TASSEL_OFS ( 8) /* TASSEL Offset */
\r
17471 #define TASSEL_M (0x0300) /* TimerA clock source select */
\r
17472 #define TASSEL0 (0x0100) /* TimerA clock source select */
\r
17473 #define TASSEL1 (0x0200) /* TimerA clock source select */
\r
17474 #define TASSEL_0 (0x0000) /* TAxCLK */
\r
17475 #define TASSEL_1 (0x0100) /* ACLK */
\r
17476 #define TASSEL_2 (0x0200) /* SMCLK */
\r
17477 #define TASSEL_3 (0x0300) /* INCLK */
\r
17478 #define TASSEL__TACLK (0x0000) /* TAxCLK */
\r
17479 #define TASSEL__ACLK (0x0100) /* ACLK */
\r
17480 #define TASSEL__SMCLK (0x0200) /* SMCLK */
\r
17481 #define TASSEL__INCLK (0x0300) /* INCLK */
\r
17482 /* TA0CCTL[CCIFG] Bits */
\r
17483 #define CCIFG_OFS ( 0) /* CCIFG Offset */
\r
17484 #define CCIFG (0x0001) /* Capture/compare interrupt flag */
\r
17485 /* TA0CCTL[COV] Bits */
\r
17486 #define COV_OFS ( 1) /* COV Offset */
\r
17487 #define COV (0x0002) /* Capture overflow */
\r
17488 /* TA0CCTL[OUT] Bits */
\r
17489 #define OUT_OFS ( 2) /* OUT Offset */
\r
17490 #define OUT (0x0004) /* Output */
\r
17491 /* TA0CCTL[CCI] Bits */
\r
17492 #define CCI_OFS ( 3) /* CCI Offset */
\r
17493 #define CCI (0x0008) /* Capture/compare input */
\r
17494 /* TA0CCTL[CCIE] Bits */
\r
17495 #define CCIE_OFS ( 4) /* CCIE Offset */
\r
17496 #define CCIE (0x0010) /* Capture/compare interrupt enable */
\r
17497 /* TA0CCTL[OUTMOD] Bits */
\r
17498 #define OUTMOD_OFS ( 5) /* OUTMOD Offset */
\r
17499 #define OUTMOD_M (0x00e0) /* Output mode */
\r
17500 #define OUTMOD0 (0x0020) /* Output mode */
\r
17501 #define OUTMOD1 (0x0040) /* Output mode */
\r
17502 #define OUTMOD2 (0x0080) /* Output mode */
\r
17503 #define OUTMOD_0 (0x0000) /* OUT bit value */
\r
17504 #define OUTMOD_1 (0x0020) /* Set */
\r
17505 #define OUTMOD_2 (0x0040) /* Toggle/reset */
\r
17506 #define OUTMOD_3 (0x0060) /* Set/reset */
\r
17507 #define OUTMOD_4 (0x0080) /* Toggle */
\r
17508 #define OUTMOD_5 (0x00a0) /* Reset */
\r
17509 #define OUTMOD_6 (0x00c0) /* Toggle/set */
\r
17510 #define OUTMOD_7 (0x00e0) /* Reset/set */
\r
17511 /* TA0CCTL[CAP] Bits */
\r
17512 #define CAP_OFS ( 8) /* CAP Offset */
\r
17513 #define CAP (0x0100) /* Capture mode */
\r
17514 /* TA0CCTL[SCCI] Bits */
\r
17515 #define SCCI_OFS (10) /* SCCI Offset */
\r
17516 #define SCCI (0x0400) /* Synchronized capture/compare input */
\r
17517 /* TA0CCTL[SCS] Bits */
\r
17518 #define SCS_OFS (11) /* SCS Offset */
\r
17519 #define SCS (0x0800) /* Synchronize capture source */
\r
17520 /* TA0CCTL[CCIS] Bits */
\r
17521 #define CCIS_OFS (12) /* CCIS Offset */
\r
17522 #define CCIS_M (0x3000) /* Capture/compare input select */
\r
17523 #define CCIS0 (0x1000) /* Capture/compare input select */
\r
17524 #define CCIS1 (0x2000) /* Capture/compare input select */
\r
17525 #define CCIS_0 (0x0000) /* CCIxA */
\r
17526 #define CCIS_1 (0x1000) /* CCIxB */
\r
17527 #define CCIS_2 (0x2000) /* GND */
\r
17528 #define CCIS_3 (0x3000) /* VCC */
\r
17529 #define CCIS__CCIA (0x0000) /* CCIxA */
\r
17530 #define CCIS__CCIB (0x1000) /* CCIxB */
\r
17531 #define CCIS__GND (0x2000) /* GND */
\r
17532 #define CCIS__VCC (0x3000) /* VCC */
\r
17533 /* TA0CCTL[CM] Bits */
\r
17534 #define CM_OFS (14) /* CM Offset */
\r
17535 #define CM_M (0xc000) /* Capture mode */
\r
17536 #define CM0 (0x4000) /* Capture mode */
\r
17537 #define CM1 (0x8000) /* Capture mode */
\r
17538 #define CM_0 (0x0000) /* No capture */
\r
17539 #define CM_1 (0x4000) /* Capture on rising edge */
\r
17540 #define CM_2 (0x8000) /* Capture on falling edge */
\r
17541 #define CM_3 (0xc000) /* Capture on both rising and falling edges */
\r
17542 #define CM__NONE (0x0000) /* No capture */
\r
17543 #define CM__RISING (0x4000) /* Capture on rising edge */
\r
17544 #define CM__FALLING (0x8000) /* Capture on falling edge */
\r
17545 #define CM__BOTH (0xc000) /* Capture on both rising and falling edges */
\r
17546 /* TA0EX0[TAIDEX] Bits */
\r
17547 #define TAIDEX_OFS ( 0) /* TAIDEX Offset */
\r
17548 #define TAIDEX_M (0x0007) /* Input divider expansion */
\r
17549 #define TAIDEX0 (0x0001) /* Input divider expansion */
\r
17550 #define TAIDEX1 (0x0002) /* Input divider expansion */
\r
17551 #define TAIDEX2 (0x0004) /* Input divider expansion */
\r
17552 #define TAIDEX_0 (0x0000) /* Divide by 1 */
\r
17553 #define TAIDEX_1 (0x0001) /* Divide by 2 */
\r
17554 #define TAIDEX_2 (0x0002) /* Divide by 3 */
\r
17555 #define TAIDEX_3 (0x0003) /* Divide by 4 */
\r
17556 #define TAIDEX_4 (0x0004) /* Divide by 5 */
\r
17557 #define TAIDEX_5 (0x0005) /* Divide by 6 */
\r
17558 #define TAIDEX_6 (0x0006) /* Divide by 7 */
\r
17559 #define TAIDEX_7 (0x0007) /* Divide by 8 */
\r
17560 #define TAIDEX__1 (0x0000) /* Divide by 1 */
\r
17561 #define TAIDEX__2 (0x0001) /* Divide by 2 */
\r
17562 #define TAIDEX__3 (0x0002) /* Divide by 3 */
\r
17563 #define TAIDEX__4 (0x0003) /* Divide by 4 */
\r
17564 #define TAIDEX__5 (0x0004) /* Divide by 5 */
\r
17565 #define TAIDEX__6 (0x0005) /* Divide by 6 */
\r
17566 #define TAIDEX__7 (0x0006) /* Divide by 7 */
\r
17567 #define TAIDEX__8 (0x0007) /* Divide by 8 */
\r
17570 //*****************************************************************************
\r
17572 //*****************************************************************************
\r
17573 /* TA1CTL[TAIFG] Bits */
\r
17574 //#define TAIFG_OFS ( 0) /* TAIFG Offset */
\r
17575 //#define TAIFG (0x0001) /* TimerA interrupt flag */
\r
17576 /* TA1CTL[TAIE] Bits */
\r
17577 //#define TAIE_OFS ( 1) /* TAIE Offset */
\r
17578 //#define TAIE (0x0002) /* TimerA interrupt enable */
\r
17579 /* TA1CTL[TACLR] Bits */
\r
17580 //#define TACLR_OFS ( 2) /* TACLR Offset */
\r
17581 //#define TACLR (0x0004) /* TimerA clear */
\r
17582 /* TA1CTL[MC] Bits */
\r
17583 //#define MC_OFS ( 4) /* MC Offset */
\r
17584 //#define MC_M (0x0030) /* Mode control */
\r
17585 //#define MC0 (0x0010) /* Mode control */
\r
17586 //#define MC1 (0x0020) /* Mode control */
\r
17587 //#define MC_0 (0x0000) /* Stop mode: Timer is halted */
\r
17588 //#define MC_1 (0x0010) /* Up mode: Timer counts up to TAxCCR0 */
\r
17589 //#define MC_2 (0x0020) /* Continuous mode: Timer counts up to 0FFFFh */
\r
17590 //#define MC_3 (0x0030) /* Up/down mode: Timer counts up to TAxCCR0 then down to 0000h */
\r
17591 //#define MC__STOP (0x0000) /* Stop mode: Timer is halted */
\r
17592 //#define MC__UP (0x0010) /* Up mode: Timer counts up to TAxCCR0 */
\r
17593 //#define MC__CONTINUOUS (0x0020) /* Continuous mode: Timer counts up to 0FFFFh */
\r
17594 //#define MC__UPDOWN (0x0030) /* Up/down mode: Timer counts up to TAxCCR0 then down to 0000h */
\r
17595 /* TA1CTL[ID] Bits */
\r
17596 //#define ID_OFS ( 6) /* ID Offset */
\r
17597 //#define ID_M (0x00c0) /* Input divider */
\r
17598 //#define ID0 (0x0040) /* Input divider */
\r
17599 //#define ID1 (0x0080) /* Input divider */
\r
17600 //#define ID_0 (0x0000) /* /1 */
\r
17601 //#define ID_1 (0x0040) /* /2 */
\r
17602 //#define ID_2 (0x0080) /* /4 */
\r
17603 //#define ID_3 (0x00c0) /* /8 */
\r
17604 //#define ID__1 (0x0000) /* /1 */
\r
17605 //#define ID__2 (0x0040) /* /2 */
\r
17606 //#define ID__4 (0x0080) /* /4 */
\r
17607 //#define ID__8 (0x00c0) /* /8 */
\r
17608 /* TA1CTL[TASSEL] Bits */
\r
17609 //#define TASSEL_OFS ( 8) /* TASSEL Offset */
\r
17610 //#define TASSEL_M (0x0300) /* TimerA clock source select */
\r
17611 //#define TASSEL0 (0x0100) /* TimerA clock source select */
\r
17612 //#define TASSEL1 (0x0200) /* TimerA clock source select */
\r
17613 //#define TASSEL_0 (0x0000) /* TAxCLK */
\r
17614 //#define TASSEL_1 (0x0100) /* ACLK */
\r
17615 //#define TASSEL_2 (0x0200) /* SMCLK */
\r
17616 //#define TASSEL_3 (0x0300) /* INCLK */
\r
17617 //#define TASSEL__TACLK (0x0000) /* TAxCLK */
\r
17618 //#define TASSEL__ACLK (0x0100) /* ACLK */
\r
17619 //#define TASSEL__SMCLK (0x0200) /* SMCLK */
\r
17620 //#define TASSEL__INCLK (0x0300) /* INCLK */
\r
17621 /* TA1CCTL[CCIFG] Bits */
\r
17622 //#define CCIFG_OFS ( 0) /* CCIFG Offset */
\r
17623 //#define CCIFG (0x0001) /* Capture/compare interrupt flag */
\r
17624 /* TA1CCTL[COV] Bits */
\r
17625 //#define COV_OFS ( 1) /* COV Offset */
\r
17626 //#define COV (0x0002) /* Capture overflow */
\r
17627 /* TA1CCTL[OUT] Bits */
\r
17628 //#define OUT_OFS ( 2) /* OUT Offset */
\r
17629 //#define OUT (0x0004) /* Output */
\r
17630 /* TA1CCTL[CCI] Bits */
\r
17631 //#define CCI_OFS ( 3) /* CCI Offset */
\r
17632 //#define CCI (0x0008) /* Capture/compare input */
\r
17633 /* TA1CCTL[CCIE] Bits */
\r
17634 //#define CCIE_OFS ( 4) /* CCIE Offset */
\r
17635 //#define CCIE (0x0010) /* Capture/compare interrupt enable */
\r
17636 /* TA1CCTL[OUTMOD] Bits */
\r
17637 //#define OUTMOD_OFS ( 5) /* OUTMOD Offset */
\r
17638 //#define OUTMOD_M (0x00e0) /* Output mode */
\r
17639 //#define OUTMOD0 (0x0020) /* Output mode */
\r
17640 //#define OUTMOD1 (0x0040) /* Output mode */
\r
17641 //#define OUTMOD2 (0x0080) /* Output mode */
\r
17642 //#define OUTMOD_0 (0x0000) /* OUT bit value */
\r
17643 //#define OUTMOD_1 (0x0020) /* Set */
\r
17644 //#define OUTMOD_2 (0x0040) /* Toggle/reset */
\r
17645 //#define OUTMOD_3 (0x0060) /* Set/reset */
\r
17646 //#define OUTMOD_4 (0x0080) /* Toggle */
\r
17647 //#define OUTMOD_5 (0x00a0) /* Reset */
\r
17648 //#define OUTMOD_6 (0x00c0) /* Toggle/set */
\r
17649 //#define OUTMOD_7 (0x00e0) /* Reset/set */
\r
17650 /* TA1CCTL[CAP] Bits */
\r
17651 //#define CAP_OFS ( 8) /* CAP Offset */
\r
17652 //#define CAP (0x0100) /* Capture mode */
\r
17653 /* TA1CCTL[SCCI] Bits */
\r
17654 //#define SCCI_OFS (10) /* SCCI Offset */
\r
17655 //#define SCCI (0x0400) /* Synchronized capture/compare input */
\r
17656 /* TA1CCTL[SCS] Bits */
\r
17657 //#define SCS_OFS (11) /* SCS Offset */
\r
17658 //#define SCS (0x0800) /* Synchronize capture source */
\r
17659 /* TA1CCTL[CCIS] Bits */
\r
17660 //#define CCIS_OFS (12) /* CCIS Offset */
\r
17661 //#define CCIS_M (0x3000) /* Capture/compare input select */
\r
17662 //#define CCIS0 (0x1000) /* Capture/compare input select */
\r
17663 //#define CCIS1 (0x2000) /* Capture/compare input select */
\r
17664 //#define CCIS_0 (0x0000) /* CCIxA */
\r
17665 //#define CCIS_1 (0x1000) /* CCIxB */
\r
17666 //#define CCIS_2 (0x2000) /* GND */
\r
17667 //#define CCIS_3 (0x3000) /* VCC */
\r
17668 //#define CCIS__CCIA (0x0000) /* CCIxA */
\r
17669 //#define CCIS__CCIB (0x1000) /* CCIxB */
\r
17670 //#define CCIS__GND (0x2000) /* GND */
\r
17671 //#define CCIS__VCC (0x3000) /* VCC */
\r
17672 /* TA1CCTL[CM] Bits */
\r
17673 //#define CM_OFS (14) /* CM Offset */
\r
17674 //#define CM_M (0xc000) /* Capture mode */
\r
17675 //#define CM0 (0x4000) /* Capture mode */
\r
17676 //#define CM1 (0x8000) /* Capture mode */
\r
17677 //#define CM_0 (0x0000) /* No capture */
\r
17678 //#define CM_1 (0x4000) /* Capture on rising edge */
\r
17679 //#define CM_2 (0x8000) /* Capture on falling edge */
\r
17680 //#define CM_3 (0xc000) /* Capture on both rising and falling edges */
\r
17681 //#define CM__NONE (0x0000) /* No capture */
\r
17682 //#define CM__RISING (0x4000) /* Capture on rising edge */
\r
17683 //#define CM__FALLING (0x8000) /* Capture on falling edge */
\r
17684 //#define CM__BOTH (0xc000) /* Capture on both rising and falling edges */
\r
17685 /* TA1EX0[TAIDEX] Bits */
\r
17686 //#define TAIDEX_OFS ( 0) /* TAIDEX Offset */
\r
17687 //#define TAIDEX_M (0x0007) /* Input divider expansion */
\r
17688 //#define TAIDEX0 (0x0001) /* Input divider expansion */
\r
17689 //#define TAIDEX1 (0x0002) /* Input divider expansion */
\r
17690 //#define TAIDEX2 (0x0004) /* Input divider expansion */
\r
17691 //#define TAIDEX_0 (0x0000) /* Divide by 1 */
\r
17692 //#define TAIDEX_1 (0x0001) /* Divide by 2 */
\r
17693 //#define TAIDEX_2 (0x0002) /* Divide by 3 */
\r
17694 //#define TAIDEX_3 (0x0003) /* Divide by 4 */
\r
17695 //#define TAIDEX_4 (0x0004) /* Divide by 5 */
\r
17696 //#define TAIDEX_5 (0x0005) /* Divide by 6 */
\r
17697 //#define TAIDEX_6 (0x0006) /* Divide by 7 */
\r
17698 //#define TAIDEX_7 (0x0007) /* Divide by 8 */
\r
17699 //#define TAIDEX__1 (0x0000) /* Divide by 1 */
\r
17700 //#define TAIDEX__2 (0x0001) /* Divide by 2 */
\r
17701 //#define TAIDEX__3 (0x0002) /* Divide by 3 */
\r
17702 //#define TAIDEX__4 (0x0003) /* Divide by 4 */
\r
17703 //#define TAIDEX__5 (0x0004) /* Divide by 5 */
\r
17704 //#define TAIDEX__6 (0x0005) /* Divide by 6 */
\r
17705 //#define TAIDEX__7 (0x0006) /* Divide by 7 */
\r
17706 //#define TAIDEX__8 (0x0007) /* Divide by 8 */
\r
17709 //*****************************************************************************
\r
17711 //*****************************************************************************
\r
17712 /* TA2CTL[TAIFG] Bits */
\r
17713 //#define TAIFG_OFS ( 0) /* TAIFG Offset */
\r
17714 //#define TAIFG (0x0001) /* TimerA interrupt flag */
\r
17715 /* TA2CTL[TAIE] Bits */
\r
17716 //#define TAIE_OFS ( 1) /* TAIE Offset */
\r
17717 //#define TAIE (0x0002) /* TimerA interrupt enable */
\r
17718 /* TA2CTL[TACLR] Bits */
\r
17719 //#define TACLR_OFS ( 2) /* TACLR Offset */
\r
17720 //#define TACLR (0x0004) /* TimerA clear */
\r
17721 /* TA2CTL[MC] Bits */
\r
17722 //#define MC_OFS ( 4) /* MC Offset */
\r
17723 //#define MC_M (0x0030) /* Mode control */
\r
17724 //#define MC0 (0x0010) /* Mode control */
\r
17725 //#define MC1 (0x0020) /* Mode control */
\r
17726 //#define MC_0 (0x0000) /* Stop mode: Timer is halted */
\r
17727 //#define MC_1 (0x0010) /* Up mode: Timer counts up to TAxCCR0 */
\r
17728 //#define MC_2 (0x0020) /* Continuous mode: Timer counts up to 0FFFFh */
\r
17729 //#define MC_3 (0x0030) /* Up/down mode: Timer counts up to TAxCCR0 then down to 0000h */
\r
17730 //#define MC__STOP (0x0000) /* Stop mode: Timer is halted */
\r
17731 //#define MC__UP (0x0010) /* Up mode: Timer counts up to TAxCCR0 */
\r
17732 //#define MC__CONTINUOUS (0x0020) /* Continuous mode: Timer counts up to 0FFFFh */
\r
17733 //#define MC__UPDOWN (0x0030) /* Up/down mode: Timer counts up to TAxCCR0 then down to 0000h */
\r
17734 /* TA2CTL[ID] Bits */
\r
17735 //#define ID_OFS ( 6) /* ID Offset */
\r
17736 //#define ID_M (0x00c0) /* Input divider */
\r
17737 //#define ID0 (0x0040) /* Input divider */
\r
17738 //#define ID1 (0x0080) /* Input divider */
\r
17739 //#define ID_0 (0x0000) /* /1 */
\r
17740 //#define ID_1 (0x0040) /* /2 */
\r
17741 //#define ID_2 (0x0080) /* /4 */
\r
17742 //#define ID_3 (0x00c0) /* /8 */
\r
17743 //#define ID__1 (0x0000) /* /1 */
\r
17744 //#define ID__2 (0x0040) /* /2 */
\r
17745 //#define ID__4 (0x0080) /* /4 */
\r
17746 //#define ID__8 (0x00c0) /* /8 */
\r
17747 /* TA2CTL[TASSEL] Bits */
\r
17748 //#define TASSEL_OFS ( 8) /* TASSEL Offset */
\r
17749 //#define TASSEL_M (0x0300) /* TimerA clock source select */
\r
17750 //#define TASSEL0 (0x0100) /* TimerA clock source select */
\r
17751 //#define TASSEL1 (0x0200) /* TimerA clock source select */
\r
17752 //#define TASSEL_0 (0x0000) /* TAxCLK */
\r
17753 //#define TASSEL_1 (0x0100) /* ACLK */
\r
17754 //#define TASSEL_2 (0x0200) /* SMCLK */
\r
17755 //#define TASSEL_3 (0x0300) /* INCLK */
\r
17756 //#define TASSEL__TACLK (0x0000) /* TAxCLK */
\r
17757 //#define TASSEL__ACLK (0x0100) /* ACLK */
\r
17758 //#define TASSEL__SMCLK (0x0200) /* SMCLK */
\r
17759 //#define TASSEL__INCLK (0x0300) /* INCLK */
\r
17760 /* TA2CCTL[CCIFG] Bits */
\r
17761 //#define CCIFG_OFS ( 0) /* CCIFG Offset */
\r
17762 //#define CCIFG (0x0001) /* Capture/compare interrupt flag */
\r
17763 /* TA2CCTL[COV] Bits */
\r
17764 //#define COV_OFS ( 1) /* COV Offset */
\r
17765 //#define COV (0x0002) /* Capture overflow */
\r
17766 /* TA2CCTL[OUT] Bits */
\r
17767 //#define OUT_OFS ( 2) /* OUT Offset */
\r
17768 //#define OUT (0x0004) /* Output */
\r
17769 /* TA2CCTL[CCI] Bits */
\r
17770 //#define CCI_OFS ( 3) /* CCI Offset */
\r
17771 //#define CCI (0x0008) /* Capture/compare input */
\r
17772 /* TA2CCTL[CCIE] Bits */
\r
17773 //#define CCIE_OFS ( 4) /* CCIE Offset */
\r
17774 //#define CCIE (0x0010) /* Capture/compare interrupt enable */
\r
17775 /* TA2CCTL[OUTMOD] Bits */
\r
17776 //#define OUTMOD_OFS ( 5) /* OUTMOD Offset */
\r
17777 //#define OUTMOD_M (0x00e0) /* Output mode */
\r
17778 //#define OUTMOD0 (0x0020) /* Output mode */
\r
17779 //#define OUTMOD1 (0x0040) /* Output mode */
\r
17780 //#define OUTMOD2 (0x0080) /* Output mode */
\r
17781 //#define OUTMOD_0 (0x0000) /* OUT bit value */
\r
17782 //#define OUTMOD_1 (0x0020) /* Set */
\r
17783 //#define OUTMOD_2 (0x0040) /* Toggle/reset */
\r
17784 //#define OUTMOD_3 (0x0060) /* Set/reset */
\r
17785 //#define OUTMOD_4 (0x0080) /* Toggle */
\r
17786 //#define OUTMOD_5 (0x00a0) /* Reset */
\r
17787 //#define OUTMOD_6 (0x00c0) /* Toggle/set */
\r
17788 //#define OUTMOD_7 (0x00e0) /* Reset/set */
\r
17789 /* TA2CCTL[CAP] Bits */
\r
17790 //#define CAP_OFS ( 8) /* CAP Offset */
\r
17791 //#define CAP (0x0100) /* Capture mode */
\r
17792 /* TA2CCTL[SCCI] Bits */
\r
17793 //#define SCCI_OFS (10) /* SCCI Offset */
\r
17794 //#define SCCI (0x0400) /* Synchronized capture/compare input */
\r
17795 /* TA2CCTL[SCS] Bits */
\r
17796 //#define SCS_OFS (11) /* SCS Offset */
\r
17797 //#define SCS (0x0800) /* Synchronize capture source */
\r
17798 /* TA2CCTL[CCIS] Bits */
\r
17799 //#define CCIS_OFS (12) /* CCIS Offset */
\r
17800 //#define CCIS_M (0x3000) /* Capture/compare input select */
\r
17801 //#define CCIS0 (0x1000) /* Capture/compare input select */
\r
17802 //#define CCIS1 (0x2000) /* Capture/compare input select */
\r
17803 //#define CCIS_0 (0x0000) /* CCIxA */
\r
17804 //#define CCIS_1 (0x1000) /* CCIxB */
\r
17805 //#define CCIS_2 (0x2000) /* GND */
\r
17806 //#define CCIS_3 (0x3000) /* VCC */
\r
17807 //#define CCIS__CCIA (0x0000) /* CCIxA */
\r
17808 //#define CCIS__CCIB (0x1000) /* CCIxB */
\r
17809 //#define CCIS__GND (0x2000) /* GND */
\r
17810 //#define CCIS__VCC (0x3000) /* VCC */
\r
17811 /* TA2CCTL[CM] Bits */
\r
17812 //#define CM_OFS (14) /* CM Offset */
\r
17813 //#define CM_M (0xc000) /* Capture mode */
\r
17814 //#define CM0 (0x4000) /* Capture mode */
\r
17815 //#define CM1 (0x8000) /* Capture mode */
\r
17816 //#define CM_0 (0x0000) /* No capture */
\r
17817 //#define CM_1 (0x4000) /* Capture on rising edge */
\r
17818 //#define CM_2 (0x8000) /* Capture on falling edge */
\r
17819 //#define CM_3 (0xc000) /* Capture on both rising and falling edges */
\r
17820 //#define CM__NONE (0x0000) /* No capture */
\r
17821 //#define CM__RISING (0x4000) /* Capture on rising edge */
\r
17822 //#define CM__FALLING (0x8000) /* Capture on falling edge */
\r
17823 //#define CM__BOTH (0xc000) /* Capture on both rising and falling edges */
\r
17824 /* TA2EX0[TAIDEX] Bits */
\r
17825 //#define TAIDEX_OFS ( 0) /* TAIDEX Offset */
\r
17826 //#define TAIDEX_M (0x0007) /* Input divider expansion */
\r
17827 //#define TAIDEX0 (0x0001) /* Input divider expansion */
\r
17828 //#define TAIDEX1 (0x0002) /* Input divider expansion */
\r
17829 //#define TAIDEX2 (0x0004) /* Input divider expansion */
\r
17830 //#define TAIDEX_0 (0x0000) /* Divide by 1 */
\r
17831 //#define TAIDEX_1 (0x0001) /* Divide by 2 */
\r
17832 //#define TAIDEX_2 (0x0002) /* Divide by 3 */
\r
17833 //#define TAIDEX_3 (0x0003) /* Divide by 4 */
\r
17834 //#define TAIDEX_4 (0x0004) /* Divide by 5 */
\r
17835 //#define TAIDEX_5 (0x0005) /* Divide by 6 */
\r
17836 //#define TAIDEX_6 (0x0006) /* Divide by 7 */
\r
17837 //#define TAIDEX_7 (0x0007) /* Divide by 8 */
\r
17838 //#define TAIDEX__1 (0x0000) /* Divide by 1 */
\r
17839 //#define TAIDEX__2 (0x0001) /* Divide by 2 */
\r
17840 //#define TAIDEX__3 (0x0002) /* Divide by 3 */
\r
17841 //#define TAIDEX__4 (0x0003) /* Divide by 4 */
\r
17842 //#define TAIDEX__5 (0x0004) /* Divide by 5 */
\r
17843 //#define TAIDEX__6 (0x0005) /* Divide by 6 */
\r
17844 //#define TAIDEX__7 (0x0006) /* Divide by 7 */
\r
17845 //#define TAIDEX__8 (0x0007) /* Divide by 8 */
\r
17848 //*****************************************************************************
\r
17850 //*****************************************************************************
\r
17851 /* TA3CTL[TAIFG] Bits */
\r
17852 //#define TAIFG_OFS ( 0) /* TAIFG Offset */
\r
17853 //#define TAIFG (0x0001) /* TimerA interrupt flag */
\r
17854 /* TA3CTL[TAIE] Bits */
\r
17855 //#define TAIE_OFS ( 1) /* TAIE Offset */
\r
17856 //#define TAIE (0x0002) /* TimerA interrupt enable */
\r
17857 /* TA3CTL[TACLR] Bits */
\r
17858 //#define TACLR_OFS ( 2) /* TACLR Offset */
\r
17859 //#define TACLR (0x0004) /* TimerA clear */
\r
17860 /* TA3CTL[MC] Bits */
\r
17861 //#define MC_OFS ( 4) /* MC Offset */
\r
17862 //#define MC_M (0x0030) /* Mode control */
\r
17863 //#define MC0 (0x0010) /* Mode control */
\r
17864 //#define MC1 (0x0020) /* Mode control */
\r
17865 //#define MC_0 (0x0000) /* Stop mode: Timer is halted */
\r
17866 //#define MC_1 (0x0010) /* Up mode: Timer counts up to TAxCCR0 */
\r
17867 //#define MC_2 (0x0020) /* Continuous mode: Timer counts up to 0FFFFh */
\r
17868 //#define MC_3 (0x0030) /* Up/down mode: Timer counts up to TAxCCR0 then down to 0000h */
\r
17869 //#define MC__STOP (0x0000) /* Stop mode: Timer is halted */
\r
17870 //#define MC__UP (0x0010) /* Up mode: Timer counts up to TAxCCR0 */
\r
17871 //#define MC__CONTINUOUS (0x0020) /* Continuous mode: Timer counts up to 0FFFFh */
\r
17872 //#define MC__UPDOWN (0x0030) /* Up/down mode: Timer counts up to TAxCCR0 then down to 0000h */
\r
17873 /* TA3CTL[ID] Bits */
\r
17874 //#define ID_OFS ( 6) /* ID Offset */
\r
17875 //#define ID_M (0x00c0) /* Input divider */
\r
17876 //#define ID0 (0x0040) /* Input divider */
\r
17877 //#define ID1 (0x0080) /* Input divider */
\r
17878 //#define ID_0 (0x0000) /* /1 */
\r
17879 //#define ID_1 (0x0040) /* /2 */
\r
17880 //#define ID_2 (0x0080) /* /4 */
\r
17881 //#define ID_3 (0x00c0) /* /8 */
\r
17882 //#define ID__1 (0x0000) /* /1 */
\r
17883 //#define ID__2 (0x0040) /* /2 */
\r
17884 //#define ID__4 (0x0080) /* /4 */
\r
17885 //#define ID__8 (0x00c0) /* /8 */
\r
17886 /* TA3CTL[TASSEL] Bits */
\r
17887 //#define TASSEL_OFS ( 8) /* TASSEL Offset */
\r
17888 //#define TASSEL_M (0x0300) /* TimerA clock source select */
\r
17889 //#define TASSEL0 (0x0100) /* TimerA clock source select */
\r
17890 //#define TASSEL1 (0x0200) /* TimerA clock source select */
\r
17891 //#define TASSEL_0 (0x0000) /* TAxCLK */
\r
17892 //#define TASSEL_1 (0x0100) /* ACLK */
\r
17893 //#define TASSEL_2 (0x0200) /* SMCLK */
\r
17894 //#define TASSEL_3 (0x0300) /* INCLK */
\r
17895 //#define TASSEL__TACLK (0x0000) /* TAxCLK */
\r
17896 //#define TASSEL__ACLK (0x0100) /* ACLK */
\r
17897 //#define TASSEL__SMCLK (0x0200) /* SMCLK */
\r
17898 //#define TASSEL__INCLK (0x0300) /* INCLK */
\r
17899 /* TA3CCTL[CCIFG] Bits */
\r
17900 //#define CCIFG_OFS ( 0) /* CCIFG Offset */
\r
17901 //#define CCIFG (0x0001) /* Capture/compare interrupt flag */
\r
17902 /* TA3CCTL[COV] Bits */
\r
17903 //#define COV_OFS ( 1) /* COV Offset */
\r
17904 //#define COV (0x0002) /* Capture overflow */
\r
17905 /* TA3CCTL[OUT] Bits */
\r
17906 //#define OUT_OFS ( 2) /* OUT Offset */
\r
17907 //#define OUT (0x0004) /* Output */
\r
17908 /* TA3CCTL[CCI] Bits */
\r
17909 //#define CCI_OFS ( 3) /* CCI Offset */
\r
17910 //#define CCI (0x0008) /* Capture/compare input */
\r
17911 /* TA3CCTL[CCIE] Bits */
\r
17912 //#define CCIE_OFS ( 4) /* CCIE Offset */
\r
17913 //#define CCIE (0x0010) /* Capture/compare interrupt enable */
\r
17914 /* TA3CCTL[OUTMOD] Bits */
\r
17915 //#define OUTMOD_OFS ( 5) /* OUTMOD Offset */
\r
17916 //#define OUTMOD_M (0x00e0) /* Output mode */
\r
17917 //#define OUTMOD0 (0x0020) /* Output mode */
\r
17918 //#define OUTMOD1 (0x0040) /* Output mode */
\r
17919 //#define OUTMOD2 (0x0080) /* Output mode */
\r
17920 //#define OUTMOD_0 (0x0000) /* OUT bit value */
\r
17921 //#define OUTMOD_1 (0x0020) /* Set */
\r
17922 //#define OUTMOD_2 (0x0040) /* Toggle/reset */
\r
17923 //#define OUTMOD_3 (0x0060) /* Set/reset */
\r
17924 //#define OUTMOD_4 (0x0080) /* Toggle */
\r
17925 //#define OUTMOD_5 (0x00a0) /* Reset */
\r
17926 //#define OUTMOD_6 (0x00c0) /* Toggle/set */
\r
17927 //#define OUTMOD_7 (0x00e0) /* Reset/set */
\r
17928 /* TA3CCTL[CAP] Bits */
\r
17929 //#define CAP_OFS ( 8) /* CAP Offset */
\r
17930 //#define CAP (0x0100) /* Capture mode */
\r
17931 /* TA3CCTL[SCCI] Bits */
\r
17932 //#define SCCI_OFS (10) /* SCCI Offset */
\r
17933 //#define SCCI (0x0400) /* Synchronized capture/compare input */
\r
17934 /* TA3CCTL[SCS] Bits */
\r
17935 //#define SCS_OFS (11) /* SCS Offset */
\r
17936 //#define SCS (0x0800) /* Synchronize capture source */
\r
17937 /* TA3CCTL[CCIS] Bits */
\r
17938 //#define CCIS_OFS (12) /* CCIS Offset */
\r
17939 //#define CCIS_M (0x3000) /* Capture/compare input select */
\r
17940 //#define CCIS0 (0x1000) /* Capture/compare input select */
\r
17941 //#define CCIS1 (0x2000) /* Capture/compare input select */
\r
17942 //#define CCIS_0 (0x0000) /* CCIxA */
\r
17943 //#define CCIS_1 (0x1000) /* CCIxB */
\r
17944 //#define CCIS_2 (0x2000) /* GND */
\r
17945 //#define CCIS_3 (0x3000) /* VCC */
\r
17946 //#define CCIS__CCIA (0x0000) /* CCIxA */
\r
17947 //#define CCIS__CCIB (0x1000) /* CCIxB */
\r
17948 //#define CCIS__GND (0x2000) /* GND */
\r
17949 //#define CCIS__VCC (0x3000) /* VCC */
\r
17950 /* TA3CCTL[CM] Bits */
\r
17951 //#define CM_OFS (14) /* CM Offset */
\r
17952 //#define CM_M (0xc000) /* Capture mode */
\r
17953 //#define CM0 (0x4000) /* Capture mode */
\r
17954 //#define CM1 (0x8000) /* Capture mode */
\r
17955 //#define CM_0 (0x0000) /* No capture */
\r
17956 //#define CM_1 (0x4000) /* Capture on rising edge */
\r
17957 //#define CM_2 (0x8000) /* Capture on falling edge */
\r
17958 //#define CM_3 (0xc000) /* Capture on both rising and falling edges */
\r
17959 //#define CM__NONE (0x0000) /* No capture */
\r
17960 //#define CM__RISING (0x4000) /* Capture on rising edge */
\r
17961 //#define CM__FALLING (0x8000) /* Capture on falling edge */
\r
17962 //#define CM__BOTH (0xc000) /* Capture on both rising and falling edges */
\r
17963 /* TA3EX0[TAIDEX] Bits */
\r
17964 //#define TAIDEX_OFS ( 0) /* TAIDEX Offset */
\r
17965 //#define TAIDEX_M (0x0007) /* Input divider expansion */
\r
17966 //#define TAIDEX0 (0x0001) /* Input divider expansion */
\r
17967 //#define TAIDEX1 (0x0002) /* Input divider expansion */
\r
17968 //#define TAIDEX2 (0x0004) /* Input divider expansion */
\r
17969 //#define TAIDEX_0 (0x0000) /* Divide by 1 */
\r
17970 //#define TAIDEX_1 (0x0001) /* Divide by 2 */
\r
17971 //#define TAIDEX_2 (0x0002) /* Divide by 3 */
\r
17972 //#define TAIDEX_3 (0x0003) /* Divide by 4 */
\r
17973 //#define TAIDEX_4 (0x0004) /* Divide by 5 */
\r
17974 //#define TAIDEX_5 (0x0005) /* Divide by 6 */
\r
17975 //#define TAIDEX_6 (0x0006) /* Divide by 7 */
\r
17976 //#define TAIDEX_7 (0x0007) /* Divide by 8 */
\r
17977 //#define TAIDEX__1 (0x0000) /* Divide by 1 */
\r
17978 //#define TAIDEX__2 (0x0001) /* Divide by 2 */
\r
17979 //#define TAIDEX__3 (0x0002) /* Divide by 3 */
\r
17980 //#define TAIDEX__4 (0x0003) /* Divide by 4 */
\r
17981 //#define TAIDEX__5 (0x0004) /* Divide by 5 */
\r
17982 //#define TAIDEX__6 (0x0005) /* Divide by 6 */
\r
17983 //#define TAIDEX__7 (0x0006) /* Divide by 7 */
\r
17984 //#define TAIDEX__8 (0x0007) /* Divide by 8 */
\r
17987 //*****************************************************************************
\r
17989 //*****************************************************************************
\r
17992 //*****************************************************************************
\r
17994 //*****************************************************************************
\r
17995 /* WDTCTL[WDTIS] Bits */
\r
17996 #define WDTIS_OFS ( 0) /* WDTIS Offset */
\r
17997 #define WDTIS_M (0x0007) /* Watchdog timer interval select */
\r
17998 #define WDTIS0 (0x0001) /* Watchdog timer interval select */
\r
17999 #define WDTIS1 (0x0002) /* Watchdog timer interval select */
\r
18000 #define WDTIS2 (0x0004) /* Watchdog timer interval select */
\r
18001 #define WDTIS_0 (0x0000) /* Watchdog clock source / (2^(31)) (18:12:16 at 32.768 kHz) */
\r
18002 #define WDTIS_1 (0x0001) /* Watchdog clock source /(2^(27)) (01:08:16 at 32.768 kHz) */
\r
18003 #define WDTIS_2 (0x0002) /* Watchdog clock source /(2^(23)) (00:04:16 at 32.768 kHz) */
\r
18004 #define WDTIS_3 (0x0003) /* Watchdog clock source /(2^(19)) (00:00:16 at 32.768 kHz) */
\r
18005 #define WDTIS_4 (0x0004) /* Watchdog clock source /(2^(15)) (1 s at 32.768 kHz) */
\r
18006 #define WDTIS_5 (0x0005) /* Watchdog clock source / (2^(13)) (250 ms at 32.768 kHz) */
\r
18007 #define WDTIS_6 (0x0006) /* Watchdog clock source / (2^(9)) (15.625 ms at 32.768 kHz) */
\r
18008 #define WDTIS_7 (0x0007) /* Watchdog clock source / (2^(6)) (1.95 ms at 32.768 kHz) */
\r
18009 /* WDTCTL[WDTCNTCL] Bits */
\r
18010 #define WDTCNTCL_OFS ( 3) /* WDTCNTCL Offset */
\r
18011 #define WDTCNTCL (0x0008) /* Watchdog timer counter clear */
\r
18012 /* WDTCTL[WDTTMSEL] Bits */
\r
18013 #define WDTTMSEL_OFS ( 4) /* WDTTMSEL Offset */
\r
18014 #define WDTTMSEL (0x0010) /* Watchdog timer mode select */
\r
18015 /* WDTCTL[WDTSSEL] Bits */
\r
18016 #define WDTSSEL_OFS ( 5) /* WDTSSEL Offset */
\r
18017 #define WDTSSEL_M (0x0060) /* Watchdog timer clock source select */
\r
18018 #define WDTSSEL0 (0x0020) /* Watchdog timer clock source select */
\r
18019 #define WDTSSEL1 (0x0040) /* Watchdog timer clock source select */
\r
18020 #define WDTSSEL_0 (0x0000) /* SMCLK */
\r
18021 #define WDTSSEL_1 (0x0020) /* ACLK */
\r
18022 #define WDTSSEL_2 (0x0040) /* VLOCLK */
\r
18023 #define WDTSSEL_3 (0x0060) /* BCLK */
\r
18024 #define WDTSSEL__SMCLK (0x0000) /* SMCLK */
\r
18025 #define WDTSSEL__ACLK (0x0020) /* ACLK */
\r
18026 #define WDTSSEL__VLOCLK (0x0040) /* VLOCLK */
\r
18027 #define WDTSSEL__BCLK (0x0060) /* BCLK */
\r
18028 /* WDTCTL[WDTHOLD] Bits */
\r
18029 #define WDTHOLD_OFS ( 7) /* WDTHOLD Offset */
\r
18030 #define WDTHOLD (0x0080) /* Watchdog timer hold */
\r
18031 /* WDTCTL[WDTPW] Bits */
\r
18032 #define WDTPW_OFS ( 8) /* WDTPW Offset */
\r
18033 #define WDTPW_M (0xff00) /* Watchdog timer password */
\r
18035 /* Pre-defined bitfield values */
\r
18036 #define WDTPW (0x5A00) /* WDT Key Value for WDT write access */
\r
18038 //*****************************************************************************
\r
18040 //*****************************************************************************
\r
18041 #define BSL_DEFAULT_PARAM (0xFC48FFFF) /* I2C slave address = 0x48, Interface selection = Auto */
\r
18042 #define BSL_API_TABLE_ADDR (0x00202000) /* Address of BSL API table */
\r
18043 #define BSL_ENTRY_FUNCTION (*((uint32_t *)BSL_API_TABLE_ADDR))
\r
18045 #define BSL_AUTO_INTERFACE (0x0000E0000) /* Auto detect interface */
\r
18046 #define BSL_UART_INTERFACE (0x0000C0000) /* UART interface */
\r
18047 #define BSL_SPI_INTERFACE (0x0000A0000) /* SPI interface */
\r
18048 #define BSL_I2C_INTERFACE (0x000080000) /* I2C interface */
\r
18050 #define BSL_INVOKE(x) ((void (*)())BSL_ENTRY_FUNCTION)((uint32_t) x) /* Invoke the BSL with paramters */
\r
18052 //*****************************************************************************
\r
18054 //*****************************************************************************
\r
18055 #ifdef __TMS470__
\r
18056 #pragma ULP_PORT_CONFIG(1,DIR={0x40004C04,8},OUT={0x40004C02,8},SEL1={0x40004C0A,8},SEL2={0x40004C0C,8})
\r
18057 #pragma ULP_PORT_CONFIG(2,DIR={0x40004C05,8},OUT={0x40004C03,8},SEL1={0x40004C0B,8},SEL2={0x40004C0D,8})
\r
18058 #pragma ULP_PORT_CONFIG(3,DIR={0x40004C24,8},OUT={0x40004C22,8},SEL1={0x40004C2A,8},SEL2={0x40004C2C,8})
\r
18059 #pragma ULP_PORT_CONFIG(4,DIR={0x40004C25,8},OUT={0x40004C23,8},SEL1={0x40004C2B,8},SEL2={0x40004C2D,8})
\r
18060 #pragma ULP_PORT_CONFIG(5,DIR={0x40004C44,8},OUT={0x40004C42,8},SEL1={0x40004C4A,8},SEL2={0x40004C4C,8})
\r
18061 #pragma ULP_PORT_CONFIG(6,DIR={0x40004C45,8},OUT={0x40004C43,8},SEL1={0x40004C4B,8},SEL2={0x40004C4D,8})
\r
18062 #pragma ULP_PORT_CONFIG(7,DIR={0x40004C64,8},OUT={0x40004C62,8},SEL1={0x40004C6A,8},SEL2={0x40004C6C,8})
\r
18063 #pragma ULP_PORT_CONFIG(8,DIR={0x40004C65,8},OUT={0x40004C63,8},SEL1={0x40004C6B,8},SEL2={0x40004C6D,8})
\r
18064 #pragma ULP_PORT_CONFIG(9,DIR={0x40004C84,8},OUT={0x40004C82,8},SEL1={0x40004C8A,8},SEL2={0x40004C8C,8})
\r
18065 #pragma ULP_PORT_CONFIG(10,DIR={0x40004C85,8},OUT={0x40004C83,8},SEL1={0x40004C8B,8},SEL2={0x40004C8D,8})
\r
18068 //*****************************************************************************
\r
18069 // NVIC interrupts
\r
18070 //*****************************************************************************
\r
18072 // System exceptions
\r
18073 #define FAULT_NMI ( 2) /* NMI fault */
\r
18074 #define FAULT_HARD ( 3) /* Hard fault */
\r
18075 #define FAULT_MPU ( 4) /* MPU fault */
\r
18076 #define FAULT_BUS ( 5) /* Bus fault */
\r
18077 #define FAULT_USAGE ( 6) /* Usage fault */
\r
18078 #define FAULT_SVCALL (11) /* SVCall */
\r
18079 #define FAULT_DEBUG (12) /* Debug monitor */
\r
18080 #define FAULT_PENDSV (14) /* PendSV */
\r
18081 #define FAULT_SYSTICK (15) /* System Tick */
\r
18083 // External interrupts
\r
18084 #define INT_PSS (16) /* PSS IRQ */
\r
18085 #define INT_CS (17) /* CS IRQ */
\r
18086 #define INT_PCM (18) /* PCM IRQ */
\r
18087 #define INT_WDT_A (19) /* WDT_A IRQ */
\r
18088 #define INT_FPU (20) /* FPU IRQ */
\r
18089 #define INT_FLCTL (21) /* FLCTL IRQ */
\r
18090 #define INT_COMP_E0 (22) /* COMP_E0 IRQ */
\r
18091 #define INT_COMP_E1 (23) /* COMP_E1 IRQ */
\r
18092 #define INT_TA0_0 (24) /* TA0_0 IRQ */
\r
18093 #define INT_TA0_N (25) /* TA0_N IRQ */
\r
18094 #define INT_TA1_0 (26) /* TA1_0 IRQ */
\r
18095 #define INT_TA1_N (27) /* TA1_N IRQ */
\r
18096 #define INT_TA2_0 (28) /* TA2_0 IRQ */
\r
18097 #define INT_TA2_N (29) /* TA2_N IRQ */
\r
18098 #define INT_TA3_0 (30) /* TA3_0 IRQ */
\r
18099 #define INT_TA3_N (31) /* TA3_N IRQ */
\r
18100 #define INT_EUSCIA0 (32) /* EUSCIA0 IRQ */
\r
18101 #define INT_EUSCIA1 (33) /* EUSCIA1 IRQ */
\r
18102 #define INT_EUSCIA2 (34) /* EUSCIA2 IRQ */
\r
18103 #define INT_EUSCIA3 (35) /* EUSCIA3 IRQ */
\r
18104 #define INT_EUSCIB0 (36) /* EUSCIB0 IRQ */
\r
18105 #define INT_EUSCIB1 (37) /* EUSCIB1 IRQ */
\r
18106 #define INT_EUSCIB2 (38) /* EUSCIB2 IRQ */
\r
18107 #define INT_EUSCIB3 (39) /* EUSCIB3 IRQ */
\r
18108 #define INT_ADC14 (40) /* ADC14 IRQ */
\r
18109 #define INT_T32_INT1 (41) /* T32_INT1 IRQ */
\r
18110 #define INT_T32_INT2 (42) /* T32_INT2 IRQ */
\r
18111 #define INT_T32_INTC (43) /* T32_INTC IRQ */
\r
18112 #define INT_AES256 (44) /* AES256 IRQ */
\r
18113 #define INT_RTC_C (45) /* RTC_C IRQ */
\r
18114 #define INT_DMA_ERR (46) /* DMA_ERR IRQ */
\r
18115 #define INT_DMA_INT3 (47) /* DMA_INT3 IRQ */
\r
18116 #define INT_DMA_INT2 (48) /* DMA_INT2 IRQ */
\r
18117 #define INT_DMA_INT1 (49) /* DMA_INT1 IRQ */
\r
18118 #define INT_DMA_INT0 (50) /* DMA_INT0 IRQ */
\r
18119 #define INT_PORT1 (51) /* PORT1 IRQ */
\r
18120 #define INT_PORT2 (52) /* PORT2 IRQ */
\r
18121 #define INT_PORT3 (53) /* PORT3 IRQ */
\r
18122 #define INT_PORT4 (54) /* PORT4 IRQ */
\r
18123 #define INT_PORT5 (55) /* PORT5 IRQ */
\r
18124 #define INT_PORT6 (56) /* PORT6 IRQ */
\r
18126 // Highest interrupt available
\r
18127 #define NUM_INTERRUPTS (56)
\r
18129 #endif // __MSP432P401R_H__
\r
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