2 * -------------------------------------------
3 * MSP432 DriverLib - v01_04_00_18
4 * -------------------------------------------
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37 #ifndef __INTERRUPT_H__
38 #define __INTERRUPT_H__
40 //*****************************************************************************
42 //! \addtogroup interrupt_api
45 //*****************************************************************************
48 //*****************************************************************************
50 // If building with a C++ compiler, make all of the definitions in this header
53 //*****************************************************************************
63 //*****************************************************************************
65 // Macro to generate an interrupt priority mask based on the number of bits
66 // of priority supported by the hardware.
68 //*****************************************************************************
69 #define INT_PRIORITY_MASK ((0xFF << (8 - NUM_PRIORITY_BITS)) & 0xFF)
70 #define NUM_PRIORITY 8
72 #define NVIC_APINT_PRIGROUP_M 0x00000700 // Interrupt Priority Grouping
73 #define NVIC_APINT_PRIGROUP_7_1 0x00000000 // Priority group 7.1 split
74 #define NVIC_APINT_PRIGROUP_6_2 0x00000100 // Priority group 6.2 split
75 #define NVIC_APINT_PRIGROUP_5_3 0x00000200 // Priority group 5.3 split
76 #define NVIC_APINT_PRIGROUP_4_4 0x00000300 // Priority group 4.4 split
77 #define NVIC_APINT_PRIGROUP_3_5 0x00000400 // Priority group 3.5 split
78 #define NVIC_APINT_PRIGROUP_2_6 0x00000500 // Priority group 2.6 split
79 #define NVIC_APINT_PRIGROUP_1_7 0x00000600 // Priority group 1.7 split
80 #define NVIC_APINT_PRIGROUP_0_8 0x00000700 // Priority group 0.8 split
81 #define NVIC_SYS_PRI1_R 0xE000ED18 // System Handler Priority 1
82 #define NVIC_SYS_PRI2_R 0xE000ED1C // System Handler Priority 2
83 #define NVIC_SYS_PRI3_R 0xE000ED20 // System Handler Priority 3
84 #define NVIC_PRI0_R 0xE000E400 // Interrupt 0-3 Priority
85 #define NVIC_PRI1_R 0xE000E404 // Interrupt 4-7 Priority
86 #define NVIC_PRI2_R 0xE000E408 // Interrupt 8-11 Priority
87 #define NVIC_PRI3_R 0xE000E40C // Interrupt 12-15 Priority
88 #define NVIC_PRI4_R 0xE000E410 // Interrupt 16-19 Priority
89 #define NVIC_PRI5_R 0xE000E414 // Interrupt 20-23 Priority
90 #define NVIC_PRI6_R 0xE000E418 // Interrupt 24-27 Priority
91 #define NVIC_PRI7_R 0xE000E41C // Interrupt 28-31 Priority
92 #define NVIC_PRI8_R 0xE000E420 // Interrupt 32-35 Priority
93 #define NVIC_PRI9_R 0xE000E424 // Interrupt 36-39 Priority
94 #define NVIC_PRI10_R 0xE000E428 // Interrupt 40-43 Priority
95 #define NVIC_PRI11_R 0xE000E42C // Interrupt 44-47 Priority
96 #define NVIC_PRI12_R 0xE000E430 // Interrupt 48-51 Priority
97 #define NVIC_PRI13_R 0xE000E434 // Interrupt 52-55 Priority
98 #define NVIC_PRI14_R 0xE000E438 // Interrupt 56-59 Priority
99 #define NVIC_PRI15_R 0xE000E43C // Interrupt 60-63 Priority
100 #define NVIC_EN0_R 0xE000E100 // Interrupt 0-31 Set Enable
101 #define NVIC_EN1_R 0xE000E104 // Interrupt 32-54 Set Enable
102 #define NVIC_DIS0_R 0xE000E180 // Interrupt 0-31 Clear Enable
103 #define NVIC_DIS1_R 0xE000E184 // Interrupt 32-54 Clear Enable
104 #define NVIC_PEND0_R 0xE000E200 // Interrupt 0-31 Set Pending
105 #define NVIC_PEND1_R 0xE000E204 // Interrupt 32-54 Set Pending
106 #define NVIC_UNPEND0_R 0xE000E280 // Interrupt 0-31 Clear Pending
107 #define NVIC_UNPEND1_R 0xE000E284 // Interrupt 32-54 Clear Pending
108 //*****************************************************************************
110 // Prototypes for the APIs.
112 //*****************************************************************************
114 //*****************************************************************************
116 //! Enables the processor interrupt.
118 //! This function allows the processor to respond to interrupts. This function
119 //! does not affect the set of interrupts enabled in the interrupt controller;
120 //! it just gates the single interrupt from the controller to the processor.
122 //! \return Returns \b true if interrupts were disabled when the function was
123 //! called or \b false if they were initially enabled.
125 //*****************************************************************************
126 extern bool Interrupt_enableMaster(void);
128 //*****************************************************************************
130 //! Disables the processor interrupt.
132 //! This function prevents the processor from receiving interrupts. This
133 //! function does not affect the set of interrupts enabled in the interrupt
134 //! controller; it just gates the single interrupt from the controller to the
137 //! \return Returns \b true if interrupts were already disabled when the
138 //! function was called or \b false if they were initially enabled.
140 //*****************************************************************************
141 extern bool Interrupt_disableMaster(void);
143 //*****************************************************************************
145 //! Registers a function to be called when an interrupt occurs.
147 //! \param interruptNumber specifies the interrupt in question.
148 //! \param intHandler is a pointer to the function to be called.
150 //! \note The use of this function (directly or indirectly via a peripheral
151 //! driver interrupt register function) moves the interrupt vector table from
152 //! flash to SRAM. Therefore, care must be taken when linking the application
153 //! to ensure that the SRAM vector table is located at the beginning of SRAM;
154 //! otherwise the NVIC does not look in the correct portion of memory for the
155 //! vector table (it requires the vector table be on a 1 kB memory alignment).
156 //! Normally, the SRAM vector table is so placed via the use of linker scripts.
157 //! See the discussion of compile-time versus run-time interrupt handler
158 //! registration in the introduction to this chapter.
160 //! See \link Interrupt_enableInterrupt \endlink for details about the interrupt
165 //*****************************************************************************
166 extern void Interrupt_registerInterrupt(uint32_t interruptNumber,
167 void (*intHandler)(void));
169 //*****************************************************************************
171 //! Unregisters the function to be called when an interrupt occurs.
173 //! \param interruptNumber specifies the interrupt in question.
175 //! This function is used to indicate that no handler should be called when the
176 //! given interrupt is asserted to the processor. The interrupt source is
177 //! automatically disabled (via Interrupt_disableInterrupt()) if necessary.
179 //! \sa Interrupt_registerInterrupt() for important information about
180 //! registering interrupt handlers.
182 //! See \link Interrupt_enableInterrupt \endlink for details about the interrupt
187 //*****************************************************************************
188 extern void Interrupt_unregisterInterrupt(uint32_t interruptNumber);
190 //*****************************************************************************
192 //! Sets the priority grouping of the interrupt controller.
194 //! \param bits specifies the number of bits of preemptable priority.
196 //! This function specifies the split between preemptable priority levels and
197 //! sub-priority levels in the interrupt priority specification. The range of
198 //! the grouping values are dependent upon the hardware implementation; on
199 //! the MSP432 family, three bits are available for hardware interrupt
200 //! prioritization and therefore priority grouping values of three through
201 //! seven have the same effect.
205 //*****************************************************************************
206 extern void Interrupt_setPriorityGrouping(uint32_t bits);
208 //*****************************************************************************
210 //! Gets the priority grouping of the interrupt controller.
212 //! This function returns the split between preemptable priority levels and
213 //! sub-priority levels in the interrupt priority specification.
215 //! \return The number of bits of preemptable priority.
217 //*****************************************************************************
218 extern uint32_t Interrupt_getPriorityGrouping(void);
220 //*****************************************************************************
222 //! Sets the priority of an interrupt.
224 //! \param interruptNumber specifies the interrupt in question.
225 //! \param priority specifies the priority of the interrupt.
227 //! This function is used to set the priority of an interrupt. When multiple
228 //! interrupts are asserted simultaneously, the ones with the highest priority
229 //! are processed before the lower priority interrupts. Smaller numbers
230 //! correspond to higher interrupt priorities; priority 0 is the highest
231 //! interrupt priority.
233 //! The hardware priority mechanism only looks at the upper N bits of the
234 //! priority level (where N is 3 for the MSP432 family), so any
235 //! prioritization must be performed in those bits. The remaining bits can be
236 //! used to sub-prioritize the interrupt sources, and may be used by the
237 //! hardware priority mechanism on a future part. This arrangement allows
238 //! priorities to migrate to different NVIC implementations without changing
239 //! the gross prioritization of the interrupts.
241 //! See \link Interrupt_enableInterrupt \endlink for details about the interrupt
246 //*****************************************************************************
247 extern void Interrupt_setPriority(uint32_t interruptNumber, uint8_t priority);
249 //*****************************************************************************
251 //! Gets the priority of an interrupt.
253 //! \param interruptNumber specifies the interrupt in question.
255 //! This function gets the priority of an interrupt. See
256 //! Interrupt_setPriority() for a definition of the priority value.
258 //! See \link Interrupt_enableInterrupt \endlink for details about the interrupt
261 //! \return Returns the interrupt priority, or -1 if an invalid interrupt was
264 //*****************************************************************************
265 extern uint8_t Interrupt_getPriority(uint32_t interruptNumber);
267 //*****************************************************************************
269 //! Enables an interrupt.
271 //! \param interruptNumber specifies the interrupt to be enabled.
273 //! The specified interrupt is enabled in the interrupt controller. Other
274 //! enables for the interrupt (such as at the peripheral level) are unaffected
275 //! by this function.
277 //! Valid values will vary from part to part, so it is important to check the
278 //! device specific datasheet, however for MSP432 101 the following values can
285 //! - \b FAULT_SVCALL
287 //! - \b FAULT_PENDSV
288 //! - \b FAULT_SYSTICK
314 //! - \b INT_T32_INT1
315 //! - \b INT_T32_INT2
316 //! - \b INT_T32_INTC
320 //! - \b INT_DMA_INT3
321 //! - \b INT_DMA_INT2
322 //! - \b INT_DMA_INT1
323 //! - \b INT_DMA_INT0
333 //*****************************************************************************
334 extern void Interrupt_enableInterrupt(uint32_t interruptNumber);
336 //*****************************************************************************
338 //! Disables an interrupt.
340 //! \param interruptNumber specifies the interrupt to be disabled.
342 //! The specified interrupt is disabled in the interrupt controller. Other
343 //! enables for the interrupt (such as at the peripheral level) are unaffected
344 //! by this function.
346 //! See \link Interrupt_enableInterrupt \endlink for details about the interrupt
351 //*****************************************************************************
352 extern void Interrupt_disableInterrupt(uint32_t interruptNumber);
354 //*****************************************************************************
356 //! Returns if a peripheral interrupt is enabled.
358 //! \param interruptNumber specifies the interrupt to check.
360 //! This function checks if the specified interrupt is enabled in the interrupt
363 //! See \link Interrupt_enableInterrupt \endlink for details about the interrupt
366 //! \return A non-zero value if the interrupt is enabled.
368 //*****************************************************************************
369 extern bool Interrupt_isEnabled(uint32_t interruptNumber);
371 //*****************************************************************************
373 //! Pends an interrupt.
375 //! \param interruptNumber specifies the interrupt to be pended.
377 //! The specified interrupt is pended in the interrupt controller. Pending an
378 //! interrupt causes the interrupt controller to execute the corresponding
379 //! interrupt handler at the next available time, based on the current
380 //! interrupt state priorities. For example, if called by a higher priority
381 //! interrupt handler, the specified interrupt handler is not called until
382 //! after the current interrupt handler has completed execution. The interrupt
383 //! must have been enabled for it to be called.
385 //! See \link Interrupt_enableInterrupt \endlink for details about the interrupt
390 //*****************************************************************************
391 extern void Interrupt_pendInterrupt(uint32_t interruptNumber);
393 //*****************************************************************************
395 //! Un-pends an interrupt.
397 //! \param interruptNumber specifies the interrupt to be un-pended.
399 //! The specified interrupt is un-pended in the interrupt controller. This
400 //! will cause any previously generated interrupts that have not been handled
401 //! yet (due to higher priority interrupts or the interrupt no having been
402 //! enabled yet) to be discarded.
404 //! See \link Interrupt_enableInterrupt \endlink for details about the interrupt
409 //*****************************************************************************
410 extern void Interrupt_unpendInterrupt(uint32_t interruptNumber);
412 //*****************************************************************************
414 //! Sets the priority masking level
416 //! \param priorityMask is the priority level that is masked.
418 //! This function sets the interrupt priority masking level so that all
419 //! interrupts at the specified or lesser priority level are masked. Masking
420 //! interrupts can be used to globally disable a set of interrupts with
421 //! priority below a predetermined threshold. A value of 0 disables priority
424 //! Smaller numbers correspond to higher interrupt priorities. So for example
425 //! a priority level mask of 4 allows interrupts of priority level 0-3,
426 //! and interrupts with a numerical priority of 4 and greater are blocked.
428 //! The hardware priority mechanism only looks at the upper N bits of the
429 //! priority level (where N is 3 for the MSP432 family), so any
430 //! prioritization must be performed in those bits.
434 //*****************************************************************************
435 extern void Interrupt_setPriorityMask(uint8_t priorityMask);
437 //*****************************************************************************
439 //! Gets the priority masking level
441 //! This function gets the current setting of the interrupt priority masking
442 //! level. The value returned is the priority level such that all interrupts
443 //! of that and lesser priority are masked. A value of 0 means that priority
444 //! masking is disabled.
446 //! Smaller numbers correspond to higher interrupt priorities. So for example
447 //! a priority level mask of 4 allows interrupts of priority level 0-3,
448 //! and interrupts with a numerical priority of 4 and greater are blocked.
450 //! The hardware priority mechanism only looks at the upper N bits of the
451 //! priority level (where N is 3 for the MSP432 family), so any
452 //! prioritization must be performed in those bits.
454 //! \return Returns the value of the interrupt priority level mask.
456 //*****************************************************************************
457 extern uint8_t Interrupt_getPriorityMask(void);
459 //*****************************************************************************
461 //! Sets the address of the vector table. This function is for advanced users
462 //! who might want to switch between multiple instances of vector tables
463 //! (perhaps between flash/ram).
465 //! \param addr is the new address of the vector table.
469 //*****************************************************************************
470 extern void Interrupt_setVectorTableAddress(uint32_t addr);
472 //*****************************************************************************
474 //! Returns the address of the interrupt vector table.
476 //! \return Address of the vector table.
478 //*****************************************************************************
479 extern uint32_t Interrupt_getVectorTableAddress(void);
481 //*****************************************************************************
483 //! Enables the processor to sleep when exiting an ISR. For low power operation,
484 //! this is ideal as power cycles are not wasted with the processing required
485 //! for waking up from an ISR and going back to sleep.
487 //! \return Address of the vector table.
489 //*****************************************************************************
490 extern void Interrupt_enableSleepOnIsrExit(void);
492 //*****************************************************************************
494 //! Enables the processor to sleep when exiting an ISR. For low power operation,
495 //! this is ideal as power cycles are not wasted with the processing required
496 //! for waking up from an ISR and going back to sleep.
498 //! \return Address of the vector table.
500 //*****************************************************************************
501 extern void Interrupt_disableSleepOnIsrExit(void);
503 //*****************************************************************************
505 // Mark the end of the C bindings section for C++ compilers.
507 //*****************************************************************************
512 //*****************************************************************************
514 // Close the Doxygen group.
517 //*****************************************************************************
519 #endif // __INTERRUPT_H__