git.sur5r.net Git - freertos/blob - FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/driverlib/spi.c

   1 /*
   2  * -------------------------------------------
   3  *    MSP432 DriverLib - v01_04_00_18
   4  * -------------------------------------------
   5  *
   6  * --COPYRIGHT--,BSD,BSD
   7  * Copyright (c) 2015, Texas Instruments Incorporated
   8  * All rights reserved.
   9  *
  10  * Redistribution and use in source and binary forms, with or without
  11  * modification, are permitted provided that the following conditions
  12  * are met:
  13  *
  14  * *  Redistributions of source code must retain the above copyright
  15  *    notice, this list of conditions and the following disclaimer.
  16  *
  17  * *  Redistributions in binary form must reproduce the above copyright
  18  *    notice, this list of conditions and the following disclaimer in the
  19  *    documentation and/or other materials provided with the distribution.
  20  *
  21  * *  Neither the name of Texas Instruments Incorporated nor the names of
  22  *    its contributors may be used to endorse or promote products derived
  23  *    from this software without specific prior written permission.
  24  *
  25  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  26  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  27  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  28  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
  29  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  30  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  31  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
  32  * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  33  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
  34  * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
  35  * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  36  * --/COPYRIGHT--*/
  37 #include <spi.h>
  38 #include <interrupt.h>
  39 #include <debug.h>
  40 #include <eusci.h>
  41
  42 static bool is_A_Module(uint32_t module)
  43 {
  44     if (module == EUSCI_A0_MODULE || module == EUSCI_A1_MODULE
  45 #ifdef EUSCI_A2_MODULE
  46             || module == EUSCI_A2_MODULE
  47 #endif
  48 #ifdef EUSCI_A3_MODULE
  49             || module == EUSCI_A3_MODULE
  50 #endif
  51     )
  52         return true;
  53     else
  54         return false;
  55 }
  56
  57 bool SPI_initMaster(uint32_t moduleInstance, const eUSCI_SPI_MasterConfig *config)
  58 {
  59     if (is_A_Module(moduleInstance))
  60     {
  61         ASSERT(
  62                 (EUSCI_A_SPI_CLOCKSOURCE_ACLK == config->selectClockSource)
  63                 || (EUSCI_A_SPI_CLOCKSOURCE_SMCLK
  64                         == config->selectClockSource));
  65
  66         ASSERT(
  67                 (EUSCI_A_SPI_MSB_FIRST == config->msbFirst)
  68                 || (EUSCI_A_SPI_LSB_FIRST == config->msbFirst));
  69
  70         ASSERT(
  71                 (EUSCI_A_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT
  72                         == config->clockPhase)
  73                 || (EUSCI_A_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT
  74                         == config->clockPhase));
  75
  76         ASSERT(
  77                 (EUSCI_A_SPI_CLOCKPOLARITY_INACTIVITY_HIGH
  78                         == config->clockPolarity)
  79                 || (EUSCI_A_SPI_CLOCKPOLARITY_INACTIVITY_LOW
  80                         == config->clockPolarity));
  81
  82         ASSERT(
  83                 (EUSCI_A_SPI_3PIN == config->spiMode)
  84                 || (EUSCI_A_SPI_4PIN_UCxSTE_ACTIVE_HIGH
  85                         == config->spiMode)
  86                 || (EUSCI_A_SPI_4PIN_UCxSTE_ACTIVE_LOW
  87                         == config->spiMode));
  88
  89         //Disable the USCI Module
  90         BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r, UCSWRST_OFS) = 1;
  91
  92         /*
  93          * Configure as SPI master mode.
  94          * Clock phase select, polarity, msb
  95          * UCMST = Master mode
  96          * UCSYNC = Synchronous mode
  97          * UCMODE_0 = 3-pin SPI
  98          */
  99         EUSCI_A_CMSIS(moduleInstance)->rCTLW0.r =
 100                 (EUSCI_A_CMSIS(moduleInstance)->rCTLW0.r
 101                         & ~(UCSSEL_3 + UCCKPH + UCCKPL + UC7BIT + UCMSB + UCMST
 102                                 + UCMODE_3 + UCSYNC))
 103                         | (config->selectClockSource + config->msbFirst
 104                                 + config->clockPhase + config->clockPolarity
 105                                 + UCMST + UCSYNC + config->spiMode);
 106
 107         EUSCI_A_CMSIS(moduleInstance)->rBRW =
 108                 (uint16_t) (config->clockSourceFrequency
 109                         / config->desiredSpiClock);
 110
 111         //No modulation
 112         EUSCI_A_CMSIS(moduleInstance)->rMCTLW.r = 0;
 113
 114         return true;
 115     } else
 116     {
 117         ASSERT(
 118                 (EUSCI_B_SPI_CLOCKSOURCE_ACLK == config->selectClockSource)
 119                 || (EUSCI_B_SPI_CLOCKSOURCE_SMCLK
 120                         == config->selectClockSource));
 121
 122         ASSERT(
 123                 (EUSCI_B_SPI_MSB_FIRST == config->msbFirst)
 124                 || (EUSCI_B_SPI_LSB_FIRST == config->msbFirst));
 125
 126         ASSERT(
 127                 (EUSCI_B_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT
 128                         == config->clockPhase)
 129                 || (EUSCI_B_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT
 130                         == config->clockPhase));
 131
 132         ASSERT(
 133                 (EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_HIGH
 134                         == config->clockPolarity)
 135                 || (EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_LOW
 136                         == config->clockPolarity));
 137
 138         ASSERT(
 139                 (EUSCI_B_SPI_3PIN == config->spiMode)
 140                 || (EUSCI_B_SPI_4PIN_UCxSTE_ACTIVE_HIGH
 141                         == config->spiMode)
 142                 || (EUSCI_B_SPI_4PIN_UCxSTE_ACTIVE_LOW
 143                         == config->spiMode));
 144
 145         //Disable the USCI Module
 146         BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r, UCSWRST_OFS) = 1;
 147
 148         /*
 149          * Configure as SPI master mode.
 150          * Clock phase select, polarity, msb
 151          * UCMST = Master mode
 152          * UCSYNC = Synchronous mode
 153          * UCMODE_0 = 3-pin SPI
 154          */
 155         EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r =
 156                 (EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r
 157                         & ~(UCSSEL_3 + UCCKPH + UCCKPL + UC7BIT + UCMSB + UCMST
 158                                 + UCMODE_3 + UCSYNC))
 159                         | (config->selectClockSource + config->msbFirst
 160                                 + config->clockPhase + config->clockPolarity
 161                                 + UCMST + UCSYNC + config->spiMode);
 162
 163         EUSCI_B_CMSIS(moduleInstance)->rBRW =
 164                 (uint16_t) (config->clockSourceFrequency
 165                         / config->desiredSpiClock);
 166
 167         return true;
 168     }
 169
 170 }
 171
 172 void SPI_selectFourPinFunctionality(uint32_t moduleInstance,
 173         uint_fast8_t select4PinFunctionality)
 174 {
 175     if (is_A_Module(moduleInstance))
 176     {
 177         EUSCI_A_SPI_select4PinFunctionality(moduleInstance,
 178                 select4PinFunctionality);
 179     } else
 180     {
 181         EUSCI_B_SPI_select4PinFunctionality(moduleInstance,
 182                 select4PinFunctionality);
 183     }
 184
 185 }
 186
 187 void SPI_changeMasterClock(uint32_t moduleInstance,
 188         uint32_t clockSourceFrequency, uint32_t desiredSpiClock)
 189 {
 190     if (is_A_Module(moduleInstance))
 191     {
 192         EUSCI_A_SPI_masterChangeClock(moduleInstance, clockSourceFrequency,
 193                 desiredSpiClock);
 194     } else
 195     {
 196         EUSCI_B_SPI_masterChangeClock(moduleInstance, clockSourceFrequency,
 197                 desiredSpiClock);
 198     }
 199
 200 }
 201
 202 bool SPI_initSlave(uint32_t moduleInstance, const eUSCI_SPI_SlaveConfig *config)
 203 {
 204     if (is_A_Module(moduleInstance))
 205     {
 206         ASSERT(
 207                 (EUSCI_A_SPI_MSB_FIRST == config->msbFirst)
 208                 || (EUSCI_A_SPI_LSB_FIRST == config->msbFirst));
 209
 210         ASSERT(
 211                 (EUSCI_A_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT
 212                         == config->clockPhase)
 213                 || (EUSCI_A_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT
 214                         == config->clockPhase));
 215
 216         ASSERT(
 217                 (EUSCI_A_SPI_CLOCKPOLARITY_INACTIVITY_HIGH
 218                         == config->clockPolarity)
 219                 || (EUSCI_A_SPI_CLOCKPOLARITY_INACTIVITY_LOW
 220                         == config->clockPolarity));
 221
 222         ASSERT(
 223                 (EUSCI_A_SPI_3PIN == config->spiMode)
 224                 || (EUSCI_A_SPI_4PIN_UCxSTE_ACTIVE_HIGH
 225                         == config->spiMode)
 226                 || (EUSCI_A_SPI_4PIN_UCxSTE_ACTIVE_LOW
 227                         == config->spiMode));
 228
 229         //Disable USCI Module
 230         BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->rCTLW0.r, UCSWRST_OFS) = 1;
 231
 232         //Reset OFS_UCAxCTLW0 register
 233         EUSCI_A_CMSIS(moduleInstance)->rCTLW0.r =
 234                 (EUSCI_A_CMSIS(moduleInstance)->rCTLW0.r
 235                         & ~(UCMSB + UC7BIT + UCMST + UCCKPL + UCCKPH + UCMODE_3))
 236                         | (config->clockPhase + config->clockPolarity
 237                                 + config->msbFirst + UCSYNC + config->spiMode);
 238
 239         return true;
 240     } else
 241     {
 242         ASSERT(
 243                 (EUSCI_B_SPI_MSB_FIRST == config->msbFirst)
 244                 || (EUSCI_B_SPI_LSB_FIRST == config->msbFirst));
 245
 246         ASSERT(
 247                 (EUSCI_B_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT
 248                         == config->clockPhase)
 249                 || (EUSCI_B_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT
 250                         == config->clockPhase));
 251
 252         ASSERT(
 253                 (EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_HIGH
 254                         == config->clockPolarity)
 255                 || (EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_LOW
 256                         == config->clockPolarity));
 257
 258         ASSERT(
 259                 (EUSCI_B_SPI_3PIN == config->spiMode)
 260                 || (EUSCI_B_SPI_4PIN_UCxSTE_ACTIVE_HIGH
 261                         == config->spiMode)
 262                 || (EUSCI_B_SPI_4PIN_UCxSTE_ACTIVE_LOW
 263                         == config->spiMode));
 264
 265         //Disable USCI Module
 266         BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r, UCSWRST_OFS) = 1;
 267
 268         //Reset OFS_UCBxCTLW0 register
 269         EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r =
 270                 (EUSCI_B_CMSIS(moduleInstance)->rCTLW0.r
 271                         & ~(UCMSB + UC7BIT + UCMST + UCCKPL + UCCKPH + UCMODE_3))
 272                         | (config->clockPhase + config->clockPolarity
 273                                 + config->msbFirst + UCSYNC + config->spiMode);
 274
 275         return true;
 276     }
 277
 278 }
 279
 280 void SPI_changeClockPhasePolarity(uint32_t moduleInstance,
 281         uint_fast16_t clockPhase, uint_fast16_t clockPolarity)
 282 {
 283     if (is_A_Module(moduleInstance))
 284     {
 285         EUSCI_A_SPI_changeClockPhasePolarity(moduleInstance, clockPhase,
 286                 clockPolarity);
 287     } else
 288     {
 289         EUSCI_B_SPI_changeClockPhasePolarity(moduleInstance, clockPhase,
 290                 clockPolarity);
 291     }
 292
 293 }
 294
 295 void SPI_transmitData(uint32_t moduleInstance, uint_fast8_t transmitData)
 296 {
 297     if (is_A_Module(moduleInstance))
 298     {
 299         EUSCI_A_SPI_transmitData(moduleInstance, transmitData);
 300     } else
 301     {
 302         EUSCI_B_SPI_transmitData(moduleInstance, transmitData);
 303     }
 304
 305 }
 306
 307 uint8_t SPI_receiveData(uint32_t moduleInstance)
 308 {
 309     if (is_A_Module(moduleInstance))
 310     {
 311         return EUSCI_A_SPI_receiveData(moduleInstance);
 312     } else
 313     {
 314         return EUSCI_B_SPI_receiveData(moduleInstance);
 315     }
 316
 317 }
 318
 319 void SPI_enableModule(uint32_t moduleInstance)
 320 {
 321     if (is_A_Module(moduleInstance))
 322     {
 323         EUSCI_A_SPI_enable(moduleInstance);
 324     } else
 325     {
 326         EUSCI_B_SPI_enable(moduleInstance);
 327     }
 328
 329 }
 330
 331 void SPI_disableModule(uint32_t moduleInstance)
 332 {
 333     if (is_A_Module(moduleInstance))
 334     {
 335         EUSCI_A_SPI_disable(moduleInstance);
 336     } else
 337     {
 338         EUSCI_B_SPI_disable(moduleInstance);
 339     }
 340
 341 }
 342
 343 uint32_t SPI_getReceiveBufferAddressForDMA(uint32_t moduleInstance)
 344 {
 345     if (is_A_Module(moduleInstance))
 346     {
 347         return EUSCI_A_SPI_getReceiveBufferAddressForDMA(moduleInstance);
 348     } else
 349     {
 350         return EUSCI_B_SPI_getReceiveBufferAddressForDMA(moduleInstance);
 351     }
 352
 353 }
 354
 355 uint32_t SPI_getTransmitBufferAddressForDMA(uint32_t moduleInstance)
 356 {
 357     if (is_A_Module(moduleInstance))
 358     {
 359         return EUSCI_A_SPI_getTransmitBufferAddressForDMA(moduleInstance);
 360     } else
 361     {
 362         return EUSCI_B_SPI_getTransmitBufferAddressForDMA(moduleInstance);
 363     }
 364
 365 }
 366
 367 uint_fast8_t SPI_isBusy(uint32_t moduleInstance)
 368 {
 369     if (is_A_Module(moduleInstance))
 370     {
 371         return EUSCI_A_SPI_isBusy(moduleInstance);
 372     } else
 373     {
 374         return EUSCI_B_SPI_isBusy(moduleInstance);
 375     }
 376
 377 }
 378
 379 void SPI_enableInterrupt(uint32_t moduleInstance, uint_fast8_t mask)
 380 {
 381     if (is_A_Module(moduleInstance))
 382     {
 383         EUSCI_A_SPI_enableInterrupt(moduleInstance, mask);
 384     } else
 385     {
 386         EUSCI_B_SPI_enableInterrupt(moduleInstance, mask);
 387     }
 388
 389 }
 390
 391 void SPI_disableInterrupt(uint32_t moduleInstance, uint_fast8_t mask)
 392 {
 393     if (is_A_Module(moduleInstance))
 394     {
 395         EUSCI_A_SPI_disableInterrupt(moduleInstance, mask);
 396     } else
 397     {
 398         EUSCI_B_SPI_disableInterrupt(moduleInstance, mask);
 399     }
 400
 401 }
 402
 403 uint_fast8_t SPI_getInterruptStatus(uint32_t moduleInstance, uint16_t mask)
 404 {
 405     if (is_A_Module(moduleInstance))
 406     {
 407         return EUSCI_A_SPI_getInterruptStatus(moduleInstance, mask);
 408     } else
 409     {
 410         return EUSCI_B_SPI_getInterruptStatus(moduleInstance, mask);
 411     }
 412
 413 }
 414
 415 uint_fast8_t SPI_getEnabledInterruptStatus(uint32_t moduleInstance)
 416 {
 417     if (is_A_Module(moduleInstance))
 418     {
 419         return SPI_getInterruptStatus(moduleInstance,
 420                 EUSCI_SPI_TRANSMIT_INTERRUPT | EUSCI_SPI_RECEIVE_INTERRUPT)
 421                 & HWREG16(moduleInstance + OFS_UCA0IE);
 422     } else
 423     {
 424         return SPI_getInterruptStatus(moduleInstance,
 425                 EUSCI_SPI_TRANSMIT_INTERRUPT | EUSCI_SPI_RECEIVE_INTERRUPT)
 426                 & HWREG16(moduleInstance + OFS_UCB0IE);
 427
 428     }
 429 }
 430
 431 void SPI_clearInterruptFlag(uint32_t moduleInstance, uint_fast8_t mask)
 432 {
 433     if (is_A_Module(moduleInstance))
 434     {
 435         EUSCI_A_SPI_clearInterruptFlag(moduleInstance, mask);
 436     } else
 437     {
 438         EUSCI_B_SPI_clearInterruptFlag(moduleInstance, mask);
 439     }
 440
 441 }
 442
 443 void SPI_registerInterrupt(uint32_t moduleInstance, void (*intHandler)(void))
 444 {
 445     switch (moduleInstance)
 446     {
 447     case EUSCI_A0_MODULE:
 448         Interrupt_registerInterrupt(INT_EUSCIA0, intHandler);
 449         Interrupt_enableInterrupt(INT_EUSCIA0);
 450         break;
 451     case EUSCI_A1_MODULE:
 452         Interrupt_registerInterrupt(INT_EUSCIA1, intHandler);
 453         Interrupt_enableInterrupt(INT_EUSCIA1);
 454         break;
 455 #ifdef EUSCI_A2_MODULE
 456     case EUSCI_A2_MODULE:
 457         Interrupt_registerInterrupt(INT_EUSCIA2, intHandler);
 458         Interrupt_enableInterrupt(INT_EUSCIA2);
 459         break;
 460 #endif
 461 #ifdef EUSCI_A3_MODULE
 462     case EUSCI_A3_MODULE:
 463         Interrupt_registerInterrupt(INT_EUSCIA3, intHandler);
 464         Interrupt_enableInterrupt(INT_EUSCIA3);
 465         break;
 466 #endif
 467     case EUSCI_B0_MODULE:
 468         Interrupt_registerInterrupt(INT_EUSCIB0, intHandler);
 469         Interrupt_enableInterrupt(INT_EUSCIB0);
 470         break;
 471     case EUSCI_B1_MODULE:
 472         Interrupt_registerInterrupt(INT_EUSCIB1, intHandler);
 473         Interrupt_enableInterrupt(INT_EUSCIB1);
 474         break;
 475 #ifdef EUSCI_B2_MODULE
 476     case EUSCI_B2_MODULE:
 477         Interrupt_registerInterrupt(INT_EUSCIB2, intHandler);
 478         Interrupt_enableInterrupt(INT_EUSCIB2);
 479         break;
 480 #endif
 481 #ifdef EUSCI_B3_MODULE
 482     case EUSCI_B3_MODULE:
 483         Interrupt_registerInterrupt(INT_EUSCIB3, intHandler);
 484         Interrupt_enableInterrupt(INT_EUSCIB3);
 485         break;
 486 #endif
 487     default:
 488         ASSERT(false);
 489     }
 490 }
 491
 492 void SPI_unregisterInterrupt(uint32_t moduleInstance)
 493 {
 494     switch (moduleInstance)
 495     {
 496     case EUSCI_A0_MODULE:
 497         Interrupt_disableInterrupt(INT_EUSCIA0);
 498         Interrupt_unregisterInterrupt(INT_EUSCIA0);
 499         break;
 500     case EUSCI_A1_MODULE:
 501         Interrupt_disableInterrupt(INT_EUSCIA1);
 502         Interrupt_unregisterInterrupt(INT_EUSCIA1);
 503         break;
 504 #ifdef EUSCI_A2_MODULE
 505     case EUSCI_A2_MODULE:
 506         Interrupt_disableInterrupt(INT_EUSCIA2);
 507         Interrupt_unregisterInterrupt(INT_EUSCIA2);
 508         break;
 509 #endif
 510 #ifdef EUSCI_A3_MODULE
 511     case EUSCI_A3_MODULE:
 512         Interrupt_disableInterrupt(INT_EUSCIA3);
 513         Interrupt_unregisterInterrupt(INT_EUSCIA3);
 514         break;
 515 #endif
 516     case EUSCI_B0_MODULE:
 517         Interrupt_disableInterrupt(INT_EUSCIB0);
 518         Interrupt_unregisterInterrupt(INT_EUSCIB0);
 519         break;
 520     case EUSCI_B1_MODULE:
 521         Interrupt_disableInterrupt(INT_EUSCIB1);
 522         Interrupt_unregisterInterrupt(INT_EUSCIB1);
 523         break;
 524 #ifdef EUSCI_B2_MODULE
 525     case EUSCI_B2_MODULE:
 526         Interrupt_disableInterrupt(INT_EUSCIB2);
 527         Interrupt_unregisterInterrupt(INT_EUSCIB2);
 528         break;
 529 #endif
 530 #ifdef EUSCI_B3_MODULE
 531     case EUSCI_B3_MODULE:
 532         Interrupt_disableInterrupt(INT_EUSCIB3);
 533         Interrupt_unregisterInterrupt(INT_EUSCIB3);
 534         break;
 535 #endif
 536     default:
 537         ASSERT(false);
 538     }
 539
 540 }
 541
 542 /* Backwards Compatibility Layer */
 543
 544 //*****************************************************************************
 545 //
 546 //! \brief Selects 4Pin Functionality
 547 //!
 548 //! This function should be invoked only in 4-wire mode. Invoking this function
 549 //! has no effect in 3-wire mode.
 550 //!
 551 //! \param baseAddress is the base address of the EUSCI_B_SPI module.
 552 //! \param select4PinFunctionality selects 4 pin functionality
 553 //!        Valid values are:
 554 //!        - \b EUSCI_B_SPI_PREVENT_CONFLICTS_WITH_OTHER_MASTERS
 555 //!        - \b EUSCI_B_SPI_ENABLE_SIGNAL_FOR_4WIRE_SLAVE
 556 //!
 557 //! Modified bits are \b UCSTEM of \b UCAxCTLW0 register.
 558 //!
 559 //! \return None
 560 //
 561 //*****************************************************************************
 562 void EUSCI_B_SPI_select4PinFunctionality(uint32_t baseAddress,
 563         uint8_t select4PinFunctionality)
 564 {
 565     ASSERT(
 566             (EUSCI_B_SPI_PREVENT_CONFLICTS_WITH_OTHER_MASTERS
 567                     == select4PinFunctionality)
 568             || (EUSCI_B_SPI_ENABLE_SIGNAL_FOR_4WIRE_SLAVE
 569                     == select4PinFunctionality));
 570
 571     EUSCI_B_CMSIS(baseAddress)->rCTLW0.r = (EUSCI_B_CMSIS(baseAddress)->rCTLW0.r
 572             & ~UCSTEM) | select4PinFunctionality;
 573 }
 574
 575 //*****************************************************************************
 576 //
 577 //! \brief Initializes the SPI Master clock. At the end of this function call,
 578 //! SPI module is left enabled.
 579 //!
 580 //! \param baseAddress is the base address of the EUSCI_B_SPI module.
 581 //! \param clockSourceFrequency is the frequency of the slected clock source
 582 //! \param desiredSpiClock is the desired clock rate for SPI communication
 583 //!
 584 //! Modified bits are \b UCSWRST of \b UCAxCTLW0 register.
 585 //!
 586 //! \return None
 587 //
 588 //*****************************************************************************
 589 void EUSCI_B_SPI_masterChangeClock(uint32_t baseAddress,
 590         uint32_t clockSourceFrequency, uint32_t desiredSpiClock)
 591 {
 592     //Disable the USCI Module
 593     BITBAND_PERI(EUSCI_B_CMSIS(baseAddress)->rCTLW0.r, UCSWRST_OFS) = 1;
 594
 595     EUSCI_B_CMSIS(baseAddress)->rBRW = (uint16_t) (clockSourceFrequency
 596             / desiredSpiClock);
 597
 598     //Reset the UCSWRST bit to enable the USCI Module
 599     BITBAND_PERI(EUSCI_B_CMSIS(baseAddress)->rCTLW0.r, UCSWRST_OFS) = 0;
 600 }
 601
 602 //*****************************************************************************
 603 //
 604 //! \brief Initializes the SPI Slave block.
 605 //!
 606 //! Upon successful initialization of the SPI slave block, this function will
 607 //! have initailized the slave block, but the SPI Slave block still remains
 608 //! disabled and must be enabled with EUSCI_B_SPI_enable()
 609 //!
 610 //! \param baseAddress is the base address of the EUSCI_B_SPI Slave module.
 611 //! \param msbFirst controls the direction of the receive and transmit shift
 612 //!        register.
 613 //!        Valid values are:
 614 //!        - \b EUSCI_B_SPI_MSB_FIRST
 615 //!        - \b EUSCI_B_SPI_LSB_FIRST [Default]
 616 //! \param clockPhase is clock phase select.
 617 //!        Valid values are:
 618 //!        - \b EUSCI_B_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT
 619 //!           [Default]
 620 //!        - \b EUSCI_B_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT
 621 //! \param clockPolarity is clock polarity select
 622 //!        Valid values are:
 623 //!        - \b EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_HIGH
 624 //!        - \b EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_LOW [Default]
 625 //! \param spiMode is SPI mode select
 626 //!        Valid values are:
 627 //!        - \b EUSCI_B_SPI_3PIN
 628 //!        - \b EUSCI_B_SPI_4PIN_UCxSTE_ACTIVE_HIGH
 629 //!        - \b EUSCI_B_SPI_4PIN_UCxSTE_ACTIVE_LOW
 630 //!
 631 //! Modified bits are \b UCMSB, \b UCMST, \b UC7BIT, \b UCCKPL, \b UCCKPH, \b
 632 //! UCMODE and \b UCSWRST of \b UCAxCTLW0 register.
 633 //!
 634 //! \return STATUS_SUCCESS
 635 //
 636 //*****************************************************************************
 637 bool EUSCI_B_SPI_slaveInit(uint32_t baseAddress, uint16_t msbFirst,
 638         uint16_t clockPhase, uint16_t clockPolarity, uint16_t spiMode)
 639 {
 640     ASSERT(
 641             (EUSCI_B_SPI_MSB_FIRST == msbFirst)
 642             || (EUSCI_B_SPI_LSB_FIRST == msbFirst));
 643
 644     ASSERT(
 645             (EUSCI_B_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT
 646                     == clockPhase)
 647             || (EUSCI_B_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT
 648                     == clockPhase));
 649
 650     ASSERT(
 651             (EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_HIGH == clockPolarity)
 652             || (EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_LOW
 653                     == clockPolarity));
 654
 655     ASSERT(
 656             (EUSCI_B_SPI_3PIN == spiMode)
 657             || (EUSCI_B_SPI_4PIN_UCxSTE_ACTIVE_HIGH == spiMode)
 658             || (EUSCI_B_SPI_4PIN_UCxSTE_ACTIVE_LOW == spiMode));
 659
 660     //Disable USCI Module
 661     BITBAND_PERI(EUSCI_B_CMSIS(baseAddress)->rCTLW0.r, UCSWRST_OFS) = 1;
 662
 663     //Reset OFS_UCBxCTLW0 register
 664     EUSCI_B_CMSIS(baseAddress)->rCTLW0.r = (EUSCI_B_CMSIS(baseAddress)->rCTLW0.r
 665             & ~(UCMSB + UC7BIT + UCMST + UCCKPL + UCCKPH + UCMODE_3))
 666             | (clockPhase + clockPolarity + msbFirst + UCSYNC + spiMode);
 667
 668     return true;
 669 }
 670
 671 //*****************************************************************************
 672 //
 673 //! \brief Changes the SPI colock phase and polarity. At the end of this
 674 //! function call, SPI module is left enabled.
 675 //!
 676 //! \param baseAddress is the base address of the EUSCI_B_SPI module.
 677 //! \param clockPhase is clock phase select.
 678 //!        Valid values are:
 679 //!        - \b EUSCI_B_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT
 680 //!           [Default]
 681 //!        - \b EUSCI_B_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT
 682 //! \param clockPolarity is clock polarity select
 683 //!        Valid values are:
 684 //!        - \b EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_HIGH
 685 //!        - \b EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_LOW [Default]
 686 //!
 687 //! Modified bits are \b UCCKPL, \b UCCKPH and \b UCSWRST of \b UCAxCTLW0
 688 //! register.
 689 //!
 690 //! \return None
 691 //
 692 //*****************************************************************************
 693 void EUSCI_B_SPI_changeClockPhasePolarity(uint32_t baseAddress,
 694         uint16_t clockPhase, uint16_t clockPolarity)
 695 {
 696
 697     ASSERT(
 698             (EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_HIGH == clockPolarity)
 699             || (EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_LOW
 700                     == clockPolarity));
 701
 702     ASSERT(
 703             (EUSCI_B_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT
 704                     == clockPhase)
 705             || (EUSCI_B_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT
 706                     == clockPhase));
 707
 708     //Disable the USCI Module
 709     BITBAND_PERI(EUSCI_B_CMSIS(baseAddress)->rCTLW0.r, UCSWRST_OFS) = 1;
 710
 711     EUSCI_B_CMSIS(baseAddress)->rCTLW0.r = (EUSCI_B_CMSIS(baseAddress)->rCTLW0.r
 712             & ~(UCCKPH + UCCKPL)) | (clockPhase + clockPolarity);
 713
 714     //Reset the UCSWRST bit to enable the USCI Module
 715     BITBAND_PERI(EUSCI_B_CMSIS(baseAddress)->rCTLW0.r, UCSWRST_OFS) = 0;
 716 }
 717
 718 //*****************************************************************************
 719 //
 720 //! \brief Transmits a byte from the SPI Module.
 721 //!
 722 //! This function will place the supplied data into SPI trasmit data register
 723 //! to start transmission.
 724 //!
 725 //! \param baseAddress is the base address of the EUSCI_B_SPI module.
 726 //! \param transmitData data to be transmitted from the SPI module
 727 //!
 728 //! \return None
 729 //
 730 //*****************************************************************************
 731 void EUSCI_B_SPI_transmitData(uint32_t baseAddress, uint8_t transmitData)
 732 {
 733     EUSCI_B_CMSIS(baseAddress)->rTXBUF.r = transmitData;
 734 }
 735
 736 //*****************************************************************************
 737 //
 738 //! \brief Receives a byte that has been sent to the SPI Module.
 739 //!
 740 //! This function reads a byte of data from the SPI receive data Register.
 741 //!
 742 //! \param baseAddress is the base address of the EUSCI_B_SPI module.
 743 //!
 744 //! \return Returns the byte received from by the SPI module, cast as an
 745 //!         uint8_t.
 746 //
 747 //*****************************************************************************
 748 uint8_t EUSCI_B_SPI_receiveData(uint32_t baseAddress)
 749 {
 750     return EUSCI_B_CMSIS(baseAddress)->rRXBUF.r;
 751 }
 752
 753 //*****************************************************************************
 754 //
 755 //! \brief Enables individual SPI interrupt sources.
 756 //!
 757 //! Enables the indicated SPI interrupt sources.  Only the sources that are
 758 //! enabled can be reflected to the processor interrupt; disabled sources have
 759 //! no effect on the processor. Does not clear interrupt flags.
 760 //!
 761 //! \param baseAddress is the base address of the EUSCI_B_SPI module.
 762 //! \param mask is the bit mask of the interrupt sources to be enabled.
 763 //!        Mask value is the logical OR of any of the following:
 764 //!        - \b EUSCI_B_SPI_TRANSMIT_INTERRUPT
 765 //!        - \b EUSCI_B_SPI_RECEIVE_INTERRUPT
 766 //!
 767 //! Modified bits of \b UCAxIFG register and bits of \b UCAxIE register.
 768 //!
 769 //! \return None
 770 //
 771 //*****************************************************************************
 772 void EUSCI_B_SPI_enableInterrupt(uint32_t baseAddress, uint8_t mask)
 773 {
 774     ASSERT(
 775             !(mask
 776                     & ~(EUSCI_B_SPI_RECEIVE_INTERRUPT
 777                             | EUSCI_B_SPI_TRANSMIT_INTERRUPT)));
 778
 779     EUSCI_B_CMSIS(baseAddress)->rIE.r |= mask;
 780 }
 781
 782 //*****************************************************************************
 783 //
 784 //! \brief Disables individual SPI interrupt sources.
 785 //!
 786 //! Disables the indicated SPI interrupt sources. Only the sources that are
 787 //! enabled can be reflected to the processor interrupt; disabled sources have
 788 //! no effect on the processor.
 789 //!
 790 //! \param baseAddress is the base address of the EUSCI_B_SPI module.
 791 //! \param mask is the bit mask of the interrupt sources to be disabled.
 792 //!        Mask value is the logical OR of any of the following:
 793 //!        - \b EUSCI_B_SPI_TRANSMIT_INTERRUPT
 794 //!        - \b EUSCI_B_SPI_RECEIVE_INTERRUPT
 795 //!
 796 //! Modified bits of \b UCAxIE register.
 797 //!
 798 //! \return None
 799 //
 800 //*****************************************************************************
 801 void EUSCI_B_SPI_disableInterrupt(uint32_t baseAddress, uint8_t mask)
 802 {
 803     ASSERT(
 804             !(mask
 805                     & ~(EUSCI_B_SPI_RECEIVE_INTERRUPT
 806                             | EUSCI_B_SPI_TRANSMIT_INTERRUPT)));
 807
 808     EUSCI_B_CMSIS(baseAddress)->rIE.r &= ~mask;
 809 }
 810
 811 //*****************************************************************************
 812 //
 813 //! \brief Gets the current SPI interrupt status.
 814 //!
 815 //! This returns the interrupt status for the SPI module based on which flag is
 816 //! passed.
 817 //!
 818 //! \param baseAddress is the base address of the EUSCI_B_SPI module.
 819 //! \param mask is the masked interrupt flag status to be returned.
 820 //!        Mask value is the logical OR of any of the following:
 821 //!        - \b EUSCI_B_SPI_TRANSMIT_INTERRUPT
 822 //!        - \b EUSCI_B_SPI_RECEIVE_INTERRUPT
 823 //!
 824 //! \return Logical OR of any of the following:
 825 //!         - \b EUSCI_B_SPI_TRANSMIT_INTERRUPT
 826 //!         - \b EUSCI_B_SPI_RECEIVE_INTERRUPT
 827 //!         \n indicating the status of the masked interrupts
 828 //
 829 //*****************************************************************************
 830 uint8_t EUSCI_B_SPI_getInterruptStatus(uint32_t baseAddress, uint8_t mask)
 831 {
 832     ASSERT(
 833             !(mask
 834                     & ~(EUSCI_B_SPI_RECEIVE_INTERRUPT
 835                             | EUSCI_B_SPI_TRANSMIT_INTERRUPT)));
 836
 837     return EUSCI_B_CMSIS(baseAddress)->rIFG.r & mask;
 838 }
 839
 840 //*****************************************************************************
 841 //
 842 //! \brief Clears the selected SPI interrupt status flag.
 843 //!
 844 //! \param baseAddress is the base address of the EUSCI_B_SPI module.
 845 //! \param mask is the masked interrupt flag to be cleared.
 846 //!        Mask value is the logical OR of any of the following:
 847 //!        - \b EUSCI_B_SPI_TRANSMIT_INTERRUPT
 848 //!        - \b EUSCI_B_SPI_RECEIVE_INTERRUPT
 849 //!
 850 //! Modified bits of \b UCAxIFG register.
 851 //!
 852 //! \return None
 853 //
 854 //*****************************************************************************
 855 void EUSCI_B_SPI_clearInterruptFlag(uint32_t baseAddress, uint8_t mask)
 856 {
 857     ASSERT(
 858             !(mask
 859                     & ~(EUSCI_B_SPI_RECEIVE_INTERRUPT
 860                             | EUSCI_B_SPI_TRANSMIT_INTERRUPT)));
 861
 862     EUSCI_B_CMSIS(baseAddress)->rIFG.r &= ~mask;
 863 }
 864
 865 //*****************************************************************************
 866 //
 867 //! \brief Enables the SPI block.
 868 //!
 869 //! This will enable operation of the SPI block.
 870 //!
 871 //! \param baseAddress is the base address of the EUSCI_B_SPI module.
 872 //!
 873 //! Modified bits are \b UCSWRST of \b UCBxCTLW0 register.
 874 //!
 875 //! \return None
 876 //
 877 //*****************************************************************************
 878 void EUSCI_B_SPI_enable(uint32_t baseAddress)
 879 {
 880     //Reset the UCSWRST bit to enable the USCI Module
 881     BITBAND_PERI(EUSCI_B_CMSIS(baseAddress)->rCTLW0.r, UCSWRST_OFS) = 0;
 882 }
 883
 884 //*****************************************************************************
 885 //
 886 //! \brief Disables the SPI block.
 887 //!
 888 //! This will disable operation of the SPI block.
 889 //!
 890 //! \param baseAddress is the base address of the EUSCI_B_SPI module.
 891 //!
 892 //! Modified bits are \b UCSWRST of \b UCBxCTLW0 register.
 893 //!
 894 //! \return None
 895 //
 896 //*****************************************************************************
 897 void EUSCI_B_SPI_disable(uint32_t baseAddress)
 898 {
 899     //Set the UCSWRST bit to disable the USCI Module
 900     BITBAND_PERI(EUSCI_B_CMSIS(baseAddress)->rCTLW0.r, UCSWRST_OFS) = 1;
 901 }
 902
 903 //*****************************************************************************
 904 //
 905 //! \brief Returns the address of the RX Buffer of the SPI for the DMA module.
 906 //!
 907 //! Returns the address of the SPI RX Buffer. This can be used in conjunction
 908 //! with the DMA to store the received data directly to memory.
 909 //!
 910 //! \param baseAddress is the base address of the EUSCI_B_SPI module.
 911 //!
 912 //! \return the address of the RX Buffer
 913 //
 914 //*****************************************************************************
 915 uint32_t EUSCI_B_SPI_getReceiveBufferAddressForDMA(uint32_t baseAddress)
 916 {
 917     return baseAddress + OFS_UCB0RXBUF;
 918 }
 919
 920 //*****************************************************************************
 921 //
 922 //! \brief Returns the address of the TX Buffer of the SPI for the DMA module.
 923 //!
 924 //! Returns the address of the SPI TX Buffer. This can be used in conjunction
 925 //! with the DMA to obtain transmitted data directly from memory.
 926 //!
 927 //! \param baseAddress is the base address of the EUSCI_B_SPI module.
 928 //!
 929 //! \return the address of the TX Buffer
 930 //
 931 //*****************************************************************************
 932 uint32_t EUSCI_B_SPI_getTransmitBufferAddressForDMA(uint32_t baseAddress)
 933 {
 934     return baseAddress + OFS_UCB0TXBUF;
 935 }
 936
 937 //*****************************************************************************
 938 //
 939 //! \brief Indicates whether or not the SPI bus is busy.
 940 //!
 941 //! This function returns an indication of whether or not the SPI bus is
 942 //! busy.This function checks the status of the bus via UCBBUSY bit
 943 //!
 944 //! \param baseAddress is the base address of the EUSCI_B_SPI module.
 945 //!
 946 //! \return true if busy, false otherwise
 947 //
 948 //*****************************************************************************
 949 bool EUSCI_B_SPI_isBusy(uint32_t baseAddress)
 950 {
 951     //Return the bus busy status.
 952     return BITBAND_PERI(EUSCI_B_CMSIS(baseAddress)->rSTATW.r, UCBBUSY_OFS);
 953 }
 954
 955 //*****************************************************************************
 956 //
 957 //! \brief Selects 4Pin Functionality
 958 //!
 959 //! This function should be invoked only in 4-wire mode. Invoking this function
 960 //! has no effect in 3-wire mode.
 961 //!
 962 //! \param baseAddress is the base address of the EUSCI_A_SPI module.
 963 //! \param select4PinFunctionality selects 4 pin functionality
 964 //!        Valid values are:
 965 //!        - \b EUSCI_A_SPI_PREVENT_CONFLICTS_WITH_OTHER_MASTERS
 966 //!        - \b EUSCI_A_SPI_ENABLE_SIGNAL_FOR_4WIRE_SLAVE
 967 //!
 968 //! Modified bits are \b UCSTEM of \b UCAxCTLW0 register.
 969 //!
 970 //! \return None
 971 //
 972 //*****************************************************************************
 973 void EUSCI_A_SPI_select4PinFunctionality(uint32_t baseAddress,
 974         uint8_t select4PinFunctionality)
 975 {
 976     ASSERT(
 977             (EUSCI_A_SPI_PREVENT_CONFLICTS_WITH_OTHER_MASTERS
 978                     == select4PinFunctionality)
 979             || (EUSCI_A_SPI_ENABLE_SIGNAL_FOR_4WIRE_SLAVE
 980                     == select4PinFunctionality));
 981
 982     EUSCI_A_CMSIS(baseAddress)->rCTLW0.r = (EUSCI_A_CMSIS(baseAddress)->rCTLW0.r
 983             & ~UCSTEM) | select4PinFunctionality;
 984 }
 985
 986 //*****************************************************************************
 987 //
 988 //! \brief Initializes the SPI Master clock. At the end of this function call,
 989 //! SPI module is left enabled.
 990 //!
 991 //! \param baseAddress is the base address of the EUSCI_A_SPI module.
 992 //! \param clockSourceFrequency is the frequency of the slected clock source
 993 //! \param desiredSpiClock is the desired clock rate for SPI communication
 994 //!
 995 //! Modified bits are \b UCSWRST of \b UCAxCTLW0 register.
 996 //!
 997 //! \return None
 998 //
 999 //*****************************************************************************
1000 void EUSCI_A_SPI_masterChangeClock(uint32_t baseAddress,
1001         uint32_t clockSourceFrequency, uint32_t desiredSpiClock)
1002 {
1003     //Disable the USCI Module
1004     BITBAND_PERI(EUSCI_A_CMSIS(baseAddress)->rCTLW0.r, UCSWRST_OFS) = 1;
1005
1006     EUSCI_A_CMSIS(baseAddress)->rBRW = (uint16_t) (clockSourceFrequency
1007             / desiredSpiClock);
1008
1009     //Reset the UCSWRST bit to enable the USCI Module
1010     BITBAND_PERI(EUSCI_A_CMSIS(baseAddress)->rCTLW0.r, UCSWRST_OFS) = 0;
1011 }
1012
1013 //*****************************************************************************
1014 //
1015 //! \brief Initializes the SPI Slave block.
1016 //!
1017 //! Upon successful initialization of the SPI slave block, this function will
1018 //! have initailized the slave block, but the SPI Slave block still remains
1019 //! disabled and must be enabled with EUSCI_A_SPI_enable()
1020 //!
1021 //! \param baseAddress is the base address of the EUSCI_A_SPI Slave module.
1022 //! \param msbFirst controls the direction of the receive and transmit shift
1023 //!        register.
1024 //!        Valid values are:
1025 //!        - \b EUSCI_A_SPI_MSB_FIRST
1026 //!        - \b EUSCI_A_SPI_LSB_FIRST [Default]
1027 //! \param clockPhase is clock phase select.
1028 //!        Valid values are:
1029 //!        - \b EUSCI_A_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT
1030 //!           [Default]
1031 //!        - \b EUSCI_A_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT
1032 //! \param clockPolarity is clock polarity select
1033 //!        Valid values are:
1034 //!        - \b EUSCI_A_SPI_CLOCKPOLARITY_INACTIVITY_HIGH
1035 //!        - \b EUSCI_A_SPI_CLOCKPOLARITY_INACTIVITY_LOW [Default]
1036 //! \param spiMode is SPI mode select
1037 //!        Valid values are:
1038 //!        - \b EUSCI_A_SPI_3PIN
1039 //!        - \b EUSCI_A_SPI_4PIN_UCxSTE_ACTIVE_HIGH
1040 //!        - \b EUSCI_A_SPI_4PIN_UCxSTE_ACTIVE_LOW
1041 //!
1042 //! Modified bits are \b UCMSB, \b UCMST, \b UC7BIT, \b UCCKPL, \b UCCKPH, \b
1043 //! UCMODE and \b UCSWRST of \b UCAxCTLW0 register.
1044 //!
1045 //! \return STATUS_SUCCESS
1046 //
1047 //*****************************************************************************
1048 bool EUSCI_A_SPI_slaveInit(uint32_t baseAddress, uint16_t msbFirst,
1049         uint16_t clockPhase, uint16_t clockPolarity, uint16_t spiMode)
1050 {
1051     ASSERT(
1052             (EUSCI_A_SPI_MSB_FIRST == msbFirst)
1053             || (EUSCI_A_SPI_LSB_FIRST == msbFirst));
1054
1055     ASSERT(
1056             (EUSCI_A_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT
1057                     == clockPhase)
1058             || (EUSCI_A_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT
1059                     == clockPhase));
1060
1061     ASSERT(
1062             (EUSCI_A_SPI_CLOCKPOLARITY_INACTIVITY_HIGH == clockPolarity)
1063             || (EUSCI_A_SPI_CLOCKPOLARITY_INACTIVITY_LOW
1064                     == clockPolarity));
1065
1066     ASSERT(
1067             (EUSCI_A_SPI_3PIN == spiMode)
1068             || (EUSCI_A_SPI_4PIN_UCxSTE_ACTIVE_HIGH == spiMode)
1069             || (EUSCI_A_SPI_4PIN_UCxSTE_ACTIVE_LOW == spiMode));
1070
1071     //Disable USCI Module
1072     BITBAND_PERI(EUSCI_A_CMSIS(baseAddress)->rCTLW0.r, UCSWRST_OFS) = 1;
1073
1074     //Reset OFS_UCAxCTLW0 register
1075     EUSCI_A_CMSIS(baseAddress)->rCTLW0.r = (EUSCI_A_CMSIS(baseAddress)->rCTLW0.r
1076             & ~(UCMSB + UC7BIT + UCMST + UCCKPL + UCCKPH + UCMODE_3))
1077             | (clockPhase + clockPolarity + msbFirst + UCSYNC + spiMode);
1078
1079     return true;
1080 }
1081
1082 //*****************************************************************************
1083 //
1084 //! \brief Changes the SPI colock phase and polarity. At the end of this
1085 //! function call, SPI module is left enabled.
1086 //!
1087 //! \param baseAddress is the base address of the EUSCI_A_SPI module.
1088 //! \param clockPhase is clock phase select.
1089 //!        Valid values are:
1090 //!        - \b EUSCI_A_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT
1091 //!           [Default]
1092 //!        - \b EUSCI_A_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT
1093 //! \param clockPolarity is clock polarity select
1094 //!        Valid values are:
1095 //!        - \b EUSCI_A_SPI_CLOCKPOLARITY_INACTIVITY_HIGH
1096 //!        - \b EUSCI_A_SPI_CLOCKPOLARITY_INACTIVITY_LOW [Default]
1097 //!
1098 //! Modified bits are \b UCCKPL, \b UCCKPH and \b UCSWRST of \b UCAxCTLW0
1099 //! register.
1100 //!
1101 //! \return None
1102 //
1103 //*****************************************************************************
1104 void EUSCI_A_SPI_changeClockPhasePolarity(uint32_t baseAddress,
1105         uint16_t clockPhase, uint16_t clockPolarity)
1106 {
1107
1108     ASSERT(
1109             (EUSCI_A_SPI_CLOCKPOLARITY_INACTIVITY_HIGH == clockPolarity)
1110             || (EUSCI_A_SPI_CLOCKPOLARITY_INACTIVITY_LOW
1111                     == clockPolarity));
1112
1113     ASSERT(
1114             (EUSCI_A_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT
1115                     == clockPhase)
1116             || (EUSCI_A_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT
1117                     == clockPhase));
1118
1119     //Disable the USCI Module
1120     BITBAND_PERI(EUSCI_A_CMSIS(baseAddress)->rCTLW0.r, UCSWRST_OFS) = 1;
1121
1122     EUSCI_A_CMSIS(baseAddress)->rCTLW0.r = (EUSCI_A_CMSIS(baseAddress)->rCTLW0.r
1123             & ~(UCCKPH + UCCKPL)) | (clockPhase + clockPolarity);
1124
1125     //Reset the UCSWRST bit to enable the USCI Module
1126     BITBAND_PERI(EUSCI_A_CMSIS(baseAddress)->rCTLW0.r, UCSWRST_OFS) = 0;
1127 }
1128
1129 //*****************************************************************************
1130 //
1131 //! \brief Transmits a byte from the SPI Module.
1132 //!
1133 //! This function will place the supplied data into SPI trasmit data register
1134 //! to start transmission.
1135 //!
1136 //! \param baseAddress is the base address of the EUSCI_A_SPI module.
1137 //! \param transmitData data to be transmitted from the SPI module
1138 //!
1139 //! \return None
1140 //
1141 //*****************************************************************************
1142 void EUSCI_A_SPI_transmitData(uint32_t baseAddress, uint8_t transmitData)
1143 {
1144     EUSCI_A_CMSIS(baseAddress)->rTXBUF.r = transmitData;
1145 }
1146
1147 //*****************************************************************************
1148 //
1149 //! \brief Receives a byte that has been sent to the SPI Module.
1150 //!
1151 //! This function reads a byte of data from the SPI receive data Register.
1152 //!
1153 //! \param baseAddress is the base address of the EUSCI_A_SPI module.
1154 //!
1155 //! \return Returns the byte received from by the SPI module, cast as an
1156 //!         uint8_t.
1157 //
1158 //*****************************************************************************
1159 uint8_t EUSCI_A_SPI_receiveData(uint32_t baseAddress)
1160 {
1161     return EUSCI_A_CMSIS(baseAddress)->rRXBUF.r;
1162 }
1163
1164 //*****************************************************************************
1165 //
1166 //! \brief Enables individual SPI interrupt sources.
1167 //!
1168 //! Enables the indicated SPI interrupt sources.  Only the sources that are
1169 //! enabled can be reflected to the processor interrupt; disabled sources have
1170 //! no effect on the processor. Does not clear interrupt flags.
1171 //!
1172 //! \param baseAddress is the base address of the EUSCI_A_SPI module.
1173 //! \param mask is the bit mask of the interrupt sources to be enabled.
1174 //!        Mask value is the logical OR of any of the following:
1175 //!        - \b EUSCI_A_SPI_TRANSMIT_INTERRUPT
1176 //!        - \b EUSCI_A_SPI_RECEIVE_INTERRUPT
1177 //!
1178 //! Modified bits of \b UCAxIFG register and bits of \b UCAxIE register.
1179 //!
1180 //! \return None
1181 //
1182 //*****************************************************************************
1183 void EUSCI_A_SPI_enableInterrupt(uint32_t baseAddress, uint8_t mask)
1184 {
1185     ASSERT(
1186             !(mask
1187                     & ~(EUSCI_A_SPI_RECEIVE_INTERRUPT
1188                             | EUSCI_A_SPI_TRANSMIT_INTERRUPT)));
1189
1190     EUSCI_A_CMSIS(baseAddress)->rIE.r |= mask;
1191 }
1192
1193 //*****************************************************************************
1194 //
1195 //! \brief Disables individual SPI interrupt sources.
1196 //!
1197 //! Disables the indicated SPI interrupt sources. Only the sources that are
1198 //! enabled can be reflected to the processor interrupt; disabled sources have
1199 //! no effect on the processor.
1200 //!
1201 //! \param baseAddress is the base address of the EUSCI_A_SPI module.
1202 //! \param mask is the bit mask of the interrupt sources to be disabled.
1203 //!        Mask value is the logical OR of any of the following:
1204 //!        - \b EUSCI_A_SPI_TRANSMIT_INTERRUPT
1205 //!        - \b EUSCI_A_SPI_RECEIVE_INTERRUPT
1206 //!
1207 //! Modified bits of \b UCAxIE register.
1208 //!
1209 //! \return None
1210 //
1211 //*****************************************************************************
1212 void EUSCI_A_SPI_disableInterrupt(uint32_t baseAddress, uint8_t mask)
1213 {
1214     ASSERT(
1215             !(mask
1216                     & ~(EUSCI_A_SPI_RECEIVE_INTERRUPT
1217                             | EUSCI_A_SPI_TRANSMIT_INTERRUPT)));
1218
1219     EUSCI_A_CMSIS(baseAddress)->rIE.r &= ~mask;
1220 }
1221
1222 //*****************************************************************************
1223 //
1224 //! \brief Gets the current SPI interrupt status.
1225 //!
1226 //! This returns the interrupt status for the SPI module based on which flag is
1227 //! passed.
1228 //!
1229 //! \param baseAddress is the base address of the EUSCI_A_SPI module.
1230 //! \param mask is the masked interrupt flag status to be returned.
1231 //!        Mask value is the logical OR of any of the following:
1232 //!        - \b EUSCI_A_SPI_TRANSMIT_INTERRUPT
1233 //!        - \b EUSCI_A_SPI_RECEIVE_INTERRUPT
1234 //!
1235 //! \return Logical OR of any of the following:
1236 //!         - \b EUSCI_A_SPI_TRANSMIT_INTERRUPT
1237 //!         - \b EUSCI_A_SPI_RECEIVE_INTERRUPT
1238 //!         \n indicating the status of the masked interrupts
1239 //
1240 //*****************************************************************************
1241 uint8_t EUSCI_A_SPI_getInterruptStatus(uint32_t baseAddress, uint8_t mask)
1242 {
1243     ASSERT(
1244             !(mask
1245                     & ~(EUSCI_A_SPI_RECEIVE_INTERRUPT
1246                             | EUSCI_A_SPI_TRANSMIT_INTERRUPT)));
1247
1248     return EUSCI_A_CMSIS(baseAddress)->rIFG.r & mask;
1249 }
1250
1251 //*****************************************************************************
1252 //
1253 //! \brief Clears the selected SPI interrupt status flag.
1254 //!
1255 //! \param baseAddress is the base address of the EUSCI_A_SPI module.
1256 //! \param mask is the masked interrupt flag to be cleared.
1257 //!        Mask value is the logical OR of any of the following:
1258 //!        - \b EUSCI_A_SPI_TRANSMIT_INTERRUPT
1259 //!        - \b EUSCI_A_SPI_RECEIVE_INTERRUPT
1260 //!
1261 //! Modified bits of \b UCAxIFG register.
1262 //!
1263 //! \return None
1264 //
1265 //*****************************************************************************
1266 void EUSCI_A_SPI_clearInterruptFlag(uint32_t baseAddress, uint8_t mask)
1267 {
1268     ASSERT(
1269             !(mask
1270                     & ~(EUSCI_A_SPI_RECEIVE_INTERRUPT
1271                             | EUSCI_A_SPI_TRANSMIT_INTERRUPT)));
1272
1273     EUSCI_A_CMSIS(baseAddress)->rIFG.r &= ~mask;
1274 }
1275
1276 //*****************************************************************************
1277 //
1278 //! \brief Enables the SPI block.
1279 //!
1280 //! This will enable operation of the SPI block.
1281 //!
1282 //! \param baseAddress is the base address of the EUSCI_A_SPI module.
1283 //!
1284 //! Modified bits are \b UCSWRST of \b UCAxCTLW0 register.
1285 //!
1286 //! \return None
1287 //
1288 //*****************************************************************************
1289 void EUSCI_A_SPI_enable(uint32_t baseAddress)
1290 {
1291     //Reset the UCSWRST bit to enable the USCI Module
1292     BITBAND_PERI(EUSCI_A_CMSIS(baseAddress)->rCTLW0.r, UCSWRST_OFS) = 0;
1293 }
1294
1295 //*****************************************************************************
1296 //
1297 //! \brief Disables the SPI block.
1298 //!
1299 //! This will disable operation of the SPI block.
1300 //!
1301 //! \param baseAddress is the base address of the EUSCI_A_SPI module.
1302 //!
1303 //! Modified bits are \b UCSWRST of \b UCAxCTLW0 register.
1304 //!
1305 //! \return None
1306 //
1307 //*****************************************************************************
1308 void EUSCI_A_SPI_disable(uint32_t baseAddress)
1309 {
1310     //Set the UCSWRST bit to disable the USCI Module
1311     BITBAND_PERI(EUSCI_A_CMSIS(baseAddress)->rCTLW0.r, UCSWRST_OFS) = 1;
1312 }
1313
1314 //*****************************************************************************
1315 //
1316 //! \brief Returns the address of the RX Buffer of the SPI for the DMA module.
1317 //!
1318 //! Returns the address of the SPI RX Buffer. This can be used in conjunction
1319 //! with the DMA to store the received data directly to memory.
1320 //!
1321 //! \param baseAddress is the base address of the EUSCI_A_SPI module.
1322 //!
1323 //! \return the address of the RX Buffer
1324 //
1325 //*****************************************************************************
1326 uint32_t EUSCI_A_SPI_getReceiveBufferAddressForDMA(uint32_t baseAddress)
1327 {
1328     return baseAddress + OFS_UCA0RXBUF;
1329 }
1330
1331 //*****************************************************************************
1332 //
1333 //! \brief Returns the address of the TX Buffer of the SPI for the DMA module.
1334 //!
1335 //! Returns the address of the SPI TX Buffer. This can be used in conjunction
1336 //! with the DMA to obtain transmitted data directly from memory.
1337 //!
1338 //! \param baseAddress is the base address of the EUSCI_A_SPI module.
1339 //!
1340 //! \return the address of the TX Buffer
1341 //
1342 //*****************************************************************************
1343 uint32_t EUSCI_A_SPI_getTransmitBufferAddressForDMA(uint32_t baseAddress)
1344 {
1345     return baseAddress + OFS_UCA0TXBUF;
1346 }
1347
1348 //*****************************************************************************
1349 //
1350 //! \brief Indicates whether or not the SPI bus is busy.
1351 //!
1352 //! This function returns an indication of whether or not the SPI bus is
1353 //! busy.This function checks the status of the bus via UCBBUSY bit
1354 //!
1355 //! \param baseAddress is the base address of the EUSCI_A_SPI module.
1356 //!
1357 //! \return true if busy, false otherwise
1358 //*****************************************************************************
1359 bool EUSCI_A_SPI_isBusy(uint32_t baseAddress)
1360 {
1361     //Return the bus busy status.
1362     return BITBAND_PERI(EUSCI_A_CMSIS(baseAddress)->rSTATW.r, UCBBUSY_OFS);
1363 }