git.sur5r.net Git - freertos/blob - FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/system/IAR/msp432_startup_ewarm.c

   1 #include <stdint.h>\r
   2 #include <msp.h>\r
   3 \r
   4 //*****************************************************************************\r
   5 //\r
   6 // Enable the IAR extensions for this source file.\r
   7 //\r
   8 //*****************************************************************************\r
   9 #pragma language=extended\r
  10 \r
  11 //*****************************************************************************\r
  12 //\r
  13 // Forward declaration of the default fault handlers.\r
  14 //\r
  15 //*****************************************************************************\r
  16 void resetISR(void);\r
  17 static void nmiSR(void);\r
  18 static void faultISR(void);\r
  19 static void intDefaultHandler(void);\r
  20 \r
  21 //*****************************************************************************\r
  22 //\r
  23 // External declaration for the interrupt handler used by the application.\r
  24 //\r
  25 //*****************************************************************************\r
  26 extern void SysTick_Handler( void );\r
  27 extern void PendSV_Handler( void );\r
  28 extern void SVC_Handler( void );\r
  29 extern void vUART_Handler( void );\r
  30 extern void vT32_0_Handler( void );\r
  31 extern void vT32_1_Handler( void );\r
  32 //*****************************************************************************\r
  33 //\r
  34 // The entry point for the application startup code.\r
  35 //\r
  36 //*****************************************************************************\r
  37 extern void __iar_program_start(void);\r
  38 \r
  39 //*****************************************************************************\r
  40 //\r
  41 // Reserve space for the system stack.\r
  42 //\r
  43 //*****************************************************************************\r
  44 static uint32_t systemStack[128] @ ".noinit";\r
  45 \r
  46 //*****************************************************************************\r
  47 //\r
  48 // A union that describes the entries of the vector table.  The union is needed\r
  49 // since the first entry is the stack pointer and the remainder are function\r
  50 // pointers.\r
  51 //\r
  52 //*****************************************************************************\r
  53 typedef union\r
  54 {\r
  55     void (*handler)(void);\r
  56     uint32_t ptr;\r
  57 }\r
  58 uVectorEntry;\r
  59 \r
  60 //*****************************************************************************\r
  61 //\r
  62 // The vector table.  Note that the proper constructs must be placed on this to\r
  63 // ensure that it ends up at physical address 0x0000.0000.\r
  64 //\r
  65 //*****************************************************************************\r
  66 __root const uVectorEntry __vector_table[] @ ".intvec" =\r
  67 {\r
  68     { .ptr = (uint32_t)systemStack + sizeof(systemStack) },\r
  69                                             // The initial stack pointer\r
  70     resetISR,                               // The reset handler\r
  71     nmiSR,                                  // The NMI handler\r
  72     faultISR,                               // The hard fault handler\r
  73     intDefaultHandler,                             // The MPU fault handler\r
  74     intDefaultHandler,                             // The bus fault handler\r
  75     intDefaultHandler,                             // The usage fault handler\r
  76     0,                                      // Reserved\r
  77     0,                                      // Reserved\r
  78     0,                                      // Reserved\r
  79     0,                                      // Reserved\r
  80     SVC_Handler,                             // SVCall handler\r
  81     intDefaultHandler,                             // Debug monitor handler\r
  82     0,                                      // Reserved\r
  83     PendSV_Handler,                             // The PendSV handler\r
  84     SysTick_Handler,                            // The SysTick handler\r
  85     intDefaultHandler,                             // PSS ISR\r
  86     intDefaultHandler,                             // CS ISR\r
  87     intDefaultHandler,                             // PCM ISR\r
  88     intDefaultHandler,                             // WDT ISR\r
  89     intDefaultHandler,                             // FPU ISR\r
  90     intDefaultHandler,                             // FLCTL ISR\r
  91     intDefaultHandler,                             // COMP0 ISR\r
  92     intDefaultHandler,                             // COMP1 ISR\r
  93     intDefaultHandler,                             // TA0_0 ISR\r
  94     intDefaultHandler,                             // TA0_N ISR\r
  95     intDefaultHandler,                            // TA1_0 ISR\r
  96     intDefaultHandler,                             // TA1_N ISR\r
  97     intDefaultHandler,                            // TA2_0 ISR\r
  98     intDefaultHandler,                             // TA2_N ISR\r
  99     intDefaultHandler,                             // TA3_0 ISR\r
 100     intDefaultHandler,                             // TA3_N ISR\r
 101     vUART_Handler,                            // EUSCIA0 ISR\r
 102     intDefaultHandler,                             // EUSCIA1 ISR\r
 103     intDefaultHandler,                             // EUSCIA2 ISR\r
 104     intDefaultHandler,                             // EUSCIA3 ISR\r
 105     intDefaultHandler,                             // EUSCIB0 ISR\r
 106     intDefaultHandler,                             // EUSCIB1 ISR\r
 107     intDefaultHandler,                             // EUSCIB2 ISR\r
 108     intDefaultHandler,                             // EUSCIB3 ISR\r
 109     intDefaultHandler,                             // ADC14 ISR\r
 110     vT32_0_Handler,                                // T32_INT1 ISR\r
 111     vT32_1_Handler,                                // T32_INT2 ISR\r
 112     intDefaultHandler,                             // T32_INTC ISR\r
 113     intDefaultHandler,                             // AES ISR\r
 114     intDefaultHandler,                             // RTC ISR\r
 115     intDefaultHandler,                             // DMA_ERR ISR\r
 116     intDefaultHandler,                             // DMA_INT3 ISR\r
 117     intDefaultHandler,                             // DMA_INT2 ISR\r
 118     intDefaultHandler,                             // DMA_INT1 ISR\r
 119     intDefaultHandler,                             // DMA_INT0 ISR\r
 120     intDefaultHandler,                        // PORT1 ISR\r
 121     intDefaultHandler,                             // PORT2 ISR\r
 122     intDefaultHandler,                             // PORT3 ISR\r
 123     intDefaultHandler,                             // PORT4 ISR\r
 124     intDefaultHandler,                             // PORT5 ISR\r
 125     intDefaultHandler,                             // PORT6 ISR\r
 126     intDefaultHandler,                             // Reserved 41\r
 127     intDefaultHandler,                             // Reserved 42\r
 128     intDefaultHandler,                             // Reserved 43\r
 129     intDefaultHandler,                             // Reserved 44\r
 130     intDefaultHandler,                             // Reserved 45\r
 131     intDefaultHandler,                             // Reserved 46\r
 132     intDefaultHandler,                             // Reserved 47\r
 133     intDefaultHandler,                             // Reserved 48\r
 134     intDefaultHandler,                             // Reserved 49\r
 135     intDefaultHandler,                             // Reserved 50\r
 136     intDefaultHandler,                             // Reserved 51\r
 137     intDefaultHandler,                             // Reserved 52\r
 138     intDefaultHandler,                             // Reserved 53\r
 139     intDefaultHandler,                             // Reserved 54\r
 140     intDefaultHandler,                             // Reserved 55\r
 141     intDefaultHandler,                             // Reserved 56\r
 142     intDefaultHandler,                             // Reserved 57\r
 143     intDefaultHandler,                             // Reserved 58\r
 144     intDefaultHandler,                             // Reserved 59\r
 145     intDefaultHandler,                             // Reserved 60\r
 146     intDefaultHandler,                             // Reserved 61\r
 147     intDefaultHandler,                             // Reserved 62\r
 148     intDefaultHandler,                             // Reserved 63\r
 149     intDefaultHandler                              // Reserved 64\r
 150 };\r
 151 \r
 152 //*****************************************************************************\r
 153 //\r
 154 // This is the code that gets called when the processor first starts execution\r
 155 // following a reset event.  Only the absolutely necessary set is performed,\r
 156 // after which the application supplied entry() routine is called.  Any fancy\r
 157 // actions (such as making decisions based on the reset cause register, and\r
 158 // resetting the bits in that register) are left solely in the hands of the\r
 159 // application.\r
 160 //\r
 161 //*****************************************************************************\r
 162 void\r
 163 resetISR(void)\r
 164 {\r
 165 \r
 166     WDTCTL = WDTPW | WDTHOLD;               // Stop WDT\r
 167 \r
 168     //\r
 169     // Call the application's entry point.\r
 170     //\r
 171     __iar_program_start();\r
 172 }\r
 173 \r
 174 //*****************************************************************************\r
 175 //\r
 176 // This is the code that gets called when the processor receives a NMI.  This\r
 177 // simply enters an infinite loop, preserving the system state for examination\r
 178 // by a debugger.\r
 179 //\r
 180 //*****************************************************************************\r
 181 static void\r
 182 nmiSR(void)\r
 183 {\r
 184     //\r
 185     // Enter an infinite loop.\r
 186     //\r
 187     while(1)\r
 188     {\r
 189     }\r
 190 }\r
 191 \r
 192 //*****************************************************************************\r
 193 //\r
 194 // This is the code that gets called when the processor receives a fault\r
 195 // interrupt.  This simply enters an infinite loop, preserving the system state\r
 196 // for examination by a debugger.\r
 197 //\r
 198 //*****************************************************************************\r
 199 static void\r
 200 faultISR(void)\r
 201 {\r
 202     //\r
 203     // Enter an infinite loop.\r
 204     //\r
 205     while(1)\r
 206     {\r
 207     }\r
 208 }\r
 209 \r
 210 //*****************************************************************************\r
 211 //\r
 212 // This is the code that gets called when the processor receives an unexpected\r
 213 // interrupt.  This simply enters an infinite loop, preserving the system state\r
 214 // for examination by a debugger.\r
 215 //\r
 216 //*****************************************************************************\r
 217 static void\r
 218 intDefaultHandler(void)\r
 219 {\r
 220     //\r
 221     // Go into an infinite loop.\r
 222     //\r
 223     while(1)\r
 224     {\r
 225     }\r
 226 }\r