git.sur5r.net Git - freertos/blob - FreeRTOS/Demo/CORTEX_M4F_MSP432_LaunchPad_IAR_CCS_Keil/system/Keil/startup_MSP432P4.s

   1 ;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------\r
   2 ;*/\r
   3 \r
   4 \r
   5 ; <h> Stack Configuration\r
   6 ;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\r
   7 ; </h>\r
   8 \r
   9 Stack_Size      EQU     0x00000200\r
  10 \r
  11                 AREA    STACK, NOINIT, READWRITE, ALIGN=3\r
  12 Stack_Mem       SPACE   Stack_Size\r
  13 __initial_sp\r
  14 \r
  15 \r
  16 ; <h> Heap Configuration\r
  17 ;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\r
  18 ; </h>\r
  19 \r
  20 Heap_Size       EQU     0x00000000\r
  21 \r
  22                 AREA    HEAP, NOINIT, READWRITE, ALIGN=3\r
  23 __heap_base\r
  24 Heap_Mem        SPACE   Heap_Size\r
  25 __heap_limit\r
  26 \r
  27 \r
  28                 PRESERVE8\r
  29                 THUMB\r
  30 \r
  31 \r
  32 ; Vector Table Mapped to Address 0 at Reset\r
  33 \r
  34                 AREA    RESET, DATA, READONLY\r
  35                 EXPORT  __Vectors\r
  36                 EXPORT  __Vectors_End\r
  37                 EXPORT  __Vectors_Size\r
  38                                 IMPORT  vUART_Handler\r
  39                                 IMPORT  vT32_0_Handler\r
  40                                 IMPORT  vT32_1_Handler\r
  41 \r
  42 __Vectors       DCD     __initial_sp              ; Top of Stack\r
  43                 DCD     Reset_Handler             ; Reset Handler\r
  44                 DCD     NMI_Handler               ; NMI Handler\r
  45                 DCD     HardFault_Handler         ; Hard Fault Handler\r
  46                 DCD     0                         ; Reserved\r
  47                 DCD     0                         ; Reserved\r
  48                 DCD     0                         ; Reserved\r
  49                 DCD     0                         ; Reserved\r
  50                 DCD     0                         ; Reserved\r
  51                 DCD     0                         ; Reserved\r
  52                 DCD     0                         ; Reserved\r
  53                 DCD     SVC_Handler               ; SVCall Handler\r
  54                 DCD     0                         ; Reserved\r
  55                 DCD     0                         ; Reserved\r
  56                 DCD     PendSV_Handler            ; PendSV Handler\r
  57                 DCD     SysTick_Handler           ; SysTick Handler\r
  58 \r
  59                 ; External Interrupts\r
  60                 DCD     IntDefault_Handler        ; PSS ISR\r
  61                 DCD     IntDefault_Handler        ; CS ISR \r
  62                 DCD     IntDefault_Handler        ; PCM ISR\r
  63                 DCD     IntDefault_Handler        ; WDT ISR\r
  64                 DCD     IntDefault_Handler        ; FPU ISR\r
  65                 DCD     IntDefault_Handler        ; FLCTL ISR\r
  66                 DCD     IntDefault_Handler        ; COMP0 ISR\r
  67                 DCD     IntDefault_Handler        ; COMP1 ISR\r
  68                 DCD     IntDefault_Handler        ; TA0_0 ISR \r
  69                 DCD     IntDefault_Handler        ; TA0_N ISR\r
  70                 DCD     IntDefault_Handler        ; TA1_0 ISR\r
  71                 DCD     IntDefault_Handler        ; TA1_N ISR\r
  72                 DCD     IntDefault_Handler        ; TA2_0 ISR\r
  73                 DCD     IntDefault_Handler        ; TA2_N ISR\r
  74                 DCD     IntDefault_Handler        ; TA3_0 ISR\r
  75                 DCD     IntDefault_Handler        ; TA3_N ISR\r
  76                 DCD     vUART_Handler             ; EUSCIA0 ISR\r
  77                 DCD     IntDefault_Handler        ; EUSCIA1 ISR\r
  78                 DCD     IntDefault_Handler        ; EUSCIA2 ISR\r
  79                 DCD     IntDefault_Handler        ; EUSCIA3 ISR\r
  80                 DCD     IntDefault_Handler        ; EUSCIB0 ISR\r
  81                 DCD     IntDefault_Handler        ; EUSCIB1 ISR\r
  82                 DCD     IntDefault_Handler        ; EUSCIB2 ISR\r
  83                 DCD     IntDefault_Handler        ; EUSCIB3 ISR\r
  84                 DCD     IntDefault_Handler        ; ADC12 ISR\r
  85                 DCD     vT32_0_Handler            ; T32_INT1 ISR\r
  86                 DCD     vT32_1_Handler            ; T32_INT2 ISR\r
  87                 DCD     IntDefault_Handler        ; T32_INTC ISR\r
  88                 DCD     IntDefault_Handler        ; AES ISR\r
  89                 DCD     IntDefault_Handler        ; RTC ISR\r
  90                 DCD     IntDefault_Handler        ; DMA_ERR ISR\r
  91                 DCD     IntDefault_Handler        ; DMA_INT3 ISR\r
  92                 DCD     IntDefault_Handler        ; DMA_INT2 ISR\r
  93                 DCD     IntDefault_Handler        ; DMA_INT1 ISR\r
  94                 DCD     IntDefault_Handler        ; DMA_INT0 ISR\r
  95                 DCD     IntDefault_Handler        ; PORT1 ISR\r
  96                 DCD     IntDefault_Handler        ; PORT2 ISR\r
  97                 DCD     IntDefault_Handler        ; PORT3 ISR\r
  98                 DCD     IntDefault_Handler        ; PORT4 ISR\r
  99                 DCD     IntDefault_Handler        ; PORT5 ISR\r
 100                 DCD     IntDefault_Handler        ; PORT6 ISR\r
 101                 DCD     IntDefault_Handler        ; Reserved 41\r
 102                 DCD     IntDefault_Handler        ; Reserved 42\r
 103                 DCD     IntDefault_Handler        ; Reserved 43\r
 104                 DCD     IntDefault_Handler        ; Reserved 44\r
 105                 DCD     IntDefault_Handler        ; Reserved 45\r
 106                 DCD     IntDefault_Handler        ; Reserved 46\r
 107                 DCD     IntDefault_Handler        ; Reserved 47\r
 108                 DCD     IntDefault_Handler        ; Reserved 48\r
 109                 DCD     IntDefault_Handler        ; Reserved 49\r
 110                 DCD     IntDefault_Handler        ; Reserved 50\r
 111                 DCD     IntDefault_Handler        ; Reserved 51\r
 112                 DCD     IntDefault_Handler        ; Reserved 52\r
 113                 DCD     IntDefault_Handler        ; Reserved 53\r
 114                 DCD     IntDefault_Handler        ; Reserved 54\r
 115                 DCD     IntDefault_Handler        ; Reserved 55\r
 116                 DCD     IntDefault_Handler        ; Reserved 56\r
 117                 DCD     IntDefault_Handler        ; Reserved 57\r
 118                 DCD     IntDefault_Handler        ; Reserved 58\r
 119                 DCD     IntDefault_Handler        ; Reserved 59\r
 120                 DCD     IntDefault_Handler        ; Reserved 60\r
 121                 DCD     IntDefault_Handler        ; Reserved 61\r
 122                 DCD     IntDefault_Handler        ; Reserved 62\r
 123                 DCD     IntDefault_Handler        ; Reserved 63\r
 124                 DCD     IntDefault_Handler        ; Reserved 64\r
 125 __Vectors_End\r
 126 \r
 127 __Vectors_Size  EQU     __Vectors_End - __Vectors\r
 128 \r
 129                 AREA    |.text|, CODE, READONLY\r
 130 \r
 131 \r
 132 ; Reset Handler\r
 133 \r
 134 Reset_Handler   PROC\r
 135                 EXPORT  Reset_Handler             [WEAK]\r
 136                 IMPORT  SystemInit\r
 137                 IMPORT  __main\r
 138                 LDR     R0, =SystemInit\r
 139                 BLX     R0\r
 140                 LDR     R0, =__main\r
 141                 BX      R0\r
 142                 ENDP\r
 143 \r
 144 \r
 145 ; Dummy Exception Handlers (infinite loops which can be modified)\r
 146 \r
 147 NMI_Handler     PROC\r
 148                 EXPORT  NMI_Handler               [WEAK]\r
 149                 B       .\r
 150                 ENDP\r
 151 HardFault_Handler\\r
 152                 PROC\r
 153                 EXPORT  HardFault_Handler         [WEAK]\r
 154                 B       .\r
 155                 ENDP\r
 156 SVC_Handler     PROC\r
 157                 EXPORT  SVC_Handler               [WEAK]\r
 158                 B       .\r
 159                 ENDP\r
 160 PendSV_Handler  PROC\r
 161                 EXPORT  PendSV_Handler            [WEAK]\r
 162                 B       .\r
 163                 ENDP\r
 164 SysTick_Handler PROC\r
 165                 EXPORT  SysTick_Handler           [WEAK]\r
 166                 B       .\r
 167                 ENDP\r
 168 IntDefault_Handler PROC\r
 169                 EXPORT  IntDefault_Handler        [WEAK]\r
 170                 B       .\r
 171                 ENDP\r
 172 \r
 173                 ALIGN\r
 174 \r
 175                 \r
 176 ; User Initial Stack & Heap\r
 177 \r
 178                 IF      :DEF:__MICROLIB\r
 179 \r
 180                 EXPORT  __initial_sp\r
 181                 EXPORT  __heap_base\r
 182                 EXPORT  __heap_limit\r
 183 \r
 184                 ELSE\r
 185 \r
 186                 IMPORT  __use_two_region_memory\r
 187                 EXPORT  __user_initial_stackheap\r
 188 __user_initial_stackheap\r
 189 \r
 190                 LDR     R0, =  Heap_Mem\r
 191                 LDR     R1, =(Stack_Mem + Stack_Size)\r
 192                 LDR     R2, = (Heap_Mem +  Heap_Size)\r
 193                 LDR     R3, = Stack_Mem\r
 194                 BX      LR\r
 195 \r
 196                 ALIGN\r
 197 \r
 198                 ENDIF\r
 199 \r
 200 \r
 201                 END\r