git.sur5r.net Git - freertos/blob - FreeRTOS/Demo/CORTEX_M4_ATSAM4S_Atmel_Studio/src/asf/common/services/clock/sam4s/genclk.h

   1 /**\r
   2  * \file\r
   3  *\r
   4  * \brief Chip-specific generic clock management.\r
   5  *\r
   6  * Copyright (c) 2011 - 2012 Atmel Corporation. All rights reserved.\r
   7  *\r
   8  * \asf_license_start\r
   9  *\r
  10  * Redistribution and use in source and binary forms, with or without\r
  11  * modification, are permitted provided that the following conditions are met:\r
  12  *\r
  13  * 1. Redistributions of source code must retain the above copyright notice,\r
  14  *    this list of conditions and the following disclaimer.\r
  15  *\r
  16  * 2. Redistributions in binary form must reproduce the above copyright notice,\r
  17  *    this list of conditions and the following disclaimer in the documentation\r
  18  *    and/or other materials provided with the distribution.\r
  19  *\r
  20  * 3. The name of Atmel may not be used to endorse or promote products derived\r
  21  *    from this software without specific prior written permission.\r
  22  *\r
  23  * 4. This software may only be redistributed and used in connection with an\r
  24  *    Atmel microcontroller product.\r
  25  *\r
  26  * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
  27  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
  28  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
  29  * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
  30  * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
  31  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
  32  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
  33  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
  34  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
  35  * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
  36  * POSSIBILITY OF SUCH DAMAGE.\r
  37  *\r
  38  * \asf_license_stop\r
  39  *\r
  40  */\r
  41 \r
  42 #ifndef CHIP_GENCLK_H_INCLUDED\r
  43 #define CHIP_GENCLK_H_INCLUDED\r
  44 \r
  45 #include <osc.h>\r
  46 #include <pll.h>\r
  47 \r
  48 /// @cond 0\r
  49 /**INDENT-OFF**/\r
  50 #ifdef __cplusplus\r
  51 extern "C" {\r
  52 #endif\r
  53 /**INDENT-ON**/\r
  54 /// @endcond\r
  55 \r
  56 /**\r
  57  * \weakgroup genclk_group\r
  58  * @{\r
  59  */\r
  60 \r
  61 //! \name Programmable Clock Identifiers (PCK)\r
  62 //@{\r
  63 #define GENCLK_PCK_0                    0                                               //!< PCK0 ID\r
  64 #define GENCLK_PCK_1                    1                                               //!< PCK1 ID\r
  65 #define GENCLK_PCK_2                    2                                               //!< PCK2 ID\r
  66 //@}\r
  67 \r
  68 //! \name Programmable Clock Sources (PCK)\r
  69 //@{\r
  70 \r
  71 enum genclk_source {\r
  72         GENCLK_PCK_SRC_SLCK_RC                  =       0,      //!< Internal 32kHz RC oscillator as PCK source clock\r
  73         GENCLK_PCK_SRC_SLCK_XTAL                =       1,      //!< External 32kHz crystal oscillator as PCK source clock\r
  74         GENCLK_PCK_SRC_SLCK_BYPASS              =       2,      //!< External 32kHz bypass oscillator as PCK source clock\r
  75         GENCLK_PCK_SRC_MAINCK_4M_RC             =       3,      //!< Internal 4MHz RC oscillator as PCK source clock\r
  76         GENCLK_PCK_SRC_MAINCK_8M_RC             =       4,      //!< Internal 8MHz RC oscillator as PCK source clock\r
  77         GENCLK_PCK_SRC_MAINCK_12M_RC    =       5,      //!< Internal 12MHz RC oscillator as PCK source clock\r
  78         GENCLK_PCK_SRC_MAINCK_XTAL              =       6,      //!< External crystal oscillator as PCK source clock\r
  79         GENCLK_PCK_SRC_MAINCK_BYPASS    =       7,      //!< External bypass oscillator as PCK source clock\r
  80         GENCLK_PCK_SRC_PLLACK                   =       8,      //!< Use PLLACK as PCK source clock\r
  81         GENCLK_PCK_SRC_PLLBCK                   =       9,      //!< Use PLLBCK as PCK source clock\r
  82 };\r
  83 \r
  84 //@}\r
  85 \r
  86 //! \name Programmable Clock Prescalers (PCK)\r
  87 //@{\r
  88 \r
  89 enum genclk_divider {\r
  90         GENCLK_PCK_PRES_1       =       PMC_PCK_PRES_CLK_1,             //!< Set PCK clock prescaler to 1\r
  91         GENCLK_PCK_PRES_2       =       PMC_PCK_PRES_CLK_2,             //!< Set PCK clock prescaler to 2\r
  92         GENCLK_PCK_PRES_4       =       PMC_PCK_PRES_CLK_4,             //!< Set PCK clock prescaler to 4\r
  93         GENCLK_PCK_PRES_8       =       PMC_PCK_PRES_CLK_8,             //!< Set PCK clock prescaler to 8\r
  94         GENCLK_PCK_PRES_16      =       PMC_PCK_PRES_CLK_16,    //!< Set PCK clock prescaler to 16\r
  95         GENCLK_PCK_PRES_32      =       PMC_PCK_PRES_CLK_32,    //!< Set PCK clock prescaler to 32\r
  96         GENCLK_PCK_PRES_64      =       PMC_PCK_PRES_CLK_64,    //!< Set PCK clock prescaler to 64\r
  97 };\r
  98 \r
  99 //@}\r
 100 \r
 101 struct genclk_config {\r
 102         uint32_t ctrl;\r
 103 };\r
 104 \r
 105 static inline void genclk_config_defaults(struct genclk_config *p_cfg,\r
 106                 uint32_t ul_id)\r
 107 {\r
 108         ul_id = ul_id;\r
 109         p_cfg->ctrl = 0;\r
 110 }\r
 111 \r
 112 static inline void genclk_config_read(struct genclk_config *p_cfg,\r
 113                 uint32_t ul_id)\r
 114 {\r
 115         p_cfg->ctrl = PMC->PMC_PCK[ul_id];\r
 116 }\r
 117 \r
 118 static inline void genclk_config_write(const struct genclk_config *p_cfg,\r
 119                 uint32_t ul_id)\r
 120 {\r
 121         PMC->PMC_PCK[ul_id] = p_cfg->ctrl;\r
 122 }\r
 123 \r
 124 //! \name Programmable Clock Source and Prescaler configuration\r
 125 //@{\r
 126 \r
 127 static inline void genclk_config_set_source(struct genclk_config *p_cfg,\r
 128                 enum genclk_source e_src)\r
 129 {\r
 130         p_cfg->ctrl &= (~PMC_PCK_CSS_Msk);\r
 131 \r
 132         switch (e_src) {\r
 133         case GENCLK_PCK_SRC_SLCK_RC:\r
 134         case GENCLK_PCK_SRC_SLCK_XTAL:\r
 135         case GENCLK_PCK_SRC_SLCK_BYPASS:\r
 136                 p_cfg->ctrl |= (PMC_MCKR_CSS_SLOW_CLK);\r
 137                 break;\r
 138 \r
 139         case GENCLK_PCK_SRC_MAINCK_4M_RC:\r
 140         case GENCLK_PCK_SRC_MAINCK_8M_RC:\r
 141         case GENCLK_PCK_SRC_MAINCK_12M_RC:\r
 142         case GENCLK_PCK_SRC_MAINCK_XTAL:\r
 143         case GENCLK_PCK_SRC_MAINCK_BYPASS:\r
 144                 p_cfg->ctrl |= (PMC_MCKR_CSS_MAIN_CLK);\r
 145                 break;\r
 146 \r
 147         case GENCLK_PCK_SRC_PLLACK:\r
 148                 p_cfg->ctrl |= (PMC_MCKR_CSS_PLLA_CLK);\r
 149                 break;\r
 150 \r
 151         case GENCLK_PCK_SRC_PLLBCK:\r
 152                 p_cfg->ctrl |= (PMC_MCKR_CSS_PLLB_CLK);\r
 153                 break;\r
 154         }\r
 155 }\r
 156 \r
 157 static inline void genclk_config_set_divider(struct genclk_config *p_cfg,\r
 158                 enum genclk_divider e_divider)\r
 159 {\r
 160         p_cfg->ctrl &= ~PMC_PCK_PRES_Msk;\r
 161         p_cfg->ctrl |= e_divider;       \r
 162 }\r
 163 \r
 164 //@}\r
 165 \r
 166 static inline void genclk_enable(const struct genclk_config *p_cfg, uint32_t ul_id)\r
 167 {\r
 168         PMC->PMC_PCK[ul_id] = p_cfg->ctrl;\r
 169         pmc_enable_pck(ul_id);\r
 170 }\r
 171 \r
 172 static inline void genclk_disable(uint32_t ul_id)\r
 173 {\r
 174         pmc_disable_pck(ul_id);\r
 175 }\r
 176 \r
 177 static inline void genclk_enable_source(enum genclk_source e_src)\r
 178 {\r
 179         switch (e_src) {\r
 180         case GENCLK_PCK_SRC_SLCK_RC:\r
 181                 if (!osc_is_ready(OSC_SLCK_32K_RC)) {\r
 182                         osc_enable(OSC_SLCK_32K_RC);\r
 183                         osc_wait_ready(OSC_SLCK_32K_RC);\r
 184                 }               \r
 185                 break;\r
 186         \r
 187         case GENCLK_PCK_SRC_SLCK_XTAL:\r
 188                 if (!osc_is_ready(OSC_SLCK_32K_XTAL)) {\r
 189                         osc_enable(OSC_SLCK_32K_XTAL);\r
 190                         osc_wait_ready(OSC_SLCK_32K_XTAL);\r
 191                 }\r
 192                 break;\r
 193                 \r
 194         case GENCLK_PCK_SRC_SLCK_BYPASS:\r
 195                 if (!osc_is_ready(OSC_SLCK_32K_BYPASS)) {\r
 196                         osc_enable(OSC_SLCK_32K_BYPASS);\r
 197                         osc_wait_ready(OSC_SLCK_32K_BYPASS);            \r
 198                 }               \r
 199                 break;\r
 200         \r
 201     case GENCLK_PCK_SRC_MAINCK_4M_RC:\r
 202                 if (!osc_is_ready(OSC_MAINCK_4M_RC)) {\r
 203                         osc_enable(OSC_MAINCK_4M_RC);\r
 204                         osc_wait_ready(OSC_MAINCK_4M_RC);               \r
 205                 }               \r
 206                 break;\r
 207 \r
 208     case GENCLK_PCK_SRC_MAINCK_8M_RC:\r
 209                 if (!osc_is_ready(OSC_MAINCK_8M_RC)) {\r
 210                         osc_enable(OSC_MAINCK_8M_RC);\r
 211                         osc_wait_ready(OSC_MAINCK_8M_RC);               \r
 212                 }               \r
 213                 break;\r
 214 \r
 215     case GENCLK_PCK_SRC_MAINCK_12M_RC:\r
 216                 if (!osc_is_ready(OSC_MAINCK_12M_RC)) {\r
 217                         osc_enable(OSC_MAINCK_12M_RC);\r
 218                         osc_wait_ready(OSC_MAINCK_12M_RC);              \r
 219                 }               \r
 220                 break;\r
 221 \r
 222     case GENCLK_PCK_SRC_MAINCK_XTAL:\r
 223                 if (!osc_is_ready(OSC_MAINCK_XTAL)) {\r
 224                         osc_enable(OSC_MAINCK_XTAL);\r
 225                         osc_wait_ready(OSC_MAINCK_XTAL);                \r
 226                 }               \r
 227                 break;\r
 228 \r
 229     case GENCLK_PCK_SRC_MAINCK_BYPASS:\r
 230                 if (!osc_is_ready(OSC_MAINCK_BYPASS)) {\r
 231                         osc_enable(OSC_MAINCK_BYPASS);\r
 232                         osc_wait_ready(OSC_MAINCK_BYPASS);              \r
 233                 }               \r
 234                 break;\r
 235 \r
 236 #ifdef CONFIG_PLL0_SOURCE\r
 237         case GENCLK_PCK_SRC_PLLACK:\r
 238                 pll_enable_config_defaults(0);          \r
 239                 break;  \r
 240 #endif\r
 241 \r
 242 #ifdef CONFIG_PLL1_SOURCE\r
 243         case GENCLK_PCK_SRC_PLLBCK:\r
 244                 pll_enable_config_defaults(1);          \r
 245                 break;  \r
 246 #endif  \r
 247 \r
 248         default:\r
 249                 Assert(false);\r
 250                 break;\r
 251         }\r
 252 }\r
 253 \r
 254 //! @}\r
 255 \r
 256 /// @cond 0\r
 257 /**INDENT-OFF**/\r
 258 #ifdef __cplusplus\r
 259 }\r
 260 #endif\r
 261 /**INDENT-ON**/\r
 262 /// @endcond\r
 263 \r
 264 #endif /* CHIP_GENCLK_H_INCLUDED */\r