git.sur5r.net Git - freertos/blob - FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/boards/CC3220SF_LAUNCHXL/CC3220SF_LAUNCHXL.c

   1 /*
   2  * Copyright (c) 2016, Texas Instruments Incorporated
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  *
   9  * *  Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  *
  12  * *  Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  *
  16  * *  Neither the name of Texas Instruments Incorporated nor the names of
  17  *    its contributors may be used to endorse or promote products derived
  18  *    from this software without specific prior written permission.
  19  *
  20  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  22  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  23  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
  24  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  25  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  26  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
  27  * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  28  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
  29  * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
  30  * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  31  */
  32
  33 /*
  34  *  ======== CC3220SF_LAUNCHXL.c ========
  35  *  This file is responsible for setting up the board specific items for the
  36  *  CC3220SF_LAUNCHXL board.
  37  */
  38
  39 #include <stdint.h>
  40 #include <stdbool.h>
  41
  42 #include <ti/devices/cc32xx/inc/hw_ints.h>
  43 #include <ti/devices/cc32xx/inc/hw_memmap.h>
  44 #include <ti/devices/cc32xx/inc/hw_types.h>
  45
  46 #include <ti/devices/cc32xx/driverlib/rom.h>
  47 #include <ti/devices/cc32xx/driverlib/rom_map.h>
  48 #include <ti/devices/cc32xx/driverlib/adc.h>
  49 #include <ti/devices/cc32xx/driverlib/gpio.h>
  50 #include <ti/devices/cc32xx/driverlib/pin.h>
  51 #include <ti/devices/cc32xx/driverlib/prcm.h>
  52 #include <ti/devices/cc32xx/driverlib/spi.h>
  53 #include <ti/devices/cc32xx/driverlib/sdhost.h>
  54 #include <ti/devices/cc32xx/driverlib/timer.h>
  55 #include <ti/devices/cc32xx/driverlib/uart.h>
  56 #include <ti/devices/cc32xx/driverlib/udma.h>
  57 #include <ti/devices/cc32xx/driverlib/wdt.h>
  58
  59 #include <ti/drivers/Power.h>
  60 #include <ti/drivers/power/PowerCC32XX.h>
  61
  62 #include "CC3220SF_LAUNCHXL.h"
  63
  64 /*
  65  *  This define determines whether to use the UARTCC32XXDMA driver
  66  *  or the UARTCC32XX (no DMA) driver.  Set to 1 to use the UARTCC32XXDMA
  67  *  driver.
  68  */
  69 #ifndef TI_DRIVERS_UART_DMA
  70 #define TI_DRIVERS_UART_DMA 0
  71 #endif
  72
  73 /*
  74  *  =============================== ADC ===============================
  75  */
  76 #include <ti/drivers/ADC.h>
  77 #include <ti/drivers/adc/ADCCC32XX.h>
  78
  79 ADCCC32XX_Object adcCC3220SObjects[CC3220SF_LAUNCHXL_ADCCOUNT];
  80
  81 const ADCCC32XX_HWAttrsV1 adcCC3220SHWAttrs[CC3220SF_LAUNCHXL_ADCCOUNT] = {
  82     {
  83         .adcPin = ADCCC32XX_PIN_59_CH_2
  84     },
  85     {
  86         .adcPin = ADCCC32XX_PIN_60_CH_3
  87     }
  88 };
  89
  90 const ADC_Config ADC_config[CC3220SF_LAUNCHXL_ADCCOUNT] = {
  91     {
  92         .fxnTablePtr = &ADCCC32XX_fxnTable,
  93         .object = &adcCC3220SObjects[CC3220SF_LAUNCHXL_ADC0],
  94         .hwAttrs = &adcCC3220SHWAttrs[CC3220SF_LAUNCHXL_ADC0]
  95     },
  96     {
  97         .fxnTablePtr = &ADCCC32XX_fxnTable,
  98         .object = &adcCC3220SObjects[CC3220SF_LAUNCHXL_ADC1],
  99         .hwAttrs = &adcCC3220SHWAttrs[CC3220SF_LAUNCHXL_ADC1]
 100     }
 101 };
 102
 103 const uint_least8_t ADC_count = CC3220SF_LAUNCHXL_ADCCOUNT;
 104
 105 /*
 106  *  =============================== Crypto ===============================
 107  */
 108 #include <ti/drivers/crypto/CryptoCC32XX.h>
 109
 110 CryptoCC32XX_Object cryptoCC3220SObjects[CC3220SF_LAUNCHXL_CRYPTOCOUNT];
 111
 112 const CryptoCC32XX_Config CryptoCC32XX_config[CC3220SF_LAUNCHXL_CRYPTOCOUNT] = {
 113     {
 114         .object = &cryptoCC3220SObjects[CC3220SF_LAUNCHXL_CRYPTO0]
 115     }
 116 };
 117
 118 const uint_least8_t CryptoCC32XX_count = CC3220SF_LAUNCHXL_CRYPTOCOUNT;
 119
 120 /*
 121  *  =============================== DMA ===============================
 122  */
 123 #include <ti/drivers/dma/UDMACC32XX.h>
 124
 125 #if defined(__TI_COMPILER_VERSION__)
 126 #pragma DATA_ALIGN(dmaControlTable, 1024)
 127 #elif defined(__IAR_SYSTEMS_ICC__)
 128 #pragma data_alignment=1024
 129 #elif defined(__GNUC__)
 130 __attribute__ ((aligned (1024)))
 131 #endif
 132 static tDMAControlTable dmaControlTable[64];
 133
 134 /*
 135  *  ======== dmaErrorFxn ========
 136  *  This is the handler for the uDMA error interrupt.
 137  */
 138 static void dmaErrorFxn(uintptr_t arg)
 139 {
 140     int status = MAP_uDMAErrorStatusGet();
 141     MAP_uDMAErrorStatusClear();
 142
 143     /* Suppress unused variable warning */
 144     (void)status;
 145
 146     while (1);
 147 }
 148
 149 UDMACC32XX_Object udmaCC3220SObject;
 150
 151 const UDMACC32XX_HWAttrs udmaCC3220SHWAttrs = {
 152     .controlBaseAddr = (void *)dmaControlTable,
 153     .dmaErrorFxn = (UDMACC32XX_ErrorFxn)dmaErrorFxn,
 154     .intNum = INT_UDMAERR,
 155     .intPriority = (~0)
 156 };
 157
 158 const UDMACC32XX_Config UDMACC32XX_config = {
 159     .object = &udmaCC3220SObject,
 160     .hwAttrs = &udmaCC3220SHWAttrs
 161 };
 162
 163 /*
 164  *  =============================== General ===============================
 165  */
 166 /*
 167  *  ======== CC3220SF_LAUNCHXL_initGeneral ========
 168  */
 169 void CC3220SF_LAUNCHXL_initGeneral(void)
 170 {
 171     PRCMCC3200MCUInit();
 172     Power_init();
 173 }
 174
 175 /*
 176  *  =============================== GPIO ===============================
 177  */
 178 #include <ti/drivers/GPIO.h>
 179 #include <ti/drivers/gpio/GPIOCC32XX.h>
 180
 181 /*
 182  * Array of Pin configurations
 183  * NOTE: The order of the pin configurations must coincide with what was
 184  *       defined in CC3220SF_LAUNCHXL.h
 185  * NOTE: Pins not used for interrupts should be placed at the end of the
 186  *       array.  Callback entries can be omitted from callbacks array to
 187  *       reduce memory usage.
 188  */
 189 GPIO_PinConfig gpioPinConfigs[] = {
 190     /* input pins with callbacks */
 191     /* CC3220SF_LAUNCHXL_GPIO_SW2 */
 192     GPIOCC32XX_GPIO_22 | GPIO_CFG_INPUT | GPIO_CFG_IN_INT_RISING,
 193     /* CC3220SF_LAUNCHXL_GPIO_SW3 */
 194     GPIOCC32XX_GPIO_13 | GPIO_CFG_INPUT | GPIO_CFG_IN_INT_RISING,
 195
 196     /* output pins */
 197     /* CC3220SF_LAUNCHXL_GPIO_LED_D7 */
 198     GPIOCC32XX_GPIO_09 | GPIO_CFG_OUT_STD | GPIO_CFG_OUT_STR_HIGH | GPIO_CFG_OUT_LOW,
 199
 200     /*
 201      *  CC3220SF_LAUNCHXL_GPIO_LED_D5 and CC3220SF_LAUNCHXL_GPIO_LED_D6 are shared with the
 202      *  I2C and PWM peripherals. In order for those examples to work, these
 203      *  LEDs are taken out of gpioPinCOnfig[]
 204      */
 205     /* CC3220SF_LAUNCHXL_GPIO_LED_D6 */
 206     //GPIOCC32XX_GPIO_10 | GPIO_CFG_OUT_STD | GPIO_CFG_OUT_STR_HIGH | GPIO_CFG_OUT_LOW,
 207     /* CC3220SF_LAUNCHXL_GPIO_LED_D5 */
 208     //GPIOCC32XX_GPIO_11 | GPIO_CFG_OUT_STD | GPIO_CFG_OUT_STR_HIGH | GPIO_CFG_OUT_LOW,
 209 };
 210
 211 /*
 212  * Array of callback function pointers
 213  * NOTE: The order of the pin configurations must coincide with what was
 214  *       defined in CC3220SF_LAUNCHXL.h
 215  * NOTE: Pins not used for interrupts can be omitted from callbacks array to
 216  *       reduce memory usage (if placed at end of gpioPinConfigs array).
 217  */
 218 GPIO_CallbackFxn gpioCallbackFunctions[] = {
 219     NULL,  /* CC3220SF_LAUNCHXL_GPIO_SW2 */
 220     NULL   /* CC3220SF_LAUNCHXL_GPIO_SW3 */
 221 };
 222
 223 /* The device-specific GPIO_config structure */
 224 const GPIOCC32XX_Config GPIOCC32XX_config = {
 225     .pinConfigs = (GPIO_PinConfig *)gpioPinConfigs,
 226     .callbacks = (GPIO_CallbackFxn *)gpioCallbackFunctions,
 227     .numberOfPinConfigs = sizeof(gpioPinConfigs)/sizeof(GPIO_PinConfig),
 228     .numberOfCallbacks = sizeof(gpioCallbackFunctions)/sizeof(GPIO_CallbackFxn),
 229     .intPriority = (~0)
 230 };
 231
 232 /*
 233  *  ============================= Display =============================
 234  */
 235 #if 0 /*_RB_*/
 236 #include <ti/display/Display.h>
 237 #include <ti/display/DisplayUart.h>
 238 #define MAXPRINTLEN 1024
 239
 240 DisplayUart_Object displayUartObject;
 241
 242 static char displayBuf[MAXPRINTLEN];
 243
 244 const DisplayUart_HWAttrs displayUartHWAttrs = {
 245     .uartIdx = 0,
 246     .baudRate = 115200,
 247     .mutexTimeout = (unsigned int)(-1),
 248     .strBuf = displayBuf,
 249     .strBufLen = MAXPRINTLEN
 250 };
 251
 252 #ifndef BOARD_DISPLAY_USE_UART_ANSI
 253 #define BOARD_DISPLAY_USE_UART_ANSI 0
 254 #endif
 255
 256 const Display_Config Display_config[] = {
 257     {
 258 #  if (BOARD_DISPLAY_USE_UART_ANSI)
 259         .fxnTablePtr = &DisplayUartAnsi_fxnTable,
 260 #  else /* Default to minimal UART with no cursor placement */
 261         .fxnTablePtr = &DisplayUartMin_fxnTable,
 262 #  endif
 263         .object = &displayUartObject,
 264         .hwAttrs = &displayUartHWAttrs
 265     }
 266 };
 267
 268 const uint_least8_t Display_count = sizeof(Display_config) / sizeof(Display_Config);
 269 #endif /* 0 _RB_ */
 270 /*
 271  *  =============================== I2C ===============================
 272  */
 273 #include <ti/drivers/I2C.h>
 274 #include <ti/drivers/i2c/I2CCC32XX.h>
 275
 276 I2CCC32XX_Object i2cCC3220SObjects[CC3220SF_LAUNCHXL_I2CCOUNT];
 277
 278 const I2CCC32XX_HWAttrsV1 i2cCC3220SHWAttrs[CC3220SF_LAUNCHXL_I2CCOUNT] = {
 279     {
 280         .baseAddr = I2CA0_BASE,
 281         .intNum = INT_I2CA0,
 282         .intPriority = (~0),
 283         .clkPin = I2CCC32XX_PIN_01_I2C_SCL,
 284         .dataPin = I2CCC32XX_PIN_02_I2C_SDA
 285     }
 286 };
 287
 288 const I2C_Config I2C_config[CC3220SF_LAUNCHXL_I2CCOUNT] = {
 289     {
 290         .fxnTablePtr = &I2CCC32XX_fxnTable,
 291         .object = &i2cCC3220SObjects[CC3220SF_LAUNCHXL_I2C0],
 292         .hwAttrs = &i2cCC3220SHWAttrs[CC3220SF_LAUNCHXL_I2C0]
 293     }
 294 };
 295
 296 const uint_least8_t I2C_count = CC3220SF_LAUNCHXL_I2CCOUNT;
 297
 298 /*
 299  *  =============================== I2S ===============================
 300  */
 301 #include <ti/drivers/I2S.h>
 302 #include <ti/drivers/i2s/I2SCC32XXDMA.h>
 303
 304 I2SCC32XXDMA_Object i2sCC3220SObjects[CC3220SF_LAUNCHXL_I2SCOUNT];
 305
 306 const I2SCC32XXDMA_HWAttrsV1 i2sCC3220SHWAttrs[CC3220SF_LAUNCHXL_I2SCOUNT] = {
 307     {
 308         .baseAddr = I2S_BASE,
 309         .intNum = INT_I2S,
 310         .intPriority = (~0),
 311         .rxChannelIndex = UDMA_CH4_I2S_RX,
 312         .txChannelIndex = UDMA_CH5_I2S_TX,
 313         .xr0Pin = I2SCC32XXDMA_PIN_64_McAXR0,
 314         .xr1Pin = I2SCC32XXDMA_PIN_50_McAXR1,
 315         .clkxPin = I2SCC32XXDMA_PIN_62_McACLKX,
 316         .clkPin = I2SCC32XXDMA_PIN_53_McACLK,
 317         .fsxPin = I2SCC32XXDMA_PIN_63_McAFSX,
 318     }
 319 };
 320
 321 const I2S_Config I2S_config[CC3220SF_LAUNCHXL_I2SCOUNT] = {
 322     {
 323         .fxnTablePtr = &I2SCC32XXDMA_fxnTable,
 324         .object = &i2sCC3220SObjects[CC3220SF_LAUNCHXL_I2S0],
 325         .hwAttrs = &i2sCC3220SHWAttrs[CC3220SF_LAUNCHXL_I2S0]
 326     }
 327 };
 328
 329 const uint_least8_t I2S_count = CC3220SF_LAUNCHXL_I2SCOUNT;
 330
 331 /*
 332  *  =============================== Power ===============================
 333  */
 334 /*
 335  * This table defines the parking state to be set for each parkable pin
 336  * during LPDS. (Device pins must be parked during LPDS to achieve maximum
 337  * power savings.)  If the pin should be left unparked, specify the state
 338  * PowerCC32XX_DONT_PARK.  For example, for a UART TX pin, the device
 339  * will automatically park the pin in a high state during transition to LPDS,
 340  * so the Power Manager does not need to explictly park the pin.  So the
 341  * corresponding entries in this table should indicate PowerCC32XX_DONT_PARK.
 342  */
 343 PowerCC32XX_ParkInfo parkInfo[] = {
 344 /*          PIN                    PARK STATE              PIN ALIAS (FUNCTION)
 345      -----------------  ------------------------------     -------------------- */
 346     {PowerCC32XX_PIN01, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO10              */
 347     {PowerCC32XX_PIN02, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO11              */
 348     {PowerCC32XX_PIN03, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO12              */
 349     {PowerCC32XX_PIN04, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO13              */
 350     {PowerCC32XX_PIN05, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO14              */
 351     {PowerCC32XX_PIN06, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO15              */
 352     {PowerCC32XX_PIN07, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO16              */
 353     {PowerCC32XX_PIN08, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO17              */
 354     {PowerCC32XX_PIN13, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* FLASH_SPI_DIN       */
 355     {PowerCC32XX_PIN15, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO22              */
 356     {PowerCC32XX_PIN16, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* TDI (JTAG DEBUG)    */
 357     {PowerCC32XX_PIN17, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* TDO (JTAG DEBUG)    */
 358     {PowerCC32XX_PIN19, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* TCK (JTAG DEBUG)    */
 359     {PowerCC32XX_PIN20, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* TMS (JTAG DEBUG)    */
 360     {PowerCC32XX_PIN18, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO28              */
 361     {PowerCC32XX_PIN21, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* SOP2                */
 362     {PowerCC32XX_PIN29, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* ANTSEL1             */
 363     {PowerCC32XX_PIN30, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* ANTSEL2             */
 364     {PowerCC32XX_PIN45, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* DCDC_ANA2_SW_P      */
 365     {PowerCC32XX_PIN50, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO0               */
 366     {PowerCC32XX_PIN52, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* RTC_XTAL_N          */
 367     {PowerCC32XX_PIN53, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO30              */
 368     {PowerCC32XX_PIN55, PowerCC32XX_WEAK_PULL_UP_STD},   /* GPIO1 (UART0_TX)    */
 369     {PowerCC32XX_PIN57, PowerCC32XX_WEAK_PULL_UP_STD},   /* GPIO2               */
 370     {PowerCC32XX_PIN58, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO3               */
 371     {PowerCC32XX_PIN59, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO4               */
 372     {PowerCC32XX_PIN60, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO5               */
 373     {PowerCC32XX_PIN61, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO6               */
 374     {PowerCC32XX_PIN62, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO7               */
 375     {PowerCC32XX_PIN63, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO8               */
 376     {PowerCC32XX_PIN64, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO9               */
 377 };
 378
 379 /*
 380  *  This structure defines the configuration for the Power Manager.
 381  *
 382  *  In this configuration the Power policy is disabled by default (because
 383  *  enablePolicy is set to false).  The Power policy can be enabled dynamically
 384  *  at runtime by calling Power_enablePolicy(), or at build time, by changing
 385  *  enablePolicy to true in this structure.
 386  */
 387 const PowerCC32XX_ConfigV1 PowerCC32XX_config = {
 388     .policyInitFxn = &PowerCC32XX_initPolicy,
 389     .policyFxn = &PowerCC32XX_sleepPolicy,
 390     .enterLPDSHookFxn = NULL,
 391     .resumeLPDSHookFxn = NULL,
 392     .enablePolicy = false,
 393     .enableGPIOWakeupLPDS = true,
 394     .enableGPIOWakeupShutdown = false,
 395     .enableNetworkWakeupLPDS = true,
 396     .wakeupGPIOSourceLPDS = PRCM_LPDS_GPIO13,
 397     .wakeupGPIOTypeLPDS = PRCM_LPDS_FALL_EDGE,
 398     .wakeupGPIOFxnLPDS = NULL,
 399     .wakeupGPIOFxnLPDSArg = 0,
 400     .wakeupGPIOSourceShutdown = 0,
 401     .wakeupGPIOTypeShutdown = 0,
 402     .ramRetentionMaskLPDS = PRCM_SRAM_COL_1 | PRCM_SRAM_COL_2 |
 403         PRCM_SRAM_COL_3 | PRCM_SRAM_COL_4,
 404     .keepDebugActiveDuringLPDS = false,
 405     .ioRetentionShutdown = PRCM_IO_RET_GRP_1,
 406     .pinParkDefs = parkInfo,
 407     .numPins = sizeof(parkInfo) / sizeof(PowerCC32XX_ParkInfo)
 408 };
 409
 410 /*
 411  *  =============================== PWM ===============================
 412  */
 413 #include <ti/drivers/PWM.h>
 414 #include <ti/drivers/pwm/PWMTimerCC32XX.h>
 415
 416 PWMTimerCC32XX_Object pwmTimerCC3220SObjects[CC3220SF_LAUNCHXL_PWMCOUNT];
 417
 418 const PWMTimerCC32XX_HWAttrsV2 pwmTimerCC3220SHWAttrs[CC3220SF_LAUNCHXL_PWMCOUNT] = {
 419     {    /* CC3220SF_LAUNCHXL_PWM6 */
 420         .pwmPin = PWMTimerCC32XX_PIN_01
 421     },
 422     {    /* CC3220SF_LAUNCHXL_PWM7 */
 423         .pwmPin = PWMTimerCC32XX_PIN_02
 424     }
 425 };
 426
 427 const PWM_Config PWM_config[CC3220SF_LAUNCHXL_PWMCOUNT] = {
 428     {
 429         .fxnTablePtr = &PWMTimerCC32XX_fxnTable,
 430         .object = &pwmTimerCC3220SObjects[CC3220SF_LAUNCHXL_PWM6],
 431         .hwAttrs = &pwmTimerCC3220SHWAttrs[CC3220SF_LAUNCHXL_PWM6]
 432     },
 433     {
 434         .fxnTablePtr = &PWMTimerCC32XX_fxnTable,
 435         .object = &pwmTimerCC3220SObjects[CC3220SF_LAUNCHXL_PWM7],
 436         .hwAttrs = &pwmTimerCC3220SHWAttrs[CC3220SF_LAUNCHXL_PWM7]
 437     }
 438 };
 439
 440 const uint_least8_t PWM_count = CC3220SF_LAUNCHXL_PWMCOUNT;
 441
 442 /*
 443  *  =============================== SDFatFS ===============================
 444  */
 445 #if 0 /*_RB_*/
 446 #include <ti/drivers/SD.h>
 447 #include <ti/drivers/SDFatFS.h>
 448
 449 /* Note: The SDFatFS and SD drivers must use the same count */
 450 SDFatFS_Object sdfatfsObjects[CC3220SF_LAUNCHXL_SDFatFSCOUNT];
 451
 452 const SDFatFS_Config SDFatFS_config[CC3220SF_LAUNCHXL_SDFatFSCOUNT] = {
 453     {
 454         .object = &sdfatfsObjects[CC3220SF_LAUNCHXL_SDFatFS0]
 455     }
 456 };
 457
 458 const uint_least8_t SDFatFS_count = CC3220SF_LAUNCHXL_SDFatFSCOUNT;
 459
 460 /*
 461  *  =============================== SD ===============================
 462  */
 463 #include <ti/drivers/SD.h>
 464 #include <ti/drivers/sd/SDHostCC32XX.h>
 465
 466 SDHostCC32XX_Object sdhostCC3220SObjects[CC3220SF_LAUNCHXL_SDCOUNT];
 467
 468 /* SDHost configuration structure, describing which pins are to be used */
 469 const SDHostCC32XX_HWAttrsV1 sdhostCC3220SHWattrs[CC3220SF_LAUNCHXL_SDCOUNT] = {
 470     {
 471         .clkRate = 8000000,
 472         .intPriority = ~0,
 473         .baseAddr = SDHOST_BASE,
 474         .rxChIdx = UDMA_CH23_SDHOST_RX,
 475         .txChIdx = UDMA_CH24_SDHOST_TX,
 476         .dataPin = SDHostCC32XX_PIN_06_SDCARD_DATA,
 477         .cmdPin = SDHostCC32XX_PIN_08_SDCARD_CMD,
 478         .clkPin = SDHostCC32XX_PIN_07_SDCARD_CLK
 479     }
 480 };
 481
 482 const SD_Config SD_config[CC3220SF_LAUNCHXL_SDCOUNT] = {
 483     {
 484         .fxnTablePtr = &sdHostCC32XX_fxnTable,
 485         .object = &sdhostCC3220SObjects[CC3220SF_LAUNCHXL_SD0],
 486         .hwAttrs = &sdhostCC3220SHWattrs[CC3220SF_LAUNCHXL_SD0]
 487     },
 488 };
 489
 490 const uint_least8_t SD_count = CC3220SF_LAUNCHXL_SDCOUNT;
 491
 492 /*
 493  *  =============================== SDSPI ===============================
 494  */
 495 #include <ti/drivers/SDSPI.h>
 496 #include <ti/drivers/sdspi/SDSPICC32XX.h>
 497
 498 SDSPICC32XX_Object sdspiCC3220SObjects[CC3220SF_LAUNCHXL_SDSPICOUNT];
 499
 500 /* SDSPI configuration structure, describing which pins are to be used */
 501 const SDSPICC32XX_HWAttrsV1 sdspiCC3220SHWattrs[CC3220SF_LAUNCHXL_SDSPICOUNT] = {
 502     {
 503         .baseAddr = GSPI_BASE,
 504         .spiPRCM = PRCM_GSPI,
 505         .clkPin = SDSPICC32XX_PIN_05_CLK,
 506         .mosiPin = SDSPICC32XX_PIN_07_MOSI,
 507         .misoPin = SDSPICC32XX_PIN_06_MISO,
 508         .csPin = SDSPICC32XX_PIN_62_GPIO
 509     }
 510 };
 511
 512 const SDSPI_Config SDSPI_config[CC3220SF_LAUNCHXL_SDSPICOUNT] = {
 513     {
 514         .fxnTablePtr = &SDSPICC32XX_fxnTable,
 515         .object = &sdspiCC3220SObjects[CC3220SF_LAUNCHXL_SDSPI0],
 516         .hwAttrs = &sdspiCC3220SHWattrs[CC3220SF_LAUNCHXL_SDSPI0]
 517     },
 518 };
 519
 520 const uint_least8_t SDSPI_count = CC3220SF_LAUNCHXL_SDSPICOUNT;
 521
 522 #endif /* 0 _RB_ */
 523 /*
 524  *  =============================== SPI ===============================
 525  */
 526 #include <ti/drivers/SPI.h>
 527 #include <ti/drivers/spi/SPICC32XXDMA.h>
 528
 529 SPICC32XXDMA_Object spiCC3220SDMAObjects[CC3220SF_LAUNCHXL_SPICOUNT];
 530
 531 #if defined(__TI_COMPILER_VERSION__)
 532 #pragma DATA_ALIGN(spiCC3220SDMAscratchBuf, 32)
 533 #elif defined(__IAR_SYSTEMS_ICC__)
 534 #pragma data_alignment=32
 535 #elif defined(__GNUC__)
 536 __attribute__ ((aligned (32)))
 537 #endif
 538 uint32_t spiCC3220SDMAscratchBuf[CC3220SF_LAUNCHXL_SPICOUNT];
 539
 540 const SPICC32XXDMA_HWAttrsV1 spiCC3220SDMAHWAttrs[CC3220SF_LAUNCHXL_SPICOUNT] = {
 541     /* index 0 is reserved for LSPI that links to the NWP */
 542     {
 543         .baseAddr = LSPI_BASE,
 544         .intNum = INT_LSPI,
 545         .intPriority = (~0),
 546         .spiPRCM = PRCM_LSPI,
 547         .csControl = SPI_SW_CTRL_CS,
 548         .csPolarity = SPI_CS_ACTIVEHIGH,
 549         .pinMode = SPI_4PIN_MODE,
 550         .turboMode = SPI_TURBO_OFF,
 551         .scratchBufPtr = &spiCC3220SDMAscratchBuf[CC3220SF_LAUNCHXL_SPI0],
 552         .defaultTxBufValue = 0,
 553         .rxChannelIndex = UDMA_CH12_LSPI_RX,
 554         .txChannelIndex = UDMA_CH13_LSPI_TX,
 555         .minDmaTransferSize = 100,
 556         .mosiPin = SPICC32XXDMA_PIN_NO_CONFIG,
 557         .misoPin = SPICC32XXDMA_PIN_NO_CONFIG,
 558         .clkPin = SPICC32XXDMA_PIN_NO_CONFIG,
 559         .csPin = SPICC32XXDMA_PIN_NO_CONFIG
 560     },
 561     {
 562         .baseAddr = GSPI_BASE,
 563         .intNum = INT_GSPI,
 564         .intPriority = (~0),
 565         .spiPRCM = PRCM_GSPI,
 566         .csControl = SPI_HW_CTRL_CS,
 567         .csPolarity = SPI_CS_ACTIVELOW,
 568         .pinMode = SPI_4PIN_MODE,
 569         .turboMode = SPI_TURBO_OFF,
 570         .scratchBufPtr = &spiCC3220SDMAscratchBuf[CC3220SF_LAUNCHXL_SPI1],
 571         .defaultTxBufValue = 0,
 572         .rxChannelIndex = UDMA_CH6_GSPI_RX,
 573         .txChannelIndex = UDMA_CH7_GSPI_TX,
 574         .minDmaTransferSize = 100,
 575         .mosiPin = SPICC32XXDMA_PIN_07_MOSI,
 576         .misoPin = SPICC32XXDMA_PIN_06_MISO,
 577         .clkPin = SPICC32XXDMA_PIN_05_CLK,
 578         .csPin = SPICC32XXDMA_PIN_08_CS
 579     }
 580 };
 581
 582 const SPI_Config SPI_config[CC3220SF_LAUNCHXL_SPICOUNT] = {
 583     {
 584         .fxnTablePtr = &SPICC32XXDMA_fxnTable,
 585         .object = &spiCC3220SDMAObjects[CC3220SF_LAUNCHXL_SPI0],
 586         .hwAttrs = &spiCC3220SDMAHWAttrs[CC3220SF_LAUNCHXL_SPI0]
 587     },
 588     {
 589         .fxnTablePtr = &SPICC32XXDMA_fxnTable,
 590         .object = &spiCC3220SDMAObjects[CC3220SF_LAUNCHXL_SPI1],
 591         .hwAttrs = &spiCC3220SDMAHWAttrs[CC3220SF_LAUNCHXL_SPI1]
 592     }
 593 };
 594
 595 const uint_least8_t SPI_count = CC3220SF_LAUNCHXL_SPICOUNT;
 596
 597 /*
 598  *  =============================== UART ===============================
 599  */
 600 #include <ti/drivers/UART.h>
 601 #if TI_DRIVERS_UART_DMA
 602 #include <ti/drivers/uart/UARTCC32XXDMA.h>
 603
 604 UARTCC32XXDMA_Object uartCC3220SDmaObjects[CC3220SF_LAUNCHXL_UARTCOUNT];
 605
 606 /* UART configuration structure */
 607 const UARTCC32XXDMA_HWAttrsV1 uartCC3220SDmaHWAttrs[CC3220SF_LAUNCHXL_UARTCOUNT] = {
 608     {
 609         .baseAddr = UARTA0_BASE,
 610         .intNum = INT_UARTA0,
 611         .intPriority = (~0),
 612         .rxChannelIndex = UDMA_CH8_UARTA0_RX,
 613         .txChannelIndex = UDMA_CH9_UARTA0_TX,
 614         .rxPin = UARTCC32XXDMA_PIN_57_UART0_RX,
 615         .txPin = UARTCC32XXDMA_PIN_55_UART0_TX
 616     },
 617     {
 618         .baseAddr = UARTA1_BASE,
 619         .intNum = INT_UARTA1,
 620         .intPriority = (~0),
 621         .rxChannelIndex = UDMA_CH10_UARTA1_RX,
 622         .txChannelIndex = UDMA_CH11_UARTA1_TX,
 623         .rxPin = UARTCC32XXDMA_PIN_08_UART1_RX,
 624         .txPin = UARTCC32XXDMA_PIN_07_UART1_TX
 625     }
 626 };
 627
 628 const UART_Config UART_config[CC3220SF_LAUNCHXL_UARTCOUNT] = {
 629     {
 630         .fxnTablePtr = &UARTCC32XXDMA_fxnTable,
 631         .object = &uartCC3220SDmaObjects[CC3220SF_LAUNCHXL_UART0],
 632         .hwAttrs = &uartCC3220SDmaHWAttrs[CC3220SF_LAUNCHXL_UART0]
 633     },
 634     {
 635         .fxnTablePtr = &UARTCC32XXDMA_fxnTable,
 636         .object = &uartCC3220SDmaObjects[CC3220SF_LAUNCHXL_UART1],
 637         .hwAttrs = &uartCC3220SDmaHWAttrs[CC3220SF_LAUNCHXL_UART1]
 638     }
 639 };
 640
 641 #else
 642 #include <ti/drivers/uart/UARTCC32XX.h>
 643
 644 UARTCC32XX_Object uartCC3220SObjects[CC3220SF_LAUNCHXL_UARTCOUNT];
 645 unsigned char uartCC3220SRingBuffer[CC3220SF_LAUNCHXL_UARTCOUNT][32];
 646
 647 /* UART configuration structure */
 648 const UARTCC32XX_HWAttrsV1 uartCC3220SHWAttrs[CC3220SF_LAUNCHXL_UARTCOUNT] = {
 649     {
 650         .baseAddr = UARTA0_BASE,
 651         .intNum = INT_UARTA0,
 652         .intPriority = (~0),
 653         .flowControl = UART_FLOWCONTROL_NONE,
 654         .ringBufPtr  = uartCC3220SRingBuffer[CC3220SF_LAUNCHXL_UART0],
 655         .ringBufSize = sizeof(uartCC3220SRingBuffer[CC3220SF_LAUNCHXL_UART0]),
 656         .rxPin = UARTCC32XX_PIN_57_UART0_RX,
 657         .txPin = UARTCC32XX_PIN_55_UART0_TX
 658     },
 659     {
 660         .baseAddr = UARTA1_BASE,
 661         .intNum = INT_UARTA1,
 662         .intPriority = (~0),
 663         .flowControl = UART_FLOWCONTROL_NONE,
 664         .ringBufPtr  = uartCC3220SRingBuffer[CC3220SF_LAUNCHXL_UART1],
 665         .ringBufSize = sizeof(uartCC3220SRingBuffer[CC3220SF_LAUNCHXL_UART1]),
 666         .rxPin = UARTCC32XX_PIN_08_UART1_RX,
 667         .txPin = UARTCC32XX_PIN_07_UART1_TX
 668     }
 669 };
 670
 671 const UART_Config UART_config[CC3220SF_LAUNCHXL_UARTCOUNT] = {
 672     {
 673         .fxnTablePtr = &UARTCC32XX_fxnTable,
 674         .object = &uartCC3220SObjects[CC3220SF_LAUNCHXL_UART0],
 675         .hwAttrs = &uartCC3220SHWAttrs[CC3220SF_LAUNCHXL_UART0]
 676     },
 677     {
 678         .fxnTablePtr = &UARTCC32XX_fxnTable,
 679         .object = &uartCC3220SObjects[CC3220SF_LAUNCHXL_UART1],
 680         .hwAttrs = &uartCC3220SHWAttrs[CC3220SF_LAUNCHXL_UART1]
 681     }
 682 };
 683 #endif /* TI_DRIVERS_UART_DMA */
 684
 685 const uint_least8_t UART_count = CC3220SF_LAUNCHXL_UARTCOUNT;
 686
 687 /*
 688  *  =============================== Watchdog ===============================
 689  */
 690 #include <ti/drivers/Watchdog.h>
 691 #include <ti/drivers/watchdog/WatchdogCC32XX.h>
 692
 693 WatchdogCC32XX_Object watchdogCC3220SObjects[CC3220SF_LAUNCHXL_WATCHDOGCOUNT];
 694
 695 const WatchdogCC32XX_HWAttrs watchdogCC3220SHWAttrs[CC3220SF_LAUNCHXL_WATCHDOGCOUNT] = {
 696     {
 697         .baseAddr = WDT_BASE,
 698         .intNum = INT_WDT,
 699         .intPriority = (~0),
 700         .reloadValue = 80000000 // 1 second period at default CPU clock freq
 701     }
 702 };
 703
 704 const Watchdog_Config Watchdog_config[CC3220SF_LAUNCHXL_WATCHDOGCOUNT] = {
 705     {
 706         .fxnTablePtr = &WatchdogCC32XX_fxnTable,
 707         .object = &watchdogCC3220SObjects[CC3220SF_LAUNCHXL_WATCHDOG0],
 708         .hwAttrs = &watchdogCC3220SHWAttrs[CC3220SF_LAUNCHXL_WATCHDOG0]
 709     }
 710 };
 711
 712 const uint_least8_t Watchdog_count = CC3220SF_LAUNCHXL_WATCHDOGCOUNT;
 713
 714 #if defined(__SF_DEBUG__)
 715 #if defined(__TI_COMPILER_VERSION__)
 716 #pragma DATA_SECTION(ulDebugHeader, ".dbghdr")
 717 #elif defined(__IAR_SYSTEMS_ICC__)
 718 #pragma data_location=".dbghdr"
 719 #elif defined(__GNUC__)
 720 __attribute__ ((section (".dbghdr")))
 721 #endif
 722 const unsigned long ulDebugHeader[]=
 723 {
 724                 0x5AA5A55A,
 725                 0x000FF800,
 726                 0xEFA3247D
 727 };
 728 #endif