2 * -------------------------------------------
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3 * CC3220 SDK - v0.10.00.00
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4 * -------------------------------------------
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6 * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/
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8 * Redistribution and use in source and binary forms, with or without
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9 * modification, are permitted provided that the following conditions
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12 * Redistributions of source code must retain the above copyright
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13 * notice, this list of conditions and the following disclaimer.
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15 * Redistributions in binary form must reproduce the above copyright
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16 * notice, this list of conditions and the following disclaimer in the
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17 * documentation and/or other materials provided with the
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20 * Neither the name of Texas Instruments Incorporated nor the names of
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21 * its contributors may be used to endorse or promote products derived
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22 * from this software without specific prior written permission.
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24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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25 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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26 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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27 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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28 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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29 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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30 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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31 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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32 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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33 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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34 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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38 #ifndef __HW_APPS_RCM_H__
\r
39 #define __HW_APPS_RCM_H__
\r
41 //*****************************************************************************
\r
43 // The following are defines for the APPS_RCM register offsets.
\r
45 //*****************************************************************************
\r
46 #define APPS_RCM_O_CAMERA_CLK_GEN \
\r
49 #define APPS_RCM_O_CAMERA_CLK_GATING \
\r
52 #define APPS_RCM_O_CAMERA_SOFT_RESET \
\r
55 #define APPS_RCM_O_MCASP_CLK_GATING \
\r
58 #define APPS_RCM_O_MCASP_SOFT_RESET \
\r
61 #define APPS_RCM_O_MMCHS_CLK_GEN \
\r
64 #define APPS_RCM_O_MMCHS_CLK_GATING \
\r
67 #define APPS_RCM_O_MMCHS_SOFT_RESET \
\r
70 #define APPS_RCM_O_MCSPI_A1_CLK_GEN \
\r
73 #define APPS_RCM_O_MCSPI_A1_CLK_GATING \
\r
76 #define APPS_RCM_O_MCSPI_A1_SOFT_RESET \
\r
79 #define APPS_RCM_O_MCSPI_A2_CLK_GEN \
\r
82 #define APPS_RCM_O_MCSPI_A2_CLK_GATING \
\r
85 #define APPS_RCM_O_MCSPI_A2_SOFT_RESET \
\r
88 #define APPS_RCM_O_UDMA_A_CLK_GATING \
\r
91 #define APPS_RCM_O_UDMA_A_SOFT_RESET \
\r
94 #define APPS_RCM_O_GPIO_A_CLK_GATING \
\r
97 #define APPS_RCM_O_GPIO_A_SOFT_RESET \
\r
100 #define APPS_RCM_O_GPIO_B_CLK_GATING \
\r
103 #define APPS_RCM_O_GPIO_B_SOFT_RESET \
\r
106 #define APPS_RCM_O_GPIO_C_CLK_GATING \
\r
109 #define APPS_RCM_O_GPIO_C_SOFT_RESET \
\r
112 #define APPS_RCM_O_GPIO_D_CLK_GATING \
\r
115 #define APPS_RCM_O_GPIO_D_SOFT_RESET \
\r
118 #define APPS_RCM_O_GPIO_E_CLK_GATING \
\r
121 #define APPS_RCM_O_GPIO_E_SOFT_RESET \
\r
124 #define APPS_RCM_O_WDOG_A_CLK_GATING \
\r
127 #define APPS_RCM_O_WDOG_A_SOFT_RESET \
\r
130 #define APPS_RCM_O_UART_A0_CLK_GATING \
\r
133 #define APPS_RCM_O_UART_A0_SOFT_RESET \
\r
136 #define APPS_RCM_O_UART_A1_CLK_GATING \
\r
139 #define APPS_RCM_O_UART_A1_SOFT_RESET \
\r
142 #define APPS_RCM_O_GPT_A0_CLK_GATING \
\r
145 #define APPS_RCM_O_GPT_A0_SOFT_RESET \
\r
148 #define APPS_RCM_O_GPT_A1_CLK_GATING \
\r
151 #define APPS_RCM_O_GPT_A1_SOFT_RESET \
\r
154 #define APPS_RCM_O_GPT_A2_CLK_GATING \
\r
157 #define APPS_RCM_O_GPT_A2_SOFT_RESET \
\r
160 #define APPS_RCM_O_GPT_A3_CLK_GATING \
\r
163 #define APPS_RCM_O_GPT_A3_SOFT_RESET \
\r
166 #define APPS_RCM_O_MCASP_FRAC_CLK_CONFIG0 \
\r
169 #define APPS_RCM_O_MCASP_FRAC_CLK_CONFIG1 \
\r
172 #define APPS_RCM_O_CRYPTO_CLK_GATING \
\r
175 #define APPS_RCM_O_CRYPTO_SOFT_RESET \
\r
178 #define APPS_RCM_O_MCSPI_S0_CLK_GATING \
\r
181 #define APPS_RCM_O_MCSPI_S0_SOFT_RESET \
\r
184 #define APPS_RCM_O_MCSPI_S0_CLKDIV_CFG \
\r
187 #define APPS_RCM_O_I2C_CLK_GATING \
\r
190 #define APPS_RCM_O_I2C_SOFT_RESET \
\r
193 #define APPS_RCM_O_APPS_LPDS_REQ \
\r
196 #define APPS_RCM_O_APPS_TURBO_REQ \
\r
199 #define APPS_RCM_O_APPS_DSLP_WAKE_CONFIG \
\r
202 #define APPS_RCM_O_APPS_DSLP_WAKE_TIMER_CFG \
\r
205 #define APPS_RCM_O_APPS_RCM_SLP_WAKE_ENABLE \
\r
208 #define APPS_RCM_O_APPS_SLP_WAKETIMER_CFG \
\r
211 #define APPS_RCM_O_APPS_TO_NWP_WAKE_REQUEST \
\r
214 #define APPS_RCM_O_APPS_RCM_INTERRUPT_STATUS \
\r
217 #define APPS_RCM_O_APPS_RCM_INTERRUPT_ENABLE \
\r
224 //******************************************************************************
\r
226 // The following are defines for the bit fields in the
\r
227 // APPS_RCM_O_CAMERA_CLK_GEN register.
\r
229 //******************************************************************************
\r
230 #define APPS_RCM_CAMERA_CLK_GEN_CAMERA_PLLCKDIV_OFF_TIME_M \
\r
231 0x00000700 // Configuration of OFF-TIME for
\r
232 // dividing PLL clk (240 MHz) in
\r
233 // generation of Camera func-clk :
\r
234 // "000" - 1 "001" - 2 "010" - 3
\r
235 // "011" - 4 "100" - 5 "101" - 6
\r
236 // "110" - 7 "111" - 8
\r
238 #define APPS_RCM_CAMERA_CLK_GEN_CAMERA_PLLCKDIV_OFF_TIME_S 8
\r
239 #define APPS_RCM_CAMERA_CLK_GEN_NU1_M \
\r
242 #define APPS_RCM_CAMERA_CLK_GEN_NU1_S 3
\r
243 #define APPS_RCM_CAMERA_CLK_GEN_CAMERA_PLLCKDIV_ON_TIME_M \
\r
244 0x00000007 // Configuration of ON-TIME for
\r
245 // dividing PLL clk (240 MHz) in
\r
246 // generation of Camera func-clk :
\r
247 // "000" - 1 "001" - 2 "010" - 3
\r
248 // "011" - 4 "100" - 5 "101" - 6
\r
249 // "110" - 7 "111" - 8
\r
251 #define APPS_RCM_CAMERA_CLK_GEN_CAMERA_PLLCKDIV_ON_TIME_S 0
\r
252 //******************************************************************************
\r
254 // The following are defines for the bit fields in the
\r
255 // APPS_RCM_O_CAMERA_CLK_GATING register.
\r
257 //******************************************************************************
\r
258 #define APPS_RCM_CAMERA_CLK_GATING_NU1_M \
\r
261 #define APPS_RCM_CAMERA_CLK_GATING_NU1_S 17
\r
262 #define APPS_RCM_CAMERA_CLK_GATING_CAMERA_DSLP_CLK_ENABLE \
\r
263 0x00010000 // 0 - Disable camera clk during
\r
266 #define APPS_RCM_CAMERA_CLK_GATING_NU2_M \
\r
269 #define APPS_RCM_CAMERA_CLK_GATING_NU2_S 9
\r
270 #define APPS_RCM_CAMERA_CLK_GATING_CAMERA_SLP_CLK_ENABLE \
\r
271 0x00000100 // 1- Enable camera clk during
\r
272 // sleep mode ; 0- Disable camera
\r
273 // clk during sleep mode
\r
275 #define APPS_RCM_CAMERA_CLK_GATING_NU3_M \
\r
278 #define APPS_RCM_CAMERA_CLK_GATING_NU3_S 1
\r
279 #define APPS_RCM_CAMERA_CLK_GATING_CAMERA_RUN_CLK_ENABLE \
\r
280 0x00000001 // 1- Enable camera clk during run
\r
281 // mode ; 0- Disable camera clk
\r
284 //******************************************************************************
\r
286 // The following are defines for the bit fields in the
\r
287 // APPS_RCM_O_CAMERA_SOFT_RESET register.
\r
289 //******************************************************************************
\r
290 #define APPS_RCM_CAMERA_SOFT_RESET_CAMERA_ENABLED_STATUS \
\r
291 0x00000002 // 1 - Camera clocks/resets are
\r
292 // enabled ; 0 - Camera
\r
293 // clocks/resets are disabled
\r
295 #define APPS_RCM_CAMERA_SOFT_RESET_CAMERA_SOFT_RESET \
\r
296 0x00000001 // 1 - Assert reset for Camera-core
\r
297 // ; 0 - De-assert reset for
\r
300 //******************************************************************************
\r
302 // The following are defines for the bit fields in the
\r
303 // APPS_RCM_O_MCASP_CLK_GATING register.
\r
305 //******************************************************************************
\r
306 #define APPS_RCM_MCASP_CLK_GATING_NU1_M \
\r
309 #define APPS_RCM_MCASP_CLK_GATING_NU1_S 17
\r
310 #define APPS_RCM_MCASP_CLK_GATING_MCASP_DSLP_CLK_ENABLE \
\r
311 0x00010000 // 0 - Disable MCASP clk during
\r
314 #define APPS_RCM_MCASP_CLK_GATING_NU2_M \
\r
317 #define APPS_RCM_MCASP_CLK_GATING_NU2_S 9
\r
318 #define APPS_RCM_MCASP_CLK_GATING_MCASP_SLP_CLK_ENABLE \
\r
319 0x00000100 // 1- Enable MCASP clk during sleep
\r
320 // mode ; 0- Disable MCASP clk
\r
321 // during sleep mode
\r
323 #define APPS_RCM_MCASP_CLK_GATING_NU3_M \
\r
326 #define APPS_RCM_MCASP_CLK_GATING_NU3_S 1
\r
327 #define APPS_RCM_MCASP_CLK_GATING_MCASP_RUN_CLK_ENABLE \
\r
328 0x00000001 // 1- Enable MCASP clk during run
\r
329 // mode ; 0- Disable MCASP clk
\r
332 //******************************************************************************
\r
334 // The following are defines for the bit fields in the
\r
335 // APPS_RCM_O_MCASP_SOFT_RESET register.
\r
337 //******************************************************************************
\r
338 #define APPS_RCM_MCASP_SOFT_RESET_MCASP_ENABLED_STATUS \
\r
339 0x00000002 // 1 - MCASP Clocks/resets are
\r
340 // enabled ; 0 - MCASP Clocks/resets
\r
343 #define APPS_RCM_MCASP_SOFT_RESET_MCASP_SOFT_RESET \
\r
344 0x00000001 // 1 - Assert reset for MCASP-core
\r
345 // ; 0 - De-assert reset for
\r
348 //******************************************************************************
\r
350 // The following are defines for the bit fields in the
\r
351 // APPS_RCM_O_MMCHS_CLK_GEN register.
\r
353 //******************************************************************************
\r
354 #define APPS_RCM_MMCHS_CLK_GEN_MMCHS_PLLCKDIV_OFF_TIME_M \
\r
355 0x00000700 // Configuration of OFF-TIME for
\r
356 // dividing PLL clk (240 MHz) in
\r
357 // generation of MMCHS func-clk :
\r
358 // "000" - 1 "001" - 2 "010" - 3
\r
359 // "011" - 4 "100" - 5 "101" - 6
\r
360 // "110" - 7 "111" - 8
\r
362 #define APPS_RCM_MMCHS_CLK_GEN_MMCHS_PLLCKDIV_OFF_TIME_S 8
\r
363 #define APPS_RCM_MMCHS_CLK_GEN_NU1_M \
\r
366 #define APPS_RCM_MMCHS_CLK_GEN_NU1_S 3
\r
367 #define APPS_RCM_MMCHS_CLK_GEN_MMCHS_PLLCKDIV_ON_TIME_M \
\r
368 0x00000007 // Configuration of ON-TIME for
\r
369 // dividing PLL clk (240 MHz) in
\r
370 // generation of MMCHS func-clk :
\r
371 // "000" - 1 "001" - 2 "010" - 3
\r
372 // "011" - 4 "100" - 5 "101" - 6
\r
373 // "110" - 7 "111" - 8
\r
375 #define APPS_RCM_MMCHS_CLK_GEN_MMCHS_PLLCKDIV_ON_TIME_S 0
\r
376 //******************************************************************************
\r
378 // The following are defines for the bit fields in the
\r
379 // APPS_RCM_O_MMCHS_CLK_GATING register.
\r
381 //******************************************************************************
\r
382 #define APPS_RCM_MMCHS_CLK_GATING_NU1_M \
\r
385 #define APPS_RCM_MMCHS_CLK_GATING_NU1_S 17
\r
386 #define APPS_RCM_MMCHS_CLK_GATING_MMCHS_DSLP_CLK_ENABLE \
\r
387 0x00010000 // 0 - Disable MMCHS clk during
\r
390 #define APPS_RCM_MMCHS_CLK_GATING_NU2_M \
\r
393 #define APPS_RCM_MMCHS_CLK_GATING_NU2_S 9
\r
394 #define APPS_RCM_MMCHS_CLK_GATING_MMCHS_SLP_CLK_ENABLE \
\r
395 0x00000100 // 1- Enable MMCHS clk during sleep
\r
396 // mode ; 0- Disable MMCHS clk
\r
397 // during sleep mode
\r
399 #define APPS_RCM_MMCHS_CLK_GATING_NU3_M \
\r
402 #define APPS_RCM_MMCHS_CLK_GATING_NU3_S 1
\r
403 #define APPS_RCM_MMCHS_CLK_GATING_MMCHS_RUN_CLK_ENABLE \
\r
404 0x00000001 // 1- Enable MMCHS clk during run
\r
405 // mode ; 0- Disable MMCHS clk
\r
408 //******************************************************************************
\r
410 // The following are defines for the bit fields in the
\r
411 // APPS_RCM_O_MMCHS_SOFT_RESET register.
\r
413 //******************************************************************************
\r
414 #define APPS_RCM_MMCHS_SOFT_RESET_MMCHS_ENABLED_STATUS \
\r
415 0x00000002 // 1 - MMCHS Clocks/resets are
\r
416 // enabled ; 0 - MMCHS Clocks/resets
\r
419 #define APPS_RCM_MMCHS_SOFT_RESET_MMCHS_SOFT_RESET \
\r
420 0x00000001 // 1 - Assert reset for MMCHS-core
\r
421 // ; 0 - De-assert reset for
\r
424 //******************************************************************************
\r
426 // The following are defines for the bit fields in the
\r
427 // APPS_RCM_O_MCSPI_A1_CLK_GEN register.
\r
429 //******************************************************************************
\r
430 #define APPS_RCM_MCSPI_A1_CLK_GEN_MCSPI_A1_BAUD_CLK_SEL \
\r
431 0x00010000 // 0 - XTAL clk is used as baud clk
\r
432 // for MCSPI_A1 ; 1 - PLL divclk is
\r
433 // used as baud clk for MCSPI_A1.
\r
435 #define APPS_RCM_MCSPI_A1_CLK_GEN_NU1_M \
\r
438 #define APPS_RCM_MCSPI_A1_CLK_GEN_NU1_S 11
\r
439 #define APPS_RCM_MCSPI_A1_CLK_GEN_MCSPI_A1_PLLCLKDIV_OFF_TIME_M \
\r
440 0x00000700 // Configuration of OFF-TIME for
\r
441 // dividing PLL clk (240 MHz) in
\r
442 // generation of MCSPI_A1 func-clk :
\r
443 // "000" - 1 "001" - 2 "010" - 3
\r
444 // "011" - 4 "100" - 5 "101" - 6
\r
445 // "110" - 7 "111" - 8
\r
447 #define APPS_RCM_MCSPI_A1_CLK_GEN_MCSPI_A1_PLLCLKDIV_OFF_TIME_S 8
\r
448 #define APPS_RCM_MCSPI_A1_CLK_GEN_NU2_M \
\r
451 #define APPS_RCM_MCSPI_A1_CLK_GEN_NU2_S 3
\r
452 #define APPS_RCM_MCSPI_A1_CLK_GEN_MCSPI_A1_PLLCLKDIV_ON_TIME_M \
\r
453 0x00000007 // Configuration of ON-TIME for
\r
454 // dividing PLL clk (240 MHz) in
\r
455 // generation of MCSPI_A1 func-clk :
\r
456 // "000" - 1 "001" - 2 "010" - 3
\r
457 // "011" - 4 "100" - 5 "101" - 6
\r
458 // "110" - 7 "111" - 8
\r
460 #define APPS_RCM_MCSPI_A1_CLK_GEN_MCSPI_A1_PLLCLKDIV_ON_TIME_S 0
\r
461 //******************************************************************************
\r
463 // The following are defines for the bit fields in the
\r
464 // APPS_RCM_O_MCSPI_A1_CLK_GATING register.
\r
466 //******************************************************************************
\r
467 #define APPS_RCM_MCSPI_A1_CLK_GATING_NU1_M \
\r
470 #define APPS_RCM_MCSPI_A1_CLK_GATING_NU1_S 17
\r
471 #define APPS_RCM_MCSPI_A1_CLK_GATING_MCSPI_A1_DSLP_CLK_ENABLE \
\r
472 0x00010000 // 0 - Disable MCSPI_A1 clk during
\r
475 #define APPS_RCM_MCSPI_A1_CLK_GATING_NU2_M \
\r
478 #define APPS_RCM_MCSPI_A1_CLK_GATING_NU2_S 9
\r
479 #define APPS_RCM_MCSPI_A1_CLK_GATING_MCSPI_A1_SLP_CLK_ENABLE \
\r
480 0x00000100 // 1- Enable MCSPI_A1 clk during
\r
481 // sleep mode ; 0- Disable MCSPI_A1
\r
482 // clk during sleep mode
\r
484 #define APPS_RCM_MCSPI_A1_CLK_GATING_NU3_M \
\r
487 #define APPS_RCM_MCSPI_A1_CLK_GATING_NU3_S 1
\r
488 #define APPS_RCM_MCSPI_A1_CLK_GATING_MCSPI_A1_RUN_CLK_ENABLE \
\r
489 0x00000001 // 1- Enable MCSPI_A1 clk during
\r
490 // run mode ; 0- Disable MCSPI_A1
\r
491 // clk during run mode
\r
493 //******************************************************************************
\r
495 // The following are defines for the bit fields in the
\r
496 // APPS_RCM_O_MCSPI_A1_SOFT_RESET register.
\r
498 //******************************************************************************
\r
499 #define APPS_RCM_MCSPI_A1_SOFT_RESET_MCSPI_A1_ENABLED_STATUS \
\r
500 0x00000002 // 1 - MCSPI_A1 Clocks/Resets are
\r
501 // enabled ; 0 - MCSPI_A1
\r
502 // Clocks/Resets are disabled
\r
504 #define APPS_RCM_MCSPI_A1_SOFT_RESET_MCSPI_A1_SOFT_RESET \
\r
505 0x00000001 // 1 - Assert reset for
\r
506 // MCSPI_A1-core ; 0 - De-assert
\r
507 // reset for MCSPI_A1-core
\r
509 //******************************************************************************
\r
511 // The following are defines for the bit fields in the
\r
512 // APPS_RCM_O_MCSPI_A2_CLK_GEN register.
\r
514 //******************************************************************************
\r
515 #define APPS_RCM_MCSPI_A2_CLK_GEN_MCSPI_A2_BAUD_CLK_SEL \
\r
516 0x00010000 // 0 - XTAL clk is used as baud-clk
\r
517 // for MCSPI_A2 ; 1 - PLL divclk is
\r
518 // used as baud-clk for MCSPI_A2
\r
520 #define APPS_RCM_MCSPI_A2_CLK_GEN_NU1_M \
\r
523 #define APPS_RCM_MCSPI_A2_CLK_GEN_NU1_S 11
\r
524 #define APPS_RCM_MCSPI_A2_CLK_GEN_MCSPI_A2_PLLCKDIV_OFF_TIME_M \
\r
525 0x00000700 // Configuration of OFF-TIME for
\r
526 // dividing PLL clk (240 MHz) in
\r
527 // generation of MCSPI_A2 func-clk :
\r
528 // "000" - 1 "001" - 2 "010" - 3
\r
529 // "011" - 4 "100" - 5 "101" - 6
\r
530 // "110" - 7 "111" - 8
\r
532 #define APPS_RCM_MCSPI_A2_CLK_GEN_MCSPI_A2_PLLCKDIV_OFF_TIME_S 8
\r
533 #define APPS_RCM_MCSPI_A2_CLK_GEN_NU2_M \
\r
536 #define APPS_RCM_MCSPI_A2_CLK_GEN_NU2_S 3
\r
537 #define APPS_RCM_MCSPI_A2_CLK_GEN_MCSPI_A2_PLLCKDIV_ON_TIME_M \
\r
538 0x00000007 // Configuration of OFF-TIME for
\r
539 // dividing PLL clk (240 MHz) in
\r
540 // generation of MCSPI_A2 func-clk :
\r
541 // "000" - 1 "001" - 2 "010" - 3
\r
542 // "011" - 4 "100" - 5 "101" - 6
\r
543 // "110" - 7 "111" - 8
\r
545 #define APPS_RCM_MCSPI_A2_CLK_GEN_MCSPI_A2_PLLCKDIV_ON_TIME_S 0
\r
546 //******************************************************************************
\r
548 // The following are defines for the bit fields in the
\r
549 // APPS_RCM_O_MCSPI_A2_CLK_GATING register.
\r
551 //******************************************************************************
\r
552 #define APPS_RCM_MCSPI_A2_CLK_GATING_NU1_M \
\r
555 #define APPS_RCM_MCSPI_A2_CLK_GATING_NU1_S 17
\r
556 #define APPS_RCM_MCSPI_A2_CLK_GATING_MCSPI_A2_DSLP_CLK_ENABLE \
\r
557 0x00010000 // 0 - Disable MCSPI_A2 clk during
\r
560 #define APPS_RCM_MCSPI_A2_CLK_GATING_NU2_M \
\r
563 #define APPS_RCM_MCSPI_A2_CLK_GATING_NU2_S 9
\r
564 #define APPS_RCM_MCSPI_A2_CLK_GATING_MCSPI_A2_SLP_CLK_ENABLE \
\r
565 0x00000100 // 1- Enable MCSPI_A2 clk during
\r
566 // sleep mode ; 0- Disable MCSPI_A2
\r
567 // clk during sleep mode
\r
569 #define APPS_RCM_MCSPI_A2_CLK_GATING_NU3_M \
\r
572 #define APPS_RCM_MCSPI_A2_CLK_GATING_NU3_S 1
\r
573 #define APPS_RCM_MCSPI_A2_CLK_GATING_MCSPI_A2_RUN_CLK_ENABLE \
\r
574 0x00000001 // 1- Enable MCSPI_A2 clk during
\r
575 // run mode ; 0- Disable MCSPI_A2
\r
576 // clk during run mode
\r
578 //******************************************************************************
\r
580 // The following are defines for the bit fields in the
\r
581 // APPS_RCM_O_MCSPI_A2_SOFT_RESET register.
\r
583 //******************************************************************************
\r
584 #define APPS_RCM_MCSPI_A2_SOFT_RESET_MCSPI_A2_ENABLED_STATUS \
\r
585 0x00000002 // 1 - MCSPI_A2 Clocks/Resets are
\r
586 // enabled ; 0 - MCSPI_A2
\r
587 // Clocks/Resets are disabled
\r
589 #define APPS_RCM_MCSPI_A2_SOFT_RESET_MCSPI_A2_SOFT_RESET \
\r
590 0x00000001 // 1 - Assert reset for
\r
591 // MCSPI_A2-core ; 0 - De-assert
\r
592 // reset for MCSPI_A2-core
\r
594 //******************************************************************************
\r
596 // The following are defines for the bit fields in the
\r
597 // APPS_RCM_O_UDMA_A_CLK_GATING register.
\r
599 //******************************************************************************
\r
600 #define APPS_RCM_UDMA_A_CLK_GATING_UDMA_A_DSLP_CLK_ENABLE \
\r
601 0x00010000 // 1 - Enable UDMA_A clk during
\r
602 // deep-sleep mode 0 - Disable
\r
603 // UDMA_A clk during deep-sleep mode
\r
606 #define APPS_RCM_UDMA_A_CLK_GATING_NU1_M \
\r
609 #define APPS_RCM_UDMA_A_CLK_GATING_NU1_S 9
\r
610 #define APPS_RCM_UDMA_A_CLK_GATING_UDMA_A_SLP_CLK_ENABLE \
\r
611 0x00000100 // 1 - Enable UDMA_A clk during
\r
612 // sleep mode 0 - Disable UDMA_A clk
\r
613 // during sleep mode ;
\r
615 #define APPS_RCM_UDMA_A_CLK_GATING_NU2_M \
\r
618 #define APPS_RCM_UDMA_A_CLK_GATING_NU2_S 1
\r
619 #define APPS_RCM_UDMA_A_CLK_GATING_UDMA_A_RUN_CLK_ENABLE \
\r
620 0x00000001 // 1 - Enable UDMA_A clk during run
\r
621 // mode 0 - Disable UDMA_A clk
\r
622 // during run mode ;
\r
624 //******************************************************************************
\r
626 // The following are defines for the bit fields in the
\r
627 // APPS_RCM_O_UDMA_A_SOFT_RESET register.
\r
629 //******************************************************************************
\r
630 #define APPS_RCM_UDMA_A_SOFT_RESET_UDMA_A_ENABLED_STATUS \
\r
631 0x00000002 // 1 - UDMA_A Clocks/Resets are
\r
632 // enabled ; 0 - UDMA_A
\r
633 // Clocks/Resets are disabled
\r
635 #define APPS_RCM_UDMA_A_SOFT_RESET_UDMA_A_SOFT_RESET \
\r
636 0x00000001 // 1 - Assert reset for DMA_A ; 0 -
\r
637 // De-assert reset for DMA_A
\r
639 //******************************************************************************
\r
641 // The following are defines for the bit fields in the
\r
642 // APPS_RCM_O_GPIO_A_CLK_GATING register.
\r
644 //******************************************************************************
\r
645 #define APPS_RCM_GPIO_A_CLK_GATING_GPIO_A_DSLP_CLK_ENABLE \
\r
646 0x00010000 // 1 - Enable GPIO_A clk during
\r
647 // deep-sleep mode 0 - Disable
\r
648 // GPIO_A clk during deep-sleep mode
\r
651 #define APPS_RCM_GPIO_A_CLK_GATING_NU1_M \
\r
654 #define APPS_RCM_GPIO_A_CLK_GATING_NU1_S 9
\r
655 #define APPS_RCM_GPIO_A_CLK_GATING_GPIO_A_SLP_CLK_ENABLE \
\r
656 0x00000100 // 1 - Enable GPIO_A clk during
\r
657 // sleep mode 0 - Disable GPIO_A clk
\r
658 // during sleep mode ;
\r
660 #define APPS_RCM_GPIO_A_CLK_GATING_NU2_M \
\r
663 #define APPS_RCM_GPIO_A_CLK_GATING_NU2_S 1
\r
664 #define APPS_RCM_GPIO_A_CLK_GATING_GPIO_A_RUN_CLK_ENABLE \
\r
665 0x00000001 // 1 - Enable GPIO_A clk during run
\r
666 // mode 0 - Disable GPIO_A clk
\r
667 // during run mode ;
\r
669 //******************************************************************************
\r
671 // The following are defines for the bit fields in the
\r
672 // APPS_RCM_O_GPIO_A_SOFT_RESET register.
\r
674 //******************************************************************************
\r
675 #define APPS_RCM_GPIO_A_SOFT_RESET_GPIO_A_ENABLED_STATUS \
\r
676 0x00000002 // 1 - GPIO_A Clocks/Resets are
\r
677 // enabled ; 0 - GPIO_A
\r
678 // Clocks/Resets are disabled
\r
680 #define APPS_RCM_GPIO_A_SOFT_RESET_GPIO_A_SOFT_RESET \
\r
681 0x00000001 // 1 - Assert reset for GPIO_A ; 0
\r
682 // - De-assert reset for GPIO_A
\r
684 //******************************************************************************
\r
686 // The following are defines for the bit fields in the
\r
687 // APPS_RCM_O_GPIO_B_CLK_GATING register.
\r
689 //******************************************************************************
\r
690 #define APPS_RCM_GPIO_B_CLK_GATING_GPIO_B_DSLP_CLK_ENABLE \
\r
691 0x00010000 // 1 - Enable GPIO_B clk during
\r
692 // deep-sleep mode 0 - Disable
\r
693 // GPIO_B clk during deep-sleep mode
\r
696 #define APPS_RCM_GPIO_B_CLK_GATING_NU1_M \
\r
699 #define APPS_RCM_GPIO_B_CLK_GATING_NU1_S 9
\r
700 #define APPS_RCM_GPIO_B_CLK_GATING_GPIO_B_SLP_CLK_ENABLE \
\r
701 0x00000100 // 1 - Enable GPIO_B clk during
\r
702 // sleep mode 0 - Disable GPIO_B clk
\r
703 // during sleep mode ;
\r
705 #define APPS_RCM_GPIO_B_CLK_GATING_NU2_M \
\r
708 #define APPS_RCM_GPIO_B_CLK_GATING_NU2_S 1
\r
709 #define APPS_RCM_GPIO_B_CLK_GATING_GPIO_B_RUN_CLK_ENABLE \
\r
710 0x00000001 // 1 - Enable GPIO_B clk during run
\r
711 // mode 0 - Disable GPIO_B clk
\r
712 // during run mode ;
\r
714 //******************************************************************************
\r
716 // The following are defines for the bit fields in the
\r
717 // APPS_RCM_O_GPIO_B_SOFT_RESET register.
\r
719 //******************************************************************************
\r
720 #define APPS_RCM_GPIO_B_SOFT_RESET_GPIO_B_ENABLED_STATUS \
\r
721 0x00000002 // 1 - GPIO_B Clocks/Resets are
\r
722 // enabled ; 0 - GPIO_B
\r
723 // Clocks/Resets are disabled
\r
725 #define APPS_RCM_GPIO_B_SOFT_RESET_GPIO_B_SOFT_RESET \
\r
726 0x00000001 // 1 - Assert reset for GPIO_B ; 0
\r
727 // - De-assert reset for GPIO_B
\r
729 //******************************************************************************
\r
731 // The following are defines for the bit fields in the
\r
732 // APPS_RCM_O_GPIO_C_CLK_GATING register.
\r
734 //******************************************************************************
\r
735 #define APPS_RCM_GPIO_C_CLK_GATING_GPIO_C_DSLP_CLK_ENABLE \
\r
736 0x00010000 // 1 - Enable GPIO_C clk during
\r
737 // deep-sleep mode 0 - Disable
\r
738 // GPIO_C clk during deep-sleep mode
\r
741 #define APPS_RCM_GPIO_C_CLK_GATING_NU1_M \
\r
744 #define APPS_RCM_GPIO_C_CLK_GATING_NU1_S 9
\r
745 #define APPS_RCM_GPIO_C_CLK_GATING_GPIO_C_SLP_CLK_ENABLE \
\r
746 0x00000100 // 1 - Enable GPIO_C clk during
\r
747 // sleep mode 0 - Disable GPIO_C clk
\r
748 // during sleep mode ;
\r
750 #define APPS_RCM_GPIO_C_CLK_GATING_NU2_M \
\r
753 #define APPS_RCM_GPIO_C_CLK_GATING_NU2_S 1
\r
754 #define APPS_RCM_GPIO_C_CLK_GATING_GPIO_C_RUN_CLK_ENABLE \
\r
755 0x00000001 // 1 - Enable GPIO_C clk during run
\r
756 // mode 0 - Disable GPIO_C clk
\r
757 // during run mode ;
\r
759 //******************************************************************************
\r
761 // The following are defines for the bit fields in the
\r
762 // APPS_RCM_O_GPIO_C_SOFT_RESET register.
\r
764 //******************************************************************************
\r
765 #define APPS_RCM_GPIO_C_SOFT_RESET_GPIO_C_ENABLED_STATUS \
\r
766 0x00000002 // 1 - GPIO_C Clocks/Resets are
\r
767 // enabled ; 0 - GPIO_C
\r
768 // Clocks/Resets are disabled
\r
770 #define APPS_RCM_GPIO_C_SOFT_RESET_GPIO_C_SOFT_RESET \
\r
771 0x00000001 // 1 - Assert reset for GPIO_C ; 0
\r
772 // - De-assert reset for GPIO_C
\r
774 //******************************************************************************
\r
776 // The following are defines for the bit fields in the
\r
777 // APPS_RCM_O_GPIO_D_CLK_GATING register.
\r
779 //******************************************************************************
\r
780 #define APPS_RCM_GPIO_D_CLK_GATING_GPIO_D_DSLP_CLK_ENABLE \
\r
781 0x00010000 // 1 - Enable GPIO_D clk during
\r
782 // deep-sleep mode 0 - Disable
\r
783 // GPIO_D clk during deep-sleep mode
\r
786 #define APPS_RCM_GPIO_D_CLK_GATING_NU1_M \
\r
789 #define APPS_RCM_GPIO_D_CLK_GATING_NU1_S 9
\r
790 #define APPS_RCM_GPIO_D_CLK_GATING_GPIO_D_SLP_CLK_ENABLE \
\r
791 0x00000100 // 1 - Enable GPIO_D clk during
\r
792 // sleep mode 0 - Disable GPIO_D clk
\r
793 // during sleep mode ;
\r
795 #define APPS_RCM_GPIO_D_CLK_GATING_NU2_M \
\r
798 #define APPS_RCM_GPIO_D_CLK_GATING_NU2_S 1
\r
799 #define APPS_RCM_GPIO_D_CLK_GATING_GPIO_D_RUN_CLK_ENABLE \
\r
800 0x00000001 // 1 - Enable GPIO_D clk during run
\r
801 // mode 0 - Disable GPIO_D clk
\r
802 // during run mode ;
\r
804 //******************************************************************************
\r
806 // The following are defines for the bit fields in the
\r
807 // APPS_RCM_O_GPIO_D_SOFT_RESET register.
\r
809 //******************************************************************************
\r
810 #define APPS_RCM_GPIO_D_SOFT_RESET_GPIO_D_ENABLED_STATUS \
\r
811 0x00000002 // 1 - GPIO_D Clocks/Resets are
\r
812 // enabled ; 0 - GPIO_D
\r
813 // Clocks/Resets are disabled
\r
815 #define APPS_RCM_GPIO_D_SOFT_RESET_GPIO_D_SOFT_RESET \
\r
816 0x00000001 // 1 - Assert reset for GPIO_D ; 0
\r
817 // - De-assert reset for GPIO_D
\r
819 //******************************************************************************
\r
821 // The following are defines for the bit fields in the
\r
822 // APPS_RCM_O_GPIO_E_CLK_GATING register.
\r
824 //******************************************************************************
\r
825 #define APPS_RCM_GPIO_E_CLK_GATING_GPIO_E_DSLP_CLK_ENABLE \
\r
826 0x00010000 // 1 - Enable GPIO_E clk during
\r
827 // deep-sleep mode 0 - Disable
\r
828 // GPIO_E clk during deep-sleep mode
\r
831 #define APPS_RCM_GPIO_E_CLK_GATING_NU1_M \
\r
834 #define APPS_RCM_GPIO_E_CLK_GATING_NU1_S 9
\r
835 #define APPS_RCM_GPIO_E_CLK_GATING_GPIO_E_SLP_CLK_ENABLE \
\r
836 0x00000100 // 1 - Enable GPIO_E clk during
\r
837 // sleep mode 0 - Disable GPIO_E clk
\r
838 // during sleep mode ;
\r
840 #define APPS_RCM_GPIO_E_CLK_GATING_NU2_M \
\r
843 #define APPS_RCM_GPIO_E_CLK_GATING_NU2_S 1
\r
844 #define APPS_RCM_GPIO_E_CLK_GATING_GPIO_E_RUN_CLK_ENABLE \
\r
845 0x00000001 // 1 - Enable GPIO_E clk during run
\r
846 // mode 0 - Disable GPIO_E clk
\r
847 // during run mode ;
\r
849 //******************************************************************************
\r
851 // The following are defines for the bit fields in the
\r
852 // APPS_RCM_O_GPIO_E_SOFT_RESET register.
\r
854 //******************************************************************************
\r
855 #define APPS_RCM_GPIO_E_SOFT_RESET_GPIO_E_ENABLED_STATUS \
\r
856 0x00000002 // 1 - GPIO_E Clocks/Resets are
\r
857 // enabled ; 0 - GPIO_E
\r
858 // Clocks/Resets are disabled
\r
860 #define APPS_RCM_GPIO_E_SOFT_RESET_GPIO_E_SOFT_RESET \
\r
861 0x00000001 // 1 - Assert reset for GPIO_E ; 0
\r
862 // - De-assert reset for GPIO_E
\r
864 //******************************************************************************
\r
866 // The following are defines for the bit fields in the
\r
867 // APPS_RCM_O_WDOG_A_CLK_GATING register.
\r
869 //******************************************************************************
\r
870 #define APPS_RCM_WDOG_A_CLK_GATING_WDOG_A_BAUD_CLK_SEL_M \
\r
871 0x03000000 // "00" - Sysclk ; "01" - REF_CLK
\r
872 // (38.4 MHz) ; "10/11" - Slow_clk
\r
874 #define APPS_RCM_WDOG_A_CLK_GATING_WDOG_A_BAUD_CLK_SEL_S 24
\r
875 #define APPS_RCM_WDOG_A_CLK_GATING_WDOG_A_DSLP_CLK_ENABLE \
\r
876 0x00010000 // 1 - Enable WDOG_A clk during
\r
877 // deep-sleep mode 0 - Disable
\r
878 // WDOG_A clk during deep-sleep mode
\r
881 #define APPS_RCM_WDOG_A_CLK_GATING_NU1_M \
\r
884 #define APPS_RCM_WDOG_A_CLK_GATING_NU1_S 9
\r
885 #define APPS_RCM_WDOG_A_CLK_GATING_WDOG_A_SLP_CLK_ENABLE \
\r
886 0x00000100 // 1 - Enable WDOG_A clk during
\r
887 // sleep mode 0 - Disable WDOG_A clk
\r
888 // during sleep mode ;
\r
890 #define APPS_RCM_WDOG_A_CLK_GATING_NU2_M \
\r
893 #define APPS_RCM_WDOG_A_CLK_GATING_NU2_S 1
\r
894 #define APPS_RCM_WDOG_A_CLK_GATING_WDOG_A_RUN_CLK_ENABLE \
\r
895 0x00000001 // 1 - Enable WDOG_A clk during run
\r
896 // mode 0 - Disable WDOG_A clk
\r
897 // during run mode ;
\r
899 //******************************************************************************
\r
901 // The following are defines for the bit fields in the
\r
902 // APPS_RCM_O_WDOG_A_SOFT_RESET register.
\r
904 //******************************************************************************
\r
905 #define APPS_RCM_WDOG_A_SOFT_RESET_WDOG_A_ENABLED_STATUS \
\r
906 0x00000002 // 1 - WDOG_A Clocks/Resets are
\r
907 // enabled ; 0 - WDOG_A
\r
908 // Clocks/Resets are disabled
\r
910 #define APPS_RCM_WDOG_A_SOFT_RESET_WDOG_A_SOFT_RESET \
\r
911 0x00000001 // 1 - Assert reset for WDOG_A ; 0
\r
912 // - De-assert reset for WDOG_A
\r
914 //******************************************************************************
\r
916 // The following are defines for the bit fields in the
\r
917 // APPS_RCM_O_UART_A0_CLK_GATING register.
\r
919 //******************************************************************************
\r
920 #define APPS_RCM_UART_A0_CLK_GATING_UART_A0_DSLP_CLK_ENABLE \
\r
921 0x00010000 // 1 - Enable UART_A0 clk during
\r
922 // deep-sleep mode 0 - Disable
\r
923 // UART_A0 clk during deep-sleep
\r
926 #define APPS_RCM_UART_A0_CLK_GATING_NU1_M \
\r
929 #define APPS_RCM_UART_A0_CLK_GATING_NU1_S 9
\r
930 #define APPS_RCM_UART_A0_CLK_GATING_UART_A0_SLP_CLK_ENABLE \
\r
931 0x00000100 // 1 - Enable UART_A0 clk during
\r
932 // sleep mode 0 - Disable UART_A0
\r
933 // clk during sleep mode ;
\r
935 #define APPS_RCM_UART_A0_CLK_GATING_NU2_M \
\r
938 #define APPS_RCM_UART_A0_CLK_GATING_NU2_S 1
\r
939 #define APPS_RCM_UART_A0_CLK_GATING_UART_A0_RUN_CLK_ENABLE \
\r
940 0x00000001 // 1 - Enable UART_A0 clk during
\r
941 // run mode 0 - Disable UART_A0 clk
\r
942 // during run mode ;
\r
944 //******************************************************************************
\r
946 // The following are defines for the bit fields in the
\r
947 // APPS_RCM_O_UART_A0_SOFT_RESET register.
\r
949 //******************************************************************************
\r
950 #define APPS_RCM_UART_A0_SOFT_RESET_UART_A0_ENABLED_STATUS \
\r
951 0x00000002 // 1 - UART_A0 Clocks/Resets are
\r
952 // enabled ; 0 - UART_A0
\r
953 // Clocks/Resets are disabled
\r
955 #define APPS_RCM_UART_A0_SOFT_RESET_UART_A0_SOFT_RESET \
\r
956 0x00000001 // 1 - Assert reset for UART_A0 ; 0
\r
957 // - De-assert reset for UART_A0
\r
959 //******************************************************************************
\r
961 // The following are defines for the bit fields in the
\r
962 // APPS_RCM_O_UART_A1_CLK_GATING register.
\r
964 //******************************************************************************
\r
965 #define APPS_RCM_UART_A1_CLK_GATING_UART_A1_DSLP_CLK_ENABLE \
\r
966 0x00010000 // 1 - Enable UART_A1 clk during
\r
967 // deep-sleep mode 0 - Disable
\r
968 // UART_A1 clk during deep-sleep
\r
971 #define APPS_RCM_UART_A1_CLK_GATING_NU1_M \
\r
974 #define APPS_RCM_UART_A1_CLK_GATING_NU1_S 9
\r
975 #define APPS_RCM_UART_A1_CLK_GATING_UART_A1_SLP_CLK_ENABLE \
\r
976 0x00000100 // 1 - Enable UART_A1 clk during
\r
977 // sleep mode 0 - Disable UART_A1
\r
978 // clk during sleep mode ;
\r
980 #define APPS_RCM_UART_A1_CLK_GATING_NU2_M \
\r
983 #define APPS_RCM_UART_A1_CLK_GATING_NU2_S 1
\r
984 #define APPS_RCM_UART_A1_CLK_GATING_UART_A1_RUN_CLK_ENABLE \
\r
985 0x00000001 // 1 - Enable UART_A1 clk during
\r
986 // run mode 0 - Disable UART_A1 clk
\r
987 // during run mode ;
\r
989 //******************************************************************************
\r
991 // The following are defines for the bit fields in the
\r
992 // APPS_RCM_O_UART_A1_SOFT_RESET register.
\r
994 //******************************************************************************
\r
995 #define APPS_RCM_UART_A1_SOFT_RESET_UART_A1_ENABLED_STATUS \
\r
996 0x00000002 // 1 - UART_A1 Clocks/Resets are
\r
997 // enabled ; 0 - UART_A1
\r
998 // Clocks/Resets are disabled
\r
1000 #define APPS_RCM_UART_A1_SOFT_RESET_UART_A1_SOFT_RESET \
\r
1001 0x00000001 // 1 - Assert the soft reset for
\r
1002 // UART_A1 ; 0 - De-assert the soft
\r
1003 // reset for UART_A1
\r
1005 //******************************************************************************
\r
1007 // The following are defines for the bit fields in the
\r
1008 // APPS_RCM_O_GPT_A0_CLK_GATING register.
\r
1010 //******************************************************************************
\r
1011 #define APPS_RCM_GPT_A0_CLK_GATING_GPT_A0_DSLP_CLK_ENABLE \
\r
1012 0x00010000 // 1 - Enable the GPT_A0 clock
\r
1013 // during deep-sleep ; 0 - Disable
\r
1014 // the GPT_A0 clock during
\r
1017 #define APPS_RCM_GPT_A0_CLK_GATING_NU1_M \
\r
1020 #define APPS_RCM_GPT_A0_CLK_GATING_NU1_S 9
\r
1021 #define APPS_RCM_GPT_A0_CLK_GATING_GPT_A0_SLP_CLK_ENABLE \
\r
1022 0x00000100 // 1 - Enable the GPT_A0 clock
\r
1023 // during sleep ; 0 - Disable the
\r
1024 // GPT_A0 clock during sleep
\r
1026 #define APPS_RCM_GPT_A0_CLK_GATING_NU2_M \
\r
1029 #define APPS_RCM_GPT_A0_CLK_GATING_NU2_S 1
\r
1030 #define APPS_RCM_GPT_A0_CLK_GATING_GPT_A0_RUN_CLK_ENABLE \
\r
1031 0x00000001 // 1 - Enable the GPT_A0 clock
\r
1032 // during run ; 0 - Disable the
\r
1033 // GPT_A0 clock during run
\r
1035 //******************************************************************************
\r
1037 // The following are defines for the bit fields in the
\r
1038 // APPS_RCM_O_GPT_A0_SOFT_RESET register.
\r
1040 //******************************************************************************
\r
1041 #define APPS_RCM_GPT_A0_SOFT_RESET_GPT_A0_ENABLED_STATUS \
\r
1042 0x00000002 // 1 - GPT_A0 clocks/resets are
\r
1043 // enabled ; 0 - GPT_A0
\r
1044 // clocks/resets are disabled
\r
1046 #define APPS_RCM_GPT_A0_SOFT_RESET_GPT_A0_SOFT_RESET \
\r
1047 0x00000001 // 1 - Assert the soft reset for
\r
1048 // GPT_A0 ; 0 - De-assert the soft
\r
1049 // reset for GPT_A0
\r
1051 //******************************************************************************
\r
1053 // The following are defines for the bit fields in the
\r
1054 // APPS_RCM_O_GPT_A1_CLK_GATING register.
\r
1056 //******************************************************************************
\r
1057 #define APPS_RCM_GPT_A1_CLK_GATING_GPT_A1_DSLP_CLK_ENABLE \
\r
1058 0x00010000 // 1 - Enable the GPT_A1 clock
\r
1059 // during deep-sleep ; 0 - Disable
\r
1060 // the GPT_A1 clock during
\r
1063 #define APPS_RCM_GPT_A1_CLK_GATING_NU1_M \
\r
1066 #define APPS_RCM_GPT_A1_CLK_GATING_NU1_S 9
\r
1067 #define APPS_RCM_GPT_A1_CLK_GATING_GPT_A1_SLP_CLK_ENABLE \
\r
1068 0x00000100 // 1 - Enable the GPT_A1 clock
\r
1069 // during sleep ; 0 - Disable the
\r
1070 // GPT_A1 clock during sleep
\r
1072 #define APPS_RCM_GPT_A1_CLK_GATING_NU2_M \
\r
1075 #define APPS_RCM_GPT_A1_CLK_GATING_NU2_S 1
\r
1076 #define APPS_RCM_GPT_A1_CLK_GATING_GPT_A1_RUN_CLK_ENABLE \
\r
1077 0x00000001 // 1 - Enable the GPT_A1 clock
\r
1078 // during run ; 0 - Disable the
\r
1079 // GPT_A1 clock during run
\r
1081 //******************************************************************************
\r
1083 // The following are defines for the bit fields in the
\r
1084 // APPS_RCM_O_GPT_A1_SOFT_RESET register.
\r
1086 //******************************************************************************
\r
1087 #define APPS_RCM_GPT_A1_SOFT_RESET_GPT_A1_ENABLED_STATUS \
\r
1088 0x00000002 // 1 - GPT_A1 clocks/resets are
\r
1089 // enabled ; 0 - GPT_A1
\r
1090 // clocks/resets are disabled
\r
1092 #define APPS_RCM_GPT_A1_SOFT_RESET_GPT_A1_SOFT_RESET \
\r
1093 0x00000001 // 1 - Assert the soft reset for
\r
1094 // GPT_A1 ; 0 - De-assert the soft
\r
1095 // reset for GPT_A1
\r
1097 //******************************************************************************
\r
1099 // The following are defines for the bit fields in the
\r
1100 // APPS_RCM_O_GPT_A2_CLK_GATING register.
\r
1102 //******************************************************************************
\r
1103 #define APPS_RCM_GPT_A2_CLK_GATING_GPT_A2_DSLP_CLK_ENABLE \
\r
1104 0x00010000 // 1 - Enable the GPT_A2 clock
\r
1105 // during deep-sleep ; 0 - Disable
\r
1106 // the GPT_A2 clock during
\r
1109 #define APPS_RCM_GPT_A2_CLK_GATING_NU1_M \
\r
1112 #define APPS_RCM_GPT_A2_CLK_GATING_NU1_S 9
\r
1113 #define APPS_RCM_GPT_A2_CLK_GATING_GPT_A2_SLP_CLK_ENABLE \
\r
1114 0x00000100 // 1 - Enable the GPT_A2 clock
\r
1115 // during sleep ; 0 - Disable the
\r
1116 // GPT_A2 clock during sleep
\r
1118 #define APPS_RCM_GPT_A2_CLK_GATING_NU2_M \
\r
1121 #define APPS_RCM_GPT_A2_CLK_GATING_NU2_S 1
\r
1122 #define APPS_RCM_GPT_A2_CLK_GATING_GPT_A2_RUN_CLK_ENABLE \
\r
1123 0x00000001 // 1 - Enable the GPT_A2 clock
\r
1124 // during run ; 0 - Disable the
\r
1125 // GPT_A2 clock during run
\r
1127 //******************************************************************************
\r
1129 // The following are defines for the bit fields in the
\r
1130 // APPS_RCM_O_GPT_A2_SOFT_RESET register.
\r
1132 //******************************************************************************
\r
1133 #define APPS_RCM_GPT_A2_SOFT_RESET_GPT_A2_ENABLED_STATUS \
\r
1134 0x00000002 // 1 - GPT_A2 clocks/resets are
\r
1135 // enabled ; 0 - GPT_A2
\r
1136 // clocks/resets are disabled
\r
1138 #define APPS_RCM_GPT_A2_SOFT_RESET_GPT_A2_SOFT_RESET \
\r
1139 0x00000001 // 1 - Assert the soft reset for
\r
1140 // GPT_A2 ; 0 - De-assert the soft
\r
1141 // reset for GPT_A2
\r
1143 //******************************************************************************
\r
1145 // The following are defines for the bit fields in the
\r
1146 // APPS_RCM_O_GPT_A3_CLK_GATING register.
\r
1148 //******************************************************************************
\r
1149 #define APPS_RCM_GPT_A3_CLK_GATING_GPT_A3_DSLP_CLK_ENABLE \
\r
1150 0x00010000 // 1 - Enable the GPT_A3 clock
\r
1151 // during deep-sleep ; 0 - Disable
\r
1152 // the GPT_A3 clock during
\r
1155 #define APPS_RCM_GPT_A3_CLK_GATING_NU1_M \
\r
1158 #define APPS_RCM_GPT_A3_CLK_GATING_NU1_S 9
\r
1159 #define APPS_RCM_GPT_A3_CLK_GATING_GPT_A3_SLP_CLK_ENABLE \
\r
1160 0x00000100 // 1 - Enable the GPT_A3 clock
\r
1161 // during sleep ; 0 - Disable the
\r
1162 // GPT_A3 clock during sleep
\r
1164 #define APPS_RCM_GPT_A3_CLK_GATING_NU2_M \
\r
1167 #define APPS_RCM_GPT_A3_CLK_GATING_NU2_S 1
\r
1168 #define APPS_RCM_GPT_A3_CLK_GATING_GPT_A3_RUN_CLK_ENABLE \
\r
1169 0x00000001 // 1 - Enable the GPT_A3 clock
\r
1170 // during run ; 0 - Disable the
\r
1171 // GPT_A3 clock during run
\r
1173 //******************************************************************************
\r
1175 // The following are defines for the bit fields in the
\r
1176 // APPS_RCM_O_GPT_A3_SOFT_RESET register.
\r
1178 //******************************************************************************
\r
1179 #define APPS_RCM_GPT_A3_SOFT_RESET_GPT_A3_ENABLED_STATUS \
\r
1180 0x00000002 // 1 - GPT_A3 Clocks/resets are
\r
1181 // enabled ; 0 - GPT_A3
\r
1182 // Clocks/resets are disabled
\r
1184 #define APPS_RCM_GPT_A3_SOFT_RESET_GPT_A3_SOFT_RESET \
\r
1185 0x00000001 // 1 - Assert the soft reset for
\r
1186 // GPT_A3 ; 0 - De-assert the soft
\r
1187 // reset for GPT_A3
\r
1189 //******************************************************************************
\r
1191 // The following are defines for the bit fields in the
\r
1192 // APPS_RCM_O_MCASP_FRAC_CLK_CONFIG0 register.
\r
1194 //******************************************************************************
\r
1195 #define APPS_RCM_MCASP_FRAC_CLK_CONFIG0_MCASP_FRAC_DIV_DIVISOR_M \
\r
1198 #define APPS_RCM_MCASP_FRAC_CLK_CONFIG0_MCASP_FRAC_DIV_DIVISOR_S 16
\r
1199 #define APPS_RCM_MCASP_FRAC_CLK_CONFIG0_MCASP_FRAC_DIV_FRACTION_M \
\r
1202 #define APPS_RCM_MCASP_FRAC_CLK_CONFIG0_MCASP_FRAC_DIV_FRACTION_S 0
\r
1203 //******************************************************************************
\r
1205 // The following are defines for the bit fields in the
\r
1206 // APPS_RCM_O_MCASP_FRAC_CLK_CONFIG1 register.
\r
1208 //******************************************************************************
\r
1209 #define APPS_RCM_MCASP_FRAC_CLK_CONFIG1_MCASP_FRAC_DIV_SOFT_RESET \
\r
1210 0x00010000 // 1 - Assert the reset for MCASP
\r
1211 // Frac-clk div; 0 - Donot assert
\r
1212 // the reset for MCASP frac clk-div
\r
1214 #define APPS_RCM_MCASP_FRAC_CLK_CONFIG1_MCASP_FRAC_DIV_PERIOD_M \
\r
1217 #define APPS_RCM_MCASP_FRAC_CLK_CONFIG1_MCASP_FRAC_DIV_PERIOD_S 0
\r
1218 //******************************************************************************
\r
1220 // The following are defines for the bit fields in the
\r
1221 // APPS_RCM_O_CRYPTO_CLK_GATING register.
\r
1223 //******************************************************************************
\r
1224 #define APPS_RCM_CRYPTO_CLK_GATING_CRYPTO_DSLP_CLK_ENABLE \
\r
1225 0x00010000 // 0 - Disable the Crypto clock
\r
1226 // during deep-sleep
\r
1228 #define APPS_RCM_CRYPTO_CLK_GATING_NU1_M \
\r
1231 #define APPS_RCM_CRYPTO_CLK_GATING_NU1_S 9
\r
1232 #define APPS_RCM_CRYPTO_CLK_GATING_CRYPTO_SLP_CLK_ENABLE \
\r
1233 0x00000100 // 1 - Enable the Crypto clock
\r
1234 // during sleep ; 0 - Disable the
\r
1235 // Crypto clock during sleep
\r
1237 #define APPS_RCM_CRYPTO_CLK_GATING_NU2_M \
\r
1240 #define APPS_RCM_CRYPTO_CLK_GATING_NU2_S 1
\r
1241 #define APPS_RCM_CRYPTO_CLK_GATING_CRYPTO_RUN_CLK_ENABLE \
\r
1242 0x00000001 // 1 - Enable the Crypto clock
\r
1243 // during run ; 0 - Disable the
\r
1244 // Crypto clock during run
\r
1246 //******************************************************************************
\r
1248 // The following are defines for the bit fields in the
\r
1249 // APPS_RCM_O_CRYPTO_SOFT_RESET register.
\r
1251 //******************************************************************************
\r
1252 #define APPS_RCM_CRYPTO_SOFT_RESET_CRYPTO_ENABLED_STATUS \
\r
1253 0x00000002 // 1 - Crypto clocks/resets are
\r
1254 // enabled ; 0 - Crypto
\r
1255 // clocks/resets are disabled
\r
1257 #define APPS_RCM_CRYPTO_SOFT_RESET_CRYPTO_SOFT_RESET \
\r
1258 0x00000001 // 1 - Assert the soft reset for
\r
1259 // Crypto ; 0 - De-assert the soft
\r
1260 // reset for Crypto
\r
1262 //******************************************************************************
\r
1264 // The following are defines for the bit fields in the
\r
1265 // APPS_RCM_O_MCSPI_S0_CLK_GATING register.
\r
1267 //******************************************************************************
\r
1268 #define APPS_RCM_MCSPI_S0_CLK_GATING_MCSPI_S0_DSLP_CLK_ENABLE \
\r
1269 0x00010000 // 0 - Disable the MCSPI_S0 clock
\r
1270 // during deep-sleep
\r
1272 #define APPS_RCM_MCSPI_S0_CLK_GATING_NU1_M \
\r
1275 #define APPS_RCM_MCSPI_S0_CLK_GATING_NU1_S 9
\r
1276 #define APPS_RCM_MCSPI_S0_CLK_GATING_MCSPI_S0_SLP_CLK_ENABLE \
\r
1277 0x00000100 // 1 - Enable the MCSPI_S0 clock
\r
1278 // during sleep ; 0 - Disable the
\r
1279 // MCSPI_S0 clock during sleep
\r
1281 #define APPS_RCM_MCSPI_S0_CLK_GATING_NU2_M \
\r
1284 #define APPS_RCM_MCSPI_S0_CLK_GATING_NU2_S 1
\r
1285 #define APPS_RCM_MCSPI_S0_CLK_GATING_MCSPI_S0_RUN_CLK_ENABLE \
\r
1286 0x00000001 // 1 - Enable the MCSPI_S0 clock
\r
1287 // during run ; 0 - Disable the
\r
1288 // MCSPI_S0 clock during run
\r
1290 //******************************************************************************
\r
1292 // The following are defines for the bit fields in the
\r
1293 // APPS_RCM_O_MCSPI_S0_SOFT_RESET register.
\r
1295 //******************************************************************************
\r
1296 #define APPS_RCM_MCSPI_S0_SOFT_RESET_MCSPI_S0_ENABLED_STATUS \
\r
1297 0x00000002 // 1 - MCSPI_S0 Clocks/Resets are
\r
1298 // enabled ; 0 - MCSPI_S0
\r
1299 // Clocks/resets are disabled
\r
1301 #define APPS_RCM_MCSPI_S0_SOFT_RESET_MCSPI_S0_SOFT_RESET \
\r
1302 0x00000001 // 1 - Assert the soft reset for
\r
1303 // MCSPI_S0 ; 0 - De-assert the soft
\r
1304 // reset for MCSPI_S0
\r
1306 //******************************************************************************
\r
1308 // The following are defines for the bit fields in the
\r
1309 // APPS_RCM_O_MCSPI_S0_CLKDIV_CFG register.
\r
1311 //******************************************************************************
\r
1312 #define APPS_RCM_MCSPI_S0_CLKDIV_CFG_MCSPI_S0_BAUD_CLK_SEL \
\r
1313 0x00010000 // 0 - XTAL clk is used as baud-clk
\r
1314 // for MCSPI_S0 ; 1 - PLL divclk is
\r
1315 // used as buad-clk for MCSPI_S0
\r
1317 #define APPS_RCM_MCSPI_S0_CLKDIV_CFG_NU1_M \
\r
1320 #define APPS_RCM_MCSPI_S0_CLKDIV_CFG_NU1_S 11
\r
1321 #define APPS_RCM_MCSPI_S0_CLKDIV_CFG_MCSPI_S0_PLLCLKDIV_OFF_TIME_M \
\r
1322 0x00000700 // Configuration of OFF-TIME for
\r
1323 // dividing PLL clk (240 MHz) in
\r
1324 // generation of MCSPI_S0 func-clk :
\r
1325 // "000" - 1 "001" - 2 "010" - 3
\r
1326 // "011" - 4 "100" - 5 "101" - 6
\r
1327 // "110" - 7 "111" - 8
\r
1329 #define APPS_RCM_MCSPI_S0_CLKDIV_CFG_MCSPI_S0_PLLCLKDIV_OFF_TIME_S 8
\r
1330 #define APPS_RCM_MCSPI_S0_CLKDIV_CFG_NU2_M \
\r
1333 #define APPS_RCM_MCSPI_S0_CLKDIV_CFG_NU2_S 3
\r
1334 #define APPS_RCM_MCSPI_S0_CLKDIV_CFG_MCSPI_S0_PLLCLKDIV_ON_TIME_M \
\r
1335 0x00000007 // Configuration of ON-TIME for
\r
1336 // dividing PLL clk (240 MHz) in
\r
1337 // generation of MCSPI_S0 func-clk :
\r
1338 // "000" - 1 "001" - 2 "010" - 3
\r
1339 // "011" - 4 "100" - 5 "101" - 6
\r
1340 // "110" - 7 "111" - 8
\r
1342 #define APPS_RCM_MCSPI_S0_CLKDIV_CFG_MCSPI_S0_PLLCLKDIV_ON_TIME_S 0
\r
1343 //******************************************************************************
\r
1345 // The following are defines for the bit fields in the
\r
1346 // APPS_RCM_O_I2C_CLK_GATING register.
\r
1348 //******************************************************************************
\r
1349 #define APPS_RCM_I2C_CLK_GATING_I2C_DSLP_CLK_ENABLE \
\r
1350 0x00010000 // 1 - Enable the I2C Clock during
\r
1351 // deep-sleep 0 - Disable the I2C
\r
1352 // clock during deep-sleep
\r
1354 #define APPS_RCM_I2C_CLK_GATING_NU1_M \
\r
1357 #define APPS_RCM_I2C_CLK_GATING_NU1_S 9
\r
1358 #define APPS_RCM_I2C_CLK_GATING_I2C_SLP_CLK_ENABLE \
\r
1359 0x00000100 // 1 - Enable the I2C clock during
\r
1360 // sleep ; 0 - Disable the I2C clock
\r
1363 #define APPS_RCM_I2C_CLK_GATING_NU2_M \
\r
1366 #define APPS_RCM_I2C_CLK_GATING_NU2_S 1
\r
1367 #define APPS_RCM_I2C_CLK_GATING_I2C_RUN_CLK_ENABLE \
\r
1368 0x00000001 // 1 - Enable the I2C clock during
\r
1369 // run ; 0 - Disable the I2C clock
\r
1372 //******************************************************************************
\r
1374 // The following are defines for the bit fields in the
\r
1375 // APPS_RCM_O_I2C_SOFT_RESET register.
\r
1377 //******************************************************************************
\r
1378 #define APPS_RCM_I2C_SOFT_RESET_I2C_ENABLED_STATUS \
\r
1379 0x00000002 // 1 - I2C Clocks/Resets are
\r
1380 // enabled ; 0 - I2C clocks/resets
\r
1383 #define APPS_RCM_I2C_SOFT_RESET_I2C_SOFT_RESET \
\r
1384 0x00000001 // 1 - Assert the soft reset for
\r
1385 // Shared-I2C ; 0 - De-assert the
\r
1386 // soft reset for Shared-I2C
\r
1388 //******************************************************************************
\r
1390 // The following are defines for the bit fields in the
\r
1391 // APPS_RCM_O_APPS_LPDS_REQ register.
\r
1393 //******************************************************************************
\r
1394 #define APPS_RCM_APPS_LPDS_REQ_APPS_LPDS_REQ \
\r
1395 0x00000001 // 1 - Request for LPDS
\r
1397 //******************************************************************************
\r
1399 // The following are defines for the bit fields in the
\r
1400 // APPS_RCM_O_APPS_TURBO_REQ register.
\r
1402 //******************************************************************************
\r
1403 #define APPS_RCM_APPS_TURBO_REQ_APPS_TURBO_REQ \
\r
1404 0x00000001 // 1 - Request for TURBO
\r
1406 //******************************************************************************
\r
1408 // The following are defines for the bit fields in the
\r
1409 // APPS_RCM_O_APPS_DSLP_WAKE_CONFIG register.
\r
1411 //******************************************************************************
\r
1412 #define APPS_RCM_APPS_DSLP_WAKE_CONFIG_DSLP_WAKE_FROM_NWP_ENABLE \
\r
1413 0x00000002 // 1 - Enable the NWP to wake APPS
\r
1414 // from deep-sleep ; 0 - Disable NWP
\r
1415 // to wake APPS from deep-sleep
\r
1417 #define APPS_RCM_APPS_DSLP_WAKE_CONFIG_DSLP_WAKE_TIMER_ENABLE \
\r
1418 0x00000001 // 1 - Enable deep-sleep wake timer
\r
1419 // in APPS RCM for deep-sleep; 0 -
\r
1420 // Disable deep-sleep wake timer in
\r
1423 //******************************************************************************
\r
1425 // The following are defines for the bit fields in the
\r
1426 // APPS_RCM_O_APPS_DSLP_WAKE_TIMER_CFG register.
\r
1428 //******************************************************************************
\r
1429 #define APPS_RCM_APPS_DSLP_WAKE_TIMER_CFG_DSLP_WAKE_TIMER_OPP_CFG_M \
\r
1430 0xFFFF0000 // Configuration (in slow_clks)
\r
1431 // which says when to request for
\r
1432 // OPP during deep-sleep exit
\r
1434 #define APPS_RCM_APPS_DSLP_WAKE_TIMER_CFG_DSLP_WAKE_TIMER_OPP_CFG_S 16
\r
1435 #define APPS_RCM_APPS_DSLP_WAKE_TIMER_CFG_DSLP_WAKE_TIMER_WAKE_CFG_M \
\r
1436 0x0000FFFF // Configuration (in slow_clks)
\r
1437 // which says when to request for
\r
1438 // WAKE during deep-sleep exit
\r
1440 #define APPS_RCM_APPS_DSLP_WAKE_TIMER_CFG_DSLP_WAKE_TIMER_WAKE_CFG_S 0
\r
1441 //******************************************************************************
\r
1443 // The following are defines for the bit fields in the
\r
1444 // APPS_RCM_O_APPS_RCM_SLP_WAKE_ENABLE register.
\r
1446 //******************************************************************************
\r
1447 #define APPS_RCM_APPS_RCM_SLP_WAKE_ENABLE_SLP_WAKE_FROM_NWP_ENABLE \
\r
1448 0x00000002 // 1- Enable the sleep wakeup due
\r
1449 // to NWP request. 0- Disable the
\r
1450 // sleep wakeup due to NWP request
\r
1452 #define APPS_RCM_APPS_RCM_SLP_WAKE_ENABLE_SLP_WAKE_TIMER_ENABLE \
\r
1453 0x00000001 // 1- Enable the sleep wakeup due
\r
1454 // to sleep-timer; 0-Disable the
\r
1455 // sleep wakeup due to sleep-timer
\r
1457 //******************************************************************************
\r
1459 // The following are defines for the bit fields in the
\r
1460 // APPS_RCM_O_APPS_SLP_WAKETIMER_CFG register.
\r
1462 //******************************************************************************
\r
1463 #define APPS_RCM_APPS_SLP_WAKETIMER_CFG_SLP_WAKE_TIMER_CFG_M \
\r
1464 0xFFFFFFFF // Configuration (number of
\r
1465 // sysclks-80MHz) for the Sleep
\r
1468 #define APPS_RCM_APPS_SLP_WAKETIMER_CFG_SLP_WAKE_TIMER_CFG_S 0
\r
1469 //******************************************************************************
\r
1471 // The following are defines for the bit fields in the
\r
1472 // APPS_RCM_O_APPS_TO_NWP_WAKE_REQUEST register.
\r
1474 //******************************************************************************
\r
1475 #define APPS_RCM_APPS_TO_NWP_WAKE_REQUEST_APPS_TO_NWP_WAKEUP_REQUEST \
\r
1476 0x00000001 // When 1 => APPS generated a wake
\r
1477 // request to NWP (When NWP is in
\r
1478 // any of its low-power modes :
\r
1481 //******************************************************************************
\r
1483 // The following are defines for the bit fields in the
\r
1484 // APPS_RCM_O_APPS_RCM_INTERRUPT_STATUS register.
\r
1486 //******************************************************************************
\r
1487 #define APPS_RCM_APPS_RCM_INTERRUPT_STATUS_apps_deep_sleep_timer_wake \
\r
1488 0x00000008 // 1 - Indicates that deep-sleep
\r
1489 // timer expiry had caused the
\r
1490 // wakeup from deep-sleep
\r
1492 #define APPS_RCM_APPS_RCM_INTERRUPT_STATUS_apps_sleep_timer_wake \
\r
1493 0x00000004 // 1 - Indicates that sleep timer
\r
1494 // expiry had caused the wakeup from
\r
1497 #define APPS_RCM_APPS_RCM_INTERRUPT_STATUS_apps_deep_sleep_wake_from_nwp \
\r
1498 0x00000002 // 1 - Indicates that NWP had
\r
1499 // caused the wakeup from deep-sleep
\r
1501 #define APPS_RCM_APPS_RCM_INTERRUPT_STATUS_apps_sleep_wake_from_nwp \
\r
1502 0x00000001 // 1 - Indicates that NWP had
\r
1503 // caused the wakeup from Sleep
\r
1508 #endif // __HW_APPS_RCM_H__
\r
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