2 * -------------------------------------------
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3 * CC3220 SDK - v0.10.00.00
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4 * -------------------------------------------
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6 * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/
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8 * Redistribution and use in source and binary forms, with or without
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9 * modification, are permitted provided that the following conditions
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12 * Redistributions of source code must retain the above copyright
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13 * notice, this list of conditions and the following disclaimer.
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15 * Redistributions in binary form must reproduce the above copyright
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16 * notice, this list of conditions and the following disclaimer in the
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17 * documentation and/or other materials provided with the
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20 * Neither the name of Texas Instruments Incorporated nor the names of
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21 * its contributors may be used to endorse or promote products derived
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22 * from this software without specific prior written permission.
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24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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25 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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26 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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27 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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28 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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29 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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30 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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31 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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32 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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33 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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34 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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38 #ifndef __HW_FLASH_CTRL_H__
\r
39 #define __HW_FLASH_CTRL_H__
\r
41 //*****************************************************************************
\r
43 // The following are defines for the FLASH_CTRL register offsets.
\r
45 //*****************************************************************************
\r
46 #define FLASH_CTRL_O_FMA 0x00000000 // Flash Memory Address (FMA)
\r
47 // offset 0x000 During a write
\r
48 // operation this register contains
\r
49 // a 4-byte-aligned address and
\r
50 // specifies where the data is
\r
51 // written. During erase operations
\r
52 // this register contains a 1
\r
53 // KB-aligned CPU byte address and
\r
54 // specifies which block is erased.
\r
55 // Note that the alignment
\r
56 // requirements must be met by
\r
57 // software or the results of the
\r
58 // operation are unpredictable.
\r
59 #define FLASH_CTRL_O_FMD 0x00000004 // Flash Memory Data (FMD) offset
\r
60 // 0x004 This register contains the
\r
61 // data to be written during the
\r
62 // programming cycle or read during
\r
63 // the read cycle. Note that the
\r
64 // contents of this register are
\r
65 // undefined for a read access of an
\r
66 // execute-only block. This register
\r
67 // is not used during erase cycles.
\r
68 #define FLASH_CTRL_O_FMC 0x00000008 // Flash Memory Control (FMC)
\r
69 // offset 0x008 When this register
\r
70 // is written the Flash memory
\r
71 // controller initiates the
\r
72 // appropriate access cycle for the
\r
73 // location specified by the Flash
\r
74 // Memory Address (FMA) register .
\r
75 // If the access is a write access
\r
76 // the data contained in the Flash
\r
77 // Memory Data (FMD) register is
\r
78 // written to the specified address.
\r
79 // This register must be the final
\r
80 // register written and initiates
\r
81 // the memory operation. The four
\r
82 // control bits in the lower byte of
\r
83 // this register are used to
\r
84 // initiate memory operations.
\r
85 #define FLASH_CTRL_O_FCRIS 0x0000000C // Flash Controller Raw Interrupt
\r
86 // Status (FCRIS) offset 0x00C This
\r
87 // register indicates that the Flash
\r
88 // memory controller has an
\r
89 // interrupt condition. An interrupt
\r
90 // is sent to the interrupt
\r
91 // controller only if the
\r
92 // corresponding FCIM register bit
\r
94 #define FLASH_CTRL_O_FCIM 0x00000010 // Flash Controller Interrupt Mask
\r
95 // (FCIM) offset 0x010 This register
\r
96 // controls whether the Flash memory
\r
97 // controller generates interrupts
\r
98 // to the controller.
\r
99 #define FLASH_CTRL_O_FCMISC 0x00000014 // Flash Controller Masked
\r
100 // Interrupt Status and Clear
\r
101 // (FCMISC) offset 0x014 This
\r
102 // register provides two functions.
\r
103 // First it reports the cause of an
\r
104 // interrupt by indicating which
\r
105 // interrupt source or sources are
\r
106 // signalling the interrupt. Second
\r
107 // it serves as the method to clear
\r
108 // the interrupt reporting.
\r
109 #define FLASH_CTRL_O_FMC2 0x00000020 // Flash Memory Control 2 (FMC2)
\r
110 // offset 0x020 When this register
\r
111 // is written the Flash memory
\r
112 // controller initiates the
\r
113 // appropriate access cycle for the
\r
114 // location specified by the Flash
\r
115 // Memory Address (FMA) register .
\r
116 // If the access is a write access
\r
117 // the data contained in the Flash
\r
118 // Write Buffer (FWB) registers is
\r
119 // written. This register must be
\r
120 // the final register written as it
\r
121 // initiates the memory operation.
\r
122 #define FLASH_CTRL_O_FWBVAL 0x00000030 // Flash Write Buffer Valid
\r
123 // (FWBVAL) offset 0x030 This
\r
124 // register provides a bitwise
\r
125 // status of which FWBn registers
\r
126 // have been written by the
\r
127 // processor since the last write of
\r
128 // the Flash memory write buffer.
\r
129 // The entries with a 1 are written
\r
130 // on the next write of the Flash
\r
131 // memory write buffer. This
\r
132 // register is cleared after the
\r
133 // write operation by hardware. A
\r
134 // protection violation on the write
\r
135 // operation also clears this
\r
136 // status. Software can program the
\r
137 // same 32 words to various Flash
\r
138 // memory locations by setting the
\r
139 // FWB[n] bits after they are
\r
140 // cleared by the write operation.
\r
141 // The next write operation then
\r
142 // uses the same data as the
\r
143 // previous one. In addition if a
\r
144 // FWBn register change should not
\r
145 // be written to Flash memory
\r
146 // software can clear the
\r
147 // corresponding FWB[n] bit to
\r
148 // preserve the existing data when
\r
149 // the next write operation occurs.
\r
150 #define FLASH_CTRL_O_FWB1 0x00000100 // Flash Write Buffer n (FWBn)
\r
151 // offset 0x100 - 0x17C These 32
\r
152 // registers hold the contents of
\r
153 // the data to be written into the
\r
154 // Flash memory on a buffered Flash
\r
155 // memory write operation. The
\r
156 // offset selects one of the 32-bit
\r
157 // registers. Only FWBn registers
\r
158 // that have been updated since the
\r
159 // preceding buffered Flash memory
\r
160 // write operation are written into
\r
161 // the Flash memory so it is not
\r
162 // necessary to write the entire
\r
163 // bank of registers in order to
\r
164 // write 1 or 2 words. The FWBn
\r
165 // registers are written into the
\r
166 // Flash memory with the FWB0
\r
167 // register corresponding to the
\r
168 // address contained in FMA. FWB1 is
\r
169 // written to the address FMA+0x4
\r
170 // etc. Note that only data bits
\r
171 // that are 0 result in the Flash
\r
172 // memory being modified. A data bit
\r
173 // that is 1 leaves the content of
\r
174 // the Flash memory bit at its
\r
176 #define FLASH_CTRL_O_FWB2 0x00000104 // Flash Write Buffer n (FWBn)
\r
177 // offset 0x100 - 0x17C These 32
\r
178 // registers hold the contents of
\r
179 // the data to be written into the
\r
180 // Flash memory on a buffered Flash
\r
181 // memory write operation. The
\r
182 // offset selects one of the 32-bit
\r
183 // registers. Only FWBn registers
\r
184 // that have been updated since the
\r
185 // preceding buffered Flash memory
\r
186 // write operation are written into
\r
187 // the Flash memory so it is not
\r
188 // necessary to write the entire
\r
189 // bank of registers in order to
\r
190 // write 1 or 2 words. The FWBn
\r
191 // registers are written into the
\r
192 // Flash memory with the FWB0
\r
193 // register corresponding to the
\r
194 // address contained in FMA. FWB1 is
\r
195 // written to the address FMA+0x4
\r
196 // etc. Note that only data bits
\r
197 // that are 0 result in the Flash
\r
198 // memory being modified. A data bit
\r
199 // that is 1 leaves the content of
\r
200 // the Flash memory bit at its
\r
202 #define FLASH_CTRL_O_FWB3 0x00000108 // Flash Write Buffer n (FWBn)
\r
203 // offset 0x100 - 0x17C These 32
\r
204 // registers hold the contents of
\r
205 // the data to be written into the
\r
206 // Flash memory on a buffered Flash
\r
207 // memory write operation. The
\r
208 // offset selects one of the 32-bit
\r
209 // registers. Only FWBn registers
\r
210 // that have been updated since the
\r
211 // preceding buffered Flash memory
\r
212 // write operation are written into
\r
213 // the Flash memory so it is not
\r
214 // necessary to write the entire
\r
215 // bank of registers in order to
\r
216 // write 1 or 2 words. The FWBn
\r
217 // registers are written into the
\r
218 // Flash memory with the FWB0
\r
219 // register corresponding to the
\r
220 // address contained in FMA. FWB1 is
\r
221 // written to the address FMA+0x4
\r
222 // etc. Note that only data bits
\r
223 // that are 0 result in the Flash
\r
224 // memory being modified. A data bit
\r
225 // that is 1 leaves the content of
\r
226 // the Flash memory bit at its
\r
228 #define FLASH_CTRL_O_FWB4 0x0000010C // Flash Write Buffer n (FWBn)
\r
229 // offset 0x100 - 0x17C These 32
\r
230 // registers hold the contents of
\r
231 // the data to be written into the
\r
232 // Flash memory on a buffered Flash
\r
233 // memory write operation. The
\r
234 // offset selects one of the 32-bit
\r
235 // registers. Only FWBn registers
\r
236 // that have been updated since the
\r
237 // preceding buffered Flash memory
\r
238 // write operation are written into
\r
239 // the Flash memory so it is not
\r
240 // necessary to write the entire
\r
241 // bank of registers in order to
\r
242 // write 1 or 2 words. The FWBn
\r
243 // registers are written into the
\r
244 // Flash memory with the FWB0
\r
245 // register corresponding to the
\r
246 // address contained in FMA. FWB1 is
\r
247 // written to the address FMA+0x4
\r
248 // etc. Note that only data bits
\r
249 // that are 0 result in the Flash
\r
250 // memory being modified. A data bit
\r
251 // that is 1 leaves the content of
\r
252 // the Flash memory bit at its
\r
254 #define FLASH_CTRL_O_FWB5 0x00000110 // Flash Write Buffer n (FWBn)
\r
255 // offset 0x100 - 0x17C These 32
\r
256 // registers hold the contents of
\r
257 // the data to be written into the
\r
258 // Flash memory on a buffered Flash
\r
259 // memory write operation. The
\r
260 // offset selects one of the 32-bit
\r
261 // registers. Only FWBn registers
\r
262 // that have been updated since the
\r
263 // preceding buffered Flash memory
\r
264 // write operation are written into
\r
265 // the Flash memory so it is not
\r
266 // necessary to write the entire
\r
267 // bank of registers in order to
\r
268 // write 1 or 2 words. The FWBn
\r
269 // registers are written into the
\r
270 // Flash memory with the FWB0
\r
271 // register corresponding to the
\r
272 // address contained in FMA. FWB1 is
\r
273 // written to the address FMA+0x4
\r
274 // etc. Note that only data bits
\r
275 // that are 0 result in the Flash
\r
276 // memory being modified. A data bit
\r
277 // that is 1 leaves the content of
\r
278 // the Flash memory bit at its
\r
280 #define FLASH_CTRL_O_FWB6 0x00000114 // Flash Write Buffer n (FWBn)
\r
281 // offset 0x100 - 0x17C These 32
\r
282 // registers hold the contents of
\r
283 // the data to be written into the
\r
284 // Flash memory on a buffered Flash
\r
285 // memory write operation. The
\r
286 // offset selects one of the 32-bit
\r
287 // registers. Only FWBn registers
\r
288 // that have been updated since the
\r
289 // preceding buffered Flash memory
\r
290 // write operation are written into
\r
291 // the Flash memory so it is not
\r
292 // necessary to write the entire
\r
293 // bank of registers in order to
\r
294 // write 1 or 2 words. The FWBn
\r
295 // registers are written into the
\r
296 // Flash memory with the FWB0
\r
297 // register corresponding to the
\r
298 // address contained in FMA. FWB1 is
\r
299 // written to the address FMA+0x4
\r
300 // etc. Note that only data bits
\r
301 // that are 0 result in the Flash
\r
302 // memory being modified. A data bit
\r
303 // that is 1 leaves the content of
\r
304 // the Flash memory bit at its
\r
306 #define FLASH_CTRL_O_FWB7 0x00000118 // Flash Write Buffer n (FWBn)
\r
307 // offset 0x100 - 0x17C These 32
\r
308 // registers hold the contents of
\r
309 // the data to be written into the
\r
310 // Flash memory on a buffered Flash
\r
311 // memory write operation. The
\r
312 // offset selects one of the 32-bit
\r
313 // registers. Only FWBn registers
\r
314 // that have been updated since the
\r
315 // preceding buffered Flash memory
\r
316 // write operation are written into
\r
317 // the Flash memory so it is not
\r
318 // necessary to write the entire
\r
319 // bank of registers in order to
\r
320 // write 1 or 2 words. The FWBn
\r
321 // registers are written into the
\r
322 // Flash memory with the FWB0
\r
323 // register corresponding to the
\r
324 // address contained in FMA. FWB1 is
\r
325 // written to the address FMA+0x4
\r
326 // etc. Note that only data bits
\r
327 // that are 0 result in the Flash
\r
328 // memory being modified. A data bit
\r
329 // that is 1 leaves the content of
\r
330 // the Flash memory bit at its
\r
332 #define FLASH_CTRL_O_FWB8 0x0000011C // Flash Write Buffer n (FWBn)
\r
333 // offset 0x100 - 0x17C These 32
\r
334 // registers hold the contents of
\r
335 // the data to be written into the
\r
336 // Flash memory on a buffered Flash
\r
337 // memory write operation. The
\r
338 // offset selects one of the 32-bit
\r
339 // registers. Only FWBn registers
\r
340 // that have been updated since the
\r
341 // preceding buffered Flash memory
\r
342 // write operation are written into
\r
343 // the Flash memory so it is not
\r
344 // necessary to write the entire
\r
345 // bank of registers in order to
\r
346 // write 1 or 2 words. The FWBn
\r
347 // registers are written into the
\r
348 // Flash memory with the FWB0
\r
349 // register corresponding to the
\r
350 // address contained in FMA. FWB1 is
\r
351 // written to the address FMA+0x4
\r
352 // etc. Note that only data bits
\r
353 // that are 0 result in the Flash
\r
354 // memory being modified. A data bit
\r
355 // that is 1 leaves the content of
\r
356 // the Flash memory bit at its
\r
358 #define FLASH_CTRL_O_FWB9 0x00000120 // Flash Write Buffer n (FWBn)
\r
359 // offset 0x100 - 0x17C These 32
\r
360 // registers hold the contents of
\r
361 // the data to be written into the
\r
362 // Flash memory on a buffered Flash
\r
363 // memory write operation. The
\r
364 // offset selects one of the 32-bit
\r
365 // registers. Only FWBn registers
\r
366 // that have been updated since the
\r
367 // preceding buffered Flash memory
\r
368 // write operation are written into
\r
369 // the Flash memory so it is not
\r
370 // necessary to write the entire
\r
371 // bank of registers in order to
\r
372 // write 1 or 2 words. The FWBn
\r
373 // registers are written into the
\r
374 // Flash memory with the FWB0
\r
375 // register corresponding to the
\r
376 // address contained in FMA. FWB1 is
\r
377 // written to the address FMA+0x4
\r
378 // etc. Note that only data bits
\r
379 // that are 0 result in the Flash
\r
380 // memory being modified. A data bit
\r
381 // that is 1 leaves the content of
\r
382 // the Flash memory bit at its
\r
384 #define FLASH_CTRL_O_FWB10 0x00000124 // Flash Write Buffer n (FWBn)
\r
385 // offset 0x100 - 0x17C These 32
\r
386 // registers hold the contents of
\r
387 // the data to be written into the
\r
388 // Flash memory on a buffered Flash
\r
389 // memory write operation. The
\r
390 // offset selects one of the 32-bit
\r
391 // registers. Only FWBn registers
\r
392 // that have been updated since the
\r
393 // preceding buffered Flash memory
\r
394 // write operation are written into
\r
395 // the Flash memory so it is not
\r
396 // necessary to write the entire
\r
397 // bank of registers in order to
\r
398 // write 1 or 2 words. The FWBn
\r
399 // registers are written into the
\r
400 // Flash memory with the FWB0
\r
401 // register corresponding to the
\r
402 // address contained in FMA. FWB1 is
\r
403 // written to the address FMA+0x4
\r
404 // etc. Note that only data bits
\r
405 // that are 0 result in the Flash
\r
406 // memory being modified. A data bit
\r
407 // that is 1 leaves the content of
\r
408 // the Flash memory bit at its
\r
410 #define FLASH_CTRL_O_FWB11 0x00000128 // Flash Write Buffer n (FWBn)
\r
411 // offset 0x100 - 0x17C These 32
\r
412 // registers hold the contents of
\r
413 // the data to be written into the
\r
414 // Flash memory on a buffered Flash
\r
415 // memory write operation. The
\r
416 // offset selects one of the 32-bit
\r
417 // registers. Only FWBn registers
\r
418 // that have been updated since the
\r
419 // preceding buffered Flash memory
\r
420 // write operation are written into
\r
421 // the Flash memory so it is not
\r
422 // necessary to write the entire
\r
423 // bank of registers in order to
\r
424 // write 1 or 2 words. The FWBn
\r
425 // registers are written into the
\r
426 // Flash memory with the FWB0
\r
427 // register corresponding to the
\r
428 // address contained in FMA. FWB1 is
\r
429 // written to the address FMA+0x4
\r
430 // etc. Note that only data bits
\r
431 // that are 0 result in the Flash
\r
432 // memory being modified. A data bit
\r
433 // that is 1 leaves the content of
\r
434 // the Flash memory bit at its
\r
436 #define FLASH_CTRL_O_FWB12 0x0000012C // Flash Write Buffer n (FWBn)
\r
437 // offset 0x100 - 0x17C These 32
\r
438 // registers hold the contents of
\r
439 // the data to be written into the
\r
440 // Flash memory on a buffered Flash
\r
441 // memory write operation. The
\r
442 // offset selects one of the 32-bit
\r
443 // registers. Only FWBn registers
\r
444 // that have been updated since the
\r
445 // preceding buffered Flash memory
\r
446 // write operation are written into
\r
447 // the Flash memory so it is not
\r
448 // necessary to write the entire
\r
449 // bank of registers in order to
\r
450 // write 1 or 2 words. The FWBn
\r
451 // registers are written into the
\r
452 // Flash memory with the FWB0
\r
453 // register corresponding to the
\r
454 // address contained in FMA. FWB1 is
\r
455 // written to the address FMA+0x4
\r
456 // etc. Note that only data bits
\r
457 // that are 0 result in the Flash
\r
458 // memory being modified. A data bit
\r
459 // that is 1 leaves the content of
\r
460 // the Flash memory bit at its
\r
462 #define FLASH_CTRL_O_FWB13 0x00000130 // Flash Write Buffer n (FWBn)
\r
463 // offset 0x100 - 0x17C These 32
\r
464 // registers hold the contents of
\r
465 // the data to be written into the
\r
466 // Flash memory on a buffered Flash
\r
467 // memory write operation. The
\r
468 // offset selects one of the 32-bit
\r
469 // registers. Only FWBn registers
\r
470 // that have been updated since the
\r
471 // preceding buffered Flash memory
\r
472 // write operation are written into
\r
473 // the Flash memory so it is not
\r
474 // necessary to write the entire
\r
475 // bank of registers in order to
\r
476 // write 1 or 2 words. The FWBn
\r
477 // registers are written into the
\r
478 // Flash memory with the FWB0
\r
479 // register corresponding to the
\r
480 // address contained in FMA. FWB1 is
\r
481 // written to the address FMA+0x4
\r
482 // etc. Note that only data bits
\r
483 // that are 0 result in the Flash
\r
484 // memory being modified. A data bit
\r
485 // that is 1 leaves the content of
\r
486 // the Flash memory bit at its
\r
488 #define FLASH_CTRL_O_FWB14 0x00000134 // Flash Write Buffer n (FWBn)
\r
489 // offset 0x100 - 0x17C These 32
\r
490 // registers hold the contents of
\r
491 // the data to be written into the
\r
492 // Flash memory on a buffered Flash
\r
493 // memory write operation. The
\r
494 // offset selects one of the 32-bit
\r
495 // registers. Only FWBn registers
\r
496 // that have been updated since the
\r
497 // preceding buffered Flash memory
\r
498 // write operation are written into
\r
499 // the Flash memory so it is not
\r
500 // necessary to write the entire
\r
501 // bank of registers in order to
\r
502 // write 1 or 2 words. The FWBn
\r
503 // registers are written into the
\r
504 // Flash memory with the FWB0
\r
505 // register corresponding to the
\r
506 // address contained in FMA. FWB1 is
\r
507 // written to the address FMA+0x4
\r
508 // etc. Note that only data bits
\r
509 // that are 0 result in the Flash
\r
510 // memory being modified. A data bit
\r
511 // that is 1 leaves the content of
\r
512 // the Flash memory bit at its
\r
514 #define FLASH_CTRL_O_FWB15 0x00000138 // Flash Write Buffer n (FWBn)
\r
515 // offset 0x100 - 0x17C These 32
\r
516 // registers hold the contents of
\r
517 // the data to be written into the
\r
518 // Flash memory on a buffered Flash
\r
519 // memory write operation. The
\r
520 // offset selects one of the 32-bit
\r
521 // registers. Only FWBn registers
\r
522 // that have been updated since the
\r
523 // preceding buffered Flash memory
\r
524 // write operation are written into
\r
525 // the Flash memory so it is not
\r
526 // necessary to write the entire
\r
527 // bank of registers in order to
\r
528 // write 1 or 2 words. The FWBn
\r
529 // registers are written into the
\r
530 // Flash memory with the FWB0
\r
531 // register corresponding to the
\r
532 // address contained in FMA. FWB1 is
\r
533 // written to the address FMA+0x4
\r
534 // etc. Note that only data bits
\r
535 // that are 0 result in the Flash
\r
536 // memory being modified. A data bit
\r
537 // that is 1 leaves the content of
\r
538 // the Flash memory bit at its
\r
540 #define FLASH_CTRL_O_FWB16 0x0000013C // Flash Write Buffer n (FWBn)
\r
541 // offset 0x100 - 0x17C These 32
\r
542 // registers hold the contents of
\r
543 // the data to be written into the
\r
544 // Flash memory on a buffered Flash
\r
545 // memory write operation. The
\r
546 // offset selects one of the 32-bit
\r
547 // registers. Only FWBn registers
\r
548 // that have been updated since the
\r
549 // preceding buffered Flash memory
\r
550 // write operation are written into
\r
551 // the Flash memory so it is not
\r
552 // necessary to write the entire
\r
553 // bank of registers in order to
\r
554 // write 1 or 2 words. The FWBn
\r
555 // registers are written into the
\r
556 // Flash memory with the FWB0
\r
557 // register corresponding to the
\r
558 // address contained in FMA. FWB1 is
\r
559 // written to the address FMA+0x4
\r
560 // etc. Note that only data bits
\r
561 // that are 0 result in the Flash
\r
562 // memory being modified. A data bit
\r
563 // that is 1 leaves the content of
\r
564 // the Flash memory bit at its
\r
566 #define FLASH_CTRL_O_FWB17 0x00000140 // Flash Write Buffer n (FWBn)
\r
567 // offset 0x100 - 0x17C These 32
\r
568 // registers hold the contents of
\r
569 // the data to be written into the
\r
570 // Flash memory on a buffered Flash
\r
571 // memory write operation. The
\r
572 // offset selects one of the 32-bit
\r
573 // registers. Only FWBn registers
\r
574 // that have been updated since the
\r
575 // preceding buffered Flash memory
\r
576 // write operation are written into
\r
577 // the Flash memory so it is not
\r
578 // necessary to write the entire
\r
579 // bank of registers in order to
\r
580 // write 1 or 2 words. The FWBn
\r
581 // registers are written into the
\r
582 // Flash memory with the FWB0
\r
583 // register corresponding to the
\r
584 // address contained in FMA. FWB1 is
\r
585 // written to the address FMA+0x4
\r
586 // etc. Note that only data bits
\r
587 // that are 0 result in the Flash
\r
588 // memory being modified. A data bit
\r
589 // that is 1 leaves the content of
\r
590 // the Flash memory bit at its
\r
592 #define FLASH_CTRL_O_FWB18 0x00000144 // Flash Write Buffer n (FWBn)
\r
593 // offset 0x100 - 0x17C These 32
\r
594 // registers hold the contents of
\r
595 // the data to be written into the
\r
596 // Flash memory on a buffered Flash
\r
597 // memory write operation. The
\r
598 // offset selects one of the 32-bit
\r
599 // registers. Only FWBn registers
\r
600 // that have been updated since the
\r
601 // preceding buffered Flash memory
\r
602 // write operation are written into
\r
603 // the Flash memory so it is not
\r
604 // necessary to write the entire
\r
605 // bank of registers in order to
\r
606 // write 1 or 2 words. The FWBn
\r
607 // registers are written into the
\r
608 // Flash memory with the FWB0
\r
609 // register corresponding to the
\r
610 // address contained in FMA. FWB1 is
\r
611 // written to the address FMA+0x4
\r
612 // etc. Note that only data bits
\r
613 // that are 0 result in the Flash
\r
614 // memory being modified. A data bit
\r
615 // that is 1 leaves the content of
\r
616 // the Flash memory bit at its
\r
618 #define FLASH_CTRL_O_FWB19 0x00000148 // Flash Write Buffer n (FWBn)
\r
619 // offset 0x100 - 0x17C These 32
\r
620 // registers hold the contents of
\r
621 // the data to be written into the
\r
622 // Flash memory on a buffered Flash
\r
623 // memory write operation. The
\r
624 // offset selects one of the 32-bit
\r
625 // registers. Only FWBn registers
\r
626 // that have been updated since the
\r
627 // preceding buffered Flash memory
\r
628 // write operation are written into
\r
629 // the Flash memory so it is not
\r
630 // necessary to write the entire
\r
631 // bank of registers in order to
\r
632 // write 1 or 2 words. The FWBn
\r
633 // registers are written into the
\r
634 // Flash memory with the FWB0
\r
635 // register corresponding to the
\r
636 // address contained in FMA. FWB1 is
\r
637 // written to the address FMA+0x4
\r
638 // etc. Note that only data bits
\r
639 // that are 0 result in the Flash
\r
640 // memory being modified. A data bit
\r
641 // that is 1 leaves the content of
\r
642 // the Flash memory bit at its
\r
644 #define FLASH_CTRL_O_FWB20 0x0000014C // Flash Write Buffer n (FWBn)
\r
645 // offset 0x100 - 0x17C These 32
\r
646 // registers hold the contents of
\r
647 // the data to be written into the
\r
648 // Flash memory on a buffered Flash
\r
649 // memory write operation. The
\r
650 // offset selects one of the 32-bit
\r
651 // registers. Only FWBn registers
\r
652 // that have been updated since the
\r
653 // preceding buffered Flash memory
\r
654 // write operation are written into
\r
655 // the Flash memory so it is not
\r
656 // necessary to write the entire
\r
657 // bank of registers in order to
\r
658 // write 1 or 2 words. The FWBn
\r
659 // registers are written into the
\r
660 // Flash memory with the FWB0
\r
661 // register corresponding to the
\r
662 // address contained in FMA. FWB1 is
\r
663 // written to the address FMA+0x4
\r
664 // etc. Note that only data bits
\r
665 // that are 0 result in the Flash
\r
666 // memory being modified. A data bit
\r
667 // that is 1 leaves the content of
\r
668 // the Flash memory bit at its
\r
670 #define FLASH_CTRL_O_FWB21 0x00000150 // Flash Write Buffer n (FWBn)
\r
671 // offset 0x100 - 0x17C These 32
\r
672 // registers hold the contents of
\r
673 // the data to be written into the
\r
674 // Flash memory on a buffered Flash
\r
675 // memory write operation. The
\r
676 // offset selects one of the 32-bit
\r
677 // registers. Only FWBn registers
\r
678 // that have been updated since the
\r
679 // preceding buffered Flash memory
\r
680 // write operation are written into
\r
681 // the Flash memory so it is not
\r
682 // necessary to write the entire
\r
683 // bank of registers in order to
\r
684 // write 1 or 2 words. The FWBn
\r
685 // registers are written into the
\r
686 // Flash memory with the FWB0
\r
687 // register corresponding to the
\r
688 // address contained in FMA. FWB1 is
\r
689 // written to the address FMA+0x4
\r
690 // etc. Note that only data bits
\r
691 // that are 0 result in the Flash
\r
692 // memory being modified. A data bit
\r
693 // that is 1 leaves the content of
\r
694 // the Flash memory bit at its
\r
696 #define FLASH_CTRL_O_FWB22 0x00000154 // Flash Write Buffer n (FWBn)
\r
697 // offset 0x100 - 0x17C These 32
\r
698 // registers hold the contents of
\r
699 // the data to be written into the
\r
700 // Flash memory on a buffered Flash
\r
701 // memory write operation. The
\r
702 // offset selects one of the 32-bit
\r
703 // registers. Only FWBn registers
\r
704 // that have been updated since the
\r
705 // preceding buffered Flash memory
\r
706 // write operation are written into
\r
707 // the Flash memory so it is not
\r
708 // necessary to write the entire
\r
709 // bank of registers in order to
\r
710 // write 1 or 2 words. The FWBn
\r
711 // registers are written into the
\r
712 // Flash memory with the FWB0
\r
713 // register corresponding to the
\r
714 // address contained in FMA. FWB1 is
\r
715 // written to the address FMA+0x4
\r
716 // etc. Note that only data bits
\r
717 // that are 0 result in the Flash
\r
718 // memory being modified. A data bit
\r
719 // that is 1 leaves the content of
\r
720 // the Flash memory bit at its
\r
722 #define FLASH_CTRL_O_FWB23 0x00000158 // Flash Write Buffer n (FWBn)
\r
723 // offset 0x100 - 0x17C These 32
\r
724 // registers hold the contents of
\r
725 // the data to be written into the
\r
726 // Flash memory on a buffered Flash
\r
727 // memory write operation. The
\r
728 // offset selects one of the 32-bit
\r
729 // registers. Only FWBn registers
\r
730 // that have been updated since the
\r
731 // preceding buffered Flash memory
\r
732 // write operation are written into
\r
733 // the Flash memory so it is not
\r
734 // necessary to write the entire
\r
735 // bank of registers in order to
\r
736 // write 1 or 2 words. The FWBn
\r
737 // registers are written into the
\r
738 // Flash memory with the FWB0
\r
739 // register corresponding to the
\r
740 // address contained in FMA. FWB1 is
\r
741 // written to the address FMA+0x4
\r
742 // etc. Note that only data bits
\r
743 // that are 0 result in the Flash
\r
744 // memory being modified. A data bit
\r
745 // that is 1 leaves the content of
\r
746 // the Flash memory bit at its
\r
748 #define FLASH_CTRL_O_FWB24 0x0000015C // Flash Write Buffer n (FWBn)
\r
749 // offset 0x100 - 0x17C These 32
\r
750 // registers hold the contents of
\r
751 // the data to be written into the
\r
752 // Flash memory on a buffered Flash
\r
753 // memory write operation. The
\r
754 // offset selects one of the 32-bit
\r
755 // registers. Only FWBn registers
\r
756 // that have been updated since the
\r
757 // preceding buffered Flash memory
\r
758 // write operation are written into
\r
759 // the Flash memory so it is not
\r
760 // necessary to write the entire
\r
761 // bank of registers in order to
\r
762 // write 1 or 2 words. The FWBn
\r
763 // registers are written into the
\r
764 // Flash memory with the FWB0
\r
765 // register corresponding to the
\r
766 // address contained in FMA. FWB1 is
\r
767 // written to the address FMA+0x4
\r
768 // etc. Note that only data bits
\r
769 // that are 0 result in the Flash
\r
770 // memory being modified. A data bit
\r
771 // that is 1 leaves the content of
\r
772 // the Flash memory bit at its
\r
774 #define FLASH_CTRL_O_FWB25 0x00000160 // Flash Write Buffer n (FWBn)
\r
775 // offset 0x100 - 0x17C These 32
\r
776 // registers hold the contents of
\r
777 // the data to be written into the
\r
778 // Flash memory on a buffered Flash
\r
779 // memory write operation. The
\r
780 // offset selects one of the 32-bit
\r
781 // registers. Only FWBn registers
\r
782 // that have been updated since the
\r
783 // preceding buffered Flash memory
\r
784 // write operation are written into
\r
785 // the Flash memory so it is not
\r
786 // necessary to write the entire
\r
787 // bank of registers in order to
\r
788 // write 1 or 2 words. The FWBn
\r
789 // registers are written into the
\r
790 // Flash memory with the FWB0
\r
791 // register corresponding to the
\r
792 // address contained in FMA. FWB1 is
\r
793 // written to the address FMA+0x4
\r
794 // etc. Note that only data bits
\r
795 // that are 0 result in the Flash
\r
796 // memory being modified. A data bit
\r
797 // that is 1 leaves the content of
\r
798 // the Flash memory bit at its
\r
800 #define FLASH_CTRL_O_FWB26 0x00000164 // Flash Write Buffer n (FWBn)
\r
801 // offset 0x100 - 0x17C These 32
\r
802 // registers hold the contents of
\r
803 // the data to be written into the
\r
804 // Flash memory on a buffered Flash
\r
805 // memory write operation. The
\r
806 // offset selects one of the 32-bit
\r
807 // registers. Only FWBn registers
\r
808 // that have been updated since the
\r
809 // preceding buffered Flash memory
\r
810 // write operation are written into
\r
811 // the Flash memory so it is not
\r
812 // necessary to write the entire
\r
813 // bank of registers in order to
\r
814 // write 1 or 2 words. The FWBn
\r
815 // registers are written into the
\r
816 // Flash memory with the FWB0
\r
817 // register corresponding to the
\r
818 // address contained in FMA. FWB1 is
\r
819 // written to the address FMA+0x4
\r
820 // etc. Note that only data bits
\r
821 // that are 0 result in the Flash
\r
822 // memory being modified. A data bit
\r
823 // that is 1 leaves the content of
\r
824 // the Flash memory bit at its
\r
826 #define FLASH_CTRL_O_FWB27 0x00000168 // Flash Write Buffer n (FWBn)
\r
827 // offset 0x100 - 0x17C These 32
\r
828 // registers hold the contents of
\r
829 // the data to be written into the
\r
830 // Flash memory on a buffered Flash
\r
831 // memory write operation. The
\r
832 // offset selects one of the 32-bit
\r
833 // registers. Only FWBn registers
\r
834 // that have been updated since the
\r
835 // preceding buffered Flash memory
\r
836 // write operation are written into
\r
837 // the Flash memory so it is not
\r
838 // necessary to write the entire
\r
839 // bank of registers in order to
\r
840 // write 1 or 2 words. The FWBn
\r
841 // registers are written into the
\r
842 // Flash memory with the FWB0
\r
843 // register corresponding to the
\r
844 // address contained in FMA. FWB1 is
\r
845 // written to the address FMA+0x4
\r
846 // etc. Note that only data bits
\r
847 // that are 0 result in the Flash
\r
848 // memory being modified. A data bit
\r
849 // that is 1 leaves the content of
\r
850 // the Flash memory bit at its
\r
852 #define FLASH_CTRL_O_FWB28 0x0000016C // Flash Write Buffer n (FWBn)
\r
853 // offset 0x100 - 0x17C These 32
\r
854 // registers hold the contents of
\r
855 // the data to be written into the
\r
856 // Flash memory on a buffered Flash
\r
857 // memory write operation. The
\r
858 // offset selects one of the 32-bit
\r
859 // registers. Only FWBn registers
\r
860 // that have been updated since the
\r
861 // preceding buffered Flash memory
\r
862 // write operation are written into
\r
863 // the Flash memory so it is not
\r
864 // necessary to write the entire
\r
865 // bank of registers in order to
\r
866 // write 1 or 2 words. The FWBn
\r
867 // registers are written into the
\r
868 // Flash memory with the FWB0
\r
869 // register corresponding to the
\r
870 // address contained in FMA. FWB1 is
\r
871 // written to the address FMA+0x4
\r
872 // etc. Note that only data bits
\r
873 // that are 0 result in the Flash
\r
874 // memory being modified. A data bit
\r
875 // that is 1 leaves the content of
\r
876 // the Flash memory bit at its
\r
878 #define FLASH_CTRL_O_FWB29 0x00000170 // Flash Write Buffer n (FWBn)
\r
879 // offset 0x100 - 0x17C These 32
\r
880 // registers hold the contents of
\r
881 // the data to be written into the
\r
882 // Flash memory on a buffered Flash
\r
883 // memory write operation. The
\r
884 // offset selects one of the 32-bit
\r
885 // registers. Only FWBn registers
\r
886 // that have been updated since the
\r
887 // preceding buffered Flash memory
\r
888 // write operation are written into
\r
889 // the Flash memory so it is not
\r
890 // necessary to write the entire
\r
891 // bank of registers in order to
\r
892 // write 1 or 2 words. The FWBn
\r
893 // registers are written into the
\r
894 // Flash memory with the FWB0
\r
895 // register corresponding to the
\r
896 // address contained in FMA. FWB1 is
\r
897 // written to the address FMA+0x4
\r
898 // etc. Note that only data bits
\r
899 // that are 0 result in the Flash
\r
900 // memory being modified. A data bit
\r
901 // that is 1 leaves the content of
\r
902 // the Flash memory bit at its
\r
904 #define FLASH_CTRL_O_FWB30 0x00000174 // Flash Write Buffer n (FWBn)
\r
905 // offset 0x100 - 0x17C These 32
\r
906 // registers hold the contents of
\r
907 // the data to be written into the
\r
908 // Flash memory on a buffered Flash
\r
909 // memory write operation. The
\r
910 // offset selects one of the 32-bit
\r
911 // registers. Only FWBn registers
\r
912 // that have been updated since the
\r
913 // preceding buffered Flash memory
\r
914 // write operation are written into
\r
915 // the Flash memory so it is not
\r
916 // necessary to write the entire
\r
917 // bank of registers in order to
\r
918 // write 1 or 2 words. The FWBn
\r
919 // registers are written into the
\r
920 // Flash memory with the FWB0
\r
921 // register corresponding to the
\r
922 // address contained in FMA. FWB1 is
\r
923 // written to the address FMA+0x4
\r
924 // etc. Note that only data bits
\r
925 // that are 0 result in the Flash
\r
926 // memory being modified. A data bit
\r
927 // that is 1 leaves the content of
\r
928 // the Flash memory bit at its
\r
930 #define FLASH_CTRL_O_FWB31 0x00000178 // Flash Write Buffer n (FWBn)
\r
931 // offset 0x100 - 0x17C These 32
\r
932 // registers hold the contents of
\r
933 // the data to be written into the
\r
934 // Flash memory on a buffered Flash
\r
935 // memory write operation. The
\r
936 // offset selects one of the 32-bit
\r
937 // registers. Only FWBn registers
\r
938 // that have been updated since the
\r
939 // preceding buffered Flash memory
\r
940 // write operation are written into
\r
941 // the Flash memory so it is not
\r
942 // necessary to write the entire
\r
943 // bank of registers in order to
\r
944 // write 1 or 2 words. The FWBn
\r
945 // registers are written into the
\r
946 // Flash memory with the FWB0
\r
947 // register corresponding to the
\r
948 // address contained in FMA. FWB1 is
\r
949 // written to the address FMA+0x4
\r
950 // etc. Note that only data bits
\r
951 // that are 0 result in the Flash
\r
952 // memory being modified. A data bit
\r
953 // that is 1 leaves the content of
\r
954 // the Flash memory bit at its
\r
956 #define FLASH_CTRL_O_FWB32 0x0000017C // Flash Write Buffer n (FWBn)
\r
957 // offset 0x100 - 0x17C These 32
\r
958 // registers hold the contents of
\r
959 // the data to be written into the
\r
960 // Flash memory on a buffered Flash
\r
961 // memory write operation. The
\r
962 // offset selects one of the 32-bit
\r
963 // registers. Only FWBn registers
\r
964 // that have been updated since the
\r
965 // preceding buffered Flash memory
\r
966 // write operation are written into
\r
967 // the Flash memory so it is not
\r
968 // necessary to write the entire
\r
969 // bank of registers in order to
\r
970 // write 1 or 2 words. The FWBn
\r
971 // registers are written into the
\r
972 // Flash memory with the FWB0
\r
973 // register corresponding to the
\r
974 // address contained in FMA. FWB1 is
\r
975 // written to the address FMA+0x4
\r
976 // etc. Note that only data bits
\r
977 // that are 0 result in the Flash
\r
978 // memory being modified. A data bit
\r
979 // that is 1 leaves the content of
\r
980 // the Flash memory bit at its
\r
982 #define FLASH_CTRL_O_FSIZE 0x00000FC0 // Flash Size (FSIZE) offset 0xFC0
\r
983 // This register indicates the size
\r
984 // of the on-chip Flash memory.
\r
985 // Important: This register should
\r
986 // be used to determine the size of
\r
987 // the Flash memory that is
\r
988 // implemented on this
\r
989 // microcontroller. However to
\r
990 // support legacy software the DC0
\r
991 // register is available. A read of
\r
992 // the DC0 register correctly
\r
993 // identifies legacy memory sizes.
\r
994 // Software must use the FSIZE
\r
995 // register for memory sizes that
\r
996 // are not listed in the DC0
\r
997 // register description.
\r
998 #define FLASH_CTRL_O_SSIZE 0x00000FC4 // SRAM Size (SSIZE) offset 0xFC4
\r
999 // This register indicates the size
\r
1000 // of the on-chip SRAM. Important:
\r
1001 // This register should be used to
\r
1002 // determine the size of the SRAM
\r
1003 // that is implemented on this
\r
1004 // microcontroller. However to
\r
1005 // support legacy software the DC0
\r
1006 // register is available. A read of
\r
1007 // the DC0 register correctly
\r
1008 // identifies legacy memory sizes.
\r
1009 // Software must use the SSIZE
\r
1010 // register for memory sizes that
\r
1011 // are not listed in the DC0
\r
1012 // register description.
\r
1016 //******************************************************************************
\r
1018 // The following are defines for the bit fields in the FLASH_CTRL_O_FMA register.
\r
1020 //******************************************************************************
\r
1021 #define FLASH_CTRL_FMA_OFFSET_M 0x0003FFFF // Address Offset Address offset in
\r
1022 // Flash memory where operation is
\r
1023 // performed except for nonvolatile
\r
1025 #define FLASH_CTRL_FMA_OFFSET_S 0
\r
1026 //******************************************************************************
\r
1028 // The following are defines for the bit fields in the FLASH_CTRL_O_FMD register.
\r
1030 //******************************************************************************
\r
1031 #define FLASH_CTRL_FMD_DATA_M 0xFFFFFFFF // Data Value Data value for write
\r
1033 #define FLASH_CTRL_FMD_DATA_S 0
\r
1034 //******************************************************************************
\r
1036 // The following are defines for the bit fields in the FLASH_CTRL_O_FMC register.
\r
1038 //******************************************************************************
\r
1039 #define FLASH_CTRL_FMC_WRKEY_M 0xFFFF0000 // Flash Memory Write Key This
\r
1040 // field contains a write key which
\r
1041 // is used to minimize the incidence
\r
1042 // of accidental Flash memory
\r
1043 // writes. The value 0xA442 must be
\r
1044 // written into this field for a
\r
1045 // Flash memory write to occur.
\r
1046 // Writes to the FMC register
\r
1047 // without this WRKEY value are
\r
1048 // ignored. A read of this field
\r
1049 // returns the value 0.
\r
1050 #define FLASH_CTRL_FMC_WRKEY_S 16
\r
1051 #define FLASH_CTRL_FMC_COMT 0x00000008 // Commit Register Value This bit
\r
1052 // is used to commit writes to
\r
1053 // Flash-memory-resident registers
\r
1054 // and to monitor the progress of
\r
1055 // that process. Value Description 1
\r
1056 // Set this bit to commit (write)
\r
1057 // the register value to a
\r
1058 // Flash-memory-resident register.
\r
1059 // When read a 1 indicates that the
\r
1060 // previous commit access is not
\r
1061 // complete. 0 A write of 0 has no
\r
1062 // effect on the state of this bit.
\r
1063 // When read a 0 indicates that the
\r
1064 // previous commit access is
\r
1066 #define FLASH_CTRL_FMC_MERASE1 0x00000004 // Mass Erase Flash Memory This bit
\r
1067 // is used to mass erase the Flash
\r
1068 // main memory and to monitor the
\r
1069 // progress of that process. Value
\r
1070 // Description 1 Set this bit to
\r
1071 // erase the Flash main memory. When
\r
1072 // read a 1 indicates that the
\r
1073 // previous mass erase access is not
\r
1074 // complete. 0 A write of 0 has no
\r
1075 // effect on the state of this bit.
\r
1076 // When read a 0 indicates that the
\r
1077 // previous mass erase access is
\r
1079 #define FLASH_CTRL_FMC_ERASE 0x00000002 // Erase a Page of Flash Memory
\r
1080 // This bit is used to erase a page
\r
1081 // of Flash memory and to monitor
\r
1082 // the progress of that process.
\r
1083 // Value Description 1 Set this bit
\r
1084 // to erase the Flash memory page
\r
1085 // specified by the contents of the
\r
1086 // FMA register. When read a 1
\r
1087 // indicates that the previous page
\r
1088 // erase access is not complete. 0 A
\r
1089 // write of 0 has no effect on the
\r
1090 // state of this bit. When read a 0
\r
1091 // indicates that the previous page
\r
1092 // erase access is complete.
\r
1093 #define FLASH_CTRL_FMC_WRITE 0x00000001 // Write a Word into Flash Memory
\r
1094 // This bit is used to write a word
\r
1095 // into Flash memory and to monitor
\r
1096 // the progress of that process.
\r
1097 // Value Description 1 Set this bit
\r
1098 // to write the data stored in the
\r
1099 // FMD register into the Flash
\r
1100 // memory location specified by the
\r
1101 // contents of the FMA register.
\r
1102 // When read a 1 indicates that the
\r
1103 // write update access is not
\r
1104 // complete. 0 A write of 0 has no
\r
1105 // effect on the state of this bit.
\r
1106 // When read a 0 indicates that the
\r
1107 // previous write update access is
\r
1109 //******************************************************************************
\r
1111 // The following are defines for the bit fields in the
\r
1112 // FLASH_CTRL_O_FCRIS register.
\r
1114 //******************************************************************************
\r
1115 #define FLASH_CTRL_FCRIS_PROGRIS \
\r
1116 0x00002000 // Program Verify Error Raw
\r
1117 // Interrupt Status Value
\r
1118 // Description 1 An interrupt is
\r
1119 // pending because the verify of a
\r
1120 // PROGRAM operation failed. 0 An
\r
1121 // interrupt has not occurred. This
\r
1122 // bit is cleared by writing a 1 to
\r
1123 // the PROGMISC bit in the FCMISC
\r
1126 #define FLASH_CTRL_FCRIS_ERRIS 0x00000800 // Erase Verify Error Raw Interrupt
\r
1127 // Status Value Description 1 An
\r
1128 // interrupt is pending because the
\r
1129 // verify of an ERASE operation
\r
1130 // failed. 0 An interrupt has not
\r
1131 // occurred. This bit is cleared by
\r
1132 // writing a 1 to the ERMISC bit in
\r
1133 // the FCMISC register.
\r
1134 #define FLASH_CTRL_FCRIS_INVDRIS \
\r
1135 0x00000400 // Invalid Data Raw Interrupt
\r
1136 // Status Value Description 1 An
\r
1137 // interrupt is pending because a
\r
1138 // bit that was previously
\r
1139 // programmed as a 0 is now being
\r
1140 // requested to be programmed as a
\r
1141 // 1. 0 An interrupt has not
\r
1142 // occurred. This bit is cleared by
\r
1143 // writing a 1 to the INVMISC bit in
\r
1144 // the FCMISC register.
\r
1146 #define FLASH_CTRL_FCRIS_VOLTRIS \
\r
1147 0x00000200 // Pump Voltage Raw Interrupt
\r
1148 // Status Value Description 1 An
\r
1149 // interrupt is pending because the
\r
1150 // regulated voltage of the pump
\r
1151 // went out of spec during the Flash
\r
1152 // operation and the operation was
\r
1153 // terminated. 0 An interrupt has
\r
1154 // not occurred. This bit is cleared
\r
1155 // by writing a 1 to the VOLTMISC
\r
1156 // bit in the FCMISC register.
\r
1158 #define FLASH_CTRL_FCRIS_ERIS 0x00000004 // EEPROM Raw Interrupt Status This
\r
1159 // bit provides status EEPROM
\r
1160 // operation. Value Description 1 An
\r
1161 // EEPROM interrupt has occurred. 0
\r
1162 // An EEPROM interrupt has not
\r
1163 // occurred. This bit is cleared by
\r
1164 // writing a 1 to the EMISC bit in
\r
1165 // the FCMISC register.
\r
1166 #define FLASH_CTRL_FCRIS_PRIS 0x00000002 // Programming Raw Interrupt Status
\r
1167 // This bit provides status on
\r
1168 // programming cycles which are
\r
1169 // write or erase actions generated
\r
1170 // through the FMC or FMC2 register
\r
1171 // bits (see page 537 and page 549).
\r
1172 // Value Description 1 The
\r
1173 // programming or erase cycle has
\r
1174 // completed. 0 The programming or
\r
1175 // erase cycle has not completed.
\r
1176 // This status is sent to the
\r
1177 // interrupt controller when the
\r
1178 // PMASK bit in the FCIM register is
\r
1179 // set. This bit is cleared by
\r
1180 // writing a 1 to the PMISC bit in
\r
1181 // the FCMISC register.
\r
1182 #define FLASH_CTRL_FCRIS_ARIS 0x00000001 // Access Raw Interrupt Status
\r
1183 // Value Description 1 A program or
\r
1184 // erase action was attempted on a
\r
1185 // block of Flash memory that
\r
1186 // contradicts the protection policy
\r
1187 // for that block as set in the
\r
1188 // FMPPEn registers. 0 No access has
\r
1189 // tried to improperly program or
\r
1190 // erase the Flash memory. This
\r
1191 // status is sent to the interrupt
\r
1192 // controller when the AMASK bit in
\r
1193 // the FCIM register is set. This
\r
1194 // bit is cleared by writing a 1 to
\r
1195 // the AMISC bit in the FCMISC
\r
1197 //******************************************************************************
\r
1199 // The following are defines for the bit fields in the FLASH_CTRL_O_FCIM register.
\r
1201 //******************************************************************************
\r
1202 #define FLASH_CTRL_FCIM_ILLMASK 0x00004000 // Illegal Address Interrupt Mask
\r
1203 // Value Description 1 An interrupt
\r
1204 // is sent to the interrupt
\r
1205 // controller when the ILLARIS bit
\r
1206 // is set. 0 The ILLARIS interrupt
\r
1207 // is suppressed and not sent to the
\r
1208 // interrupt controller.
\r
1209 #define FLASH_CTRL_FCIM_PROGMASK \
\r
1210 0x00002000 // PROGVER Interrupt Mask Value
\r
1211 // Description 1 An interrupt is
\r
1212 // sent to the interrupt controller
\r
1213 // when the PROGRIS bit is set. 0
\r
1214 // The PROGRIS interrupt is
\r
1215 // suppressed and not sent to the
\r
1216 // interrupt controller.
\r
1218 #define FLASH_CTRL_FCIM_PREMASK 0x00001000 // PREVER Interrupt Mask Value
\r
1219 // Description 1 An interrupt is
\r
1220 // sent to the interrupt controller
\r
1221 // when the PRERIS bit is set. 0 The
\r
1222 // PRERIS interrupt is suppressed
\r
1223 // and not sent to the interrupt
\r
1225 #define FLASH_CTRL_FCIM_ERMASK 0x00000800 // ERVER Interrupt Mask Value
\r
1226 // Description 1 An interrupt is
\r
1227 // sent to the interrupt controller
\r
1228 // when the ERRIS bit is set. 0 The
\r
1229 // ERRIS interrupt is suppressed and
\r
1230 // not sent to the interrupt
\r
1232 #define FLASH_CTRL_FCIM_INVDMASK \
\r
1233 0x00000400 // Invalid Data Interrupt Mask
\r
1234 // Value Description 1 An interrupt
\r
1235 // is sent to the interrupt
\r
1236 // controller when the INVDRIS bit
\r
1237 // is set. 0 The INVDRIS interrupt
\r
1238 // is suppressed and not sent to the
\r
1239 // interrupt controller.
\r
1241 #define FLASH_CTRL_FCIM_VOLTMASK \
\r
1242 0x00000200 // VOLT Interrupt Mask Value
\r
1243 // Description 1 An interrupt is
\r
1244 // sent to the interrupt controller
\r
1245 // when the VOLTRIS bit is set. 0
\r
1246 // The VOLTRIS interrupt is
\r
1247 // suppressed and not sent to the
\r
1248 // interrupt controller.
\r
1250 #define FLASH_CTRL_FCIM_LOCKMASK \
\r
1251 0x00000100 // LOCK Interrupt Mask Value
\r
1252 // Description 1 An interrupt is
\r
1253 // sent to the interrupt controller
\r
1254 // when the LOCKRIS bit is set. 0
\r
1255 // The LOCKRIS interrupt is
\r
1256 // suppressed and not sent to the
\r
1257 // interrupt controller.
\r
1259 #define FLASH_CTRL_FCIM_EMASK 0x00000004 // EEPROM Interrupt Mask Value
\r
1260 // Description 1 An interrupt is
\r
1261 // sent to the interrupt controller
\r
1262 // when the ERIS bit is set. 0 The
\r
1263 // ERIS interrupt is suppressed and
\r
1264 // not sent to the interrupt
\r
1266 #define FLASH_CTRL_FCIM_PMASK 0x00000002 // Programming Interrupt Mask This
\r
1267 // bit controls the reporting of the
\r
1268 // programming raw interrupt status
\r
1269 // to the interrupt controller.
\r
1270 // Value Description 1 An interrupt
\r
1271 // is sent to the interrupt
\r
1272 // controller when the PRIS bit is
\r
1273 // set. 0 The PRIS interrupt is
\r
1274 // suppressed and not sent to the
\r
1275 // interrupt controller.
\r
1276 #define FLASH_CTRL_FCIM_AMASK 0x00000001 // Access Interrupt Mask This bit
\r
1277 // controls the reporting of the
\r
1278 // access raw interrupt status to
\r
1279 // the interrupt controller. Value
\r
1280 // Description 1 An interrupt is
\r
1281 // sent to the interrupt controller
\r
1282 // when the ARIS bit is set. 0 The
\r
1283 // ARIS interrupt is suppressed and
\r
1284 // not sent to the interrupt
\r
1286 //******************************************************************************
\r
1288 // The following are defines for the bit fields in the
\r
1289 // FLASH_CTRL_O_FCMISC register.
\r
1291 //******************************************************************************
\r
1292 #define FLASH_CTRL_FCMISC_ILLMISC \
\r
1293 0x00004000 // Illegal Address Masked Interrupt
\r
1294 // Status and Clear Value
\r
1295 // Description 1 When read a 1
\r
1296 // indicates that an unmasked
\r
1297 // interrupt was signaled. Writing a
\r
1298 // 1 to this bit clears ILLAMISC and
\r
1299 // also the ILLARIS bit in the FCRIS
\r
1300 // register (see page 540). 0 When
\r
1301 // read a 0 indicates that an
\r
1302 // interrupt has not occurred. A
\r
1303 // write of 0 has no effect on the
\r
1304 // state of this bit.
\r
1306 #define FLASH_CTRL_FCMISC_PROGMISC \
\r
1307 0x00002000 // PROGVER Masked Interrupt Status
\r
1308 // and Clear Value Description 1
\r
1309 // When read a 1 indicates that an
\r
1310 // unmasked interrupt was signaled.
\r
1311 // Writing a 1 to this bit clears
\r
1312 // PROGMISC and also the PROGRIS bit
\r
1313 // in the FCRIS register (see page
\r
1314 // 540). 0 When read a 0 indicates
\r
1315 // that an interrupt has not
\r
1316 // occurred. A write of 0 has no
\r
1317 // effect on the state of this bit.
\r
1319 #define FLASH_CTRL_FCMISC_PREMISC \
\r
1320 0x00001000 // PREVER Masked Interrupt Status
\r
1321 // and Clear Value Description 1
\r
1322 // When read a 1 indicates that an
\r
1323 // unmasked interrupt was signaled.
\r
1324 // Writing a 1 to this bit clears
\r
1325 // PREMISC and also the PRERIS bit
\r
1326 // in the FCRIS register . 0 When
\r
1327 // read a 0 indicates that an
\r
1328 // interrupt has not occurred. A
\r
1329 // write of 0 has no effect on the
\r
1330 // state of this bit.
\r
1332 #define FLASH_CTRL_FCMISC_ERMISC \
\r
1333 0x00000800 // ERVER Masked Interrupt Status
\r
1334 // and Clear Value Description 1
\r
1335 // When read a 1 indicates that an
\r
1336 // unmasked interrupt was signaled.
\r
1337 // Writing a 1 to this bit clears
\r
1338 // ERMISC and also the ERRIS bit in
\r
1339 // the FCRIS register 0 When read a
\r
1340 // 0 indicates that an interrupt has
\r
1341 // not occurred. A write of 0 has no
\r
1342 // effect on the state of this bit.
\r
1344 #define FLASH_CTRL_FCMISC_INVDMISC \
\r
1345 0x00000400 // Invalid Data Masked Interrupt
\r
1346 // Status and Clear Value
\r
1347 // Description 1 When read a 1
\r
1348 // indicates that an unmasked
\r
1349 // interrupt was signaled. Writing a
\r
1350 // 1 to this bit clears INVDMISC and
\r
1351 // also the INVDRIS bit in the FCRIS
\r
1352 // register (see page 540). 0 When
\r
1353 // read a 0 indicates that an
\r
1354 // interrupt has not occurred. A
\r
1355 // write of 0 has no effect on the
\r
1356 // state of this bit.
\r
1358 #define FLASH_CTRL_FCMISC_VOLTMISC \
\r
1359 0x00000200 // VOLT Masked Interrupt Status and
\r
1360 // Clear Value Description 1 When
\r
1361 // read a 1 indicates that an
\r
1362 // unmasked interrupt was signaled.
\r
1363 // Writing a 1 to this bit clears
\r
1364 // VOLTMISC and also the VOLTRIS bit
\r
1365 // in the FCRIS register (see page
\r
1366 // 540). 0 When read a 0 indicates
\r
1367 // that an interrupt has not
\r
1368 // occurred. A write of 0 has no
\r
1369 // effect on the state of this bit.
\r
1371 #define FLASH_CTRL_FCMISC_LOCKMISC \
\r
1372 0x00000100 // LOCK Masked Interrupt Status and
\r
1373 // Clear Value Description 1 When
\r
1374 // read a 1 indicates that an
\r
1375 // unmasked interrupt was signaled.
\r
1376 // Writing a 1 to this bit clears
\r
1377 // LOCKMISC and also the LOCKRIS bit
\r
1378 // in the FCRIS register (see page
\r
1379 // 540). 0 When read a 0 indicates
\r
1380 // that an interrupt has not
\r
1381 // occurred. A write of 0 has no
\r
1382 // effect on the state of this bit.
\r
1384 #define FLASH_CTRL_FCMISC_EMISC 0x00000004 // EEPROM Masked Interrupt Status
\r
1385 // and Clear Value Description 1
\r
1386 // When read a 1 indicates that an
\r
1387 // unmasked interrupt was signaled.
\r
1388 // Writing a 1 to this bit clears
\r
1389 // EMISC and also the ERIS bit in
\r
1390 // the FCRIS register 0 When read a
\r
1391 // 0 indicates that an interrupt has
\r
1392 // not occurred. A write of 0 has no
\r
1393 // effect on the state of this bit.
\r
1394 #define FLASH_CTRL_FCMISC_PMISC 0x00000002 // Programming Masked Interrupt
\r
1395 // Status and Clear Value
\r
1396 // Description 1 When read a 1
\r
1397 // indicates that an unmasked
\r
1398 // interrupt was signaled because a
\r
1399 // programming cycle completed.
\r
1400 // Writing a 1 to this bit clears
\r
1401 // PMISC and also the PRIS bit in
\r
1402 // the FCRIS register 0 When read a
\r
1403 // 0 indicates that a programming
\r
1404 // cycle complete interrupt has not
\r
1405 // occurred. A write of 0 has no
\r
1406 // effect on the state of this bit.
\r
1407 #define FLASH_CTRL_FCMISC_AMISC 0x00000001 // Access Masked Interrupt Status
\r
1408 // and Clear Value Description 1
\r
1409 // When read a 1 indicates that an
\r
1410 // unmasked interrupt was signaled
\r
1411 // because a program or erase action
\r
1412 // was attempted on a block of Flash
\r
1413 // memory that contradicts the
\r
1414 // protection policy for that block
\r
1415 // as set in the FMPPEn registers.
\r
1416 // Writing a 1 to this bit clears
\r
1417 // AMISC and also the ARIS bit in
\r
1418 // the FCRIS register 0 When read a
\r
1419 // 0 indicates that no improper
\r
1420 // accesses have occurred. A write
\r
1421 // of 0 has no effect on the state
\r
1423 //******************************************************************************
\r
1425 // The following are defines for the bit fields in the FLASH_CTRL_O_FMC2 register.
\r
1427 //******************************************************************************
\r
1428 #define FLASH_CTRL_FMC2_WRKEY_M 0xFFFF0000 // Flash Memory Write Key This
\r
1429 // field contains a write key which
\r
1430 // is used to minimize the incidence
\r
1431 // of accidental Flash memory
\r
1432 // writes. The value 0xA442 must be
\r
1433 // written into this field for a
\r
1434 // write to occur. Writes to the
\r
1435 // FMC2 register without this WRKEY
\r
1436 // value are ignored. A read of this
\r
1437 // field returns the value 0.
\r
1438 #define FLASH_CTRL_FMC2_WRKEY_S 16
\r
1439 #define FLASH_CTRL_FMC2_WRBUF 0x00000001 // Buffered Flash Memory Write This
\r
1440 // bit is used to start a buffered
\r
1441 // write to Flash memory. Value
\r
1442 // Description 1 Set this bit to
\r
1443 // write the data stored in the FWBn
\r
1444 // registers to the location
\r
1445 // specified by the contents of the
\r
1446 // FMA register. When read a 1
\r
1447 // indicates that the previous
\r
1448 // buffered Flash memory write
\r
1449 // access is not complete. 0 A write
\r
1450 // of 0 has no effect on the state
\r
1451 // of this bit. When read a 0
\r
1452 // indicates that the previous
\r
1453 // buffered Flash memory write
\r
1454 // access is complete.
\r
1455 //******************************************************************************
\r
1457 // The following are defines for the bit fields in the
\r
1458 // FLASH_CTRL_O_FWBVAL register.
\r
1460 //******************************************************************************
\r
1461 #define FLASH_CTRL_FWBVAL_FWBN_M \
\r
1462 0xFFFFFFFF // Flash Memory Write Buffer Value
\r
1463 // Description 1 The corresponding
\r
1464 // FWBn register has been updated
\r
1465 // since the last buffer write
\r
1466 // operation and is ready to be
\r
1467 // written to Flash memory. 0 The
\r
1468 // corresponding FWBn register has
\r
1469 // no new data to be written. Bit 0
\r
1470 // corresponds to FWB0 offset 0x100
\r
1471 // and bit 31 corresponds to FWB31
\r
1474 #define FLASH_CTRL_FWBVAL_FWBN_S 0
\r
1475 //******************************************************************************
\r
1477 // The following are defines for the bit fields in the FLASH_CTRL_O_FWB1 register.
\r
1479 //******************************************************************************
\r
1480 #define FLASH_CTRL_FWB1_DATA_M 0xFFFFFFFF // Data Data to be written into the
\r
1482 #define FLASH_CTRL_FWB1_DATA_S 0
\r
1483 //******************************************************************************
\r
1485 // The following are defines for the bit fields in the FLASH_CTRL_O_FWB2 register.
\r
1487 //******************************************************************************
\r
1488 #define FLASH_CTRL_FWB2_DATA_M 0xFFFFFFFF // Data Data to be written into the
\r
1490 #define FLASH_CTRL_FWB2_DATA_S 0
\r
1491 //******************************************************************************
\r
1493 // The following are defines for the bit fields in the FLASH_CTRL_O_FWB3 register.
\r
1495 //******************************************************************************
\r
1496 #define FLASH_CTRL_FWB3_DATA_M 0xFFFFFFFF // Data Data to be written into the
\r
1498 #define FLASH_CTRL_FWB3_DATA_S 0
\r
1499 //******************************************************************************
\r
1501 // The following are defines for the bit fields in the FLASH_CTRL_O_FWB4 register.
\r
1503 //******************************************************************************
\r
1504 #define FLASH_CTRL_FWB4_DATA_M 0xFFFFFFFF // Data Data to be written into the
\r
1506 #define FLASH_CTRL_FWB4_DATA_S 0
\r
1507 //******************************************************************************
\r
1509 // The following are defines for the bit fields in the FLASH_CTRL_O_FWB5 register.
\r
1511 //******************************************************************************
\r
1512 #define FLASH_CTRL_FWB5_DATA_M 0xFFFFFFFF // Data Data to be written into the
\r
1514 #define FLASH_CTRL_FWB5_DATA_S 0
\r
1515 //******************************************************************************
\r
1517 // The following are defines for the bit fields in the FLASH_CTRL_O_FWB6 register.
\r
1519 //******************************************************************************
\r
1520 #define FLASH_CTRL_FWB6_DATA_M 0xFFFFFFFF // Data Data to be written into the
\r
1522 #define FLASH_CTRL_FWB6_DATA_S 0
\r
1523 //******************************************************************************
\r
1525 // The following are defines for the bit fields in the FLASH_CTRL_O_FWB7 register.
\r
1527 //******************************************************************************
\r
1528 #define FLASH_CTRL_FWB7_DATA_M 0xFFFFFFFF // Data Data to be written into the
\r
1530 #define FLASH_CTRL_FWB7_DATA_S 0
\r
1531 //******************************************************************************
\r
1533 // The following are defines for the bit fields in the FLASH_CTRL_O_FWB8 register.
\r
1535 //******************************************************************************
\r
1536 #define FLASH_CTRL_FWB8_DATA_M 0xFFFFFFFF // Data Data to be written into the
\r
1538 #define FLASH_CTRL_FWB8_DATA_S 0
\r
1539 //******************************************************************************
\r
1541 // The following are defines for the bit fields in the FLASH_CTRL_O_FWB9 register.
\r
1543 //******************************************************************************
\r
1544 #define FLASH_CTRL_FWB9_DATA_M 0xFFFFFFFF // Data Data to be written into the
\r
1546 #define FLASH_CTRL_FWB9_DATA_S 0
\r
1547 //******************************************************************************
\r
1549 // The following are defines for the bit fields in the
\r
1550 // FLASH_CTRL_O_FWB10 register.
\r
1552 //******************************************************************************
\r
1553 #define FLASH_CTRL_FWB10_DATA_M 0xFFFFFFFF // Data Data to be written into the
\r
1555 #define FLASH_CTRL_FWB10_DATA_S 0
\r
1556 //******************************************************************************
\r
1558 // The following are defines for the bit fields in the
\r
1559 // FLASH_CTRL_O_FWB11 register.
\r
1561 //******************************************************************************
\r
1562 #define FLASH_CTRL_FWB11_DATA_M 0xFFFFFFFF // Data Data to be written into the
\r
1564 #define FLASH_CTRL_FWB11_DATA_S 0
\r
1565 //******************************************************************************
\r
1567 // The following are defines for the bit fields in the
\r
1568 // FLASH_CTRL_O_FWB12 register.
\r
1570 //******************************************************************************
\r
1571 #define FLASH_CTRL_FWB12_DATA_M 0xFFFFFFFF // Data Data to be written into the
\r
1573 #define FLASH_CTRL_FWB12_DATA_S 0
\r
1574 //******************************************************************************
\r
1576 // The following are defines for the bit fields in the
\r
1577 // FLASH_CTRL_O_FWB13 register.
\r
1579 //******************************************************************************
\r
1580 #define FLASH_CTRL_FWB13_DATA_M 0xFFFFFFFF // Data Data to be written into the
\r
1582 #define FLASH_CTRL_FWB13_DATA_S 0
\r
1583 //******************************************************************************
\r
1585 // The following are defines for the bit fields in the
\r
1586 // FLASH_CTRL_O_FWB14 register.
\r
1588 //******************************************************************************
\r
1589 #define FLASH_CTRL_FWB14_DATA_M 0xFFFFFFFF // Data Data to be written into the
\r
1591 #define FLASH_CTRL_FWB14_DATA_S 0
\r
1592 //******************************************************************************
\r
1594 // The following are defines for the bit fields in the
\r
1595 // FLASH_CTRL_O_FWB15 register.
\r
1597 //******************************************************************************
\r
1598 #define FLASH_CTRL_FWB15_DATA_M 0xFFFFFFFF // Data Data to be written into the
\r
1600 #define FLASH_CTRL_FWB15_DATA_S 0
\r
1601 //******************************************************************************
\r
1603 // The following are defines for the bit fields in the
\r
1604 // FLASH_CTRL_O_FWB16 register.
\r
1606 //******************************************************************************
\r
1607 #define FLASH_CTRL_FWB16_DATA_M 0xFFFFFFFF // Data Data to be written into the
\r
1609 #define FLASH_CTRL_FWB16_DATA_S 0
\r
1610 //******************************************************************************
\r
1612 // The following are defines for the bit fields in the
\r
1613 // FLASH_CTRL_O_FWB17 register.
\r
1615 //******************************************************************************
\r
1616 #define FLASH_CTRL_FWB17_DATA_M 0xFFFFFFFF // Data Data to be written into the
\r
1618 #define FLASH_CTRL_FWB17_DATA_S 0
\r
1619 //******************************************************************************
\r
1621 // The following are defines for the bit fields in the
\r
1622 // FLASH_CTRL_O_FWB18 register.
\r
1624 //******************************************************************************
\r
1625 #define FLASH_CTRL_FWB18_DATA_M 0xFFFFFFFF // Data Data to be written into the
\r
1627 #define FLASH_CTRL_FWB18_DATA_S 0
\r
1628 //******************************************************************************
\r
1630 // The following are defines for the bit fields in the
\r
1631 // FLASH_CTRL_O_FWB19 register.
\r
1633 //******************************************************************************
\r
1634 #define FLASH_CTRL_FWB19_DATA_M 0xFFFFFFFF // Data Data to be written into the
\r
1636 #define FLASH_CTRL_FWB19_DATA_S 0
\r
1637 //******************************************************************************
\r
1639 // The following are defines for the bit fields in the
\r
1640 // FLASH_CTRL_O_FWB20 register.
\r
1642 //******************************************************************************
\r
1643 #define FLASH_CTRL_FWB20_DATA_M 0xFFFFFFFF // Data Data to be written into the
\r
1645 #define FLASH_CTRL_FWB20_DATA_S 0
\r
1646 //******************************************************************************
\r
1648 // The following are defines for the bit fields in the
\r
1649 // FLASH_CTRL_O_FWB21 register.
\r
1651 //******************************************************************************
\r
1652 #define FLASH_CTRL_FWB21_DATA_M 0xFFFFFFFF // Data Data to be written into the
\r
1654 #define FLASH_CTRL_FWB21_DATA_S 0
\r
1655 //******************************************************************************
\r
1657 // The following are defines for the bit fields in the
\r
1658 // FLASH_CTRL_O_FWB22 register.
\r
1660 //******************************************************************************
\r
1661 #define FLASH_CTRL_FWB22_DATA_M 0xFFFFFFFF // Data Data to be written into the
\r
1663 #define FLASH_CTRL_FWB22_DATA_S 0
\r
1664 //******************************************************************************
\r
1666 // The following are defines for the bit fields in the
\r
1667 // FLASH_CTRL_O_FWB23 register.
\r
1669 //******************************************************************************
\r
1670 #define FLASH_CTRL_FWB23_DATA_M 0xFFFFFFFF // Data Data to be written into the
\r
1672 #define FLASH_CTRL_FWB23_DATA_S 0
\r
1673 //******************************************************************************
\r
1675 // The following are defines for the bit fields in the
\r
1676 // FLASH_CTRL_O_FWB24 register.
\r
1678 //******************************************************************************
\r
1679 #define FLASH_CTRL_FWB24_DATA_M 0xFFFFFFFF // Data Data to be written into the
\r
1681 #define FLASH_CTRL_FWB24_DATA_S 0
\r
1682 //******************************************************************************
\r
1684 // The following are defines for the bit fields in the
\r
1685 // FLASH_CTRL_O_FWB25 register.
\r
1687 //******************************************************************************
\r
1688 #define FLASH_CTRL_FWB25_DATA_M 0xFFFFFFFF // Data Data to be written into the
\r
1690 #define FLASH_CTRL_FWB25_DATA_S 0
\r
1691 //******************************************************************************
\r
1693 // The following are defines for the bit fields in the
\r
1694 // FLASH_CTRL_O_FWB26 register.
\r
1696 //******************************************************************************
\r
1697 #define FLASH_CTRL_FWB26_DATA_M 0xFFFFFFFF // Data Data to be written into the
\r
1699 #define FLASH_CTRL_FWB26_DATA_S 0
\r
1700 //******************************************************************************
\r
1702 // The following are defines for the bit fields in the
\r
1703 // FLASH_CTRL_O_FWB27 register.
\r
1705 //******************************************************************************
\r
1706 #define FLASH_CTRL_FWB27_DATA_M 0xFFFFFFFF // Data Data to be written into the
\r
1708 #define FLASH_CTRL_FWB27_DATA_S 0
\r
1709 //******************************************************************************
\r
1711 // The following are defines for the bit fields in the
\r
1712 // FLASH_CTRL_O_FWB28 register.
\r
1714 //******************************************************************************
\r
1715 #define FLASH_CTRL_FWB28_DATA_M 0xFFFFFFFF // Data Data to be written into the
\r
1717 #define FLASH_CTRL_FWB28_DATA_S 0
\r
1718 //******************************************************************************
\r
1720 // The following are defines for the bit fields in the
\r
1721 // FLASH_CTRL_O_FWB29 register.
\r
1723 //******************************************************************************
\r
1724 #define FLASH_CTRL_FWB29_DATA_M 0xFFFFFFFF // Data Data to be written into the
\r
1726 #define FLASH_CTRL_FWB29_DATA_S 0
\r
1727 //******************************************************************************
\r
1729 // The following are defines for the bit fields in the
\r
1730 // FLASH_CTRL_O_FWB30 register.
\r
1732 //******************************************************************************
\r
1733 #define FLASH_CTRL_FWB30_DATA_M 0xFFFFFFFF // Data Data to be written into the
\r
1735 #define FLASH_CTRL_FWB30_DATA_S 0
\r
1736 //******************************************************************************
\r
1738 // The following are defines for the bit fields in the
\r
1739 // FLASH_CTRL_O_FWB31 register.
\r
1741 //******************************************************************************
\r
1742 #define FLASH_CTRL_FWB31_DATA_M 0xFFFFFFFF // Data Data to be written into the
\r
1744 #define FLASH_CTRL_FWB31_DATA_S 0
\r
1745 //******************************************************************************
\r
1747 // The following are defines for the bit fields in the
\r
1748 // FLASH_CTRL_O_FWB32 register.
\r
1750 //******************************************************************************
\r
1751 #define FLASH_CTRL_FWB32_DATA_M 0xFFFFFFFF // Data Data to be written into the
\r
1753 #define FLASH_CTRL_FWB32_DATA_S 0
\r
1754 //******************************************************************************
\r
1756 // The following are defines for the bit fields in the
\r
1757 // FLASH_CTRL_O_FSIZE register.
\r
1759 //******************************************************************************
\r
1760 #define FLASH_CTRL_FSIZE_SIZE_M 0x0000FFFF // Flash Size Indicates the size of
\r
1761 // the on-chip Flash memory. Value
\r
1762 // Description 0x0003 8 KB of Flash
\r
1763 // 0x0007 16 KB of Flash 0x000F 32
\r
1764 // KB of Flash 0x001F 64 KB of Flash
\r
1765 // 0x002F 96 KB of Flash 0x003F 128
\r
1766 // KB of Flash 0x005F 192 KB of
\r
1767 // Flash 0x007F 256 KB of Flash
\r
1768 #define FLASH_CTRL_FSIZE_SIZE_S 0
\r
1769 //******************************************************************************
\r
1771 // The following are defines for the bit fields in the
\r
1772 // FLASH_CTRL_O_SSIZE register.
\r
1774 //******************************************************************************
\r
1775 #define FLASH_CTRL_SSIZE_SRAM_SIZE_M \
\r
1776 0x0000FFFF // SRAM Size Indicates the size of
\r
1777 // the on-chip SRAM. Value
\r
1778 // Description 0x0007 2 KB of SRAM
\r
1779 // 0x000F 4 KB of SRAM 0x0017 6 KB
\r
1780 // of SRAM 0x001F 8 KB of SRAM
\r
1781 // 0x002F 12 KB of SRAM 0x003F 16 KB
\r
1782 // of SRAM 0x004F 20 KB of SRAM
\r
1783 // 0x005F 24 KB of SRAM 0x007F 32 KB
\r
1786 #define FLASH_CTRL_SSIZE_SRAM_SIZE_S 0
\r
1787 #define FLASH_CTRL_FMC_WRKEY 0xA4420000 // FLASH write key
\r
1788 #define FLASH_CTRL_FMC2_WRKEY 0xA4420000 // FLASH write key
\r
1789 #define FLASH_CTRL_O_FWBN FLASH_CTRL_O_FWB1
\r
1790 #define FLASH_ERASE_SIZE 0x00000400
\r
1791 #define FLASH_PROTECT_SIZE 0x00000800
\r
1792 #define FLASH_FMP_BLOCK_0 0x00000001 // Enable for block 0
\r
1794 #define FLASH_FMPRE0 0x400FE200 // Flash Memory Protection Read
\r
1796 #define FLASH_FMPRE1 0x400FE204 // Flash Memory Protection Read
\r
1798 #define FLASH_FMPRE2 0x400FE208 // Flash Memory Protection Read
\r
1800 #define FLASH_FMPRE3 0x400FE20C // Flash Memory Protection Read
\r
1802 #define FLASH_FMPRE4 0x400FE210 // Flash Memory Protection Read
\r
1804 #define FLASH_FMPRE5 0x400FE214 // Flash Memory Protection Read
\r
1806 #define FLASH_FMPRE6 0x400FE218 // Flash Memory Protection Read
\r
1808 #define FLASH_FMPRE7 0x400FE21C // Flash Memory Protection Read
\r
1810 #define FLASH_FMPRE8 0x400FE220 // Flash Memory Protection Read
\r
1812 #define FLASH_FMPRE9 0x400FE224 // Flash Memory Protection Read
\r
1814 #define FLASH_FMPRE10 0x400FE228 // Flash Memory Protection Read
\r
1816 #define FLASH_FMPRE11 0x400FE22C // Flash Memory Protection Read
\r
1818 #define FLASH_FMPRE12 0x400FE230 // Flash Memory Protection Read
\r
1820 #define FLASH_FMPRE13 0x400FE234 // Flash Memory Protection Read
\r
1822 #define FLASH_FMPRE14 0x400FE238 // Flash Memory Protection Read
\r
1824 #define FLASH_FMPRE15 0x400FE23C // Flash Memory Protection Read
\r
1827 #define FLASH_FMPPE0 0x400FE400 // Flash Memory Protection Program
\r
1829 #define FLASH_FMPPE1 0x400FE404 // Flash Memory Protection Program
\r
1831 #define FLASH_FMPPE2 0x400FE408 // Flash Memory Protection Program
\r
1833 #define FLASH_FMPPE3 0x400FE40C // Flash Memory Protection Program
\r
1835 #define FLASH_FMPPE4 0x400FE410 // Flash Memory Protection Program
\r
1837 #define FLASH_FMPPE5 0x400FE414 // Flash Memory Protection Program
\r
1839 #define FLASH_FMPPE6 0x400FE418 // Flash Memory Protection Program
\r
1841 #define FLASH_FMPPE7 0x400FE41C // Flash Memory Protection Program
\r
1843 #define FLASH_FMPPE8 0x400FE420 // Flash Memory Protection Program
\r
1845 #define FLASH_FMPPE9 0x400FE424 // Flash Memory Protection Program
\r
1847 #define FLASH_FMPPE10 0x400FE428 // Flash Memory Protection Program
\r
1849 #define FLASH_FMPPE11 0x400FE42C // Flash Memory Protection Program
\r
1851 #define FLASH_FMPPE12 0x400FE430 // Flash Memory Protection Program
\r
1853 #define FLASH_FMPPE13 0x400FE434 // Flash Memory Protection Program
\r
1855 #define FLASH_FMPPE14 0x400FE438 // Flash Memory Protection Program
\r
1857 #define FLASH_FMPPE15 0x400FE43C // Flash Memory Protection Program
\r
1860 #define FLASH_USECRL 0x400FE140 // USec Reload
\r
1861 #define FLASH_CTRL_ERASE_SIZE 0x00000400
\r
1864 #endif // __HW_FLASH_CTRL_H__
\r
projects / freertos / blob