2 * -------------------------------------------
\r
3 * CC3220 SDK - v0.10.00.00
\r
4 * -------------------------------------------
\r
6 * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/
\r
8 * Redistribution and use in source and binary forms, with or without
\r
9 * modification, are permitted provided that the following conditions
\r
12 * Redistributions of source code must retain the above copyright
\r
13 * notice, this list of conditions and the following disclaimer.
\r
15 * Redistributions in binary form must reproduce the above copyright
\r
16 * notice, this list of conditions and the following disclaimer in the
\r
17 * documentation and/or other materials provided with the
\r
20 * Neither the name of Texas Instruments Incorporated nor the names of
\r
21 * its contributors may be used to endorse or promote products derived
\r
22 * from this software without specific prior written permission.
\r
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
\r
25 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
\r
26 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
\r
27 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
\r
28 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
\r
29 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
\r
30 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
\r
31 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
\r
32 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
\r
33 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
\r
34 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
\r
38 #ifndef __HW_HIB3P3_H__
\r
39 #define __HW_HIB3P3_H__
\r
41 //*****************************************************************************
\r
43 // The following are defines for the HIB3P3 register offsets.
\r
45 //*****************************************************************************
\r
46 #define HIB3P3_O_MEM_HIB_REQ 0x00000000
\r
47 #define HIB3P3_O_MEM_HIB_RTC_TIMER_ENABLE \
\r
50 #define HIB3P3_O_MEM_HIB_RTC_TIMER_RESET \
\r
53 #define HIB3P3_O_MEM_HIB_RTC_TIMER_READ \
\r
56 #define HIB3P3_O_MEM_HIB_RTC_TIMER_LSW \
\r
59 #define HIB3P3_O_MEM_HIB_RTC_TIMER_MSW \
\r
62 #define HIB3P3_O_MEM_HIB_RTC_WAKE_EN \
\r
65 #define HIB3P3_O_MEM_HIB_RTC_WAKE_LSW_CONF \
\r
68 #define HIB3P3_O_MEM_HIB_RTC_WAKE_MSW_CONF \
\r
71 #define HIB3P3_O_MEM_INT_OSC_CONF \
\r
74 #define HIB3P3_O_MEM_XTAL_OSC_CONF \
\r
77 #define HIB3P3_O_MEM_BGAP_PARAMETERS0 \
\r
80 #define HIB3P3_O_MEM_BGAP_PARAMETERS1 \
\r
83 #define HIB3P3_O_MEM_HIB_DETECTION_STATUS \
\r
86 #define HIB3P3_O_MEM_HIB_MISC_CONTROLS \
\r
89 #define HIB3P3_O_MEM_HIB_CONFIG 0x00000050
\r
90 #define HIB3P3_O_MEM_HIB_RTC_IRQ_ENABLE \
\r
93 #define HIB3P3_O_MEM_HIB_RTC_IRQ_LSW_CONF \
\r
96 #define HIB3P3_O_MEM_HIB_RTC_IRQ_MSW_CONF \
\r
99 #define HIB3P3_O_MEM_HIB_UART_CONF \
\r
102 #define HIB3P3_O_MEM_GPIO_WAKE_EN \
\r
105 #define HIB3P3_O_MEM_GPIO_WAKE_CONF \
\r
108 #define HIB3P3_O_MEM_PAD_OEN_RET33_CONF \
\r
111 #define HIB3P3_O_MEM_UART_RTS_OEN_RET33_CONF \
\r
114 #define HIB3P3_O_MEM_JTAG_CONF 0x00000414
\r
115 #define HIB3P3_O_MEM_HIB_REG0 0x00000418
\r
116 #define HIB3P3_O_MEM_HIB_REG1 0x0000041C
\r
117 #define HIB3P3_O_MEM_HIB_REG2 0x00000420
\r
118 #define HIB3P3_O_MEM_HIB_REG3 0x00000424
\r
119 #define HIB3P3_O_MEM_HIB_SEQUENCER_CFG0 \
\r
122 #define HIB3P3_O_MEM_HIB_SEQUENCER_CFG1 \
\r
125 #define HIB3P3_O_MEM_HIB_MISC_CONFIG \
\r
128 #define HIB3P3_O_MEM_HIB_WAKE_STATUS \
\r
131 #define HIB3P3_O_MEM_HIB_LPDS_GPIO_SEL \
\r
134 #define HIB3P3_O_MEM_HIB_SEQUENCER_CFG2 \
\r
137 #define HIB3P3_O_HIBANA_SPARE_LOWV \
\r
140 #define HIB3P3_O_HIB_TMUX_CTRL 0x00000478
\r
141 #define HIB3P3_O_HIB_1P2_1P8_LDO_TRIM \
\r
144 #define HIB3P3_O_HIB_COMP_TRIM 0x00000480
\r
145 #define HIB3P3_O_HIB_EN_TS 0x00000484
\r
146 #define HIB3P3_O_HIB_1P8V_DET_EN \
\r
149 #define HIB3P3_O_HIB_VBAT_MON_EN \
\r
152 #define HIB3P3_O_HIB_NHIB_ENABLE \
\r
155 #define HIB3P3_O_HIB_UART_RTS_SW_ENABLE \
\r
161 //******************************************************************************
\r
163 // The following are defines for the bit fields in the
\r
164 // HIB3P3_O_MEM_HIB_REQ register.
\r
166 //******************************************************************************
\r
167 #define HIB3P3_MEM_HIB_REQ_reserved_M \
\r
170 #define HIB3P3_MEM_HIB_REQ_reserved_S 9
\r
171 #define HIB3P3_MEM_HIB_REQ_NU1_M \
\r
174 #define HIB3P3_MEM_HIB_REQ_NU1_S 2
\r
175 #define HIB3P3_MEM_HIB_REQ_mem_hib_clk_disable \
\r
176 0x00000002 // 1 - Specifies that the Hiberante
\r
177 // mode is without clocks ; 0 -
\r
178 // Specified that the Hibernate mode
\r
179 // is with clocks This register will
\r
180 // be reset during Hibernate
\r
181 // -WO-Clks mode (but not during
\r
182 // Hibernate-W-Clks mode).
\r
184 #define HIB3P3_MEM_HIB_REQ_mem_hib_req \
\r
185 0x00000001 // 1 - Request for hibernate mode
\r
186 // (This is an auto-clear bit) ; 0 -
\r
187 // Donot request for hibernate mode
\r
188 // This register will be reset
\r
189 // during Hibernate -WO-Clks mode
\r
190 // (but not during Hibernate-W-Clks
\r
193 //******************************************************************************
\r
195 // The following are defines for the bit fields in the
\r
196 // HIB3P3_O_MEM_HIB_RTC_TIMER_ENABLE register.
\r
198 //******************************************************************************
\r
199 #define HIB3P3_MEM_HIB_RTC_TIMER_ENABLE_reserved_M \
\r
202 #define HIB3P3_MEM_HIB_RTC_TIMER_ENABLE_reserved_S 1
\r
203 #define HIB3P3_MEM_HIB_RTC_TIMER_ENABLE_mem_hib_rtc_timer_enable \
\r
204 0x00000001 // 1 - Enable the RTC timer to
\r
205 // start running ; 0 - Keep the RTC
\r
206 // timer disabled This register will
\r
207 // be reset during Hibernate
\r
208 // -WO-Clks mode (but not during
\r
209 // Hibernate-W-Clks mode).
\r
211 //******************************************************************************
\r
213 // The following are defines for the bit fields in the
\r
214 // HIB3P3_O_MEM_HIB_RTC_TIMER_RESET register.
\r
216 //******************************************************************************
\r
217 #define HIB3P3_MEM_HIB_RTC_TIMER_RESET_reserved_M \
\r
220 #define HIB3P3_MEM_HIB_RTC_TIMER_RESET_reserved_S 1
\r
221 #define HIB3P3_MEM_HIB_RTC_TIMER_RESET_mem_hib_rtc_timer_reset \
\r
222 0x00000001 // 1 - Reset the RTC timer ; 0 -
\r
223 // Donot reset the RTC timer. This
\r
224 // is an auto-clear bit. This
\r
225 // register will be reset during
\r
226 // Hibernate -WO-Clks mode (but not
\r
227 // during Hibernate-W-Clks mode).
\r
229 //******************************************************************************
\r
231 // The following are defines for the bit fields in the
\r
232 // HIB3P3_O_MEM_HIB_RTC_TIMER_READ register.
\r
234 //******************************************************************************
\r
235 #define HIB3P3_MEM_HIB_RTC_TIMER_READ_reserved_M \
\r
238 #define HIB3P3_MEM_HIB_RTC_TIMER_READ_reserved_S 1
\r
239 #define HIB3P3_MEM_HIB_RTC_TIMER_READ_mem_hib_rtc_timer_read \
\r
240 0x00000001 // 1 - Latch the running RTC timer
\r
241 // into local registers. After
\r
242 // programming this bit to 1, the
\r
243 // F/w can read the latched RTC
\r
244 // timer values from
\r
245 // MEM_HIB_RTC_TIMER_LSW and
\r
246 // MEM_HIB_RTC_TIMER_MSW. Before the
\r
247 // F/w (APPS or NWP) wants to read
\r
248 // the RTC-Timer, it has to program
\r
249 // this bit to 1, then only read the
\r
250 // MSW and LSW values. This is an
\r
251 // auto-clear bit. This register
\r
252 // will be reset during Hibernate
\r
253 // -WO-Clks mode (but not during
\r
254 // Hibernate-W-Clks mode).
\r
256 //******************************************************************************
\r
258 // The following are defines for the bit fields in the
\r
259 // HIB3P3_O_MEM_HIB_RTC_TIMER_LSW register.
\r
261 //******************************************************************************
\r
262 #define HIB3P3_MEM_HIB_RTC_TIMER_LSW_hib_rtc_timer_lsw_M \
\r
263 0xFFFFFFFF // Lower 32b value of the latched
\r
266 #define HIB3P3_MEM_HIB_RTC_TIMER_LSW_hib_rtc_timer_lsw_S 0
\r
267 //******************************************************************************
\r
269 // The following are defines for the bit fields in the
\r
270 // HIB3P3_O_MEM_HIB_RTC_TIMER_MSW register.
\r
272 //******************************************************************************
\r
273 #define HIB3P3_MEM_HIB_RTC_TIMER_MSW_reserved_M \
\r
276 #define HIB3P3_MEM_HIB_RTC_TIMER_MSW_reserved_S 16
\r
277 #define HIB3P3_MEM_HIB_RTC_TIMER_MSW_hib_rtc_timer_msw_M \
\r
278 0x0000FFFF // Upper 32b value of the latched
\r
281 #define HIB3P3_MEM_HIB_RTC_TIMER_MSW_hib_rtc_timer_msw_S 0
\r
282 //******************************************************************************
\r
284 // The following are defines for the bit fields in the
\r
285 // HIB3P3_O_MEM_HIB_RTC_WAKE_EN register.
\r
287 //******************************************************************************
\r
288 #define HIB3P3_MEM_HIB_RTC_WAKE_EN_reserved_M \
\r
291 #define HIB3P3_MEM_HIB_RTC_WAKE_EN_reserved_S 1
\r
292 #define HIB3P3_MEM_HIB_RTC_WAKE_EN_mem_hib_rtc_wake_en \
\r
293 0x00000001 // 1 - Enable the RTC timer based
\r
294 // wakeup during Hibernate mode ; 0
\r
295 // - Disable the RTC timer based
\r
296 // wakeup during Hibernate mode This
\r
297 // register will be reset during
\r
298 // Hibernate-WO-Clks mode (but not
\r
299 // during Hibernate-W-Clks mode).
\r
301 //******************************************************************************
\r
303 // The following are defines for the bit fields in the
\r
304 // HIB3P3_O_MEM_HIB_RTC_WAKE_LSW_CONF register.
\r
306 //******************************************************************************
\r
307 #define HIB3P3_MEM_HIB_RTC_WAKE_LSW_CONF_mem_hib_rtc_wake_lsw_conf_M \
\r
308 0xFFFFFFFF // Configuration for RTC-Timer
\r
309 // Wakeup (Lower 32b word)
\r
311 #define HIB3P3_MEM_HIB_RTC_WAKE_LSW_CONF_mem_hib_rtc_wake_lsw_conf_S 0
\r
312 //******************************************************************************
\r
314 // The following are defines for the bit fields in the
\r
315 // HIB3P3_O_MEM_HIB_RTC_WAKE_MSW_CONF register.
\r
317 //******************************************************************************
\r
318 #define HIB3P3_MEM_HIB_RTC_WAKE_MSW_CONF_reserved_M \
\r
321 #define HIB3P3_MEM_HIB_RTC_WAKE_MSW_CONF_reserved_S 16
\r
322 #define HIB3P3_MEM_HIB_RTC_WAKE_MSW_CONF_mem_hib_rtc_wake_msw_conf_M \
\r
323 0x0000FFFF // Configuration for RTC-Timer
\r
324 // Wakeup (Upper 16b word)
\r
326 #define HIB3P3_MEM_HIB_RTC_WAKE_MSW_CONF_mem_hib_rtc_wake_msw_conf_S 0
\r
327 //******************************************************************************
\r
329 // The following are defines for the bit fields in the
\r
330 // HIB3P3_O_MEM_INT_OSC_CONF register.
\r
332 //******************************************************************************
\r
333 #define HIB3P3_MEM_INT_OSC_CONF_reserved_M \
\r
336 #define HIB3P3_MEM_INT_OSC_CONF_reserved_S 16
\r
337 #define HIB3P3_MEM_INT_OSC_CONF_cm_clk_good_32k_int \
\r
338 0x00008000 // 1 - Internal 32kHz Oscillator is
\r
339 // valid ; 0 - Internal 32k
\r
340 // oscillator clk is not valid
\r
342 #define HIB3P3_MEM_INT_OSC_CONF_mem_cm_intosc_32k_spare_M \
\r
345 #define HIB3P3_MEM_INT_OSC_CONF_mem_cm_intosc_32k_spare_S 9
\r
346 #define HIB3P3_MEM_INT_OSC_CONF_mem_cm_en_intosc_32k_override_ctrl \
\r
347 0x00000100 // When 1, the INT_32K_OSC_EN comes
\r
348 // from bit [0] of this register,
\r
349 // else comes from the FSM. This
\r
350 // register will be reset during
\r
351 // Hibernate-WO-Clks mode (but not
\r
352 // during Hibernate-W-Clks mode)
\r
354 #define HIB3P3_MEM_INT_OSC_CONF_NU1 \
\r
357 #define HIB3P3_MEM_INT_OSC_CONF_mem_cm_intosc_32k_trim_M \
\r
360 #define HIB3P3_MEM_INT_OSC_CONF_mem_cm_intosc_32k_trim_S 1
\r
361 #define HIB3P3_MEM_INT_OSC_CONF_mem_cm_en_intosc_32k \
\r
362 0x00000001 // Override value for INT_OSC_EN.
\r
363 // Applicable only when bit [3] of
\r
364 // this register is set to 1.
\r
366 //******************************************************************************
\r
368 // The following are defines for the bit fields in the
\r
369 // HIB3P3_O_MEM_XTAL_OSC_CONF register.
\r
371 //******************************************************************************
\r
372 #define HIB3P3_MEM_XTAL_OSC_CONF_reserved_M \
\r
375 #define HIB3P3_MEM_XTAL_OSC_CONF_reserved_S 20
\r
376 #define HIB3P3_MEM_XTAL_OSC_CONF_mem_cm_en_sli_32k_override_ctrl \
\r
377 0x00080000 // When 1, the SLICER_EN comes from
\r
378 // bit [10] of this register, else
\r
379 // comes from the FSM.
\r
381 #define HIB3P3_MEM_XTAL_OSC_CONF_mem_cm_en_xtal_32k_override_ctrl \
\r
382 0x00040000 // When 1, the XTAL_EN comes from
\r
383 // bit [0] of this register, else
\r
384 // comes from the FSM.
\r
386 #define HIB3P3_MEM_XTAL_OSC_CONF_cm_clk_good_xtal \
\r
387 0x00020000 // 1 - XTAL Clk is good ; 0 - XTAL
\r
388 // Clk is yet to be valid.
\r
390 #define HIB3P3_MEM_XTAL_OSC_CONF_mem_cm_xtal_trim_M \
\r
393 #define HIB3P3_MEM_XTAL_OSC_CONF_mem_cm_xtal_trim_S 11
\r
394 #define HIB3P3_MEM_XTAL_OSC_CONF_mem_cm_en_sli_32k \
\r
395 0x00000400 // SLICER_EN Override value :
\r
396 // Applicable only when bit [19] of
\r
397 // this register is set to 1.
\r
399 #define HIB3P3_MEM_XTAL_OSC_CONF_mem_cm_sli_32k_trim_M \
\r
402 #define HIB3P3_MEM_XTAL_OSC_CONF_mem_cm_sli_32k_trim_S 7
\r
403 #define HIB3P3_MEM_XTAL_OSC_CONF_mem_cm_fref_32k_slicer_itrim_M \
\r
406 #define HIB3P3_MEM_XTAL_OSC_CONF_mem_cm_fref_32k_slicer_itrim_S 4
\r
407 #define HIB3P3_MEM_XTAL_OSC_CONF_mem_cm_en_fref_32k_slicer \
\r
410 #define HIB3P3_MEM_XTAL_OSC_CONF_mem_cm_en_input_sense_M \
\r
413 #define HIB3P3_MEM_XTAL_OSC_CONF_mem_cm_en_input_sense_S 1
\r
414 #define HIB3P3_MEM_XTAL_OSC_CONF_mem_cm_en_xtal_32k \
\r
415 0x00000001 // XTAL_EN Override value :
\r
416 // Applicable only when bit [18] of
\r
417 // this register is set to 1.
\r
419 //******************************************************************************
\r
421 // The following are defines for the bit fields in the
\r
422 // HIB3P3_O_MEM_BGAP_PARAMETERS0 register.
\r
424 //******************************************************************************
\r
425 #define HIB3P3_MEM_BGAP_PARAMETERS0_reserved_M \
\r
428 #define HIB3P3_MEM_BGAP_PARAMETERS0_reserved_S 19
\r
429 #define HIB3P3_MEM_BGAP_PARAMETERS0_mem_en_seq \
\r
432 #define HIB3P3_MEM_BGAP_PARAMETERS0_mem_vbok4bg_comp_trim_M \
\r
435 #define HIB3P3_MEM_BGAP_PARAMETERS0_mem_vbok4bg_comp_trim_S 14
\r
436 #define HIB3P3_MEM_BGAP_PARAMETERS0_mem_bgap_en_vbat_ok_4bg \
\r
439 #define HIB3P3_MEM_BGAP_PARAMETERS0_mem_bgap_en_vbok4bg_comp \
\r
442 #define HIB3P3_MEM_BGAP_PARAMETERS0_mem_bgap_en_vbok4bg_comp_ref \
\r
445 #define HIB3P3_MEM_BGAP_PARAMETERS0_mem_bgap_spare_M \
\r
448 #define HIB3P3_MEM_BGAP_PARAMETERS0_mem_bgap_spare_S 0
\r
449 //******************************************************************************
\r
451 // The following are defines for the bit fields in the
\r
452 // HIB3P3_O_MEM_BGAP_PARAMETERS1 register.
\r
454 //******************************************************************************
\r
455 #define HIB3P3_MEM_BGAP_PARAMETERS1_reserved_M \
\r
458 #define HIB3P3_MEM_BGAP_PARAMETERS1_reserved_S 29
\r
459 #define HIB3P3_MEM_BGAP_PARAMETERS1_mem_bgap_act_iref_itrim_M \
\r
462 #define HIB3P3_MEM_BGAP_PARAMETERS1_mem_bgap_act_iref_itrim_S 24
\r
463 #define HIB3P3_MEM_BGAP_PARAMETERS1_mem_bgap_en_act_iref \
\r
466 #define HIB3P3_MEM_BGAP_PARAMETERS1_mem_bgap_en_v2i \
\r
469 #define HIB3P3_MEM_BGAP_PARAMETERS1_mem_bgap_en_cap_sw \
\r
472 #define HIB3P3_MEM_BGAP_PARAMETERS1_mem_bgap_en \
\r
475 //******************************************************************************
\r
477 // The following are defines for the bit fields in the
\r
478 // HIB3P3_O_MEM_HIB_DETECTION_STATUS register.
\r
480 //******************************************************************************
\r
481 #define HIB3P3_MEM_HIB_DETECTION_STATUS_reserved_M \
\r
484 #define HIB3P3_MEM_HIB_DETECTION_STATUS_reserved_S 7
\r
485 #define HIB3P3_MEM_HIB_DETECTION_STATUS_hib_forced_ana_status \
\r
486 0x00000040 // 1 - 1.8 V supply forced mode.
\r
488 #define HIB3P3_MEM_HIB_DETECTION_STATUS_hib_forced_flash_status \
\r
489 0x00000004 // 1 - 3.3 V supply forced mode for
\r
492 #define HIB3P3_MEM_HIB_DETECTION_STATUS_hib_ext_clk_det_out_status \
\r
493 0x00000002 // 1 - Forced clock mode
\r
495 #define HIB3P3_MEM_HIB_DETECTION_STATUS_hib_xtal_det_out_status \
\r
496 0x00000001 // 1 - XTAL clock mode
\r
498 //******************************************************************************
\r
500 // The following are defines for the bit fields in the
\r
501 // HIB3P3_O_MEM_HIB_MISC_CONTROLS register.
\r
503 //******************************************************************************
\r
504 #define HIB3P3_MEM_HIB_MISC_CONTROLS_reserved_M \
\r
507 #define HIB3P3_MEM_HIB_MISC_CONTROLS_reserved_S 11
\r
508 #define HIB3P3_MEM_HIB_MISC_CONTROLS_mem_hib_en_pok_por_comp \
\r
511 #define HIB3P3_MEM_HIB_MISC_CONTROLS_mem_hib_en_pok_por_comp_ref \
\r
514 #define HIB3P3_MEM_HIB_MISC_CONTROLS_mem_hib_pok_por_comp_trim_M \
\r
517 #define HIB3P3_MEM_HIB_MISC_CONTROLS_mem_hib_pok_por_comp_trim_S 6
\r
518 #define HIB3P3_MEM_HIB_MISC_CONTROLS_NU1 \
\r
521 #define HIB3P3_MEM_HIB_MISC_CONTROLS_mem_hib_flash_det_en \
\r
524 #define HIB3P3_MEM_HIB_MISC_CONTROLS_mem_hib_en_tmux \
\r
527 //******************************************************************************
\r
529 // The following are defines for the bit fields in the
\r
530 // HIB3P3_O_MEM_HIB_CONFIG register.
\r
532 //******************************************************************************
\r
533 #define HIB3P3_MEM_HIB_CONFIG_TOP_MUX_CTRL_SOP_SPIO_M \
\r
536 #define HIB3P3_MEM_HIB_CONFIG_TOP_MUX_CTRL_SOP_SPIO_S 24
\r
537 #define HIB3P3_MEM_HIB_CONFIG_EN_ANA_DIG_SHARED3 \
\r
538 0x00080000 // 1 - Enable VDD_FLASH_INDP_PAD
\r
539 // for digital path (SHARED4) ; 0 -
\r
540 // Disable VDD_FLASH_INDP_PAD for
\r
541 // digital path (SHARED4) ; Before
\r
542 // programming this bit to 1, ensure
\r
543 // that the device is in FORCED 3.3
\r
544 // supply Mode, which can be
\r
545 // inferred from the register :
\r
546 // MEM_HIB_DETECTION_STATUS : 0x0040
\r
548 #define HIB3P3_MEM_HIB_CONFIG_EN_ANA_DIG_SHARED2 \
\r
549 0x00040000 // 1 - Enable the
\r
550 // VDD_FB_GPIO_MUX_PAD for digital
\r
551 // path (SHARED3) ; 0 - Disable the
\r
552 // VDD_FB_GPIO_MUX_PAD for digital
\r
553 // path (SHARED3) ; This pin can be
\r
554 // used only in modes other than
\r
557 #define HIB3P3_MEM_HIB_CONFIG_EN_ANA_DIG_SHARED1 \
\r
558 0x00020000 // 1 - Enable the PM_TEST_PAD for
\r
559 // digital GPIO path (SHARED2) ; 0 -
\r
560 // Disable the PM_TEST_PAD for
\r
561 // digital GPIO path (SHARED2) This
\r
562 // pin can be used for digital only
\r
563 // in modes other then SOP-111
\r
565 #define HIB3P3_MEM_HIB_CONFIG_EN_ANA_DIG_SHARED0 \
\r
566 0x00010000 // 1 - Enable the XTAL_N pin
\r
567 // digital GPIO path (SHARED1); 0 -
\r
568 // Disable the XTAL_N pin digital
\r
569 // GPIO path (SHARED1). Before
\r
570 // programming this bit to 1, ensure
\r
571 // that the device is in FORCED CLK
\r
572 // Mode, which can inferred from the
\r
574 // MEM_HIB_DETECTION_STATUS :
\r
577 #define HIB3P3_MEM_HIB_CONFIG_mem_hib_xtal_enable \
\r
578 0x00000100 // 1 - Enable the XTAL Clock ; 0 -
\r
579 // Donot enable the XTAL Clock. This
\r
580 // bit has to be programmed to 1 (by
\r
581 // APPS Devinit F/w), during exit
\r
582 // from OFF or Hib_wo_clks modes,
\r
583 // after checking if the slow_clk
\r
584 // mode is XTAL_CLK mode. Once
\r
585 // enabled the XTAL will be disabled
\r
586 // only after entering HIB_WO_CLKS
\r
587 // mode. This register will be reset
\r
588 // during Hibernate -WO-Clks mode
\r
589 // (but not during Hibernate-W-Clks
\r
592 //******************************************************************************
\r
594 // The following are defines for the bit fields in the
\r
595 // HIB3P3_O_MEM_HIB_RTC_IRQ_ENABLE register.
\r
597 //******************************************************************************
\r
598 #define HIB3P3_MEM_HIB_RTC_IRQ_ENABLE_HIB_RTC_IRQ_ENABLE \
\r
599 0x00000001 // 1 - Enable the HIB RTC - IRQ ; 0
\r
600 // - Disable the HIB RTC - IRQ
\r
602 //******************************************************************************
\r
604 // The following are defines for the bit fields in the
\r
605 // HIB3P3_O_MEM_HIB_RTC_IRQ_LSW_CONF register.
\r
607 //******************************************************************************
\r
608 #define HIB3P3_MEM_HIB_RTC_IRQ_LSW_CONF_HIB_RTC_IRQ_LSW_CONF_M \
\r
609 0xFFFFFFFF // Configuration for LSW of the
\r
610 // RTC-Timestamp at which interrupt
\r
611 // need to be generated
\r
613 #define HIB3P3_MEM_HIB_RTC_IRQ_LSW_CONF_HIB_RTC_IRQ_LSW_CONF_S 0
\r
614 //******************************************************************************
\r
616 // The following are defines for the bit fields in the
\r
617 // HIB3P3_O_MEM_HIB_RTC_IRQ_MSW_CONF register.
\r
619 //******************************************************************************
\r
620 #define HIB3P3_MEM_HIB_RTC_IRQ_MSW_CONF_HIB_RTC_IRQ_MSW_CONF_M \
\r
621 0x0000FFFF // Configuration for MSW of thr
\r
622 // RTC-Timestamp at which the
\r
623 // interrupt need to be generated
\r
625 #define HIB3P3_MEM_HIB_RTC_IRQ_MSW_CONF_HIB_RTC_IRQ_MSW_CONF_S 0
\r
626 //******************************************************************************
\r
628 // The following are defines for the bit fields in the
\r
629 // HIB3P3_O_MEM_HIB_UART_CONF register.
\r
631 //******************************************************************************
\r
632 #define HIB3P3_MEM_HIB_UART_CONF_reserved_M \
\r
635 #define HIB3P3_MEM_HIB_UART_CONF_reserved_S 1
\r
636 #define HIB3P3_MEM_HIB_UART_CONF_mem_hib_uart_wake_en \
\r
637 0x00000001 // 1 - Enable the UART-Autonomous
\r
638 // mode wakeup during Hibernate mode
\r
639 // ; This is an auto-clear bit, once
\r
640 // programmed to 1, it will latched
\r
641 // into an internal register which
\r
642 // remain asserted until the
\r
643 // Hib-wakeup is initiated.
\r
645 //******************************************************************************
\r
647 // The following are defines for the bit fields in the
\r
648 // HIB3P3_O_MEM_GPIO_WAKE_EN register.
\r
650 //******************************************************************************
\r
651 #define HIB3P3_MEM_GPIO_WAKE_EN_reserved_M \
\r
654 #define HIB3P3_MEM_GPIO_WAKE_EN_reserved_S 8
\r
655 #define HIB3P3_MEM_GPIO_WAKE_EN_mem_gpio_wake_en_M \
\r
656 0x000000FF // 1 - Enable the GPIO-Autonomous
\r
657 // mode wakeup during Hibernate mode
\r
658 // ; This is an auto-clear bit, once
\r
659 // programmed to 1, it will latched
\r
660 // into an internal register which
\r
661 // remain asserted until the
\r
662 // Hib-wakeup is initiated.
\r
664 #define HIB3P3_MEM_GPIO_WAKE_EN_mem_gpio_wake_en_S 0
\r
665 //******************************************************************************
\r
667 // The following are defines for the bit fields in the
\r
668 // HIB3P3_O_MEM_GPIO_WAKE_CONF register.
\r
670 //******************************************************************************
\r
671 #define HIB3P3_MEM_GPIO_WAKE_CONF_reserved_M \
\r
674 #define HIB3P3_MEM_GPIO_WAKE_CONF_reserved_S 16
\r
675 #define HIB3P3_MEM_GPIO_WAKE_CONF_mem_gpio_wake_conf_M \
\r
676 0x0000FFFF // Configuration to say whether the
\r
677 // GPIO wakeup has to happen on
\r
678 // Level0 or falling-edge for the
\r
679 // given group. â
\80\9c00â
\80? â
\80\93 Level0 â
\80\9c01â
\80? â
\80\93\r
680 // Level1 â
\80\9c10â
\80?- Fall-edge â
\80\9c11â
\80?-
\r
681 // Rise-edge [1:0] – Conf for GPIO0
\r
682 // [3:2] – Conf for GPIO1 [5:4] –
\r
683 // Conf for GPIO2 [7:6] – Conf for
\r
684 // GPIO3 [9:8] – Conf for GPIO4
\r
685 // [11:10] – Conf for GPIO5 [13:12]
\r
686 // – Conf for GPIO6
\r
688 #define HIB3P3_MEM_GPIO_WAKE_CONF_mem_gpio_wake_conf_S 0
\r
689 //******************************************************************************
\r
691 // The following are defines for the bit fields in the
\r
692 // HIB3P3_O_MEM_PAD_OEN_RET33_CONF register.
\r
694 //******************************************************************************
\r
695 #define HIB3P3_MEM_PAD_OEN_RET33_CONF_mem_pad_oen_ret33_override_ctrl \
\r
696 0x00000004 // 1 - Override the OEN33 and RET33
\r
697 // controls of GPIOs during
\r
698 // SOP-Bootdebug mode ; 0 - Donot
\r
699 // override the OEN33 and RET33
\r
700 // controls of GPIOs during
\r
701 // SOP-Bootdebug mode
\r
703 #define HIB3P3_MEM_PAD_OEN_RET33_CONF_PAD_OEN33_CONF \
\r
706 #define HIB3P3_MEM_PAD_OEN_RET33_CONF_PAD_RET33_CONF \
\r
709 //******************************************************************************
\r
711 // The following are defines for the bit fields in the
\r
712 // HIB3P3_O_MEM_UART_RTS_OEN_RET33_CONF register.
\r
714 //******************************************************************************
\r
715 #define HIB3P3_MEM_UART_RTS_OEN_RET33_CONF_mem_uart_nrts_oen_ret33_override_ctrl \
\r
716 0x00000004 // 1 - Override the OEN33 and RET33
\r
717 // controls of UART NRTS GPIO during
\r
718 // SOP-Bootdebug mode ; 0 - Donot
\r
719 // override the OEN33 and RET33
\r
720 // controls of UART NRTS GPIO during
\r
721 // SOP-Bootdebug mode
\r
723 #define HIB3P3_MEM_UART_RTS_OEN_RET33_CONF_PAD_UART_RTS_OEN33_CONF \
\r
726 #define HIB3P3_MEM_UART_RTS_OEN_RET33_CONF_PAD_UART_RTS_RET33_CONF \
\r
729 //******************************************************************************
\r
731 // The following are defines for the bit fields in the
\r
732 // HIB3P3_O_MEM_JTAG_CONF register.
\r
734 //******************************************************************************
\r
735 #define HIB3P3_MEM_JTAG_CONF_mem_jtag1_oen_ret33_override_ctrl \
\r
738 #define HIB3P3_MEM_JTAG_CONF_mem_jtag0_oen_ret33_override_ctrl \
\r
741 #define HIB3P3_MEM_JTAG_CONF_PAD_JTAG1_RTS_OEN33_CONF \
\r
744 #define HIB3P3_MEM_JTAG_CONF_PAD_JTAG1_RTS_RET33_CONF \
\r
747 #define HIB3P3_MEM_JTAG_CONF_PAD_JTAG0_RTS_OEN33_CONF \
\r
750 #define HIB3P3_MEM_JTAG_CONF_PAD_JTAG0_RTS_RET33_CONF \
\r
753 //******************************************************************************
\r
755 // The following are defines for the bit fields in the
\r
756 // HIB3P3_O_MEM_HIB_REG0 register.
\r
758 //******************************************************************************
\r
759 #define HIB3P3_MEM_HIB_REG0_mem_hib_reg0_M \
\r
762 #define HIB3P3_MEM_HIB_REG0_mem_hib_reg0_S 0
\r
763 //******************************************************************************
\r
765 // The following are defines for the bit fields in the
\r
766 // HIB3P3_O_MEM_HIB_REG1 register.
\r
768 //******************************************************************************
\r
769 #define HIB3P3_MEM_HIB_REG1_mem_hib_reg1_M \
\r
772 #define HIB3P3_MEM_HIB_REG1_mem_hib_reg1_S 0
\r
773 //******************************************************************************
\r
775 // The following are defines for the bit fields in the
\r
776 // HIB3P3_O_MEM_HIB_REG2 register.
\r
778 //******************************************************************************
\r
779 #define HIB3P3_MEM_HIB_REG2_mem_hib_reg2_M \
\r
782 #define HIB3P3_MEM_HIB_REG2_mem_hib_reg2_S 0
\r
783 //******************************************************************************
\r
785 // The following are defines for the bit fields in the
\r
786 // HIB3P3_O_MEM_HIB_REG3 register.
\r
788 //******************************************************************************
\r
789 #define HIB3P3_MEM_HIB_REG3_mem_hib_reg3_M \
\r
792 #define HIB3P3_MEM_HIB_REG3_mem_hib_reg3_S 0
\r
793 //******************************************************************************
\r
795 // The following are defines for the bit fields in the
\r
796 // HIB3P3_O_MEM_HIB_SEQUENCER_CFG0 register.
\r
798 //******************************************************************************
\r
799 #define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_bdc_ev0_to_ev1_time_M \
\r
800 0xFFFF0000 // Configuration for the number of
\r
801 // slow-clks between de-assertion of
\r
802 // EN_BG_3P3V to assertion of
\r
805 #define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_bdc_ev0_to_ev1_time_S 16
\r
806 #define HIB3P3_MEM_HIB_SEQUENCER_CFG0_NU1 \
\r
809 #define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_bdc_ev3_to_ev4_time_M \
\r
810 0x00006000 // Configuration for the number of
\r
811 // slow-clks between assertion of
\r
812 // EN_COMP_3P3V and assertion of
\r
813 // EN_COMP_LATCH_3P3V
\r
815 #define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_bdc_ev3_to_ev4_time_S 13
\r
816 #define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_bdc_ev2_to_ev3_time_M \
\r
817 0x00001800 // Configuration for the number of
\r
818 // slow-clks between assertion of
\r
819 // (EN_CAP_SW_3P3V,EN_COMP_REF) and
\r
820 // assertion of (EN_COMP_3P3V)
\r
822 #define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_bdc_ev2_to_ev3_time_S 11
\r
823 #define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_bdc_ev1_to_ev2_time_M \
\r
824 0x00000600 // Configuration for the number of
\r
825 // slow-clks between assertion of
\r
826 // (EN_BG_3P3V) and assertion of
\r
827 // (EN_CAP_SW_3P3V,
\r
828 // EN_COMP_REF_3P3V)
\r
830 #define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_bdc_ev1_to_ev2_time_S 9
\r
831 #define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_en_crude_ref_comp \
\r
834 #define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_en_vbok4bg_ref_override_ctrl \
\r
835 0x00000080 // 1 - EN_VBOK4BG_REF comes from
\r
836 // bit[10] of the register
\r
837 // MEM_BGAP_PARAMETERS0 [0x0038]. 0
\r
838 // - EN_VBOK4BG_REF comes directly
\r
839 // from the Hib-Sequencer.
\r
841 #define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_en_vbok4bg_comp_override_ctrl \
\r
842 0x00000040 // 1 - EN_VBOK4BG comes from
\r
843 // bit[11] of the register
\r
844 // MEM_BGAP_PARAMETERS0 [0x0038]. 0
\r
845 // - EN_VBOK4BG comes directly from
\r
846 // the Hib-Sequencer.
\r
848 #define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_en_v2i_override_ctrl \
\r
849 0x00000020 // 1 - EN_V2I comes from bit[2] of
\r
850 // the register MEM_BGAP_PARAMETERS1
\r
851 // [0x003C]. 0 - EN_V2I comes
\r
852 // directly from the Hib-Sequencer.
\r
854 #define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_por_comp_ref_override_ctrl \
\r
855 0x00000010 // 1 - EN_POR_COMP_REF comes from
\r
856 // bit[9] of the register
\r
857 // MEM_HIB_MISC_CONTROLS [0x0044]. 0
\r
858 // - EN_POR_COMP_REF comes directly
\r
859 // from the Hib-Sequencer.
\r
861 #define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_en_por_comp_override_ctrl \
\r
862 0x00000008 // 1 - EN_POR_COMP comes from
\r
863 // bit[10] of the register
\r
864 // MEM_HIB_MISC_CONTROLS [0x044]. 0
\r
865 // - EN_POR_COMP comes directly from
\r
866 // the Hib-Sequencer.
\r
868 #define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_cap_sw_override_ctrl \
\r
869 0x00000004 // 1 - EN_CAP_SW comes from bit[1]
\r
871 // MEM_BGAP_PARAMETERS1 [0x003C]. 0
\r
872 // - EN_CAP_SW comes directly from
\r
875 #define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_bg_override_ctrl \
\r
876 0x00000002 // 1 - EN_BGAP comes from bit[0] of
\r
877 // the register MEM_BGAP_PARAMETERS1
\r
878 // [0x003C]. 0 - EN_BGAP comes
\r
879 // directly from Hib-Sequencer.
\r
881 #define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_act_iref_override_ctrl \
\r
884 //******************************************************************************
\r
886 // The following are defines for the bit fields in the
\r
887 // HIB3P3_O_MEM_HIB_SEQUENCER_CFG1 register.
\r
889 //******************************************************************************
\r
890 #define HIB3P3_MEM_HIB_SEQUENCER_CFG1_reserved_M \
\r
893 #define HIB3P3_MEM_HIB_SEQUENCER_CFG1_reserved_S 16
\r
894 #define HIB3P3_MEM_HIB_SEQUENCER_CFG1_mem_bdc_ev5_to_ev6_time_M \
\r
895 0x0000C000 // Configuration for number of
\r
896 // slow-clks between de-assertion of
\r
897 // EN_COMP_LATCH and assertion of
\r
899 #define HIB3P3_MEM_HIB_SEQUENCER_CFG1_mem_bdc_ev5_to_ev6_time_S 14
\r
900 #define HIB3P3_MEM_HIB_SEQUENCER_CFG1_mem_bdc_to_active_ev1_to_ev2_time_M \
\r
901 0x00003000 // Configuration for number of
\r
902 // slow-clks between assertion of
\r
903 // EN_COMP_REF to assertion of
\r
904 // EN_COMP during HIB-Exit
\r
906 #define HIB3P3_MEM_HIB_SEQUENCER_CFG1_mem_bdc_to_active_ev1_to_ev2_time_S 12
\r
907 #define HIB3P3_MEM_HIB_SEQUENCER_CFG1_mem_bdc_to_active_ev0_to_ev1_time_M \
\r
910 #define HIB3P3_MEM_HIB_SEQUENCER_CFG1_mem_bdc_to_active_ev0_to_ev1_time_S 10
\r
911 #define HIB3P3_MEM_HIB_SEQUENCER_CFG1_mem_bdc_to_active_ev0_to_active_M \
\r
912 0x00000300 // Configuration in number of
\r
913 // slow-clks between assertion of
\r
914 // (EN_BGAP_3P3V, EN_CAP_SW_3P3V,
\r
915 // EN_ACT_IREF_3P3V, EN_COMP_REF) to
\r
916 // assertion of EN_COMP_3P3V
\r
918 #define HIB3P3_MEM_HIB_SEQUENCER_CFG1_mem_bdc_to_active_ev0_to_active_S 8
\r
919 #define HIB3P3_MEM_HIB_SEQUENCER_CFG1_mem_active_to_bdc_ev1_to_bdc_ev0_time_M \
\r
920 0x000000C0 // Configuration in number of
\r
921 // slow-clks between de-assertion of
\r
922 // (EN_COMP_3P3V, EN_COMP_REF_3P3V,
\r
923 // EN_ACT_IREF_3P3V, EN_CAP_SW_3P3V)
\r
924 // to deassertion of EN_BGAP_3P3V.
\r
926 #define HIB3P3_MEM_HIB_SEQUENCER_CFG1_mem_active_to_bdc_ev1_to_bdc_ev0_time_S 6
\r
927 #define HIB3P3_MEM_HIB_SEQUENCER_CFG1_NU1_M \
\r
930 #define HIB3P3_MEM_HIB_SEQUENCER_CFG1_NU1_S 0
\r
931 //******************************************************************************
\r
933 // The following are defines for the bit fields in the
\r
934 // HIB3P3_O_MEM_HIB_MISC_CONFIG register.
\r
936 //******************************************************************************
\r
937 #define HIB3P3_MEM_HIB_MISC_CONFIG_mem_en_pll_untrim_current \
\r
940 //******************************************************************************
\r
942 // The following are defines for the bit fields in the
\r
943 // HIB3P3_O_MEM_HIB_WAKE_STATUS register.
\r
945 //******************************************************************************
\r
946 #define HIB3P3_MEM_HIB_WAKE_STATUS_hib_wake_src_M \
\r
947 0x0000001E // "0100" - GPIO ; "0010" - RTC ;
\r
948 // "0001" - UART Others - Reserved
\r
950 #define HIB3P3_MEM_HIB_WAKE_STATUS_hib_wake_src_S 1
\r
951 #define HIB3P3_MEM_HIB_WAKE_STATUS_hib_wake_status \
\r
952 0x00000001 // 1 - Wake from Hibernate ; 0 -
\r
955 //******************************************************************************
\r
957 // The following are defines for the bit fields in the
\r
958 // HIB3P3_O_MEM_HIB_LPDS_GPIO_SEL register.
\r
960 //******************************************************************************
\r
961 #define HIB3P3_MEM_HIB_LPDS_GPIO_SEL_HIB_LPDS_GPIO_SEL_M \
\r
964 #define HIB3P3_MEM_HIB_LPDS_GPIO_SEL_HIB_LPDS_GPIO_SEL_S 0
\r
965 //******************************************************************************
\r
967 // The following are defines for the bit fields in the
\r
968 // HIB3P3_O_MEM_HIB_SEQUENCER_CFG2 register.
\r
970 //******************************************************************************
\r
971 #define HIB3P3_MEM_HIB_SEQUENCER_CFG2_reserved_M \
\r
974 #define HIB3P3_MEM_HIB_SEQUENCER_CFG2_reserved_S 11
\r
975 #define HIB3P3_MEM_HIB_SEQUENCER_CFG2_mem_active_to_bdc_ev0_to_active_to_bdc_ev1_time_M \
\r
976 0x00000600 // Deassertion of EN_COMP_LATCH_3P3
\r
977 // to deassertion of (EN_COMP_3P3,
\r
978 // EN_COMP_REF_3P3, EN_ACT_IREF_3P3,
\r
981 #define HIB3P3_MEM_HIB_SEQUENCER_CFG2_mem_active_to_bdc_ev0_to_active_to_bdc_ev1_time_S 9
\r
982 #define HIB3P3_MEM_HIB_SEQUENCER_CFG2_mem_bdc_ev4_to_ev5_time_M \
\r
983 0x000001C0 // Assertion of EN_COMP_LATCH_3P3
\r
984 // to deassertion of
\r
985 // EN_COMP_LATCH_3P3
\r
987 #define HIB3P3_MEM_HIB_SEQUENCER_CFG2_mem_bdc_ev4_to_ev5_time_S 6
\r
988 #define HIB3P3_MEM_HIB_SEQUENCER_CFG2_mem_bdc_ev6_to_ev7_time_M \
\r
989 0x00000030 // Deassertion of (EN_CAP_SW_3P3,
\r
990 // EN_COMP_REF_3P3, EN_COMP_3P3,
\r
991 // EN_COMP_OUT_LATCH_3P3) to
\r
992 // deassertion of EN_BGAP_3P3
\r
994 #define HIB3P3_MEM_HIB_SEQUENCER_CFG2_mem_bdc_ev6_to_ev7_time_S 4
\r
995 #define HIB3P3_MEM_HIB_SEQUENCER_CFG2_mem_bdc_to_active_ev1_to_ev2_time_M \
\r
996 0x0000000C // Assertion of EN_COMP_3P3 to
\r
997 // assertion of EN_COMPOUT_LATCH_3P3
\r
999 #define HIB3P3_MEM_HIB_SEQUENCER_CFG2_mem_bdc_to_active_ev1_to_ev2_time_S 2
\r
1000 #define HIB3P3_MEM_HIB_SEQUENCER_CFG2_mem_hib_to_active_ev2_to_ev3_time_M \
\r
1001 0x00000003 // Assertion of EN_COMP_3P3 to
\r
1002 // assertion of EN_COMPOUT_LATCH_3P3
\r
1004 #define HIB3P3_MEM_HIB_SEQUENCER_CFG2_mem_hib_to_active_ev2_to_ev3_time_S 0
\r
1005 //******************************************************************************
\r
1007 // The following are defines for the bit fields in the
\r
1008 // HIB3P3_O_HIBANA_SPARE_LOWV register.
\r
1010 //******************************************************************************
\r
1011 #define HIB3P3_HIBANA_SPARE_LOWV_mem_hibana_spare1_M \
\r
1014 #define HIB3P3_HIBANA_SPARE_LOWV_mem_hibana_spare1_S 22
\r
1015 #define HIB3P3_HIBANA_SPARE_LOWV_mem_hibana_spare0_M \
\r
1018 #define HIB3P3_HIBANA_SPARE_LOWV_mem_hibana_spare0_S 0
\r
1019 //******************************************************************************
\r
1021 // The following are defines for the bit fields in the
\r
1022 // HIB3P3_O_HIB_TMUX_CTRL register.
\r
1024 //******************************************************************************
\r
1025 #define HIB3P3_HIB_TMUX_CTRL_reserved_M \
\r
1028 #define HIB3P3_HIB_TMUX_CTRL_reserved_S 10
\r
1029 #define HIB3P3_HIB_TMUX_CTRL_mem_hd_tmux_cntrl_M \
\r
1032 #define HIB3P3_HIB_TMUX_CTRL_mem_hd_tmux_cntrl_S 0
\r
1033 //******************************************************************************
\r
1035 // The following are defines for the bit fields in the
\r
1036 // HIB3P3_O_HIB_1P2_1P8_LDO_TRIM register.
\r
1038 //******************************************************************************
\r
1039 #define HIB3P3_HIB_1P2_1P8_LDO_TRIM_reserved_M \
\r
1042 #define HIB3P3_HIB_1P2_1P8_LDO_TRIM_reserved_S 12
\r
1043 #define HIB3P3_HIB_1P2_1P8_LDO_TRIM_mem_hd_1p2_ldo_en_override_ctrl \
\r
1046 #define HIB3P3_HIB_1P2_1P8_LDO_TRIM_mem_hd_1p8_ldo_en_override_ctrl \
\r
1049 #define HIB3P3_HIB_1P2_1P8_LDO_TRIM_mem_hd_1p2_ldo_en_override \
\r
1052 #define HIB3P3_HIB_1P2_1P8_LDO_TRIM_mem_hd_1p8_ldo_en_override \
\r
1055 #define HIB3P3_HIB_1P2_1P8_LDO_TRIM_mem_hd_1p2_ldo_vtrim_M \
\r
1058 #define HIB3P3_HIB_1P2_1P8_LDO_TRIM_mem_hd_1p2_ldo_vtrim_S 4
\r
1059 #define HIB3P3_HIB_1P2_1P8_LDO_TRIM_mem_hd_1p8_ldo_vtrim_M \
\r
1062 #define HIB3P3_HIB_1P2_1P8_LDO_TRIM_mem_hd_1p8_ldo_vtrim_S 0
\r
1063 //******************************************************************************
\r
1065 // The following are defines for the bit fields in the
\r
1066 // HIB3P3_O_HIB_COMP_TRIM register.
\r
1068 //******************************************************************************
\r
1069 #define HIB3P3_HIB_COMP_TRIM_reserved_M \
\r
1072 #define HIB3P3_HIB_COMP_TRIM_reserved_S 3
\r
1073 #define HIB3P3_HIB_COMP_TRIM_mem_hd_comp_trim_M \
\r
1076 #define HIB3P3_HIB_COMP_TRIM_mem_hd_comp_trim_S 0
\r
1077 //******************************************************************************
\r
1079 // The following are defines for the bit fields in the
\r
1080 // HIB3P3_O_HIB_EN_TS register.
\r
1082 //******************************************************************************
\r
1083 #define HIB3P3_HIB_EN_TS_reserved_M \
\r
1086 #define HIB3P3_HIB_EN_TS_reserved_S 1
\r
1087 #define HIB3P3_HIB_EN_TS_mem_hd_en_ts \
\r
1090 //******************************************************************************
\r
1092 // The following are defines for the bit fields in the
\r
1093 // HIB3P3_O_HIB_1P8V_DET_EN register.
\r
1095 //******************************************************************************
\r
1096 #define HIB3P3_HIB_1P8V_DET_EN_reserved_M \
\r
1099 #define HIB3P3_HIB_1P8V_DET_EN_reserved_S 1
\r
1100 #define HIB3P3_HIB_1P8V_DET_EN_mem_hib_1p8v_det_en \
\r
1103 //******************************************************************************
\r
1105 // The following are defines for the bit fields in the
\r
1106 // HIB3P3_O_HIB_VBAT_MON_EN register.
\r
1108 //******************************************************************************
\r
1109 #define HIB3P3_HIB_VBAT_MON_EN_reserved_M \
\r
1112 #define HIB3P3_HIB_VBAT_MON_EN_reserved_S 2
\r
1113 #define HIB3P3_HIB_VBAT_MON_EN_mem_hib_vbat_mon_del_en \
\r
1116 #define HIB3P3_HIB_VBAT_MON_EN_mem_hib_vbat_mon_en \
\r
1119 //******************************************************************************
\r
1121 // The following are defines for the bit fields in the
\r
1122 // HIB3P3_O_HIB_NHIB_ENABLE register.
\r
1124 //******************************************************************************
\r
1125 #define HIB3P3_HIB_NHIB_ENABLE_mem_hib_nhib_enable \
\r
1128 //******************************************************************************
\r
1130 // The following are defines for the bit fields in the
\r
1131 // HIB3P3_O_HIB_UART_RTS_SW_ENABLE register.
\r
1133 //******************************************************************************
\r
1134 #define HIB3P3_HIB_UART_RTS_SW_ENABLE_mem_hib_uart_rts_sw_enable \
\r
1140 #endif // __HW_HIB3P3_H__
\r
projects / freertos / blob