2 * -------------------------------------------
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3 * CC3220 SDK - v0.10.00.00
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4 * -------------------------------------------
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6 * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/
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8 * Redistribution and use in source and binary forms, with or without
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9 * modification, are permitted provided that the following conditions
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12 * Redistributions of source code must retain the above copyright
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13 * notice, this list of conditions and the following disclaimer.
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15 * Redistributions in binary form must reproduce the above copyright
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16 * notice, this list of conditions and the following disclaimer in the
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17 * documentation and/or other materials provided with the
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20 * Neither the name of Texas Instruments Incorporated nor the names of
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21 * its contributors may be used to endorse or promote products derived
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22 * from this software without specific prior written permission.
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24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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25 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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26 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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27 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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28 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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29 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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30 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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31 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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32 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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33 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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34 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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38 #ifndef __HW_MMCHS_H__
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39 #define __HW_MMCHS_H__
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41 //*****************************************************************************
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43 // The following are defines for the MMCHS register offsets.
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45 //*****************************************************************************
\r
46 #define MMCHS_O_HL_REV 0x00000000 // IP Revision Identifier (X.Y.R)
\r
47 // Used by software to track
\r
48 // features bugs and compatibility
\r
49 #define MMCHS_O_HL_HWINFO 0x00000004 // Information about the IP
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50 // module's hardware configuration
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51 // i.e. typically the module's HDL
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52 // generics (if any). Actual field
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53 // format and encoding is up to the
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54 // module's designer to decide.
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55 #define MMCHS_O_HL_SYSCONFIG 0x00000010 // Clock management configuration
\r
56 #define MMCHS_O_SYSCONFIG 0x00000110 // System Configuration Register
\r
57 // This register allows controlling
\r
58 // various parameters of the OCP
\r
60 #define MMCHS_O_SYSSTATUS 0x00000114 // System Status Register This
\r
61 // register provides status
\r
62 // information about the module
\r
63 // excluding the interrupt status
\r
65 #define MMCHS_O_CSRE 0x00000124 // Card status response error This
\r
66 // register enables the host
\r
67 // controller to detect card status
\r
68 // errors of response type R1 R1b
\r
69 // for all cards and of R5 R5b and
\r
70 // R6 response for cards types SD or
\r
71 // SDIO. When a bit MMCHS_CSRE[i] is
\r
72 // set to 1 if the corresponding bit
\r
73 // at the same position in the
\r
74 // response MMCHS_RSP0[i] is set to
\r
75 // 1 the host controller indicates a
\r
76 // card error (MMCHS_STAT[CERR])
\r
77 // interrupt status to avoid the
\r
78 // host driver reading the response
\r
79 // register (MMCHS_RSP0). Note: No
\r
80 // automatic card error detection
\r
81 // for autoCMD12 is implemented; the
\r
82 // host system has to check
\r
83 // autoCMD12 response register
\r
84 // (MMCHS_RESP76) for possible card
\r
86 #define MMCHS_O_SYSTEST 0x00000128 // System Test register This
\r
87 // register is used to control the
\r
88 // signals that connect to I/O pins
\r
89 // when the module is configured in
\r
90 // system test (SYSTEST) mode for
\r
91 // boundary connectivity
\r
92 // verification. Note: In SYSTEST
\r
93 // mode a write into MMCHS_CMD
\r
94 // register will not start a
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95 // transfer. The buffer behaves as a
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96 // stack accessible only by the
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97 // local host (push and pop
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98 // operations). In this mode the
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99 // Transfer Block Size
\r
100 // (MMCHS_BLK[BLEN]) and the Blocks
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101 // count for current transfer
\r
102 // (MMCHS_BLK[NBLK]) are needed to
\r
103 // generate a Buffer write ready
\r
104 // interrupt (MMCHS_STAT[BWR]) or a
\r
105 // Buffer read ready interrupt
\r
106 // (MMCHS_STAT[BRR]) and DMA
\r
107 // requests if enabled.
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108 #define MMCHS_O_CON 0x0000012C // Configuration register This
\r
109 // register is used: - to select the
\r
110 // functional mode or the SYSTEST
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111 // mode for any card. - to send an
\r
112 // initialization sequence to any
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113 // card. - to enable the detection
\r
114 // on DAT[1] of a card interrupt for
\r
115 // SDIO cards only. and also to
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116 // configure : - specific data and
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117 // command transfers for MMC cards
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118 // only. - the parameters related to
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119 // the card detect and write protect
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121 #define MMCHS_O_PWCNT 0x00000130 // Power counter register This
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122 // register is used to program a mmc
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123 // counter to delay command
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124 // transfers after activating the
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125 // PAD power this value depends on
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126 // PAD characteristics and voltage.
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127 #define MMCHS_O_BLK 0x00000204 // Transfer Length Configuration
\r
128 // register MMCHS_BLK[BLEN] is the
\r
129 // block size register.
\r
130 // MMCHS_BLK[NBLK] is the block
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131 // count register. This register
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132 // shall be used for any card.
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133 #define MMCHS_O_ARG 0x00000208 // Command argument Register This
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134 // register contains command
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135 // argument specified as bit 39-8 of
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136 // Command-Format These registers
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137 // must be initialized prior to
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138 // sending the command itself to the
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139 // card (write action into the
\r
140 // register MMCHS_CMD register).
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141 // Only exception is for a command
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142 // index specifying stuff bits in
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143 // arguments making a write
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145 #define MMCHS_O_CMD 0x0000020C // Command and transfer mode
\r
146 // register MMCHS_CMD[31:16] = the
\r
147 // command register MMCHS_CMD[15:0]
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148 // = the transfer mode. This
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149 // register configures the data and
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150 // command transfers. A write into
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151 // the most significant byte send
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152 // the command. A write into
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153 // MMCHS_CMD[15:0] registers during
\r
154 // data transfer has no effect. This
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155 // register shall be used for any
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156 // card. Note: In SYSTEST mode a
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157 // write into MMCHS_CMD register
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158 // will not start a transfer.
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159 #define MMCHS_O_RSP10 0x00000210 // Command response[31:0] Register
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160 // This 32-bit register holds bits
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161 // positions [31:0] of command
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163 // R1/R1b/R2/R3/R4/R5/R5b/R6
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164 #define MMCHS_O_RSP32 0x00000214 // Command response[63:32] Register
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165 // This 32-bit register holds bits
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166 // positions [63:32] of command
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167 // response type R2
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168 #define MMCHS_O_RSP54 0x00000218 // Command response[95:64] Register
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169 // This 32-bit register holds bits
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170 // positions [95:64] of command
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171 // response type R2
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172 #define MMCHS_O_RSP76 0x0000021C // Command response[127:96]
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173 // Register This 32-bit register
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174 // holds bits positions [127:96] of
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175 // command response type R2
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176 #define MMCHS_O_DATA 0x00000220 // Data Register This register is
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177 // the 32-bit entry point of the
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178 // buffer for read or write data
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179 // transfers. The buffer size is
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180 // 32bits x256(1024 bytes). Bytes
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181 // within a word are stored and read
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182 // in little endian format. This
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183 // buffer can be used as two 512
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184 // byte buffers to transfer data
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185 // efficiently without reducing the
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186 // throughput. Sequential and
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187 // contiguous access is necessary to
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188 // increment the pointer correctly.
\r
189 // Random or skipped access is not
\r
190 // allowed. In little endian if the
\r
191 // local host accesses this register
\r
192 // byte-wise or 16bit-wise the least
\r
193 // significant byte (bits [7:0])
\r
194 // must always be written/read
\r
195 // first. The update of the buffer
\r
196 // address is done on the most
\r
197 // significant byte write for full
\r
198 // 32-bit DATA register or on the
\r
199 // most significant byte of the last
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200 // word of block transfer. Example
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201 // 1: Byte or 16-bit access
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202 // Mbyteen[3:0]=0001 (1-byte) =>
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203 // Mbyteen[3:0]=0010 (1-byte) =>
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204 // Mbyteen[3:0]=1100 (2-bytes) OK
\r
205 // Mbyteen[3:0]=0001 (1-byte) =>
\r
206 // Mbyteen[3:0]=0010 (1-byte) =>
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207 // Mbyteen[3:0]=0100 (1-byte) OK
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208 // Mbyteen[3:0]=0001 (1-byte) =>
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209 // Mbyteen[3:0]=0010 (1-byte) =>
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210 // Mbyteen[3:0]=1000 (1-byte) Bad
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211 #define MMCHS_O_PSTATE 0x00000224 // Present state register The Host
\r
212 // can get status of the Host
\r
213 // Controller from this 32-bit read
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215 #define MMCHS_O_HCTL 0x00000228 // Control register This register
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216 // defines the host controls to set
\r
217 // power wakeup and transfer
\r
218 // parameters. MMCHS_HCTL[31:24] =
\r
219 // Wakeup control MMCHS_HCTL[23:16]
\r
220 // = Block gap control
\r
221 // MMCHS_HCTL[15:8] = Power control
\r
222 // MMCHS_HCTL[7:0] = Host control
\r
223 #define MMCHS_O_SYSCTL 0x0000022C // SD system control register This
\r
224 // register defines the system
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225 // controls to set software resets
\r
226 // clock frequency management and
\r
227 // data timeout. MMCHS_SYSCTL[31:24]
\r
228 // = Software resets
\r
229 // MMCHS_SYSCTL[23:16] = Timeout
\r
230 // control MMCHS_SYSCTL[15:0] =
\r
232 #define MMCHS_O_STAT 0x00000230 // Interrupt status register The
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233 // interrupt status regroups all the
\r
234 // status of the module internal
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235 // events that can generate an
\r
236 // interrupt. MMCHS_STAT[31:16] =
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237 // Error Interrupt Status
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238 // MMCHS_STAT[15:0] = Normal
\r
239 // Interrupt Status
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240 #define MMCHS_O_IE 0x00000234 // Interrupt SD enable register
\r
241 // This register allows to
\r
242 // enable/disable the module to set
\r
243 // status bits on an event-by-event
\r
244 // basis. MMCHS_IE[31:16] = Error
\r
245 // Interrupt Status Enable
\r
246 // MMCHS_IE[15:0] = Normal Interrupt
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248 #define MMCHS_O_ISE 0x00000238 // Interrupt signal enable register
\r
249 // This register allows to
\r
250 // enable/disable the module
\r
251 // internal sources of status on an
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252 // event-by-event basis.
\r
253 // MMCHS_ISE[31:16] = Error
\r
254 // Interrupt Signal Enable
\r
255 // MMCHS_ISE[15:0] = Normal
\r
256 // Interrupt Signal Enable
\r
257 #define MMCHS_O_AC12 0x0000023C // Auto CMD12 Error Status Register
\r
258 // The host driver may determine
\r
259 // which of the errors cases related
\r
260 // to Auto CMD12 has occurred by
\r
261 // checking this MMCHS_AC12 register
\r
262 // when an Auto CMD12 Error
\r
263 // interrupt occurs. This register
\r
264 // is valid only when Auto CMD12 is
\r
265 // enabled (MMCHS_CMD[ACEN]) and
\r
266 // Auto CMD12Error (MMCHS_STAT[ACE])
\r
267 // is set to 1. Note: These bits are
\r
268 // automatically reset when starting
\r
269 // a new adtc command with data.
\r
270 #define MMCHS_O_CAPA 0x00000240 // Capabilities register This
\r
271 // register lists the capabilities
\r
272 // of the MMC/SD/SDIO host
\r
274 #define MMCHS_O_CUR_CAPA 0x00000248 // Maximum current capabilities
\r
275 // Register This register indicates
\r
276 // the maximum current capability
\r
277 // for each voltage. The value is
\r
278 // meaningful if the voltage support
\r
279 // is set in the capabilities
\r
280 // register (MMCHS_CAPA).
\r
281 // Initialization of this register
\r
282 // (via a write access to this
\r
283 // register) depends on the system
\r
284 // capabilities. The host driver
\r
285 // shall not modify this register
\r
286 // after the initilaization. This
\r
287 // register is only reinitialized by
\r
288 // a hard reset (via RESETN signal)
\r
289 #define MMCHS_O_FE 0x00000250 // Force Event Register for Error
\r
290 // Interrupt status The force Event
\r
291 // Register is not a physically
\r
292 // implemented register. Rather it
\r
293 // is an address at which the Error
\r
294 // Interrupt Status register can be
\r
295 // written. The effect of a write to
\r
296 // this address will be reflected in
\r
297 // the Error Interrupt Status
\r
298 // Register if corresponding bit of
\r
299 // the Error Interrupt Status Enable
\r
300 // Register is set.
\r
301 #define MMCHS_O_ADMAES 0x00000254 // ADMA Error Status Register When
\r
302 // ADMA Error Interrupt is occurred
\r
303 // the ADMA Error States field in
\r
304 // this register holds the ADMA
\r
305 // state and the ADMA System Address
\r
306 // Register holds the address around
\r
307 // the error descriptor. For
\r
308 // recovering the error the Host
\r
309 // Driver requires the ADMA state to
\r
310 // identify the error descriptor
\r
311 // address as follows: ST_STOP:
\r
312 // Previous location set in the ADMA
\r
313 // System Address register is the
\r
314 // error descriptor address ST_FDS:
\r
315 // Current location set in the ADMA
\r
316 // System Address register is the
\r
317 // error descriptor address ST_CADR:
\r
318 // This sate is never set because do
\r
319 // not generate ADMA error in this
\r
320 // state. ST_TFR: Previous location
\r
321 // set in the ADMA System Address
\r
322 // register is the error descriptor
\r
323 // address In case of write
\r
324 // operation the Host Driver should
\r
325 // use ACMD22 to get the number of
\r
326 // written block rather than using
\r
327 // this information since unwritten
\r
328 // data may exist in the Host
\r
329 // Controller. The Host Controller
\r
330 // generates the ADMA Error
\r
331 // Interrupt when it detects invalid
\r
332 // descriptor data (Valid=0) at the
\r
333 // ST_FDS state. In this case ADMA
\r
334 // Error State indicates that an
\r
335 // error occurs at ST_FDS state. The
\r
336 // Host Driver may find that the
\r
337 // Valid bit is not set in the error
\r
339 #define MMCHS_O_ADMASAL 0x00000258 // ADMA System address Low bits
\r
340 #define MMCHS_O_REV 0x000002FC // Versions Register This register
\r
341 // contains the hard coded RTL
\r
342 // vendor revision number the
\r
343 // version number of SD
\r
344 // specification compliancy and a
\r
345 // slot status bit. MMCHS_REV[31:16]
\r
346 // = Host controller version
\r
347 // MMCHS_REV[15:0] = Slot Interrupt
\r
352 //******************************************************************************
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354 // The following are defines for the bit fields in the MMCHS_O_HL_REV register.
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356 //******************************************************************************
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357 #define MMCHS_HL_REV_SCHEME_M 0xC0000000
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358 #define MMCHS_HL_REV_SCHEME_S 30
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359 #define MMCHS_HL_REV_FUNC_M 0x0FFF0000 // Function indicates a software
\r
360 // compatible module family. If
\r
361 // there is no level of software
\r
362 // compatibility a new Func number
\r
363 // (and hence REVISION) should be
\r
365 #define MMCHS_HL_REV_FUNC_S 16
\r
366 #define MMCHS_HL_REV_R_RTL_M 0x0000F800 // RTL Version (R) maintained by IP
\r
367 // design owner. RTL follows a
\r
368 // numbering such as X.Y.R.Z which
\r
369 // are explained in this table. R
\r
370 // changes ONLY when: (1) PDS
\r
371 // uploads occur which may have been
\r
372 // due to spec changes (2) Bug fixes
\r
373 // occur (3) Resets to '0' when X or
\r
374 // Y changes. Design team has an
\r
375 // internal 'Z' (customer invisible)
\r
376 // number which increments on every
\r
377 // drop that happens due to DV and
\r
378 // RTL updates. Z resets to 0 when R
\r
380 #define MMCHS_HL_REV_R_RTL_S 11
\r
381 #define MMCHS_HL_REV_X_MAJOR_M 0x00000700 // Major Revision (X) maintained by
\r
382 // IP specification owner. X changes
\r
383 // ONLY when: (1) There is a major
\r
384 // feature addition. An example
\r
385 // would be adding Master Mode to
\r
386 // Utopia Level2. The Func field (or
\r
387 // Class/Type in old PID format)
\r
388 // will remain the same. X does NOT
\r
389 // change due to: (1) Bug fixes (2)
\r
390 // Change in feature parameters.
\r
391 #define MMCHS_HL_REV_X_MAJOR_S 8
\r
392 #define MMCHS_HL_REV_CUSTOM_M 0x000000C0
\r
393 #define MMCHS_HL_REV_CUSTOM_S 6
\r
394 #define MMCHS_HL_REV_Y_MINOR_M 0x0000003F // Minor Revision (Y) maintained by
\r
395 // IP specification owner. Y changes
\r
396 // ONLY when: (1) Features are
\r
397 // scaled (up or down). Flexibility
\r
398 // exists in that this feature
\r
399 // scalability may either be
\r
400 // represented in the Y change or a
\r
401 // specific register in the IP that
\r
402 // indicates which features are
\r
403 // exactly available. (2) When
\r
404 // feature creeps from Is-Not list
\r
405 // to Is list. But this may not be
\r
406 // the case once it sees silicon; in
\r
407 // which case X will change. Y does
\r
408 // NOT change due to: (1) Bug fixes
\r
409 // (2) Typos or clarifications (3)
\r
410 // major functional/feature
\r
411 // change/addition/deletion. Instead
\r
412 // these changes may be reflected
\r
413 // via R S X as applicable. Spec
\r
414 // owner maintains a
\r
415 // customer-invisible number 'S'
\r
416 // which changes due to: (1)
\r
417 // Typos/clarifications (2) Bug
\r
418 // documentation. Note that this bug
\r
419 // is not due to a spec change but
\r
420 // due to implementation.
\r
421 // Nevertheless the spec tracks the
\r
422 // IP bugs. An RTL release (say for
\r
423 // silicon PG1.1) that occurs due to
\r
424 // bug fix should document the
\r
425 // corresponding spec number (X.Y.S)
\r
426 // in its release notes.
\r
427 #define MMCHS_HL_REV_Y_MINOR_S 0
\r
428 //******************************************************************************
\r
430 // The following are defines for the bit fields in the MMCHS_O_HL_HWINFO register.
\r
432 //******************************************************************************
\r
433 #define MMCHS_HL_HWINFO_RETMODE 0x00000040
\r
434 #define MMCHS_HL_HWINFO_MEM_SIZE_M \
\r
437 #define MMCHS_HL_HWINFO_MEM_SIZE_S 2
\r
438 #define MMCHS_HL_HWINFO_MERGE_MEM \
\r
441 #define MMCHS_HL_HWINFO_MADMA_EN \
\r
444 //******************************************************************************
\r
446 // The following are defines for the bit fields in the
\r
447 // MMCHS_O_HL_SYSCONFIG register.
\r
449 //******************************************************************************
\r
450 #define MMCHS_HL_SYSCONFIG_STANDBYMODE_M \
\r
451 0x00000030 // Configuration of the local
\r
452 // initiator state management mode.
\r
453 // By definition initiator may
\r
454 // generate read/write transaction
\r
455 // as long as it is out of STANDBY
\r
456 // state. 0x0 Force-standby mode:
\r
457 // local initiator is
\r
458 // unconditionally placed in standby
\r
459 // state.Backup mode for debug only.
\r
460 // 0x1 No-standby mode: local
\r
461 // initiator is unconditionally
\r
462 // placed out of standby
\r
463 // state.Backup mode for debug only.
\r
464 // 0x2 Smart-standby mode: local
\r
465 // initiator standby status depends
\r
466 // on local conditions i.e. the
\r
467 // module's functional requirement
\r
468 // from the initiator.IP module
\r
469 // shall not generate
\r
470 // (initiator-related) wakeup
\r
471 // events. 0x3 "Smart-Standby
\r
472 // wakeup-capable mode: local
\r
473 // initiator standby status depends
\r
474 // on local conditions i.e. the
\r
475 // module's functional requirement
\r
476 // from the initiator. IP module may
\r
477 // generate (master-related) wakeup
\r
478 // events when in standby state.Mode
\r
479 // is only relevant if the
\r
480 // appropriate IP module ""mwakeup""
\r
481 // output is implemented."
\r
483 #define MMCHS_HL_SYSCONFIG_STANDBYMODE_S 4
\r
484 #define MMCHS_HL_SYSCONFIG_IDLEMODE_M \
\r
485 0x0000000C // Configuration of the local
\r
486 // target state management mode. By
\r
487 // definition target can handle
\r
488 // read/write transaction as long as
\r
489 // it is out of IDLE state. 0x0
\r
490 // Force-idle mode: local target's
\r
491 // idle state follows (acknowledges)
\r
492 // the system's idle requests
\r
493 // unconditionally i.e. regardless
\r
494 // of the IP module's internal
\r
495 // requirements.Backup mode for
\r
496 // debug only. 0x1 No-idle mode:
\r
497 // local target never enters idle
\r
498 // state.Backup mode for debug only.
\r
499 // 0x2 Smart-idle mode: local
\r
500 // target's idle state eventually
\r
501 // follows (acknowledges) the
\r
502 // system's idle requests depending
\r
503 // on the IP module's internal
\r
504 // requirements.IP module shall not
\r
505 // generate (IRQ- or
\r
506 // DMA-request-related) wakeup
\r
507 // events. 0x3 "Smart-idle
\r
508 // wakeup-capable mode: local
\r
509 // target's idle state eventually
\r
510 // follows (acknowledges) the
\r
511 // system's idle requests depending
\r
512 // on the IP module's internal
\r
513 // requirements.IP module may
\r
514 // generate (IRQ- or
\r
515 // DMA-request-related) wakeup
\r
516 // events when in idle state.Mode is
\r
517 // only relevant if the appropriate
\r
518 // IP module ""swakeup"" output(s)
\r
519 // is (are) implemented."
\r
521 #define MMCHS_HL_SYSCONFIG_IDLEMODE_S 2
\r
522 #define MMCHS_HL_SYSCONFIG_FREEEMU \
\r
523 0x00000002 // Sensitivity to emulation (debug)
\r
524 // suspend input signal.
\r
525 // Functionality NOT implemented in
\r
526 // MMCHS. 0 IP module is sensitive
\r
527 // to emulation suspend 1 IP module
\r
528 // is not sensitive to emulation
\r
531 #define MMCHS_HL_SYSCONFIG_SOFTRESET \
\r
534 //******************************************************************************
\r
536 // The following are defines for the bit fields in the MMCHS_O_SYSCONFIG register.
\r
538 //******************************************************************************
\r
539 #define MMCHS_SYSCONFIG_STANDBYMODE_M \
\r
540 0x00003000 // Master interface power
\r
541 // Management standby/wait control.
\r
542 // The bit field is only useful when
\r
543 // generic parameter MADMA_EN
\r
544 // (Master ADMA enable) is set as
\r
545 // active otherwise it is a read
\r
546 // only register read a '0'. 0x0
\r
547 // Force-standby. Mstandby is forced
\r
548 // unconditionnaly. 0x1 No-standby.
\r
549 // Mstandby is never asserted. 0x2
\r
550 // Smart-standby mode: local
\r
551 // initiator standby status depends
\r
552 // on local conditions i.e. the
\r
553 // module's functional requirement
\r
554 // from the initiator.IP module
\r
555 // shall not generate
\r
556 // (initiator-related) wakeup
\r
557 // events. 0x3 Smart-Standby
\r
558 // wakeup-capable mode: "local
\r
559 // initiator standby status depends
\r
560 // on local conditions i.e. the
\r
561 // module's functional requirement
\r
562 // from the initiator. IP module may
\r
563 // generate (master-related) wakeup
\r
564 // events when in standby state.Mode
\r
565 // is only relevant if the
\r
566 // appropriate IP module ""mwakeup""
\r
567 // output is implemented."
\r
569 #define MMCHS_SYSCONFIG_STANDBYMODE_S 12
\r
570 #define MMCHS_SYSCONFIG_CLOCKACTIVITY_M \
\r
571 0x00000300 // Clocks activity during wake up
\r
572 // mode period. Bit8: OCP interface
\r
573 // clock Bit9: Functional clock 0x0
\r
574 // OCP and Functional clock may be
\r
575 // switched off. 0x1 OCP clock is
\r
576 // maintained. Functional clock may
\r
577 // be switched-off. 0x2 Functional
\r
578 // clock is maintained. OCP clock
\r
579 // may be switched-off. 0x3 OCP and
\r
580 // Functional clocks are maintained.
\r
582 #define MMCHS_SYSCONFIG_CLOCKACTIVITY_S 8
\r
583 #define MMCHS_SYSCONFIG_SIDLEMODE_M \
\r
584 0x00000018 // Power management 0x0 If an idle
\r
585 // request is detected the MMCHS
\r
586 // acknowledges it unconditionally
\r
587 // and goes in Inactive mode.
\r
588 // Interrupt and DMA requests are
\r
589 // unconditionally de-asserted. 0x1
\r
590 // If an idle request is detected
\r
591 // the request is ignored and the
\r
592 // module keeps on behaving
\r
593 // normally. 0x2 Smart-idle mode:
\r
594 // local target's idle state
\r
595 // eventually follows (acknowledges)
\r
596 // the system's idle requests
\r
597 // depending on the IP module's
\r
598 // internal requirements.IP module
\r
599 // shall not generate (IRQ- or
\r
600 // DMA-request-related) wakeup
\r
601 // events. 0x3 Smart-idle
\r
602 // wakeup-capable mode: "local
\r
603 // target's idle state eventually
\r
604 // follows (acknowledges) the
\r
605 // system's idle requests depending
\r
606 // on the IP module's internal
\r
607 // requirements.IP module may
\r
608 // generate (IRQ- or
\r
609 // DMA-request-related) wakeup
\r
610 // events when in idle state.Mode is
\r
611 // only relevant if the appropriate
\r
612 // IP module ""swakeup"" output(s)
\r
613 // is (are) implemented."
\r
615 #define MMCHS_SYSCONFIG_SIDLEMODE_S 3
\r
616 #define MMCHS_SYSCONFIG_ENAWAKEUP \
\r
617 0x00000004 // Wakeup feature control 0 Wakeup
\r
618 // capability is disabled 1 Wakeup
\r
619 // capability is enabled
\r
621 #define MMCHS_SYSCONFIG_SOFTRESET \
\r
624 #define MMCHS_SYSCONFIG_AUTOIDLE \
\r
625 0x00000001 // Internal Clock gating strategy 0
\r
626 // Clocks are free-running 1
\r
627 // Automatic clock gating strategy
\r
628 // is applied based on the OCP and
\r
629 // MMC interface activity
\r
631 //******************************************************************************
\r
633 // The following are defines for the bit fields in the MMCHS_O_SYSSTATUS register.
\r
635 //******************************************************************************
\r
636 #define MMCHS_SYSSTATUS_RESETDONE \
\r
639 //******************************************************************************
\r
641 // The following are defines for the bit fields in the MMCHS_O_CSRE register.
\r
643 //******************************************************************************
\r
644 #define MMCHS_CSRE_CSRE_M 0xFFFFFFFF // Card status response error
\r
645 #define MMCHS_CSRE_CSRE_S 0
\r
646 //******************************************************************************
\r
648 // The following are defines for the bit fields in the MMCHS_O_SYSTEST register.
\r
650 //******************************************************************************
\r
651 #define MMCHS_SYSTEST_OBI 0x00010000
\r
652 #define MMCHS_SYSTEST_SDCD 0x00008000
\r
653 #define MMCHS_SYSTEST_SDWP 0x00004000
\r
654 #define MMCHS_SYSTEST_WAKD 0x00002000
\r
655 #define MMCHS_SYSTEST_SSB 0x00001000
\r
656 #define MMCHS_SYSTEST_D7D 0x00000800
\r
657 #define MMCHS_SYSTEST_D6D 0x00000400
\r
658 #define MMCHS_SYSTEST_D5D 0x00000200
\r
659 #define MMCHS_SYSTEST_D4D 0x00000100
\r
660 #define MMCHS_SYSTEST_D3D 0x00000080
\r
661 #define MMCHS_SYSTEST_D2D 0x00000040
\r
662 #define MMCHS_SYSTEST_D1D 0x00000020
\r
663 #define MMCHS_SYSTEST_D0D 0x00000010
\r
664 #define MMCHS_SYSTEST_DDIR 0x00000008
\r
665 #define MMCHS_SYSTEST_CDAT 0x00000004
\r
666 #define MMCHS_SYSTEST_CDIR 0x00000002
\r
667 #define MMCHS_SYSTEST_MCKD 0x00000001
\r
668 //******************************************************************************
\r
670 // The following are defines for the bit fields in the MMCHS_O_CON register.
\r
672 //******************************************************************************
\r
673 #define MMCHS_CON_SDMA_LNE 0x00200000 // Slave DMA Level/Edge Request:
\r
674 // The waveform of the DMA request
\r
675 // can be configured either edge
\r
676 // sensitive with early de-assertion
\r
677 // on first access to MMCHS_DATA
\r
678 // register or late de-assertion
\r
679 // request remains active until last
\r
680 // allowed data written into
\r
681 // MMCHS_DATA. 0 Slave DMA edge
\r
682 // sensitive Early DMA de-assertion
\r
683 // 1 Slave DMA level sensitive Late
\r
684 // DMA de-assertion
\r
685 #define MMCHS_CON_DMA_MNS 0x00100000 // DMA Master or Slave selection:
\r
686 // When this bit is set and the
\r
687 // controller is configured to use
\r
688 // the DMA Ocp master interface is
\r
689 // used to get datas from system
\r
690 // using ADMA2 procedure (direct
\r
691 // access to the memory).This option
\r
692 // is only available if generic
\r
693 // parameter MADMA_EN is asserted to
\r
694 // '1'. 0 The controller is slave on
\r
695 // data transfers with system. 1 The
\r
696 // controller is master on data
\r
697 // exchange with system controller
\r
698 // must be configured as using DMA.
\r
699 #define MMCHS_CON_DDR 0x00080000 // Dual Data Rate mode: When this
\r
700 // register is set the controller
\r
701 // uses both clock edge to emit or
\r
702 // receive data. Odd bytes are
\r
703 // transmitted on falling edges and
\r
704 // even bytes are transmitted on
\r
705 // rise edges. It only applies on
\r
706 // Data bytes and CRC Start end bits
\r
707 // and CRC status are kept full
\r
708 // cycle. This bit field is only
\r
709 // meaningful and active for even
\r
710 // clock divider ratio of
\r
711 // MMCHS_SYSCTL[CLKD] it is
\r
712 // insensitive to MMCHS_HCTL[HSPE]
\r
713 // setting. 0 Standard mode : data
\r
714 // are transmitted on a single edge
\r
715 // depending on MMCHS_HCTRL[HSPE]. 1
\r
716 // Data Bytes and CRC are
\r
717 // transmitted on both edge.
\r
718 #define MMCHS_CON_BOOT_CF0 0x00040000
\r
719 #define MMCHS_CON_BOOT_ACK 0x00020000 // Book acknowledge received: When
\r
720 // this bit is set the controller
\r
721 // should receive a boot status on
\r
722 // DAT0 line after next command
\r
723 // issued. If no status is received
\r
724 // a data timeout will be generated.
\r
725 // 0 No acknowledge to be received 1
\r
726 // A boot status will be received on
\r
727 // DAT0 line after issuing a
\r
729 #define MMCHS_CON_CLKEXTFREE 0x00010000 // External clock free running:
\r
730 // This register is used to maintain
\r
731 // card clock out of transfer
\r
732 // transaction to enable slave
\r
733 // module for example to generate a
\r
734 // synchronous interrupt on DAT[1].
\r
735 // The Clock will be maintain only
\r
736 // if MMCHS_SYSCTL[CEN] is set. 0
\r
737 // External card clock is cut off
\r
738 // outside active transaction
\r
739 // period. 1 External card clock is
\r
740 // maintain even out of active
\r
741 // transaction period only if
\r
742 // MMCHS_SYSCTL[CEN] is set.
\r
743 #define MMCHS_CON_PADEN 0x00008000 // Control Power for MMC Lines:
\r
744 // This register is only useful when
\r
745 // MMC PADs contain power saving
\r
746 // mechanism to minimize its leakage
\r
747 // power. It works as a GPIO that
\r
748 // directly control the ACTIVE pin
\r
749 // of PADs. Excepted for DAT[1] the
\r
750 // signal is also combine outside
\r
751 // the module with the dedicated
\r
752 // power control MMCHS_CON[CTPL]
\r
753 // bit. 0 ADPIDLE module pin is not
\r
754 // forced it is automatically
\r
755 // generated by the MMC fsms. 1
\r
756 // ADPIDLE module pin is forced to
\r
758 #define MMCHS_CON_OBIE 0x00004000 // Out-of-Band Interrupt Enable MMC
\r
759 // cards only: This bit enables the
\r
760 // detection of Out-of-Band
\r
761 // Interrupt on MMCOBI input pin.
\r
762 // The usage of the Out-of-Band
\r
763 // signal (OBI) is optional and
\r
764 // depends on the system
\r
765 // integration. 0 Out-of-Band
\r
766 // interrupt detection disabled 1
\r
767 // Out-of-Band interrupt detection
\r
769 #define MMCHS_CON_OBIP 0x00002000 // Out-of-Band Interrupt Polarity
\r
770 // MMC cards only: This bit selects
\r
771 // the active level of the
\r
772 // out-of-band interrupt coming from
\r
773 // MMC cards. The usage of the
\r
774 // Out-of-Band signal (OBI) is
\r
775 // optional and depends on the
\r
776 // system integration. 0 active high
\r
777 // level 1 active low level
\r
778 #define MMCHS_CON_CEATA 0x00001000 // CE-ATA control mode MMC cards
\r
779 // compliant with CE-ATA:By default
\r
780 // this bit is set to 0. It is use
\r
781 // to indicate that next commands
\r
782 // are considered as specific CE-ATA
\r
783 // commands that potentially use
\r
784 // 'command completion' features. 0
\r
785 // Standard MMC/SD/SDIO mode. 1
\r
786 // CE-ATA mode next commands are
\r
787 // considered as CE-ATA commands.
\r
788 #define MMCHS_CON_CTPL 0x00000800 // Control Power for DAT[1] line
\r
789 // MMC and SD cards: By default this
\r
790 // bit is set to 0 and the host
\r
791 // controller automatically disables
\r
792 // all the input buffers outside of
\r
793 // a transaction to minimize the
\r
794 // leakage current. SDIO cards: When
\r
795 // this bit is set to 1 the host
\r
796 // controller automatically disables
\r
797 // all the input buffers except the
\r
798 // buffer of DAT[1] outside of a
\r
799 // transaction in order to detect
\r
800 // asynchronous card interrupt on
\r
801 // DAT[1] line and minimize the
\r
802 // leakage current of the buffers. 0
\r
803 // Disable all the input buffers
\r
804 // outside of a transaction. 1
\r
805 // Disable all the input buffers
\r
806 // except the buffer of DAT[1]
\r
807 // outside of a transaction.
\r
808 #define MMCHS_CON_DVAL_M 0x00000600 // Debounce filter value All cards
\r
809 // This register is used to define a
\r
810 // debounce period to filter the
\r
811 // card detect input signal (SDCD).
\r
812 // The usage of the card detect
\r
813 // input signal (SDCD) is optional
\r
814 // and depends on the system
\r
815 // integration and the type of the
\r
816 // connector housing that
\r
817 // accommodates the card. 0x0 33 us
\r
818 // debounce period 0x1 231 us
\r
819 // debounce period 0x2 1 ms debounce
\r
820 // period 0x3 84 ms debounce period
\r
821 #define MMCHS_CON_DVAL_S 9
\r
822 #define MMCHS_CON_WPP 0x00000100 // Write protect polarity For SD
\r
823 // and SDIO cards only This bit
\r
824 // selects the active level of the
\r
825 // write protect input signal
\r
826 // (SDWP). The usage of the write
\r
827 // protect input signal (SDWP) is
\r
828 // optional and depends on the
\r
829 // system integration and the type
\r
830 // of the connector housing that
\r
831 // accommodates the card. 0 active
\r
832 // high level 1 active low level
\r
833 #define MMCHS_CON_CDP 0x00000080 // Card detect polarity All cards
\r
834 // This bit selects the active level
\r
835 // of the card detect input signal
\r
836 // (SDCD). The usage of the card
\r
837 // detect input signal (SDCD) is
\r
838 // optional and depends on the
\r
839 // system integration and the type
\r
840 // of the connector housing that
\r
841 // accommodates the card. 0 active
\r
842 // high level 1 active low level
\r
843 #define MMCHS_CON_MIT 0x00000040 // MMC interrupt command Only for
\r
844 // MMC cards. This bit must be set
\r
845 // to 1 when the next write access
\r
846 // to the command register
\r
847 // (MMCHS_CMD) is for writing a MMC
\r
848 // interrupt command (CMD40)
\r
849 // requiring the command timeout
\r
850 // detection to be disabled for the
\r
851 // command response. 0 Command
\r
852 // timeout enabled 1 Command timeout
\r
854 #define MMCHS_CON_DW8 0x00000020 // 8-bit mode MMC select For
\r
855 // SD/SDIO cards this bit must be
\r
856 // set to 0. For MMC card this bit
\r
857 // must be set following a valid
\r
858 // SWITCH command (CMD6) with the
\r
859 // correct value and extend CSD
\r
860 // index written in the argument.
\r
861 // Prior to this command the MMC
\r
862 // card configuration register (CSD
\r
863 // and EXT_CSD) must be verified for
\r
864 // compliancy with MMC standard
\r
865 // specification 4.x (see section
\r
866 // 3.6). 0 1-bit or 4-bit Data width
\r
867 // (DAT[0] used MMC SD cards) 1
\r
868 // 8-bit Data width (DAT[7:0] used
\r
870 #define MMCHS_CON_MODE 0x00000010 // Mode select All cards These bits
\r
871 // select between Functional mode
\r
872 // and SYSTEST mode. 0 Functional
\r
873 // mode. Transfers to the
\r
874 // MMC/SD/SDIO cards follow the card
\r
875 // protocol. MMC clock is enabled.
\r
876 // MMC/SD transfers are operated
\r
877 // under the control of the CMD
\r
878 // register. 1 SYSTEST mode The
\r
879 // signal pins are configured as
\r
880 // general-purpose input/output and
\r
881 // the 1024-byte buffer is
\r
882 // configured as a stack memory
\r
883 // accessible only by the local host
\r
884 // or system DMA. The pins retain
\r
885 // their default type (input output
\r
886 // or in-out). SYSTEST mode is
\r
887 // operated under the control of the
\r
888 // SYSTEST register.
\r
889 #define MMCHS_CON_STR 0x00000008 // Stream command Only for MMC
\r
890 // cards. This bit must be set to 1
\r
891 // only for the stream data
\r
892 // transfers (read or write) of the
\r
893 // adtc commands. Stream read is a
\r
894 // class 1 command (CMD11:
\r
895 // READ_DAT_UNTIL_STOP). Stream
\r
896 // write is a class 3 command
\r
897 // (CMD20: WRITE_DAT_UNTIL_STOP). 0
\r
898 // Block oriented data transfer 1
\r
899 // Stream oriented data transfer
\r
900 #define MMCHS_CON_HR 0x00000004 // Broadcast host response Only for
\r
901 // MMC cards. This register is used
\r
902 // to force the host to generate a
\r
903 // 48-bit response for bc command
\r
904 // type. "It can be used to
\r
905 // terminate the interrupt mode by
\r
906 // generating a CMD40 response by
\r
907 // the core (see section 4.3
\r
908 // ""Interrupt Mode"" in the MMC [1]
\r
909 // specification). In order to have
\r
910 // the host response to be generated
\r
911 // in open drain mode the register
\r
912 // MMCHS_CON[OD] must be set to 1."
\r
913 // When MMCHS_CON[CEATA] is set to 1
\r
914 // and MMCHS_ARG set to 0x00000000
\r
915 // when writing 0x00000000 into
\r
916 // MMCHS_CMD register the host
\r
917 // controller performs a 'command
\r
918 // completion signal disable' token
\r
919 // i.e. CMD line held to '0' during
\r
920 // 47 cycles followed by a 1. 0 The
\r
921 // host does not generate a 48-bit
\r
922 // response instead of a command. 1
\r
923 // The host generates a 48-bit
\r
924 // response instead of a command or
\r
925 // a command completion signal
\r
927 #define MMCHS_CON_INIT 0x00000002 // Send initialization stream All
\r
928 // cards. When this bit is set to 1
\r
929 // and the card is idle an
\r
930 // initialization sequence is sent
\r
931 // to the card. "An initialization
\r
932 // sequence consists of setting the
\r
933 // CMD line to 1 during 80 clock
\r
934 // cycles. The initialisation
\r
935 // sequence is mandatory - but it is
\r
936 // not required to do it through
\r
937 // this bit - this bit makes it
\r
938 // easier. Clock divider
\r
939 // (MMCHS_SYSCTL[CLKD]) should be
\r
940 // set to ensure that 80 clock
\r
941 // periods are greater than 1ms.
\r
942 // (see section 9.3 ""Power-Up"" in
\r
943 // the MMC card specification [1] or
\r
944 // section 6.4 in the SD card
\r
945 // specification [2])." Note: in
\r
946 // this mode there is no command
\r
947 // sent to the card and no response
\r
948 // is expected 0 The host does not
\r
949 // send an initialization sequence.
\r
950 // 1 The host sends an
\r
951 // initialization sequence.
\r
952 #define MMCHS_CON_OD 0x00000001 // Card open drain mode. Only for
\r
953 // MMC cards. This bit must be set
\r
954 // to 1 for MMC card commands 1 2 3
\r
955 // and 40 and if the MMC card bus is
\r
956 // operating in open-drain mode
\r
957 // during the response phase to the
\r
958 // command sent. Typically during
\r
959 // card identification mode when the
\r
960 // card is either in idle ready or
\r
961 // ident state. It is also necessary
\r
962 // to set this bit to 1 for a
\r
963 // broadcast host response (see
\r
964 // Broadcast host response register
\r
965 // MMCHS_CON[HR]) 0 No Open Drain 1
\r
966 // Open Drain or Broadcast host
\r
968 //******************************************************************************
\r
970 // The following are defines for the bit fields in the MMCHS_O_PWCNT register.
\r
972 //******************************************************************************
\r
973 #define MMCHS_PWCNT_PWRCNT_M 0x0000FFFF // Power counter register. This
\r
974 // register is used to introduce a
\r
975 // delay between the PAD ACTIVE pin
\r
976 // assertion and the command issued.
\r
977 // 0x0000 No additional delay added
\r
978 // 0x0001 TCF delay (card clock
\r
979 // period) 0x0002 TCF x 2 delay
\r
980 // (card clock period) 0xFFFE TCF x
\r
981 // 65534 delay (card clock period)
\r
982 // 0xFFFF TCF x 65535 delay (card
\r
984 #define MMCHS_PWCNT_PWRCNT_S 0
\r
985 //******************************************************************************
\r
987 // The following are defines for the bit fields in the MMCHS_O_BLK register.
\r
989 //******************************************************************************
\r
990 #define MMCHS_BLK_NBLK_M 0xFFFF0000 // Blocks count for current
\r
991 // transfer This register is enabled
\r
992 // when Block count Enable
\r
993 // (MMCHS_CMD[BCE]) is set to 1 and
\r
994 // is valid only for multiple block
\r
995 // transfers. Setting the block
\r
996 // count to 0 results no data blocks
\r
997 // being transferred. Note: The host
\r
998 // controller decrements the block
\r
999 // count after each block transfer
\r
1000 // and stops when the count reaches
\r
1001 // zero. This register can be
\r
1002 // accessed only if no transaction
\r
1003 // is executing (i.e after a
\r
1004 // transaction has stopped). Read
\r
1005 // operations during transfers may
\r
1006 // return an invalid value and write
\r
1007 // operation will be ignored. In
\r
1008 // suspend context the number of
\r
1009 // blocks yet to be transferred can
\r
1010 // be determined by reading this
\r
1011 // register. When restoring transfer
\r
1012 // context prior to issuing a Resume
\r
1013 // command The local host shall
\r
1014 // restore the previously saved
\r
1015 // block count. 0x0000 Stop count
\r
1016 // 0x0001 1 block 0x0002 2 blocks
\r
1017 // 0xFFFF 65535 blocks
\r
1018 #define MMCHS_BLK_NBLK_S 16
\r
1019 #define MMCHS_BLK_BLEN_M 0x00000FFF // Transfer Block Size. This
\r
1020 // register specifies the block size
\r
1021 // for block data transfers. Read
\r
1022 // operations during transfers may
\r
1023 // return an invalid value and write
\r
1024 // operations are ignored. When a
\r
1025 // CMD12 command is issued to stop
\r
1026 // the transfer a read of the BLEN
\r
1027 // field after transfer completion
\r
1028 // (MMCHS_STAT[TC] set to 1) will
\r
1029 // not return the true byte number
\r
1030 // of data length while the stop
\r
1031 // occurs but the value written in
\r
1032 // this register before transfer is
\r
1033 // launched. 0x000 No data transfer
\r
1034 // 0x001 1 byte block length 0x002 2
\r
1035 // bytes block length 0x003 3 bytes
\r
1036 // block length 0x1FF 511 bytes
\r
1037 // block length 0x200 512 bytes
\r
1038 // block length 0x7FF 2047 bytes
\r
1039 // block length 0x800 2048 bytes
\r
1041 #define MMCHS_BLK_BLEN_S 0
\r
1042 //******************************************************************************
\r
1044 // The following are defines for the bit fields in the MMCHS_O_ARG register.
\r
1046 //******************************************************************************
\r
1047 #define MMCHS_ARG_ARG_M 0xFFFFFFFF // Command argument bits [31:0]
\r
1048 #define MMCHS_ARG_ARG_S 0
\r
1049 //******************************************************************************
\r
1051 // The following are defines for the bit fields in the MMCHS_O_CMD register.
\r
1053 //******************************************************************************
\r
1054 #define MMCHS_CMD_INDX_M 0x3F000000 // Command index Binary encoded
\r
1055 // value from 0 to 63 specifying the
\r
1056 // command number send to card 0x00
\r
1057 // CMD0 or ACMD0 0x01 CMD1 or ACMD1
\r
1058 // 0x02 CMD2 or ACMD2 0x03 CMD3 or
\r
1059 // ACMD3 0x04 CMD4 or ACMD4 0x05
\r
1060 // CMD5 or ACMD5 0x06 CMD6 or ACMD6
\r
1061 // 0x07 CMD7 or ACMD7 0x08 CMD8 or
\r
1062 // ACMD8 0x09 CMD9 or ACMD9 0x0A
\r
1063 // CMD10 or ACMD10 0x0B CMD11 or
\r
1064 // ACMD11 0x0C CMD12 or ACMD12 0x0D
\r
1065 // CMD13 or ACMD13 0x0E CMD14 or
\r
1066 // ACMD14 0x0F CMD15 or ACMD15 0x10
\r
1067 // CMD16 or ACMD16 0x11 CMD17 or
\r
1068 // ACMD17 0x12 CMD18 or ACMD18 0x13
\r
1069 // CMD19 or ACMD19 0x14 CMD20 or
\r
1070 // ACMD20 0x15 CMD21 or ACMD21 0x16
\r
1071 // CMD22 or ACMD22 0x17 CMD23 or
\r
1072 // ACMD23 0x18 CMD24 or ACMD24 0x19
\r
1073 // CMD25 or ACMD25 0x1A CMD26 or
\r
1074 // ACMD26 0x1B CMD27 or ACMD27 0x1C
\r
1075 // CMD28 or ACMD28 0x1D CMD29 or
\r
1076 // ACMD29 0x1E CMD30 or ACMD30 0x1F
\r
1077 // CMD31 or ACMD31 0x20 CMD32 or
\r
1078 // ACMD32 0x21 CMD33 or ACMD33 0x22
\r
1079 // CMD34 or ACMD34 0x23 CMD35 or
\r
1080 // ACMD35 0x24 CMD36 or ACMD36 0x25
\r
1081 // CMD37 or ACMD37 0x26 CMD38 or
\r
1082 // ACMD38 0x27 CMD39 or ACMD39 0x28
\r
1083 // CMD40 or ACMD40 0x29 CMD41 or
\r
1084 // ACMD41 0x2A CMD42 or ACMD42 0x2B
\r
1085 // CMD43 or ACMD43 0x2C CMD44 or
\r
1086 // ACMD44 0x2D CMD45 or ACMD45 0x2E
\r
1087 // CMD46 or ACMD46 0x2F CMD47 or
\r
1088 // ACMD47 0x30 CMD48 or ACMD48 0x31
\r
1089 // CMD49 or ACMD49 0x32 CMD50 or
\r
1090 // ACMD50 0x33 CMD51 or ACMD51 0x34
\r
1091 // CMD52 or ACMD52 0x35 CMD53 or
\r
1092 // ACMD53 0x36 CMD54 or ACMD54 0x37
\r
1093 // CMD55 or ACMD55 0x38 CMD56 or
\r
1094 // ACMD56 0x39 CMD57 or ACMD57 0x3A
\r
1095 // CMD58 or ACMD58 0x3B CMD59 or
\r
1096 // ACMD59 0x3C CMD60 or ACMD60 0x3D
\r
1097 // CMD61 or ACMD61 0x3E CMD62 or
\r
1098 // ACMD62 0x3F CMD63 or ACMD63
\r
1099 #define MMCHS_CMD_INDX_S 24
\r
1100 #define MMCHS_CMD_CMD_TYPE_M 0x00C00000 // Command type This register
\r
1101 // specifies three types of special
\r
1102 // command: Suspend Resume and
\r
1103 // Abort. These bits shall be set to
\r
1104 // 00b for all other commands. 0x0
\r
1105 // Others Commands 0x1 "CMD52 for
\r
1106 // writing ""Bus Suspend"" in CCCR"
\r
1107 // 0x2 "CMD52 for writing ""Function
\r
1108 // Select"" in CCCR" 0x3 "Abort
\r
1109 // command CMD12 CMD52 for writing
\r
1110 // "" I/O Abort"" in CCCR"
\r
1111 #define MMCHS_CMD_CMD_TYPE_S 22
\r
1112 #define MMCHS_CMD_DP 0x00200000 // Data present select This
\r
1113 // register indicates that data is
\r
1114 // present and DAT line shall be
\r
1115 // used. It must be set to 0 in the
\r
1116 // following conditions: - command
\r
1117 // using only CMD line - command
\r
1118 // with no data transfer but using
\r
1119 // busy signal on DAT[0] - Resume
\r
1120 // command 0 Command with no data
\r
1121 // transfer 1 Command with data
\r
1123 #define MMCHS_CMD_CICE 0x00100000 // Command Index check enable This
\r
1124 // bit must be set to 1 to enable
\r
1125 // index check on command response
\r
1126 // to compare the index field in the
\r
1127 // response against the index of the
\r
1128 // command. If the index is not the
\r
1129 // same in the response as in the
\r
1130 // command it is reported as a
\r
1131 // command index error
\r
1132 // (MMCHS_STAT[CIE] set to1) Note:
\r
1133 // The register CICE cannot be
\r
1134 // configured for an Auto CMD12 then
\r
1135 // index check is automatically
\r
1136 // checked when this command is
\r
1137 // issued. 0 Index check disable 1
\r
1138 // Index check enable
\r
1139 #define MMCHS_CMD_CCCE 0x00080000 // Command CRC check enable This
\r
1140 // bit must be set to 1 to enable
\r
1141 // CRC7 check on command response to
\r
1142 // protect the response against
\r
1143 // transmission errors on the bus.
\r
1144 // If an error is detected it is
\r
1145 // reported as a command CRC error
\r
1146 // (MMCHS_STAT[CCRC] set to 1).
\r
1147 // Note: The register CCCE cannot be
\r
1148 // configured for an Auto CMD12 and
\r
1149 // then CRC check is automatically
\r
1150 // checked when this command is
\r
1151 // issued. 0 CRC7 check disable 1
\r
1152 // CRC7 check enable
\r
1153 #define MMCHS_CMD_RSP_TYPE_M 0x00030000 // Response type This bits defines
\r
1154 // the response type of the command
\r
1155 // 0x0 No response 0x1 Response
\r
1156 // Length 136 bits 0x2 Response
\r
1157 // Length 48 bits 0x3 Response
\r
1158 // Length 48 bits with busy after
\r
1160 #define MMCHS_CMD_RSP_TYPE_S 16
\r
1161 #define MMCHS_CMD_MSBS 0x00000020 // Multi/Single block select This
\r
1162 // bit must be set to 1 for data
\r
1163 // transfer in case of multi block
\r
1164 // command. For any others command
\r
1165 // this bit shall be set to 0. 0
\r
1166 // Single block. If this bit is 0 it
\r
1167 // is not necessary to set the
\r
1168 // register MMCHS_BLK[NBLK]. 1 Multi
\r
1169 // block. When Block Count is
\r
1170 // disabled (MMCHS_CMD[BCE] is set
\r
1171 // to 0) in Multiple block transfers
\r
1172 // (MMCHS_CMD[MSBS] is set to 1) the
\r
1173 // module can perform infinite
\r
1175 #define MMCHS_CMD_DDIR 0x00000010 // Data transfer Direction Select
\r
1176 // This bit defines either data
\r
1177 // transfer will be a read or a
\r
1178 // write. 0 Data Write (host to
\r
1179 // card) 1 Data Read (card to host)
\r
1180 #define MMCHS_CMD_ACEN 0x00000004 // Auto CMD12 Enable SD card only.
\r
1181 // When this bit is set to 1 the
\r
1182 // host controller issues a CMD12
\r
1183 // automatically after the transfer
\r
1184 // completion of the last block. The
\r
1185 // Host Driver shall not set this
\r
1186 // bit to issue commands that do not
\r
1187 // require CMD12 to stop data
\r
1188 // transfer. In particular secure
\r
1189 // commands do not require CMD12. 0
\r
1190 // Auto CMD12 disable 1 Auto CMD12
\r
1191 // enable or CCS detection enabled.
\r
1192 #define MMCHS_CMD_BCE 0x00000002 // Block Count Enable Multiple
\r
1193 // block transfers only. This bit is
\r
1194 // used to enable the block count
\r
1195 // register (MMCHS_BLK[NBLK]). When
\r
1196 // Block Count is disabled
\r
1197 // (MMCHS_CMD[BCE] is set to 0) in
\r
1198 // Multiple block transfers
\r
1199 // (MMCHS_CMD[MSBS] is set to 1) the
\r
1200 // module can perform infinite
\r
1201 // transfer. 0 Block count disabled
\r
1202 // for infinite transfer. 1 Block
\r
1203 // count enabled for multiple block
\r
1204 // transfer with known number of
\r
1206 #define MMCHS_CMD_DE 0x00000001 // DMA Enable This bit is used to
\r
1207 // enable DMA mode for host data
\r
1208 // access. 0 DMA mode disable 1 DMA
\r
1210 //******************************************************************************
\r
1212 // The following are defines for the bit fields in the MMCHS_O_RSP10 register.
\r
1214 //******************************************************************************
\r
1215 #define MMCHS_RSP10_RSP1_M 0xFFFF0000 // Command Response [31:16]
\r
1216 #define MMCHS_RSP10_RSP1_S 16
\r
1217 #define MMCHS_RSP10_RSP0_M 0x0000FFFF // Command Response [15:0]
\r
1218 #define MMCHS_RSP10_RSP0_S 0
\r
1219 //******************************************************************************
\r
1221 // The following are defines for the bit fields in the MMCHS_O_RSP32 register.
\r
1223 //******************************************************************************
\r
1224 #define MMCHS_RSP32_RSP3_M 0xFFFF0000 // Command Response [63:48]
\r
1225 #define MMCHS_RSP32_RSP3_S 16
\r
1226 #define MMCHS_RSP32_RSP2_M 0x0000FFFF // Command Response [47:32]
\r
1227 #define MMCHS_RSP32_RSP2_S 0
\r
1228 //******************************************************************************
\r
1230 // The following are defines for the bit fields in the MMCHS_O_RSP54 register.
\r
1232 //******************************************************************************
\r
1233 #define MMCHS_RSP54_RSP5_M 0xFFFF0000 // Command Response [95:80]
\r
1234 #define MMCHS_RSP54_RSP5_S 16
\r
1235 #define MMCHS_RSP54_RSP4_M 0x0000FFFF // Command Response [79:64]
\r
1236 #define MMCHS_RSP54_RSP4_S 0
\r
1237 //******************************************************************************
\r
1239 // The following are defines for the bit fields in the MMCHS_O_RSP76 register.
\r
1241 //******************************************************************************
\r
1242 #define MMCHS_RSP76_RSP7_M 0xFFFF0000 // Command Response [127:112]
\r
1243 #define MMCHS_RSP76_RSP7_S 16
\r
1244 #define MMCHS_RSP76_RSP6_M 0x0000FFFF // Command Response [111:96]
\r
1245 #define MMCHS_RSP76_RSP6_S 0
\r
1246 //******************************************************************************
\r
1248 // The following are defines for the bit fields in the MMCHS_O_DATA register.
\r
1250 //******************************************************************************
\r
1251 #define MMCHS_DATA_DATA_M 0xFFFFFFFF // Data Register [31:0] In
\r
1252 // functional mode (MMCHS_CON[MODE]
\r
1253 // set to the default value 0) A
\r
1254 // read access to this register is
\r
1255 // allowed only when the buffer read
\r
1256 // enable status is set to 1
\r
1257 // (MMCHS_PSTATE[BRE]) otherwise a
\r
1258 // bad access (MMCHS_STAT[BADA]) is
\r
1259 // signaled. A write access to this
\r
1260 // register is allowed only when the
\r
1261 // buffer write enable status is set
\r
1262 // to 1(MMCHS_STATE[BWE]) otherwise
\r
1263 // a bad access (MMCHS_STAT[BADA])
\r
1264 // is signaled and the data is not
\r
1266 #define MMCHS_DATA_DATA_S 0
\r
1267 //******************************************************************************
\r
1269 // The following are defines for the bit fields in the MMCHS_O_PSTATE register.
\r
1271 //******************************************************************************
\r
1272 #define MMCHS_PSTATE_CLEV 0x01000000
\r
1273 #define MMCHS_PSTATE_DLEV_M 0x00F00000 // DAT[3:0] line signal level
\r
1274 // DAT[3] => bit 23 DAT[2] => bit 22
\r
1275 // DAT[1] => bit 21 DAT[0] => bit 20
\r
1276 // This status is used to check DAT
\r
1277 // line level to recover from errors
\r
1278 // and for debugging. This is
\r
1279 // especially useful in detecting
\r
1280 // the busy signal level from
\r
1281 // DAT[0]. The value of these
\r
1282 // registers after reset depends on
\r
1283 // the DAT lines level at that time.
\r
1284 #define MMCHS_PSTATE_DLEV_S 20
\r
1285 #define MMCHS_PSTATE_WP 0x00080000
\r
1286 #define MMCHS_PSTATE_CDPL 0x00040000
\r
1287 #define MMCHS_PSTATE_CSS 0x00020000
\r
1288 #define MMCHS_PSTATE_CINS 0x00010000
\r
1289 #define MMCHS_PSTATE_BRE 0x00000800
\r
1290 #define MMCHS_PSTATE_BWE 0x00000400
\r
1291 #define MMCHS_PSTATE_RTA 0x00000200
\r
1292 #define MMCHS_PSTATE_WTA 0x00000100
\r
1293 #define MMCHS_PSTATE_DLA 0x00000004
\r
1294 #define MMCHS_PSTATE_DATI 0x00000002
\r
1295 #define MMCHS_PSTATE_CMDI 0x00000001
\r
1296 //******************************************************************************
\r
1298 // The following are defines for the bit fields in the MMCHS_O_HCTL register.
\r
1300 //******************************************************************************
\r
1301 #define MMCHS_HCTL_OBWE 0x08000000 // Wakeup event enable for
\r
1302 // 'Out-of-Band' Interrupt. This bit
\r
1303 // enables wakeup events for
\r
1304 // 'Out-of-Band' assertion. Wakeup
\r
1305 // is generated if the wakeup
\r
1306 // feature is enabled
\r
1307 // (MMCHS_SYSCONFIG[ENAWAKEUP]). The
\r
1308 // write to this register is ignored
\r
1309 // when MMCHS_CON[OBIE] is not set.
\r
1310 // 0 Disable wakeup on 'Out-of-Band'
\r
1311 // Interrupt 1 Enable wakeup on
\r
1312 // 'Out-of-Band' Interrupt
\r
1313 #define MMCHS_HCTL_REM 0x04000000 // Wakeup event enable on SD card
\r
1314 // removal This bit enables wakeup
\r
1315 // events for card removal
\r
1316 // assertion. Wakeup is generated if
\r
1317 // the wakeup feature is enabled
\r
1318 // (MMCHS_SYSCONFIG[ENAWAKEUP]). 0
\r
1319 // Disable wakeup on card removal 1
\r
1320 // Enable wakeup on card removal
\r
1321 #define MMCHS_HCTL_INS 0x02000000 // Wakeup event enable on SD card
\r
1322 // insertion This bit enables wakeup
\r
1323 // events for card insertion
\r
1324 // assertion. Wakeup is generated if
\r
1325 // the wakeup feature is enabled
\r
1326 // (MMCHS_SYSCONFIG[ENAWAKEUP]). 0
\r
1327 // Disable wakeup on card insertion
\r
1328 // 1 Enable wakeup on card insertion
\r
1329 #define MMCHS_HCTL_IWE 0x01000000 // Wakeup event enable on SD card
\r
1330 // interrupt This bit enables wakeup
\r
1331 // events for card interrupt
\r
1332 // assertion. Wakeup is generated if
\r
1333 // the wakeup feature is enabled
\r
1334 // (MMCHS_SYSCONFIG[ENAWAKEUP]). 0
\r
1335 // Disable wakeup on card interrupt
\r
1336 // 1 Enable wakeup on card interrupt
\r
1337 #define MMCHS_HCTL_IBG 0x00080000 // Interrupt block at gap This bit
\r
1338 // is valid only in 4-bit mode of
\r
1339 // SDIO card to enable interrupt
\r
1340 // detection in the interrupt cycle
\r
1341 // at block gap for a multiple block
\r
1342 // transfer. For MMC cards and for
\r
1343 // SD card this bit should be set to
\r
1344 // 0. 0 Disable interrupt detection
\r
1345 // at the block gap in 4-bit mode 1
\r
1346 // Enable interrupt detection at the
\r
1347 // block gap in 4-bit mode
\r
1348 #define MMCHS_HCTL_RWC 0x00040000 // Read wait control The read wait
\r
1349 // function is optional only for
\r
1350 // SDIO cards. If the card supports
\r
1351 // read wait this bit must be
\r
1352 // enabled then requesting a stop at
\r
1353 // block gap (MMCHS_HCTL[SBGR])
\r
1354 // generates a read wait period
\r
1355 // after the current end of block.
\r
1356 // Be careful if read wait is not
\r
1357 // supported it may cause a conflict
\r
1358 // on DAT line. 0 Disable Read Wait
\r
1359 // Control. Suspend/Resume cannot be
\r
1360 // supported. 1 Enable Read Wait
\r
1362 #define MMCHS_HCTL_CR 0x00020000 // Continue request This bit is
\r
1363 // used to restart a transaction
\r
1364 // that was stopped by requesting a
\r
1365 // stop at block gap
\r
1366 // (MMCHS_HCTL[SBGR]). Set this bit
\r
1367 // to 1 restarts the transfer. The
\r
1368 // bit is automatically set to 0 by
\r
1369 // the host controller when transfer
\r
1370 // has restarted i.e DAT line is
\r
1371 // active (MMCHS_PSTATE[DLA]) or
\r
1372 // transferring data
\r
1373 // (MMCHS_PSTATE[WTA]). The Stop at
\r
1374 // block gap request must be
\r
1375 // disabled (MMCHS_HCTL[SBGR]=0)
\r
1376 // before setting this bit. 0 No
\r
1377 // affect 1 transfer restart
\r
1378 #define MMCHS_HCTL_SBGR 0x00010000 // Stop at block gap request This
\r
1379 // bit is used to stop executing a
\r
1380 // transaction at the next block
\r
1381 // gap. The transfer can restart
\r
1382 // with a continue request
\r
1383 // (MMHS_HCTL[CR]) or during a
\r
1384 // suspend/resume sequence. In case
\r
1385 // of read transfer the card must
\r
1386 // support read wait control. In
\r
1387 // case of write transfer the host
\r
1388 // driver shall set this bit after
\r
1389 // all block data written. Until the
\r
1390 // transfer completion
\r
1391 // (MMCHS_STAT[TC] set to 1) the
\r
1392 // host driver shall leave this bit
\r
1393 // set to 1. If this bit is set the
\r
1394 // local host shall not write to the
\r
1395 // data register (MMCHS_DATA). 0
\r
1396 // Transfer mode 1 Stop at block gap
\r
1397 #define MMCHS_HCTL_SDVS_M 0x00000E00 // SD bus voltage select All cards.
\r
1398 // The host driver should set to
\r
1399 // these bits to select the voltage
\r
1400 // level for the card according to
\r
1401 // the voltage supported by the
\r
1402 // system (MMCHS_CAPA[VS18VS30VS33])
\r
1403 // before starting a transfer. 0x5
\r
1404 // 1.8V (Typical) 0x6 3.0V (Typical)
\r
1405 // 0x7 3.3V (Typical)
\r
1406 #define MMCHS_HCTL_SDVS_S 9
\r
1407 #define MMCHS_HCTL_SDBP 0x00000100 // SD bus power Before setting this
\r
1408 // bit the host driver shall select
\r
1409 // the SD bus voltage
\r
1410 // (MMCHS_HCTL[SDVS]). If the host
\r
1411 // controller detects the No card
\r
1412 // state this bit is automatically
\r
1413 // set to 0. If the module is power
\r
1414 // off a write in the command
\r
1415 // register (MMCHS_CMD) will not
\r
1416 // start the transfer. A write to
\r
1417 // this bit has no effect if the
\r
1418 // selected SD bus voltage
\r
1419 // MMCHS_HCTL[SDVS] is not supported
\r
1420 // according to capability register
\r
1421 // (MMCHS_CAPA[VS*]). 0 Power off 1
\r
1423 #define MMCHS_HCTL_CDSS 0x00000080 // Card Detect Signal Selection
\r
1424 // This bit selects source for the
\r
1425 // card detection.When the source
\r
1426 // for the card detection is
\r
1427 // switched the interrupt should be
\r
1428 // disabled during the switching
\r
1429 // period by clearing the Interrupt
\r
1430 // Status/Signal Enable register in
\r
1431 // order to mask unexpected
\r
1432 // interrupt being caused by the
\r
1433 // glitch. The Interrupt
\r
1434 // Status/Signal Enable should be
\r
1435 // disabled during over the period
\r
1436 // of debouncing. 0 SDCD# is
\r
1437 // selected (for normal use) 1 The
\r
1438 // Card Detect Test Level is
\r
1439 // selected (for test purpose)
\r
1440 #define MMCHS_HCTL_CDTL 0x00000040 // Card Detect Test Level: This bit
\r
1441 // is enabled while the Card Detect
\r
1442 // Signal Selection is set to 1 and
\r
1443 // it indicates card inserted or
\r
1444 // not. 0 No Card 1 Card Inserted
\r
1445 #define MMCHS_HCTL_DMAS_M 0x00000018 // DMA Select Mode: One of
\r
1446 // supported DMA modes can be
\r
1447 // selected. The host driver shall
\r
1448 // check support of DMA modes by
\r
1449 // referring the Capabilities
\r
1450 // register. Use of selected DMA is
\r
1451 // determined by DMA Enable of the
\r
1452 // Transfer Mode register. This
\r
1453 // register is only meaningful when
\r
1454 // MADMA_EN is set to 1. When
\r
1455 // MADMA_EN is set to 0 the bit
\r
1456 // field is read only and returned
\r
1457 // value is 0. 0x0 Reserved 0x1
\r
1458 // Reserved 0x2 32-bit Address ADMA2
\r
1459 // is selected 0x3 Reserved
\r
1460 #define MMCHS_HCTL_DMAS_S 3
\r
1461 #define MMCHS_HCTL_HSPE 0x00000004 // High Speed Enable: Before
\r
1462 // setting this bit the Host Driver
\r
1463 // shall check the High Speed
\r
1464 // Support in the Capabilities
\r
1465 // register. If this bit is set to 0
\r
1466 // (default) the Host Controller
\r
1467 // outputs CMD line and DAT lines at
\r
1468 // the falling edge of the SD Clock.
\r
1469 // If this bit is set to 1 the Host
\r
1470 // Controller outputs CMD line and
\r
1471 // DAT lines at the rising edge of
\r
1472 // the SD Clock.This bit shall not
\r
1473 // be set when dual data rate mode
\r
1474 // is activated in MMCHS_CON[DDR]. 0
\r
1475 // Normal speed mode 1 High speed
\r
1477 #define MMCHS_HCTL_DTW 0x00000002 // Data transfer width For MMC card
\r
1478 // this bit must be set following a
\r
1479 // valid SWITCH command (CMD6) with
\r
1480 // the correct value and extend CSD
\r
1481 // index written in the argument.
\r
1482 // Prior to this command the MMC
\r
1483 // card configuration register (CSD
\r
1484 // and EXT_CSD) must be verified for
\r
1485 // compliance with MMC standard
\r
1486 // specification 4.x (see section
\r
1487 // 3.6). This register has no effect
\r
1488 // when the MMC 8-bit mode is
\r
1489 // selected (register MMCHS_CON[DW8]
\r
1490 // set to1 ) For SD/SDIO cards this
\r
1491 // bit must be set following a valid
\r
1492 // SET_BUS_WIDTH command (ACMD6)
\r
1493 // with the value written in bit 1
\r
1494 // of the argument. Prior to this
\r
1495 // command the SD card configuration
\r
1496 // register (SCR) must be verified
\r
1497 // for the supported bus width by
\r
1498 // the SD card. 0 1-bit Data width
\r
1499 // (DAT[0] used) 1 4-bit Data width
\r
1500 // (DAT[3:0] used)
\r
1501 //******************************************************************************
\r
1503 // The following are defines for the bit fields in the MMCHS_O_SYSCTL register.
\r
1505 //******************************************************************************
\r
1506 #define MMCHS_SYSCTL_SRD 0x04000000 // Software reset for DAT line This
\r
1507 // bit is set to 1 for reset and
\r
1508 // released to 0 when completed. DAT
\r
1509 // finite state machine in both
\r
1510 // clock domain are also reset. Here
\r
1511 // below are the registers cleared
\r
1512 // by MMCHS_SYSCTL[SRD]: #VALUE! -
\r
1513 // MMCHS_PSTATE: BRE BWE RTA WTA DLA
\r
1514 // and DATI - MMCHS_HCTL: SBGR and
\r
1515 // CR - MMCHS_STAT: BRR BWR BGE and
\r
1516 // TC OCP and MMC buffer data
\r
1517 // management is reinitialized. 0
\r
1518 // Reset completed 1 Software reset
\r
1520 #define MMCHS_SYSCTL_SRC 0x02000000 // Software reset for CMD line This
\r
1521 // bit is set to 1 for reset and
\r
1522 // released to 0 when completed. CMD
\r
1523 // finite state machine in both
\r
1524 // clock domain are also reset. Here
\r
1525 // below the registers cleared by
\r
1526 // MMCHS_SYSCTL[SRC]: -
\r
1527 // MMCHS_PSTATE: CMDI - MMCHS_STAT:
\r
1528 // CC OCP and MMC command status
\r
1529 // management is reinitialized. 0
\r
1530 // Reset completed 1 Software reset
\r
1532 #define MMCHS_SYSCTL_SRA 0x01000000 // Software reset for all This bit
\r
1533 // is set to 1 for reset and
\r
1534 // released to 0 when completed.
\r
1535 // This reset affects the entire
\r
1536 // host controller except for the
\r
1537 // card detection circuit and
\r
1538 // capabilities registers. 0 Reset
\r
1539 // completed 1 Software reset for
\r
1541 #define MMCHS_SYSCTL_DTO_M 0x000F0000 // Data timeout counter value and
\r
1542 // busy timeout. This value
\r
1543 // determines the interval by which
\r
1544 // DAT lines timeouts are detected.
\r
1545 // The host driver needs to set this
\r
1546 // bitfield based on - the maximum
\r
1547 // read access time (NAC) (Refer to
\r
1548 // the SD Specification Part1
\r
1549 // Physical Layer) - the data read
\r
1550 // access time values (TAAC and
\r
1551 // NSAC) in the card specific data
\r
1552 // register (CSD) of the card - the
\r
1553 // timeout clock base frequency
\r
1554 // (MMCHS_CAPA[TCF]). If the card
\r
1555 // does not respond within the
\r
1556 // specified number of cycles a data
\r
1557 // timeout error occurs
\r
1558 // (MMCHS_STA[DTO]). The
\r
1559 // MMCHS_SYSCTL[DTO] register is
\r
1560 // also used to check busy duration
\r
1561 // to generate busy timeout for
\r
1562 // commands with busy response or
\r
1563 // for busy programming during a
\r
1564 // write command. Timeout on CRC
\r
1565 // status is generated if no CRC
\r
1566 // token is present after a block
\r
1567 // write. 0x0 TCF x 2^13 0x1 TCF x
\r
1568 // 2^14 0xE TCF x 2^27 0xF Reserved
\r
1569 #define MMCHS_SYSCTL_DTO_S 16
\r
1570 #define MMCHS_SYSCTL_CLKD_M 0x0000FFC0 // Clock frequency select These
\r
1571 // bits define the ratio between a
\r
1572 // reference clock frequency (system
\r
1573 // dependant) and the output clock
\r
1574 // frequency on the CLK pin of
\r
1575 // either the memory card (MMC SD or
\r
1576 // SDIO). 0x000 Clock Ref bypass
\r
1577 // 0x001 Clock Ref bypass 0x002
\r
1578 // Clock Ref / 2 0x003 Clock Ref / 3
\r
1579 // 0x3FF Clock Ref / 1023
\r
1580 #define MMCHS_SYSCTL_CLKD_S 6
\r
1581 #define MMCHS_SYSCTL_CEN 0x00000004 // Clock enable This bit controls
\r
1582 // if the clock is provided to the
\r
1583 // card or not. 0 The clock is not
\r
1584 // provided to the card . Clock
\r
1585 // frequency can be changed . 1 The
\r
1586 // clock is provided to the card and
\r
1587 // can be automatically gated when
\r
1588 // MMCHS_SYSCONFIG[AUTOIDLE] is set
\r
1589 // to 1 (default value) . The host
\r
1590 // driver shall wait to set this bit
\r
1591 // to 1 until the Internal clock is
\r
1592 // stable (MMCHS_SYSCTL[ICS]).
\r
1593 #define MMCHS_SYSCTL_ICS 0x00000002
\r
1594 #define MMCHS_SYSCTL_ICE 0x00000001 // Internal clock enable This
\r
1595 // register controls the internal
\r
1596 // clock activity. In very low power
\r
1597 // state the internal clock is
\r
1598 // stopped. Note: The activity of
\r
1599 // the debounce clock (used for
\r
1600 // wakeup events) and the OCP clock
\r
1601 // (used for reads and writes to the
\r
1602 // module register map) are not
\r
1603 // affected by this register. 0 The
\r
1604 // internal clock is stopped (very
\r
1605 // low power state). 1 The internal
\r
1606 // clock oscillates and can be
\r
1607 // automatically gated when
\r
1608 // MMCHS_SYSCONFIG[AUTOIDLE] is set
\r
1609 // to 1 (default value) .
\r
1610 //******************************************************************************
\r
1612 // The following are defines for the bit fields in the MMCHS_O_STAT register.
\r
1614 //******************************************************************************
\r
1615 #define MMCHS_STAT_BADA 0x20000000
\r
1616 #define MMCHS_STAT_CERR 0x10000000
\r
1617 #define MMCHS_STAT_ADMAE 0x02000000
\r
1618 #define MMCHS_STAT_ACE 0x01000000
\r
1619 #define MMCHS_STAT_DEB 0x00400000
\r
1620 #define MMCHS_STAT_DCRC 0x00200000
\r
1621 #define MMCHS_STAT_DTO 0x00100000
\r
1622 #define MMCHS_STAT_CIE 0x00080000
\r
1623 #define MMCHS_STAT_CEB 0x00040000
\r
1624 #define MMCHS_STAT_CCRC 0x00020000
\r
1625 #define MMCHS_STAT_CTO 0x00010000
\r
1626 #define MMCHS_STAT_ERRI 0x00008000
\r
1627 #define MMCHS_STAT_BSR 0x00000400
\r
1628 #define MMCHS_STAT_OBI 0x00000200
\r
1629 #define MMCHS_STAT_CIRQ 0x00000100
\r
1630 #define MMCHS_STAT_CREM 0x00000080
\r
1631 #define MMCHS_STAT_CINS 0x00000040
\r
1632 #define MMCHS_STAT_BRR 0x00000020
\r
1633 #define MMCHS_STAT_BWR 0x00000010
\r
1634 #define MMCHS_STAT_DMA 0x00000008
\r
1635 #define MMCHS_STAT_BGE 0x00000004
\r
1636 #define MMCHS_STAT_TC 0x00000002
\r
1637 #define MMCHS_STAT_CC 0x00000001
\r
1638 //******************************************************************************
\r
1640 // The following are defines for the bit fields in the MMCHS_O_IE register.
\r
1642 //******************************************************************************
\r
1643 #define MMCHS_IE_BADA_ENABLE 0x20000000 // Bad access to data space
\r
1644 // Interrupt Enable 0 Masked 1
\r
1646 #define MMCHS_IE_CERR_ENABLE 0x10000000 // Card error interrupt Enable 0
\r
1647 // Masked 1 Enabled
\r
1648 #define MMCHS_IE_ADMAE_ENABLE 0x02000000 // ADMA error Interrupt Enable 0
\r
1649 // Masked 1 Enabled
\r
1650 #define MMCHS_IE_ACE_ENABLE 0x01000000 // Auto CMD12 error Interrupt
\r
1651 // Enable 0 Masked 1 Enabled
\r
1652 #define MMCHS_IE_DEB_ENABLE 0x00400000 // Data end bit error Interrupt
\r
1653 // Enable 0 Masked 1 Enabled
\r
1654 #define MMCHS_IE_DCRC_ENABLE 0x00200000 // Data CRC error Interrupt Enable
\r
1655 // 0 Masked 1 Enabled
\r
1656 #define MMCHS_IE_DTO_ENABLE 0x00100000 // Data timeout error Interrupt
\r
1657 // Enable 0 The data timeout
\r
1658 // detection is deactivated. The
\r
1659 // host controller provides the
\r
1660 // clock to the card until the card
\r
1661 // sends the data or the transfer is
\r
1662 // aborted. 1 The data timeout
\r
1663 // detection is enabled.
\r
1664 #define MMCHS_IE_CIE_ENABLE 0x00080000 // Command index error Interrupt
\r
1665 // Enable 0 Masked 1 Enabled
\r
1666 #define MMCHS_IE_CEB_ENABLE 0x00040000 // Command end bit error Interrupt
\r
1667 // Enable 0 Masked 1 Enabled
\r
1668 #define MMCHS_IE_CCRC_ENABLE 0x00020000 // Command CRC error Interrupt
\r
1669 // Enable 0 Masked 1 Enabled
\r
1670 #define MMCHS_IE_CTO_ENABLE 0x00010000 // Command timeout error Interrupt
\r
1671 // Enable 0 Masked 1 Enabled
\r
1672 #define MMCHS_IE_NULL 0x00008000 // Fixed to 0 The host driver shall
\r
1673 // control error interrupts using
\r
1674 // the Error Interrupt Signal Enable
\r
1675 // register. Writes to this bit are
\r
1677 #define MMCHS_IE_BSR_ENABLE 0x00000400 // Boot status interrupt Enable A
\r
1678 // write to this register when
\r
1679 // MMCHS_CON[BOOT_ACK] is set to 0x0
\r
1680 // is ignored. 0 Masked 1 Enabled
\r
1681 #define MMCHS_IE_OBI_ENABLE 0x00000200 // Out-of-Band interrupt Enable A
\r
1682 // write to this register when
\r
1683 // MMCHS_CON[OBIE] is set to '0' is
\r
1684 // ignored. 0 Masked 1 Enabled
\r
1685 #define MMCHS_IE_CIRQ_ENABLE 0x00000100 // Card interrupt Enable A clear of
\r
1686 // this bit also clears the
\r
1687 // corresponding status bit. During
\r
1688 // 1-bit mode if the interrupt
\r
1689 // routine doesn't remove the source
\r
1690 // of a card interrupt in the SDIO
\r
1691 // card the status bit is reasserted
\r
1692 // when this bit is set to 1. 0
\r
1693 // Masked 1 Enabled
\r
1694 #define MMCHS_IE_CREM_ENABLE 0x00000080 // Card removal Interrupt Enable 0
\r
1695 // Masked 1 Enabled
\r
1696 #define MMCHS_IE_CINS_ENABLE 0x00000040 // Card insertion Interrupt Enable
\r
1697 // 0 Masked 1 Enabled
\r
1698 #define MMCHS_IE_BRR_ENABLE 0x00000020 // Buffer Read Ready Interrupt
\r
1699 // Enable 0 Masked 1 Enabled
\r
1700 #define MMCHS_IE_BWR_ENABLE 0x00000010 // Buffer Write Ready Interrupt
\r
1701 // Enable 0 Masked 1 Enabled
\r
1702 #define MMCHS_IE_DMA_ENABLE 0x00000008 // DMA interrupt Enable 0 Masked 1
\r
1704 #define MMCHS_IE_BGE_ENABLE 0x00000004 // Block Gap Event Interrupt Enable
\r
1705 // 0 Masked 1 Enabled
\r
1706 #define MMCHS_IE_TC_ENABLE 0x00000002 // Transfer completed Interrupt
\r
1707 // Enable 0 Masked 1 Enabled
\r
1708 #define MMCHS_IE_CC_ENABLE 0x00000001 // Command completed Interrupt
\r
1709 // Enable 0 Masked 1 Enabled
\r
1710 //******************************************************************************
\r
1712 // The following are defines for the bit fields in the MMCHS_O_ISE register.
\r
1714 //******************************************************************************
\r
1715 #define MMCHS_ISE_BADA_SIGEN 0x20000000 // Bad access to data space signal
\r
1716 // status Enable 0 Masked 1 Enabled
\r
1717 #define MMCHS_ISE_CERR_SIGEN 0x10000000 // Card error interrupt signal
\r
1718 // status Enable 0 Masked 1 Enabled
\r
1719 #define MMCHS_ISE_ADMAE_SIGEN 0x02000000 // ADMA error signal status Enable
\r
1720 // 0 Masked 1 Enabled
\r
1721 #define MMCHS_ISE_ACE_SIGEN 0x01000000 // Auto CMD12 error signal status
\r
1722 // Enable 0 Masked 1 Enabled
\r
1723 #define MMCHS_ISE_DEB_SIGEN 0x00400000 // Data end bit error signal status
\r
1724 // Enable 0 Masked 1 Enabled
\r
1725 #define MMCHS_ISE_DCRC_SIGEN 0x00200000 // Data CRC error signal status
\r
1726 // Enable 0 Masked 1 Enabled
\r
1727 #define MMCHS_ISE_DTO_SIGEN 0x00100000 // Data timeout error signal status
\r
1728 // Enable 0 Masked 1 Enabled
\r
1729 #define MMCHS_ISE_CIE_SIGEN 0x00080000 // Command index error signal
\r
1730 // status Enable 0 Masked 1 Enabled
\r
1731 #define MMCHS_ISE_CEB_SIGEN 0x00040000 // Command end bit error signal
\r
1732 // status Enable 0 Masked 1 Enabled
\r
1733 #define MMCHS_ISE_CCRC_SIGEN 0x00020000 // Command CRC error signal status
\r
1734 // Enable 0 Masked 1 Enabled
\r
1735 #define MMCHS_ISE_CTO_SIGEN 0x00010000 // Command timeout error signal
\r
1736 // status Enable 0 Masked 1 Enabled
\r
1737 #define MMCHS_ISE_NULL 0x00008000 // Fixed to 0 The host driver shall
\r
1738 // control error interrupts using
\r
1739 // the Error Interrupt Signal Enable
\r
1740 // register. Writes to this bit are
\r
1742 #define MMCHS_ISE_BSR_SIGEN 0x00000400 // Boot status signal status
\r
1743 // EnableA write to this register
\r
1744 // when MMCHS_CON[BOOT_ACK] is set
\r
1745 // to 0x0 is ignored. 0 Masked 1
\r
1747 #define MMCHS_ISE_OBI_SIGEN 0x00000200 // Out-Of-Band Interrupt signal
\r
1748 // status Enable A write to this
\r
1749 // register when MMCHS_CON[OBIE] is
\r
1750 // set to '0' is ignored. 0 Masked 1
\r
1752 #define MMCHS_ISE_CIRQ_SIGEN 0x00000100 // Card interrupt signal status
\r
1753 // Enable 0 Masked 1 Enabled
\r
1754 #define MMCHS_ISE_CREM_SIGEN 0x00000080 // Card removal signal status
\r
1755 // Enable 0 Masked 1 Enabled
\r
1756 #define MMCHS_ISE_CINS_SIGEN 0x00000040 // Card insertion signal status
\r
1757 // Enable 0 Masked 1 Enabled
\r
1758 #define MMCHS_ISE_BRR_SIGEN 0x00000020 // Buffer Read Ready signal status
\r
1759 // Enable 0 Masked 1 Enabled
\r
1760 #define MMCHS_ISE_BWR_SIGEN 0x00000010 // Buffer Write Ready signal status
\r
1761 // Enable 0 Masked 1 Enabled
\r
1762 #define MMCHS_ISE_DMA_SIGEN 0x00000008 // DMA interrupt Signal status
\r
1763 // enable 0 Masked 1 Enabled
\r
1764 #define MMCHS_ISE_BGE_SIGEN 0x00000004 // Black Gap Event signal status
\r
1765 // Enable 0 Masked 1 Enabled
\r
1766 #define MMCHS_ISE_TC_SIGEN 0x00000002 // Transfer completed signal status
\r
1767 // Enable 0 Masked 1 Enabled
\r
1768 #define MMCHS_ISE_CC_SIGEN 0x00000001 // Command completed signal status
\r
1769 // Enable 0 Masked 1 Enabled
\r
1770 //******************************************************************************
\r
1772 // The following are defines for the bit fields in the MMCHS_O_AC12 register.
\r
1774 //******************************************************************************
\r
1775 #define MMCHS_AC12_CNI 0x00000080
\r
1776 #define MMCHS_AC12_ACIE 0x00000010
\r
1777 #define MMCHS_AC12_ACEB 0x00000008
\r
1778 #define MMCHS_AC12_ACCE 0x00000004
\r
1779 #define MMCHS_AC12_ACTO 0x00000002
\r
1780 #define MMCHS_AC12_ACNE 0x00000001
\r
1781 //******************************************************************************
\r
1783 // The following are defines for the bit fields in the MMCHS_O_CAPA register.
\r
1785 //******************************************************************************
\r
1786 #define MMCHS_CAPA_BIT64 0x10000000
\r
1787 #define MMCHS_CAPA_VS18 0x04000000
\r
1788 #define MMCHS_CAPA_VS30 0x02000000
\r
1789 #define MMCHS_CAPA_VS33 0x01000000
\r
1790 #define MMCHS_CAPA_SRS 0x00800000
\r
1791 #define MMCHS_CAPA_DS 0x00400000
\r
1792 #define MMCHS_CAPA_HSS 0x00200000
\r
1793 #define MMCHS_CAPA_AD2S 0x00080000
\r
1794 #define MMCHS_CAPA_MBL_M 0x00030000
\r
1795 #define MMCHS_CAPA_MBL_S 16
\r
1796 #define MMCHS_CAPA_BCF_M 0x00003F00
\r
1797 #define MMCHS_CAPA_BCF_S 8
\r
1798 #define MMCHS_CAPA_TCU 0x00000080
\r
1799 #define MMCHS_CAPA_TCF_M 0x0000003F
\r
1800 #define MMCHS_CAPA_TCF_S 0
\r
1801 //******************************************************************************
\r
1803 // The following are defines for the bit fields in the MMCHS_O_CUR_CAPA register.
\r
1805 //******************************************************************************
\r
1806 #define MMCHS_CUR_CAPA_CUR_1V8_M \
\r
1809 #define MMCHS_CUR_CAPA_CUR_1V8_S 16
\r
1810 #define MMCHS_CUR_CAPA_CUR_3V0_M \
\r
1813 #define MMCHS_CUR_CAPA_CUR_3V0_S 8
\r
1814 #define MMCHS_CUR_CAPA_CUR_3V3_M \
\r
1817 #define MMCHS_CUR_CAPA_CUR_3V3_S 0
\r
1818 //******************************************************************************
\r
1820 // The following are defines for the bit fields in the MMCHS_O_FE register.
\r
1822 //******************************************************************************
\r
1823 #define MMCHS_FE_FE_BADA 0x20000000
\r
1824 #define MMCHS_FE_FE_CERR 0x10000000
\r
1825 #define MMCHS_FE_FE_ADMAE 0x02000000
\r
1826 #define MMCHS_FE_FE_ACE 0x01000000
\r
1827 #define MMCHS_FE_FE_DEB 0x00400000
\r
1828 #define MMCHS_FE_FE_DCRC 0x00200000
\r
1829 #define MMCHS_FE_FE_DTO 0x00100000
\r
1830 #define MMCHS_FE_FE_CIE 0x00080000
\r
1831 #define MMCHS_FE_FE_CEB 0x00040000
\r
1832 #define MMCHS_FE_FE_CCRC 0x00020000
\r
1833 #define MMCHS_FE_FE_CTO 0x00010000
\r
1834 #define MMCHS_FE_FE_CNI 0x00000080
\r
1835 #define MMCHS_FE_FE_ACIE 0x00000010
\r
1836 #define MMCHS_FE_FE_ACEB 0x00000008
\r
1837 #define MMCHS_FE_FE_ACCE 0x00000004
\r
1838 #define MMCHS_FE_FE_ACTO 0x00000002
\r
1839 #define MMCHS_FE_FE_ACNE 0x00000001
\r
1840 //******************************************************************************
\r
1842 // The following are defines for the bit fields in the MMCHS_O_ADMAES register.
\r
1844 //******************************************************************************
\r
1845 #define MMCHS_ADMAES_LME 0x00000004 // ADMA Length Mismatch Error: (1)
\r
1846 // While Block Count Enable being
\r
1847 // set the total data length
\r
1848 // specified by the Descriptor table
\r
1849 // is different from that specified
\r
1850 // by the Block Count and Block
\r
1851 // Length. (2) Total data length can
\r
1852 // not be divided by the block
\r
1853 // length. 0 No Error 1 Error
\r
1854 #define MMCHS_ADMAES_AES_M 0x00000003 // ADMA Error State his field
\r
1855 // indicates the state of ADMA when
\r
1856 // error is occurred during ADMA
\r
1857 // data transfer. "This field never
\r
1858 // indicates ""10"" because ADMA
\r
1859 // never stops in this state." 0x0
\r
1860 // ST_STOP (Stop DMA)Contents of
\r
1861 // SYS_SDR register 0x1 ST_STOP
\r
1862 // (Stop DMA)Points the error
\r
1863 // descriptor 0x2 Never set this
\r
1864 // state(Not used) 0x3 ST_TFR
\r
1865 // (Transfer Data)Points the next of
\r
1866 // the error descriptor
\r
1867 #define MMCHS_ADMAES_AES_S 0
\r
1868 //******************************************************************************
\r
1870 // The following are defines for the bit fields in the MMCHS_O_ADMASAL register.
\r
1872 //******************************************************************************
\r
1873 #define MMCHS_ADMASAL_ADMA_A32B_M \
\r
1874 0xFFFFFFFF // ADMA System address 32 bits.This
\r
1875 // register holds byte address of
\r
1876 // executing command of the
\r
1877 // Descriptor table. 32-bit Address
\r
1878 // Descriptor uses lower 32-bit of
\r
1879 // this register. At the start of
\r
1880 // ADMA the Host Driver shall set
\r
1881 // start address of the Descriptor
\r
1882 // table. The ADMA increments this
\r
1883 // register address which points to
\r
1884 // next line when every fetching a
\r
1885 // Descriptor line. When the ADMA
\r
1886 // Error Interrupt is generated this
\r
1887 // register shall hold valid
\r
1888 // Descriptor address depending on
\r
1889 // the ADMA state. The Host Driver
\r
1890 // shall program Descriptor Table on
\r
1891 // 32-bit boundary and set 32-bit
\r
1892 // boundary address to this
\r
1893 // register. ADMA2 ignores lower
\r
1894 // 2-bit of this register and
\r
1895 // assumes it to be 00b.
\r
1897 #define MMCHS_ADMASAL_ADMA_A32B_S 0
\r
1898 //******************************************************************************
\r
1900 // The following are defines for the bit fields in the MMCHS_O_REV register.
\r
1902 //******************************************************************************
\r
1903 #define MMCHS_REV_VREV_M 0xFF000000 // Vendor Version Number: IP
\r
1904 // revision [7:4] Major revision
\r
1905 // [3:0] Minor revision Examples:
\r
1906 // 0x10 for 1.0 0x21 for 2.1
\r
1907 #define MMCHS_REV_VREV_S 24
\r
1908 #define MMCHS_REV_SREV_M 0x00FF0000
\r
1909 #define MMCHS_REV_SREV_S 16
\r
1910 #define MMCHS_REV_SIS 0x00000001 // Slot Interrupt Status This
\r
1911 // status bit indicates the inverted
\r
1912 // state of interrupt signal for the
\r
1913 // module. By a power on reset or by
\r
1914 // setting a software reset for all
\r
1915 // (MMCHS_HCTL[SRA]) the interrupt
\r
1916 // signal shall be de-asserted and
\r
1917 // this status shall read 0.
\r
1921 #endif // __HW_MMCHS_H__
\r
projects / freertos / blob