2 * -------------------------------------------
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3 * CC3220 SDK - v0.10.00.00
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4 * -------------------------------------------
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6 * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/
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8 * Redistribution and use in source and binary forms, with or without
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9 * modification, are permitted provided that the following conditions
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12 * Redistributions of source code must retain the above copyright
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13 * notice, this list of conditions and the following disclaimer.
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15 * Redistributions in binary form must reproduce the above copyright
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16 * notice, this list of conditions and the following disclaimer in the
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17 * documentation and/or other materials provided with the
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20 * Neither the name of Texas Instruments Incorporated nor the names of
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21 * its contributors may be used to endorse or promote products derived
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22 * from this software without specific prior written permission.
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24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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25 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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26 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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27 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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28 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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29 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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30 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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31 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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32 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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33 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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34 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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38 #ifndef __HW_SHAMD5_H__
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39 #define __HW_SHAMD5_H__
\r
41 //*****************************************************************************
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43 // The following are defines for the SHAMD5_P register offsets.
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45 //*****************************************************************************
\r
46 #define SHAMD5_O_ODIGEST_A 0x00000000 // WRITE: Outer Digest [127:96] for
\r
47 // MD5 [159:128] for SHA-1 [255:224]
\r
48 // for SHA-2 / HMAC Key [31:0] for
\r
49 // HMAC key proc READ: Outer Digest
\r
50 // [127:96] for MD5 [159:128] for
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51 // SHA-1 [255:224] for SHA-2
\r
52 #define SHAMD5_O_ODIGEST_B 0x00000004 // WRITE: Outer Digest [95:64] for
\r
53 // MD5 [127:96] for SHA-1 [223:192]
\r
54 // for SHA-2 / HMAC Key [63:32] for
\r
55 // HMAC key proc READ: Outer Digest
\r
56 // [95:64] for MD5 [127:96] for
\r
57 // SHA-1 [223:192] for SHA-2
\r
58 #define SHAMD5_O_ODIGEST_C 0x00000008 // WRITE: Outer Digest [63:32] for
\r
59 // MD5 [95:64] for SHA-1 [191:160]
\r
60 // for SHA-2 / HMAC Key [95:64] for
\r
61 // HMAC key proc READ: Outer Digest
\r
62 // [63:32] for MD5 [95:64] for SHA-1
\r
63 // [191:160] for SHA-2
\r
64 #define SHAMD5_O_ODIGEST_D 0x0000000C // WRITE: Outer Digest [31:0] for
\r
65 // MD5 [63:31] for SHA-1 [159:128]
\r
66 // for SHA-2 / HMAC Key [127:96] for
\r
67 // HMAC key proc READ: Outer Digest
\r
68 // [31:0] for MD5 [63:32] for SHA-1
\r
69 // [159:128] for SHA-2
\r
70 #define SHAMD5_O_ODIGEST_E 0x00000010 // WRITE: Outer Digest [31:0] for
\r
71 // SHA-1 [127:96] for SHA-2 / HMAC
\r
72 // Key [159:128] for HMAC key proc
\r
73 // READ: Outer Digest [31:0] for
\r
74 // SHA-1 [127:96] for SHA-2
\r
75 #define SHAMD5_O_ODIGEST_F 0x00000014 // WRITE: Outer Digest [95:64] for
\r
76 // SHA-2 / HMAC Key [191:160] for
\r
77 // HMAC key proc READ: Outer Digest
\r
78 // [95:64] for SHA-2
\r
79 #define SHAMD5_O_ODIGEST_G 0x00000018 // WRITE: Outer Digest [63:32] for
\r
80 // SHA-2 / HMAC Key [223:192] for
\r
81 // HMAC key proc READ: Outer Digest
\r
82 // [63:32] for SHA-2
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83 #define SHAMD5_O_ODIGEST_H 0x0000001C // WRITE: Outer Digest [31:0] for
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84 // SHA-2 / HMAC Key [255:224] for
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85 // HMAC key proc READ: Outer Digest
\r
87 #define SHAMD5_O_IDIGEST_A 0x00000020 // WRITE: Inner / Initial Digest
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88 // [127:96] for MD5 [159:128] for
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89 // SHA-1 [255:224] for SHA-2 / HMAC
\r
90 // Key [287:256] for HMAC key proc
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91 // READ: Intermediate / Inner Digest
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92 // [127:96] for MD5 [159:128] for
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93 // SHA-1 [255:224] for SHA-2 /
\r
94 // Result Digest/MAC [127:96] for
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95 // MD5 [159:128] for SHA-1 [223:192]
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96 // for SHA-2 224 [255:224] for SHA-2
\r
98 #define SHAMD5_O_IDIGEST_B 0x00000024 // WRITE: Inner / Initial Digest
\r
99 // [95:64] for MD5 [127:96] for
\r
100 // SHA-1 [223:192] for SHA-2 / HMAC
\r
101 // Key [319:288] for HMAC key proc
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102 // READ: Intermediate / Inner Digest
\r
103 // [95:64] for MD5 [127:96] for
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104 // SHA-1 [223:192] for SHA-2 /
\r
105 // Result Digest/MAC [95:64] for MD5
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106 // [127:96] for SHA-1 [191:160] for
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107 // SHA-2 224 [223:192] for SHA-2 256
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108 #define SHAMD5_O_IDIGEST_C 0x00000028 // WRITE: Inner / Initial Digest
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109 // [63:32] for MD5 [95:64] for SHA-1
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110 // [191:160] for SHA- 2 / HMAC Key
\r
111 // [351:320] for HMAC key proc READ:
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112 // Intermediate / Inner Digest
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113 // [63:32] for MD5 [95:64] for SHA-1
\r
114 // [191:160] for SHA-2 / Result
\r
115 // Digest/MAC [63:32] for MD5
\r
116 // [95:64] for SHA-1 [159:128] for
\r
117 // SHA-2 224 [191:160] for SHA-2 256
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118 #define SHAMD5_O_IDIGEST_D 0x0000002C // WRITE: Inner / Initial Digest
\r
119 // [31:0] for MD5 [63:32] for SHA-1
\r
120 // [159:128] for SHA-2 / HMAC Key
\r
121 // [383:352] for HMAC key proc READ:
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122 // Intermediate / Inner Digest
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123 // [31:0] for MD5 [63:32] for SHA-1
\r
124 // [159:128] for SHA-2 / Result
\r
125 // Digest/MAC [31:0] for MD5 [63:32]
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126 // for SHA-1 [127:96] for SHA-2 224
\r
127 // [159:128] for SHA-2 256
\r
128 #define SHAMD5_O_IDIGEST_E 0x00000030 // WRITE: Inner / Initial Digest
\r
129 // [31:0] for SHA-1 [127:96] for
\r
130 // SHA-2 / HMAC Key [415:384] for
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131 // HMAC key proc READ: Intermediate
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132 // / Inner Digest [31:0] for SHA-1
\r
133 // [127:96] for SHA-2 / Result
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134 // Digest/MAC [31:0] for SHA-1
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135 // [95:64] for SHA-2 224 [127:96]
\r
137 #define SHAMD5_O_IDIGEST_F 0x00000034 // WRITE: Inner / Initial Digest
\r
138 // [95:64] for SHA-2 / HMAC Key
\r
139 // [447:416] for HMAC key proc READ:
\r
140 // Intermediate / Inner Digest
\r
141 // [95:64] for SHA-2 / Result
\r
142 // Digest/MAC [63:32] for SHA-2 224
\r
143 // [95:64] for SHA-2 256
\r
144 #define SHAMD5_O_IDIGEST_G 0x00000038 // WRITE: Inner / Initial Digest
\r
145 // [63:32] for SHA-2 / HMAC Key
\r
146 // [479:448] for HMAC key proc READ:
\r
147 // Intermediate / Inner Digest
\r
148 // [63:32] for SHA-2 / Result
\r
149 // Digest/MAC [31:0] for SHA-2 224
\r
150 // [63:32] for SHA-2 256
\r
151 #define SHAMD5_O_IDIGEST_H 0x0000003C // WRITE: Inner / Initial Digest
\r
152 // [31:0] for SHA-2 / HMAC Key
\r
153 // [511:480] for HMAC key proc READ:
\r
154 // Intermediate / Inner Digest
\r
155 // [31:0] for SHA-2 / Result
\r
156 // Digest/MAC [31:0] for SHA-2 256
\r
157 #define SHAMD5_O_DIGEST_COUNT 0x00000040 // WRITE: Initial Digest Count
\r
158 // ([31:6] only [5:0] assumed 0)
\r
159 // READ: Result / IntermediateDigest
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160 // Count The initial digest byte
\r
161 // count for hash/HMAC continue
\r
162 // operations (HMAC Key Processing =
\r
163 // 0 and Use Algorithm Constants =
\r
164 // 0) on the Secure World must be
\r
165 // written to this register prior to
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166 // starting the operation by writing
\r
167 // to S_HASH_MODE. When either HMAC
\r
168 // Key Processing is 1 or Use
\r
169 // Algorithm Constants is 1 this
\r
170 // register does not need to be
\r
171 // written it will be overwritten
\r
172 // with 64 (1 hash block of key XOR
\r
173 // ipad) or 0 respectively
\r
174 // automatically. When starting a
\r
175 // HMAC operation from pre-computes
\r
176 // (HMAC Key Processing is 0) then
\r
177 // the value 64 must be written here
\r
178 // to compensate for the appended
\r
179 // key XOR ipad block. Note that the
\r
180 // value written should always be a
\r
181 // 64 byte multiple the lower 6 bits
\r
182 // written are ignored. The updated
\r
183 // digest byte count (initial digest
\r
184 // byte count + bytes processed) can
\r
185 // be read from this register when
\r
186 // the status register indicates
\r
187 // that the operation is done or
\r
188 // suspended due to a context switch
\r
189 // request or when a Secure World
\r
190 // context out DMA is requested. In
\r
191 // Advanced DMA mode when not
\r
192 // suspended with a partial result
\r
193 // reading the SHAMD5_DIGEST_COUNT
\r
194 // register triggers the Hash/HMAC
\r
195 // Engine to start the next context
\r
196 // input DMA. Therefore reading the
\r
197 // SHAMD5_DIGEST_COUNT register
\r
198 // should always be the last
\r
199 // context-read action if not
\r
200 // suspended with a partial result
\r
201 // (i.e. PartHashReady interrupt not
\r
203 #define SHAMD5_O_MODE 0x00000044 // Register SHAMD5_MODE
\r
204 #define SHAMD5_O_LENGTH 0x00000048 // WRITE: Block Length / Remaining
\r
205 // Byte Count (bytes) READ:
\r
206 // Remaining Byte Count. The value
\r
207 // programmed MUST be a 64-byte
\r
208 // multiple if Close Hash is set to
\r
209 // 0. This register is also the
\r
210 // trigger to start processing: once
\r
211 // this register is written the core
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212 // will commence requesting input
\r
213 // data via DMA or IRQ (if
\r
214 // programmed length > 0) and start
\r
215 // processing. The remaining byte
\r
216 // count for the active operation
\r
217 // can be read from this register
\r
218 // when the interrupt status
\r
219 // register indicates that the
\r
220 // operation is suspended due to a
\r
221 // context switch request.
\r
222 #define SHAMD5_O_DATA0_IN 0x00000080 // Data input message 0
\r
223 #define SHAMD5_O_DATA1_IN 0x00000084 // Data input message 1
\r
224 #define SHAMD5_O_DATA2_IN 0x00000088 // Data input message 2
\r
225 #define SHAMD5_O_DATA3_IN 0x0000008C // Data input message 3
\r
226 #define SHAMD5_O_DATA4_IN 0x00000090 // Data input message 4
\r
227 #define SHAMD5_O_DATA5_IN 0x00000094 // Data input message 5
\r
228 #define SHAMD5_O_DATA6_IN 0x00000098 // Data input message 6
\r
229 #define SHAMD5_O_DATA7_IN 0x0000009C // Data input message 7
\r
230 #define SHAMD5_O_DATA8_IN 0x000000A0 // Data input message 8
\r
231 #define SHAMD5_O_DATA9_IN 0x000000A4 // Data input message 9
\r
232 #define SHAMD5_O_DATA10_IN 0x000000A8 // Data input message 10
\r
233 #define SHAMD5_O_DATA11_IN 0x000000AC // Data input message 11
\r
234 #define SHAMD5_O_DATA12_IN 0x000000B0 // Data input message 12
\r
235 #define SHAMD5_O_DATA13_IN 0x000000B4 // Data input message 13
\r
236 #define SHAMD5_O_DATA14_IN 0x000000B8 // Data input message 14
\r
237 #define SHAMD5_O_DATA15_IN 0x000000BC // Data input message 15
\r
238 #define SHAMD5_O_REVISION 0x00000100 // Register SHAMD5_REV
\r
239 #define SHAMD5_O_SYSCONFIG 0x00000110 // Register SHAMD5_SYSCONFIG
\r
240 #define SHAMD5_O_SYSSTATUS 0x00000114 // Register SHAMD5_SYSSTATUS
\r
241 #define SHAMD5_O_IRQSTATUS 0x00000118 // Register SHAMD5_IRQSTATUS
\r
242 #define SHAMD5_O_IRQENABLE 0x0000011C // Register SHAMD5_IRQENABLE. The
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243 // SHAMD5_IRQENABLE register contains
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244 // an enable bit for each unique
\r
245 // interrupt for the public side. An
\r
246 // interrupt is enabled when both
\r
247 // the global enable in
\r
248 // SHAMD5_SYSCONFIG (PIT_en) and the
\r
249 // bit in this register are both set
\r
250 // to 1. An interrupt that is
\r
251 // enabled is propagated to the
\r
252 // SINTREQUEST_P output. Please note
\r
253 // that the dedicated partial hash
\r
254 // output (SINTREQUEST_PART_P) is
\r
255 // not affected by this register it
\r
256 // is only affected by the global
\r
257 // enable SHAMD5_SYSCONFIG (PIT_en).
\r
258 #define SHAMD5_O_HASH512_ODIGEST_A \
\r
261 #define SHAMD5_O_HASH512_ODIGEST_B \
\r
264 #define SHAMD5_O_HASH512_ODIGEST_C \
\r
267 #define SHAMD5_O_HASH512_ODIGEST_D \
\r
270 #define SHAMD5_O_HASH512_ODIGEST_E \
\r
273 #define SHAMD5_O_HASH512_ODIGEST_F \
\r
276 #define SHAMD5_O_HASH512_ODIGEST_G \
\r
279 #define SHAMD5_O_HASH512_ODIGEST_H \
\r
282 #define SHAMD5_O_HASH512_ODIGEST_I \
\r
285 #define SHAMD5_O_HASH512_ODIGEST_J \
\r
288 #define SHAMD5_O_HASH512_ODIGEST_K \
\r
291 #define SHAMD5_O_HASH512_ODIGEST_L \
\r
294 #define SHAMD5_O_HASH512_ODIGEST_M \
\r
297 #define SHAMD5_O_HASH512_ODIGEST_N \
\r
300 #define SHAMD5_O_HASH512_ODIGEST_O \
\r
303 #define SHAMD5_O_HASH512_ODIGEST_P \
\r
306 #define SHAMD5_O_HASH512_IDIGEST_A \
\r
309 #define SHAMD5_O_HASH512_IDIGEST_B \
\r
312 #define SHAMD5_O_HASH512_IDIGEST_C \
\r
315 #define SHAMD5_O_HASH512_IDIGEST_D \
\r
318 #define SHAMD5_O_HASH512_IDIGEST_E \
\r
321 #define SHAMD5_O_HASH512_IDIGEST_F \
\r
324 #define SHAMD5_O_HASH512_IDIGEST_G \
\r
327 #define SHAMD5_O_HASH512_IDIGEST_H \
\r
330 #define SHAMD5_O_HASH512_IDIGEST_I \
\r
333 #define SHAMD5_O_HASH512_IDIGEST_J \
\r
336 #define SHAMD5_O_HASH512_IDIGEST_K \
\r
339 #define SHAMD5_O_HASH512_IDIGEST_L \
\r
342 #define SHAMD5_O_HASH512_IDIGEST_M \
\r
345 #define SHAMD5_O_HASH512_IDIGEST_N \
\r
348 #define SHAMD5_O_HASH512_IDIGEST_O \
\r
351 #define SHAMD5_O_HASH512_IDIGEST_P \
\r
354 #define SHAMD5_O_HASH512_DIGEST_COUNT \
\r
357 #define SHAMD5_O_HASH512_MODE 0x00000284
\r
358 #define SHAMD5_O_HASH512_LENGTH 0x00000288
\r
362 //******************************************************************************
\r
364 // The following are defines for the bit fields in the SHAMD5_O_ODIGEST_A register.
\r
366 //******************************************************************************
\r
367 #define SHAMD5_ODIGEST_A_DATA_M 0xFFFFFFFF // data
\r
368 #define SHAMD5_ODIGEST_A_DATA_S 0
\r
369 //******************************************************************************
\r
371 // The following are defines for the bit fields in the SHAMD5_O_ODIGEST_B register.
\r
373 //******************************************************************************
\r
374 #define SHAMD5_ODIGEST_B_DATA_M 0xFFFFFFFF // data
\r
375 #define SHAMD5_ODIGEST_B_DATA_S 0
\r
376 //******************************************************************************
\r
378 // The following are defines for the bit fields in the SHAMD5_O_ODIGEST_C register.
\r
380 //******************************************************************************
\r
381 #define SHAMD5_ODIGEST_C_DATA_M 0xFFFFFFFF // data
\r
382 #define SHAMD5_ODIGEST_C_DATA_S 0
\r
383 //******************************************************************************
\r
385 // The following are defines for the bit fields in the SHAMD5_O_ODIGEST_D register.
\r
387 //******************************************************************************
\r
388 #define SHAMD5_ODIGEST_D_DATA_M 0xFFFFFFFF // data
\r
389 #define SHAMD5_ODIGEST_D_DATA_S 0
\r
390 //******************************************************************************
\r
392 // The following are defines for the bit fields in the SHAMD5_O_ODIGEST_E register.
\r
394 //******************************************************************************
\r
395 #define SHAMD5_ODIGEST_E_DATA_M 0xFFFFFFFF // data
\r
396 #define SHAMD5_ODIGEST_E_DATA_S 0
\r
397 //******************************************************************************
\r
399 // The following are defines for the bit fields in the SHAMD5_O_ODIGEST_F register.
\r
401 //******************************************************************************
\r
402 #define SHAMD5_ODIGEST_F_DATA_M 0xFFFFFFFF // data
\r
403 #define SHAMD5_ODIGEST_F_DATA_S 0
\r
404 //******************************************************************************
\r
406 // The following are defines for the bit fields in the SHAMD5_O_ODIGEST_G register.
\r
408 //******************************************************************************
\r
409 #define SHAMD5_ODIGEST_G_DATA_M 0xFFFFFFFF // data
\r
410 #define SHAMD5_ODIGEST_G_DATA_S 0
\r
411 //******************************************************************************
\r
413 // The following are defines for the bit fields in the SHAMD5_O_ODIGEST_H register.
\r
415 //******************************************************************************
\r
416 #define SHAMD5_ODIGEST_H_DATA_M 0xFFFFFFFF // data
\r
417 #define SHAMD5_ODIGEST_H_DATA_S 0
\r
418 //******************************************************************************
\r
420 // The following are defines for the bit fields in the SHAMD5_O_IDIGEST_A register.
\r
422 //******************************************************************************
\r
423 #define SHAMD5_IDIGEST_A_DATA_M 0xFFFFFFFF // data
\r
424 #define SHAMD5_IDIGEST_A_DATA_S 0
\r
425 //******************************************************************************
\r
427 // The following are defines for the bit fields in the SHAMD5_O_IDIGEST_B register.
\r
429 //******************************************************************************
\r
430 #define SHAMD5_IDIGEST_B_DATA_M 0xFFFFFFFF // data
\r
431 #define SHAMD5_IDIGEST_B_DATA_S 0
\r
432 //******************************************************************************
\r
434 // The following are defines for the bit fields in the SHAMD5_O_IDIGEST_C register.
\r
436 //******************************************************************************
\r
437 #define SHAMD5_IDIGEST_C_DATA_M 0xFFFFFFFF // data
\r
438 #define SHAMD5_IDIGEST_C_DATA_S 0
\r
439 //******************************************************************************
\r
441 // The following are defines for the bit fields in the SHAMD5_O_IDIGEST_D register.
\r
443 //******************************************************************************
\r
444 #define SHAMD5_IDIGEST_D_DATA_M 0xFFFFFFFF // data
\r
445 #define SHAMD5_IDIGEST_D_DATA_S 0
\r
446 //******************************************************************************
\r
448 // The following are defines for the bit fields in the SHAMD5_O_IDIGEST_E register.
\r
450 //******************************************************************************
\r
451 #define SHAMD5_IDIGEST_E_DATA_M 0xFFFFFFFF // data
\r
452 #define SHAMD5_IDIGEST_E_DATA_S 0
\r
453 //******************************************************************************
\r
455 // The following are defines for the bit fields in the SHAMD5_O_IDIGEST_F register.
\r
457 //******************************************************************************
\r
458 #define SHAMD5_IDIGEST_F_DATA_M 0xFFFFFFFF // data
\r
459 #define SHAMD5_IDIGEST_F_DATA_S 0
\r
460 //******************************************************************************
\r
462 // The following are defines for the bit fields in the SHAMD5_O_IDIGEST_G register.
\r
464 //******************************************************************************
\r
465 #define SHAMD5_IDIGEST_G_DATA_M 0xFFFFFFFF // data
\r
466 #define SHAMD5_IDIGEST_G_DATA_S 0
\r
467 //******************************************************************************
\r
469 // The following are defines for the bit fields in the SHAMD5_O_IDIGEST_H register.
\r
471 //******************************************************************************
\r
472 #define SHAMD5_IDIGEST_H_DATA_M 0xFFFFFFFF // data
\r
473 #define SHAMD5_IDIGEST_H_DATA_S 0
\r
474 //******************************************************************************
\r
476 // The following are defines for the bit fields in the
\r
477 // SHAMD5_O_DIGEST_COUNT register.
\r
479 //******************************************************************************
\r
480 #define SHAMD5_DIGEST_COUNT_DATA_M \
\r
483 #define SHAMD5_DIGEST_COUNT_DATA_S 0
\r
484 //******************************************************************************
\r
486 // The following are defines for the bit fields in the SHAMD5_O_MODE register.
\r
488 //******************************************************************************
\r
489 #define SHAMD5_MODE_HMAC_OUTER_HASH \
\r
490 0x00000080 // The HMAC Outer Hash is performed
\r
491 // on the hash digest when the inner
\r
492 // hash hash finished (block length
\r
493 // exhausted and final hash
\r
494 // performed if close_hash is 1).
\r
495 // This bit should normally be set
\r
496 // together with close_hash to
\r
497 // finish the inner hash first or
\r
498 // Block Length should be zero (HMAC
\r
499 // continue with the just outer hash
\r
500 // to be done). Auto cleared
\r
501 // internally when outer hash
\r
502 // performed. 0 No operation 1 hmac
\r
505 #define SHAMD5_MODE_HMAC_KEY_PROC \
\r
506 0x00000020 // Performs HMAC key processing on
\r
507 // the 512 bit HMAC key loaded into
\r
508 // the SHAMD5_IDIGEST_{A to H} and
\r
509 // SHAMD5_ODIGEST_{A to H} register
\r
510 // block. Once HMAC key processing
\r
511 // is finished this bit is
\r
512 // automatically cleared and the
\r
513 // resulting Inner and Outer digest
\r
514 // is available from
\r
515 // SHAMD5_IDIGEST_{A to H} and
\r
516 // SHAMD5_ODIGEST_{A to H}
\r
517 // respectively after which regular
\r
518 // hash processing (using
\r
519 // SHAMD5_IDIGEST_{A to H} as initial
\r
520 // digest) will commence until the
\r
521 // Block Length is exhausted. 0 No
\r
522 // operation. 1 Hmac processing.
\r
524 #define SHAMD5_MODE_CLOSE_HASH 0x00000010 // Performs the padding the
\r
525 // hash/HMAC will be 'closed' at the
\r
526 // end of the block as per
\r
527 // MD5/SHA-1/SHA-2 specification
\r
528 // (i.e. appropriate padding is
\r
529 // added) or no padding is done
\r
530 // allowing the hash to be continued
\r
531 // later. However if the hash/HMAC
\r
532 // is not closed then the Block
\r
533 // Length MUST be a multiple of 64
\r
534 // bytes to ensure correct
\r
535 // operation. Auto cleared
\r
536 // internally when hash closed. 0 No
\r
537 // padding hash computation can be
\r
538 // contimued. 1 Last packet will be
\r
540 #define SHAMD5_MODE_ALGO_CONSTANT \
\r
541 0x00000008 // The initial digest register will
\r
542 // be overwritten with the algorithm
\r
543 // constants for the selected
\r
544 // algorithm when hashing and the
\r
545 // initial digest count register
\r
546 // will be reset to 0. This will
\r
547 // start a normal hash operation.
\r
548 // When continuing an existing hash
\r
549 // or when performing an HMAC
\r
550 // operation this register must be
\r
551 // set to 0 and the
\r
552 // intermediate/inner digest or HMAC
\r
553 // key and digest count need to be
\r
554 // written to the context input
\r
555 // registers prior to writing
\r
556 // SHAMD5_MODE. Auto cleared
\r
557 // internally after first block
\r
558 // processed. 0 Use pre-calculated
\r
559 // digest (from an other operation)
\r
560 // 1 Use constants of the selected
\r
563 #define SHAMD5_MODE_ALGO_M 0x00000006 // These bits select the hash
\r
564 // algorithm to be used for
\r
565 // processing: 0x0 md5_128 algorithm
\r
566 // 0x1 sha1_160 algorithm 0x2
\r
567 // sha2_224 algorithm 0x3 sha2_256
\r
569 #define SHAMD5_MODE_ALGO_S 1
\r
570 //******************************************************************************
\r
572 // The following are defines for the bit fields in the SHAMD5_O_LENGTH register.
\r
574 //******************************************************************************
\r
575 #define SHAMD5_LENGTH_DATA_M 0xFFFFFFFF // data
\r
576 #define SHAMD5_LENGTH_DATA_S 0
\r
577 //******************************************************************************
\r
579 // The following are defines for the bit fields in the SHAMD5_O_DATA0_IN register.
\r
581 //******************************************************************************
\r
582 #define SHAMD5_DATA0_IN_DATA0_IN_M \
\r
585 #define SHAMD5_DATA0_IN_DATA0_IN_S 0
\r
586 //******************************************************************************
\r
588 // The following are defines for the bit fields in the SHAMD5_O_DATA1_IN register.
\r
590 //******************************************************************************
\r
591 #define SHAMD5_DATA1_IN_DATA1_IN_M \
\r
594 #define SHAMD5_DATA1_IN_DATA1_IN_S 0
\r
595 //******************************************************************************
\r
597 // The following are defines for the bit fields in the SHAMD5_O_DATA2_IN register.
\r
599 //******************************************************************************
\r
600 #define SHAMD5_DATA2_IN_DATA2_IN_M \
\r
603 #define SHAMD5_DATA2_IN_DATA2_IN_S 0
\r
604 //******************************************************************************
\r
606 // The following are defines for the bit fields in the SHAMD5_O_DATA3_IN register.
\r
608 //******************************************************************************
\r
609 #define SHAMD5_DATA3_IN_DATA3_IN_M \
\r
612 #define SHAMD5_DATA3_IN_DATA3_IN_S 0
\r
613 //******************************************************************************
\r
615 // The following are defines for the bit fields in the SHAMD5_O_DATA4_IN register.
\r
617 //******************************************************************************
\r
618 #define SHAMD5_DATA4_IN_DATA4_IN_M \
\r
621 #define SHAMD5_DATA4_IN_DATA4_IN_S 0
\r
622 //******************************************************************************
\r
624 // The following are defines for the bit fields in the SHAMD5_O_DATA5_IN register.
\r
626 //******************************************************************************
\r
627 #define SHAMD5_DATA5_IN_DATA5_IN_M \
\r
630 #define SHAMD5_DATA5_IN_DATA5_IN_S 0
\r
631 //******************************************************************************
\r
633 // The following are defines for the bit fields in the SHAMD5_O_DATA6_IN register.
\r
635 //******************************************************************************
\r
636 #define SHAMD5_DATA6_IN_DATA6_IN_M \
\r
639 #define SHAMD5_DATA6_IN_DATA6_IN_S 0
\r
640 //******************************************************************************
\r
642 // The following are defines for the bit fields in the SHAMD5_O_DATA7_IN register.
\r
644 //******************************************************************************
\r
645 #define SHAMD5_DATA7_IN_DATA7_IN_M \
\r
648 #define SHAMD5_DATA7_IN_DATA7_IN_S 0
\r
649 //******************************************************************************
\r
651 // The following are defines for the bit fields in the SHAMD5_O_DATA8_IN register.
\r
653 //******************************************************************************
\r
654 #define SHAMD5_DATA8_IN_DATA8_IN_M \
\r
657 #define SHAMD5_DATA8_IN_DATA8_IN_S 0
\r
658 //******************************************************************************
\r
660 // The following are defines for the bit fields in the SHAMD5_O_DATA9_IN register.
\r
662 //******************************************************************************
\r
663 #define SHAMD5_DATA9_IN_DATA9_IN_M \
\r
666 #define SHAMD5_DATA9_IN_DATA9_IN_S 0
\r
667 //******************************************************************************
\r
669 // The following are defines for the bit fields in the SHAMD5_O_DATA10_IN register.
\r
671 //******************************************************************************
\r
672 #define SHAMD5_DATA10_IN_DATA10_IN_M \
\r
675 #define SHAMD5_DATA10_IN_DATA10_IN_S 0
\r
676 //******************************************************************************
\r
678 // The following are defines for the bit fields in the SHAMD5_O_DATA11_IN register.
\r
680 //******************************************************************************
\r
681 #define SHAMD5_DATA11_IN_DATA11_IN_M \
\r
684 #define SHAMD5_DATA11_IN_DATA11_IN_S 0
\r
685 //******************************************************************************
\r
687 // The following are defines for the bit fields in the SHAMD5_O_DATA12_IN register.
\r
689 //******************************************************************************
\r
690 #define SHAMD5_DATA12_IN_DATA12_IN_M \
\r
693 #define SHAMD5_DATA12_IN_DATA12_IN_S 0
\r
694 //******************************************************************************
\r
696 // The following are defines for the bit fields in the SHAMD5_O_DATA13_IN register.
\r
698 //******************************************************************************
\r
699 #define SHAMD5_DATA13_IN_DATA13_IN_M \
\r
702 #define SHAMD5_DATA13_IN_DATA13_IN_S 0
\r
703 //******************************************************************************
\r
705 // The following are defines for the bit fields in the SHAMD5_O_DATA14_IN register.
\r
707 //******************************************************************************
\r
708 #define SHAMD5_DATA14_IN_DATA14_IN_M \
\r
711 #define SHAMD5_DATA14_IN_DATA14_IN_S 0
\r
712 //******************************************************************************
\r
714 // The following are defines for the bit fields in the SHAMD5_O_DATA15_IN register.
\r
716 //******************************************************************************
\r
717 #define SHAMD5_DATA15_IN_DATA15_IN_M \
\r
720 #define SHAMD5_DATA15_IN_DATA15_IN_S 0
\r
721 //******************************************************************************
\r
723 // The following are defines for the bit fields in the SHAMD5_O_REVISION register.
\r
725 //******************************************************************************
\r
726 #define SHAMD5_REVISION_SCHEME_M 0xC0000000
\r
727 #define SHAMD5_REVISION_SCHEME_S 30
\r
728 #define SHAMD5_REVISION_FUNC_M 0x0FFF0000 // Function indicates a software
\r
729 // compatible module family. If
\r
730 // there is no level of software
\r
731 // compatibility a new Func number
\r
732 // (and hence REVISION) should be
\r
734 #define SHAMD5_REVISION_FUNC_S 16
\r
735 #define SHAMD5_REVISION_R_RTL_M 0x0000F800 // RTL Version (R) maintained by IP
\r
736 // design owner. RTL follows a
\r
737 // numbering such as X.Y.R.Z which
\r
738 // are explained in this table. R
\r
739 // changes ONLY when: (1) PDS
\r
740 // uploads occur which may have been
\r
741 // due to spec changes (2) Bug fixes
\r
742 // occur (3) Resets to '0' when X or
\r
743 // Y changes. Design team has an
\r
744 // internal 'Z' (customer invisible)
\r
745 // number which increments on every
\r
746 // drop that happens due to DV and
\r
747 // RTL updates. Z resets to 0 when R
\r
749 #define SHAMD5_REVISION_R_RTL_S 11
\r
750 #define SHAMD5_REVISION_X_MAJOR_M \
\r
751 0x00000700 // Major Revision (X) maintained by
\r
752 // IP specification owner. X changes
\r
753 // ONLY when: (1) There is a major
\r
754 // feature addition. An example
\r
755 // would be adding Master Mode to
\r
756 // Utopia Level2. The Func field (or
\r
757 // Class/Type in old PID format)
\r
758 // will remain the same. X does NOT
\r
759 // change due to: (1) Bug fixes (2)
\r
760 // Change in feature parameters.
\r
762 #define SHAMD5_REVISION_X_MAJOR_S 8
\r
763 #define SHAMD5_REVISION_CUSTOM_M 0x000000C0
\r
764 #define SHAMD5_REVISION_CUSTOM_S 6
\r
765 #define SHAMD5_REVISION_Y_MINOR_M \
\r
766 0x0000003F // Minor Revision (Y) maintained by
\r
767 // IP specification owner. Y changes
\r
768 // ONLY when: (1) Features are
\r
769 // scaled (up or down). Flexibility
\r
770 // exists in that this feature
\r
771 // scalability may either be
\r
772 // represented in the Y change or a
\r
773 // specific register in the IP that
\r
774 // indicates which features are
\r
775 // exactly available. (2) When
\r
776 // feature creeps from Is-Not list
\r
777 // to Is list. But this may not be
\r
778 // the case once it sees silicon; in
\r
779 // which case X will change. Y does
\r
780 // NOT change due to: (1) Bug fixes
\r
781 // (2) Typos or clarifications (3)
\r
782 // major functional/feature
\r
783 // change/addition/deletion. Instead
\r
784 // these changes may be reflected
\r
785 // via R S X as applicable. Spec
\r
786 // owner maintains a
\r
787 // customer-invisible number 'S'
\r
788 // which changes due to: (1)
\r
789 // Typos/clarifications (2) Bug
\r
790 // documentation. Note that this bug
\r
791 // is not due to a spec change but
\r
792 // due to implementation.
\r
793 // Nevertheless the spec tracks the
\r
794 // IP bugs. An RTL release (say for
\r
795 // silicon PG1.1) that occurs due to
\r
796 // bug fix should document the
\r
797 // corresponding spec number (X.Y.S)
\r
798 // in its release notes.
\r
800 #define SHAMD5_REVISION_Y_MINOR_S 0
\r
801 //******************************************************************************
\r
803 // The following are defines for the bit fields in the SHAMD5_O_SYSCONFIG register.
\r
805 //******************************************************************************
\r
806 #define SHAMD5_SYSCONFIG_PADVANCED \
\r
807 0x00000080 // If set to 1 Advanced mode is
\r
808 // enabled for the Secure World. If
\r
809 // set to 0 Legacy mode is enabled
\r
810 // for the Secure World.
\r
812 #define SHAMD5_SYSCONFIG_PCONT_SWT \
\r
813 0x00000040 // Finish all pending data and
\r
814 // context DMA input requests (but
\r
815 // will not assert any new requests)
\r
816 // finish processing all data in the
\r
817 // module and provide a saved
\r
818 // context (partial hash result
\r
819 // updated digest count remaining
\r
820 // length updated mode information
\r
821 // where applicable) for the last
\r
822 // operation that was interrupted so
\r
823 // that it can be resumed later.
\r
825 #define SHAMD5_SYSCONFIG_PDMA_EN 0x00000008
\r
826 #define SHAMD5_SYSCONFIG_PIT_EN 0x00000004
\r
827 //******************************************************************************
\r
829 // The following are defines for the bit fields in the SHAMD5_O_SYSSTATUS register.
\r
831 //******************************************************************************
\r
832 #define SHAMD5_SYSSTATUS_RESETDONE \
\r
835 //******************************************************************************
\r
837 // The following are defines for the bit fields in the SHAMD5_O_IRQSTATUS register.
\r
839 //******************************************************************************
\r
840 #define SHAMD5_IRQSTATUS_CONTEXT_READY \
\r
841 0x00000008 // indicates that the secure side
\r
842 // context input registers are
\r
843 // available for a new context for
\r
844 // the next packet to be processed.
\r
846 #define SHAMD5_IRQSTATUS_PARTHASH_READY \
\r
847 0x00000004 // After a secure side context
\r
848 // switch request this bit will read
\r
849 // as 1 indicating that the saved
\r
850 // context is available from the
\r
851 // secure side context output
\r
852 // registers. Note that if the
\r
853 // context switch request coincides
\r
854 // with a final hash (when hashing)
\r
855 // or an outer hash (when doing
\r
856 // HMAC) that PartHashReady will not
\r
857 // become active but a regular
\r
858 // Output Ready will occur instead
\r
859 // (indicating that the result is
\r
860 // final and therefore no
\r
861 // continuation is required).
\r
863 #define SHAMD5_IRQSTATUS_INPUT_READY \
\r
864 0x00000002 // indicates that the secure side
\r
865 // data FIFO is ready to receive the
\r
866 // next 64 byte data block.
\r
868 #define SHAMD5_IRQSTATUS_OUTPUT_READY \
\r
869 0x00000001 // Indicates that a (partial)
\r
870 // result or saved context is
\r
871 // available from the secure side
\r
872 // context output registers.
\r
874 //******************************************************************************
\r
876 // The following are defines for the bit fields in the SHAMD5_O_IRQENABLE register.
\r
878 //******************************************************************************
\r
879 #define SHAMD5_IRQENABLE_M_CONTEXT_READY \
\r
880 0x00000008 // mask for context ready
\r
882 #define SHAMD5_IRQENABLE_M_PARTHASH_READY \
\r
883 0x00000004 // mask for partial hash
\r
885 #define SHAMD5_IRQENABLE_M_INPUT_READY \
\r
886 0x00000002 // mask for input_ready
\r
888 #define SHAMD5_IRQENABLE_M_OUTPUT_READY \
\r
889 0x00000001 // mask for output_ready
\r
891 //******************************************************************************
\r
893 // The following are defines for the bit fields in the
\r
894 // SHAMD5_O_HASH512_ODIGEST_A register.
\r
896 //******************************************************************************
\r
897 #define SHAMD5_HASH512_ODIGEST_A_DATA_M \
\r
900 #define SHAMD5_HASH512_ODIGEST_A_DATA_S 0
\r
901 //******************************************************************************
\r
903 // The following are defines for the bit fields in the
\r
904 // SHAMD5_O_HASH512_ODIGEST_B register.
\r
906 //******************************************************************************
\r
907 #define SHAMD5_HASH512_ODIGEST_B_DATA_M \
\r
910 #define SHAMD5_HASH512_ODIGEST_B_DATA_S 0
\r
911 //******************************************************************************
\r
913 // The following are defines for the bit fields in the
\r
914 // SHAMD5_O_HASH512_ODIGEST_C register.
\r
916 //******************************************************************************
\r
917 #define SHAMD5_HASH512_ODIGEST_C_DATA_M \
\r
920 #define SHAMD5_HASH512_ODIGEST_C_DATA_S 0
\r
921 //******************************************************************************
\r
923 // The following are defines for the bit fields in the
\r
924 // SHAMD5_O_HASH512_ODIGEST_D register.
\r
926 //******************************************************************************
\r
927 #define SHAMD5_HASH512_ODIGEST_D_DATA_M \
\r
930 #define SHAMD5_HASH512_ODIGEST_D_DATA_S 0
\r
931 //******************************************************************************
\r
933 // The following are defines for the bit fields in the
\r
934 // SHAMD5_O_HASH512_ODIGEST_E register.
\r
936 //******************************************************************************
\r
937 #define SHAMD5_HASH512_ODIGEST_E_DATA_M \
\r
940 #define SHAMD5_HASH512_ODIGEST_E_DATA_S 0
\r
941 //******************************************************************************
\r
943 // The following are defines for the bit fields in the
\r
944 // SHAMD5_O_HASH512_ODIGEST_F register.
\r
946 //******************************************************************************
\r
947 #define SHAMD5_HASH512_ODIGEST_F_DATA_M \
\r
950 #define SHAMD5_HASH512_ODIGEST_F_DATA_S 0
\r
951 //******************************************************************************
\r
953 // The following are defines for the bit fields in the
\r
954 // SHAMD5_O_HASH512_ODIGEST_G register.
\r
956 //******************************************************************************
\r
957 #define SHAMD5_HASH512_ODIGEST_G_DATA_M \
\r
960 #define SHAMD5_HASH512_ODIGEST_G_DATA_S 0
\r
961 //******************************************************************************
\r
963 // The following are defines for the bit fields in the
\r
964 // SHAMD5_O_HASH512_ODIGEST_H register.
\r
966 //******************************************************************************
\r
967 #define SHAMD5_HASH512_ODIGEST_H_DATA_M \
\r
970 #define SHAMD5_HASH512_ODIGEST_H_DATA_S 0
\r
971 //******************************************************************************
\r
973 // The following are defines for the bit fields in the
\r
974 // SHAMD5_O_HASH512_ODIGEST_I register.
\r
976 //******************************************************************************
\r
977 #define SHAMD5_HASH512_ODIGEST_I_DATA_M \
\r
980 #define SHAMD5_HASH512_ODIGEST_I_DATA_S 0
\r
981 //******************************************************************************
\r
983 // The following are defines for the bit fields in the
\r
984 // SHAMD5_O_HASH512_ODIGEST_J register.
\r
986 //******************************************************************************
\r
987 #define SHAMD5_HASH512_ODIGEST_J_DATA_M \
\r
990 #define SHAMD5_HASH512_ODIGEST_J_DATA_S 0
\r
991 //******************************************************************************
\r
993 // The following are defines for the bit fields in the
\r
994 // SHAMD5_O_HASH512_ODIGEST_K register.
\r
996 //******************************************************************************
\r
997 #define SHAMD5_HASH512_ODIGEST_K_DATA_M \
\r
1000 #define SHAMD5_HASH512_ODIGEST_K_DATA_S 0
\r
1001 //******************************************************************************
\r
1003 // The following are defines for the bit fields in the
\r
1004 // SHAMD5_O_HASH512_ODIGEST_L register.
\r
1006 //******************************************************************************
\r
1007 #define SHAMD5_HASH512_ODIGEST_L_DATA_M \
\r
1010 #define SHAMD5_HASH512_ODIGEST_L_DATA_S 0
\r
1011 //******************************************************************************
\r
1013 // The following are defines for the bit fields in the
\r
1014 // SHAMD5_O_HASH512_ODIGEST_M register.
\r
1016 //******************************************************************************
\r
1017 #define SHAMD5_HASH512_ODIGEST_M_DATA_M \
\r
1020 #define SHAMD5_HASH512_ODIGEST_M_DATA_S 0
\r
1021 //******************************************************************************
\r
1023 // The following are defines for the bit fields in the
\r
1024 // SHAMD5_O_HASH512_ODIGEST_N register.
\r
1026 //******************************************************************************
\r
1027 #define SHAMD5_HASH512_ODIGEST_N_DATA_M \
\r
1030 #define SHAMD5_HASH512_ODIGEST_N_DATA_S 0
\r
1031 //******************************************************************************
\r
1033 // The following are defines for the bit fields in the
\r
1034 // SHAMD5_O_HASH512_ODIGEST_O register.
\r
1036 //******************************************************************************
\r
1037 #define SHAMD5_HASH512_ODIGEST_O_DATA_M \
\r
1040 #define SHAMD5_HASH512_ODIGEST_O_DATA_S 0
\r
1041 //******************************************************************************
\r
1043 // The following are defines for the bit fields in the
\r
1044 // SHAMD5_O_HASH512_ODIGEST_P register.
\r
1046 //******************************************************************************
\r
1047 #define SHAMD5_HASH512_ODIGEST_DATA_M \
\r
1050 #define SHAMD5_HASH512_ODIGEST_DATA_S 0
\r
1051 //******************************************************************************
\r
1053 // The following are defines for the bit fields in the
\r
1054 // SHAMD5_O_HASH512_IDIGEST_A register.
\r
1056 //******************************************************************************
\r
1057 #define SHAMD5_HASH512_IDIGEST_A_DATA_M \
\r
1060 #define SHAMD5_HASH512_IDIGEST_A_DATA_S 0
\r
1061 //******************************************************************************
\r
1063 // The following are defines for the bit fields in the
\r
1064 // SHAMD5_O_HASH512_IDIGEST_B register.
\r
1066 //******************************************************************************
\r
1067 #define SHAMD5_HASH512_IDIGEST_B_DATA_M \
\r
1070 #define SHAMD5_HASH512_IDIGEST_B_DATA_S 0
\r
1071 //******************************************************************************
\r
1073 // The following are defines for the bit fields in the
\r
1074 // SHAMD5_O_HASH512_IDIGEST_C register.
\r
1076 //******************************************************************************
\r
1077 #define SHAMD5_HASH512_IDIGEST_C_DATA_M \
\r
1080 #define SHAMD5_HASH512_IDIGEST_C_DATA_S 0
\r
1081 //******************************************************************************
\r
1083 // The following are defines for the bit fields in the
\r
1084 // SHAMD5_O_HASH512_IDIGEST_D register.
\r
1086 //******************************************************************************
\r
1087 #define SHAMD5_HASH512_IDIGEST_D_DATA_M \
\r
1090 #define SHAMD5_HASH512_IDIGEST_D_DATA_S 0
\r
1091 //******************************************************************************
\r
1093 // The following are defines for the bit fields in the
\r
1094 // SHAMD5_O_HASH512_IDIGEST_E register.
\r
1096 //******************************************************************************
\r
1097 #define SHAMD5_HASH512_IDIGEST_E_DATA_M \
\r
1100 #define SHAMD5_HASH512_IDIGEST_E_DATA_S 0
\r
1101 //******************************************************************************
\r
1103 // The following are defines for the bit fields in the
\r
1104 // SHAMD5_O_HASH512_IDIGEST_F register.
\r
1106 //******************************************************************************
\r
1107 #define SHAMD5_HASH512_IDIGEST_F_DATA_M \
\r
1110 #define SHAMD5_HASH512_IDIGEST_F_DATA_S 0
\r
1111 //******************************************************************************
\r
1113 // The following are defines for the bit fields in the
\r
1114 // SHAMD5_O_HASH512_IDIGEST_G register.
\r
1116 //******************************************************************************
\r
1117 #define SHAMD5_HASH512_IDIGEST_G_DATA_M \
\r
1120 #define SHAMD5_HASH512_IDIGEST_G_DATA_S 0
\r
1121 //******************************************************************************
\r
1123 // The following are defines for the bit fields in the
\r
1124 // SHAMD5_O_HASH512_IDIGEST_H register.
\r
1126 //******************************************************************************
\r
1127 #define SHAMD5_HASH512_IDIGEST_H_DATA_M \
\r
1130 #define SHAMD5_HASH512_IDIGEST_H_DATA_S 0
\r
1131 //******************************************************************************
\r
1133 // The following are defines for the bit fields in the
\r
1134 // SHAMD5_O_HASH512_IDIGEST_I register.
\r
1136 //******************************************************************************
\r
1137 #define SHAMD5_HASH512_IDIGEST_I_DATA_M \
\r
1140 #define SHAMD5_HASH512_IDIGEST_I_DATA_S 0
\r
1141 //******************************************************************************
\r
1143 // The following are defines for the bit fields in the
\r
1144 // SHAMD5_O_HASH512_IDIGEST_J register.
\r
1146 //******************************************************************************
\r
1147 #define SHAMD5_HASH512_IDIGEST_J_DATA_M \
\r
1150 #define SHAMD5_HASH512_IDIGEST_J_DATA_S 0
\r
1151 //******************************************************************************
\r
1153 // The following are defines for the bit fields in the
\r
1154 // SHAMD5_O_HASH512_IDIGEST_K register.
\r
1156 //******************************************************************************
\r
1157 #define SHAMD5_HASH512_IDIGEST_K_DATA_M \
\r
1160 #define SHAMD5_HASH512_IDIGEST_K_DATA_S 0
\r
1161 //******************************************************************************
\r
1163 // The following are defines for the bit fields in the
\r
1164 // SHAMD5_O_HASH512_IDIGEST_L register.
\r
1166 //******************************************************************************
\r
1167 #define SHAMD5_HASH512_IDIGEST_L_DATA_M \
\r
1170 #define SHAMD5_HASH512_IDIGEST_L_DATA_S 0
\r
1171 //******************************************************************************
\r
1173 // The following are defines for the bit fields in the
\r
1174 // SHAMD5_O_HASH512_IDIGEST_M register.
\r
1176 //******************************************************************************
\r
1177 #define SHAMD5_HASH512_IDIGEST_M_DATA_M \
\r
1180 #define SHAMD5_HASH512_IDIGEST_M_DATA_S 0
\r
1181 //******************************************************************************
\r
1183 // The following are defines for the bit fields in the
\r
1184 // SHAMD5_O_HASH512_IDIGEST_N register.
\r
1186 //******************************************************************************
\r
1187 #define SHAMD5_HASH512_IDIGEST_N_DATA_M \
\r
1190 #define SHAMD5_HASH512_IDIGEST_N_DATA_S 0
\r
1191 //******************************************************************************
\r
1193 // The following are defines for the bit fields in the
\r
1194 // SHAMD5_O_HASH512_IDIGEST_O register.
\r
1196 //******************************************************************************
\r
1197 #define SHAMD5_HASH512_IDIGEST_O_DATA_M \
\r
1200 #define SHAMD5_HASH512_IDIGEST_O_DATA_S 0
\r
1201 //******************************************************************************
\r
1203 // The following are defines for the bit fields in the
\r
1204 // SHAMD5_O_HASH512_IDIGEST_P register.
\r
1206 //******************************************************************************
\r
1207 #define SHAMD5_HASH512_IDIGEST_DATA_M \
\r
1210 #define SHAMD5_HASH512_IDIGEST_DATA_S 0
\r
1211 //******************************************************************************
\r
1213 // The following are defines for the bit fields in the
\r
1214 // SHAMD5_O_HASH512_DIGEST_COUNT register.
\r
1216 //******************************************************************************
\r
1217 #define SHAMD5_HASH512_DIGEST_COUNT_DATA_M \
\r
1220 #define SHAMD5_HASH512_DIGEST_COUNT_DATA_S 0
\r
1221 //******************************************************************************
\r
1223 // The following are defines for the bit fields in the
\r
1224 // SHAMD5_O_HASH512_MODE register.
\r
1226 //******************************************************************************
\r
1227 #define SHAMD5_HASH512_MODE_DATA_M \
\r
1230 #define SHAMD5_HASH512_MODE_DATA_S 0
\r
1231 //******************************************************************************
\r
1233 // The following are defines for the bit fields in the
\r
1234 // SHAMD5_O_HASH512_LENGTH register.
\r
1236 //******************************************************************************
\r
1237 #define SHAMD5_HASH512_LENGTH_DATA_M \
\r
1240 #define SHAMD5_HASH512_LENGTH_DATA_S 0
\r
1244 #endif // __HW_SHAMD5_H__
\r
projects / freertos / blob