git.sur5r.net Git - freertos/blob - FreeRTOS/Demo/CORTEX_M4_SimpleLink_CC3220SF_CCS/ti/devices/cc32xx/inc/hw_uart.h

   1 /*\r
   2  * -------------------------------------------\r
   3  *    CC3220 SDK - v0.10.00.00 \r
   4  * -------------------------------------------\r
   5  *\r
   6  *  Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/ \r
   7  *  \r
   8  *  Redistribution and use in source and binary forms, with or without \r
   9  *  modification, are permitted provided that the following conditions \r
  10  *  are met:\r
  11  *\r
  12  *    Redistributions of source code must retain the above copyright \r
  13  *    notice, this list of conditions and the following disclaimer.\r
  14  *\r
  15  *    Redistributions in binary form must reproduce the above copyright\r
  16  *    notice, this list of conditions and the following disclaimer in the \r
  17  *    documentation and/or other materials provided with the   \r
  18  *    distribution.\r
  19  *\r
  20  *    Neither the name of Texas Instruments Incorporated nor the names of\r
  21  *    its contributors may be used to endorse or promote products derived\r
  22  *    from this software without specific prior written permission.\r
  23  *\r
  24  *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \r
  25  *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT \r
  26  *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
  27  *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT \r
  28  *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, \r
  29  *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT \r
  30  *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\r
  31  *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\r
  32  *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT \r
  33  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE \r
  34  *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
  35  *  \r
  36  */\r
  37 \r
  38 #ifndef __HW_UART_H__\r
  39 #define __HW_UART_H__\r
  40 \r
  41 //*****************************************************************************\r
  42 //\r
  43 // The following are defines for the UART register offsets.\r
  44 //\r
  45 //*****************************************************************************\r
  46 #define UART_O_DR               0x00000000\r
  47 #define UART_O_RSR              0x00000004\r
  48 #define UART_O_ECR              0x00000004\r
  49 #define UART_O_FR               0x00000018\r
  50 #define UART_O_ILPR             0x00000020\r
  51 #define UART_O_IBRD             0x00000024\r
  52 #define UART_O_FBRD             0x00000028\r
  53 #define UART_O_LCRH             0x0000002C\r
  54 #define UART_O_CTL              0x00000030\r
  55 #define UART_O_IFLS             0x00000034\r
  56 #define UART_O_IM               0x00000038\r
  57 #define UART_O_RIS              0x0000003C\r
  58 #define UART_O_MIS              0x00000040\r
  59 #define UART_O_ICR              0x00000044\r
  60 #define UART_O_DMACTL           0x00000048\r
  61 #define UART_O_LCTL             0x00000090\r
  62 #define UART_O_LSS              0x00000094\r
  63 #define UART_O_LTIM             0x00000098\r
  64 #define UART_O_9BITADDR      0x000000A4\r
  65 #define UART_O_9BITAMASK     0x000000A8\r
  66 #define UART_O_PP               0x00000FC0\r
  67 #define UART_O_CC               0x00000FC8\r
  68 \r
  69 \r
  70 \r
  71 //******************************************************************************\r
  72 //\r
  73 // The following are defines for the bit fields in the UART_O_DR register.\r
  74 //\r
  75 //******************************************************************************\r
  76 #define UART_DR_OE              0x00000800  // UART Overrun Error\r
  77 #define UART_DR_BE              0x00000400  // UART Break Error\r
  78 #define UART_DR_PE              0x00000200  // UART Parity Error\r
  79 #define UART_DR_FE              0x00000100  // UART Framing Error\r
  80 #define UART_DR_DATA_M        0x000000FF  // Data Transmitted or Received\r
  81 #define UART_DR_DATA_S        0\r
  82 //******************************************************************************\r
  83 //\r
  84 // The following are defines for the bit fields in the UART_O_RSR register.\r
  85 //\r
  86 //******************************************************************************\r
  87 #define UART_RSR_OE             0x00000008  // UART Overrun Error\r
  88 #define UART_RSR_BE             0x00000004  // UART Break Error\r
  89 #define UART_RSR_PE             0x00000002  // UART Parity Error\r
  90 #define UART_RSR_FE             0x00000001  // UART Framing Error\r
  91 //******************************************************************************\r
  92 //\r
  93 // The following are defines for the bit fields in the UART_O_ECR register.\r
  94 //\r
  95 //******************************************************************************\r
  96 #define UART_ECR_DATA_M       0x000000FF  // Error Clear\r
  97 #define UART_ECR_DATA_S       0\r
  98 //******************************************************************************\r
  99 //\r
 100 // The following are defines for the bit fields in the UART_O_FR register.\r
 101 //\r
 102 //******************************************************************************\r
 103 #define UART_FR_RI              0x00000100  // Ring Indicator\r
 104 #define UART_FR_TXFE            0x00000080  // UART Transmit FIFO Empty\r
 105 #define UART_FR_RXFF            0x00000040  // UART Receive FIFO Full\r
 106 #define UART_FR_TXFF            0x00000020  // UART Transmit FIFO Full\r
 107 #define UART_FR_RXFE            0x00000010  // UART Receive FIFO Empty\r
 108 #define UART_FR_BUSY            0x00000008  // UART Busy\r
 109 #define UART_FR_DCD             0x00000004  // Data Carrier Detect\r
 110 #define UART_FR_DSR             0x00000002  // Data Set Ready\r
 111 #define UART_FR_CTS             0x00000001  // Clear To Send\r
 112 //******************************************************************************\r
 113 //\r
 114 // The following are defines for the bit fields in the UART_O_ILPR register.\r
 115 //\r
 116 //******************************************************************************\r
 117 #define UART_ILPR_ILPDVSR_M   0x000000FF  // IrDA Low-Power Divisor\r
 118 #define UART_ILPR_ILPDVSR_S   0\r
 119 //******************************************************************************\r
 120 //\r
 121 // The following are defines for the bit fields in the UART_O_IBRD register.\r
 122 //\r
 123 //******************************************************************************\r
 124 #define UART_IBRD_DIVINT_M    0x0000FFFF  // Integer Baud-Rate Divisor\r
 125 #define UART_IBRD_DIVINT_S    0\r
 126 //******************************************************************************\r
 127 //\r
 128 // The following are defines for the bit fields in the UART_O_FBRD register.\r
 129 //\r
 130 //******************************************************************************\r
 131 #define UART_FBRD_DIVFRAC_M   0x0000003F  // Fractional Baud-Rate Divisor\r
 132 #define UART_FBRD_DIVFRAC_S   0\r
 133 //******************************************************************************\r
 134 //\r
 135 // The following are defines for the bit fields in the UART_O_LCRH register.\r
 136 //\r
 137 //******************************************************************************\r
 138 #define UART_LCRH_SPS           0x00000080  // UART Stick Parity Select\r
 139 #define UART_LCRH_WLEN_M      0x00000060  // UART Word Length 0x00000000 :\r
 140                                             // UART_LCRH_WLEN_5 : 5 bits\r
 141                                             // (default) 0x00000020 :\r
 142                                             // UART_LCRH_WLEN_6 : 6 bits\r
 143                                             // 0x00000040 : UART_LCRH_WLEN_7 : 7\r
 144                                             // bits 0x00000060 :\r
 145                                             // UART_LCRH_WLEN_8 : 8 bits\r
 146 #define UART_LCRH_WLEN_S      5\r
 147 #define UART_LCRH_FEN           0x00000010  // UART Enable FIFOs\r
 148 #define UART_LCRH_STP2          0x00000008  // UART Two Stop Bits Select\r
 149 #define UART_LCRH_EPS           0x00000004  // UART Even Parity Select\r
 150 #define UART_LCRH_PEN           0x00000002  // UART Parity Enable\r
 151 #define UART_LCRH_BRK           0x00000001  // UART Send Break\r
 152 #define UART_LCRH_WLEN_M        0x00000060  // UART Word Length\r
 153 #define UART_LCRH_WLEN_5        0x00000000  // 5 bits (default)\r
 154 #define UART_LCRH_WLEN_6        0x00000020  // 6 bits\r
 155 #define UART_LCRH_WLEN_7        0x00000040  // 7 bits\r
 156 #define UART_LCRH_WLEN_8        0x00000060  // 8 bits\r
 157 //******************************************************************************\r
 158 //\r
 159 // The following are defines for the bit fields in the UART_O_CTL register.\r
 160 //\r
 161 //******************************************************************************\r
 162 #define UART_CTL_CTSEN          0x00008000  // Enable Clear To Send\r
 163 #define UART_CTL_RTSEN          0x00004000  // Enable Request to Send\r
 164 #define UART_CTL_RI             0x00002000  // Ring Indicator\r
 165 #define UART_CTL_DCD            0x00001000  // Data Carrier Detect\r
 166 #define UART_CTL_RTS            0x00000800  // Request to Send\r
 167 #define UART_CTL_DTR            0x00000400  // Data Terminal Ready\r
 168 #define UART_CTL_RXE            0x00000200  // UART Receive Enable\r
 169 #define UART_CTL_TXE            0x00000100  // UART Transmit Enable\r
 170 #define UART_CTL_LBE            0x00000080  // UART Loop Back Enable\r
 171 #define UART_CTL_LIN            0x00000040  // LIN Mode Enable\r
 172 #define UART_CTL_HSE            0x00000020  // High-Speed Enable\r
 173 #define UART_CTL_EOT            0x00000010  // End of Transmission\r
 174 #define UART_CTL_SMART          0x00000008  // ISO 7816 Smart Card Support\r
 175 #define UART_CTL_SIRLP          0x00000004  // UART SIR Low-Power Mode\r
 176 #define UART_CTL_SIREN          0x00000002  // UART SIR Enable\r
 177 #define UART_CTL_UARTEN         0x00000001  // UART Enable\r
 178 //******************************************************************************\r
 179 //\r
 180 // The following are defines for the bit fields in the UART_O_IFLS register.\r
 181 //\r
 182 //******************************************************************************\r
 183 #define UART_IFLS_RX_M        0x00000038  // UART Receive Interrupt FIFO\r
 184                                             // Level Select\r
 185 #define UART_IFLS_RX_S        3\r
 186 #define UART_IFLS_TX_M        0x00000007  // UART Transmit Interrupt FIFO\r
 187                                             // Level Select\r
 188 #define UART_IFLS_TX_S        0\r
 189 //******************************************************************************\r
 190 //\r
 191 // The following are defines for the bit fields in the UART_O_IM register.\r
 192 //\r
 193 //******************************************************************************\r
 194 #define UART_IM_DMATXIM         0x00020000  // Transmit DMA Interrupt Mask\r
 195 #define UART_IM_DMARXIM         0x00010000  // Receive DMA Interrupt Mask\r
 196 #define UART_IM_LME5IM          0x00008000  // LIN Mode Edge 5 Interrupt Mask\r
 197 #define UART_IM_LME1IM          0x00004000  // LIN Mode Edge 1 Interrupt Mask\r
 198 #define UART_IM_LMSBIM          0x00002000  // LIN Mode Sync Break Interrupt\r
 199                                             // Mask\r
 200 #define UART_IM_9BITIM       0x00001000  // 9-Bit Mode Interrupt Mask\r
 201 #define UART_IM_EOTIM           0x00000800  // End of Transmission Interrupt\r
 202                                             // Mask\r
 203 #define UART_IM_OEIM            0x00000400  // UART Overrun Error Interrupt\r
 204                                             // Mask\r
 205 #define UART_IM_BEIM            0x00000200  // UART Break Error Interrupt Mask\r
 206 #define UART_IM_PEIM            0x00000100  // UART Parity Error Interrupt Mask\r
 207 #define UART_IM_FEIM            0x00000080  // UART Framing Error Interrupt\r
 208                                             // Mask\r
 209 #define UART_IM_RTIM            0x00000040  // UART Receive Time-Out Interrupt\r
 210                                             // Mask\r
 211 #define UART_IM_TXIM            0x00000020  // UART Transmit Interrupt Mask\r
 212 #define UART_IM_RXIM            0x00000010  // UART Receive Interrupt Mask\r
 213 #define UART_IM_DSRMIM          0x00000008  // UART Data Set Ready Modem\r
 214                                             // Interrupt Mask\r
 215 #define UART_IM_DCDMIM          0x00000004  // UART Data Carrier Detect Modem\r
 216                                             // Interrupt Mask\r
 217 #define UART_IM_CTSMIM          0x00000002  // UART Clear to Send Modem\r
 218                                             // Interrupt Mask\r
 219 #define UART_IM_RIMIM           0x00000001  // UART Ring Indicator Modem\r
 220                                             // Interrupt Mask\r
 221 //******************************************************************************\r
 222 //\r
 223 // The following are defines for the bit fields in the UART_O_RIS register.\r
 224 //\r
 225 //******************************************************************************\r
 226 #define UART_RIS_DMATXRIS       0x00020000  // Transmit DMA Raw Interrupt\r
 227                                             // Status\r
 228 #define UART_RIS_DMARXRIS       0x00010000  // Receive DMA Raw Interrupt Status\r
 229 #define UART_RIS_LME5RIS        0x00008000  // LIN Mode Edge 5 Raw Interrupt\r
 230                                             // Status\r
 231 #define UART_RIS_LME1RIS        0x00004000  // LIN Mode Edge 1 Raw Interrupt\r
 232                                             // Status\r
 233 #define UART_RIS_LMSBRIS        0x00002000  // LIN Mode Sync Break Raw\r
 234                                             // Interrupt Status\r
 235 #define UART_RIS_9BITRIS     0x00001000  // 9-Bit Mode Raw Interrupt Status\r
 236 #define UART_RIS_EOTRIS         0x00000800  // End of Transmission Raw\r
 237                                             // Interrupt Status\r
 238 #define UART_RIS_OERIS          0x00000400  // UART Overrun Error Raw Interrupt\r
 239                                             // Status\r
 240 #define UART_RIS_BERIS          0x00000200  // UART Break Error Raw Interrupt\r
 241                                             // Status\r
 242 #define UART_RIS_PERIS          0x00000100  // UART Parity Error Raw Interrupt\r
 243                                             // Status\r
 244 #define UART_RIS_FERIS          0x00000080  // UART Framing Error Raw Interrupt\r
 245                                             // Status\r
 246 #define UART_RIS_RTRIS          0x00000040  // UART Receive Time-Out Raw\r
 247                                             // Interrupt Status\r
 248 #define UART_RIS_TXRIS          0x00000020  // UART Transmit Raw Interrupt\r
 249                                             // Status\r
 250 #define UART_RIS_RXRIS          0x00000010  // UART Receive Raw Interrupt\r
 251                                             // Status\r
 252 #define UART_RIS_DSRRIS         0x00000008  // UART Data Set Ready Modem Raw\r
 253                                             // Interrupt Status\r
 254 #define UART_RIS_DCDRIS         0x00000004  // UART Data Carrier Detect Modem\r
 255                                             // Raw Interrupt Status\r
 256 #define UART_RIS_CTSRIS         0x00000002  // UART Clear to Send Modem Raw\r
 257                                             // Interrupt Status\r
 258 #define UART_RIS_RIRIS          0x00000001  // UART Ring Indicator Modem Raw\r
 259                                             // Interrupt Status\r
 260 //******************************************************************************\r
 261 //\r
 262 // The following are defines for the bit fields in the UART_O_MIS register.\r
 263 //\r
 264 //******************************************************************************\r
 265 #define UART_MIS_DMATXMIS       0x00020000  // Transmit DMA Masked Interrupt\r
 266                                             // Status\r
 267 #define UART_MIS_DMARXMIS       0x00010000  // Receive DMA Masked Interrupt\r
 268                                             // Status\r
 269 #define UART_MIS_LME5MIS        0x00008000  // LIN Mode Edge 5 Masked Interrupt\r
 270                                             // Status\r
 271 #define UART_MIS_LME1MIS        0x00004000  // LIN Mode Edge 1 Masked Interrupt\r
 272                                             // Status\r
 273 #define UART_MIS_LMSBMIS        0x00002000  // LIN Mode Sync Break Masked\r
 274                                             // Interrupt Status\r
 275 #define UART_MIS_9BITMIS     0x00001000  // 9-Bit Mode Masked Interrupt\r
 276                                             // Status\r
 277 #define UART_MIS_EOTMIS         0x00000800  // End of Transmission Masked\r
 278                                             // Interrupt Status\r
 279 #define UART_MIS_OEMIS          0x00000400  // UART Overrun Error Masked\r
 280                                             // Interrupt Status\r
 281 #define UART_MIS_BEMIS          0x00000200  // UART Break Error Masked\r
 282                                             // Interrupt Status\r
 283 #define UART_MIS_PEMIS          0x00000100  // UART Parity Error Masked\r
 284                                             // Interrupt Status\r
 285 #define UART_MIS_FEMIS          0x00000080  // UART Framing Error Masked\r
 286                                             // Interrupt Status\r
 287 #define UART_MIS_RTMIS          0x00000040  // UART Receive Time-Out Masked\r
 288                                             // Interrupt Status\r
 289 #define UART_MIS_TXMIS          0x00000020  // UART Transmit Masked Interrupt\r
 290                                             // Status\r
 291 #define UART_MIS_RXMIS          0x00000010  // UART Receive Masked Interrupt\r
 292                                             // Status\r
 293 #define UART_MIS_DSRMIS         0x00000008  // UART Data Set Ready Modem Masked\r
 294                                             // Interrupt Status\r
 295 #define UART_MIS_DCDMIS         0x00000004  // UART Data Carrier Detect Modem\r
 296                                             // Masked Interrupt Status\r
 297 #define UART_MIS_CTSMIS         0x00000002  // UART Clear to Send Modem Masked\r
 298                                             // Interrupt Status\r
 299 #define UART_MIS_RIMIS          0x00000001  // UART Ring Indicator Modem Masked\r
 300                                             // Interrupt Status\r
 301 //******************************************************************************\r
 302 //\r
 303 // The following are defines for the bit fields in the UART_O_ICR register.\r
 304 //\r
 305 //******************************************************************************\r
 306 #define UART_ICR_DMATXIC        0x00020000  // Transmit DMA Interrupt Clear\r
 307 #define UART_ICR_DMARXIC        0x00010000  // Receive DMA Interrupt Clear\r
 308 #define UART_ICR_LME5MIC        0x00008000  // LIN Mode Edge 5 Interrupt Clear\r
 309 #define UART_ICR_LME1MIC        0x00004000  // LIN Mode Edge 1 Interrupt Clear\r
 310 #define UART_ICR_LMSBMIC        0x00002000  // LIN Mode Sync Break Interrupt\r
 311                                             // Clear\r
 312 #define UART_ICR_9BITIC      0x00001000  // 9-Bit Mode Interrupt Clear\r
 313 #define UART_ICR_EOTIC          0x00000800  // End of Transmission Interrupt\r
 314                                             // Clear\r
 315 #define UART_ICR_OEIC           0x00000400  // Overrun Error Interrupt Clear\r
 316 #define UART_ICR_BEIC           0x00000200  // Break Error Interrupt Clear\r
 317 #define UART_ICR_PEIC           0x00000100  // Parity Error Interrupt Clear\r
 318 #define UART_ICR_FEIC           0x00000080  // Framing Error Interrupt Clear\r
 319 #define UART_ICR_RTIC           0x00000040  // Receive Time-Out Interrupt Clear\r
 320 #define UART_ICR_TXIC           0x00000020  // Transmit Interrupt Clear\r
 321 #define UART_ICR_RXIC           0x00000010  // Receive Interrupt Clear\r
 322 #define UART_ICR_DSRMIC         0x00000008  // UART Data Set Ready Modem\r
 323                                             // Interrupt Clear\r
 324 #define UART_ICR_DCDMIC         0x00000004  // UART Data Carrier Detect Modem\r
 325                                             // Interrupt Clear\r
 326 #define UART_ICR_CTSMIC         0x00000002  // UART Clear to Send Modem\r
 327                                             // Interrupt Clear\r
 328 #define UART_ICR_RIMIC          0x00000001  // UART Ring Indicator Modem\r
 329                                             // Interrupt Clear\r
 330 //******************************************************************************\r
 331 //\r
 332 // The following are defines for the bit fields in the UART_O_DMACTL register.\r
 333 //\r
 334 //******************************************************************************\r
 335 #define UART_DMACTL_DMAERR      0x00000004  // DMA on Error\r
 336 #define UART_DMACTL_TXDMAE      0x00000002  // Transmit DMA Enable\r
 337 #define UART_DMACTL_RXDMAE      0x00000001  // Receive DMA Enable\r
 338 //******************************************************************************\r
 339 //\r
 340 // The following are defines for the bit fields in the UART_O_LCTL register.\r
 341 //\r
 342 //******************************************************************************\r
 343 #define UART_LCTL_BLEN_M      0x00000030  // Sync Break Length 0x00000000 :\r
 344                                             // UART_LCTL_BLEN_13T : Sync break\r
 345                                             // length is 13T bits (default)\r
 346                                             // 0x00000010 : UART_LCTL_BLEN_14T :\r
 347                                             // Sync break length is 14T bits\r
 348                                             // 0x00000020 : UART_LCTL_BLEN_15T :\r
 349                                             // Sync break length is 15T bits\r
 350                                             // 0x00000030 : UART_LCTL_BLEN_16T :\r
 351                                             // Sync break length is 16T bits\r
 352 #define UART_LCTL_BLEN_S      4\r
 353 #define UART_LCTL_MASTER        0x00000001  // LIN Master Enable\r
 354 //******************************************************************************\r
 355 //\r
 356 // The following are defines for the bit fields in the UART_O_LSS register.\r
 357 //\r
 358 //******************************************************************************\r
 359 #define UART_LSS_TSS_M        0x0000FFFF  // Timer Snap Shot\r
 360 #define UART_LSS_TSS_S        0\r
 361 //******************************************************************************\r
 362 //\r
 363 // The following are defines for the bit fields in the UART_O_LTIM register.\r
 364 //\r
 365 //******************************************************************************\r
 366 #define UART_LTIM_TIMER_M     0x0000FFFF  // Timer Value\r
 367 #define UART_LTIM_TIMER_S     0\r
 368 //******************************************************************************\r
 369 //\r
 370 // The following are defines for the bit fields in the\r
 371 // UART_O_9BITADDR register.\r
 372 //\r
 373 //******************************************************************************\r
 374 #define UART_9BITADDR_9BITEN \\r
 375                                 0x00008000  // Enable 9-Bit Mode\r
 376 \r
 377 #define UART_9BITADDR_ADDR_M \\r
 378                                 0x000000FF  // Self Address for 9-Bit Mode\r
 379 \r
 380 #define UART_9BITADDR_ADDR_S 0\r
 381 //******************************************************************************\r
 382 //\r
 383 // The following are defines for the bit fields in the\r
 384 // UART_O_9BITAMASK register.\r
 385 //\r
 386 //******************************************************************************\r
 387 #define UART_9BITAMASK_RANGE_M \\r
 388                                 0x0000FF00  // Self Address Range for 9-Bit\r
 389                                             // Mode\r
 390 \r
 391 #define UART_9BITAMASK_RANGE_S 8\r
 392 #define UART_9BITAMASK_MASK_M \\r
 393                                 0x000000FF  // Self Address Mask for 9-Bit Mode\r
 394 \r
 395 #define UART_9BITAMASK_MASK_S 0\r
 396 //******************************************************************************\r
 397 //\r
 398 // The following are defines for the bit fields in the UART_O_PP register.\r
 399 //\r
 400 //******************************************************************************\r
 401 #define UART_PP_MSE             0x00000008  // Modem Support Extended\r
 402 #define UART_PP_MS              0x00000004  // Modem Support\r
 403 #define UART_PP_NB              0x00000002  // 9-Bit Support\r
 404 #define UART_PP_SC              0x00000001  // Smart Card Support\r
 405 //******************************************************************************\r
 406 //\r
 407 // The following are defines for the bit fields in the UART_O_CC register.\r
 408 //\r
 409 //******************************************************************************\r
 410 #define UART_CC_CS_M          0x0000000F  // UART Baud Clock Source\r
 411                                             // 0x00000005 : UART_CC_CS_PIOSC :\r
 412                                             // PIOSC 0x00000000 :\r
 413                                             // UART_CC_CS_SYSCLK : The system\r
 414                                             // clock (default)\r
 415 #define UART_CC_CS_S          0\r
 416 \r
 417 \r
 418 \r
 419 #endif // __HW_UART_H__\r