2 * FreeRTOS Kernel V10.3.0
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3 * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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5 * Permission is hereby granted, free of charge, to any person obtaining a copy of
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6 * this software and associated documentation files (the "Software"), to deal in
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7 * the Software without restriction, including without limitation the rights to
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8 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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9 * the Software, and to permit persons to whom the Software is furnished to do so,
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10 * subject to the following conditions:
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12 * The above copyright notice and this permission notice shall be included in all
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13 * copies or substantial portions of the Software.
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15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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17 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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18 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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19 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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20 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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22 * http://www.FreeRTOS.org
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23 * http://aws.amazon.com/freertos
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25 * 1 tab == 4 spaces!
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29 * See https://www.freertos.org/STM32H7_Dual_Core_AMP_RTOS_demo.html for usage
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30 * instructions, and the following blog post for a more detailed explanation
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31 * https://www.freertos.org/articles/001_simple_freertos_core_to_core_communication/simple_freertos_core_to_core_communication_AMP.html
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36 * This example stress tests a simple Asymmetric Multi Processing (AMP) core to
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37 * core communication mechanism implemented using FreeRTOS message buffers:
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38 * https://www.freertos.org/RTOS-stream-message-buffers.html Message buffers
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39 * are used to pass an ASCII representation of an incrementing number (so "0",
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40 * followed by "1", followed by "2", etc.) from a single 'sending' task that
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41 * runs on the Arm Cortex-M7 core (the M7 core) to two "receiving" tasks
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42 * running on the Arm Cortex-M4 core (the M4 core). There are two data message
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43 * buffers, one for each receiving task. To distinguish between the receiving
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44 * tasks one is assigned the task number 0, and the other task number 1.
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46 * The M7 task sits in a loop sending the ascii strings to each M4 task. If a
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47 * receiving task receives the next expected value in the sequence it prints its
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48 * task number to the UART. If a receiving task receives anything else, or its
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49 * attempt to receive data times out, then it hits an assert() that prints an
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50 * error message to the UART before stopping all further processing on the M4
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51 * core. If the example is running correctly you will see lots of "0"s (from
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52 * the receiving task assigned task number 0) and "1"s (from the receiving task
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53 * assigned task number 1) streaming from the UART. The time taken to output
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54 * characters from the UART is the only thing throttling the speed of the core
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55 * to core communication as it causes the message buffers to become full - which
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56 * would probably happen anyway as the M7 core is executing at twice the
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57 * frequency of the M4 core.
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60 * Implementation of sbSEND_COMPLETED()
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61 * ------------------------------------
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63 * sbSEND_COMPLETED is a macro called by FreeRTOS after data has been sent to a
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64 * message buffer in case there was a task blocked on the message buffer waiting
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65 * for data to become available - in which case the waiting task would be
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66 * unblocked: https://www.freertos.org/RTOS-message-buffer-example.html
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67 * However, the default sbSEND_COMPLETED implementation assumes the sending task
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68 * (or interrupt) and the receiving task are under the control of the same
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69 * instance of the FreeRTOS kernel and run on the same MCU core. In this AMP
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70 * example the sending task and the receiving tasks are under the control of two
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71 * different instances of the FreeRTOS kernel, and run on different MCU cores,
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72 * so the default sbSEND_COMPLETED implementation won't work (each FreeRTOS
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73 * kernel instance only knowns about the tasks under its control). AMP
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74 * scenarios therefore require the sbSEND_COMPLETED macro (and potentially the
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75 * sbRECEIVE_COMPLETED macro, see below) to be overridden, which is done by
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76 * simply providing your own implementation in the project's FreeRTOSConfig.h
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77 * file. Note this example has a FreeRTOSConfig.h file used by the application
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78 * that runs on the M7 core and a separate FreeRTOSConfig.h file used by the
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79 * application that runs on the M4 core. The implementation of sbSEND_COMPLETED
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80 * used by the M7 core simply triggers an interrupt in the M4 core. The
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81 * interrupt's handler (the ISR that was triggered by the M7 core but executes
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82 * on the M4 core) must then do the job that would otherwise be done by the
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83 * default implementation of sbSEND_COMPLETE - namely unblock a task if the task
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84 * was waiting to receive data from the message buffer that now contains data.
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85 * There are two data message buffers though, so first ISR must determine which
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86 * of the two contains data.
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88 * This demo only has two data message buffers, so it would be reasonable to
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89 * have the ISR simply query both to see which contained data, but that solution
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90 * would not scale if there are many message buffers, or if the number of
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91 * message buffers was unknown. Therefore, to demonstrate a more scalable
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92 * solution, this example introduced a third message buffer - a 'control'
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93 * message buffer as opposed to a 'data' message buffer. After the task on the
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94 * M7 core writes to a data message buffer it writes the handle of the message
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95 * buffer that contains data to the control message buffer. The ISR running on
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96 * the M4 core then reads from the control message buffer to know which data
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97 * message buffer contains data.
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99 * The above described scenario contains many implementation decisions.
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100 * Alternative methods of enabling the M4 core to know data message buffer
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101 * contains data include:
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103 * 1) Using a different interrupt for each data message buffer.
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104 * 2) Passing all data from the M7 core to the M4 core through a single message
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105 * buffer, along with additional data that tells the ISR running on the M4
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106 * core which task to forward the data to.
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109 * Implementation of sbRECEIVE_COMPLETED()
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110 * ---------------------------------------
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112 * sbRECEIVE_COMPLETED is the complement of sbSEND_COMPLETED. It is a macro
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113 * called by FreeRTOS after data has been read from a message buffer in case
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114 * there was a task blocked on the message buffer waiting for space to become
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115 * available - in which case the waiting task would be unblocked so it can
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116 * complete its write to the buffer.
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118 * In this example the M7 task writes to the message buffers faster than the M4
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119 * tasks read from them (in part because the M7 is running faster, and in part
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120 * because the M4 cores write to the UART), so the buffers become full, and the
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121 * M7 task enters the Blocked state to wait for space to become available. As
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122 * with the sbSEND_COMPLETED macro, the default implementation of the
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123 * sbRECEIVE_COMPLETED macro only works if the sender and receiver are under the
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124 * control of the same instance of FreeRTOS and execute on the same core.
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125 * Therefore, just as the application that executes on the M7 core overrides
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126 * the default implementation of sbSEND_SOMPLETED(), the application that runs
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127 * on the M4 core overrides the default implementation of sbRECEIVE_COMPLETED()
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128 * to likewise generate an interrupt in the M7 core - so sbRECEIVE_COMPLETED()
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129 * executes on the M4 core and generates an interrupt on the M7 core. To keep
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130 * things simple the ISR that runs on the M7 core does not use a control
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131 * message buffer to know which data message buffer contains space, and instead
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132 * simply sends a notification to both data message buffers. Note however that
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133 * this overly simplistic implementation is only acceptable because it is
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134 * known that there is only one sending task, and that task cannot be blocked on
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135 * both message buffers at the same time. Also, sending the notification to the
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136 * data message buffer updates the receiving task's direct to task notification
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137 * state: https://www.freertos.org/RTOS-task-notifications.html which is only ok
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138 * because it is known the task is not using its notification state for any
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143 /* Standard includes. */
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145 #include "string.h"
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147 /* FreeRTOS includes. */
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148 #include "FreeRTOS.h"
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150 #include "message_buffer.h"
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151 #include "MessageBufferLocations.h"
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154 #include "stm32h7xx_hal.h"
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155 #include "stm32h745i_discovery.h"
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157 /* When the cores boot they very crudely wait for each other in a non chip
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158 specific way by waiting for the other core to start incrementing a shared
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159 variable within an array. mainINDEX_TO_TEST sets the index within the array to
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160 the variable this core tests to see if it is incrementing, and
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161 mainINDEX_TO_INCREMENT sets the index within the array to the variable this core
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162 increments to indicate to the other core that it is at the sync point. Note
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163 this is not a foolproof method and it is better to use a hardware specific
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164 solution, such as having one core boot the other core when it was ready, or
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165 using some kind of shared semaphore or interrupt. */
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166 #define mainINDEX_TO_TEST 0
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167 #define mainINDEX_TO_INCREMENT 1
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169 /*-----------------------------------------------------------*/
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172 * Implements the task that sends messages to the M7 core.
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174 static void prvM7CoreTasks( void *pvParameters );
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177 * configSUPPORT_STATIC_ALLOCATION is set to 1, requiring this callback to
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178 * provide statically allocated data for use by the idle task, which is a task
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179 * created by the scheduler when it starts.
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181 void vApplicationGetIdleTaskMemory( StaticTask_t **ppxIdleTaskTCBBuffer, uint32_t **ppxIdleTaskStackBuffer, uint32_t *pulIdleTaskStackSize );
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184 * Just waits to see a variable being incremented by the M4 core to know when
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185 * the M4 has created the message buffers used for core to core communication.
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187 static void prvWaitForOtherCoreToStart( uint32_t ulIndexToTest, uint32_t ulIndexToIncrement );
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190 * Setup the hardware ready to run this demo.
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192 static void prvSetupHardware( void );
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194 /*-----------------------------------------------------------*/
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196 static TaskHandle_t xM7AMPTask = NULL;
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202 /*** See the comments at the top of this page ***/
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204 prvSetupHardware();
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206 /* Create the control and data message buffers, as described at the top of
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207 this file. The message buffers are statically allocated at a known location
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208 as both cores need to know where they are. See MessageBufferLocations.h. */
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209 xControlMessageBuffer = xMessageBufferCreateStatic( /* The buffer size in bytes. */
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210 mbaCONTROL_MESSAGE_BUFFER_SIZE,
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211 /* Statically allocated buffer storage area. */
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212 ucControlBufferStorage,
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213 /* Message buffer handle. */
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214 &xControlMessageBufferStruct );
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215 for( x = 0; x < mbaNUMBER_OF_CORE_2_TASKS; x++ )
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217 xDataMessageBuffers[ x ] = xMessageBufferCreateStatic( mbaTASK_MESSAGE_BUFFER_SIZE,
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218 &( ucDataBufferStorage[ x ][ 0 ] ),
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219 &( xDataMessageBufferStructs[ x ] ) );
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222 /* The message buffers have been initialised so it is safe for both cores to
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223 synchronise their startup. */
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224 prvWaitForOtherCoreToStart( mainINDEX_TO_TEST, mainINDEX_TO_INCREMENT );
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226 /* Start the task that executes on the M7 core. */
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227 xTaskCreate( prvM7CoreTasks, /* Function that implements the task. */
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228 "AMPM7Core", /* Task name, for debugging only. */
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229 configMINIMAL_STACK_SIZE, /* Size of stack (in words) to allocate for this task. */
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230 NULL, /* Task parameter, not used in this case. */
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231 tskIDLE_PRIORITY, /* Task priority. */
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232 &xM7AMPTask ); /* Task handle, used to unblock task from interrupt. */
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234 /* Start scheduler */
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235 vTaskStartScheduler();
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237 /* Will not get here if the scheduler starts successfully. If you do end up
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238 here then there wasn't enough heap memory available to start either the idle
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239 task or the timer/daemon task. https://www.freertos.org/a00111.html */
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242 /*-----------------------------------------------------------*/
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244 static void prvM7CoreTasks( void *pvParameters )
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247 uint32_t ulNextValue = 0;
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248 char cString[ 15 ];
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249 size_t xStringLength;
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251 /* Remove warning about unused parameters. */
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252 ( void ) pvParameters;
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256 /* Create the next string to send. The value is incremented on each
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257 loop iteration, and the length of the string changes as the number of
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258 digits in the value increases. */
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259 sprintf( cString, "%lu", ( unsigned long ) ulNextValue );
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260 xStringLength = strlen( cString );
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262 /* This task runs on the M7 core, use the message buffers to send the
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263 strings to the tasks running on the M4 core. This will result in
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264 sbSEND_COMPLETED() being executed, which in turn will write the handle
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265 of the message buffer written to into xControlMessageBuffer then
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266 generate an interrupt in M4 core. */
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267 for( x = 0; x < mbaNUMBER_OF_CORE_2_TASKS; x++ )
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269 while( xMessageBufferSend( xDataMessageBuffers[ x ],
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270 ( void * ) cString,
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272 portMAX_DELAY ) != xStringLength );
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278 /*-----------------------------------------------------------*/
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280 void vGenerateM7ToM4Interrupt( void * xUpdatedMessageBuffer )
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282 MessageBufferHandle_t xUpdatedBuffer = ( MessageBufferHandle_t ) xUpdatedMessageBuffer;
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284 /* Called by the implementation of sbSEND_COMPLETED() in FreeRTOSConfig.h.
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285 See the comments at the top of this file. Write the handle of the data
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286 message buffer to which data was written to the control message buffer. */
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287 if( xUpdatedBuffer != xControlMessageBuffer )
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289 while( xMessageBufferSend( xControlMessageBuffer, &xUpdatedBuffer, sizeof( xUpdatedBuffer ), mbaDONT_BLOCK ) != sizeof( xUpdatedBuffer ) )
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291 /* Nothing to do here. */
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294 /* Generate interrupt in the M4 core. */
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295 HAL_EXTI_D1_EventInputConfig( EXTI_LINE0, EXTI_MODE_IT, DISABLE );
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296 HAL_EXTI_D2_EventInputConfig( EXTI_LINE0, EXTI_MODE_IT, ENABLE );
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297 HAL_EXTI_GenerateSWInterrupt( EXTI_LINE0 );
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300 /*-----------------------------------------------------------*/
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302 void vApplicationGetIdleTaskMemory( StaticTask_t **ppxIdleTaskTCBBuffer, uint32_t **ppxIdleTaskStackBuffer, uint32_t *pulIdleTaskStackSize )
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304 /* If the buffers to be provided to the Idle task are declared inside this
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305 function then they must be declared static - otherwise they will be allocated on
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306 the stack and so not exists after this function exits. */
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307 static StaticTask_t xIdleTaskTCB;
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308 static uint32_t uxIdleTaskStack[ configMINIMAL_STACK_SIZE ];
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310 /* configUSE_STATIC_ALLOCATION is set to 1, so the application must provide
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311 an implementation of vApplicationGetIdleTaskMemory() to provide the memory
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312 that is used by the Idle task.
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313 https://www.freertos.org/a00110.html#configSUPPORT_STATIC_ALLOCATION */
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315 /* Pass out a pointer to the StaticTask_t structure in which the Idle task's
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316 state will be stored. */
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317 *ppxIdleTaskTCBBuffer = &xIdleTaskTCB;
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319 /* Pass out the array that will be used as the Idle task's stack. */
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320 *ppxIdleTaskStackBuffer = uxIdleTaskStack;
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322 /* Pass out the size of the array pointed to by *ppxIdleTaskStackBuffer.
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323 Note that, as the array is necessarily of type StackType_t,
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324 configMINIMAL_STACK_SIZE is specified in words, not bytes. */
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325 *pulIdleTaskStackSize = configMINIMAL_STACK_SIZE;
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327 /*-----------------------------------------------------------*/
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329 static void prvWaitForOtherCoreToStart( uint32_t ulIndexToTest, uint32_t ulIndexToIncrement )
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331 volatile uint32_t ulInitialCount = ulStartSyncCounters[ ulIndexToTest ], x;
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332 const uint32_t ulCrudeLoopDelay = 0xfffffUL;
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334 /* When the cores boot they very crudely wait for each other in a non chip
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335 specific way by waiting for the other core to start incrementing a shared
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336 variable within an array. mainINDEX_TO_TEST sets the index within the array
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337 to the variable this core tests to see if it is incrementing, and
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338 mainINDEX_TO_INCREMENT sets the index within the array to the variable this
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339 core increments to indicate to the other core that it is at the sync point.
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340 Note this is not a foolproof method and it is better to use a hardware
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341 specific solution, such as having one core boot the other core when it was
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342 ready, or using some kind of shared semaphore or interrupt. */
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344 /* Wait for the other core to reach the synchronisation point. */
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345 while( ulStartSyncCounters[ ulIndexToTest ] == ulInitialCount );
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346 ulInitialCount = ulStartSyncCounters[ ulIndexToTest ];
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350 ulStartSyncCounters[ ulIndexToIncrement ]++;
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351 if( ulStartSyncCounters[ ulIndexToTest ] != ulInitialCount )
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353 ulStartSyncCounters[ ulIndexToIncrement ]++;
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357 /* Unlike the M4 core, this core does not have direct access to the UART,
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358 so simply toggle an LED to show its status. */
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359 for( x = 0; x < ulCrudeLoopDelay; x++ ) __asm volatile( "NOP" );
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360 BSP_LED_Off( LED2 );
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361 for( x = 0; x < ulCrudeLoopDelay; x++ ) __asm volatile( "NOP" );
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362 BSP_LED_On( LED2 );
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365 /*-----------------------------------------------------------*/
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367 void HAL_GPIO_EXTI_Callback( uint16_t GPIO_Pin )
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369 BaseType_t xHigherPriorityTaskWoken = pdFALSE;
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372 configASSERT( xM7AMPTask );
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374 HAL_EXTI_D1_ClearFlag( EXTI_LINE1 );
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376 /* Task can't be blocked on both so just send the notification to both. */
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377 for( x = 0; x < mbaNUMBER_OF_CORE_2_TASKS; x++ )
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379 xMessageBufferReceiveCompletedFromISR( xDataMessageBuffers[ x ], &xHigherPriorityTaskWoken );
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382 /* Normal FreeRTOS "yield from interrupt" semantics, where
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383 xHigherPriorityTaskWoken is initialzed to pdFALSE and will then get set to
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384 pdTRUE if the interrupt unblocks a task that has a priority above that of
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385 the currently executing task. */
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386 portYIELD_FROM_ISR( xHigherPriorityTaskWoken );
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388 /*-----------------------------------------------------------*/
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390 static void prvSetupHardware( void )
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392 MPU_Region_InitTypeDef MPU_InitStruct;
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393 RCC_ClkInitTypeDef RCC_ClkInitStruct;
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394 RCC_OscInitTypeDef RCC_OscInitStruct;
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396 /* Configure the MPU attributes as Not Cachable for Internal D3SRAM. The
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397 Base Address is 0x38000000 (D3_SRAM_BASE), and the size is 64K. */
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399 MPU_InitStruct.Enable = MPU_REGION_ENABLE;
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400 MPU_InitStruct.BaseAddress = D3_SRAM_BASE;
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401 MPU_InitStruct.Size = MPU_REGION_SIZE_64KB;
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402 MPU_InitStruct.AccessPermission = MPU_REGION_FULL_ACCESS;
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403 MPU_InitStruct.IsBufferable = MPU_ACCESS_NOT_BUFFERABLE;
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404 MPU_InitStruct.IsCacheable = MPU_ACCESS_NOT_CACHEABLE;
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405 MPU_InitStruct.IsShareable = MPU_ACCESS_SHAREABLE;
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406 MPU_InitStruct.Number = MPU_REGION_NUMBER0;
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407 MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL0;
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408 MPU_InitStruct.SubRegionDisable = 0x00;
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409 MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_ENABLE;
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410 HAL_MPU_ConfigRegion(&MPU_InitStruct);
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411 HAL_MPU_Enable(MPU_PRIVILEGED_DEFAULT);
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413 /* Enable I-Cache */
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414 SCB_EnableICache();
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416 /* Enable D-Cache */
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417 SCB_EnableDCache();
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420 BSP_LED_Init(LED1);
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424 System Clock Configuration:
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425 System Clock source = PLL (HSE)
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426 SYSCLK(Hz) = 400000000 (Cortex-M7 CPU Clock)
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427 HCLK(Hz) = 200000000 (Cortex-M4 CPU, Bus matrix Clocks)
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429 D1 APB3 Prescaler = 2 (APB3 Clock 100MHz)
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430 D2 APB1 Prescaler = 2 (APB1 Clock 100MHz)
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431 D2 APB2 Prescaler = 2 (APB2 Clock 100MHz)
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432 D3 APB4 Prescaler = 2 (APB4 Clock 100MHz)
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433 HSE Frequency(Hz) = 25000000
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440 Flash Latency(WS) = 4
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443 HAL_PWREx_ConfigSupply(PWR_DIRECT_SMPS_SUPPLY);
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445 /* The voltage scaling allows optimizing the power consumption when the
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446 device is clocked below the maximum system frequency, to update the voltage
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447 scaling value regarding system frequency refer to product datasheet. */
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448 __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
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450 while( !__HAL_PWR_GET_FLAG( PWR_FLAG_VOSRDY ) )
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452 __asm volatile ( "NOP" );
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455 /* Enable HSE Oscillator and activate PLL with HSE as source */
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456 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
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457 RCC_OscInitStruct.HSEState = RCC_HSE_ON;
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458 RCC_OscInitStruct.HSIState = RCC_HSI_OFF;
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459 RCC_OscInitStruct.CSIState = RCC_CSI_OFF;
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460 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
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461 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
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463 RCC_OscInitStruct.PLL.PLLM = 5;
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464 RCC_OscInitStruct.PLL.PLLN = 160;
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465 RCC_OscInitStruct.PLL.PLLFRACN = 0;
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466 RCC_OscInitStruct.PLL.PLLP = 2;
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467 RCC_OscInitStruct.PLL.PLLR = 2;
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468 RCC_OscInitStruct.PLL.PLLQ = 4;
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470 RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE;
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471 RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_2;
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472 configASSERT( HAL_RCC_OscConfig( &RCC_OscInitStruct ) == HAL_OK );
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474 /* Select PLL as system clock source and configure bus clocks dividers */
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475 RCC_ClkInitStruct.ClockType = ( RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_D1PCLK1 | RCC_CLOCKTYPE_PCLK1 | \
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476 RCC_CLOCKTYPE_PCLK2 | RCC_CLOCKTYPE_D3PCLK1 );
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478 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
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479 RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1;
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480 RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2;
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481 RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2;
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482 RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2;
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483 RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2;
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484 RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2;
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485 configASSERT( HAL_RCC_ClockConfig( &RCC_ClkInitStruct, FLASH_LATENCY_4 ) == HAL_OK );
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487 /* AIEC Common configuration: make CPU1 and CPU2 SWI line0 sensitive to
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489 HAL_EXTI_EdgeConfig( EXTI_LINE0, EXTI_RISING_EDGE );
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491 /* Interrupt used for M4 to M7 notifications. */
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492 HAL_NVIC_SetPriority( EXTI1_IRQn, 0xFU, 0U );
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493 HAL_NVIC_EnableIRQ( EXTI1_IRQn );
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