2 * FreeRTOS Kernel V10.2.0
\r
3 * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
\r
5 * Permission is hereby granted, free of charge, to any person obtaining a copy of
\r
6 * this software and associated documentation files (the "Software"), to deal in
\r
7 * the Software without restriction, including without limitation the rights to
\r
8 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
\r
9 * the Software, and to permit persons to whom the Software is furnished to do so,
\r
10 * subject to the following conditions:
\r
12 * The above copyright notice and this permission notice shall be included in all
\r
13 * copies or substantial portions of the Software.
\r
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
\r
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
\r
17 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
\r
18 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
\r
19 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
\r
20 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
\r
22 * http://www.FreeRTOS.org
\r
23 * http://aws.amazon.com/freertos
\r
25 * 1 tab == 4 spaces!
\r
29 * See https://www.freertos.org/STM32H7_Dual_Core_AMP_RTOS_demo.html for usage
\r
30 * instructions (TBD, not available at the time of writing).
\r
35 * This example stress tests a simple Asymmetric Multi Processing (AMP) core to
\r
36 * core communication mechanism implemented using FreeRTOS message buffers:
\r
37 * https://www.freertos.org/RTOS-stream-message-buffers.html Message buffers
\r
38 * are used to pass an ASCII representation of an incrementing number (so "0",
\r
39 * followed by "1", followed by "2", etc.) from a single 'sending' task that
\r
40 * runs on the Arm Cortex-M7 core (the M7 core) to two "receiving" tasks
\r
41 * running on the Arm Cortex-M4 core (the M4 core). There are two data message
\r
42 * buffers, one for each receiving task. To distinguish between the receiving
\r
43 * tasks one is assigned the task number 0, and the other task number 1.
\r
45 * The M7 task sits in a loop sending the ascii strings to each M4 task. If a
\r
46 * receiving task receives the next expected value in the sequence it prints its
\r
47 * task number to the UART. If a receiving task receives anything else, or its
\r
48 * attempt to receive data times out, then it hits an assert() that prints an
\r
49 * error message to the UART before stopping all further processing on the M4
\r
50 * core. If the example is running correctly you will see lots of "0"s (from
\r
51 * the receiving task assigned task number 0) and "1"s (from the receiving task
\r
52 * assigned task number 1) streaming from the UART. The time taken to output
\r
53 * characters from the UART is the only thing throttling the speed of the core
\r
54 * to core communication as it causes the message buffers to become full - which
\r
55 * would probably happen anyway as the M7 core is executing at twice the
\r
56 * frequency of the M4 core.
\r
59 * Implementation of sbSEND_COMPLETED()
\r
60 * ------------------------------------
\r
62 * sbSEND_COMPLETED is a macro called by FreeRTOS after data has been sent to a
\r
63 * message buffer in case there was a task blocked on the message buffer waiting
\r
64 * for data to become available - in which case the waiting task would be
\r
65 * unblocked: https://www.freertos.org/RTOS-message-buffer-example.html
\r
66 * However, the default sbSEND_COMPLETED implementation assumes the sending task
\r
67 * (or interrupt) and the receiving task are under the control of the same
\r
68 * instance of the FreeRTOS kernel and run on the same MCU core. In this AMP
\r
69 * example the sending task and the receiving tasks are under the control of two
\r
70 * different instances of the FreeRTOS kernel, and run on different MCU cores,
\r
71 * so the default sbSEND_COMPLETED implementation won't work (each FreeRTOS
\r
72 * kernel instance only knowns about the tasks under its control). AMP
\r
73 * scenarios therefore require the sbSEND_COMPLETED macro (and potentially the
\r
74 * sbRECEIVE_COMPLETED macro, see below) to be overridden, which is done by
\r
75 * simply providing your own implementation in the project's FreeRTOSConfig.h
\r
76 * file. Note this example has a FreeRTOSConfig.h file used by the application
\r
77 * that runs on the M7 core and a separate FreeRTOSConfig.h file used by the
\r
78 * application that runs on the M4 core. The implementation of sbSEND_COMPLETED
\r
79 * used by the M7 core simply triggers an interrupt in the M4 core. The
\r
80 * interrupt's handler (the ISR that was triggered by the M7 core but executes
\r
81 * on the M4 core) must then do the job that would otherwise be done by the
\r
82 * default implementation of sbSEND_COMPLETE - namely unblock a task if the task
\r
83 * was waiting to receive data from the message buffer that now contains data.
\r
84 * There are two data message buffers though, so first ISR must determine which
\r
85 * of the two contains data.
\r
87 * This demo only has two data message buffers, so it would be reasonable to
\r
88 * have the ISR simply query both to see which contained data, but that solution
\r
89 * would not scale if there are many message buffers, or if the number of
\r
90 * message buffers was unknown. Therefore, to demonstrate a more scalable
\r
91 * solution, this example introduced a third message buffer - a 'control'
\r
92 * message buffer as opposed to a 'data' message buffer. After the task on the
\r
93 * M7 core writes to a data message buffer it writes the handle of the message
\r
94 * buffer that contains data to the control message buffer. The ISR running on
\r
95 * the M4 core then reads from the control message buffer to know which data
\r
96 * message buffer contains data.
\r
98 * The above described scenario contains many implementation decisions.
\r
99 * Alternative methods of enabling the M4 core to know data message buffer
\r
100 * contains data include:
\r
102 * 1) Using a different interrupt for each data message buffer.
\r
103 * 2) Passing all data from the M7 core to the M4 core through a single message
\r
104 * buffer, along with additional data that tells the ISR running on the M4
\r
105 * core which task to forward the data to.
\r
108 * Implementation of sbRECEIVE_COMPLETED()
\r
109 * ---------------------------------------
\r
111 * sbRECEIVE_COMPLETED is the complement of sbSEND_COMPLETED. It is a macro
\r
112 * called by FreeRTOS after data has been read from a message buffer in case
\r
113 * there was a task blocked on the message buffer waiting for space to become
\r
114 * available - in which case the waiting task would be unblocked so it can
\r
115 * complete its write to the buffer.
\r
117 * In this example the M7 task writes to the message buffers faster than the M4
\r
118 * tasks read from them (in part because the M7 is running faster, and in part
\r
119 * because the M4 cores write to the UART), so the buffers become full, and the
\r
120 * M7 task enters the Blocked state to wait for space to become available. As
\r
121 * with the sbSEND_COMPLETED macro, the default implementation of the
\r
122 * sbRECEIVE_COMPLETED macro only works if the sender and receiver are under the
\r
123 * control of the same instance of FreeRTOS and execute on the same core.
\r
124 * Therefore, just as the application that executes on the M7 core overrides
\r
125 * the default implementation of sbSEND_SOMPLETED(), the application that runs
\r
126 * on the M4 core overrides the default implementation of sbRECEIVE_COMPLETED()
\r
127 * to likewise generate an interrupt in the M7 core - so sbRECEIVE_COMPLETED()
\r
128 * executes on the M4 core and generates an interrupt on the M7 core. To keep
\r
129 * things simple the ISR that runs on the M7 core does not use a control
\r
130 * message buffer to know which data message buffer contains space, and instead
\r
131 * simply sends a notification to both data message buffers. Note however that
\r
132 * this overly simplistic implementation is only acceptable because it is
\r
133 * known that there is only one sending task, and that task cannot be blocked on
\r
134 * both message buffers at the same time. Also, sending the notification to the
\r
135 * data message buffer updates the receiving task's direct to task notification
\r
136 * state: https://www.freertos.org/RTOS-task-notifications.html which is only ok
\r
137 * because it is known the task is not using its notification state for any
\r
142 /* Standard includes. */
\r
144 #include "string.h"
\r
146 /* FreeRTOS includes. */
\r
147 #include "FreeRTOS.h"
\r
149 #include "message_buffer.h"
\r
150 #include "MessageBufferLocations.h"
\r
153 #include "stm32h7xx_hal.h"
\r
154 #include "stm32h745i_discovery.h"
\r
156 /* When the cores boot they very crudely wait for each other in a non chip
\r
157 specific way by waiting for the other core to start incrementing a shared
\r
158 variable within an array. mainINDEX_TO_TEST sets the index within the array to
\r
159 the variable this core tests to see if it is incrementing, and
\r
160 mainINDEX_TO_INCREMENT sets the index within the array to the variable this core
\r
161 increments to indicate to the other core that it is at the sync point. Note
\r
162 this is not a foolproof method and it is better to use a hardware specific
\r
163 solution, such as having one core boot the other core when it was ready, or
\r
164 using some kind of shared semaphore or interrupt. */
\r
165 #define mainINDEX_TO_TEST 0
\r
166 #define mainINDEX_TO_INCREMENT 1
\r
168 /*-----------------------------------------------------------*/
\r
171 * Implements the task that sends messages to the M7 core.
\r
173 static void prvM7CoreTasks( void *pvParameters );
\r
176 * configSUPPORT_STATIC_ALLOCATION is set to 1, requiring this callback to
\r
177 * provide statically allocated data for use by the idle task, which is a task
\r
178 * created by the scheduler when it starts.
\r
180 void vApplicationGetIdleTaskMemory( StaticTask_t **ppxIdleTaskTCBBuffer, uint32_t **ppxIdleTaskStackBuffer, uint32_t *pulIdleTaskStackSize );
\r
183 * Just waits to see a variable being incremented by the M4 core to know when
\r
184 * the M4 has created the message buffers used for core to core communication.
\r
186 static void prvWaitForOtherCoreToStart( uint32_t ulIndexToTest, uint32_t ulIndexToIncrement );
\r
189 * Setup the hardware ready to run this demo.
\r
191 static void prvSetupHardware( void );
\r
193 /*-----------------------------------------------------------*/
\r
195 static TaskHandle_t xM7AMPTask = NULL;
\r
201 /*** See the comments at the top of this page ***/
\r
203 prvSetupHardware();
\r
205 /* Create the control and data message buffers, as described at the top of
\r
206 this file. The message buffers are statically allocated at a known location
\r
207 as both cores need to know where they are. See MessageBufferLocations.h. */
\r
208 xControlMessageBuffer = xMessageBufferCreateStatic( /* The buffer size in bytes. */
\r
209 mbaCONTROL_MESSAGE_BUFFER_SIZE,
\r
210 /* Statically allocated buffer storage area. */
\r
211 ucControlBufferStorage,
\r
212 /* Message buffer handle. */
\r
213 &xControlMessageBufferStruct );
\r
214 for( x = 0; x < mbaNUMBER_OF_CORE_2_TASKS; x++ )
\r
216 xDataMessageBuffers[ x ] = xMessageBufferCreateStatic( mbaTASK_MESSAGE_BUFFER_SIZE,
\r
217 &( ucDataBufferStorage[ x ][ 0 ] ),
\r
218 &( xDataMessageBufferStructs[ x ] ) );
\r
221 /* The message buffers have been initialised so it is safe for both cores to
\r
222 synchronise their startup. */
\r
223 prvWaitForOtherCoreToStart( mainINDEX_TO_TEST, mainINDEX_TO_INCREMENT );
\r
225 /* Start the task that executes on the M7 core. */
\r
226 xTaskCreate( prvM7CoreTasks, /* Function that implements the task. */
\r
227 "AMPM7Core", /* Task name, for debugging only. */
\r
228 configMINIMAL_STACK_SIZE, /* Size of stack (in words) to allocate for this task. */
\r
229 NULL, /* Task parameter, not used in this case. */
\r
230 tskIDLE_PRIORITY, /* Task priority. */
\r
231 &xM7AMPTask ); /* Task handle, used to unblock task from interrupt. */
\r
233 /* Start scheduler */
\r
234 vTaskStartScheduler();
\r
236 /* Will not get here if the scheduler starts successfully. If you do end up
\r
237 here then there wasn't enough heap memory available to start either the idle
\r
238 task or the timer/daemon task. https://www.freertos.org/a00111.html */
\r
241 /*-----------------------------------------------------------*/
\r
243 static void prvM7CoreTasks( void *pvParameters )
\r
246 uint32_t ulNextValue = 0;
\r
247 char cString[ 15 ];
\r
248 size_t xStringLength;
\r
250 /* Remove warning about unused parameters. */
\r
251 ( void ) pvParameters;
\r
255 /* Create the next string to send. The value is incremented on each
\r
256 loop iteration, and the length of the string changes as the number of
\r
257 digits in the value increases. */
\r
258 sprintf( cString, "%lu", ( unsigned long ) ulNextValue );
\r
259 xStringLength = strlen( cString );
\r
261 /* This task runs on the M7 core, use the message buffers to send the
\r
262 strings to the tasks running on the M4 core. This will result in
\r
263 sbSEND_COMPLETED() being executed, which in turn will write the handle
\r
264 of the message buffer written to into xControlMessageBuffer then
\r
265 generate an interrupt in M4 core. */
\r
266 for( x = 0; x < mbaNUMBER_OF_CORE_2_TASKS; x++ )
\r
268 while( xMessageBufferSend( xDataMessageBuffers[ x ],
\r
269 ( void * ) cString,
\r
271 portMAX_DELAY ) != xStringLength );
\r
277 /*-----------------------------------------------------------*/
\r
279 void vGenerateM7ToM4Interrupt( void * xUpdatedMessageBuffer )
\r
281 MessageBufferHandle_t xUpdatedBuffer = ( MessageBufferHandle_t ) xUpdatedMessageBuffer;
\r
283 /* Called by the implementation of sbSEND_COMPLETED() in FreeRTOSConfig.h.
\r
284 See the comments at the top of this file. Write the handle of the data
\r
285 message buffer to which data was written to the control message buffer. */
\r
286 if( xUpdatedBuffer != xControlMessageBuffer )
\r
288 while( xMessageBufferSend( xControlMessageBuffer, &xUpdatedBuffer, sizeof( xUpdatedBuffer ), mbaDONT_BLOCK ) != sizeof( xUpdatedBuffer ) )
\r
290 /* Nothing to do here. Note it is very bad to loop in an interrupt
\r
291 service routine. If a loop is really required then defer the
\r
292 routine to a task. */
\r
295 /* Generate interrupt in the M4 core. */
\r
296 HAL_EXTI_D1_EventInputConfig( EXTI_LINE0, EXTI_MODE_IT, DISABLE );
\r
297 HAL_EXTI_D2_EventInputConfig( EXTI_LINE0, EXTI_MODE_IT, ENABLE );
\r
298 HAL_EXTI_GenerateSWInterrupt( EXTI_LINE0 );
\r
301 /*-----------------------------------------------------------*/
\r
303 void vApplicationGetIdleTaskMemory( StaticTask_t **ppxIdleTaskTCBBuffer, uint32_t **ppxIdleTaskStackBuffer, uint32_t *pulIdleTaskStackSize )
\r
305 /* If the buffers to be provided to the Idle task are declared inside this
\r
306 function then they must be declared static - otherwise they will be allocated on
\r
307 the stack and so not exists after this function exits. */
\r
308 static StaticTask_t xIdleTaskTCB;
\r
309 static uint32_t uxIdleTaskStack[ configMINIMAL_STACK_SIZE ];
\r
311 /* configUSE_STATIC_ALLOCATION is set to 1, so the application must provide
\r
312 an implementation of vApplicationGetIdleTaskMemory() to provide the memory
\r
313 that is used by the Idle task.
\r
314 https://www.freertos.org/a00110.html#configSUPPORT_STATIC_ALLOCATION */
\r
316 /* Pass out a pointer to the StaticTask_t structure in which the Idle task's
\r
317 state will be stored. */
\r
318 *ppxIdleTaskTCBBuffer = &xIdleTaskTCB;
\r
320 /* Pass out the array that will be used as the Idle task's stack. */
\r
321 *ppxIdleTaskStackBuffer = uxIdleTaskStack;
\r
323 /* Pass out the size of the array pointed to by *ppxIdleTaskStackBuffer.
\r
324 Note that, as the array is necessarily of type StackType_t,
\r
325 configMINIMAL_STACK_SIZE is specified in words, not bytes. */
\r
326 *pulIdleTaskStackSize = configMINIMAL_STACK_SIZE;
\r
328 /*-----------------------------------------------------------*/
\r
330 static void prvWaitForOtherCoreToStart( uint32_t ulIndexToTest, uint32_t ulIndexToIncrement )
\r
332 volatile uint32_t ulInitialCount = ulStartSyncCounters[ ulIndexToTest ], x;
\r
333 const uint32_t ulCrudeLoopDelay = 0xfffffUL;
\r
335 /* When the cores boot they very crudely wait for each other in a non chip
\r
336 specific way by waiting for the other core to start incrementing a shared
\r
337 variable within an array. mainINDEX_TO_TEST sets the index within the array
\r
338 to the variable this core tests to see if it is incrementing, and
\r
339 mainINDEX_TO_INCREMENT sets the index within the array to the variable this
\r
340 core increments to indicate to the other core that it is at the sync point.
\r
341 Note this is not a foolproof method and it is better to use a hardware
\r
342 specific solution, such as having one core boot the other core when it was
\r
343 ready, or using some kind of shared semaphore or interrupt. */
\r
345 /* Wait for the other core to reach the synchronisation point. */
\r
346 while( ulStartSyncCounters[ ulIndexToTest ] == ulInitialCount );
\r
347 ulInitialCount = ulStartSyncCounters[ ulIndexToTest ];
\r
351 ulStartSyncCounters[ ulIndexToIncrement ]++;
\r
352 if( ulStartSyncCounters[ ulIndexToTest ] != ulInitialCount )
\r
354 ulStartSyncCounters[ ulIndexToIncrement ]++;
\r
358 /* Unlike the M4 core, this core does not have direct access to the UART,
\r
359 so simply toggle an LED to show its status. */
\r
360 for( x = 0; x < ulCrudeLoopDelay; x++ ) __asm volatile( "NOP" );
\r
361 BSP_LED_Off( LED2 );
\r
362 for( x = 0; x < ulCrudeLoopDelay; x++ ) __asm volatile( "NOP" );
\r
363 BSP_LED_On( LED2 );
\r
366 /*-----------------------------------------------------------*/
\r
368 void HAL_GPIO_EXTI_Callback( uint16_t GPIO_Pin )
\r
370 BaseType_t xHigherPriorityTaskWoken = pdFALSE;
\r
373 configASSERT( xM7AMPTask );
\r
375 HAL_EXTI_D1_ClearFlag( EXTI_LINE1 );
\r
377 /* Task can't be blocked on both so just send the notification to both. */
\r
378 for( x = 0; x < mbaNUMBER_OF_CORE_2_TASKS; x++ )
\r
380 xMessageBufferReceiveCompletedFromISR( xDataMessageBuffers[ x ], &xHigherPriorityTaskWoken );
\r
383 /* Normal FreeRTOS "yield from interrupt" semantics, where
\r
384 xHigherPriorityTaskWoken is initialzed to pdFALSE and will then get set to
\r
385 pdTRUE if the interrupt unblocks a task that has a priority above that of
\r
386 the currently executing task. */
\r
387 portYIELD_FROM_ISR( xHigherPriorityTaskWoken );
\r
389 /*-----------------------------------------------------------*/
\r
391 static void prvSetupHardware( void )
\r
393 MPU_Region_InitTypeDef MPU_InitStruct;
\r
394 RCC_ClkInitTypeDef RCC_ClkInitStruct;
\r
395 RCC_OscInitTypeDef RCC_OscInitStruct;
\r
397 /* Configure the MPU attributes as Not Cachable for Internal D3SRAM. The
\r
398 Base Address is 0x38000000 (D3_SRAM_BASE), and the size is 64K. */
\r
400 MPU_InitStruct.Enable = MPU_REGION_ENABLE;
\r
401 MPU_InitStruct.BaseAddress = D3_SRAM_BASE;
\r
402 MPU_InitStruct.Size = MPU_REGION_SIZE_64KB;
\r
403 MPU_InitStruct.AccessPermission = MPU_REGION_FULL_ACCESS;
\r
404 MPU_InitStruct.IsBufferable = MPU_ACCESS_NOT_BUFFERABLE;
\r
405 MPU_InitStruct.IsCacheable = MPU_ACCESS_NOT_CACHEABLE;
\r
406 MPU_InitStruct.IsShareable = MPU_ACCESS_SHAREABLE;
\r
407 MPU_InitStruct.Number = MPU_REGION_NUMBER0;
\r
408 MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL0;
\r
409 MPU_InitStruct.SubRegionDisable = 0x00;
\r
410 MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_ENABLE;
\r
411 HAL_MPU_ConfigRegion(&MPU_InitStruct);
\r
412 HAL_MPU_Enable(MPU_PRIVILEGED_DEFAULT);
\r
414 /* Enable I-Cache */
\r
415 SCB_EnableICache();
\r
417 /* Enable D-Cache */
\r
418 SCB_EnableDCache();
\r
421 BSP_LED_Init(LED1);
\r
425 System Clock Configuration:
\r
426 System Clock source = PLL (HSE)
\r
427 SYSCLK(Hz) = 400000000 (Cortex-M7 CPU Clock)
\r
428 HCLK(Hz) = 200000000 (Cortex-M4 CPU, Bus matrix Clocks)
\r
430 D1 APB3 Prescaler = 2 (APB3 Clock 100MHz)
\r
431 D2 APB1 Prescaler = 2 (APB1 Clock 100MHz)
\r
432 D2 APB2 Prescaler = 2 (APB2 Clock 100MHz)
\r
433 D3 APB4 Prescaler = 2 (APB4 Clock 100MHz)
\r
434 HSE Frequency(Hz) = 25000000
\r
441 Flash Latency(WS) = 4
\r
444 HAL_PWREx_ConfigSupply(PWR_DIRECT_SMPS_SUPPLY);
\r
446 /* The voltage scaling allows optimizing the power consumption when the
\r
447 device is clocked below the maximum system frequency, to update the voltage
\r
448 scaling value regarding system frequency refer to product datasheet. */
\r
449 __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
\r
451 while( !__HAL_PWR_GET_FLAG( PWR_FLAG_VOSRDY ) )
\r
453 __asm volatile ( "NOP" );
\r
456 /* Enable HSE Oscillator and activate PLL with HSE as source */
\r
457 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
\r
458 RCC_OscInitStruct.HSEState = RCC_HSE_ON;
\r
459 RCC_OscInitStruct.HSIState = RCC_HSI_OFF;
\r
460 RCC_OscInitStruct.CSIState = RCC_CSI_OFF;
\r
461 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
\r
462 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
\r
464 RCC_OscInitStruct.PLL.PLLM = 5;
\r
465 RCC_OscInitStruct.PLL.PLLN = 160;
\r
466 RCC_OscInitStruct.PLL.PLLFRACN = 0;
\r
467 RCC_OscInitStruct.PLL.PLLP = 2;
\r
468 RCC_OscInitStruct.PLL.PLLR = 2;
\r
469 RCC_OscInitStruct.PLL.PLLQ = 4;
\r
471 RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE;
\r
472 RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_2;
\r
473 configASSERT( HAL_RCC_OscConfig( &RCC_OscInitStruct ) == HAL_OK );
\r
475 /* Select PLL as system clock source and configure bus clocks dividers */
\r
476 RCC_ClkInitStruct.ClockType = ( RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_D1PCLK1 | RCC_CLOCKTYPE_PCLK1 | \
\r
477 RCC_CLOCKTYPE_PCLK2 | RCC_CLOCKTYPE_D3PCLK1 );
\r
479 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
\r
480 RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1;
\r
481 RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2;
\r
482 RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2;
\r
483 RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2;
\r
484 RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2;
\r
485 RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2;
\r
486 configASSERT( HAL_RCC_ClockConfig( &RCC_ClkInitStruct, FLASH_LATENCY_4 ) == HAL_OK );
\r
488 /* AIEC Common configuration: make CPU1 and CPU2 SWI line0 sensitive to
\r
490 HAL_EXTI_EdgeConfig( EXTI_LINE0, EXTI_RISING_EDGE );
\r
492 /* Interrupt used for M4 to M7 notifications. */
\r
493 HAL_NVIC_SetPriority( EXTI1_IRQn, 0xFU, 0U );
\r
494 HAL_NVIC_EnableIRQ( EXTI1_IRQn );
\r
projects / freertos / blob