4 * \brief Global interrupt management for SAM D20, SAM3 and SAM4 (NVIC based)
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6 * Copyright (c) 2012-2015 Atmel Corporation. All rights reserved.
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12 * Redistribution and use in source and binary forms, with or without
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13 * modification, are permitted provided that the following conditions are met:
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15 * 1. Redistributions of source code must retain the above copyright notice,
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16 * this list of conditions and the following disclaimer.
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18 * 2. Redistributions in binary form must reproduce the above copyright notice,
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19 * this list of conditions and the following disclaimer in the documentation
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20 * and/or other materials provided with the distribution.
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22 * 3. The name of Atmel may not be used to endorse or promote products derived
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23 * from this software without specific prior written permission.
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25 * 4. This software may only be redistributed and used in connection with an
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26 * Atmel microcontroller product.
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28 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
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29 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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30 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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38 * POSSIBILITY OF SUCH DAMAGE.
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44 * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
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47 #ifndef UTILS_INTERRUPT_INTERRUPT_H
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48 #define UTILS_INTERRUPT_INTERRUPT_H
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50 #include <compiler.h>
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58 * \weakgroup interrupt_group
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64 * \name Interrupt Service Routine definition
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70 * \brief Define service routine
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72 * \note For NVIC devices the interrupt service routines are predefined to
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73 * add to vector table in binary generation, so there is no service
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74 * register at run time. The routine collections are in exceptions.h.
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78 ISR(foo_irq_handler)
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80 // Function definition
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85 * \param func Name for the function.
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87 # define ISR(func) \
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91 * \brief Initialize interrupt vectors
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93 * For NVIC the interrupt vectors are put in vector table. So nothing
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94 * to do to initialize them, except defined the vector function with
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97 * This must be called prior to \ref irq_register_handler.
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99 # define irq_initialize_vectors() \
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104 * \brief Register handler for interrupt
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106 * For NVIC the interrupt vectors are put in vector table. So nothing
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107 * to do to register them, except defined the vector function with
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112 irq_initialize_vectors();
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113 irq_register_handler(foo_irq_handler);
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116 * \note The function \a func must be defined with the \ref ISR macro.
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117 * \note The functions prototypes can be found in the device exception header
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118 * files (exceptions.h).
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120 # define irq_register_handler(int_num, int_prio) \
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121 NVIC_ClearPendingIRQ( (IRQn_Type)int_num); \
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122 NVIC_SetPriority( (IRQn_Type)int_num, int_prio); \
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123 NVIC_EnableIRQ( (IRQn_Type)int_num); \
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127 # define cpu_irq_enable() \
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129 g_interrupt_enabled = true; \
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133 # define cpu_irq_disable() \
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137 g_interrupt_enabled = false; \
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140 typedef uint32_t irqflags_t;
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142 #if !defined(__DOXYGEN__)
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143 extern volatile bool g_interrupt_enabled;
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146 #define cpu_irq_is_enabled() (__get_PRIMASK() == 0)
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148 static volatile uint32_t cpu_irq_critical_section_counter;
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149 static volatile bool cpu_irq_prev_interrupt_state;
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151 static inline irqflags_t cpu_irq_save(void)
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153 irqflags_t flags = cpu_irq_is_enabled();
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158 static inline bool cpu_irq_is_enabled_flags(irqflags_t flags)
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163 static inline void cpu_irq_restore(irqflags_t flags)
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165 if (cpu_irq_is_enabled_flags(flags))
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169 void cpu_irq_enter_critical(void);
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170 void cpu_irq_leave_critical(void);
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173 * \weakgroup interrupt_deprecated_group
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177 #define Enable_global_interrupt() cpu_irq_enable()
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178 #define Disable_global_interrupt() cpu_irq_disable()
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179 #define Is_global_interrupt_enabled() cpu_irq_is_enabled()
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189 #endif /* UTILS_INTERRUPT_INTERRUPT_H */
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