4 * Copyright (c) 2015 Atmel Corporation. All rights reserved.
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10 * Redistribution and use in source and binary forms, with or without
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11 * modification, are permitted provided that the following conditions are met:
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13 * 1. Redistributions of source code must retain the above copyright notice,
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14 * this list of conditions and the following disclaimer.
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16 * 2. Redistributions in binary form must reproduce the above copyright notice,
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17 * this list of conditions and the following disclaimer in the documentation
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18 * and/or other materials provided with the distribution.
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20 * 3. The name of Atmel may not be used to endorse or promote products derived
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21 * from this software without specific prior written permission.
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23 * 4. This software may only be redistributed and used in connection with an
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24 * Atmel microcontroller product.
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26 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
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27 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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29 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
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30 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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34 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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35 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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36 * POSSIBILITY OF SUCH DAMAGE.
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42 * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
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45 #ifndef _SAME70_ACC_COMPONENT_
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46 #define _SAME70_ACC_COMPONENT_
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48 /* ============================================================================= */
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49 /** SOFTWARE API DEFINITION FOR Analog Comparator Controller */
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50 /* ============================================================================= */
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51 /** \addtogroup SAME70_ACC Analog Comparator Controller */
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54 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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55 /** \brief Acc hardware registers */
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57 __O uint32_t ACC_CR; /**< \brief (Acc Offset: 0x00) Control Register */
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58 __IO uint32_t ACC_MR; /**< \brief (Acc Offset: 0x04) Mode Register */
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59 __I uint32_t Reserved1[7];
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60 __O uint32_t ACC_IER; /**< \brief (Acc Offset: 0x24) Interrupt Enable Register */
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61 __O uint32_t ACC_IDR; /**< \brief (Acc Offset: 0x28) Interrupt Disable Register */
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62 __I uint32_t ACC_IMR; /**< \brief (Acc Offset: 0x2C) Interrupt Mask Register */
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63 __I uint32_t ACC_ISR; /**< \brief (Acc Offset: 0x30) Interrupt Status Register */
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64 __I uint32_t Reserved2[24];
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65 __IO uint32_t ACC_ACR; /**< \brief (Acc Offset: 0x94) Analog Control Register */
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66 __I uint32_t Reserved3[19];
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67 __IO uint32_t ACC_WPMR; /**< \brief (Acc Offset: 0xE4) Write Protection Mode Register */
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68 __I uint32_t ACC_WPSR; /**< \brief (Acc Offset: 0xE8) Write Protection Status Register */
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70 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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71 /* -------- ACC_CR : (ACC Offset: 0x00) Control Register -------- */
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72 #define ACC_CR_SWRST (0x1u << 0) /**< \brief (ACC_CR) Software Reset */
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73 /* -------- ACC_MR : (ACC Offset: 0x04) Mode Register -------- */
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74 #define ACC_MR_SELMINUS_Pos 0
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75 #define ACC_MR_SELMINUS_Msk (0x7u << ACC_MR_SELMINUS_Pos) /**< \brief (ACC_MR) Selection for Minus Comparator Input */
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76 #define ACC_MR_SELMINUS(value) ((ACC_MR_SELMINUS_Msk & ((value) << ACC_MR_SELMINUS_Pos)))
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77 #define ACC_MR_SELMINUS_TS (0x0u << 0) /**< \brief (ACC_MR) Select TS */
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78 #define ACC_MR_SELMINUS_ADVREFP (0x1u << 0) /**< \brief (ACC_MR) Select ADVREFP */
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79 #define ACC_MR_SELMINUS_DAC0 (0x2u << 0) /**< \brief (ACC_MR) Select DAC0 */
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80 #define ACC_MR_SELMINUS_DAC1 (0x3u << 0) /**< \brief (ACC_MR) Select DAC1 */
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81 #define ACC_MR_SELMINUS_AFE0_AD0 (0x4u << 0) /**< \brief (ACC_MR) Select AFE0_AD0 */
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82 #define ACC_MR_SELMINUS_AFE0_AD1 (0x5u << 0) /**< \brief (ACC_MR) Select AFE0_AD1 */
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83 #define ACC_MR_SELMINUS_AFE0_AD2 (0x6u << 0) /**< \brief (ACC_MR) Select AFE0_AD2 */
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84 #define ACC_MR_SELMINUS_AFE0_AD3 (0x7u << 0) /**< \brief (ACC_MR) Select AFE0_AD3 */
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85 #define ACC_MR_SELPLUS_Pos 4
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86 #define ACC_MR_SELPLUS_Msk (0x7u << ACC_MR_SELPLUS_Pos) /**< \brief (ACC_MR) Selection For Plus Comparator Input */
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87 #define ACC_MR_SELPLUS(value) ((ACC_MR_SELPLUS_Msk & ((value) << ACC_MR_SELPLUS_Pos)))
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88 #define ACC_MR_SELPLUS_AFE0_AD0 (0x0u << 4) /**< \brief (ACC_MR) Select AFE0_AD0 */
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89 #define ACC_MR_SELPLUS_AFE0_AD1 (0x1u << 4) /**< \brief (ACC_MR) Select AFE0_AD1 */
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90 #define ACC_MR_SELPLUS_AFE0_AD2 (0x2u << 4) /**< \brief (ACC_MR) Select AFE0_AD2 */
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91 #define ACC_MR_SELPLUS_AFE0_AD3 (0x3u << 4) /**< \brief (ACC_MR) Select AFE0_AD3 */
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92 #define ACC_MR_SELPLUS_AFE0_AD4 (0x4u << 4) /**< \brief (ACC_MR) Select AFE0_AD4 */
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93 #define ACC_MR_SELPLUS_AFE0_AD5 (0x5u << 4) /**< \brief (ACC_MR) Select AFE0_AD5 */
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94 #define ACC_MR_SELPLUS_AFE1_AD0 (0x6u << 4) /**< \brief (ACC_MR) Select AFE1_AD0 */
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95 #define ACC_MR_SELPLUS_AFE1_AD1 (0x7u << 4) /**< \brief (ACC_MR) Select AFE1_AD1 */
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96 #define ACC_MR_ACEN (0x1u << 8) /**< \brief (ACC_MR) Analog Comparator Enable */
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97 #define ACC_MR_ACEN_DIS (0x0u << 8) /**< \brief (ACC_MR) Analog comparator disabled. */
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98 #define ACC_MR_ACEN_EN (0x1u << 8) /**< \brief (ACC_MR) Analog comparator enabled. */
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99 #define ACC_MR_EDGETYP_Pos 9
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100 #define ACC_MR_EDGETYP_Msk (0x3u << ACC_MR_EDGETYP_Pos) /**< \brief (ACC_MR) Edge Type */
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101 #define ACC_MR_EDGETYP(value) ((ACC_MR_EDGETYP_Msk & ((value) << ACC_MR_EDGETYP_Pos)))
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102 #define ACC_MR_EDGETYP_RISING (0x0u << 9) /**< \brief (ACC_MR) Only rising edge of comparator output */
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103 #define ACC_MR_EDGETYP_FALLING (0x1u << 9) /**< \brief (ACC_MR) Falling edge of comparator output */
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104 #define ACC_MR_EDGETYP_ANY (0x2u << 9) /**< \brief (ACC_MR) Any edge of comparator output */
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105 #define ACC_MR_INV (0x1u << 12) /**< \brief (ACC_MR) Invert Comparator Output */
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106 #define ACC_MR_INV_DIS (0x0u << 12) /**< \brief (ACC_MR) Analog comparator output is directly processed. */
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107 #define ACC_MR_INV_EN (0x1u << 12) /**< \brief (ACC_MR) Analog comparator output is inverted prior to being processed. */
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108 #define ACC_MR_SELFS (0x1u << 13) /**< \brief (ACC_MR) Selection Of Fault Source */
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109 #define ACC_MR_SELFS_CE (0x0u << 13) /**< \brief (ACC_MR) The CE flag is used to drive the FAULT output. */
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110 #define ACC_MR_SELFS_OUTPUT (0x1u << 13) /**< \brief (ACC_MR) The output of the analog comparator flag is used to drive the FAULT output. */
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111 #define ACC_MR_FE (0x1u << 14) /**< \brief (ACC_MR) Fault Enable */
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112 #define ACC_MR_FE_DIS (0x0u << 14) /**< \brief (ACC_MR) The FAULT output is tied to 0. */
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113 #define ACC_MR_FE_EN (0x1u << 14) /**< \brief (ACC_MR) The FAULT output is driven by the signal defined by SELFS. */
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114 /* -------- ACC_IER : (ACC Offset: 0x24) Interrupt Enable Register -------- */
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115 #define ACC_IER_CE (0x1u << 0) /**< \brief (ACC_IER) Comparison Edge */
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116 /* -------- ACC_IDR : (ACC Offset: 0x28) Interrupt Disable Register -------- */
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117 #define ACC_IDR_CE (0x1u << 0) /**< \brief (ACC_IDR) Comparison Edge */
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118 /* -------- ACC_IMR : (ACC Offset: 0x2C) Interrupt Mask Register -------- */
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119 #define ACC_IMR_CE (0x1u << 0) /**< \brief (ACC_IMR) Comparison Edge */
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120 /* -------- ACC_ISR : (ACC Offset: 0x30) Interrupt Status Register -------- */
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121 #define ACC_ISR_CE (0x1u << 0) /**< \brief (ACC_ISR) Comparison Edge (cleared on read) */
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122 #define ACC_ISR_SCO (0x1u << 1) /**< \brief (ACC_ISR) Synchronized Comparator Output */
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123 #define ACC_ISR_MASK (0x1u << 31) /**< \brief (ACC_ISR) Flag Mask */
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124 /* -------- ACC_ACR : (ACC Offset: 0x94) Analog Control Register -------- */
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125 #define ACC_ACR_ISEL (0x1u << 0) /**< \brief (ACC_ACR) Current Selection */
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126 #define ACC_ACR_ISEL_LOPW (0x0u << 0) /**< \brief (ACC_ACR) Low-power option. */
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127 #define ACC_ACR_ISEL_HISP (0x1u << 0) /**< \brief (ACC_ACR) High-speed option. */
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128 #define ACC_ACR_HYST_Pos 1
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129 #define ACC_ACR_HYST_Msk (0x3u << ACC_ACR_HYST_Pos) /**< \brief (ACC_ACR) Hysteresis Selection */
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130 #define ACC_ACR_HYST(value) ((ACC_ACR_HYST_Msk & ((value) << ACC_ACR_HYST_Pos)))
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131 /* -------- ACC_WPMR : (ACC Offset: 0xE4) Write Protection Mode Register -------- */
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132 #define ACC_WPMR_WPEN (0x1u << 0) /**< \brief (ACC_WPMR) Write Protection Enable */
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133 #define ACC_WPMR_WPKEY_Pos 8
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134 #define ACC_WPMR_WPKEY_Msk (0xffffffu << ACC_WPMR_WPKEY_Pos) /**< \brief (ACC_WPMR) Write Protection Key */
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135 #define ACC_WPMR_WPKEY(value) ((ACC_WPMR_WPKEY_Msk & ((value) << ACC_WPMR_WPKEY_Pos)))
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136 #define ACC_WPMR_WPKEY_PASSWD (0x414343u << 8) /**< \brief (ACC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */
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137 /* -------- ACC_WPSR : (ACC Offset: 0xE8) Write Protection Status Register -------- */
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138 #define ACC_WPSR_WPVS (0x1u << 0) /**< \brief (ACC_WPSR) Write Protection Violation Status */
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143 #endif /* _SAME70_ACC_COMPONENT_ */
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