1 /* ----------------------------------------------------------------------------
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2 * ATMEL Microcontroller Software Support
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3 * ----------------------------------------------------------------------------
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4 * Copyright (c) 2010, Atmel Corporation
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6 * All rights reserved.
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8 * Redistribution and use in source and binary forms, with or without
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9 * modification, are permitted provided that the following conditions are met:
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11 * - Redistributions of source code must retain the above copyright notice,
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12 * this list of conditions and the disclaimer below.
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14 * Atmel's name may not be used to endorse or promote products derived from
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15 * this software without specific prior written permission.
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17 * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
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18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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20 * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
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21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
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23 * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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24 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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25 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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26 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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27 * ----------------------------------------------------------------------------
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33 * Interface for the S25fl1 SPI driver.
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37 #ifndef S25FL1_SPI_H
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38 #define S25FL1_SPI_H
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40 /*----------------------------------------------------------------------------
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42 *----------------------------------------------------------------------------*/
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45 /*----------------------------------------------------------------------------
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47 *----------------------------------------------------------------------------*/
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49 #define S25FL1_Size(pS25fl1) ((pS25fl1)->pDesc->size)
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50 #define S25FL1_PageSize(pS25fl1) ((pS25fl1)->pDesc->pageSize)
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51 #define S25FL1_BlockSize(pS25fl1) ((pS25fl1)->pDesc->blockSize)
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52 #define S25FL1_Name(pS25fl1) ((pS25fl1)->pDesc->name)
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53 #define S25FL1_ManId(pS25fl1) (((pS25fl1)->pDesc->jedecId) & 0xFF)
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54 #define S25FL1_PageNumber(pS25fl1) (S25FL1_Size(pS25FL1) / S25FL1_PageSize(pS25fl1))
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55 #define S25FL1_BlockNumber(pS25fl1) (S25FL1_Size(pS25fl1) / S25FL1_BlockSize(pS25fl1))
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56 #define S25FL1_PagePerBlock(pS25fl1) (S25FL1_BlockSize(pS25fl1) / S25FL1_PageSize(pS25fl1))
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57 #define S25FL1_BlockEraseCmd(pS25fl1) ((pS25fl1)->pDesc->blockEraseCmd)
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59 /*----------------------------------------------------------------------------
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61 *----------------------------------------------------------------------------*/
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63 /** Device is protected, operation cannot be carried out. */
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64 #define S25FL1_ERROR_PROTECTED 1
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65 /** Device is busy executing a command. */
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66 #define S25FL1_ERROR_BUSY 2
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67 /** There was a problem while trying to program page data. */
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68 #define S25FL1_ERROR_PROGRAM 3
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69 /** There was an SPI communication error. */
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70 #define S25FL1_ERROR_SPI 4
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72 /** Device ready/busy status bit. */
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73 #define S25FL1_STATUS_RDYBSY (1 << 0)
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74 /** Device is ready. */
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75 #define S25FL1_STATUS_RDYBSY_READY (0 << 0)
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76 /** Device is busy with internal operations. */
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77 #define S25FL1_STATUS_RDYBSY_BUSY (1 << 0)
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78 /** Write enable latch status bit. */
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79 #define S25FL1_STATUS_WEL (1 << 1)
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80 /** Device is not write enabled. */
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81 #define S25FL1_STATUS_WEL_DISABLED (0 << 1)
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82 /** Device is write enabled. */
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83 #define S25FL1_STATUS_WEL_ENABLED (1 << 1)
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84 /** Software protection status bitfield. */
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85 #define S25FL1_STATUS_SWP (3 << 2)
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86 /** All sectors are software protected. */
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87 #define S25FL1_STATUS_SWP_PROTALL (3 << 2)
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88 /** Some sectors are software protected. */
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89 #define S25FL1_STATUS_SWP_PROTSOME (1 << 2)
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90 /** No sector is software protected. */
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91 #define S25FL1_STATUS_SWP_PROTNONE (0 << 2)
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92 /** Write protect pin status bit. */
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93 #define S25FL1_STATUS_WPP (1 << 4)
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94 /** Write protect signal is not asserted. */
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95 #define S25FL1_STATUS_WPP_NOTASSERTED (0 << 4)
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96 /** Write protect signal is asserted. */
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97 #define S25FL1_STATUS_WPP_ASSERTED (1 << 4)
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98 /** Erase/program error bit. */
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99 #define S25FL1_STATUS_EPE (1 << 5)
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100 /** Erase or program operation was successful. */
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101 #define S25FL1_STATUS_EPE_SUCCESS (0 << 5)
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102 /** Erase or program error detected. */
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103 #define S25FL1_STATUS_EPE_ERROR (1 << 5)
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104 /** Sector protection registers locked bit. */
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105 #define S25FL1_STATUS_SPRL (1 << 7)
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106 /** Sector protection registers are unlocked. */
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107 #define S25FL1_STATUS_SPRL_UNLOCKED (0 << 7)
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108 /** Sector protection registers are locked. */
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109 #define S25FL1_STATUS_SPRL_LOCKED (1 << 7)
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111 /** Read array command code. */
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112 #define S25FL1_READ_ARRAY 0x0B
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113 /** Read array (low frequency) command code. */
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114 #define S25FL1_READ_ARRAY_LF 0x03
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115 /** Block erase command code (4K block). */
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116 #define S25FL1_BLOCK_ERASE_4K 0x20
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117 /** Block erase command code (32K block). */
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118 #define S25FL1_BLOCK_ERASE_32K 0x52
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119 /** Block erase command code (64K block). */
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120 #define S25FL1_BLOCK_ERASE_64K 0xD8
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121 /** Chip erase command code 1. */
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122 #define S25FL1_CHIP_ERASE_1 0x60
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123 /** Chip erase command code 2. */
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124 #define S25FL1_CHIP_ERASE_2 0xC7
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125 /** Byte/page program command code. */
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126 #define S25FL1_BYTE_PAGE_PROGRAM 0x02
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127 /** Sequential program mode command code 1. */
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128 #define S25FL1_SEQUENTIAL_PROGRAM_1 0xAD
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129 /** Sequential program mode command code 2. */
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130 #define S25FL1_SEQUENTIAL_PROGRAM_2 0xAF
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131 /** Write enable command code. */
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132 #define S25FL1_WRITE_ENABLE 0x06
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133 /** Write disable command code. */
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134 #define S25FL1_WRITE_DISABLE 0x04
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135 /** Protect sector command code. */
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136 #define S25FL1_PROTECT_SECTOR 0x36
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137 /** Unprotect sector command code. */
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138 #define S25FL1_UNPROTECT_SECTOR 0x39
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139 /** Read sector protection registers command code. */
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140 #define S25FL1_READ_SECTOR_PROT 0x3C
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141 /** Read status register command code. */
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142 #define S25FL1_READ_STATUS 0x05
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143 /** Write status register command code. */
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144 #define S25FL1_WRITE_STATUS 0x01
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145 /** Read manufacturer and device ID command code. */
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146 #define S25FL1_READ_JEDEC_ID 0x9F
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147 /** Deep power-down command code. */
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148 #define S25FL1_DEEP_PDOWN 0xB9
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149 /** Resume from deep power-down command code. */
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150 #define S25FL1_RES_DEEP_PDOWN 0xAB
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152 /* Enter 4-BYTE ADDRESS mode */
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153 #define S25FL1_ENTER_4ADDR_MODE 0xB7
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154 /* Exit 4-BYTE ADDRESS mode */
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155 #define S25FL1_EXIT_4ADDR_MODE 0xE9
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157 /** SPI Flash Manufacturer JEDEC ID */
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158 #define ATMEL_SPI_FLASH 0x1F
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159 #define ST_SPI_FLASH 0x20
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160 #define WINBOND_SPI_FLASH 0xEF
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161 #define MACRONIX_SPI_FLASH 0xC2
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162 #define SST_SPI_FLASH 0xBF
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164 /*----------------------------------------------------------------------------
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166 *----------------------------------------------------------------------------*/
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168 /** Describes a serial firmware flash device parameters. */
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169 typedef struct _S25fl1Desc {
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171 /** Device string name. */
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173 /** JEDEC ID of device. */
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175 /** Size of device in bytes. */
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177 /** Size of one page in bytes. */
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179 /** Block erase size in bytes. */
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180 uint32_t blockSize;
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181 /** Block erase command. */
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182 uint32_t blockEraseCmd;
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187 * Serial flash driver structure. Holds the current state of the driver,
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188 * including the current command and the descriptor for the underlying device.
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190 typedef struct _S25fl1 {
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192 /** Pointer to the underlying QSPI driver. */
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194 /** Current command sent to the QSPI driver. */
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196 /** Pointer to a descriptor for the serial firmware flash device. */
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197 const S25fl1Desc *pDesc;
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198 /** Qspi Command buffer. */
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199 qspiFrame CmdBuffer;
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200 /** Polling mode */
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201 uint32_t pollingMode;
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202 /** Support for 4 byte address mode */
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203 uint32_t fourbytemode;
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206 /*----------------------------------------------------------------------------
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207 * Exported functions
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208 *----------------------------------------------------------------------------*/
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210 extern void S25fl1_Configure(S25fl1 *pS25fl1,
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215 extern uint8_t S25fl1_SendCommand(
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222 QspidCallback callback,
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225 extern uint8_t S25fl1_IsBusy(S25fl1 *pS25fl1);
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227 extern const S25fl1Desc * S25fl1_FindDevice(
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231 #endif /*#ifndef S25FL1_SPI_H */
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