1 /* ---------------------------------------------------------------------------- */
\r
2 /* Atmel Microcontroller Software Support */
\r
3 /* SAM Software Package License */
\r
4 /* ---------------------------------------------------------------------------- */
\r
5 /* Copyright (c) 2014, Atmel Corporation */
\r
7 /* All rights reserved. */
\r
9 /* Redistribution and use in source and binary forms, with or without */
\r
10 /* modification, are permitted provided that the following condition is met: */
\r
12 /* - Redistributions of source code must retain the above copyright notice, */
\r
13 /* this list of conditions and the disclaimer below. */
\r
15 /* Atmel's name may not be used to endorse or promote products derived from */
\r
16 /* this software without specific prior written permission. */
\r
18 /* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
\r
19 /* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
\r
20 /* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
\r
21 /* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
\r
22 /* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
\r
23 /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
\r
24 /* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
\r
25 /* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
\r
26 /* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
\r
27 /* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
\r
28 /* ---------------------------------------------------------------------------- */
\r
30 #ifndef _SAM_DACC_COMPONENT_
\r
31 #define _SAM_DACC_COMPONENT_
\r
33 /* ============================================================================= */
\r
34 /** SOFTWARE API DEFINITION FOR Digital-to-Analog Converter Controller */
\r
35 /* ============================================================================= */
\r
36 /** \addtogroup SAM_DACC Digital-to-Analog Converter Controller */
\r
39 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
\r
40 /** \brief Dacc hardware registers */
\r
42 __O uint32_t DACC_CR; /**< \brief (Dacc Offset: 0x00) Control Register */
\r
43 __IO uint32_t DACC_MR; /**< \brief (Dacc Offset: 0x04) Mode Register */
\r
44 __IO uint32_t DACC_TRIGR; /**< \brief (Dacc Offset: 0x08) Trigger Register */
\r
45 __I uint32_t Reserved1[1];
\r
46 __O uint32_t DACC_CHER; /**< \brief (Dacc Offset: 0x10) Channel Enable Register */
\r
47 __O uint32_t DACC_CHDR; /**< \brief (Dacc Offset: 0x14) Channel Disable Register */
\r
48 __I uint32_t DACC_CHSR; /**< \brief (Dacc Offset: 0x18) Channel Status Register */
\r
49 __O uint32_t DACC_CDR[2]; /**< \brief (Dacc Offset: 0x1C) Conversion Data Register */
\r
50 __O uint32_t DACC_IER; /**< \brief (Dacc Offset: 0x24) Interrupt Enable Register */
\r
51 __O uint32_t DACC_IDR; /**< \brief (Dacc Offset: 0x28) Interrupt Disable Register */
\r
52 __I uint32_t DACC_IMR; /**< \brief (Dacc Offset: 0x2C) Interrupt Mask Register */
\r
53 __I uint32_t DACC_ISR; /**< \brief (Dacc Offset: 0x30) Interrupt Status Register */
\r
54 __I uint32_t Reserved2[24];
\r
55 __IO uint32_t DACC_ACR; /**< \brief (Dacc Offset: 0x94) Analog Current Register */
\r
56 __I uint32_t Reserved3[19];
\r
57 __IO uint32_t DACC_WPMR; /**< \brief (Dacc Offset: 0xE4) Write Protection Mode register */
\r
58 __I uint32_t DACC_WPSR; /**< \brief (Dacc Offset: 0xE8) Write Protection Status register */
\r
60 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
\r
61 /* -------- DACC_CR : (DACC Offset: 0x00) Control Register -------- */
\r
62 #define DACC_CR_SWRST (0x1u << 0) /**< \brief (DACC_CR) Software Reset */
\r
63 /* -------- DACC_MR : (DACC Offset: 0x04) Mode Register -------- */
\r
64 #define DACC_MR_MAXS0 (0x1u << 0) /**< \brief (DACC_MR) Max Speed Mode for Channel 0 */
\r
65 #define DACC_MR_MAXS0_TRIG_EVENT (0x0u << 0) /**< \brief (DACC_MR) Triggered by selected event */
\r
66 #define DACC_MR_MAXS0_MAXIMUM (0x1u << 0) /**< \brief (DACC_MR) Max Speed Mode enabled */
\r
67 #define DACC_MR_MAXS1 (0x1u << 1) /**< \brief (DACC_MR) Max Speed Mode for Channel 1 */
\r
68 #define DACC_MR_MAXS1_TRIG_EVENT (0x0u << 1) /**< \brief (DACC_MR) Triggered by selected event */
\r
69 #define DACC_MR_MAXS1_MAXIMUM (0x1u << 1) /**< \brief (DACC_MR) Max Speed Mode enabled */
\r
70 #define DACC_MR_WORD (0x1u << 4) /**< \brief (DACC_MR) Word Transfer Mode */
\r
71 #define DACC_MR_WORD_DISABLED (0x0u << 4) /**< \brief (DACC_MR) One data to convert is written to the FIFO per access to DACC */
\r
72 #define DACC_MR_WORD_ENABLED (0x1u << 4) /**< \brief (DACC_MR) Two data to convert are written to the FIFO per access to DACC (reduces number of requests to DMA and the number of system bus accesses) */
\r
73 #define DACC_MR_SLEEP (0x1u << 5) /**< \brief (DACC_MR) Sleep Mode */
\r
74 #define DACC_MR_SLEEP_DISABLED (0x0u << 5) /**< \brief (DACC_MR) The DAC Core and reference voltage circuitry are kept ON between conversions.For the first conversion, a startup time defined by the analog cell is applied. Note that in this mode, STARTUP time is only required once, at start up. */
\r
75 #define DACC_MR_SLEEP_ENABLED (0x1u << 5) /**< \brief (DACC_MR) The DAC Core and reference voltage circuitry are OFF between conversions. */
\r
76 #define DACC_MR_REFRESH_Pos 8
\r
77 #define DACC_MR_REFRESH_Msk (0xffu << DACC_MR_REFRESH_Pos) /**< \brief (DACC_MR) Refresh Period */
\r
78 #define DACC_MR_REFRESH(value) ((DACC_MR_REFRESH_Msk & ((value) << DACC_MR_REFRESH_Pos)))
\r
79 #define DACC_MR_DIFF (0x1u << 23) /**< \brief (DACC_MR) Differential Mode */
\r
80 #define DACC_MR_DIFF_DISABLED (0x0u << 23) /**< \brief (DACC_MR) DAC0 and DAC1 outputs can be separately configured */
\r
81 #define DACC_MR_DIFF_ENABLED (0x1u << 23) /**< \brief (DACC_MR) DACP and DACN outputs are configured by the channel 0 value. */
\r
82 #define DACC_MR_PRESCALER_Pos 24
\r
83 #define DACC_MR_PRESCALER_Msk (0xfu << DACC_MR_PRESCALER_Pos) /**< \brief (DACC_MR) Peripheral Clock to DAC Clock Ratio */
\r
84 #define DACC_MR_PRESCALER(value) ((DACC_MR_PRESCALER_Msk & ((value) << DACC_MR_PRESCALER_Pos)))
\r
85 /* -------- DACC_TRIGR : (DACC Offset: 0x08) Trigger Register -------- */
\r
86 #define DACC_TRIGR_TRGEN0 (0x1u << 0) /**< \brief (DACC_TRIGR) Trigger Enable of Channel 0 */
\r
87 #define DACC_TRIGR_TRGEN0_DIS (0x0u << 0) /**< \brief (DACC_TRIGR) External trigger mode disabled. DAC is in free running mode. */
\r
88 #define DACC_TRIGR_TRGEN0_EN (0x1u << 0) /**< \brief (DACC_TRIGR) External trigger mode enabled. */
\r
89 #define DACC_TRIGR_TRGEN1 (0x1u << 1) /**< \brief (DACC_TRIGR) Trigger Enable of Channel 1 */
\r
90 #define DACC_TRIGR_TRGEN1_DIS (0x0u << 1) /**< \brief (DACC_TRIGR) External trigger mode disabled. DAC is in free running mode. */
\r
91 #define DACC_TRIGR_TRGEN1_EN (0x1u << 1) /**< \brief (DACC_TRIGR) External trigger mode enabled. */
\r
92 #define DACC_TRIGR_TRGSEL0_Pos 4
\r
93 #define DACC_TRIGR_TRGSEL0_Msk (0x7u << DACC_TRIGR_TRGSEL0_Pos) /**< \brief (DACC_TRIGR) Trigger Selection of Channel 0 */
\r
94 #define DACC_TRIGR_TRGSEL0_TRGSEL0 (0x0u << 4) /**< \brief (DACC_TRIGR) TRGSEL: Trigger Selection */
\r
95 #define DACC_TRIGR_TRGSEL0_TRGSEL1 (0x1u << 4) /**< \brief (DACC_TRIGR) TRGSEL: Trigger Selection */
\r
96 #define DACC_TRIGR_TRGSEL0_TRGSEL2 (0x2u << 4) /**< \brief (DACC_TRIGR) TRGSEL: Trigger Selection */
\r
97 #define DACC_TRIGR_TRGSEL0_TRGSEL3 (0x3u << 4) /**< \brief (DACC_TRIGR) TRGSEL: Trigger Selection */
\r
98 #define DACC_TRIGR_TRGSEL0_TRGSEL4 (0x4u << 4) /**< \brief (DACC_TRIGR) TRGSEL: Trigger Selection */
\r
99 #define DACC_TRIGR_TRGSEL0_TRGSEL5 (0x5u << 4) /**< \brief (DACC_TRIGR) TRGSEL: Trigger Selection */
\r
100 #define DACC_TRIGR_TRGSEL0_TRGSEL6 (0x6u << 4) /**< \brief (DACC_TRIGR) TRGSEL: Trigger Selection */
\r
101 #define DACC_TRIGR_TRGSEL1_Pos 8
\r
102 #define DACC_TRIGR_TRGSEL1_Msk (0x7u << DACC_TRIGR_TRGSEL1_Pos) /**< \brief (DACC_TRIGR) Trigger Selection of Channel 1 */
\r
103 #define DACC_TRIGR_TRGSEL1_TRGSEL0 (0x0u << 8) /**< \brief (DACC_TRIGR) TRGSEL: Trigger Selection */
\r
104 #define DACC_TRIGR_TRGSEL1_TRGSEL1 (0x1u << 8) /**< \brief (DACC_TRIGR) TRGSEL: Trigger Selection */
\r
105 #define DACC_TRIGR_TRGSEL1_TRGSEL2 (0x2u << 8) /**< \brief (DACC_TRIGR) TRGSEL: Trigger Selection */
\r
106 #define DACC_TRIGR_TRGSEL1_TRGSEL3 (0x3u << 8) /**< \brief (DACC_TRIGR) TRGSEL: Trigger Selection */
\r
107 #define DACC_TRIGR_TRGSEL1_TRGSEL4 (0x4u << 8) /**< \brief (DACC_TRIGR) TRGSEL: Trigger Selection */
\r
108 #define DACC_TRIGR_TRGSEL1_TRGSEL5 (0x5u << 8) /**< \brief (DACC_TRIGR) TRGSEL: Trigger Selection */
\r
109 #define DACC_TRIGR_TRGSEL1_TRGSEL6 (0x6u << 8) /**< \brief (DACC_TRIGR) TRGSEL: Trigger Selection */
\r
110 #define DACC_TRIGR_OSR0_Pos 16
\r
111 #define DACC_TRIGR_OSR0_Msk (0x7u << DACC_TRIGR_OSR0_Pos) /**< \brief (DACC_TRIGR) Over Sampling Ratio of Channel 0 */
\r
112 #define DACC_TRIGR_OSR0_OSR_1 (0x0u << 16) /**< \brief (DACC_TRIGR) OSR = 1 */
\r
113 #define DACC_TRIGR_OSR0_OSR_2 (0x1u << 16) /**< \brief (DACC_TRIGR) OSR = 2 */
\r
114 #define DACC_TRIGR_OSR0_OSR_4 (0x2u << 16) /**< \brief (DACC_TRIGR) OSR = 4 */
\r
115 #define DACC_TRIGR_OSR0_OSR_8 (0x3u << 16) /**< \brief (DACC_TRIGR) OSR = 8 */
\r
116 #define DACC_TRIGR_OSR0_OSR_16 (0x4u << 16) /**< \brief (DACC_TRIGR) OSR = 16 */
\r
117 #define DACC_TRIGR_OSR0_OSR_32 (0x5u << 16) /**< \brief (DACC_TRIGR) OSR = 32 */
\r
118 #define DACC_TRIGR_OSR1_Pos 20
\r
119 #define DACC_TRIGR_OSR1_Msk (0x7u << DACC_TRIGR_OSR1_Pos) /**< \brief (DACC_TRIGR) Over Sampling Ratio of Channel 1 */
\r
120 #define DACC_TRIGR_OSR1_OSR_1 (0x0u << 20) /**< \brief (DACC_TRIGR) OSR = 1 */
\r
121 #define DACC_TRIGR_OSR1_OSR_2 (0x1u << 20) /**< \brief (DACC_TRIGR) OSR = 2 */
\r
122 #define DACC_TRIGR_OSR1_OSR_4 (0x2u << 20) /**< \brief (DACC_TRIGR) OSR = 4 */
\r
123 #define DACC_TRIGR_OSR1_OSR_8 (0x3u << 20) /**< \brief (DACC_TRIGR) OSR = 8 */
\r
124 #define DACC_TRIGR_OSR1_OSR_16 (0x4u << 20) /**< \brief (DACC_TRIGR) OSR = 16 */
\r
125 #define DACC_TRIGR_OSR1_OSR_32 (0x5u << 20) /**< \brief (DACC_TRIGR) OSR = 32 */
\r
126 /* -------- DACC_CHER : (DACC Offset: 0x10) Channel Enable Register -------- */
\r
127 #define DACC_CHER_CH0 (0x1u << 0) /**< \brief (DACC_CHER) Channel 0 Enable */
\r
128 #define DACC_CHER_CH1 (0x1u << 1) /**< \brief (DACC_CHER) Channel 1 Enable */
\r
129 /* -------- DACC_CHDR : (DACC Offset: 0x14) Channel Disable Register -------- */
\r
130 #define DACC_CHDR_CH0 (0x1u << 0) /**< \brief (DACC_CHDR) Channel 0 Disable */
\r
131 #define DACC_CHDR_CH1 (0x1u << 1) /**< \brief (DACC_CHDR) Channel 1 Disable */
\r
132 /* -------- DACC_CHSR : (DACC Offset: 0x18) Channel Status Register -------- */
\r
133 #define DACC_CHSR_CH0 (0x1u << 0) /**< \brief (DACC_CHSR) Channel 0 Status */
\r
134 #define DACC_CHSR_CH1 (0x1u << 1) /**< \brief (DACC_CHSR) Channel 1 Status */
\r
135 #define DACC_CHSR_DACRDY0 (0x1u << 8) /**< \brief (DACC_CHSR) DAC ready flag */
\r
136 #define DACC_CHSR_DACRDY1 (0x1u << 9) /**< \brief (DACC_CHSR) DAC ready flag */
\r
137 /* -------- DACC_CDR[2] : (DACC Offset: 0x1C) Conversion Data Register -------- */
\r
138 #define DACC_CDR_DATA0_Pos 0
\r
139 #define DACC_CDR_DATA0_Msk (0xffffu << DACC_CDR_DATA0_Pos) /**< \brief (DACC_CDR[2]) Data to Convert for channel 0 */
\r
140 #define DACC_CDR_DATA0(value) ((DACC_CDR_DATA0_Msk & ((value) << DACC_CDR_DATA0_Pos)))
\r
141 #define DACC_CDR_DATA1_Pos 16
\r
142 #define DACC_CDR_DATA1_Msk (0xffffu << DACC_CDR_DATA1_Pos) /**< \brief (DACC_CDR[2]) Data to Convert for channel 1 */
\r
143 #define DACC_CDR_DATA1(value) ((DACC_CDR_DATA1_Msk & ((value) << DACC_CDR_DATA1_Pos)))
\r
144 /* -------- DACC_IER : (DACC Offset: 0x24) Interrupt Enable Register -------- */
\r
145 #define DACC_IER_TXRDY0 (0x1u << 0) /**< \brief (DACC_IER) Transmit Ready Interrupt Enable of channel 0 */
\r
146 #define DACC_IER_TXRDY1 (0x1u << 1) /**< \brief (DACC_IER) Transmit Ready Interrupt Enable of channel 1 */
\r
147 #define DACC_IER_EOC0 (0x1u << 4) /**< \brief (DACC_IER) End of Conversion Interrupt Enable of channel 0 */
\r
148 #define DACC_IER_EOC1 (0x1u << 5) /**< \brief (DACC_IER) End of Conversion Interrupt Enable of channel 1 */
\r
149 #define DACC_IER_ENDTX0 (0x1u << 8) /**< \brief (DACC_IER) End of Transmit Buffer Interrupt Enable of channel 0 */
\r
150 #define DACC_IER_ENDTX1 (0x1u << 9) /**< \brief (DACC_IER) End of Transmit Buffer Interrupt Enable of channel 1 */
\r
151 #define DACC_IER_TXBUFE0 (0x1u << 12) /**< \brief (DACC_IER) Transmit Buffer Empty Interrupt Enable of channel 0 */
\r
152 #define DACC_IER_TXBUFE1 (0x1u << 13) /**< \brief (DACC_IER) Transmit Buffer Empty Interrupt Enable of channel 1 */
\r
153 /* -------- DACC_IDR : (DACC Offset: 0x28) Interrupt Disable Register -------- */
\r
154 #define DACC_IDR_TXRDY0 (0x1u << 0) /**< \brief (DACC_IDR) Transmit Ready Interrupt Disable of channel 0 */
\r
155 #define DACC_IDR_TXRDY1 (0x1u << 1) /**< \brief (DACC_IDR) Transmit Ready Interrupt Disable of channel 1 */
\r
156 #define DACC_IDR_EOC0 (0x1u << 4) /**< \brief (DACC_IDR) End of Conversion Interrupt Disable of channel 0 */
\r
157 #define DACC_IDR_EOC1 (0x1u << 5) /**< \brief (DACC_IDR) End of Conversion Interrupt Disable of channel 1 */
\r
158 #define DACC_IDR_ENDTX0 (0x1u << 8) /**< \brief (DACC_IDR) End of Transmit Buffer Interrupt Disable of channel 0 */
\r
159 #define DACC_IDR_ENDTX1 (0x1u << 9) /**< \brief (DACC_IDR) End of Transmit Buffer Interrupt Disable of channel 1 */
\r
160 #define DACC_IDR_TXBUFE0 (0x1u << 12) /**< \brief (DACC_IDR) Transmit Buffer Empty Interrupt Disable of channel 0 */
\r
161 #define DACC_IDR_TXBUFE1 (0x1u << 13) /**< \brief (DACC_IDR) Transmit Buffer Empty Interrupt Disable of channel 1 */
\r
162 /* -------- DACC_IMR : (DACC Offset: 0x2C) Interrupt Mask Register -------- */
\r
163 #define DACC_IMR_TXRDY0 (0x1u << 0) /**< \brief (DACC_IMR) Transmit Ready Interrupt Mask of channel 0 */
\r
164 #define DACC_IMR_TXRDY1 (0x1u << 1) /**< \brief (DACC_IMR) Transmit Ready Interrupt Mask of channel 1 */
\r
165 #define DACC_IMR_EOC0 (0x1u << 4) /**< \brief (DACC_IMR) End of Conversion Interrupt Mask of channel 0 */
\r
166 #define DACC_IMR_EOC1 (0x1u << 5) /**< \brief (DACC_IMR) End of Conversion Interrupt Mask of channel 1 */
\r
167 #define DACC_IMR_ENDTX0 (0x1u << 8) /**< \brief (DACC_IMR) End of Transmit Buffer Interrupt Mask of channel 0 */
\r
168 #define DACC_IMR_ENDTX1 (0x1u << 9) /**< \brief (DACC_IMR) End of Transmit Buffer Interrupt Mask of channel 1 */
\r
169 #define DACC_IMR_TXBUFE0 (0x1u << 12) /**< \brief (DACC_IMR) Transmit Buffer Empty Interrupt Mask of channel 0 */
\r
170 #define DACC_IMR_TXBUFE1 (0x1u << 13) /**< \brief (DACC_IMR) Transmit Buffer Empty Interrupt Mask of channel 1 */
\r
171 /* -------- DACC_ISR : (DACC Offset: 0x30) Interrupt Status Register -------- */
\r
172 #define DACC_ISR_TXRDY0 (0x1u << 0) /**< \brief (DACC_ISR) Transmit Ready Interrupt Flag of channel 0 */
\r
173 #define DACC_ISR_TXRDY1 (0x1u << 1) /**< \brief (DACC_ISR) Transmit Ready Interrupt Flag of channel 1 */
\r
174 #define DACC_ISR_EOC0 (0x1u << 4) /**< \brief (DACC_ISR) End of Conversion Interrupt Flag of channel 0 */
\r
175 #define DACC_ISR_EOC1 (0x1u << 5) /**< \brief (DACC_ISR) End of Conversion Interrupt Flag of channel 1 */
\r
176 #define DACC_ISR_ENDTX0 (0x1u << 8) /**< \brief (DACC_ISR) End of DMA Interrupt Flag of channel 0 */
\r
177 #define DACC_ISR_ENDTX1 (0x1u << 9) /**< \brief (DACC_ISR) End of DMA Interrupt Flag of channel 1 */
\r
178 #define DACC_ISR_TXBUFE0 (0x1u << 12) /**< \brief (DACC_ISR) Transmit Buffer Empty of channel 0 */
\r
179 #define DACC_ISR_TXBUFE1 (0x1u << 13) /**< \brief (DACC_ISR) Transmit Buffer Empty of channel 1 */
\r
180 /* -------- DACC_ACR : (DACC Offset: 0x94) Analog Current Register -------- */
\r
181 #define DACC_ACR_IBCTLCH0_Pos 0
\r
182 #define DACC_ACR_IBCTLCH0_Msk (0x3u << DACC_ACR_IBCTLCH0_Pos) /**< \brief (DACC_ACR) Analog Output Current Control */
\r
183 #define DACC_ACR_IBCTLCH0(value) ((DACC_ACR_IBCTLCH0_Msk & ((value) << DACC_ACR_IBCTLCH0_Pos)))
\r
184 #define DACC_ACR_IBCTLCH1_Pos 2
\r
185 #define DACC_ACR_IBCTLCH1_Msk (0x3u << DACC_ACR_IBCTLCH1_Pos) /**< \brief (DACC_ACR) Analog Output Current Control */
\r
186 #define DACC_ACR_IBCTLCH1(value) ((DACC_ACR_IBCTLCH1_Msk & ((value) << DACC_ACR_IBCTLCH1_Pos)))
\r
187 /* -------- DACC_WPMR : (DACC Offset: 0xE4) Write Protection Mode register -------- */
\r
188 #define DACC_WPMR_WPEN (0x1u << 0) /**< \brief (DACC_WPMR) Write Protection Enable */
\r
189 #define DACC_WPMR_WPKEY_Pos 8
\r
190 #define DACC_WPMR_WPKEY_Msk (0xffffffu << DACC_WPMR_WPKEY_Pos) /**< \brief (DACC_WPMR) Write Protect Key */
\r
191 #define DACC_WPMR_WPKEY_PASSWD (0x444143u << 8) /**< \brief (DACC_WPMR) Writing any other value in this field aborts the write operation of bit WPEN.Always reads as 0. */
\r
192 /* -------- DACC_WPSR : (DACC Offset: 0xE8) Write Protection Status register -------- */
\r
193 #define DACC_WPSR_WPVS (0x1u << 0) /**< \brief (DACC_WPSR) Write Protection Violation Status */
\r
194 #define DACC_WPSR_WPVSRC_Pos 8
\r
195 #define DACC_WPSR_WPVSRC_Msk (0xffu << DACC_WPSR_WPVSRC_Pos) /**< \brief (DACC_WPSR) Write Protection Violation Source */
\r
200 #endif /* _SAM_DACC_COMPONENT_ */
\r
projects / freertos / blob