1 /* ---------------------------------------------------------------------------- */
\r
2 /* Atmel Microcontroller Software Support */
\r
3 /* SAM Software Package License */
\r
4 /* ---------------------------------------------------------------------------- */
\r
5 /* Copyright (c) 2014, Atmel Corporation */
\r
7 /* All rights reserved. */
\r
9 /* Redistribution and use in source and binary forms, with or without */
\r
10 /* modification, are permitted provided that the following condition is met: */
\r
12 /* - Redistributions of source code must retain the above copyright notice, */
\r
13 /* this list of conditions and the disclaimer below. */
\r
15 /* Atmel's name may not be used to endorse or promote products derived from */
\r
16 /* this software without specific prior written permission. */
\r
18 /* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
\r
19 /* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
\r
20 /* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
\r
21 /* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
\r
22 /* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
\r
23 /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
\r
24 /* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
\r
25 /* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
\r
26 /* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
\r
27 /* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
\r
28 /* ---------------------------------------------------------------------------- */
\r
30 #ifndef _SAM_ICM_COMPONENT_
\r
31 #define _SAM_ICM_COMPONENT_
\r
33 /* ============================================================================= */
\r
34 /** SOFTWARE API DEFINITION FOR Integrity Check Monitor */
\r
35 /* ============================================================================= */
\r
36 /** \addtogroup SAM_ICM Integrity Check Monitor */
\r
39 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
\r
40 /** \brief Icm hardware registers */
\r
42 __IO uint32_t ICM_CFG; /**< \brief (Icm Offset: 0x00) Configuration Register */
\r
43 __O uint32_t ICM_CTRL; /**< \brief (Icm Offset: 0x04) Control Register */
\r
44 __O uint32_t ICM_SR; /**< \brief (Icm Offset: 0x08) Status Register */
\r
45 __I uint32_t Reserved1[1];
\r
46 __O uint32_t ICM_IER; /**< \brief (Icm Offset: 0x10) Interrupt Enable Register */
\r
47 __O uint32_t ICM_IDR; /**< \brief (Icm Offset: 0x14) Interrupt Disable Register */
\r
48 __I uint32_t ICM_IMR; /**< \brief (Icm Offset: 0x18) Interrupt Mask Register */
\r
49 __I uint32_t ICM_ISR; /**< \brief (Icm Offset: 0x1C) Interrupt Status Register */
\r
50 __I uint32_t ICM_UASR; /**< \brief (Icm Offset: 0x20) Undefined Access Status Register */
\r
51 __I uint32_t Reserved2[3];
\r
52 __IO uint32_t ICM_DSCR; /**< \brief (Icm Offset: 0x30) Region Descriptor Area Start Address Register */
\r
53 __IO uint32_t ICM_HASH; /**< \brief (Icm Offset: 0x34) Region Hash Area Start Address Register */
\r
54 __O uint32_t ICM_UIHVAL[8]; /**< \brief (Icm Offset: 0x38) User Initial Hash Value 0 Register */
\r
55 __I uint32_t Reserved3[37];
\r
56 __I uint32_t ICM_ADDRSIZE; /**< \brief (Icm Offset: 0xEC) Address Size Register */
\r
57 __I uint32_t ICM_IPNAME[2]; /**< \brief (Icm Offset: 0xF0) IP Name 1 Register */
\r
58 __I uint32_t ICM_FEATURES; /**< \brief (Icm Offset: 0xF8) Feature Register */
\r
59 __I uint32_t ICM_VERSION; /**< \brief (Icm Offset: 0xFC) Version Register */
\r
61 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
\r
62 /* -------- ICM_CFG : (ICM Offset: 0x00) Configuration Register -------- */
\r
63 #define ICM_CFG_WBDIS (0x1u << 0) /**< \brief (ICM_CFG) Write Back Disable */
\r
64 #define ICM_CFG_EOMDIS (0x1u << 1) /**< \brief (ICM_CFG) End of Monitoring Disable */
\r
65 #define ICM_CFG_SLBDIS (0x1u << 2) /**< \brief (ICM_CFG) Secondary List Branching Disable */
\r
66 #define ICM_CFG_BBC_Pos 4
\r
67 #define ICM_CFG_BBC_Msk (0xfu << ICM_CFG_BBC_Pos) /**< \brief (ICM_CFG) Bus Burden Control */
\r
68 #define ICM_CFG_BBC(value) ((ICM_CFG_BBC_Msk & ((value) << ICM_CFG_BBC_Pos)))
\r
69 #define ICM_CFG_ASCD (0x1u << 8) /**< \brief (ICM_CFG) Automatic Switch To Compare Digest */
\r
70 #define ICM_CFG_DUALBUFF (0x1u << 9) /**< \brief (ICM_CFG) Dual Input Buffer */
\r
71 #define ICM_CFG_UIHASH (0x1u << 12) /**< \brief (ICM_CFG) User Initial Hash Value */
\r
72 #define ICM_CFG_UALGO_Pos 13
\r
73 #define ICM_CFG_UALGO_Msk (0x7u << ICM_CFG_UALGO_Pos) /**< \brief (ICM_CFG) User SHA Algorithm */
\r
74 #define ICM_CFG_UALGO_SHA1 (0x0u << 13) /**< \brief (ICM_CFG) SHA1 algorithm processed */
\r
75 #define ICM_CFG_UALGO_SHA256 (0x1u << 13) /**< \brief (ICM_CFG) SHA256 algorithm processed */
\r
76 #define ICM_CFG_UALGO_SHA224 (0x4u << 13) /**< \brief (ICM_CFG) SHA224 algorithm processed */
\r
77 #define ICM_CFG_HAPROT_Pos 16
\r
78 #define ICM_CFG_HAPROT_Msk (0x3fu << ICM_CFG_HAPROT_Pos) /**< \brief (ICM_CFG) Region Hash Area Protection */
\r
79 #define ICM_CFG_HAPROT(value) ((ICM_CFG_HAPROT_Msk & ((value) << ICM_CFG_HAPROT_Pos)))
\r
80 #define ICM_CFG_DAPROT_Pos 24
\r
81 #define ICM_CFG_DAPROT_Msk (0x3fu << ICM_CFG_DAPROT_Pos) /**< \brief (ICM_CFG) Region Descriptor Area Protection */
\r
82 #define ICM_CFG_DAPROT(value) ((ICM_CFG_DAPROT_Msk & ((value) << ICM_CFG_DAPROT_Pos)))
\r
83 /* -------- ICM_CTRL : (ICM Offset: 0x04) Control Register -------- */
\r
84 #define ICM_CTRL_ENABLE (0x1u << 0) /**< \brief (ICM_CTRL) ICM Enable */
\r
85 #define ICM_CTRL_DISABLE (0x1u << 1) /**< \brief (ICM_CTRL) ICM Disable Register */
\r
86 #define ICM_CTRL_SWRST (0x1u << 2) /**< \brief (ICM_CTRL) Software Reset */
\r
87 #define ICM_CTRL_REHASH_Pos 4
\r
88 #define ICM_CTRL_REHASH_Msk (0xfu << ICM_CTRL_REHASH_Pos) /**< \brief (ICM_CTRL) Recompute Internal Hash */
\r
89 #define ICM_CTRL_REHASH(value) ((ICM_CTRL_REHASH_Msk & ((value) << ICM_CTRL_REHASH_Pos)))
\r
90 #define ICM_CTRL_RMDIS_Pos 8
\r
91 #define ICM_CTRL_RMDIS_Msk (0xfu << ICM_CTRL_RMDIS_Pos) /**< \brief (ICM_CTRL) Region Monitoring Disable */
\r
92 #define ICM_CTRL_RMDIS(value) ((ICM_CTRL_RMDIS_Msk & ((value) << ICM_CTRL_RMDIS_Pos)))
\r
93 #define ICM_CTRL_RMEN_Pos 12
\r
94 #define ICM_CTRL_RMEN_Msk (0xfu << ICM_CTRL_RMEN_Pos) /**< \brief (ICM_CTRL) Region Monitoring Enable */
\r
95 #define ICM_CTRL_RMEN(value) ((ICM_CTRL_RMEN_Msk & ((value) << ICM_CTRL_RMEN_Pos)))
\r
96 /* -------- ICM_SR : (ICM Offset: 0x08) Status Register -------- */
\r
97 #define ICM_SR_ENABLE (0x1u << 0) /**< \brief (ICM_SR) ICM Controller Enable Register */
\r
98 #define ICM_SR_RAWRMDIS_Pos 8
\r
99 #define ICM_SR_RAWRMDIS_Msk (0xfu << ICM_SR_RAWRMDIS_Pos) /**< \brief (ICM_SR) RAW Region Monitoring Disabled Status */
\r
100 #define ICM_SR_RAWRMDIS(value) ((ICM_SR_RAWRMDIS_Msk & ((value) << ICM_SR_RAWRMDIS_Pos)))
\r
101 #define ICM_SR_RMDIS_Pos 12
\r
102 #define ICM_SR_RMDIS_Msk (0xfu << ICM_SR_RMDIS_Pos) /**< \brief (ICM_SR) Region Monitoring Disabled Status */
\r
103 #define ICM_SR_RMDIS(value) ((ICM_SR_RMDIS_Msk & ((value) << ICM_SR_RMDIS_Pos)))
\r
104 /* -------- ICM_IER : (ICM Offset: 0x10) Interrupt Enable Register -------- */
\r
105 #define ICM_IER_RHC_Pos 0
\r
106 #define ICM_IER_RHC_Msk (0xfu << ICM_IER_RHC_Pos) /**< \brief (ICM_IER) Region Hash Completed Interrupt Enable */
\r
107 #define ICM_IER_RHC(value) ((ICM_IER_RHC_Msk & ((value) << ICM_IER_RHC_Pos)))
\r
108 #define ICM_IER_RDM_Pos 4
\r
109 #define ICM_IER_RDM_Msk (0xfu << ICM_IER_RDM_Pos) /**< \brief (ICM_IER) Region Digest Mismatch Interrupt Enable */
\r
110 #define ICM_IER_RDM(value) ((ICM_IER_RDM_Msk & ((value) << ICM_IER_RDM_Pos)))
\r
111 #define ICM_IER_RBE_Pos 8
\r
112 #define ICM_IER_RBE_Msk (0xfu << ICM_IER_RBE_Pos) /**< \brief (ICM_IER) Region Bus Error Interrupt Enable */
\r
113 #define ICM_IER_RBE(value) ((ICM_IER_RBE_Msk & ((value) << ICM_IER_RBE_Pos)))
\r
114 #define ICM_IER_RWC_Pos 12
\r
115 #define ICM_IER_RWC_Msk (0xfu << ICM_IER_RWC_Pos) /**< \brief (ICM_IER) Region Wrap Condition detected Interrupt Enable */
\r
116 #define ICM_IER_RWC(value) ((ICM_IER_RWC_Msk & ((value) << ICM_IER_RWC_Pos)))
\r
117 #define ICM_IER_REC_Pos 16
\r
118 #define ICM_IER_REC_Msk (0xfu << ICM_IER_REC_Pos) /**< \brief (ICM_IER) Region End bit Condition Detected Interrupt Enable */
\r
119 #define ICM_IER_REC(value) ((ICM_IER_REC_Msk & ((value) << ICM_IER_REC_Pos)))
\r
120 #define ICM_IER_RSU_Pos 20
\r
121 #define ICM_IER_RSU_Msk (0xfu << ICM_IER_RSU_Pos) /**< \brief (ICM_IER) Region Status Updated Interrupt Disable */
\r
122 #define ICM_IER_RSU(value) ((ICM_IER_RSU_Msk & ((value) << ICM_IER_RSU_Pos)))
\r
123 #define ICM_IER_URAD (0x1u << 24) /**< \brief (ICM_IER) Undefined Register Access Detection Interrupt Enable */
\r
124 /* -------- ICM_IDR : (ICM Offset: 0x14) Interrupt Disable Register -------- */
\r
125 #define ICM_IDR_RHC_Pos 0
\r
126 #define ICM_IDR_RHC_Msk (0xfu << ICM_IDR_RHC_Pos) /**< \brief (ICM_IDR) Region Hash Completed Interrupt Disable */
\r
127 #define ICM_IDR_RHC(value) ((ICM_IDR_RHC_Msk & ((value) << ICM_IDR_RHC_Pos)))
\r
128 #define ICM_IDR_RDM_Pos 4
\r
129 #define ICM_IDR_RDM_Msk (0xfu << ICM_IDR_RDM_Pos) /**< \brief (ICM_IDR) Region Digest Mismatch Interrupt Disable */
\r
130 #define ICM_IDR_RDM(value) ((ICM_IDR_RDM_Msk & ((value) << ICM_IDR_RDM_Pos)))
\r
131 #define ICM_IDR_RBE_Pos 8
\r
132 #define ICM_IDR_RBE_Msk (0xfu << ICM_IDR_RBE_Pos) /**< \brief (ICM_IDR) Region Bus Error Interrupt Disable */
\r
133 #define ICM_IDR_RBE(value) ((ICM_IDR_RBE_Msk & ((value) << ICM_IDR_RBE_Pos)))
\r
134 #define ICM_IDR_RWC_Pos 12
\r
135 #define ICM_IDR_RWC_Msk (0xfu << ICM_IDR_RWC_Pos) /**< \brief (ICM_IDR) Region Wrap Condition Detected Interrupt Disable */
\r
136 #define ICM_IDR_RWC(value) ((ICM_IDR_RWC_Msk & ((value) << ICM_IDR_RWC_Pos)))
\r
137 #define ICM_IDR_REC_Pos 16
\r
138 #define ICM_IDR_REC_Msk (0xfu << ICM_IDR_REC_Pos) /**< \brief (ICM_IDR) Region End bit Condition detected Interrupt Disable */
\r
139 #define ICM_IDR_REC(value) ((ICM_IDR_REC_Msk & ((value) << ICM_IDR_REC_Pos)))
\r
140 #define ICM_IDR_RSU_Pos 20
\r
141 #define ICM_IDR_RSU_Msk (0xfu << ICM_IDR_RSU_Pos) /**< \brief (ICM_IDR) Region Status Updated Interrupt Disable */
\r
142 #define ICM_IDR_RSU(value) ((ICM_IDR_RSU_Msk & ((value) << ICM_IDR_RSU_Pos)))
\r
143 #define ICM_IDR_URAD (0x1u << 24) /**< \brief (ICM_IDR) Undefined Register Access Detection Interrupt Disable */
\r
144 /* -------- ICM_IMR : (ICM Offset: 0x18) Interrupt Mask Register -------- */
\r
145 #define ICM_IMR_RHC_Pos 0
\r
146 #define ICM_IMR_RHC_Msk (0xfu << ICM_IMR_RHC_Pos) /**< \brief (ICM_IMR) Region Hash Completed Interrupt Mask */
\r
147 #define ICM_IMR_RDM_Pos 4
\r
148 #define ICM_IMR_RDM_Msk (0xfu << ICM_IMR_RDM_Pos) /**< \brief (ICM_IMR) Region Digest Mismatch Interrupt Mask */
\r
149 #define ICM_IMR_RBE_Pos 8
\r
150 #define ICM_IMR_RBE_Msk (0xfu << ICM_IMR_RBE_Pos) /**< \brief (ICM_IMR) Region Bus Error Interrupt Mask */
\r
151 #define ICM_IMR_RWC_Pos 12
\r
152 #define ICM_IMR_RWC_Msk (0xfu << ICM_IMR_RWC_Pos) /**< \brief (ICM_IMR) Region Wrap Condition Detected Interrupt Mask */
\r
153 #define ICM_IMR_REC_Pos 16
\r
154 #define ICM_IMR_REC_Msk (0xfu << ICM_IMR_REC_Pos) /**< \brief (ICM_IMR) Region End bit Condition Detected Interrupt Mask */
\r
155 #define ICM_IMR_RSU_Pos 20
\r
156 #define ICM_IMR_RSU_Msk (0xfu << ICM_IMR_RSU_Pos) /**< \brief (ICM_IMR) Region Status Updated Interrupt Mask */
\r
157 #define ICM_IMR_URAD (0x1u << 24) /**< \brief (ICM_IMR) Undefined Register Access Detection Interrupt Mask */
\r
158 /* -------- ICM_ISR : (ICM Offset: 0x1C) Interrupt Status Register -------- */
\r
159 #define ICM_ISR_RHC_Pos 0
\r
160 #define ICM_ISR_RHC_Msk (0xfu << ICM_ISR_RHC_Pos) /**< \brief (ICM_ISR) Region Hash Completed */
\r
161 #define ICM_ISR_RDM_Pos 4
\r
162 #define ICM_ISR_RDM_Msk (0xfu << ICM_ISR_RDM_Pos) /**< \brief (ICM_ISR) Region Digest Mismatch */
\r
163 #define ICM_ISR_RBE_Pos 8
\r
164 #define ICM_ISR_RBE_Msk (0xfu << ICM_ISR_RBE_Pos) /**< \brief (ICM_ISR) Region Bus Error */
\r
165 #define ICM_ISR_RWC_Pos 12
\r
166 #define ICM_ISR_RWC_Msk (0xfu << ICM_ISR_RWC_Pos) /**< \brief (ICM_ISR) Region Wrap Condition Detected */
\r
167 #define ICM_ISR_REC_Pos 16
\r
168 #define ICM_ISR_REC_Msk (0xfu << ICM_ISR_REC_Pos) /**< \brief (ICM_ISR) Region End bit Condition Detected */
\r
169 #define ICM_ISR_RSU_Pos 20
\r
170 #define ICM_ISR_RSU_Msk (0xfu << ICM_ISR_RSU_Pos) /**< \brief (ICM_ISR) Region Status Updated Detected */
\r
171 #define ICM_ISR_URAD (0x1u << 24) /**< \brief (ICM_ISR) Undefined Register Access Detection Status */
\r
172 /* -------- ICM_UASR : (ICM Offset: 0x20) Undefined Access Status Register -------- */
\r
173 #define ICM_UASR_URAT_Pos 0
\r
174 #define ICM_UASR_URAT_Msk (0x7u << ICM_UASR_URAT_Pos) /**< \brief (ICM_UASR) Undefined Register Access Trace */
\r
175 #define ICM_UASR_URAT_UNSPEC_STRUCT_MEMBER (0x0u << 0) /**< \brief (ICM_UASR) Unspecified structure member set to one detected when the descriptor is loaded. */
\r
176 #define ICM_UASR_URAT_ICM_CFG_MODIFIED (0x1u << 0) /**< \brief (ICM_UASR) ICM_CFG modified during active monitoring. */
\r
177 #define ICM_UASR_URAT_ICM_DSCR_MODIFIED (0x2u << 0) /**< \brief (ICM_UASR) ICM_DSCR modified during active monitoring. */
\r
178 #define ICM_UASR_URAT_ICM_HASH_MODIFIED (0x3u << 0) /**< \brief (ICM_UASR) ICM_HASH modified during active monitoring */
\r
179 #define ICM_UASR_URAT_READ_ACCESS (0x4u << 0) /**< \brief (ICM_UASR) Write-only register read access */
\r
180 /* -------- ICM_DSCR : (ICM Offset: 0x30) Region Descriptor Area Start Address Register -------- */
\r
181 #define ICM_DSCR_DASA_Pos 6
\r
182 #define ICM_DSCR_DASA_Msk (0x3ffffffu << ICM_DSCR_DASA_Pos) /**< \brief (ICM_DSCR) Descriptor Area Start Address */
\r
183 #define ICM_DSCR_DASA(value) ((ICM_DSCR_DASA_Msk & ((value) << ICM_DSCR_DASA_Pos)))
\r
184 /* -------- ICM_HASH : (ICM Offset: 0x34) Region Hash Area Start Address Register -------- */
\r
185 #define ICM_HASH_HASA_Pos 7
\r
186 #define ICM_HASH_HASA_Msk (0x1ffffffu << ICM_HASH_HASA_Pos) /**< \brief (ICM_HASH) Hash Area Start Address */
\r
187 #define ICM_HASH_HASA(value) ((ICM_HASH_HASA_Msk & ((value) << ICM_HASH_HASA_Pos)))
\r
188 /* -------- ICM_UIHVAL[8] : (ICM Offset: 0x38) User Initial Hash Value 0 Register -------- */
\r
189 #define ICM_UIHVAL_VAL_Pos 0
\r
190 #define ICM_UIHVAL_VAL_Msk (0xffffffffu << ICM_UIHVAL_VAL_Pos) /**< \brief (ICM_UIHVAL[8]) Initial Hash Value */
\r
191 #define ICM_UIHVAL_VAL(value) ((ICM_UIHVAL_VAL_Msk & ((value) << ICM_UIHVAL_VAL_Pos)))
\r
192 /* -------- ICM_ADDRSIZE : (ICM Offset: 0xEC) Address Size Register -------- */
\r
193 #define ICM_ADDRSIZE_ADDRSIZE_Pos 0
\r
194 #define ICM_ADDRSIZE_ADDRSIZE_Msk (0xffffu << ICM_ADDRSIZE_ADDRSIZE_Pos) /**< \brief (ICM_ADDRSIZE) Peripheral Bus Address Area Size */
\r
195 /* -------- ICM_IPNAME[2] : (ICM Offset: 0xF0) IP Name 1 Register -------- */
\r
196 #define ICM_IPNAME_IPNAME_Pos 0
\r
197 #define ICM_IPNAME_IPNAME_Msk (0xffffffffu << ICM_IPNAME_IPNAME_Pos) /**< \brief (ICM_IPNAME[2]) IP Name in ASCII Format */
\r
198 /* -------- ICM_FEATURES : (ICM Offset: 0xF8) Feature Register -------- */
\r
199 #define ICM_FEATURES_CFGALGO (0x1u << 0) /**< \brief (ICM_FEATURES) Configurable Algorithms */
\r
200 #define ICM_FEATURES_RFU (0x1u << 1) /**< \brief (ICM_FEATURES) Reserved for Future Use */
\r
201 #define ICM_FEATURES_CFGPP (0x1u << 2) /**< \brief (ICM_FEATURES) Configurable Processing Period */
\r
202 #define ICM_FEATURES_HDPP (0x1u << 3) /**< \brief (ICM_FEATURES) Hardcoded Processing Period */
\r
203 #define ICM_FEATURES_PDC (0x1u << 4) /**< \brief (ICM_FEATURES) Peripheral DMA Logic */
\r
204 #define ICM_FEATURES_NAIS (0x1u << 5) /**< \brief (ICM_FEATURES) No Access to Intermediate State */
\r
205 #define ICM_FEATURES_EF (0x1u << 6) /**< \brief (ICM_FEATURES) Embedded LFSR */
\r
206 #define ICM_FEATURES_SI (0x1u << 7) /**< \brief (ICM_FEATURES) Scan Intrusion */
\r
207 #define ICM_FEATURES_BTYP (0x1u << 8) /**< \brief (ICM_FEATURES) Bridge Type */
\r
208 #define ICM_FEATURES_PDCOFF0C (0x1u << 9) /**< \brief (ICM_FEATURES) PDC Offset is 0x0C */
\r
209 #define ICM_FEATURES_HSHA1 (0x1u << 16) /**< \brief (ICM_FEATURES) SHA1 Hardcoded Mode */
\r
210 #define ICM_FEATURES_HSHA224 (0x1u << 17) /**< \brief (ICM_FEATURES) SHA224 Hardcoded Mode */
\r
211 #define ICM_FEATURES_HSHA256 (0x1u << 18) /**< \brief (ICM_FEATURES) SHA256 Hardcoded Mode */
\r
212 #define ICM_FEATURES_HSHA384 (0x1u << 19) /**< \brief (ICM_FEATURES) SHA384 Hardcoded Mode */
\r
213 #define ICM_FEATURES_HSHA512 (0x1u << 20) /**< \brief (ICM_FEATURES) SHA512 Hardcoded Mode */
\r
214 /* -------- ICM_VERSION : (ICM Offset: 0xFC) Version Register -------- */
\r
215 #define ICM_VERSION_VERSION_Pos 0
\r
216 #define ICM_VERSION_VERSION_Msk (0xfffu << ICM_VERSION_VERSION_Pos) /**< \brief (ICM_VERSION) Version of the Hardware Module */
\r
217 #define ICM_VERSION_MFN_Pos 16
\r
218 #define ICM_VERSION_MFN_Msk (0x7u << ICM_VERSION_MFN_Pos) /**< \brief (ICM_VERSION) Metal Fix Number */
\r
223 #endif /* _SAM_ICM_COMPONENT_ */
\r
projects / freertos / blob