1 /* ---------------------------------------------------------------------------- */
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2 /* Atmel Microcontroller Software Support */
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3 /* SAM Software Package License */
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4 /* ---------------------------------------------------------------------------- */
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5 /* Copyright (c) 2014, Atmel Corporation */
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7 /* All rights reserved. */
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9 /* Redistribution and use in source and binary forms, with or without */
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10 /* modification, are permitted provided that the following condition is met: */
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12 /* - Redistributions of source code must retain the above copyright notice, */
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13 /* this list of conditions and the disclaimer below. */
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15 /* Atmel's name may not be used to endorse or promote products derived from */
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16 /* this software without specific prior written permission. */
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18 /* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
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19 /* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
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20 /* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
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21 /* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
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22 /* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
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23 /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
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24 /* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
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25 /* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
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26 /* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
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27 /* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
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28 /* ---------------------------------------------------------------------------- */
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30 #ifndef _SAM_AES_INSTANCE_
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31 #define _SAM_AES_INSTANCE_
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33 /* ========== Register definition for AES peripheral ========== */
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34 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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35 #define REG_AES_CR (0x4006C000U) /**< \brief (AES) Control Register */
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36 #define REG_AES_MR (0x4006C004U) /**< \brief (AES) Mode Register */
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37 #define REG_AES_IER (0x4006C010U) /**< \brief (AES) Interrupt Enable Register */
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38 #define REG_AES_IDR (0x4006C014U) /**< \brief (AES) Interrupt Disable Register */
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39 #define REG_AES_IMR (0x4006C018U) /**< \brief (AES) Interrupt Mask Register */
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40 #define REG_AES_ISR (0x4006C01CU) /**< \brief (AES) Interrupt Status Register */
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41 #define REG_AES_KEYWR (0x4006C020U) /**< \brief (AES) Key Word Register */
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42 #define REG_AES_IDATAR (0x4006C040U) /**< \brief (AES) Input Data Register */
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43 #define REG_AES_ODATAR (0x4006C050U) /**< \brief (AES) Output Data Register */
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44 #define REG_AES_IVR (0x4006C060U) /**< \brief (AES) Initialization Vector Register */
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45 #define REG_AES_AADLENR (0x4006C070U) /**< \brief (AES) Additional Authenticated Data Length Register */
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46 #define REG_AES_CLENR (0x4006C074U) /**< \brief (AES) Plaintext/Ciphertext Length Register */
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47 #define REG_AES_GHASHR (0x4006C078U) /**< \brief (AES) GCM Intermediate Hash Word Register */
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48 #define REG_AES_TAGR (0x4006C088U) /**< \brief (AES) GCM Authentication Tag Word Register */
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49 #define REG_AES_CTRR (0x4006C098U) /**< \brief (AES) GCM Encryption Counter Value Register */
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50 #define REG_AES_GCMHR (0x4006C09CU) /**< \brief (AES) GCM H World Register */
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51 #define REG_AES_VERSION (0x4006C0FCU) /**< \brief (AES) Version Register */
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53 #define REG_AES_CR (*(__O uint32_t*)0x4006C000U) /**< \brief (AES) Control Register */
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54 #define REG_AES_MR (*(__IO uint32_t*)0x4006C004U) /**< \brief (AES) Mode Register */
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55 #define REG_AES_IER (*(__O uint32_t*)0x4006C010U) /**< \brief (AES) Interrupt Enable Register */
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56 #define REG_AES_IDR (*(__O uint32_t*)0x4006C014U) /**< \brief (AES) Interrupt Disable Register */
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57 #define REG_AES_IMR (*(__I uint32_t*)0x4006C018U) /**< \brief (AES) Interrupt Mask Register */
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58 #define REG_AES_ISR (*(__I uint32_t*)0x4006C01CU) /**< \brief (AES) Interrupt Status Register */
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59 #define REG_AES_KEYWR (*(__O uint32_t*)0x4006C020U) /**< \brief (AES) Key Word Register */
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60 #define REG_AES_IDATAR (*(__O uint32_t*)0x4006C040U) /**< \brief (AES) Input Data Register */
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61 #define REG_AES_ODATAR (*(__I uint32_t*)0x4006C050U) /**< \brief (AES) Output Data Register */
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62 #define REG_AES_IVR (*(__O uint32_t*)0x4006C060U) /**< \brief (AES) Initialization Vector Register */
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63 #define REG_AES_AADLENR (*(__IO uint32_t*)0x4006C070U) /**< \brief (AES) Additional Authenticated Data Length Register */
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64 #define REG_AES_CLENR (*(__IO uint32_t*)0x4006C074U) /**< \brief (AES) Plaintext/Ciphertext Length Register */
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65 #define REG_AES_GHASHR (*(__IO uint32_t*)0x4006C078U) /**< \brief (AES) GCM Intermediate Hash Word Register */
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66 #define REG_AES_TAGR (*(__I uint32_t*)0x4006C088U) /**< \brief (AES) GCM Authentication Tag Word Register */
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67 #define REG_AES_CTRR (*(__I uint32_t*)0x4006C098U) /**< \brief (AES) GCM Encryption Counter Value Register */
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68 #define REG_AES_GCMHR (*(__IO uint32_t*)0x4006C09CU) /**< \brief (AES) GCM H World Register */
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69 #define REG_AES_VERSION (*(__I uint32_t*)0x4006C0FCU) /**< \brief (AES) Version Register */
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70 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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72 #endif /* _SAM_AES_INSTANCE_ */
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