1 /* ---------------------------------------------------------------------------- */
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2 /* Atmel Microcontroller Software Support */
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3 /* SAM Software Package License */
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4 /* ---------------------------------------------------------------------------- */
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5 /* Copyright (c) 2014, Atmel Corporation */
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7 /* All rights reserved. */
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9 /* Redistribution and use in source and binary forms, with or without */
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10 /* modification, are permitted provided that the following condition is met: */
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12 /* - Redistributions of source code must retain the above copyright notice, */
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13 /* this list of conditions and the disclaimer below. */
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15 /* Atmel's name may not be used to endorse or promote products derived from */
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16 /* this software without specific prior written permission. */
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18 /* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
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19 /* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
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20 /* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
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21 /* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
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22 /* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
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23 /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
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24 /* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
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25 /* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
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26 /* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
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27 /* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
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28 /* ---------------------------------------------------------------------------- */
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30 #ifndef _SAM_RTC_INSTANCE_
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31 #define _SAM_RTC_INSTANCE_
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33 /* ========== Register definition for RTC peripheral ========== */
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34 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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35 #define REG_RTC_CR (0x400E1860U) /**< \brief (RTC) Control Register */
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36 #define REG_RTC_MR (0x400E1864U) /**< \brief (RTC) Mode Register */
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37 #define REG_RTC_TIMR (0x400E1868U) /**< \brief (RTC) Time Register */
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38 #define REG_RTC_CALR (0x400E186CU) /**< \brief (RTC) Calendar Register */
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39 #define REG_RTC_TIMALR (0x400E1870U) /**< \brief (RTC) Time Alarm Register */
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40 #define REG_RTC_CALALR (0x400E1874U) /**< \brief (RTC) Calendar Alarm Register */
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41 #define REG_RTC_SR (0x400E1878U) /**< \brief (RTC) Status Register */
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42 #define REG_RTC_SCCR (0x400E187CU) /**< \brief (RTC) Status Clear Command Register */
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43 #define REG_RTC_IER (0x400E1880U) /**< \brief (RTC) Interrupt Enable Register */
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44 #define REG_RTC_IDR (0x400E1884U) /**< \brief (RTC) Interrupt Disable Register */
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45 #define REG_RTC_IMR (0x400E1888U) /**< \brief (RTC) Interrupt Mask Register */
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46 #define REG_RTC_VER (0x400E188CU) /**< \brief (RTC) Valid Entry Register */
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47 #define REG_RTC_TSTR0 (0x400E1910U) /**< \brief (RTC) TimeStamp Time Register 0 */
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48 #define REG_RTC_TSDR0 (0x400E1914U) /**< \brief (RTC) TimeStamp Date Register 0 */
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49 #define REG_RTC_TSSR0 (0x400E1918U) /**< \brief (RTC) TimeStamp Source Register 0 */
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50 #define REG_RTC_TSTR1 (0x400E191CU) /**< \brief (RTC) TimeStamp Time Register 1 */
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51 #define REG_RTC_TSDR1 (0x400E1920U) /**< \brief (RTC) TimeStamp Date Register 1 */
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52 #define REG_RTC_TSSR1 (0x400E1924U) /**< \brief (RTC) TimeStamp Source Register 1 */
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53 #define REG_RTC_WPMR (0x400E1944U) /**< \brief (RTC) Write Protection Mode Register */
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54 #define REG_RTC_VERSION (0x400E195CU) /**< \brief (RTC) Version Register */
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56 #define REG_RTC_CR (*(__IO uint32_t*)0x400E1860U) /**< \brief (RTC) Control Register */
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57 #define REG_RTC_MR (*(__IO uint32_t*)0x400E1864U) /**< \brief (RTC) Mode Register */
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58 #define REG_RTC_TIMR (*(__IO uint32_t*)0x400E1868U) /**< \brief (RTC) Time Register */
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59 #define REG_RTC_CALR (*(__IO uint32_t*)0x400E186CU) /**< \brief (RTC) Calendar Register */
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60 #define REG_RTC_TIMALR (*(__IO uint32_t*)0x400E1870U) /**< \brief (RTC) Time Alarm Register */
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61 #define REG_RTC_CALALR (*(__IO uint32_t*)0x400E1874U) /**< \brief (RTC) Calendar Alarm Register */
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62 #define REG_RTC_SR (*(__I uint32_t*)0x400E1878U) /**< \brief (RTC) Status Register */
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63 #define REG_RTC_SCCR (*(__O uint32_t*)0x400E187CU) /**< \brief (RTC) Status Clear Command Register */
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64 #define REG_RTC_IER (*(__O uint32_t*)0x400E1880U) /**< \brief (RTC) Interrupt Enable Register */
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65 #define REG_RTC_IDR (*(__O uint32_t*)0x400E1884U) /**< \brief (RTC) Interrupt Disable Register */
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66 #define REG_RTC_IMR (*(__I uint32_t*)0x400E1888U) /**< \brief (RTC) Interrupt Mask Register */
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67 #define REG_RTC_VER (*(__I uint32_t*)0x400E188CU) /**< \brief (RTC) Valid Entry Register */
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68 #define REG_RTC_TSTR0 (*(__I uint32_t*)0x400E1910U) /**< \brief (RTC) TimeStamp Time Register 0 */
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69 #define REG_RTC_TSDR0 (*(__I uint32_t*)0x400E1914U) /**< \brief (RTC) TimeStamp Date Register 0 */
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70 #define REG_RTC_TSSR0 (*(__I uint32_t*)0x400E1918U) /**< \brief (RTC) TimeStamp Source Register 0 */
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71 #define REG_RTC_TSTR1 (*(__I uint32_t*)0x400E191CU) /**< \brief (RTC) TimeStamp Time Register 1 */
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72 #define REG_RTC_TSDR1 (*(__I uint32_t*)0x400E1920U) /**< \brief (RTC) TimeStamp Date Register 1 */
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73 #define REG_RTC_TSSR1 (*(__I uint32_t*)0x400E1924U) /**< \brief (RTC) TimeStamp Source Register 1 */
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74 #define REG_RTC_WPMR (*(__IO uint32_t*)0x400E1944U) /**< \brief (RTC) Write Protection Mode Register */
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75 #define REG_RTC_VERSION (*(__I uint32_t*)0x400E195CU) /**< \brief (RTC) Version Register */
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76 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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78 #endif /* _SAM_RTC_INSTANCE_ */
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