1 /* ----------------------------------------------------------------------------
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2 * SAM Software Package License
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3 * ----------------------------------------------------------------------------
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4 * Copyright (c) 2013, Atmel Corporation
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6 * All rights reserved.
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8 * Redistribution and use in source and binary forms, with or without
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9 * modification, are permitted provided that the following conditions are met:
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11 * - Redistributions of source code must retain the above copyright notice,
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12 * this list of conditions and the disclaimer below.
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14 * Atmel's name may not be used to endorse or promote products derived from
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15 * this software without specific prior written permission.
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17 * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
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18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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20 * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
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21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
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23 * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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24 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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25 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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26 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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27 * ----------------------------------------------------------------------------
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31 * \addtogroup spi_dma_module SPI xDMA driver
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32 * \ingroup lib_spiflash
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36 * <li> QSPID_Configure() initializes and configures the SPI peripheral and xDMA for data transfer.</li>
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37 * <li> Configures the parameters for the device corresponding to the cs value by QSPID_ConfigureCS(). </li>
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38 * <li> Starts a SPI master transfer. This is a non blocking function QSPID_SendCommand(). It will
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39 * return as soon as the transfer is started..</li>
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47 * Implementation for the SPI Flash with xDMA driver.
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52 /*----------------------------------------------------------------------------
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54 *----------------------------------------------------------------------------*/
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58 /*----------------------------------------------------------------------------
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60 *----------------------------------------------------------------------------*/
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63 #define USE_QSPI_DMA
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65 #define TX_MICROBLOCK_LEN 256
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66 #define RX_MICROBLOCK_LEN 256
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68 /*----------------------------------------------------------------------------
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70 *----------------------------------------------------------------------------*/
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72 /*----------------------------------------------------------------------------
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74 *----------------------------------------------------------------------------*/
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77 /* DMA driver instance */
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78 static uint32_t qspiDmaTxChannel;
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79 static uint32_t qspiDmaRxChannel;
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81 /*----------------------------------------------------------------------------
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83 *----------------------------------------------------------------------------*/
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86 * \brief SPI xDMA Rx callback
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87 * Invoked on SPi DMA reception done.
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88 * \param channel DMA channel.
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89 * \param pArg Pointer to callback argument - Pointer to Qspid instance.
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91 static void QSPID_Rx_Cb(uint32_t channel, Qspid* pArg)
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93 QspidCmd *pQspidCmd = pArg->pCurrentCommand;
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94 Qspi *pQspiHw = pArg->pQspiHw;
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95 if (channel != qspiDmaRxChannel)
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98 /* Disable the SPI TX & RX */
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99 QSPI_Disable ( pQspiHw );
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101 /* Configure and enable interrupt on RC compare */
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102 NVIC_ClearPendingIRQ(XDMAC_IRQn);
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103 NVIC_DisableIRQ(XDMAC_IRQn);
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105 /* Disable the SPI Peripheral */
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106 PMC_DisablePeripheral ( pArg->spiId );
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109 QSPI_ReleaseCS(pQspiHw);
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111 /* Release the DMA channels */
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112 XDMAD_FreeChannel(pArg->pXdmad, qspiDmaRxChannel);
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113 XDMAD_FreeChannel(pArg->pXdmad, qspiDmaTxChannel);
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115 /* Release the dataflash semaphore */
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118 printf("\n\r%s\n\r",pArg->pCurrentCommand->pRxBuff);
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120 /* Invoke the callback associated with the current command */
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121 if (pQspidCmd && pQspidCmd->callback) {
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122 //printf("p %d", pArg->semaphore);
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123 pQspidCmd->callback(0, pQspidCmd->pArgument);
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128 * \brief Configure the DMA Channels: 0 RX, 1 TX.
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129 * Channels are disabled after configure.
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130 * \returns 0 if the dma channel configuration successfully; otherwise returns
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133 static uint8_t _qspid_configureDmaChannels( Qspid* pQspid )
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136 /* Driver initialize */
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137 XDMAD_Initialize( pQspid->pXdmad, 0 );
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139 XDMAD_FreeChannel( pQspid->pXdmad, qspiDmaTxChannel);
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140 XDMAD_FreeChannel( pQspid->pXdmad, qspiDmaRxChannel);
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142 /* Allocate a DMA channel for SPI0/1 TX. */
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143 qspiDmaTxChannel = XDMAD_AllocateChannel( pQspid->pXdmad, XDMAD_TRANSFER_MEMORY, pQspid->spiId);
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145 if ( qspiDmaTxChannel == XDMAD_ALLOC_FAILED )
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147 return QSPID_ERROR;
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150 /* Allocate a DMA channel for SPI0/1 RX. */
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151 qspiDmaRxChannel = XDMAD_AllocateChannel( pQspid->pXdmad, pQspid->spiId, XDMAD_TRANSFER_MEMORY);
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153 if ( qspiDmaRxChannel == XDMAD_ALLOC_FAILED )
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155 return QSPID_ERROR;
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159 /* Setup callbacks for SPI0/1 RX */
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160 XDMAD_SetCallback(pQspid->pXdmad, qspiDmaRxChannel, (XdmadTransferCallback)QSPID_Rx_Cb, pQspid);
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161 if (XDMAD_PrepareChannel( pQspid->pXdmad, qspiDmaRxChannel ))
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162 return QSPID_ERROR;
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164 /* Setup callbacks for SPI0/1 TX (ignored) */
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165 XDMAD_SetCallback(pQspid->pXdmad, qspiDmaTxChannel, NULL, NULL);
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166 if ( XDMAD_PrepareChannel( pQspid->pXdmad, qspiDmaTxChannel ))
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167 return QSPID_ERROR;
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174 * \brief Configure the DMA source and destination with Linker List mode.
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176 * \param pCommand Pointer to command
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177 * \returns 0 if the dma multibuffer configuration successfully; otherwise returns
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180 static uint8_t _spid_configureLinkList(Qspi *pQspiHw, void *pXdmad, QspidCmd *pCommand)
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182 sXdmadCfg xdmadRxCfg,xdmadTxCfg;
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185 if ((unsigned int)pQspiHw == (unsigned int)QSPI ) qspiId = ID_QSPI;
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191 xdmadTxCfg.mbr_ubc = TX_MICROBLOCK_LEN;
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192 xdmadTxCfg.mbr_sa = (uint32_t)pCommand->pTxBuff;
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193 xdmadTxCfg.mbr_da = (uint32_t)QSPIMEM_ADDR;
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194 xdmadTxCfg.mbr_cfg = XDMAC_CC_TYPE_MEM_TRAN |
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195 XDMAC_CC_MBSIZE_SINGLE |
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196 XDMAC_CC_MEMSET_NORMAL_MODE |
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197 XDMAC_CC_CSIZE_CHK_1 |
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198 XDMAC_CC_DWIDTH_BYTE|
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199 XDMAC_CC_SIF_AHB_IF0 |
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200 XDMAC_CC_DIF_AHB_IF0 |
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201 XDMAC_CC_SAM_INCREMENTED_AM |
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202 XDMAC_CC_DAM_INCREMENTED_AM |
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203 XDMAC_CC_PERID(XDMAIF_Get_ChannelNumber( qspiId, XDMAD_TRANSFER_TX ));
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205 xdmadTxCfg.mbr_bc = 0;
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206 xdmadTxCfg.mbr_ds = 0;
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207 xdmadTxCfg.mbr_sus = 0;
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208 xdmadTxCfg.mbr_dus = 0;
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211 /* Setup RX Link List */
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213 xdmadRxCfg.mbr_ubc = RX_MICROBLOCK_LEN;
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214 xdmadRxCfg.mbr_sa = (uint32_t)QSPIMEM_ADDR;
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215 xdmadRxCfg.mbr_da = (uint32_t)pCommand->pRxBuff;
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216 xdmadRxCfg.mbr_cfg = XDMAC_CC_TYPE_MEM_TRAN |
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217 XDMAC_CC_MBSIZE_SINGLE |
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218 XDMAC_CC_MEMSET_NORMAL_MODE |
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219 XDMAC_CC_CSIZE_CHK_1 |
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220 XDMAC_CC_DWIDTH_BYTE|
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221 XDMAC_CC_SIF_AHB_IF0 |
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222 XDMAC_CC_DIF_AHB_IF0 |
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223 XDMAC_CC_SAM_INCREMENTED_AM |
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224 XDMAC_CC_DAM_INCREMENTED_AM |
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225 XDMAC_CC_PERID(XDMAIF_Get_ChannelNumber( qspiId, XDMAD_TRANSFER_RX ));
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227 xdmadRxCfg.mbr_bc = 0;
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228 xdmadRxCfg.mbr_ds = 0;
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229 xdmadRxCfg.mbr_sus = 0;
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230 xdmadRxCfg.mbr_dus = 0;
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233 if (XDMAD_ConfigureTransfer( pXdmad, qspiDmaRxChannel, &xdmadRxCfg, 0, 0))
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234 return QSPID_ERROR;
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236 if (XDMAD_ConfigureTransfer( pXdmad, qspiDmaTxChannel, &xdmadTxCfg, 0, 0))
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237 return QSPID_ERROR;
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244 /*----------------------------------------------------------------------------
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245 * Exported functions
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246 *----------------------------------------------------------------------------*/
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248 * \brief Initializes the Qspid structure and the corresponding SPI & DMA hardware.
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250 * The driver will uses DMA channel 0 for RX and DMA channel 1 for TX.
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251 * The DMA channels are freed automatically when no SPI command processing.
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253 * \param pQspid Pointer to a Qspid instance.
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254 * \param pQspiHw Associated SPI peripheral.
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255 * \param spiId SPI peripheral identifier.
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256 * \param pDmad Pointer to a Dmad instance.
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258 uint32_t QSPID_Configure( Qspid *pQspid ,
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264 /* Initialize the SPI structure */
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265 pQspid->pQspiHw = pQspiHw;
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266 pQspid->spiId = spiId;
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267 pQspid->semaphore = 1;
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268 pQspid->pCurrentCommand = 0;
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269 pQspid->pXdmad = pXdmad;
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271 /* Enable the SPI Peripheral ,Execute a software reset of the SPI, Configure SPI in Master Mode*/
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272 QSPI_Configure ( pQspiHw, pQspid->spiId, QspiMode );
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280 * \brief Starts a SPI master transfer. This is a non blocking function. It will
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281 * return as soon as the transfer is started.
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283 * \param pQspid Pointer to a Qspid instance.
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284 * \param pCommand Pointer to the SPI command to execute.
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285 * \returns 0 if the transfer has been started successfully; otherwise returns
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286 * QQSPID_ERROR_LOCK is the driver is in use, or QQSPID_ERROR if the command is not
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289 uint32_t QSPID_SendCommand( Qspid *pQspid, QspidCmd *pCommand)
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291 Qspi *pQspiHw = pQspid->pQspiHw;
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293 /* Try to get the dataflash semaphore */
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294 if (pQspid->semaphore == 0) {
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296 return QQSPID_ERROR_LOCK;
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298 pQspid->semaphore--;
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300 /* Enable the SPI Peripheral */
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301 PMC_EnablePeripheral (pQspid->spiId );
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303 /* SPI chip select */
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304 SPI_ChipSelect (pQspiHw, 1 << pCommand->spiCs);
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306 // Initialize the callback
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307 pQspid->pCurrentCommand = pCommand;
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309 /* Initialize DMA controller using channel 0 for RX, 1 for TX. */
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310 if (_spid_configureDmaChannels(pQspid) )
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311 return QQSPID_ERROR_LOCK;
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313 /* Configure and enable interrupt on RC compare */
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314 NVIC_ClearPendingIRQ(XDMAC_IRQn);
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315 NVIC_SetPriority( XDMAC_IRQn ,1);
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316 NVIC_EnableIRQ(XDMAC_IRQn);
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319 if (_spid_configureLinkList(pQspiHw, pQspid->pXdmad, pCommand))
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320 return QSPID_ERROR_LOCK;
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322 /* Enables the SPI to transfer and receive data. */
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323 SPI_Enable (pQspiHw );
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325 /* Start DMA 0(RX) && 1(TX) */
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326 if (XDMAD_StartTransfer( pQspid->pXdmad, qspiDmaRxChannel ))
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327 return QSPID_ERROR_LOCK;
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328 if (XDMAD_StartTransfer( pQspid->pXdmad, qspiDmaTxChannel ))
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329 return QSPID_ERROR_LOCK;
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335 * \brief Check if the SPI driver is busy.
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337 * \param pQspid Pointer to a Qspid instance.
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338 * \returns 1 if the SPI driver is currently busy executing a command; otherwise
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340 uint32_t QSPID_IsBusy(const Qspid *pQspid)
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342 if (pQspid->semaphore == 0) {
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