1 /* ----------------------------------------------------------------------------
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2 * SAM Software Package License
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3 * ----------------------------------------------------------------------------
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4 * Copyright (c) 2011, Atmel Corporation
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6 * All rights reserved.
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8 * Redistribution and use in source and binary forms, with or without
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9 * modification, are permitted provided that the following conditions are met:
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11 * - Redistributions of source code must retain the above copyright notice,
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12 * this list of conditions and the disclaimer below.
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14 * Atmel's name may not be used to endorse or promote products derived from
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15 * this software without specific prior written permission.
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17 * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
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18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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20 * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
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21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
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23 * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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24 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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25 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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26 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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27 * ----------------------------------------------------------------------------
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31 /*---------------------------------------------------------------------------
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33 *---------------------------------------------------------------------------*/
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37 /*---------------------------------------------------------------------------
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39 *---------------------------------------------------------------------------*/
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41 /** Keywords to write to the reset registers */
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42 #define RSTC_KEY_PASSWORD RSTC_MR_KEY(0xA5U)
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44 #define RSTC_MR_URSTEN (1ul )
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45 #define RSTC_MR_URSTIEN (1ul << 4)
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47 /*---------------------------------------------------------------------------
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48 * Exported functions
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49 *---------------------------------------------------------------------------*/
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52 * Configure the mode of the RSTC peripheral.
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53 * The configuration is computed by the lib (RSTC_RMR_*).
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54 * \param mr Desired mode configuration.
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56 void RSTC_ConfigureMode(uint32_t mr)
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59 mr &= ~RSTC_MR_KEY_Msk;
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60 pHw->RSTC_MR = mr | RSTC_KEY_PASSWORD;
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64 * Enable/Disable the detection of a low level on the pin NRST as User Reset
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65 * \param enable 1 to enable & 0 to disable.
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67 void RSTC_SetUserResetEnable(uint8_t enable)
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70 uint32_t mr = pHw->RSTC_MR & (~RSTC_MR_KEY_Msk);
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73 mr |= RSTC_MR_URSTEN;
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77 mr &= ~RSTC_MR_URSTEN;
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79 pHw->RSTC_MR = mr | RSTC_KEY_PASSWORD;
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83 * Enable/Disable the interrupt of a User Reset (USRTS bit in RSTC_RST).
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84 * \param enable 1 to enable & 0 to disable.
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86 void RSTC_SetUserResetInterruptEnable(uint8_t enable)
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89 uint32_t mr = pHw->RSTC_MR & (~RSTC_MR_KEY_Msk);
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92 mr |= RSTC_MR_URSTIEN;
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96 mr &= ~RSTC_MR_URSTIEN;
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98 pHw->RSTC_MR = mr | RSTC_KEY_PASSWORD;
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102 * Setup the external reset length. The length is asserted during a time of
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103 * pow(2, powl+1) Slow Clock(32KHz). The duration is between 60us and 2s.
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104 * \param powl Power length defined.
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106 void RSTC_SetExtResetLength(uint8_t powl)
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109 uint32_t mr = pHw->RSTC_MR;
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110 mr &= ~(RSTC_MR_KEY_Msk | RSTC_MR_ERSTL_Msk);
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111 mr |= RSTC_MR_ERSTL(powl);
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112 pHw->RSTC_MR = mr | RSTC_KEY_PASSWORD;
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117 * Resets the processor.
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119 void RSTC_ProcessorReset(void)
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122 pHw->RSTC_CR = RSTC_CR_PROCRST | RSTC_KEY_PASSWORD;
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126 * Resets the peripherals.
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128 void RSTC_PeripheralReset(void)
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131 pHw->RSTC_CR = RSTC_CR_PERRST | RSTC_KEY_PASSWORD;
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135 * Asserts the NRST pin for external resets.
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137 void RSTC_ExtReset(void)
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140 pHw->RSTC_CR = RSTC_CR_EXTRST | RSTC_KEY_PASSWORD;
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144 * Return NRST pin level ( 1 or 0 ).
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146 uint8_t RSTC_GetNrstLevel(void)
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149 return ((pHw->RSTC_SR & RSTC_SR_NRSTL) > 0);
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153 * Returns 1 if at least one high-to-low transition of NRST (User Reset) has
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154 * been detected since the last read of RSTC_RSR.
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156 uint8_t RSTC_IsUserResetDetected(void)
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159 if (pHw->RSTC_SR & RSTC_SR_URSTS)
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167 * Return 1 if a software reset command is being performed by the reset
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168 * controller. The reset controller is busy.
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170 uint8_t RSTC_IsBusy(void)
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173 if (pHw->RSTC_SR & RSTC_SR_SRCMP)
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183 uint32_t RSTC_GetStatus(void)
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186 return (pHw->RSTC_SR);
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