1 /* ---------------------------------------------------------------------------- */
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2 /* Atmel Microcontroller Software Support */
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3 /* SAM Software Package License */
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4 /* ---------------------------------------------------------------------------- */
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5 /* Copyright (c) 2014, Atmel Corporation */
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7 /* All rights reserved. */
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9 /* Redistribution and use in source and binary forms, with or without */
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10 /* modification, are permitted provided that the following condition is met: */
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12 /* - Redistributions of source code must retain the above copyright notice, */
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13 /* this list of conditions and the disclaimer below. */
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15 /* Atmel's name may not be used to endorse or promote products derived from */
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16 /* this software without specific prior written permission. */
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18 /* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
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19 /* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
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20 /* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
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21 /* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
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22 /* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
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23 /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
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24 /* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
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25 /* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
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26 /* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
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27 /* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
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28 /* ---------------------------------------------------------------------------- */
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33 /** \addtogroup SAMV71Q19_definitions SAMV71Q19 definitions
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34 This file defines all structures and symbols for SAMV71Q19:
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35 - registers and bit-fields
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36 - peripheral base address
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46 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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50 /* ************************************************************************** */
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51 /* CMSIS DEFINITIONS FOR SAMV71Q19 */
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52 /* ************************************************************************** */
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53 /** \addtogroup SAMV71Q19_cmsis CMSIS Definitions */
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56 /**< Interrupt Number Definition */
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59 /****** Cortex-M7 Processor Exceptions Numbers ******************************/
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60 NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */
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61 HardFault_IRQn = -13, /**< 3 HardFault Interrupt */
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62 MemoryManagement_IRQn = -12, /**< 4 Cortex-M7 Memory Management Interrupt */
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63 BusFault_IRQn = -11, /**< 5 Cortex-M7 Bus Fault Interrupt */
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64 UsageFault_IRQn = -10, /**< 6 Cortex-M7 Usage Fault Interrupt */
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65 SVCall_IRQn = -5, /**< 11 Cortex-M7 SV Call Interrupt */
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66 DebugMonitor_IRQn = -4, /**< 12 Cortex-M7 Debug Monitor Interrupt */
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67 PendSV_IRQn = -2, /**< 14 Cortex-M7 Pend SV Interrupt */
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68 SysTick_IRQn = -1, /**< 15 Cortex-M7 System Tick Interrupt */
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69 /****** SAMV71Q19 specific Interrupt Numbers *********************************/
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71 SUPC_IRQn = 0, /**< 0 SAMV71Q19 Supply Controller (SUPC) */
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72 RSTC_IRQn = 1, /**< 1 SAMV71Q19 Reset Controller (RSTC) */
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73 RTC_IRQn = 2, /**< 2 SAMV71Q19 Real Time Clock (RTC) */
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74 RTT_IRQn = 3, /**< 3 SAMV71Q19 Real Time Timer (RTT) */
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75 WDT_IRQn = 4, /**< 4 SAMV71Q19 Watchdog Timer (WDT) */
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76 PMC_IRQn = 5, /**< 5 SAMV71Q19 Power Management Controller (PMC) */
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77 EFC_IRQn = 6, /**< 6 SAMV71Q19 Enhanced Embedded Flash Controller (EFC) */
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78 UART0_IRQn = 7, /**< 7 SAMV71Q19 UART 0 (UART0) */
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79 UART1_IRQn = 8, /**< 8 SAMV71Q19 UART 1 (UART1) */
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80 PIOA_IRQn = 10, /**< 10 SAMV71Q19 Parallel I/O Controller A (PIOA) */
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81 PIOB_IRQn = 11, /**< 11 SAMV71Q19 Parallel I/O Controller B (PIOB) */
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82 PIOC_IRQn = 12, /**< 12 SAMV71Q19 Parallel I/O Controller C (PIOC) */
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83 USART0_IRQn = 13, /**< 13 SAMV71Q19 USART 0 (USART0) */
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84 USART1_IRQn = 14, /**< 14 SAMV71Q19 USART 1 (USART1) */
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85 USART2_IRQn = 15, /**< 15 SAMV71Q19 USART 2 (USART2) */
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86 PIOD_IRQn = 16, /**< 16 SAMV71Q19 Parallel I/O Controller D (PIOD) */
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87 PIOE_IRQn = 17, /**< 17 SAMV71Q19 Parallel I/O Controller E (PIOE) */
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88 HSMCI_IRQn = 18, /**< 18 SAMV71Q19 Multimedia Card Interface (HSMCI) */
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89 TWIHS0_IRQn = 19, /**< 19 SAMV71Q19 Two Wire Interface 0 HS (TWIHS0) */
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90 TWIHS1_IRQn = 20, /**< 20 SAMV71Q19 Two Wire Interface 1 HS (TWIHS1) */
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91 SPI0_IRQn = 21, /**< 21 SAMV71Q19 Serial Peripheral Interface 0 (SPI0) */
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92 SSC_IRQn = 22, /**< 22 SAMV71Q19 Synchronous Serial Controller (SSC) */
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93 TC0_IRQn = 23, /**< 23 SAMV71Q19 Timer/Counter 0 (TC0) */
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94 TC1_IRQn = 24, /**< 24 SAMV71Q19 Timer/Counter 1 (TC1) */
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95 TC2_IRQn = 25, /**< 25 SAMV71Q19 Timer/Counter 2 (TC2) */
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96 TC3_IRQn = 26, /**< 26 SAMV71Q19 Timer/Counter 3 (TC3) */
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97 TC4_IRQn = 27, /**< 27 SAMV71Q19 Timer/Counter 4 (TC4) */
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98 TC5_IRQn = 28, /**< 28 SAMV71Q19 Timer/Counter 5 (TC5) */
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99 AFEC0_IRQn = 29, /**< 29 SAMV71Q19 Analog Front End 0 (AFEC0) */
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100 DACC_IRQn = 30, /**< 30 SAMV71Q19 Digital To Analog Converter (DACC) */
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101 PWM0_IRQn = 31, /**< 31 SAMV71Q19 Pulse Width Modulation 0 (PWM0) */
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102 ICM_IRQn = 32, /**< 32 SAMV71Q19 Integrity Check Monitor (ICM) */
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103 ACC_IRQn = 33, /**< 33 SAMV71Q19 Analog Comparator (ACC) */
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104 USBHS_IRQn = 34, /**< 34 SAMV71Q19 USB Host / Device Controller (USBHS) */
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105 MCAN0_IRQn = 35, /**< 35 SAMV71Q19 MCAN Controller 0 (MCAN0) */
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106 MCAN0_LINE1_IRQn = 36, /**< 36 SAMV71Q21 MCAN Controller 0 LINE1 (MCAN0) */
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107 MCAN1_IRQn = 37, /**< 37 SAMV71Q19 MCAN Controller 1 (MCAN1) */
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108 MCAN1_LINE1_IRQn = 38, /**< 38 SAMV71Q21 MCAN Controller 1 LINE1 (MCAN1) */
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109 GMAC_IRQn = 39, /**< 39 SAMV71Q19 Ethernet MAC (GMAC) */
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110 AFEC1_IRQn = 40, /**< 40 SAMV71Q19 Analog Front End 1 (AFEC1) */
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111 TWIHS2_IRQn = 41, /**< 41 SAMV71Q19 Two Wire Interface 2 HS (TWIHS2) */
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112 SPI1_IRQn = 42, /**< 42 SAMV71Q19 Serial Peripheral Interface 1 (SPI1) */
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113 QSPI_IRQn = 43, /**< 43 SAMV71Q19 Quad I/O Serial Peripheral Interface (QSPI) */
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114 UART2_IRQn = 44, /**< 44 SAMV71Q19 UART 2 (UART2) */
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115 UART3_IRQn = 45, /**< 45 SAMV71Q19 UART 3 (UART3) */
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116 UART4_IRQn = 46, /**< 46 SAMV71Q19 UART 4 (UART4) */
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117 TC6_IRQn = 47, /**< 47 SAMV71Q19 Timer/Counter 6 (TC6) */
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118 TC7_IRQn = 48, /**< 48 SAMV71Q19 Timer/Counter 7 (TC7) */
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119 TC8_IRQn = 49, /**< 49 SAMV71Q19 Timer/Counter 8 (TC8) */
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120 TC9_IRQn = 50, /**< 50 SAMV71Q19 Timer/Counter 9 (TC9) */
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121 TC10_IRQn = 51, /**< 51 SAMV71Q19 Timer/Counter 10 (TC10) */
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122 TC11_IRQn = 52, /**< 52 SAMV71Q19 Timer/Counter 11 (TC11) */
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123 MLB_IRQn = 53, /**< 53 SAMV71Q19 MediaLB (MLB) */
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124 AES_IRQn = 56, /**< 56 SAMV71Q19 AES (AES) */
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125 TRNG_IRQn = 57, /**< 57 SAMV71Q19 True Random Generator (TRNG) */
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126 XDMAC_IRQn = 58, /**< 58 SAMV71Q19 DMA (XDMAC) */
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127 ISI_IRQn = 59, /**< 59 SAMV71Q19 Camera Interface (ISI) */
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128 PWM1_IRQn = 60, /**< 60 SAMV71Q19 Pulse Width Modulation 1 (PWM1) */
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129 SDRAMC_IRQn = 62, /**< 62 SAMV71Q19 SDRAM Controller (SDRAMC) */
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130 RSWDT_IRQn = 63, /**< 63 SAMV71Q19 Reinforced Secure Watchdog Timer (RSWDT) */
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132 PERIPH_COUNT_IRQn = 64 /**< Number of peripheral IDs */
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135 typedef struct _DeviceVectors
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137 /* Stack pointer */
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140 /* Cortex-M handlers */
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141 void* pfnReset_Handler;
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142 void* pfnNMI_Handler;
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143 void* pfnHardFault_Handler;
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144 void* pfnMemManage_Handler;
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145 void* pfnBusFault_Handler;
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146 void* pfnUsageFault_Handler;
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147 void* pfnReserved1_Handler;
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148 void* pfnReserved2_Handler;
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149 void* pfnReserved3_Handler;
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150 void* pfnReserved4_Handler;
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151 void* pfnSVC_Handler;
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152 void* pfnDebugMon_Handler;
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153 void* pfnReserved5_Handler;
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154 void* pfnPendSV_Handler;
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155 void* pfnSysTick_Handler;
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157 /* Peripheral handlers */
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158 void* pfnSUPC_Handler; /* 0 Supply Controller */
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159 void* pfnRSTC_Handler; /* 1 Reset Controller */
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160 void* pfnRTC_Handler; /* 2 Real Time Clock */
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161 void* pfnRTT_Handler; /* 3 Real Time Timer */
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162 void* pfnWDT_Handler; /* 4 Watchdog Timer */
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163 void* pfnPMC_Handler; /* 5 Power Management Controller */
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164 void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */
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165 void* pfnUART0_Handler; /* 7 UART 0 */
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166 void* pfnUART1_Handler; /* 8 UART 1 */
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168 void* pfnPIOA_Handler; /* 10 Parallel I/O Controller A */
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169 void* pfnPIOB_Handler; /* 11 Parallel I/O Controller B */
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170 void* pfnPIOC_Handler; /* 12 Parallel I/O Controller C */
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171 void* pfnUSART0_Handler; /* 13 USART 0 */
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172 void* pfnUSART1_Handler; /* 14 USART 1 */
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173 void* pfnUSART2_Handler; /* 15 USART 2 */
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174 void* pfnPIOD_Handler; /* 16 Parallel I/O Controller D */
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175 void* pfnPIOE_Handler; /* 17 Parallel I/O Controller E */
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176 void* pfnHSMCI_Handler; /* 18 Multimedia Card Interface */
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177 void* pfnTWIHS0_Handler; /* 19 Two Wire Interface 0 HS */
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178 void* pfnTWIHS1_Handler; /* 20 Two Wire Interface 1 HS */
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179 void* pfnSPI0_Handler; /* 21 Serial Peripheral Interface 0 */
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180 void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */
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181 void* pfnTC0_Handler; /* 23 Timer/Counter 0 */
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182 void* pfnTC1_Handler; /* 24 Timer/Counter 1 */
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183 void* pfnTC2_Handler; /* 25 Timer/Counter 2 */
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184 void* pfnTC3_Handler; /* 26 Timer/Counter 3 */
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185 void* pfnTC4_Handler; /* 27 Timer/Counter 4 */
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186 void* pfnTC5_Handler; /* 28 Timer/Counter 5 */
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187 void* pfnAFEC0_Handler; /* 29 Analog Front End 0 */
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188 void* pfnDACC_Handler; /* 30 Digital To Analog Converter */
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189 void* pfnPWM0_Handler; /* 31 Pulse Width Modulation 0 */
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190 void* pfnICM_Handler; /* 32 Integrity Check Monitor */
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191 void* pfnACC_Handler; /* 33 Analog Comparator */
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192 void* pfnUSBHS_Handler; /* 34 USB Host / Device Controller */
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193 void* pfnMCAN0_Handler; /* 35 MCAN Controller 0 */
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194 void* pfnMCAN0_Line1_Handler; /* 36 MCAN Controller 0 */
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195 void* pfnMCAN1_Handler; /* 37 MCAN Controller 1 */
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196 void* pfnMCAN1_Line1_Handler; /* 38 MCAN Controller 1 */
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197 void* pfnGMAC_Handler; /* 39 Ethernet MAC */
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198 void* pfnAFEC1_Handler; /* 40 Analog Front End 1 */
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199 void* pfnTWIHS2_Handler; /* 41 Two Wire Interface 2 HS */
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200 void* pfnSPI1_Handler; /* 42 Serial Peripheral Interface 1 */
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201 void* pfnQSPI_Handler; /* 43 Quad I/O Serial Peripheral Interface */
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202 void* pfnUART2_Handler; /* 44 UART 2 */
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203 void* pfnUART3_Handler; /* 45 UART 3 */
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204 void* pfnUART4_Handler; /* 46 UART 4 */
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205 void* pfnTC6_Handler; /* 47 Timer/Counter 6 */
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206 void* pfnTC7_Handler; /* 48 Timer/Counter 7 */
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207 void* pfnTC8_Handler; /* 49 Timer/Counter 8 */
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208 void* pfnTC9_Handler; /* 50 Timer/Counter 9 */
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209 void* pfnTC10_Handler; /* 51 Timer/Counter 10 */
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210 void* pfnTC11_Handler; /* 52 Timer/Counter 11 */
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211 void* pfnMLB_Handler; /* 53 MediaLB */
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212 void* pvReserved54;
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213 void* pvReserved55;
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214 void* pfnAES_Handler; /* 56 AES */
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215 void* pfnTRNG_Handler; /* 57 True Random Generator */
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216 void* pfnXDMAC_Handler; /* 58 DMA */
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217 void* pfnISI_Handler; /* 59 Camera Interface */
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218 void* pfnPWM1_Handler; /* 60 Pulse Width Modulation 1 */
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219 void* pvReserved61;
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220 void* pfnSDRAMC_Handler; /* 62 SDRAM Controller */
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221 void* pfnRSWDT_Handler; /* 63 Reinforced Secure Watchdog Timer */
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224 /* Cortex-M7 core handlers */
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225 void Reset_Handler ( void );
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226 void NMI_Handler ( void );
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227 void HardFault_Handler ( void );
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228 void MemManage_Handler ( void );
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229 void BusFault_Handler ( void );
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230 void UsageFault_Handler ( void );
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231 void SVC_Handler ( void );
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232 void DebugMon_Handler ( void );
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233 void PendSV_Handler ( void );
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234 void SysTick_Handler ( void );
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236 /* Peripherals handlers */
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237 void ACC_Handler ( void );
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238 void AES_Handler ( void );
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239 void AFEC0_Handler ( void );
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240 void AFEC1_Handler ( void );
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241 void DACC_Handler ( void );
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242 void EFC_Handler ( void );
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243 void GMAC_Handler ( void );
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244 void HSMCI_Handler ( void );
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245 void ICM_Handler ( void );
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246 void ISI_Handler ( void );
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247 void MCAN0_Handler ( void );
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248 void MCAN0_Line1_Handler( void );
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249 void MCAN1_Handler ( void );
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250 void MCAN1_Line1_Handler( void );
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251 void MLB_Handler ( void );
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252 void PIOA_Handler ( void );
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253 void PIOB_Handler ( void );
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254 void PIOC_Handler ( void );
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255 void PIOD_Handler ( void );
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256 void PIOE_Handler ( void );
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257 void PMC_Handler ( void );
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258 void PWM0_Handler ( void );
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259 void PWM1_Handler ( void );
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260 void QSPI_Handler ( void );
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261 void RSTC_Handler ( void );
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262 void RSWDT_Handler ( void );
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263 void RTC_Handler ( void );
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264 void RTT_Handler ( void );
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265 void SDRAMC_Handler ( void );
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266 void SPI0_Handler ( void );
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267 void SPI1_Handler ( void );
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268 void SSC_Handler ( void );
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269 void SUPC_Handler ( void );
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270 void TC0_Handler ( void );
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271 void TC1_Handler ( void );
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272 void TC2_Handler ( void );
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273 void TC3_Handler ( void );
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274 void TC4_Handler ( void );
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275 void TC5_Handler ( void );
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276 void TC6_Handler ( void );
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277 void TC7_Handler ( void );
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278 void TC8_Handler ( void );
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279 void TC9_Handler ( void );
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280 void TC10_Handler ( void );
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281 void TC11_Handler ( void );
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282 void TRNG_Handler ( void );
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283 void TWIHS0_Handler ( void );
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284 void TWIHS1_Handler ( void );
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285 void TWIHS2_Handler ( void );
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286 void UART0_Handler ( void );
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287 void UART1_Handler ( void );
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288 void UART2_Handler ( void );
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289 void UART3_Handler ( void );
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290 void UART4_Handler ( void );
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291 void USART0_Handler ( void );
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292 void USART1_Handler ( void );
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293 void USART2_Handler ( void );
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294 void USBHS_Handler ( void );
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295 void WDT_Handler ( void );
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296 void XDMAC_Handler ( void );
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299 * \brief Configuration of the Cortex-M7 Processor and Core Peripherals
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302 #define __CM7_REV 0x0000 /**< SAMV71Q19 core revision number ([15:8] revision number, [7:0] patch number) */
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303 #define __MPU_PRESENT 1 /**< SAMV71Q19 does provide a MPU */
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304 #define __NVIC_PRIO_BITS 3 /**< SAMV71Q19 uses 3 Bits for the Priority Levels */
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305 #define __FPU_PRESENT 1 /**< SAMV71Q19 does provide a FPU */
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306 #define __FPU_DP 1 /**< SAMV71Q19 Double precision FPU */
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307 #define __ICACHE_PRESENT 1 /**< SAMV71Q19 does provide an Instruction Cache */
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308 #define __DCACHE_PRESENT 1 /**< SAMV71Q19 does provide a Data Cache */
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309 #define __DTCM_PRESENT 1 /**< SAMV71Q19 does provide a Data TCM */
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310 #define __ITCM_PRESENT 1 /**< SAMV71Q19 does provide an Instruction TCM */
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311 #define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */
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314 * \brief CMSIS includes
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317 #include <core_cm7.h>
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318 #if !defined DONT_USE_CMSIS_INIT
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319 #include "system_samv71.h"
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320 #endif /* DONT_USE_CMSIS_INIT */
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324 /* ************************************************************************** */
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325 /** SOFTWARE PERIPHERAL API DEFINITION FOR SAMV71Q19 */
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326 /* ************************************************************************** */
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327 /** \addtogroup SAMV71Q19_api Peripheral Software API */
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330 #include "component/component_acc.h"
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331 #include "component/component_aes.h"
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332 #include "component/component_afec.h"
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333 #include "component/component_chipid.h"
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334 #include "component/component_dacc.h"
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335 #include "component/component_efc.h"
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336 #include "component/component_gmac.h"
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337 #include "component/component_gpbr.h"
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338 #include "component/component_hsmci.h"
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339 #include "component/component_icm.h"
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340 #include "component/component_isi.h"
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341 #include "component/component_matrix.h"
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342 #include "component/component_mcan.h"
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343 #include "component/component_mlb.h"
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344 #include "component/component_pio.h"
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345 #include "component/component_pmc.h"
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346 #include "component/component_pwm.h"
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347 #include "component/component_qspi.h"
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348 #include "component/component_rstc.h"
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349 #include "component/component_rswdt.h"
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350 #include "component/component_rtc.h"
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351 #include "component/component_rtt.h"
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352 #include "component/component_sdramc.h"
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353 #include "component/component_smc.h"
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354 #include "component/component_spi.h"
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355 #include "component/component_ssc.h"
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356 #include "component/component_supc.h"
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357 #include "component/component_tc.h"
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358 #include "component/component_trng.h"
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359 #include "component/component_twihs.h"
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360 #include "component/component_uart.h"
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361 #include "component/component_usart.h"
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362 #include "component/component_usbhs.h"
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363 #include "component/component_utmi.h"
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364 #include "component/component_wdt.h"
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365 #include "component/component_xdmac.h"
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368 /* ************************************************************************** */
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369 /* REGISTER ACCESS DEFINITIONS FOR SAMV71Q19 */
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370 /* ************************************************************************** */
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371 /** \addtogroup SAMV71Q19_reg Registers Access Definitions */
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374 #include "instance/instance_hsmci.h"
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375 #include "instance/instance_ssc.h"
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376 #include "instance/instance_spi0.h"
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377 #include "instance/instance_tc0.h"
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378 #include "instance/instance_tc1.h"
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379 #include "instance/instance_tc2.h"
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380 #include "instance/instance_twihs0.h"
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381 #include "instance/instance_twihs1.h"
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382 #include "instance/instance_pwm0.h"
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383 #include "instance/instance_usart0.h"
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384 #include "instance/instance_usart1.h"
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385 #include "instance/instance_usart2.h"
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386 #include "instance/instance_mcan0.h"
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387 #include "instance/instance_mcan1.h"
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388 #include "instance/instance_usbhs.h"
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389 #include "instance/instance_afec0.h"
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390 #include "instance/instance_dacc.h"
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391 #include "instance/instance_acc.h"
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392 #include "instance/instance_icm.h"
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393 #include "instance/instance_isi.h"
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394 #include "instance/instance_gmac.h"
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395 #include "instance/instance_tc3.h"
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396 #include "instance/instance_spi1.h"
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397 #include "instance/instance_pwm1.h"
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398 #include "instance/instance_twihs2.h"
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399 #include "instance/instance_afec1.h"
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400 #include "instance/instance_mlb.h"
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401 #include "instance/instance_aes.h"
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402 #include "instance/instance_trng.h"
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403 #include "instance/instance_xdmac.h"
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404 #include "instance/instance_qspi.h"
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405 #include "instance/instance_smc.h"
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406 #include "instance/instance_sdramc.h"
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407 #include "instance/instance_matrix.h"
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408 #include "instance/instance_utmi.h"
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409 #include "instance/instance_pmc.h"
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410 #include "instance/instance_uart0.h"
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411 #include "instance/instance_chipid.h"
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412 #include "instance/instance_uart1.h"
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413 #include "instance/instance_efc.h"
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414 #include "instance/instance_pioa.h"
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415 #include "instance/instance_piob.h"
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416 #include "instance/instance_pioc.h"
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417 #include "instance/instance_piod.h"
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418 #include "instance/instance_pioe.h"
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419 #include "instance/instance_rstc.h"
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420 #include "instance/instance_supc.h"
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421 #include "instance/instance_rtt.h"
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422 #include "instance/instance_wdt.h"
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423 #include "instance/instance_rtc.h"
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424 #include "instance/instance_gpbr.h"
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425 #include "instance/instance_rswdt.h"
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426 #include "instance/instance_uart2.h"
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427 #include "instance/instance_uart3.h"
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428 #include "instance/instance_uart4.h"
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431 /* ************************************************************************** */
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432 /* PERIPHERAL ID DEFINITIONS FOR SAMV71Q19 */
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433 /* ************************************************************************** */
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434 /** \addtogroup SAMV71Q19_id Peripheral Ids Definitions */
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437 #define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */
\r
438 #define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */
\r
439 #define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */
\r
440 #define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */
\r
441 #define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */
\r
442 #define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */
\r
443 #define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */
\r
444 #define ID_UART0 ( 7) /**< \brief UART 0 (UART0) */
\r
445 #define ID_UART1 ( 8) /**< \brief UART 1 (UART1) */
\r
446 #define ID_SMC ( 9) /**< \brief Static Memory Controller (SMC) */
\r
447 #define ID_PIOA (10) /**< \brief Parallel I/O Controller A (PIOA) */
\r
448 #define ID_PIOB (11) /**< \brief Parallel I/O Controller B (PIOB) */
\r
449 #define ID_PIOC (12) /**< \brief Parallel I/O Controller C (PIOC) */
\r
450 #define ID_USART0 (13) /**< \brief USART 0 (USART0) */
\r
451 #define ID_USART1 (14) /**< \brief USART 1 (USART1) */
\r
452 #define ID_USART2 (15) /**< \brief USART 2 (USART2) */
\r
453 #define ID_PIOD (16) /**< \brief Parallel I/O Controller D (PIOD) */
\r
454 #define ID_PIOE (17) /**< \brief Parallel I/O Controller E (PIOE) */
\r
455 #define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */
\r
456 #define ID_TWIHS0 (19) /**< \brief Two Wire Interface 0 HS (TWIHS0) */
\r
457 #define ID_TWIHS1 (20) /**< \brief Two Wire Interface 1 HS (TWIHS1) */
\r
458 #define ID_SPI0 (21) /**< \brief Serial Peripheral Interface 0 (SPI0) */
\r
459 #define ID_SSC (22) /**< \brief Synchronous Serial Controller (SSC) */
\r
460 #define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */
\r
461 #define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */
\r
462 #define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */
\r
463 #define ID_TC3 (26) /**< \brief Timer/Counter 3 (TC3) */
\r
464 #define ID_TC4 (27) /**< \brief Timer/Counter 4 (TC4) */
\r
465 #define ID_TC5 (28) /**< \brief Timer/Counter 5 (TC5) */
\r
466 #define ID_AFEC0 (29) /**< \brief Analog Front End 0 (AFEC0) */
\r
467 #define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */
\r
468 #define ID_PWM0 (31) /**< \brief Pulse Width Modulation 0 (PWM0) */
\r
469 #define ID_ICM (32) /**< \brief Integrity Check Monitor (ICM) */
\r
470 #define ID_ACC (33) /**< \brief Analog Comparator (ACC) */
\r
471 #define ID_USBHS (34) /**< \brief USB Host / Device Controller (USBHS) */
\r
472 #define ID_MCAN0 (35) /**< \brief MCAN Controller 0 (MCAN0) */
\r
473 #define ID_MCAN1 (37) /**< \brief MCAN Controller 1 (MCAN1) */
\r
474 #define ID_GMAC (39) /**< \brief Ethernet MAC (GMAC) */
\r
475 #define ID_AFEC1 (40) /**< \brief Analog Front End 1 (AFEC1) */
\r
476 #define ID_TWIHS2 (41) /**< \brief Two Wire Interface 2 HS (TWIHS2) */
\r
477 #define ID_SPI1 (42) /**< \brief Serial Peripheral Interface 1 (SPI1) */
\r
478 #define ID_QSPI (43) /**< \brief Quad I/O Serial Peripheral Interface (QSPI) */
\r
479 #define ID_UART2 (44) /**< \brief UART 2 (UART2) */
\r
480 #define ID_UART3 (45) /**< \brief UART 3 (UART3) */
\r
481 #define ID_UART4 (46) /**< \brief UART 4 (UART4) */
\r
482 #define ID_TC6 (47) /**< \brief Timer/Counter 6 (TC6) */
\r
483 #define ID_TC7 (48) /**< \brief Timer/Counter 7 (TC7) */
\r
484 #define ID_TC8 (49) /**< \brief Timer/Counter 8 (TC8) */
\r
485 #define ID_TC9 (50) /**< \brief Timer/Counter 9 (TC9) */
\r
486 #define ID_TC10 (51) /**< \brief Timer/Counter 10 (TC10) */
\r
487 #define ID_TC11 (52) /**< \brief Timer/Counter 11 (TC11) */
\r
488 #define ID_MLB (53) /**< \brief MediaLB (MLB) */
\r
489 #define ID_AES (56) /**< \brief AES (AES) */
\r
490 #define ID_TRNG (57) /**< \brief True Random Generator (TRNG) */
\r
491 #define ID_XDMAC (58) /**< \brief DMA (XDMAC) */
\r
492 #define ID_ISI (59) /**< \brief Camera Interface (ISI) */
\r
493 #define ID_PWM1 (60) /**< \brief Pulse Width Modulation 1 (PWM1) */
\r
494 #define ID_SDRAMC (62) /**< \brief SDRAM Controller (SDRAMC) */
\r
495 #define ID_RSWDT (63) /**< \brief Reinforced Secure Watchdog Timer (RSWDT) */
\r
497 #define ID_PERIPH_COUNT (64) /**< \brief Number of peripheral IDs */
\r
500 /* ************************************************************************** */
\r
501 /* BASE ADDRESS DEFINITIONS FOR SAMV71Q19 */
\r
502 /* ************************************************************************** */
\r
503 /** \addtogroup SAMV71Q19_base Peripheral Base Address Definitions */
\r
506 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
\r
507 #define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */
\r
508 #define SSC (0x40004000U) /**< \brief (SSC ) Base Address */
\r
509 #define SPI0 (0x40008000U) /**< \brief (SPI0 ) Base Address */
\r
510 #define TC0 (0x4000C000U) /**< \brief (TC0 ) Base Address */
\r
511 #define TC1 (0x40010000U) /**< \brief (TC1 ) Base Address */
\r
512 #define TC2 (0x40014000U) /**< \brief (TC2 ) Base Address */
\r
513 #define TWIHS0 (0x40018000U) /**< \brief (TWIHS0) Base Address */
\r
514 #define TWIHS1 (0x4001C000U) /**< \brief (TWIHS1) Base Address */
\r
515 #define PWM0 (0x40020000U) /**< \brief (PWM0 ) Base Address */
\r
516 #define USART0 (0x40024000U) /**< \brief (USART0) Base Address */
\r
517 #define USART1 (0x40028000U) /**< \brief (USART1) Base Address */
\r
518 #define USART2 (0x4002C000U) /**< \brief (USART2) Base Address */
\r
519 #define MCAN0 (0x40030000U) /**< \brief (MCAN0 ) Base Address */
\r
520 #define MCAN1 (0x40034000U) /**< \brief (MCAN1 ) Base Address */
\r
521 #define USBHS (0x40038000U) /**< \brief (USBHS ) Base Address */
\r
522 #define AFEC0 (0x4003C000U) /**< \brief (AFEC0 ) Base Address */
\r
523 #define DACC (0x40040000U) /**< \brief (DACC ) Base Address */
\r
524 #define ACC (0x40044000U) /**< \brief (ACC ) Base Address */
\r
525 #define ICM (0x40048000U) /**< \brief (ICM ) Base Address */
\r
526 #define ISI (0x4004C000U) /**< \brief (ISI ) Base Address */
\r
527 #define GMAC (0x40050000U) /**< \brief (GMAC ) Base Address */
\r
528 #define TC3 (0x40054000U) /**< \brief (TC3 ) Base Address */
\r
529 #define SPI1 (0x40058000U) /**< \brief (SPI1 ) Base Address */
\r
530 #define PWM1 (0x4005C000U) /**< \brief (PWM1 ) Base Address */
\r
531 #define TWIHS2 (0x40060000U) /**< \brief (TWIHS2) Base Address */
\r
532 #define AFEC1 (0x40064000U) /**< \brief (AFEC1 ) Base Address */
\r
533 #define MLB (0x40068000U) /**< \brief (MLB ) Base Address */
\r
534 #define AES (0x4006C000U) /**< \brief (AES ) Base Address */
\r
535 #define TRNG (0x40070000U) /**< \brief (TRNG ) Base Address */
\r
536 #define XDMAC (0x40078000U) /**< \brief (XDMAC ) Base Address */
\r
537 #define QSPI (0x4007C000U) /**< \brief (QSPI ) Base Address */
\r
538 #define SMC (0x40080000U) /**< \brief (SMC ) Base Address */
\r
539 #define SDRAMC (0x40084000U) /**< \brief (SDRAMC) Base Address */
\r
540 #define MATRIX (0x40088000U) /**< \brief (MATRIX) Base Address */
\r
541 #define UTMI (0x400E0400U) /**< \brief (UTMI ) Base Address */
\r
542 #define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */
\r
543 #define UART0 (0x400E0800U) /**< \brief (UART0 ) Base Address */
\r
544 #define CHIPID (0x400E0940U) /**< \brief (CHIPID) Base Address */
\r
545 #define UART1 (0x400E0A00U) /**< \brief (UART1 ) Base Address */
\r
546 #define EFC (0x400E0C00U) /**< \brief (EFC ) Base Address */
\r
547 #define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */
\r
548 #define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */
\r
549 #define PIOC (0x400E1200U) /**< \brief (PIOC ) Base Address */
\r
550 #define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */
\r
551 #define PIOE (0x400E1600U) /**< \brief (PIOE ) Base Address */
\r
552 #define RSTC (0x400E1800U) /**< \brief (RSTC ) Base Address */
\r
553 #define SUPC (0x400E1810U) /**< \brief (SUPC ) Base Address */
\r
554 #define RTT (0x400E1830U) /**< \brief (RTT ) Base Address */
\r
555 #define WDT (0x400E1850U) /**< \brief (WDT ) Base Address */
\r
556 #define RTC (0x400E1860U) /**< \brief (RTC ) Base Address */
\r
557 #define GPBR (0x400E1890U) /**< \brief (GPBR ) Base Address */
\r
558 #define RSWDT (0x400E1900U) /**< \brief (RSWDT ) Base Address */
\r
559 #define UART2 (0x400E1A00U) /**< \brief (UART2 ) Base Address */
\r
560 #define UART3 (0x400E1C00U) /**< \brief (UART3 ) Base Address */
\r
561 #define UART4 (0x400E1E00U) /**< \brief (UART4 ) Base Address */
\r
563 #define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */
\r
564 #define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */
\r
565 #define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */
\r
566 #define TC0 ((Tc *)0x4000C000U) /**< \brief (TC0 ) Base Address */
\r
567 #define TC1 ((Tc *)0x40010000U) /**< \brief (TC1 ) Base Address */
\r
568 #define TC2 ((Tc *)0x40014000U) /**< \brief (TC2 ) Base Address */
\r
569 #define TWIHS0 ((Twihs *)0x40018000U) /**< \brief (TWIHS0) Base Address */
\r
570 #define TWIHS1 ((Twihs *)0x4001C000U) /**< \brief (TWIHS1) Base Address */
\r
571 #define PWM0 ((Pwm *)0x40020000U) /**< \brief (PWM0 ) Base Address */
\r
572 #define USART0 ((Usart *)0x40024000U) /**< \brief (USART0) Base Address */
\r
573 #define USART1 ((Usart *)0x40028000U) /**< \brief (USART1) Base Address */
\r
574 #define USART2 ((Usart *)0x4002C000U) /**< \brief (USART2) Base Address */
\r
575 #define MCAN0 ((Mcan *)0x40030000U) /**< \brief (MCAN0 ) Base Address */
\r
576 #define MCAN1 ((Mcan *)0x40034000U) /**< \brief (MCAN1 ) Base Address */
\r
577 #define USBHS ((Usbhs *)0x40038000U) /**< \brief (USBHS ) Base Address */
\r
578 #define AFEC0 ((Afec *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */
\r
579 #define DACC ((Dacc *)0x40040000U) /**< \brief (DACC ) Base Address */
\r
580 #define ACC ((Acc *)0x40044000U) /**< \brief (ACC ) Base Address */
\r
581 #define ICM ((Icm *)0x40048000U) /**< \brief (ICM ) Base Address */
\r
582 #define ISI ((Isi *)0x4004C000U) /**< \brief (ISI ) Base Address */
\r
583 #define GMAC ((Gmac *)0x40050000U) /**< \brief (GMAC ) Base Address */
\r
584 #define TC3 ((Tc *)0x40054000U) /**< \brief (TC3 ) Base Address */
\r
585 #define SPI1 ((Spi *)0x40058000U) /**< \brief (SPI1 ) Base Address */
\r
586 #define PWM1 ((Pwm *)0x4005C000U) /**< \brief (PWM1 ) Base Address */
\r
587 #define TWIHS2 ((Twihs *)0x40060000U) /**< \brief (TWIHS2) Base Address */
\r
588 #define AFEC1 ((Afec *)0x40064000U) /**< \brief (AFEC1 ) Base Address */
\r
589 #define MLB ((Mlb *)0x40068000U) /**< \brief (MLB ) Base Address */
\r
590 #define AES ((Aes *)0x4006C000U) /**< \brief (AES ) Base Address */
\r
591 #define TRNG ((Trng *)0x40070000U) /**< \brief (TRNG ) Base Address */
\r
592 #define XDMAC ((Xdmac *)0x40078000U) /**< \brief (XDMAC ) Base Address */
\r
593 #define QSPI ((Qspi *)0x4007C000U) /**< \brief (QSPI ) Base Address */
\r
594 #define SMC ((Smc *)0x40080000U) /**< \brief (SMC ) Base Address */
\r
595 #define SDRAMC ((Sdramc *)0x40084000U) /**< \brief (SDRAMC) Base Address */
\r
596 #define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX) Base Address */
\r
597 #define UTMI ((Utmi *)0x400E0400U) /**< \brief (UTMI ) Base Address */
\r
598 #define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */
\r
599 #define UART0 ((Uart *)0x400E0800U) /**< \brief (UART0 ) Base Address */
\r
600 #define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID) Base Address */
\r
601 #define UART1 ((Uart *)0x400E0A00U) /**< \brief (UART1 ) Base Address */
\r
602 #define EFC ((Efc *)0x400E0C00U) /**< \brief (EFC ) Base Address */
\r
603 #define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */
\r
604 #define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */
\r
605 #define PIOC ((Pio *)0x400E1200U) /**< \brief (PIOC ) Base Address */
\r
606 #define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */
\r
607 #define PIOE ((Pio *)0x400E1600U) /**< \brief (PIOE ) Base Address */
\r
608 #define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */
\r
609 #define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */
\r
610 #define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */
\r
611 #define WDT ((Wdt *)0x400E1850U) /**< \brief (WDT ) Base Address */
\r
612 #define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */
\r
613 #define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */
\r
614 #define RSWDT ((Rswdt *)0x400E1900U) /**< \brief (RSWDT ) Base Address */
\r
615 #define UART2 ((Uart *)0x400E1A00U) /**< \brief (UART2 ) Base Address */
\r
616 #define UART3 ((Uart *)0x400E1C00U) /**< \brief (UART3 ) Base Address */
\r
617 #define UART4 ((Uart *)0x400E1E00U) /**< \brief (UART4 ) Base Address */
\r
618 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
\r
621 /* ************************************************************************** */
\r
622 /* PIO DEFINITIONS FOR SAMV71Q19 */
\r
623 /* ************************************************************************** */
\r
624 /** \addtogroup SAMV71Q19_pio Peripheral Pio Definitions */
\r
627 #include "pio/pio_samv71q19.h"
\r
630 /* ************************************************************************** */
\r
631 /* MEMORY MAPPING DEFINITIONS FOR SAMV71Q19 */
\r
632 /* ************************************************************************** */
\r
634 #define IFLASH_SIZE (0x80000u)
\r
635 #define IFLASH_PAGE_SIZE (512u)
\r
636 #define IFLASH_LOCK_REGION_SIZE (16384u)
\r
637 #define IFLASH_NB_OF_PAGES (1024u)
\r
638 #define IFLASH_NB_OF_LOCK_BITS (32u)
\r
639 #define IRAM_SIZE (0x40000u)
\r
641 #define QSPIMEM_ADDR (0x80000000u) /**< QSPI Memory base address */
\r
642 #define AXIMX_ADDR (0xA0000000u) /**< AXI Bus Matrix base address */
\r
643 #define ITCM_ADDR (0x00000000u) /**< Instruction Tightly Coupled Memory base address */
\r
644 #define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */
\r
645 #define IROM_ADDR (0x00800000u) /**< Internal ROM base address */
\r
646 #define DTCM_ADDR (0x20000000u) /**< Data Tightly Coupled Memory base address */
\r
647 #define IRAM_ADDR (0x20400000u) /**< Internal RAM base address */
\r
648 #define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */
\r
649 #define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */
\r
650 #define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */
\r
651 #define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */
\r
652 #define SDRAM_CS_ADDR (0x70000000u) /**< SDRAM Chip Select base address */
\r
654 /* ************************************************************************** */
\r
655 /* MISCELLANEOUS DEFINITIONS FOR SAMV71Q19 */
\r
656 /* ************************************************************************** */
\r
658 #define CHIP_JTAGID (0x05B3D03FUL)
\r
659 #define CHIP_CIDR (0xA12D0A00UL)
\r
660 #define CHIP_EXID (0x00000002UL)
\r
662 /* ************************************************************************** */
\r
663 /* ELECTRICAL DEFINITIONS FOR SAMV71Q19 */
\r
664 /* ************************************************************************** */
\r
666 /* %ATMEL_ELECTRICAL% */
\r
668 /* Device characteristics */
\r
669 #define CHIP_FREQ_SLCK_RC_MIN (20000UL)
\r
670 #define CHIP_FREQ_SLCK_RC (32000UL)
\r
671 #define CHIP_FREQ_SLCK_RC_MAX (44000UL)
\r
672 #define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL)
\r
673 #define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL)
\r
674 #define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL)
\r
675 #define CHIP_FREQ_CPU_MAX (300000000UL)
\r
676 #define CHIP_FREQ_XTAL_32K (32768UL)
\r
677 #define CHIP_FREQ_XTAL_12M (12000000UL)
\r
679 /* Embedded Flash Read Wait State (VDDCORE set at 1.20V) */
\r
680 #define CHIP_FREQ_FWS_0 (26000000UL) /**< \brief Maximum operating frequency when FWS is 0 */
\r
681 #define CHIP_FREQ_FWS_1 (52000000UL) /**< \brief Maximum operating frequency when FWS is 1 */
\r
682 #define CHIP_FREQ_FWS_2 (78000000UL) /**< \brief Maximum operating frequency when FWS is 2 */
\r
683 #define CHIP_FREQ_FWS_3 (104000000UL) /**< \brief Maximum operating frequency when FWS is 3 */
\r
684 #define CHIP_FREQ_FWS_4 (131000000UL) /**< \brief Maximum operating frequency when FWS is 4 */
\r
685 #define CHIP_FREQ_FWS_5 (150000000UL) /**< \brief Maximum operating frequency when FWS is 5 */
\r
694 #endif /* _SAMV71Q19_ */
\r