1 /* ----------------------------------------------------------------------------
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2 * ATMEL Microcontroller Software Support
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3 * ----------------------------------------------------------------------------
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4 * Copyright (c) 2008, Atmel Corporation
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6 * All rights reserved.
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8 * Redistribution and use in source and binary forms, with or without
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9 * modification, are permitted provided that the following conditions are met:
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11 * - Redistributions of source code must retain the above copyright notice,
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12 * this list of conditions and the disclaimer below.
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14 * Atmel's name may not be used to endorse or promote products derived from
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15 * this software without specific prior written permission.
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17 * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
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18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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20 * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
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21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
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23 * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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24 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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25 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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26 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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27 * ----------------------------------------------------------------------------
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30 #ifndef _GMII_DEFINE_H
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31 #define _GMII_DEFINE_H
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34 //-----------------------------------------------------------------------------
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36 //-----------------------------------------------------------------------------
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37 //IEEE defined Registers
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38 #define GMII_BMCR 0x0 // Basic Mode Control Register
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39 #define GMII_BMSR 0x1 // Basic Mode Status Register
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40 #define GMII_PHYID1R 0x2 // PHY Idendifier Register 1
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41 #define GMII_PHYID2R 0x3 // PHY Idendifier Register 2
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42 #define GMII_ANAR 0x4 // Auto_Negotiation Advertisement Register
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43 #define GMII_ANLPAR 0x5 // Auto_negotiation Link Partner Ability Register
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44 #define GMII_ANER 0x6 // Auto-negotiation Expansion Register
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45 #define GMII_ANNPR 0x7 // Auto-negotiation Next Page Register
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46 #define GMII_ANLPNPAR 0x8 // Auto_negotiation Link Partner Next Page Ability Register
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47 #define GMII_AFEC0R 0x11 // AFE Control 0 Register
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48 #define GMII_AFEC3R 0x14 // AFE Control 3 Register
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49 #define GMII_RXERCR 0x15 // RXER Couter Register
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50 #define GMII_OMSSR 0x17 // Operation Mode Strap Status Register
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51 #define GMII_ECR 0x18 // Expanded Control Register
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52 #define GMII_ICSR 0x1B // Interrupt Control/Status Register
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53 #define GMII_FC 0x1C // Function Control
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54 #define GMII_LCSR 0x1D // LinkMD® Control/Status Register
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55 #define GMII_PC1R 0x1E // PHY Control 1 Register
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56 #define GMII_PC2R 0x1F // PHY Control 2 Register
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59 // PHY ID Identifier Register
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60 #define GMII_LSB_MASK 0x0U
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61 // definitions: MII_PHYID1
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62 #define GMII_OUI_MSB 0x0022
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63 // definitions: MII_PHYID2
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64 #define GMII_OUI_LSB 0x1572 // KSZ8061 PHY Id2
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68 // Basic Mode Control Register (BMCR)
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69 // Bit definitions: MII_BMCR
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70 #define GMII_RESET (1 << 15) // 1= Software Reset; 0=Normal Operation
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71 #define GMII_LOOPBACK (1 << 14) // 1=loopback Enabled; 0=Normal Operation
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72 #define GMII_SPEED_SELECT_LSB (1 << 13) // 1,0=1000Mbps 0,1=100Mbps; 0,0=10Mbps
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73 #define GMII_AUTONEG (1 << 12) // Auto-negotiation Enable
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74 #define GMII_POWER_DOWN (1 << 11) // 1=Power down 0=Normal operation
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75 #define GMII_ISOLATE (1 << 10) // 1 = Isolates 0 = Normal operation
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76 #define GMII_RESTART_AUTONEG (1 << 9) // 1 = Restart auto-negotiation 0 = Normal operation
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77 #define GMII_DUPLEX_MODE (1 << 8) // 1 = Full duplex operation 0 = Normal operation
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78 // Reserved 7 // Read as 0, ignore on write
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79 #define GMII_SPEED_SELECT_MSB (1 << 6) //
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80 // Reserved 5 to 0 // Read as 0, ignore on write
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83 // Basic Mode Status Register (BMSR)
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84 // Bit definitions: MII_BMSR
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85 #define GMII_100BASE_T4 (1 << 15) // 100BASE-T4 Capable
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86 #define GMII_100BASE_TX_FD (1 << 14) // 100BASE-TX Full Duplex Capable
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87 #define GMII_100BASE_T4_HD (1 << 13) // 100BASE-TX Half Duplex Capable
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88 #define GMII_10BASE_T_FD (1 << 12) // 10BASE-T Full Duplex Capable
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89 #define GMII_10BASE_T_HD (1 << 11) // 10BASE-T Half Duplex Capable
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90 // Reserved 10 to 9 // Read as 0, ignore on write
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91 #define GMII_EXTEND_STATUS (1 << 8) // 1 = Extend Status Information In Reg 15
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93 #define GMII_MF_PREAMB_SUPPR (1 << 6) // MII Frame Preamble Suppression
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94 #define GMII_AUTONEG_COMP (1 << 5) // Auto-negotiation Complete
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95 #define GMII_REMOTE_FAULT (1 << 4) // Remote Fault
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96 #define GMII_AUTONEG_ABILITY (1 << 3) // Auto Configuration Ability
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97 #define GMII_LINK_STATUS (1 << 2) // Link Status
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98 #define GMII_JABBER_DETECT (1 << 1) // Jabber Detect
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99 #define GMII_EXTEND_CAPAB (1 << 0) // Extended Capability
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102 // Auto-negotiation Advertisement Register (ANAR)
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103 // Auto-negotiation Link Partner Ability Register (ANLPAR)
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104 // Bit definitions: MII_ANAR, MII_ANLPAR
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105 #define GMII_NP (1 << 15) // Next page Indication
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107 #define GMII_RF (1 << 13) // Remote Fault
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108 // Reserved 12 // Write as 0, ignore on read
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109 #define GMII_PAUSE_MASK (3 << 11) // 0,0 = No Pause 1,0 = Asymmetric Pause(link partner)
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110 // 0,1 = Symmetric Pause 1,1 = Symmetric&Asymmetric Pause(local device)
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111 #define GMII_T4 (1 << 9) // 100BASE-T4 Support
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112 #define GMII_TX_FDX (1 << 8) // 100BASE-TX Full Duplex Support
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113 #define GMII_TX_HDX (1 << 7) // 100BASE-TX Support
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114 #define GMII_10_FDX (1 << 6) // 10BASE-T Full Duplex Support
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115 #define GMII_10_HDX (1 << 5) // 10BASE-T Support
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116 // Selector 4 to 0 // Protocol Selection Bits
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117 #define GMII_AN_IEEE_802_3 0x00001
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121 #endif // #ifndef _MII_DEFINE_H
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