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   1 /* ---------------------------------------------------------------------------- */\r
   2 /*                  Atmel Microcontroller Software Support                      */\r
   3 /*                       SAM Software Package License                           */\r
   4 /* ---------------------------------------------------------------------------- */\r
   5 /* Copyright (c) 2014, Atmel Corporation                                        */\r
   6 /*                                                                              */\r
   7 /* All rights reserved.                                                         */\r
   8 /*                                                                              */\r
   9 /* Redistribution and use in source and binary forms, with or without           */\r
  10 /* modification, are permitted provided that the following condition is met:    */\r
  11 /*                                                                              */\r
  12 /* - Redistributions of source code must retain the above copyright notice,     */\r
  13 /* this list of conditions and the disclaimer below.                            */\r
  14 /*                                                                              */\r
  15 /* Atmel's name may not be used to endorse or promote products derived from     */\r
  16 /* this software without specific prior written permission.                     */\r
  17 /*                                                                              */\r
  18 /* DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR   */\r
  19 /* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */\r
  20 /* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE   */\r
  21 /* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,      */\r
  22 /* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */\r
  23 /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,  */\r
  24 /* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF    */\r
  25 /* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING         */\r
  26 /* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */\r
  27 /* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                           */\r
  28 /* ---------------------------------------------------------------------------- */\r
  29 \r
  30 #include "sam.h"\r
  31 \r
  32 /* @cond 0 */\r
  33 /**INDENT-OFF**/\r
  34 #ifdef __cplusplus\r
  35 extern "C" {\r
  36 #endif\r
  37 /**INDENT-ON**/\r
  38 /* @endcond */\r
  39 \r
  40 /* Clock Settings (120MHz) */\r
  41 #define SYS_BOARD_OSCOUNT   (CKGR_MOR_MOSCXTST(0x8U))\r
  42 #define SYS_BOARD_PLLAR     (CKGR_PLLAR_ONE \\r
  43                                                         | CKGR_PLLAR_MULA(0x13U) \\r
  44                                                         | CKGR_PLLAR_PLLACOUNT(0x3fU) \\r
  45                                                         | CKGR_PLLAR_DIVA(0x1U))\r
  46 #define SYS_BOARD_MCKR      (PMC_MCKR_PRES_CLK_2 | PMC_MCKR_CSS_PLLA_CLK)\r
  47 \r
  48 #define SYS_CKGR_MOR_KEY_VALUE  CKGR_MOR_KEY_PASSWD /* Key to unlock MOR register */\r
  49 \r
  50 uint32_t SystemCoreClock = CHIP_FREQ_MAINCK_RC_4MHZ;\r
  51 \r
  52 /**\r
  53  * \brief Setup the microcontroller system.\r
  54  * Initialize the System and update the SystemFrequency variable.\r
  55  */\r
  56 void SystemInit(void)\r
  57 {\r
  58         /* Set FWS according to SYS_BOARD_MCKR configuration */\r
  59         EFC->EEFC_FMR = EEFC_FMR_FWS(5);\r
  60 #if defined(ID_EFC1)\r
  61         EFC1->EEFC_FMR = EEFC_FMR_FWS(5);\r
  62 #endif\r
  63 \r
  64         /* Initialize main oscillator */\r
  65         if (!(PMC->CKGR_MOR & CKGR_MOR_MOSCSEL)) {\r
  66                 PMC->CKGR_MOR = SYS_CKGR_MOR_KEY_VALUE | SYS_BOARD_OSCOUNT |\r
  67                                              CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN;\r
  68                 while (!(PMC->PMC_SR & PMC_SR_MOSCXTS)) {\r
  69                 }\r
  70         }\r
  71 \r
  72         /* Switch to 3-20MHz Xtal oscillator */\r
  73         PMC->CKGR_MOR = SYS_CKGR_MOR_KEY_VALUE | SYS_BOARD_OSCOUNT |\r
  74                                    CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN | CKGR_MOR_MOSCSEL;\r
  75 \r
  76         while (!(PMC->PMC_SR & PMC_SR_MOSCSELS)) {\r
  77         }\r
  78                 PMC->PMC_MCKR = (PMC->PMC_MCKR & ~(uint32_t)PMC_MCKR_CSS_Msk) |\r
  79                                             PMC_MCKR_CSS_MAIN_CLK;\r
  80                 while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) {\r
  81         }\r
  82 \r
  83         /* Initialize PLLA */\r
  84         PMC->CKGR_PLLAR = SYS_BOARD_PLLAR;\r
  85         while (!(PMC->PMC_SR & PMC_SR_LOCKA)) {\r
  86         }\r
  87 \r
  88         /* Switch to main clock */\r
  89         PMC->PMC_MCKR = (SYS_BOARD_MCKR & ~PMC_MCKR_CSS_Msk) | PMC_MCKR_CSS_MAIN_CLK;\r
  90         while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) {\r
  91         }\r
  92 \r
  93         /* Switch to PLLA */\r
  94         PMC->PMC_MCKR = SYS_BOARD_MCKR;\r
  95         while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) {\r
  96         }\r
  97 \r
  98         SystemCoreClock = CHIP_FREQ_CPU_MAX;\r
  99 }\r
 100 \r
 101 void SystemCoreClockUpdate(void)\r
 102 {\r
 103         /* Determine clock frequency according to clock register values */\r
 104         switch (PMC->PMC_MCKR & (uint32_t) PMC_MCKR_CSS_Msk) {\r
 105         case PMC_MCKR_CSS_SLOW_CLK:     /* Slow clock */\r
 106                 if (SUPC->SUPC_SR & SUPC_SR_OSCSEL) {\r
 107                         SystemCoreClock = CHIP_FREQ_XTAL_32K;\r
 108                 } else {\r
 109                         SystemCoreClock = CHIP_FREQ_SLCK_RC;\r
 110                 }\r
 111                 break;\r
 112         case PMC_MCKR_CSS_MAIN_CLK:     /* Main clock */\r
 113                 if (PMC->CKGR_MOR & CKGR_MOR_MOSCSEL) {\r
 114                         SystemCoreClock = CHIP_FREQ_XTAL_12M;\r
 115                 } else {\r
 116                         SystemCoreClock = CHIP_FREQ_MAINCK_RC_4MHZ;\r
 117 \r
 118                         switch (PMC->CKGR_MOR & CKGR_MOR_MOSCRCF_Msk) {\r
 119                         case CKGR_MOR_MOSCRCF_4_MHz:\r
 120                                 break;\r
 121                         case CKGR_MOR_MOSCRCF_8_MHz:\r
 122                                 SystemCoreClock *= 2U;\r
 123                                 break;\r
 124                         case CKGR_MOR_MOSCRCF_12_MHz:\r
 125                                 SystemCoreClock *= 3U;\r
 126                                 break;\r
 127                         default:\r
 128                                 break;\r
 129                         }\r
 130                 }\r
 131                 break;\r
 132         case PMC_MCKR_CSS_PLLA_CLK:     /* PLLA clock */\r
 133 //      case PMC_MCKR_CSS_PLLB_CLK:     /* PLLB clock */\r
 134                 if (PMC->CKGR_MOR & CKGR_MOR_MOSCSEL) {\r
 135                         SystemCoreClock = CHIP_FREQ_XTAL_12M;\r
 136                 } else {\r
 137                         SystemCoreClock = CHIP_FREQ_MAINCK_RC_4MHZ;\r
 138 \r
 139                         switch (PMC->CKGR_MOR & CKGR_MOR_MOSCRCF_Msk) {\r
 140                         case CKGR_MOR_MOSCRCF_4_MHz:\r
 141                                 break;\r
 142                         case CKGR_MOR_MOSCRCF_8_MHz:\r
 143                                 SystemCoreClock *= 2U;\r
 144                                 break;\r
 145                         case CKGR_MOR_MOSCRCF_12_MHz:\r
 146                                 SystemCoreClock *= 3U;\r
 147                                 break;\r
 148                         default:\r
 149                                 break;\r
 150                         }\r
 151                 }\r
 152                 if ((uint32_t) (PMC->PMC_MCKR & (uint32_t) PMC_MCKR_CSS_Msk) == PMC_MCKR_CSS_PLLA_CLK) {\r
 153                         SystemCoreClock *= ((((PMC->CKGR_PLLAR) & CKGR_PLLAR_MULA_Msk) >>\r
 154                                                           CKGR_PLLAR_MULA_Pos) + 1U);\r
 155                         SystemCoreClock /= ((((PMC->CKGR_PLLAR) & CKGR_PLLAR_DIVA_Msk) >>\r
 156                                                           CKGR_PLLAR_DIVA_Pos));\r
 157                 } else {\r
 158                         // SystemCoreClock *= ((((PMC->CKGR_PLLBR) & CKGR_PLLBR_MULB_Msk) >>\r
 159                                                            // CKGR_PLLBR_MULB_Pos) + 1U);\r
 160                         // SystemCoreClock /= ((((PMC->CKGR_PLLBR) & CKGR_PLLBR_DIVB_Msk) >>\r
 161                                                                // CKGR_PLLBR_DIVB_Pos));\r
 162                 }\r
 163                 break;\r
 164         default:\r
 165                 break;\r
 166         }\r
 167 \r
 168         if ((PMC->PMC_MCKR & PMC_MCKR_PRES_Msk) == PMC_MCKR_PRES_CLK_3) {\r
 169                 SystemCoreClock /= 3U;\r
 170         } else {\r
 171                 SystemCoreClock >>= ((PMC->PMC_MCKR & PMC_MCKR_PRES_Msk) >> PMC_MCKR_PRES_Pos);\r
 172         }\r
 173 }\r
 174 \r
 175 /**\r
 176  * Initialize flash.\r
 177  */\r
 178 void system_init_flash(uint32_t ul_clk)\r
 179 {\r
 180         /* Set FWS for embedded Flash access according to operating frequency */\r
 181 #if !defined(ID_EFC1)\r
 182         if (ul_clk < CHIP_FREQ_FWS_0) {\r
 183                 EFC->EEFC_FMR = EEFC_FMR_FWS(0);\r
 184         } else if (ul_clk < CHIP_FREQ_FWS_1) {\r
 185                 EFC->EEFC_FMR = EEFC_FMR_FWS(1);\r
 186         } else if (ul_clk < CHIP_FREQ_FWS_2) {\r
 187                 EFC->EEFC_FMR = EEFC_FMR_FWS(2);\r
 188         } else if (ul_clk < CHIP_FREQ_FWS_3) {\r
 189                 EFC->EEFC_FMR = EEFC_FMR_FWS(3);\r
 190         } else if (ul_clk < CHIP_FREQ_FWS_4) {\r
 191                 EFC->EEFC_FMR = EEFC_FMR_FWS(4);\r
 192         } else {\r
 193                 EFC->EEFC_FMR = EEFC_FMR_FWS(5);\r
 194         }\r
 195 #else\r
 196         if (ul_clk < CHIP_FREQ_FWS_0) {\r
 197                 EFC->EEFC_FMR = EEFC_FMR_FWS(0);\r
 198                 EFC1->EEFC_FMR = EEFC_FMR_FWS(0);\r
 199         } else if (ul_clk < CHIP_FREQ_FWS_1) {\r
 200                 EFC->EEFC_FMR = EEFC_FMR_FWS(1);\r
 201                 EFC1->EEFC_FMR = EEFC_FMR_FWS(1);\r
 202         } else if (ul_clk < CHIP_FREQ_FWS_2) {\r
 203                 EFC->EEFC_FMR = EEFC_FMR_FWS(2);\r
 204                 EFC1->EEFC_FMR = EEFC_FMR_FWS(2);\r
 205         } else if (ul_clk < CHIP_FREQ_FWS_3) {\r
 206                 EFC->EEFC_FMR = EEFC_FMR_FWS(3);\r
 207                 EFC1->EEFC_FMR = EEFC_FMR_FWS(3);\r
 208         } else if (ul_clk < CHIP_FREQ_FWS_4) {\r
 209                 EFC->EEFC_FMR = EEFC_FMR_FWS(4);\r
 210                 EFC1->EEFC_FMR = EEFC_FMR_FWS(4);\r
 211         } else {\r
 212                 EFC->EEFC_FMR = EEFC_FMR_FWS(5);\r
 213                 EFC1->EEFC_FMR = EEFC_FMR_FWS(5);\r
 214         }\r
 215 #endif\r
 216 }\r
 217 \r
 218 /* @cond 0 */\r
 219 /**INDENT-OFF**/\r
 220 #ifdef __cplusplus\r
 221 }\r
 222 #endif\r
 223 /**INDENT-ON**/\r
 224 /* @endcond */\r