1 /* ----------------------------------------------------------------------------
\r
2 * SAM Software Package License
\r
3 * ----------------------------------------------------------------------------
\r
4 * Copyright (c) 2012, Atmel Corporation
\r
6 * All rights reserved.
\r
8 * Redistribution and use in source and binary forms, with or without
\r
9 * modification, are permitted provided that the following conditions are met:
\r
11 * - Redistributions of source code must retain the above copyright notice,
\r
12 * this list of conditions and the disclaimer below.
\r
14 * Atmel's name may not be used to endorse or promote products derived from
\r
15 * this software without specific prior written permission.
\r
17 * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
\r
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
\r
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
\r
20 * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
\r
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
\r
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
\r
23 * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
\r
24 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
\r
25 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
\r
26 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
\r
27 * ----------------------------------------------------------------------------
\r
33 * Implementation of memories configuration on board.
\r
37 /*----------------------------------------------------------------------------
\r
39 *----------------------------------------------------------------------------*/
\r
42 /*----------------------------------------------------------------------------
\r
43 * Exported functions
\r
44 *----------------------------------------------------------------------------*/
\r
47 * \brief Configures the EBI for NandFlash access.
\r
49 extern void BOARD_ConfigureNandFlash( Smc* pSmc )
\r
51 /* Enable peripheral clock */
\r
52 PMC_EnablePeripheral( ID_SMC ) ;
\r
54 /* NCS0 is assigned to a NAND Flash (NANDOE and NANWE used for NCS0) */
\r
55 // MATRIX->MATRIX_SFR[5] = 1;
\r
57 pSmc->SMC_CS_NUMBER[0].SMC_SETUP =
\r
58 SMC_SETUP_NWE_SETUP(0)
\r
59 | SMC_SETUP_NCS_WR_SETUP(1)
\r
60 | SMC_SETUP_NRD_SETUP(0)
\r
61 | SMC_SETUP_NCS_RD_SETUP(1);
\r
63 pSmc->SMC_CS_NUMBER[0].SMC_PULSE =
\r
64 SMC_PULSE_NWE_PULSE(2)
\r
65 | SMC_PULSE_NCS_WR_PULSE(3)
\r
66 | SMC_PULSE_NRD_PULSE(4)
\r
67 | SMC_PULSE_NCS_RD_PULSE(4);
\r
69 pSmc->SMC_CS_NUMBER[0].SMC_CYCLE =
\r
70 SMC_CYCLE_NWE_CYCLE(4)
\r
71 | SMC_CYCLE_NRD_CYCLE(7);
\r
73 pSmc->SMC_CS_NUMBER[0].SMC_MODE =
\r
75 | SMC_MODE_WRITE_MODE;
\r
79 * \brief Configures the EBI for %NorFlash access.
\r
81 extern void BOARD_ConfigureNorFlash( Smc* pSmc )
\r
83 /* Enable peripheral clock */
\r
84 PMC_EnablePeripheral( ID_SMC ) ;
\r
86 /* Configure SMC, NCS0 is assigned to a norflash */
\r
87 pSmc->SMC_CS_NUMBER[0].SMC_SETUP =
\r
88 SMC_SETUP_NWE_SETUP(2)
\r
89 | SMC_SETUP_NCS_WR_SETUP(0)
\r
90 | SMC_SETUP_NRD_SETUP(0)
\r
91 | SMC_SETUP_NCS_RD_SETUP(0);
\r
93 pSmc->SMC_CS_NUMBER[0].SMC_PULSE =
\r
94 SMC_PULSE_NWE_PULSE(6)
\r
95 | SMC_PULSE_NCS_WR_PULSE(0xA)
\r
96 | SMC_PULSE_NRD_PULSE(0xA)
\r
97 | SMC_PULSE_NCS_RD_PULSE(0xA);
\r
99 pSmc->SMC_CS_NUMBER[0].SMC_CYCLE =
\r
100 SMC_CYCLE_NWE_CYCLE(0xA)
\r
101 | SMC_CYCLE_NRD_CYCLE(0xA);
\r
103 pSmc->SMC_CS_NUMBER[0].SMC_MODE =
\r
105 | SMC_MODE_WRITE_MODE
\r
106 | SMC_MODE_EXNW_MODE_DISABLED
\r
107 | SMC_MODE_TDF_CYCLES(0x1);
\r
111 * \brief An accurate one-to-one comparison is necessary between PSRAM and SMC waveforms for
\r
112 * a complete SMC configuration.
\r
113 * \note The system is running at 48 MHz for the EBI Bus.
\r
114 * Please refer to the "AC Characteristics" section of the customer product datasheet.
\r
116 extern void BOARD_ConfigurePSRAM( Smc* pSmc )
\r
120 /* Enable peripheral clock */
\r
121 PMC_EnablePeripheral( ID_SMC ) ;
\r
123 /* Configure SMC, NCS1 is assigned to a external PSRAM */
\r
125 * PSRAM IS66WV51216BLL
\r
126 * 55 ns Access time
\r
128 * SMC1 (timing SAM3S read mode SMC) = 21 ns of setup
\r
129 * 21 + 55 = 76 ns => at least 5 cycles at 64 MHz
\r
130 * Write pulse width minimum = 45 ns (PSRAM)
\r
132 pSmc->SMC_CS_NUMBER[1].SMC_SETUP =
\r
133 SMC_SETUP_NWE_SETUP( 1 )
\r
134 | SMC_SETUP_NCS_WR_SETUP( 0 )
\r
135 | SMC_SETUP_NRD_SETUP( 2 )
\r
136 | SMC_SETUP_NCS_RD_SETUP( 0 ) ;
\r
138 pSmc->SMC_CS_NUMBER[1].SMC_PULSE =
\r
139 SMC_PULSE_NWE_PULSE( 3 )
\r
140 | SMC_PULSE_NCS_WR_PULSE( 4 )
\r
141 | SMC_PULSE_NRD_PULSE( 3 )
\r
142 | SMC_PULSE_NCS_RD_PULSE( 5 ) ;
\r
144 /* NWE_CYCLE: The total duration of the write cycle.
\r
145 NWE_CYCLE = NWE_SETUP + NWE_PULSE + NWE_HOLD
\r
146 = NCS_WR_SETUP + NCS_WR_PULSE + NCS_WR_HOLD
\r
147 (tWC) Write Cycle Time min. 70ns
\r
148 NRD_CYCLE: The total duration of the read cycle.
\r
149 NRD_CYCLE = NRD_SETUP + NRD_PULSE + NRD_HOLD
\r
150 = NCS_RD_SETUP + NCS_RD_PULSE + NCS_RD_HOLD
\r
151 (tRC) Read Cycle Time min. 70ns. */
\r
152 pSmc->SMC_CS_NUMBER[1].SMC_CYCLE =
\r
153 SMC_CYCLE_NWE_CYCLE( 4 )
\r
154 | SMC_CYCLE_NRD_CYCLE( 5 ) ;
\r
156 dwTmp = SMC->SMC_CS_NUMBER[0].SMC_MODE;
\r
157 pSmc->SMC_CS_NUMBER[1].SMC_MODE = dwTmp
\r
158 | SMC_MODE_READ_MODE
\r
159 | SMC_MODE_WRITE_MODE;
\r
163 uint32_t ExtRAM_Validation(uint32_t baseAddr, uint32_t size)
\r
166 uint32_t *ptr = (uint32_t *) baseAddr;
\r
168 for (i = 0; i < size << 2; ++i) {
\r
171 ptr[i] = 0x55AA55AA | (1 << i);
\r
174 ptr[i] = 0xAA55AA55 | (1 << i);
\r
178 for (i = 0; i < size << 2; ++i) {
\r
180 if (ptr[i] != (0x55AA55AA | (1 << i))) {
\r
185 if (ptr[i] != (0xAA55AA55 | (1 << i))) {
\r
194 #define SDRAM_BA0 (1 << 20)
\r
195 #define SDRAM_BA1 (1 << 21)
\r
198 * \brief Configures the EBI for Sdram (IS42S16100E-7B) access.
\r
202 void BOARD_ConfigureSdram( void )
\r
204 const Pin pinsSdram[] = {BOARD_SDRAM_PINS};
\r
205 volatile uint32_t i;
\r
206 volatile uint8_t *pSdram = (uint8_t *) SDRAM_CS_ADDR;
\r
208 /* Configure PIO */
\r
209 PIO_Configure(pinsSdram, PIO_LISTSIZE(pinsSdram));
\r
210 PMC_EnablePeripheral(ID_SDRAMC);
\r
211 *((uint32_t *)0x40088124) = 0x10;
\r
213 /* 1. SDRAM features must be set in the configuration register: asynchronous timings (TRC, TRAS, etc.), number
\r
214 of columns, rows, CAS latency, and the data bus width. */
\r
215 SDRAMC->SDRAMC_CR =
\r
216 SDRAMC_CR_NC_COL8 // 8 column bits
\r
217 | SDRAMC_CR_NR_ROW11 // 12 row bits (4K)
\r
218 | SDRAMC_CR_CAS_LATENCY3 // CAS Latency 2
\r
219 | SDRAMC_CR_NB_BANK2 // 2 banks
\r
220 | SDRAMC_CR_DBW // 16 bit
\r
222 | SDRAMC_CR_TRC_TRFC(9) // 63ns min
\r
223 | SDRAMC_CR_TRP(3) // Command period (PRE to ACT) 21 ns min
\r
224 | SDRAMC_CR_TRCD(3) // Active Command to read/Write Command delay time 21ns min
\r
225 | SDRAMC_CR_TRAS(6) // Command period (ACT to PRE) 42ns min
\r
226 | SDRAMC_CR_TXSR(10U); //Exit self-refresh to active time 70ns Min
\r
228 /* 2. For mobile SDRAM, temperature-compensated self refresh (TCSR), drive strength (DS) and partial array
\r
229 self refresh (PASR) must be set in the Low Power Register. */
\r
231 /* 3. The SDRAM memory type must be set in the Memory Device Register.*/
\r
232 SDRAMC->SDRAMC_MDR = SDRAMC_MDR_MD_SDRAM;
\r
234 /* 4. A minimum pause of 200 ¦Ìs is provided to precede any signal toggle.*/
\r
235 for (i = 0; i < 100000; i++);
\r
237 /* 5. (1)A NOP command is issued to the SDRAM devices. The application must set Mode to 1 in the Mode
\r
238 Register and perform a write access to any SDRAM address.*/
\r
239 SDRAMC->SDRAMC_MR = SDRAMC_MR_MODE_NOP;
\r
241 for (i = 0; i < 100000; i++);
\r
242 /* 6. An All Banks Precharge command is issued to the SDRAM devices. The application must set Mode to 2 in
\r
243 the Mode Register and perform a write access to any SDRAM address. */
\r
244 SDRAMC->SDRAMC_MR = SDRAMC_MR_MODE_ALLBANKS_PRECHARGE;
\r
246 for (i = 0; i < 100000; i++);
\r
247 /* 7. Eight auto-refresh (CBR) cycles are provided. The application must set the Mode to 4 in the Mode Register
\r
248 and perform a write access to any SDRAM location eight times.*/
\r
249 for (i = 0 ; i< 8; i++) {
\r
250 SDRAMC->SDRAMC_MR = SDRAMC_MR_MODE_AUTO_REFRESH;
\r
253 for (i = 0; i < 100000; i++);
\r
254 /*8. A Mode Register set (MRS) cycle is issued to program the parameters of the SDRAM devices, in particular
\r
255 CAS latency and burst length. The application must set Mode to 3 in the Mode Register and perform a write
\r
256 access to the SDRAM. The write address must be chosen so that BA[1:0] are set to 0. For example, with a
\r
257 16-bit 128 MB SDRAM (12 rows, 9 columns, 4 banks) bank address, the SDRAM write access should be
\r
258 done at the address 0x70000000.*/
\r
259 SDRAMC->SDRAMC_MR = SDRAMC_MR_MODE_LOAD_MODEREG;
\r
262 for (i = 0; i < 100000; i++);
\r
263 /*9. For mobile SDRAM initialization, an Extended Mode Register set (EMRS) cycle is issued to program the
\r
264 SDRAM parameters (TCSR, PASR, DS). The application must set Mode to 5 in the Mode Register and
\r
265 perform a write access to the SDRAM. The write address must be chosen so that BA[1] or BA[0] are set to 1.
\r
266 For example, with a 16-bit 128 MB SDRAM, (12 rows, 9 columns, 4 banks) bank address the SDRAM write
\r
267 access should be done at the address 0x70800000 or 0x70400000. */
\r
268 //SDRAMC->SDRAMC_MR = SDRAMC_MR_MODE_EXT_LOAD_MODEREG;
\r
269 // *((uint8_t *)(pSdram + SDRAM_BA0)) = 0;
\r
271 /* 10. The application must go into Normal Mode, setting Mode to 0 in the Mode Register and performing a write
\r
272 access at any location in the SDRAM. */
\r
273 SDRAMC->SDRAMC_MR = SDRAMC_MR_MODE_NORMAL;
\r
275 for (i = 0; i < 100000; i++);
\r
276 /* 11. Write the refresh rate into the count field in the SDRAMC Refresh Timer register. (Refresh rate = delay
\r
277 between refresh cycles). The SDRAM device requires a refresh every 15.625 ¦Ìs or 7.81 ¦Ìs. With a 100 MHz
\r
278 frequency, the Refresh Timer Counter Register must be set with the value 1562(15.625 ¦Ìs x 100 MHz) or
\r
279 781(7.81 ¦Ìs x 100 MHz). */
\r
280 // For IS42S16100E, 2048 refresh cycle every 32ms, every 15.625 ¦Ìs
\r
281 SDRAMC->SDRAMC_TR = 2011; //1562;
\r
282 SDRAMC->SDRAMC_CR1 |= 1<<8;
\r
283 /* After initialization, the SDRAM devices are fully functional. */
\r