1 /**************************************************************************//**
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3 * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
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9 ******************************************************************************/
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10 /* Copyright (c) 2009 - 2014 ARM LIMITED
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12 All rights reserved.
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13 Redistribution and use in source and binary forms, with or without
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14 modification, are permitted provided that the following conditions are met:
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15 - Redistributions of source code must retain the above copyright
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16 notice, this list of conditions and the following disclaimer.
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17 - Redistributions in binary form must reproduce the above copyright
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18 notice, this list of conditions and the following disclaimer in the
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19 documentation and/or other materials provided with the distribution.
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20 - Neither the name of ARM nor the names of its contributors may be used
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21 to endorse or promote products derived from this software without
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22 specific prior written permission.
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24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
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28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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34 POSSIBILITY OF SUCH DAMAGE.
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35 ---------------------------------------------------------------------------*/
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38 #if defined ( __ICCARM__ )
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39 #pragma system_include /* treat file as system include file for MISRA check */
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42 #ifndef __CORE_CM0_H_GENERIC
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43 #define __CORE_CM0_H_GENERIC
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49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
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50 CMSIS violates the following MISRA-C:2004 rules:
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52 \li Required Rule 8.5, object/function definition in header file.<br>
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53 Function definitions in header files are used to allow 'inlining'.
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55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
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56 Unions are used for effective representation of core registers.
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58 \li Advisory Rule 19.7, Function-like macro defined.<br>
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59 Function-like macros are used to allow more efficient code.
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63 /*******************************************************************************
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65 ******************************************************************************/
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66 /** \ingroup Cortex_M0
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70 /* CMSIS CM0 definitions */
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71 #define __CM0_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
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72 #define __CM0_CMSIS_VERSION_SUB (0x30) /*!< [15:0] CMSIS HAL sub version */
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73 #define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | \
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74 __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
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76 #define __CORTEX_M (0x00) /*!< Cortex-M Core */
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79 #if defined ( __CC_ARM )
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80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
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81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
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82 #define __STATIC_INLINE static __inline
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84 #elif defined ( __GNUC__ )
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85 #define __ASM __asm /*!< asm keyword for GNU Compiler */
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86 #define __INLINE inline /*!< inline keyword for GNU Compiler */
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87 #define __STATIC_INLINE static inline
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89 #elif defined ( __ICCARM__ )
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90 #define __ASM __asm /*!< asm keyword for IAR Compiler */
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91 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
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92 #define __STATIC_INLINE static inline
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94 #elif defined ( __TMS470__ )
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95 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
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96 #define __STATIC_INLINE static inline
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98 #elif defined ( __TASKING__ )
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99 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
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100 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
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101 #define __STATIC_INLINE static inline
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103 #elif defined ( __CSMC__ ) /* Cosmic */
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105 #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
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106 #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
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107 #define __STATIC_INLINE static inline
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111 /** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
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113 #define __FPU_USED 0
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115 #if defined ( __CC_ARM )
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116 #if defined __TARGET_FPU_VFP
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117 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
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120 #elif defined ( __GNUC__ )
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121 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
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122 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
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125 #elif defined ( __ICCARM__ )
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126 #if defined __ARMVFP__
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127 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
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130 #elif defined ( __TMS470__ )
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131 #if defined __TI__VFP_SUPPORT____
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132 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
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135 #elif defined ( __TASKING__ )
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136 #if defined __FPU_VFP__
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137 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
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140 #elif defined ( __CSMC__ ) /* Cosmic */
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141 #if ( __CSMC__ & 0x400) // FPU present for parser
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142 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
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146 #include <stdint.h> /* standard types definitions */
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147 #include <core_cmInstr.h> /* Core Instruction Access */
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148 #include <core_cmFunc.h> /* Core Function Access */
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150 #endif /* __CORE_CM0_H_GENERIC */
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152 #ifndef __CMSIS_GENERIC
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154 #ifndef __CORE_CM0_H_DEPENDANT
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155 #define __CORE_CM0_H_DEPENDANT
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157 /* check device defines and use defaults */
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158 #if defined __CHECK_DEVICE_DEFINES
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160 #define __CM0_REV 0x0000
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161 #warning "__CM0_REV not defined in device header file; using default!"
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164 #ifndef __NVIC_PRIO_BITS
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165 #define __NVIC_PRIO_BITS 2
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166 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
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169 #ifndef __Vendor_SysTickConfig
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170 #define __Vendor_SysTickConfig 0
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171 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
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175 /* IO definitions (access restrictions to peripheral registers) */
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177 \defgroup CMSIS_glob_defs CMSIS Global Defines
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179 <strong>IO Type Qualifiers</strong> are used
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180 \li to specify the access to peripheral variables.
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181 \li for automatic generation of peripheral register debug information.
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184 #define __I volatile /*!< Defines 'read only' permissions */
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186 #define __I volatile const /*!< Defines 'read only' permissions */
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188 #define __O volatile /*!< Defines 'write only' permissions */
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189 #define __IO volatile /*!< Defines 'read / write' permissions */
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191 /*@} end of group Cortex_M0 */
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195 /*******************************************************************************
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196 * Register Abstraction
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197 Core Register contain:
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199 - Core NVIC Register
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200 - Core SCB Register
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201 - Core SysTick Register
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202 ******************************************************************************/
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203 /** \defgroup CMSIS_core_register Defines and Type Definitions
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204 \brief Type definitions and defines for Cortex-M processor based devices.
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207 /** \ingroup CMSIS_core_register
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208 \defgroup CMSIS_CORE Status and Control Registers
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209 \brief Core Register type definitions.
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213 /** \brief Union type to access the Application Program Status Register (APSR).
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219 #if (__CORTEX_M != 0x04)
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220 uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
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222 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
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223 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
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224 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
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226 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
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227 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
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228 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
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229 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
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230 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
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231 } b; /*!< Structure used for bit access */
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232 uint32_t w; /*!< Type used for word access */
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236 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
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242 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
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243 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
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244 } b; /*!< Structure used for bit access */
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245 uint32_t w; /*!< Type used for word access */
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249 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
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255 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
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256 #if (__CORTEX_M != 0x04)
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257 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
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259 uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
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260 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
\r
261 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
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263 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
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264 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
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265 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
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266 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
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267 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
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268 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
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269 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
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270 } b; /*!< Structure used for bit access */
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271 uint32_t w; /*!< Type used for word access */
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275 /** \brief Union type to access the Control Registers (CONTROL).
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281 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
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282 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
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283 uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
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284 uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
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285 } b; /*!< Structure used for bit access */
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286 uint32_t w; /*!< Type used for word access */
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289 /*@} end of group CMSIS_CORE */
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292 /** \ingroup CMSIS_core_register
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293 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
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294 \brief Type definitions for the NVIC Registers
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298 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
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302 __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
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303 uint32_t RESERVED0[31];
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304 __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
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305 uint32_t RSERVED1[31];
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306 __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
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307 uint32_t RESERVED2[31];
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308 __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
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309 uint32_t RESERVED3[31];
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310 uint32_t RESERVED4[64];
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311 __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
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314 /*@} end of group CMSIS_NVIC */
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317 /** \ingroup CMSIS_core_register
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318 \defgroup CMSIS_SCB System Control Block (SCB)
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319 \brief Type definitions for the System Control Block Registers
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323 /** \brief Structure type to access the System Control Block (SCB).
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327 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
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328 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
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329 uint32_t RESERVED0;
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330 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
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331 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
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332 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
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333 uint32_t RESERVED1;
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334 __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
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335 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
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338 /* SCB CPUID Register Definitions */
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339 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
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340 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
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342 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
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343 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
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345 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
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346 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
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348 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
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349 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
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351 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
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352 #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
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354 /* SCB Interrupt Control State Register Definitions */
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355 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
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356 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
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358 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
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359 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
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361 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
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362 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
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364 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
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365 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
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367 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
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368 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
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370 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
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371 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
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373 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
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374 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
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376 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
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377 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
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379 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
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380 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
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382 /* SCB Application Interrupt and Reset Control Register Definitions */
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383 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
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384 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
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386 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
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387 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
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389 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
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390 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
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392 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
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393 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
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395 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
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396 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
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398 /* SCB System Control Register Definitions */
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399 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
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400 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
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402 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
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403 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
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405 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
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406 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
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408 /* SCB Configuration Control Register Definitions */
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409 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
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410 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
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412 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
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413 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
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415 /* SCB System Handler Control and State Register Definitions */
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416 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
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417 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
\r
419 /*@} end of group CMSIS_SCB */
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422 /** \ingroup CMSIS_core_register
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423 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
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424 \brief Type definitions for the System Timer Registers.
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428 /** \brief Structure type to access the System Timer (SysTick).
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432 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
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433 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
\r
434 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
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435 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
\r
438 /* SysTick Control / Status Register Definitions */
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439 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
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440 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
\r
442 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
\r
443 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
\r
445 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
\r
446 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
\r
448 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
\r
449 #define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
\r
451 /* SysTick Reload Register Definitions */
\r
452 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
\r
453 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
\r
455 /* SysTick Current Register Definitions */
\r
456 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
\r
457 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
\r
459 /* SysTick Calibration Register Definitions */
\r
460 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
\r
461 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
\r
463 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
\r
464 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
\r
466 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
\r
467 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */
\r
469 /*@} end of group CMSIS_SysTick */
\r
472 /** \ingroup CMSIS_core_register
\r
473 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
\r
474 \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR)
\r
475 are only accessible over DAP and not via processor. Therefore
\r
476 they are not covered by the Cortex-M0 header file.
\r
479 /*@} end of group CMSIS_CoreDebug */
\r
482 /** \ingroup CMSIS_core_register
\r
483 \defgroup CMSIS_core_base Core Definitions
\r
484 \brief Definitions for base addresses, unions, and structures.
\r
488 /* Memory mapping of Cortex-M0 Hardware */
\r
489 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
\r
490 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
\r
491 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
\r
492 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
\r
494 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
\r
495 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
\r
496 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
\r
503 /*******************************************************************************
\r
504 * Hardware Abstraction Layer
\r
505 Core Function Interface contains:
\r
506 - Core NVIC Functions
\r
507 - Core SysTick Functions
\r
508 - Core Register Access Functions
\r
509 ******************************************************************************/
\r
510 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
\r
515 /* ########################## NVIC functions #################################### */
\r
516 /** \ingroup CMSIS_Core_FunctionInterface
\r
517 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
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518 \brief Functions that manage interrupts and exceptions via the NVIC.
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522 /* Interrupt Priorities are WORD accessible only under ARMv6M */
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523 /* The following MACROS handle generation of the register offset and byte masks */
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524 #define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 )
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525 #define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) )
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526 #define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) )
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529 /** \brief Enable External Interrupt
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531 The function enables a device-specific interrupt in the NVIC interrupt controller.
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533 \param [in] IRQn External interrupt number. Value cannot be negative.
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535 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
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537 NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
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541 /** \brief Disable External Interrupt
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543 The function disables a device-specific interrupt in the NVIC interrupt controller.
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545 \param [in] IRQn External interrupt number. Value cannot be negative.
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547 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
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549 NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
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553 /** \brief Get Pending Interrupt
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555 The function reads the pending register in the NVIC and returns the pending bit
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556 for the specified interrupt.
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558 \param [in] IRQn Interrupt number.
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560 \return 0 Interrupt status is not pending.
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561 \return 1 Interrupt status is pending.
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563 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
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565 return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
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569 /** \brief Set Pending Interrupt
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571 The function sets the pending bit of an external interrupt.
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573 \param [in] IRQn Interrupt number. Value cannot be negative.
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575 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
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577 NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
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581 /** \brief Clear Pending Interrupt
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583 The function clears the pending bit of an external interrupt.
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585 \param [in] IRQn External interrupt number. Value cannot be negative.
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587 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
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589 NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
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593 /** \brief Set Interrupt Priority
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595 The function sets the priority of an interrupt.
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597 \note The priority cannot be set for every core interrupt.
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599 \param [in] IRQn Interrupt number.
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600 \param [in] priority Priority to set.
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602 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
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605 SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
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606 (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
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608 NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
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609 (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
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613 /** \brief Get Interrupt Priority
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615 The function reads the priority of an interrupt. The interrupt
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616 number can be positive to specify an external (device specific)
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617 interrupt, or negative to specify an internal (core) interrupt.
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620 \param [in] IRQn Interrupt number.
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621 \return Interrupt Priority. Value is aligned automatically to the implemented
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622 priority bits of the microcontroller.
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624 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
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628 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */
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630 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
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634 /** \brief System Reset
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636 The function initiates a system reset request to reset the MCU.
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638 __STATIC_INLINE void NVIC_SystemReset(void)
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640 __DSB(); /* Ensure all outstanding memory accesses included
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641 buffered write are completed before reset */
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642 SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
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643 SCB_AIRCR_SYSRESETREQ_Msk);
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644 __DSB(); /* Ensure completion of memory access */
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645 while(1); /* wait until reset */
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648 /*@} end of CMSIS_Core_NVICFunctions */
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652 /* ################################## SysTick function ############################################ */
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653 /** \ingroup CMSIS_Core_FunctionInterface
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654 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
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655 \brief Functions that configure the System.
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659 #if (__Vendor_SysTickConfig == 0)
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661 /** \brief System Tick Configuration
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663 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
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664 Counter is in free running mode to generate periodic interrupts.
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666 \param [in] ticks Number of ticks between two interrupts.
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668 \return 0 Function succeeded.
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669 \return 1 Function failed.
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671 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
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672 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
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673 must contain a vendor-specific implementation of this function.
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676 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
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678 if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
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680 SysTick->LOAD = ticks - 1; /* set reload register */
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681 NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
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682 SysTick->VAL = 0; /* Load the SysTick Counter Value */
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683 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
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684 SysTick_CTRL_TICKINT_Msk |
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685 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
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686 return (0); /* Function successful */
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691 /*@} end of CMSIS_Core_SysTickFunctions */
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696 #endif /* __CORE_CM0_H_DEPENDANT */
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702 #endif /* __CMSIS_GENERIC */
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