1 /* ---------------------------------------------------------------------------- */
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2 /* Atmel Microcontroller Software Support */
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3 /* SAM Software Package License */
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4 /* ---------------------------------------------------------------------------- */
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5 /* Copyright (c) 2014, Atmel Corporation */
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7 /* All rights reserved. */
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9 /* Redistribution and use in source and binary forms, with or without */
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10 /* modification, are permitted provided that the following condition is met: */
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12 /* - Redistributions of source code must retain the above copyright notice, */
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13 /* this list of conditions and the disclaimer below. */
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15 /* Atmel's name may not be used to endorse or promote products derived from */
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16 /* this software without specific prior written permission. */
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18 /* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
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19 /* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
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20 /* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
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21 /* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
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22 /* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
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23 /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
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24 /* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
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25 /* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
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26 /* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
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27 /* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
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28 /* ---------------------------------------------------------------------------- */
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30 #ifndef _SAM_AFEC_COMPONENT_
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31 #define _SAM_AFEC_COMPONENT_
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33 /* ============================================================================= */
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34 /** SOFTWARE API DEFINITION FOR Analog-Front-End Controller */
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35 /* ============================================================================= */
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36 /** \addtogroup SAM_AFEC Analog-Front-End Controller */
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39 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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40 /** \brief Afec hardware registers */
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42 __O uint32_t AFEC_CR; /**< \brief (Afec Offset: 0x00) AFEC Control Register */
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43 __IO uint32_t AFEC_MR; /**< \brief (Afec Offset: 0x04) AFEC Mode Register */
\r
44 __IO uint32_t AFEC_EMR; /**< \brief (Afec Offset: 0x08) AFEC Extended Mode Register */
\r
45 __IO uint32_t AFEC_SEQ1R; /**< \brief (Afec Offset: 0x0C) AFEC Channel Sequence 1 Register */
\r
46 __IO uint32_t AFEC_SEQ2R; /**< \brief (Afec Offset: 0x10) AFEC Channel Sequence 2 Register */
\r
47 __O uint32_t AFEC_CHER; /**< \brief (Afec Offset: 0x14) AFEC Channel Enable Register */
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48 __O uint32_t AFEC_CHDR; /**< \brief (Afec Offset: 0x18) AFEC Channel Disable Register */
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49 __I uint32_t AFEC_CHSR; /**< \brief (Afec Offset: 0x1C) AFEC Channel Status Register */
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50 __I uint32_t AFEC_LCDR; /**< \brief (Afec Offset: 0x20) AFEC Last Converted Data Register */
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51 __O uint32_t AFEC_IER; /**< \brief (Afec Offset: 0x24) AFEC Interrupt Enable Register */
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52 __O uint32_t AFEC_IDR; /**< \brief (Afec Offset: 0x28) AFEC Interrupt Disable Register */
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53 __I uint32_t AFEC_IMR; /**< \brief (Afec Offset: 0x2C) AFEC Interrupt Mask Register */
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54 __I uint32_t AFEC_ISR; /**< \brief (Afec Offset: 0x30) AFEC Interrupt Status Register */
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55 __I uint32_t Reserved1[6];
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56 __I uint32_t AFEC_OVER; /**< \brief (Afec Offset: 0x4C) AFEC Overrun Status Register */
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57 __IO uint32_t AFEC_CWR; /**< \brief (Afec Offset: 0x50) AFEC Compare Window Register */
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58 __IO uint32_t AFEC_CG1R; /**< \brief (Afec Offset: 0x54) AFEC Channel Gain 1 Register */
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59 __IO uint32_t AFEC_CG2R; /**< \brief (Afec Offset: 0x58) AFEC Channel Gain 2 Register */
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60 __I uint32_t Reserved2[1];
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61 __IO uint32_t AFEC_DIFFR; /**< \brief (Afec Offset: 0x60) AFEC Channel Differential Register */
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62 __IO uint32_t AFEC_CSELR; /**< \brief (Afec Offset: 0x64) AFEC Channel Register Selection */
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63 __I uint32_t AFEC_CDR; /**< \brief (Afec Offset: 0x68) AFEC Channel Data Register */
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64 __IO uint32_t AFEC_COCR; /**< \brief (Afec Offset: 0x6C) AFEC Channel Offset Compensation Register */
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65 __IO uint32_t AFEC_TEMPMR; /**< \brief (Afec Offset: 0x70) AFEC Temperature Sensor Mode Register */
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66 __IO uint32_t AFEC_TEMPCWR; /**< \brief (Afec Offset: 0x74) AFEC Temperature Compare Window Register */
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67 __I uint32_t Reserved3[7];
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68 __IO uint32_t AFEC_ACR; /**< \brief (Afec Offset: 0x94) AFEC Analog Control Register */
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69 __I uint32_t Reserved4[2];
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70 __IO uint32_t AFEC_SHMR; /**< \brief (Afec Offset: 0xA0) AFEC Sample & Hold Mode Register */
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71 __I uint32_t Reserved5[11];
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72 __IO uint32_t AFEC_COSR; /**< \brief (Afec Offset: 0xD0) AFEC Correction Select Register */
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73 __IO uint32_t AFEC_CVR; /**< \brief (Afec Offset: 0xD4) AFEC Correction Values Register */
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74 __IO uint32_t AFEC_CECR; /**< \brief (Afec Offset: 0xD8) AFEC Channel Error Correction Register */
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75 __I uint32_t Reserved6[2];
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76 __IO uint32_t AFEC_WPMR; /**< \brief (Afec Offset: 0xE4) AFEC Write Protection Mode Register */
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77 __I uint32_t AFEC_WPSR; /**< \brief (Afec Offset: 0xE8) AFEC Write Protection Status Register */
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78 __I uint32_t Reserved7[4];
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79 __I uint32_t AFEC_VERSION; /**< \brief (Afec Offset: 0xFC) AFEC Version Register */
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81 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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82 /* -------- AFEC_CR : (AFEC Offset: 0x00) AFEC Control Register -------- */
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83 #define AFEC_CR_SWRST (0x1u << 0) /**< \brief (AFEC_CR) Software Reset */
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84 #define AFEC_CR_START (0x1u << 1) /**< \brief (AFEC_CR) Start Conversion */
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85 /* -------- AFEC_MR : (AFEC Offset: 0x04) AFEC Mode Register -------- */
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86 #define AFEC_MR_TRGEN (0x1u << 0) /**< \brief (AFEC_MR) Trigger Enable */
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87 #define AFEC_MR_TRGEN_DIS (0x0u << 0) /**< \brief (AFEC_MR) Hardware triggers are disabled. Starting a conversion is only possible by software. */
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88 #define AFEC_MR_TRGEN_EN (0x1u << 0) /**< \brief (AFEC_MR) Hardware trigger selected by TRGSEL field is enabled. */
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89 #define AFEC_MR_TRGSEL_Pos 1
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90 #define AFEC_MR_TRGSEL_Msk (0x7u << AFEC_MR_TRGSEL_Pos) /**< \brief (AFEC_MR) Trigger Selection */
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91 #define AFEC_MR_TRGSEL_AFEC_TRIG0 (0x0u << 1) /**< \brief (AFEC_MR) ADC_TRIG0 */
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92 #define AFEC_MR_TRGSEL_AFEC_TRIG1 (0x1u << 1) /**< \brief (AFEC_MR) ADC_TRIG1 */
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93 #define AFEC_MR_TRGSEL_AFEC_TRIG2 (0x2u << 1) /**< \brief (AFEC_MR) ADC_TRIG2 */
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94 #define AFEC_MR_TRGSEL_AFEC_TRIG3 (0x3u << 1) /**< \brief (AFEC_MR) ADC_TRIG3 */
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95 #define AFEC_MR_TRGSEL_AFEC_TRIG4 (0x4u << 1) /**< \brief (AFEC_MR) ADC_TRIG4 */
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96 #define AFEC_MR_TRGSEL_AFEC_TRIG5 (0x5u << 1) /**< \brief (AFEC_MR) ADC_TRIG5 */
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97 #define AFEC_MR_TRGSEL_AFEC_TRIG6 (0x6u << 1) /**< \brief (AFEC_MR) ADC_TRIG6 */
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98 #define AFEC_MR_SLEEP (0x1u << 5) /**< \brief (AFEC_MR) Sleep Mode */
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99 #define AFEC_MR_SLEEP_NORMAL (0x0u << 5) /**< \brief (AFEC_MR) Normal Mode: The AFEC Core and reference voltage circuitry are kept ON between conversions */
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100 #define AFEC_MR_SLEEP_SLEEP (0x1u << 5) /**< \brief (AFEC_MR) Sleep Mode: The AFEC Core and reference voltage circuitry are OFF between conversions */
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101 #define AFEC_MR_FWUP (0x1u << 6) /**< \brief (AFEC_MR) Fast Wake-up */
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102 #define AFEC_MR_FWUP_OFF (0x0u << 6) /**< \brief (AFEC_MR) Normal Sleep Mode: The sleep mode is defined by the SLEEP bit */
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103 #define AFEC_MR_FWUP_ON (0x1u << 6) /**< \brief (AFEC_MR) Fast Wake Up Sleep Mode: The Voltage reference is ON between conversions and AFEC Core is OFF */
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104 #define AFEC_MR_FREERUN (0x1u << 7) /**< \brief (AFEC_MR) Free Run Mode */
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105 #define AFEC_MR_FREERUN_OFF (0x0u << 7) /**< \brief (AFEC_MR) Normal Mode */
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106 #define AFEC_MR_FREERUN_ON (0x1u << 7) /**< \brief (AFEC_MR) Free Run Mode: Never wait for any trigger. */
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107 #define AFEC_MR_PRESCAL_Pos 8
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108 #define AFEC_MR_PRESCAL_Msk (0xffu << AFEC_MR_PRESCAL_Pos) /**< \brief (AFEC_MR) Prescaler Rate Selection */
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109 #define AFEC_MR_PRESCAL(value) ((AFEC_MR_PRESCAL_Msk & ((value) << AFEC_MR_PRESCAL_Pos)))
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110 #define AFEC_MR_STARTUP_Pos 16
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111 #define AFEC_MR_STARTUP_Msk (0xfu << AFEC_MR_STARTUP_Pos) /**< \brief (AFEC_MR) Start-up Time */
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112 #define AFEC_MR_STARTUP_SUT0 (0x0u << 16) /**< \brief (AFEC_MR) 0 periods of AFEClock */
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113 #define AFEC_MR_STARTUP_SUT8 (0x1u << 16) /**< \brief (AFEC_MR) 8 periods of AFEClock */
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114 #define AFEC_MR_STARTUP_SUT16 (0x2u << 16) /**< \brief (AFEC_MR) 16 periods of AFEClock */
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115 #define AFEC_MR_STARTUP_SUT24 (0x3u << 16) /**< \brief (AFEC_MR) 24 periods of AFEClock */
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116 #define AFEC_MR_STARTUP_SUT64 (0x4u << 16) /**< \brief (AFEC_MR) 64 periods of AFEClock */
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117 #define AFEC_MR_STARTUP_SUT80 (0x5u << 16) /**< \brief (AFEC_MR) 80 periods of AFEClock */
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118 #define AFEC_MR_STARTUP_SUT96 (0x6u << 16) /**< \brief (AFEC_MR) 96 periods of AFEClock */
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119 #define AFEC_MR_STARTUP_SUT112 (0x7u << 16) /**< \brief (AFEC_MR) 112 periods of AFEClock */
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120 #define AFEC_MR_STARTUP_SUT512 (0x8u << 16) /**< \brief (AFEC_MR) 512 periods of AFEClock */
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121 #define AFEC_MR_STARTUP_SUT576 (0x9u << 16) /**< \brief (AFEC_MR) 576 periods of AFEClock */
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122 #define AFEC_MR_STARTUP_SUT640 (0xAu << 16) /**< \brief (AFEC_MR) 640 periods of AFEClock */
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123 #define AFEC_MR_STARTUP_SUT704 (0xBu << 16) /**< \brief (AFEC_MR) 704 periods of AFEClock */
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124 #define AFEC_MR_STARTUP_SUT768 (0xCu << 16) /**< \brief (AFEC_MR) 768 periods of AFEClock */
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125 #define AFEC_MR_STARTUP_SUT832 (0xDu << 16) /**< \brief (AFEC_MR) 832 periods of AFEClock */
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126 #define AFEC_MR_STARTUP_SUT896 (0xEu << 16) /**< \brief (AFEC_MR) 896 periods of AFEClock */
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127 #define AFEC_MR_STARTUP_SUT960 (0xFu << 16) /**< \brief (AFEC_MR) 960 periods of AFEClock */
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128 #define AFEC_MR_ANACH (0x1u << 23) /**< \brief (AFEC_MR) Analog Change */
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129 #define AFEC_MR_ANACH_NONE (0x0u << 23) /**< \brief (AFEC_MR) No analog change on channel switching: DIFF0, GAIN0 are used for all channels */
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130 #define AFEC_MR_ANACH_ALLOWED (0x1u << 23) /**< \brief (AFEC_MR) Allows different analog settings for each channel. See AFEC_CGR. */
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131 #define AFEC_MR_TRACKTIM_Pos 24
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132 #define AFEC_MR_TRACKTIM_Msk (0xfu << AFEC_MR_TRACKTIM_Pos) /**< \brief (AFEC_MR) Tracking Time */
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133 #define AFEC_MR_TRACKTIM(value) ((AFEC_MR_TRACKTIM_Msk & ((value) << AFEC_MR_TRACKTIM_Pos)))
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134 #define AFEC_MR_TRANSFER_Pos 28
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135 #define AFEC_MR_TRANSFER_Msk (0x3u << AFEC_MR_TRANSFER_Pos) /**< \brief (AFEC_MR) Transfer Period */
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136 #define AFEC_MR_TRANSFER(value) ((AFEC_MR_TRANSFER_Msk & ((value) << AFEC_MR_TRANSFER_Pos)))
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137 #define AFEC_MR_USEQ (0x1u << 31) /**< \brief (AFEC_MR) Use Sequence Enable */
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138 #define AFEC_MR_USEQ_NUM_ORDER (0x0u << 31) /**< \brief (AFEC_MR) Normal Mode: The controller converts channels in a simple numeric order. */
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139 #define AFEC_MR_USEQ_REG_ORDER (0x1u << 31) /**< \brief (AFEC_MR) User Sequence Mode: The sequence respects what is defined in AFEC_SEQR1 and AFEC_SEQR2. */
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140 /* -------- AFEC_EMR : (AFEC Offset: 0x08) AFEC Extended Mode Register -------- */
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141 #define AFEC_EMR_CMPMODE_Pos 0
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142 #define AFEC_EMR_CMPMODE_Msk (0x3u << AFEC_EMR_CMPMODE_Pos) /**< \brief (AFEC_EMR) Comparison Mode */
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143 #define AFEC_EMR_CMPMODE_LOW (0x0u << 0) /**< \brief (AFEC_EMR) Generates an event when the converted data is lower than the low threshold of the window. */
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144 #define AFEC_EMR_CMPMODE_HIGH (0x1u << 0) /**< \brief (AFEC_EMR) Generates an event when the converted data is higher than the high threshold of the window. */
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145 #define AFEC_EMR_CMPMODE_IN (0x2u << 0) /**< \brief (AFEC_EMR) Generates an event when the converted data is in the comparison window. */
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146 #define AFEC_EMR_CMPMODE_OUT (0x3u << 0) /**< \brief (AFEC_EMR) Generates an event when the converted data is out of the comparison window. */
\r
147 #define AFEC_EMR_CMPSEL_Pos 3
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148 #define AFEC_EMR_CMPSEL_Msk (0x1fu << AFEC_EMR_CMPSEL_Pos) /**< \brief (AFEC_EMR) Comparison Selected Channel */
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149 #define AFEC_EMR_CMPSEL(value) ((AFEC_EMR_CMPSEL_Msk & ((value) << AFEC_EMR_CMPSEL_Pos)))
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150 #define AFEC_EMR_CMPALL (0x1u << 9) /**< \brief (AFEC_EMR) Compare All Channels */
\r
151 #define AFEC_EMR_CMPFILTER_Pos 12
\r
152 #define AFEC_EMR_CMPFILTER_Msk (0x3u << AFEC_EMR_CMPFILTER_Pos) /**< \brief (AFEC_EMR) Compare Event Filtering */
\r
153 #define AFEC_EMR_CMPFILTER(value) ((AFEC_EMR_CMPFILTER_Msk & ((value) << AFEC_EMR_CMPFILTER_Pos)))
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154 #define AFEC_EMR_RES_Pos 16
\r
155 #define AFEC_EMR_RES_Msk (0x7u << AFEC_EMR_RES_Pos) /**< \brief (AFEC_EMR) Resolution */
\r
156 #define AFEC_EMR_RES_NO_AVERAGE (0x0u << 16) /**< \brief (AFEC_EMR) 12-bit resolution, AFEC sample rate is maximum (no averaging). */
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157 #define AFEC_EMR_RES_OSR4 (0x2u << 16) /**< \brief (AFEC_EMR) 13-bit resolution, AFEC sample rate divided by 4 (averaging). */
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158 #define AFEC_EMR_RES_OSR16 (0x3u << 16) /**< \brief (AFEC_EMR) 14-bit resolution, AFEC sample rate divided by 16 (averaging). */
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159 #define AFEC_EMR_RES_OSR64 (0x4u << 16) /**< \brief (AFEC_EMR) 15-bit resolution, AFEC sample rate divided by 64 (averaging). */
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160 #define AFEC_EMR_RES_OSR256 (0x5u << 16) /**< \brief (AFEC_EMR) 16-bit resolution, AFEC sample rate divided by 256 (averaging). */
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161 #define AFEC_EMR_AFEMODE_Pos 20
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162 #define AFEC_EMR_AFEMODE_Msk (0x3u << AFEC_EMR_AFEMODE_Pos) /**< \brief (AFEC_EMR) AFE Running Mode */
\r
163 #define AFEC_EMR_AFEMODE_NORMAL (0x0u << 20) /**< \brief (AFEC_EMR) Normal mode of operation. */
\r
164 #define AFEC_EMR_AFEMODE_OFFSET_ERROR (0x1u << 20) /**< \brief (AFEC_EMR) Offset Error mode to measure the offset error. See Table 1-9 on page 35. */
\r
165 #define AFEC_EMR_AFEMODE_GAIN_ERROR_HIGH (0x2u << 20) /**< \brief (AFEC_EMR) Gain Error mode to measure the gain error. See Table 1-9 on page 35. */
\r
166 #define AFEC_EMR_AFEMODE_GAIN_ERROR_LOW (0x3u << 20) /**< \brief (AFEC_EMR) */
\r
167 #define AFEC_EMR_TAG (0x1u << 24) /**< \brief (AFEC_EMR) TAG of the AFEC_LDCR */
\r
168 #define AFEC_EMR_STM (0x1u << 25) /**< \brief (AFEC_EMR) Single Trigger Mode */
\r
169 #define AFEC_EMR_SIGNMODE_Pos 28
\r
170 #define AFEC_EMR_SIGNMODE_Msk (0x3u << AFEC_EMR_SIGNMODE_Pos) /**< \brief (AFEC_EMR) Sign Mode */
\r
171 #define AFEC_EMR_SIGNMODE_SE_UNSG_DF_SIGN (0x0u << 28) /**< \brief (AFEC_EMR) Single-Ended Channels: Unsigned conversions.Differential Channels: Signed conversions. */
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172 #define AFEC_EMR_SIGNMODE_SE_SIGN_DF_UNSG (0x1u << 28) /**< \brief (AFEC_EMR) Single-Ended Channels: Signed conversions.Differential Channels: Unsigned conversions. */
\r
173 #define AFEC_EMR_SIGNMODE_ALL_UNSIGNED (0x2u << 28) /**< \brief (AFEC_EMR) All Channels: Unsigned conversions. */
\r
174 #define AFEC_EMR_SIGNMODE_ALL_SIGNED (0x3u << 28) /**< \brief (AFEC_EMR) All Channels: Signed conversions. */
\r
175 /* -------- AFEC_SEQ1R : (AFEC Offset: 0x0C) AFEC Channel Sequence 1 Register -------- */
\r
176 #define AFEC_SEQ1R_USCH0_Pos 0
\r
177 #define AFEC_SEQ1R_USCH0_Msk (0xfu << AFEC_SEQ1R_USCH0_Pos) /**< \brief (AFEC_SEQ1R) User Sequence Number 0 */
\r
178 #define AFEC_SEQ1R_USCH0(value) ((AFEC_SEQ1R_USCH0_Msk & ((value) << AFEC_SEQ1R_USCH0_Pos)))
\r
179 #define AFEC_SEQ1R_USCH1_Pos 4
\r
180 #define AFEC_SEQ1R_USCH1_Msk (0xfu << AFEC_SEQ1R_USCH1_Pos) /**< \brief (AFEC_SEQ1R) User Sequence Number 1 */
\r
181 #define AFEC_SEQ1R_USCH1(value) ((AFEC_SEQ1R_USCH1_Msk & ((value) << AFEC_SEQ1R_USCH1_Pos)))
\r
182 #define AFEC_SEQ1R_USCH2_Pos 8
\r
183 #define AFEC_SEQ1R_USCH2_Msk (0xfu << AFEC_SEQ1R_USCH2_Pos) /**< \brief (AFEC_SEQ1R) User Sequence Number 2 */
\r
184 #define AFEC_SEQ1R_USCH2(value) ((AFEC_SEQ1R_USCH2_Msk & ((value) << AFEC_SEQ1R_USCH2_Pos)))
\r
185 #define AFEC_SEQ1R_USCH3_Pos 12
\r
186 #define AFEC_SEQ1R_USCH3_Msk (0xfu << AFEC_SEQ1R_USCH3_Pos) /**< \brief (AFEC_SEQ1R) User Sequence Number 3 */
\r
187 #define AFEC_SEQ1R_USCH3(value) ((AFEC_SEQ1R_USCH3_Msk & ((value) << AFEC_SEQ1R_USCH3_Pos)))
\r
188 #define AFEC_SEQ1R_USCH4_Pos 16
\r
189 #define AFEC_SEQ1R_USCH4_Msk (0xfu << AFEC_SEQ1R_USCH4_Pos) /**< \brief (AFEC_SEQ1R) User Sequence Number 4 */
\r
190 #define AFEC_SEQ1R_USCH4(value) ((AFEC_SEQ1R_USCH4_Msk & ((value) << AFEC_SEQ1R_USCH4_Pos)))
\r
191 #define AFEC_SEQ1R_USCH5_Pos 20
\r
192 #define AFEC_SEQ1R_USCH5_Msk (0xfu << AFEC_SEQ1R_USCH5_Pos) /**< \brief (AFEC_SEQ1R) User Sequence Number 5 */
\r
193 #define AFEC_SEQ1R_USCH5(value) ((AFEC_SEQ1R_USCH5_Msk & ((value) << AFEC_SEQ1R_USCH5_Pos)))
\r
194 #define AFEC_SEQ1R_USCH6_Pos 24
\r
195 #define AFEC_SEQ1R_USCH6_Msk (0xfu << AFEC_SEQ1R_USCH6_Pos) /**< \brief (AFEC_SEQ1R) User Sequence Number 6 */
\r
196 #define AFEC_SEQ1R_USCH6(value) ((AFEC_SEQ1R_USCH6_Msk & ((value) << AFEC_SEQ1R_USCH6_Pos)))
\r
197 #define AFEC_SEQ1R_USCH7_Pos 28
\r
198 #define AFEC_SEQ1R_USCH7_Msk (0xfu << AFEC_SEQ1R_USCH7_Pos) /**< \brief (AFEC_SEQ1R) User Sequence Number 7 */
\r
199 #define AFEC_SEQ1R_USCH7(value) ((AFEC_SEQ1R_USCH7_Msk & ((value) << AFEC_SEQ1R_USCH7_Pos)))
\r
200 /* -------- AFEC_SEQ2R : (AFEC Offset: 0x10) AFEC Channel Sequence 2 Register -------- */
\r
201 #define AFEC_SEQ2R_USCH8_Pos 0
\r
202 #define AFEC_SEQ2R_USCH8_Msk (0xfu << AFEC_SEQ2R_USCH8_Pos) /**< \brief (AFEC_SEQ2R) User Sequence Number 8 */
\r
203 #define AFEC_SEQ2R_USCH8(value) ((AFEC_SEQ2R_USCH8_Msk & ((value) << AFEC_SEQ2R_USCH8_Pos)))
\r
204 #define AFEC_SEQ2R_USCH9_Pos 4
\r
205 #define AFEC_SEQ2R_USCH9_Msk (0xfu << AFEC_SEQ2R_USCH9_Pos) /**< \brief (AFEC_SEQ2R) User Sequence Number 9 */
\r
206 #define AFEC_SEQ2R_USCH9(value) ((AFEC_SEQ2R_USCH9_Msk & ((value) << AFEC_SEQ2R_USCH9_Pos)))
\r
207 #define AFEC_SEQ2R_USCH10_Pos 8
\r
208 #define AFEC_SEQ2R_USCH10_Msk (0xfu << AFEC_SEQ2R_USCH10_Pos) /**< \brief (AFEC_SEQ2R) User Sequence Number 10 */
\r
209 #define AFEC_SEQ2R_USCH10(value) ((AFEC_SEQ2R_USCH10_Msk & ((value) << AFEC_SEQ2R_USCH10_Pos)))
\r
210 #define AFEC_SEQ2R_USCH11_Pos 12
\r
211 #define AFEC_SEQ2R_USCH11_Msk (0xfu << AFEC_SEQ2R_USCH11_Pos) /**< \brief (AFEC_SEQ2R) User Sequence Number 11 */
\r
212 #define AFEC_SEQ2R_USCH11(value) ((AFEC_SEQ2R_USCH11_Msk & ((value) << AFEC_SEQ2R_USCH11_Pos)))
\r
213 #define AFEC_SEQ2R_USCH12_Pos 16
\r
214 #define AFEC_SEQ2R_USCH12_Msk (0xfu << AFEC_SEQ2R_USCH12_Pos) /**< \brief (AFEC_SEQ2R) User Sequence Number 12 */
\r
215 #define AFEC_SEQ2R_USCH12(value) ((AFEC_SEQ2R_USCH12_Msk & ((value) << AFEC_SEQ2R_USCH12_Pos)))
\r
216 #define AFEC_SEQ2R_USCH13_Pos 20
\r
217 #define AFEC_SEQ2R_USCH13_Msk (0xfu << AFEC_SEQ2R_USCH13_Pos) /**< \brief (AFEC_SEQ2R) User Sequence Number 13 */
\r
218 #define AFEC_SEQ2R_USCH13(value) ((AFEC_SEQ2R_USCH13_Msk & ((value) << AFEC_SEQ2R_USCH13_Pos)))
\r
219 #define AFEC_SEQ2R_USCH14_Pos 24
\r
220 #define AFEC_SEQ2R_USCH14_Msk (0xfu << AFEC_SEQ2R_USCH14_Pos) /**< \brief (AFEC_SEQ2R) User Sequence Number 14 */
\r
221 #define AFEC_SEQ2R_USCH14(value) ((AFEC_SEQ2R_USCH14_Msk & ((value) << AFEC_SEQ2R_USCH14_Pos)))
\r
222 #define AFEC_SEQ2R_USCH15_Pos 28
\r
223 #define AFEC_SEQ2R_USCH15_Msk (0xfu << AFEC_SEQ2R_USCH15_Pos) /**< \brief (AFEC_SEQ2R) User Sequence Number 15 */
\r
224 #define AFEC_SEQ2R_USCH15(value) ((AFEC_SEQ2R_USCH15_Msk & ((value) << AFEC_SEQ2R_USCH15_Pos)))
\r
225 /* -------- AFEC_CHER : (AFEC Offset: 0x14) AFEC Channel Enable Register -------- */
\r
226 #define AFEC_CHER_CH0 (0x1u << 0) /**< \brief (AFEC_CHER) Channel 0 Enable */
\r
227 #define AFEC_CHER_CH1 (0x1u << 1) /**< \brief (AFEC_CHER) Channel 1 Enable */
\r
228 #define AFEC_CHER_CH2 (0x1u << 2) /**< \brief (AFEC_CHER) Channel 2 Enable */
\r
229 #define AFEC_CHER_CH3 (0x1u << 3) /**< \brief (AFEC_CHER) Channel 3 Enable */
\r
230 #define AFEC_CHER_CH4 (0x1u << 4) /**< \brief (AFEC_CHER) Channel 4 Enable */
\r
231 #define AFEC_CHER_CH5 (0x1u << 5) /**< \brief (AFEC_CHER) Channel 5 Enable */
\r
232 #define AFEC_CHER_CH6 (0x1u << 6) /**< \brief (AFEC_CHER) Channel 6 Enable */
\r
233 #define AFEC_CHER_CH7 (0x1u << 7) /**< \brief (AFEC_CHER) Channel 7 Enable */
\r
234 #define AFEC_CHER_CH8 (0x1u << 8) /**< \brief (AFEC_CHER) Channel 8 Enable */
\r
235 #define AFEC_CHER_CH9 (0x1u << 9) /**< \brief (AFEC_CHER) Channel 9 Enable */
\r
236 #define AFEC_CHER_CH10 (0x1u << 10) /**< \brief (AFEC_CHER) Channel 10 Enable */
\r
237 #define AFEC_CHER_CH11 (0x1u << 11) /**< \brief (AFEC_CHER) Channel 11 Enable */
\r
238 /* -------- AFEC_CHDR : (AFEC Offset: 0x18) AFEC Channel Disable Register -------- */
\r
239 #define AFEC_CHDR_CH0 (0x1u << 0) /**< \brief (AFEC_CHDR) Channel 0 Disable */
\r
240 #define AFEC_CHDR_CH1 (0x1u << 1) /**< \brief (AFEC_CHDR) Channel 1 Disable */
\r
241 #define AFEC_CHDR_CH2 (0x1u << 2) /**< \brief (AFEC_CHDR) Channel 2 Disable */
\r
242 #define AFEC_CHDR_CH3 (0x1u << 3) /**< \brief (AFEC_CHDR) Channel 3 Disable */
\r
243 #define AFEC_CHDR_CH4 (0x1u << 4) /**< \brief (AFEC_CHDR) Channel 4 Disable */
\r
244 #define AFEC_CHDR_CH5 (0x1u << 5) /**< \brief (AFEC_CHDR) Channel 5 Disable */
\r
245 #define AFEC_CHDR_CH6 (0x1u << 6) /**< \brief (AFEC_CHDR) Channel 6 Disable */
\r
246 #define AFEC_CHDR_CH7 (0x1u << 7) /**< \brief (AFEC_CHDR) Channel 7 Disable */
\r
247 #define AFEC_CHDR_CH8 (0x1u << 8) /**< \brief (AFEC_CHDR) Channel 8 Disable */
\r
248 #define AFEC_CHDR_CH9 (0x1u << 9) /**< \brief (AFEC_CHDR) Channel 9 Disable */
\r
249 #define AFEC_CHDR_CH10 (0x1u << 10) /**< \brief (AFEC_CHDR) Channel 10 Disable */
\r
250 #define AFEC_CHDR_CH11 (0x1u << 11) /**< \brief (AFEC_CHDR) Channel 11 Disable */
\r
251 /* -------- AFEC_CHSR : (AFEC Offset: 0x1C) AFEC Channel Status Register -------- */
\r
252 #define AFEC_CHSR_CH0 (0x1u << 0) /**< \brief (AFEC_CHSR) Channel 0 Status */
\r
253 #define AFEC_CHSR_CH1 (0x1u << 1) /**< \brief (AFEC_CHSR) Channel 1 Status */
\r
254 #define AFEC_CHSR_CH2 (0x1u << 2) /**< \brief (AFEC_CHSR) Channel 2 Status */
\r
255 #define AFEC_CHSR_CH3 (0x1u << 3) /**< \brief (AFEC_CHSR) Channel 3 Status */
\r
256 #define AFEC_CHSR_CH4 (0x1u << 4) /**< \brief (AFEC_CHSR) Channel 4 Status */
\r
257 #define AFEC_CHSR_CH5 (0x1u << 5) /**< \brief (AFEC_CHSR) Channel 5 Status */
\r
258 #define AFEC_CHSR_CH6 (0x1u << 6) /**< \brief (AFEC_CHSR) Channel 6 Status */
\r
259 #define AFEC_CHSR_CH7 (0x1u << 7) /**< \brief (AFEC_CHSR) Channel 7 Status */
\r
260 #define AFEC_CHSR_CH8 (0x1u << 8) /**< \brief (AFEC_CHSR) Channel 8 Status */
\r
261 #define AFEC_CHSR_CH9 (0x1u << 9) /**< \brief (AFEC_CHSR) Channel 9 Status */
\r
262 #define AFEC_CHSR_CH10 (0x1u << 10) /**< \brief (AFEC_CHSR) Channel 10 Status */
\r
263 #define AFEC_CHSR_CH11 (0x1u << 11) /**< \brief (AFEC_CHSR) Channel 11 Status */
\r
264 /* -------- AFEC_LCDR : (AFEC Offset: 0x20) AFEC Last Converted Data Register -------- */
\r
265 #define AFEC_LCDR_LDATA_Pos 0
\r
266 #define AFEC_LCDR_LDATA_Msk (0xffffu << AFEC_LCDR_LDATA_Pos) /**< \brief (AFEC_LCDR) Last Data Converted */
\r
267 #define AFEC_LCDR_CHNB_Pos 24
\r
268 #define AFEC_LCDR_CHNB_Msk (0x1fu << AFEC_LCDR_CHNB_Pos) /**< \brief (AFEC_LCDR) Channel Number */
\r
269 /* -------- AFEC_IER : (AFEC Offset: 0x24) AFEC Interrupt Enable Register -------- */
\r
270 #define AFEC_IER_EOC0 (0x1u << 0) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 0 */
\r
271 #define AFEC_IER_EOC1 (0x1u << 1) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 1 */
\r
272 #define AFEC_IER_EOC2 (0x1u << 2) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 2 */
\r
273 #define AFEC_IER_EOC3 (0x1u << 3) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 3 */
\r
274 #define AFEC_IER_EOC4 (0x1u << 4) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 4 */
\r
275 #define AFEC_IER_EOC5 (0x1u << 5) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 5 */
\r
276 #define AFEC_IER_EOC6 (0x1u << 6) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 6 */
\r
277 #define AFEC_IER_EOC7 (0x1u << 7) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 7 */
\r
278 #define AFEC_IER_EOC8 (0x1u << 8) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 8 */
\r
279 #define AFEC_IER_EOC9 (0x1u << 9) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 9 */
\r
280 #define AFEC_IER_EOC10 (0x1u << 10) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 10 */
\r
281 #define AFEC_IER_EOC11 (0x1u << 11) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 11 */
\r
282 #define AFEC_IER_DRDY (0x1u << 24) /**< \brief (AFEC_IER) Data Ready Interrupt Enable */
\r
283 #define AFEC_IER_GOVRE (0x1u << 25) /**< \brief (AFEC_IER) General Overrun Error Interrupt Enable */
\r
284 #define AFEC_IER_COMPE (0x1u << 26) /**< \brief (AFEC_IER) Comparison Event Interrupt Enable */
\r
285 #define AFEC_IER_TEMPCHG (0x1u << 30) /**< \brief (AFEC_IER) Temperature Change Interrupt Enable */
\r
286 /* -------- AFEC_IDR : (AFEC Offset: 0x28) AFEC Interrupt Disable Register -------- */
\r
287 #define AFEC_IDR_EOC0 (0x1u << 0) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 0 */
\r
288 #define AFEC_IDR_EOC1 (0x1u << 1) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 1 */
\r
289 #define AFEC_IDR_EOC2 (0x1u << 2) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 2 */
\r
290 #define AFEC_IDR_EOC3 (0x1u << 3) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 3 */
\r
291 #define AFEC_IDR_EOC4 (0x1u << 4) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 4 */
\r
292 #define AFEC_IDR_EOC5 (0x1u << 5) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 5 */
\r
293 #define AFEC_IDR_EOC6 (0x1u << 6) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 6 */
\r
294 #define AFEC_IDR_EOC7 (0x1u << 7) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 7 */
\r
295 #define AFEC_IDR_EOC8 (0x1u << 8) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 8 */
\r
296 #define AFEC_IDR_EOC9 (0x1u << 9) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 9 */
\r
297 #define AFEC_IDR_EOC10 (0x1u << 10) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 10 */
\r
298 #define AFEC_IDR_EOC11 (0x1u << 11) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 11 */
\r
299 #define AFEC_IDR_DRDY (0x1u << 24) /**< \brief (AFEC_IDR) Data Ready Interrupt Disable */
\r
300 #define AFEC_IDR_GOVRE (0x1u << 25) /**< \brief (AFEC_IDR) General Overrun Error Interrupt Disable */
\r
301 #define AFEC_IDR_COMPE (0x1u << 26) /**< \brief (AFEC_IDR) Comparison Event Interrupt Disable */
\r
302 #define AFEC_IDR_TEMPCHG (0x1u << 30) /**< \brief (AFEC_IDR) Temperature Change Interrupt Disable */
\r
303 /* -------- AFEC_IMR : (AFEC Offset: 0x2C) AFEC Interrupt Mask Register -------- */
\r
304 #define AFEC_IMR_EOC0 (0x1u << 0) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 0 */
\r
305 #define AFEC_IMR_EOC1 (0x1u << 1) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 1 */
\r
306 #define AFEC_IMR_EOC2 (0x1u << 2) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 2 */
\r
307 #define AFEC_IMR_EOC3 (0x1u << 3) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 3 */
\r
308 #define AFEC_IMR_EOC4 (0x1u << 4) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 4 */
\r
309 #define AFEC_IMR_EOC5 (0x1u << 5) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 5 */
\r
310 #define AFEC_IMR_EOC6 (0x1u << 6) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 6 */
\r
311 #define AFEC_IMR_EOC7 (0x1u << 7) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 7 */
\r
312 #define AFEC_IMR_EOC8 (0x1u << 8) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 8 */
\r
313 #define AFEC_IMR_EOC9 (0x1u << 9) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 9 */
\r
314 #define AFEC_IMR_EOC10 (0x1u << 10) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 10 */
\r
315 #define AFEC_IMR_EOC11 (0x1u << 11) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 11 */
\r
316 #define AFEC_IMR_DRDY (0x1u << 24) /**< \brief (AFEC_IMR) Data Ready Interrupt Mask */
\r
317 #define AFEC_IMR_GOVRE (0x1u << 25) /**< \brief (AFEC_IMR) General Overrun Error Interrupt Mask */
\r
318 #define AFEC_IMR_COMPE (0x1u << 26) /**< \brief (AFEC_IMR) Comparison Event Interrupt Mask */
\r
319 #define AFEC_IMR_TEMPCHG (0x1u << 30) /**< \brief (AFEC_IMR) Temperature Change Interrupt Mask */
\r
320 /* -------- AFEC_ISR : (AFEC Offset: 0x30) AFEC Interrupt Status Register -------- */
\r
321 #define AFEC_ISR_EOC0 (0x1u << 0) /**< \brief (AFEC_ISR) End of Conversion 0 */
\r
322 #define AFEC_ISR_EOC1 (0x1u << 1) /**< \brief (AFEC_ISR) End of Conversion 1 */
\r
323 #define AFEC_ISR_EOC2 (0x1u << 2) /**< \brief (AFEC_ISR) End of Conversion 2 */
\r
324 #define AFEC_ISR_EOC3 (0x1u << 3) /**< \brief (AFEC_ISR) End of Conversion 3 */
\r
325 #define AFEC_ISR_EOC4 (0x1u << 4) /**< \brief (AFEC_ISR) End of Conversion 4 */
\r
326 #define AFEC_ISR_EOC5 (0x1u << 5) /**< \brief (AFEC_ISR) End of Conversion 5 */
\r
327 #define AFEC_ISR_EOC6 (0x1u << 6) /**< \brief (AFEC_ISR) End of Conversion 6 */
\r
328 #define AFEC_ISR_EOC7 (0x1u << 7) /**< \brief (AFEC_ISR) End of Conversion 7 */
\r
329 #define AFEC_ISR_EOC8 (0x1u << 8) /**< \brief (AFEC_ISR) End of Conversion 8 */
\r
330 #define AFEC_ISR_EOC9 (0x1u << 9) /**< \brief (AFEC_ISR) End of Conversion 9 */
\r
331 #define AFEC_ISR_EOC10 (0x1u << 10) /**< \brief (AFEC_ISR) End of Conversion 10 */
\r
332 #define AFEC_ISR_EOC11 (0x1u << 11) /**< \brief (AFEC_ISR) End of Conversion 11 */
\r
333 #define AFEC_ISR_DRDY (0x1u << 24) /**< \brief (AFEC_ISR) Data Ready */
\r
334 #define AFEC_ISR_GOVRE (0x1u << 25) /**< \brief (AFEC_ISR) General Overrun Error */
\r
335 #define AFEC_ISR_COMPE (0x1u << 26) /**< \brief (AFEC_ISR) Comparison Error */
\r
336 #define AFEC_ISR_TEMPCHG (0x1u << 30) /**< \brief (AFEC_ISR) Temperature Change */
\r
337 /* -------- AFEC_OVER : (AFEC Offset: 0x4C) AFEC Overrun Status Register -------- */
\r
338 #define AFEC_OVER_OVRE0 (0x1u << 0) /**< \brief (AFEC_OVER) Overrun Error 0 */
\r
339 #define AFEC_OVER_OVRE1 (0x1u << 1) /**< \brief (AFEC_OVER) Overrun Error 1 */
\r
340 #define AFEC_OVER_OVRE2 (0x1u << 2) /**< \brief (AFEC_OVER) Overrun Error 2 */
\r
341 #define AFEC_OVER_OVRE3 (0x1u << 3) /**< \brief (AFEC_OVER) Overrun Error 3 */
\r
342 #define AFEC_OVER_OVRE4 (0x1u << 4) /**< \brief (AFEC_OVER) Overrun Error 4 */
\r
343 #define AFEC_OVER_OVRE5 (0x1u << 5) /**< \brief (AFEC_OVER) Overrun Error 5 */
\r
344 #define AFEC_OVER_OVRE6 (0x1u << 6) /**< \brief (AFEC_OVER) Overrun Error 6 */
\r
345 #define AFEC_OVER_OVRE7 (0x1u << 7) /**< \brief (AFEC_OVER) Overrun Error 7 */
\r
346 #define AFEC_OVER_OVRE8 (0x1u << 8) /**< \brief (AFEC_OVER) Overrun Error 8 */
\r
347 #define AFEC_OVER_OVRE9 (0x1u << 9) /**< \brief (AFEC_OVER) Overrun Error 9 */
\r
348 #define AFEC_OVER_OVRE10 (0x1u << 10) /**< \brief (AFEC_OVER) Overrun Error 10 */
\r
349 #define AFEC_OVER_OVRE11 (0x1u << 11) /**< \brief (AFEC_OVER) Overrun Error 11 */
\r
350 /* -------- AFEC_CWR : (AFEC Offset: 0x50) AFEC Compare Window Register -------- */
\r
351 #define AFEC_CWR_LOWTHRES_Pos 0
\r
352 #define AFEC_CWR_LOWTHRES_Msk (0xffffu << AFEC_CWR_LOWTHRES_Pos) /**< \brief (AFEC_CWR) Low Threshold */
\r
353 #define AFEC_CWR_LOWTHRES(value) ((AFEC_CWR_LOWTHRES_Msk & ((value) << AFEC_CWR_LOWTHRES_Pos)))
\r
354 #define AFEC_CWR_HIGHTHRES_Pos 16
\r
355 #define AFEC_CWR_HIGHTHRES_Msk (0xffffu << AFEC_CWR_HIGHTHRES_Pos) /**< \brief (AFEC_CWR) High Threshold */
\r
356 #define AFEC_CWR_HIGHTHRES(value) ((AFEC_CWR_HIGHTHRES_Msk & ((value) << AFEC_CWR_HIGHTHRES_Pos)))
\r
357 /* -------- AFEC_CG1R : (AFEC Offset: 0x54) AFEC Channel Gain 1 Register -------- */
\r
358 #define AFEC_CG1R_GAIN0_Pos 0
\r
359 #define AFEC_CG1R_GAIN0_Msk (0x3u << AFEC_CG1R_GAIN0_Pos) /**< \brief (AFEC_CG1R) Gain for channel 0 */
\r
360 #define AFEC_CG1R_GAIN0(value) ((AFEC_CG1R_GAIN0_Msk & ((value) << AFEC_CG1R_GAIN0_Pos)))
\r
361 #define AFEC_CG1R_GAIN1_Pos 2
\r
362 #define AFEC_CG1R_GAIN1_Msk (0x3u << AFEC_CG1R_GAIN1_Pos) /**< \brief (AFEC_CG1R) Gain for channel 1 */
\r
363 #define AFEC_CG1R_GAIN1(value) ((AFEC_CG1R_GAIN1_Msk & ((value) << AFEC_CG1R_GAIN1_Pos)))
\r
364 #define AFEC_CG1R_GAIN2_Pos 4
\r
365 #define AFEC_CG1R_GAIN2_Msk (0x3u << AFEC_CG1R_GAIN2_Pos) /**< \brief (AFEC_CG1R) Gain for channel 2 */
\r
366 #define AFEC_CG1R_GAIN2(value) ((AFEC_CG1R_GAIN2_Msk & ((value) << AFEC_CG1R_GAIN2_Pos)))
\r
367 #define AFEC_CG1R_GAIN3_Pos 6
\r
368 #define AFEC_CG1R_GAIN3_Msk (0x3u << AFEC_CG1R_GAIN3_Pos) /**< \brief (AFEC_CG1R) Gain for channel 3 */
\r
369 #define AFEC_CG1R_GAIN3(value) ((AFEC_CG1R_GAIN3_Msk & ((value) << AFEC_CG1R_GAIN3_Pos)))
\r
370 #define AFEC_CG1R_GAIN4_Pos 8
\r
371 #define AFEC_CG1R_GAIN4_Msk (0x3u << AFEC_CG1R_GAIN4_Pos) /**< \brief (AFEC_CG1R) Gain for channel 4 */
\r
372 #define AFEC_CG1R_GAIN4(value) ((AFEC_CG1R_GAIN4_Msk & ((value) << AFEC_CG1R_GAIN4_Pos)))
\r
373 #define AFEC_CG1R_GAIN5_Pos 10
\r
374 #define AFEC_CG1R_GAIN5_Msk (0x3u << AFEC_CG1R_GAIN5_Pos) /**< \brief (AFEC_CG1R) Gain for channel 5 */
\r
375 #define AFEC_CG1R_GAIN5(value) ((AFEC_CG1R_GAIN5_Msk & ((value) << AFEC_CG1R_GAIN5_Pos)))
\r
376 #define AFEC_CG1R_GAIN6_Pos 12
\r
377 #define AFEC_CG1R_GAIN6_Msk (0x3u << AFEC_CG1R_GAIN6_Pos) /**< \brief (AFEC_CG1R) Gain for channel 6 */
\r
378 #define AFEC_CG1R_GAIN6(value) ((AFEC_CG1R_GAIN6_Msk & ((value) << AFEC_CG1R_GAIN6_Pos)))
\r
379 #define AFEC_CG1R_GAIN7_Pos 14
\r
380 #define AFEC_CG1R_GAIN7_Msk (0x3u << AFEC_CG1R_GAIN7_Pos) /**< \brief (AFEC_CG1R) Gain for channel 7 */
\r
381 #define AFEC_CG1R_GAIN7(value) ((AFEC_CG1R_GAIN7_Msk & ((value) << AFEC_CG1R_GAIN7_Pos)))
\r
382 #define AFEC_CG1R_GAIN8_Pos 16
\r
383 #define AFEC_CG1R_GAIN8_Msk (0x3u << AFEC_CG1R_GAIN8_Pos) /**< \brief (AFEC_CG1R) Gain for channel 8 */
\r
384 #define AFEC_CG1R_GAIN8(value) ((AFEC_CG1R_GAIN8_Msk & ((value) << AFEC_CG1R_GAIN8_Pos)))
\r
385 #define AFEC_CG1R_GAIN9_Pos 18
\r
386 #define AFEC_CG1R_GAIN9_Msk (0x3u << AFEC_CG1R_GAIN9_Pos) /**< \brief (AFEC_CG1R) Gain for channel 9 */
\r
387 #define AFEC_CG1R_GAIN9(value) ((AFEC_CG1R_GAIN9_Msk & ((value) << AFEC_CG1R_GAIN9_Pos)))
\r
388 #define AFEC_CG1R_GAIN10_Pos 20
\r
389 #define AFEC_CG1R_GAIN10_Msk (0x3u << AFEC_CG1R_GAIN10_Pos) /**< \brief (AFEC_CG1R) Gain for channel 10 */
\r
390 #define AFEC_CG1R_GAIN10(value) ((AFEC_CG1R_GAIN10_Msk & ((value) << AFEC_CG1R_GAIN10_Pos)))
\r
391 #define AFEC_CG1R_GAIN11_Pos 22
\r
392 #define AFEC_CG1R_GAIN11_Msk (0x3u << AFEC_CG1R_GAIN11_Pos) /**< \brief (AFEC_CG1R) Gain for channel 11 */
\r
393 #define AFEC_CG1R_GAIN11(value) ((AFEC_CG1R_GAIN11_Msk & ((value) << AFEC_CG1R_GAIN11_Pos)))
\r
394 /* -------- AFEC_DIFFR : (AFEC Offset: 0x60) AFEC Channel Differential Register -------- */
\r
395 #define AFEC_DIFFR_DIFF0 (0x1u << 0) /**< \brief (AFEC_DIFFR) Differential inputs for channel 0 */
\r
396 #define AFEC_DIFFR_DIFF1 (0x1u << 1) /**< \brief (AFEC_DIFFR) Differential inputs for channel 1 */
\r
397 #define AFEC_DIFFR_DIFF2 (0x1u << 2) /**< \brief (AFEC_DIFFR) Differential inputs for channel 2 */
\r
398 #define AFEC_DIFFR_DIFF3 (0x1u << 3) /**< \brief (AFEC_DIFFR) Differential inputs for channel 3 */
\r
399 #define AFEC_DIFFR_DIFF4 (0x1u << 4) /**< \brief (AFEC_DIFFR) Differential inputs for channel 4 */
\r
400 #define AFEC_DIFFR_DIFF5 (0x1u << 5) /**< \brief (AFEC_DIFFR) Differential inputs for channel 5 */
\r
401 #define AFEC_DIFFR_DIFF6 (0x1u << 6) /**< \brief (AFEC_DIFFR) Differential inputs for channel 6 */
\r
402 #define AFEC_DIFFR_DIFF7 (0x1u << 7) /**< \brief (AFEC_DIFFR) Differential inputs for channel 7 */
\r
403 #define AFEC_DIFFR_DIFF8 (0x1u << 8) /**< \brief (AFEC_DIFFR) Differential inputs for channel 8 */
\r
404 #define AFEC_DIFFR_DIFF9 (0x1u << 9) /**< \brief (AFEC_DIFFR) Differential inputs for channel 9 */
\r
405 #define AFEC_DIFFR_DIFF10 (0x1u << 10) /**< \brief (AFEC_DIFFR) Differential inputs for channel 10 */
\r
406 #define AFEC_DIFFR_DIFF11 (0x1u << 11) /**< \brief (AFEC_DIFFR) Differential inputs for channel 11 */
\r
407 /* -------- AFEC_CSELR : (AFEC Offset: 0x64) AFEC Channel Register Selection -------- */
\r
408 #define AFEC_CSELR_CSEL_Pos 0
\r
409 #define AFEC_CSELR_CSEL_Msk (0x1fu << AFEC_CSELR_CSEL_Pos) /**< \brief (AFEC_CSELR) Channel Selection */
\r
410 #define AFEC_CSELR_CSEL(value) ((AFEC_CSELR_CSEL_Msk & ((value) << AFEC_CSELR_CSEL_Pos)))
\r
411 /* -------- AFEC_CDR : (AFEC Offset: 0x68) AFEC Channel Data Register -------- */
\r
412 #define AFEC_CDR_DATA_Pos 0
\r
413 #define AFEC_CDR_DATA_Msk (0xfffu << AFEC_CDR_DATA_Pos) /**< \brief (AFEC_CDR) Converted Data */
\r
414 /* -------- AFEC_COCR : (AFEC Offset: 0x6C) AFEC Channel Offset Compensation Register -------- */
\r
415 #define AFEC_COCR_AOFF_Pos 0
\r
416 #define AFEC_COCR_AOFF_Msk (0xfffu << AFEC_COCR_AOFF_Pos) /**< \brief (AFEC_COCR) Analog Offset */
\r
417 #define AFEC_COCR_AOFF(value) ((AFEC_COCR_AOFF_Msk & ((value) << AFEC_COCR_AOFF_Pos)))
\r
418 /* -------- AFEC_TEMPMR : (AFEC Offset: 0x70) AFEC Temperature Sensor Mode Register -------- */
\r
419 #define AFEC_TEMPMR_RTCT (0x1u << 0) /**< \brief (AFEC_TEMPMR) Temperature Sensor RTC Trigger mode */
\r
420 #define AFEC_TEMPMR_TEMPCMPMOD_Pos 4
\r
421 #define AFEC_TEMPMR_TEMPCMPMOD_Msk (0x3u << AFEC_TEMPMR_TEMPCMPMOD_Pos) /**< \brief (AFEC_TEMPMR) Temperature Comparison Mode */
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422 #define AFEC_TEMPMR_TEMPCMPMOD_LOW (0x0u << 4) /**< \brief (AFEC_TEMPMR) Generates an event when the converted data is lower than the low threshold of the window. */
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423 #define AFEC_TEMPMR_TEMPCMPMOD_HIGH (0x1u << 4) /**< \brief (AFEC_TEMPMR) Generates an event when the converted data is higher than the high threshold of the window. */
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424 #define AFEC_TEMPMR_TEMPCMPMOD_IN (0x2u << 4) /**< \brief (AFEC_TEMPMR) Generates an event when the converted data is in the comparison window. */
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425 #define AFEC_TEMPMR_TEMPCMPMOD_OUT (0x3u << 4) /**< \brief (AFEC_TEMPMR) Generates an event when the converted data is out of the comparison window. */
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426 /* -------- AFEC_TEMPCWR : (AFEC Offset: 0x74) AFEC Temperature Compare Window Register -------- */
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427 #define AFEC_TEMPCWR_TLOWTHRES_Pos 0
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428 #define AFEC_TEMPCWR_TLOWTHRES_Msk (0xffffu << AFEC_TEMPCWR_TLOWTHRES_Pos) /**< \brief (AFEC_TEMPCWR) Temperature Low Threshold */
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429 #define AFEC_TEMPCWR_TLOWTHRES(value) ((AFEC_TEMPCWR_TLOWTHRES_Msk & ((value) << AFEC_TEMPCWR_TLOWTHRES_Pos)))
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430 #define AFEC_TEMPCWR_THIGHTHRES_Pos 16
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431 #define AFEC_TEMPCWR_THIGHTHRES_Msk (0xffffu << AFEC_TEMPCWR_THIGHTHRES_Pos) /**< \brief (AFEC_TEMPCWR) Temperature High Threshold */
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432 #define AFEC_TEMPCWR_THIGHTHRES(value) ((AFEC_TEMPCWR_THIGHTHRES_Msk & ((value) << AFEC_TEMPCWR_THIGHTHRES_Pos)))
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433 /* -------- AFEC_ACR : (AFEC Offset: 0x94) AFEC Analog Control Register -------- */
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434 #define AFEC_ACR_IBCTL_Pos 8
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435 #define AFEC_ACR_IBCTL_Msk (0x3u << AFEC_ACR_IBCTL_Pos) /**< \brief (AFEC_ACR) AFEC Bias Current Control */
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436 #define AFEC_ACR_IBCTL(value) ((AFEC_ACR_IBCTL_Msk & ((value) << AFEC_ACR_IBCTL_Pos)))
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437 /* -------- AFEC_SHMR : (AFEC Offset: 0xA0) AFEC Sample & Hold Mode Register -------- */
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438 #define AFEC_SHMR_DUAL0 (0x1u << 0) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 0 */
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439 #define AFEC_SHMR_DUAL1 (0x1u << 1) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 1 */
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440 #define AFEC_SHMR_DUAL2 (0x1u << 2) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 2 */
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441 #define AFEC_SHMR_DUAL3 (0x1u << 3) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 3 */
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442 #define AFEC_SHMR_DUAL4 (0x1u << 4) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 4 */
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443 #define AFEC_SHMR_DUAL5 (0x1u << 5) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 5 */
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444 #define AFEC_SHMR_DUAL6 (0x1u << 6) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 6 */
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445 #define AFEC_SHMR_DUAL7 (0x1u << 7) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 7 */
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446 #define AFEC_SHMR_DUAL8 (0x1u << 8) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 8 */
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447 #define AFEC_SHMR_DUAL9 (0x1u << 9) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 9 */
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448 #define AFEC_SHMR_DUAL10 (0x1u << 10) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 10 */
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449 #define AFEC_SHMR_DUAL11 (0x1u << 11) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 11 */
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450 /* -------- AFEC_COSR : (AFEC Offset: 0xD0) AFEC Correction Select Register -------- */
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451 #define AFEC_COSR_CSEL_Pos 0
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452 #define AFEC_COSR_CSEL_Msk (0x1fu << AFEC_COSR_CSEL_Pos) /**< \brief (AFEC_COSR) 2 Correction Select */
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453 #define AFEC_COSR_CSEL(value) ((AFEC_COSR_CSEL_Msk & ((value) << AFEC_COSR_CSEL_Pos)))
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454 /* -------- AFEC_CVR : (AFEC Offset: 0xD4) AFEC Correction Values Register -------- */
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455 #define AFEC_CVR_OFFSETCORR_Pos 0
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456 #define AFEC_CVR_OFFSETCORR_Msk (0xffffu << AFEC_CVR_OFFSETCORR_Pos) /**< \brief (AFEC_CVR) Offset Correction */
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457 #define AFEC_CVR_OFFSETCORR(value) ((AFEC_CVR_OFFSETCORR_Msk & ((value) << AFEC_CVR_OFFSETCORR_Pos)))
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458 #define AFEC_CVR_GAINCORR_Pos 16
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459 #define AFEC_CVR_GAINCORR_Msk (0xffffu << AFEC_CVR_GAINCORR_Pos) /**< \brief (AFEC_CVR) Gain Correction */
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460 #define AFEC_CVR_GAINCORR(value) ((AFEC_CVR_GAINCORR_Msk & ((value) << AFEC_CVR_GAINCORR_Pos)))
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461 /* -------- AFEC_CECR : (AFEC Offset: 0xD8) AFEC Channel Error Correction Register -------- */
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462 #define AFEC_CECR_ECORR0 (0x1u << 0) /**< \brief (AFEC_CECR) Error Correction Enable for channel 0 */
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463 #define AFEC_CECR_ECORR1 (0x1u << 1) /**< \brief (AFEC_CECR) Error Correction Enable for channel 1 */
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464 #define AFEC_CECR_ECORR2 (0x1u << 2) /**< \brief (AFEC_CECR) Error Correction Enable for channel 2 */
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465 #define AFEC_CECR_ECORR3 (0x1u << 3) /**< \brief (AFEC_CECR) Error Correction Enable for channel 3 */
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466 #define AFEC_CECR_ECORR4 (0x1u << 4) /**< \brief (AFEC_CECR) Error Correction Enable for channel 4 */
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467 #define AFEC_CECR_ECORR5 (0x1u << 5) /**< \brief (AFEC_CECR) Error Correction Enable for channel 5 */
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468 #define AFEC_CECR_ECORR6 (0x1u << 6) /**< \brief (AFEC_CECR) Error Correction Enable for channel 6 */
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469 #define AFEC_CECR_ECORR7 (0x1u << 7) /**< \brief (AFEC_CECR) Error Correction Enable for channel 7 */
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470 #define AFEC_CECR_ECORR8 (0x1u << 8) /**< \brief (AFEC_CECR) Error Correction Enable for channel 8 */
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471 #define AFEC_CECR_ECORR9 (0x1u << 9) /**< \brief (AFEC_CECR) Error Correction Enable for channel 9 */
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472 #define AFEC_CECR_ECORR10 (0x1u << 10) /**< \brief (AFEC_CECR) Error Correction Enable for channel 10 */
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473 #define AFEC_CECR_ECORR11 (0x1u << 11) /**< \brief (AFEC_CECR) Error Correction Enable for channel 11 */
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474 /* -------- AFEC_WPMR : (AFEC Offset: 0xE4) AFEC Write Protection Mode Register -------- */
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475 #define AFEC_WPMR_WPEN (0x1u << 0) /**< \brief (AFEC_WPMR) Write Protection Enable */
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476 #define AFEC_WPMR_WPKEY_Pos 8
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477 #define AFEC_WPMR_WPKEY_Msk (0xffffffu << AFEC_WPMR_WPKEY_Pos) /**< \brief (AFEC_WPMR) Write Protect KEY */
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478 #define AFEC_WPMR_WPKEY_PASSWD (0x414443u << 8) /**< \brief (AFEC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. */
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479 /* -------- AFEC_WPSR : (AFEC Offset: 0xE8) AFEC Write Protection Status Register -------- */
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480 #define AFEC_WPSR_WPVS (0x1u << 0) /**< \brief (AFEC_WPSR) Write Protect Violation Status */
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481 #define AFEC_WPSR_WPVSRC_Pos 8
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482 #define AFEC_WPSR_WPVSRC_Msk (0xffffu << AFEC_WPSR_WPVSRC_Pos) /**< \brief (AFEC_WPSR) Write Protect Violation Source */
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483 /* -------- AFEC_VERSION : (AFEC Offset: 0xFC) AFEC Version Register -------- */
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484 #define AFEC_VERSION_VERSION_Pos 0
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485 #define AFEC_VERSION_VERSION_Msk (0xfffu << AFEC_VERSION_VERSION_Pos) /**< \brief (AFEC_VERSION) Version of the Hardware Module */
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486 #define AFEC_VERSION_MFN_Pos 16
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487 #define AFEC_VERSION_MFN_Msk (0x7u << AFEC_VERSION_MFN_Pos) /**< \brief (AFEC_VERSION) Metal Fix Number */
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492 #endif /* _SAM_AFEC_COMPONENT_ */
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projects / freertos / blob