1 /* ---------------------------------------------------------------------------- */
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2 /* Atmel Microcontroller Software Support */
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3 /* SAM Software Package License */
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4 /* ---------------------------------------------------------------------------- */
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5 /* Copyright (c) 2014, Atmel Corporation */
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7 /* All rights reserved. */
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9 /* Redistribution and use in source and binary forms, with or without */
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10 /* modification, are permitted provided that the following condition is met: */
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12 /* - Redistributions of source code must retain the above copyright notice, */
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13 /* this list of conditions and the disclaimer below. */
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15 /* Atmel's name may not be used to endorse or promote products derived from */
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16 /* this software without specific prior written permission. */
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18 /* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
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19 /* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
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20 /* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
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21 /* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
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22 /* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
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23 /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
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24 /* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
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25 /* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
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26 /* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
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27 /* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
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28 /* ---------------------------------------------------------------------------- */
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30 #ifndef _SAM_MATRIX_COMPONENT_
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31 #define _SAM_MATRIX_COMPONENT_
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33 /* ============================================================================= */
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34 /** SOFTWARE API DEFINITION FOR AHB Bus Matrix */
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35 /* ============================================================================= */
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36 /** \addtogroup SAM_MATRIX AHB Bus Matrix */
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39 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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40 /** \brief MatrixPr hardware registers */
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42 __IO uint32_t MATRIX_PRAS; /**< \brief (MatrixPr Offset: 0x0) Priority Register A for Slave 0 */
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43 __IO uint32_t MATRIX_PRBS; /**< \brief (MatrixPr Offset: 0x4) Priority Register B for Slave 0 */
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45 /** \brief Matrix hardware registers */
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46 #define MATRIXPR_NUMBER 16
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48 __IO uint32_t MATRIX_MCFG[16]; /**< \brief (Matrix Offset: 0x0000) Master Configuration Register */
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49 __IO uint32_t MATRIX_SCFG[16]; /**< \brief (Matrix Offset: 0x0040) Slave Configuration Register */
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50 MatrixPr MATRIX_PR[MATRIXPR_NUMBER]; /**< \brief (Matrix Offset: 0x0080) 0 .. 15 */
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51 __IO uint32_t MATRIX_MRCR; /**< \brief (Matrix Offset: 0x0100) Master Remap Control Register */
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52 __I uint32_t Reserved1[3];
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53 __IO uint32_t MATRIX_SFR[16]; /**< \brief (Matrix Offset: 0x0110) Special Function Register */
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54 __O uint32_t MATRIX_MEIER; /**< \brief (Matrix Offset: 0x0150) Master Error Interrupt Enable Register */
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55 __O uint32_t MATRIX_MEIDR; /**< \brief (Matrix Offset: 0x0154) Master Error Interrupt Disable Register */
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56 __I uint32_t MATRIX_MEIMR; /**< \brief (Matrix Offset: 0x0158) Master Error Interrupt Mask Register */
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57 __I uint32_t MATRIX_MESR; /**< \brief (Matrix Offset: 0x015C) Master Error Status Register */
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58 __I uint32_t MATRIX_MEAR[16]; /**< \brief (Matrix Offset: 0x0160) Master 0 Error Address Register */
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59 __I uint32_t Reserved2[17];
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60 __IO uint32_t MATRIX_WPMR; /**< \brief (Matrix Offset: 0x01E4) Write Protect Mode Register */
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61 __I uint32_t MATRIX_WPSR; /**< \brief (Matrix Offset: 0x01E8) Write Protect Status Register */
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62 __I uint32_t Reserved3[4];
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63 __I uint32_t MATRIX_VERSION; /**< \brief (Matrix Offset: 0x01FC) Version Register */
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64 __IO uint32_t MATRIX_SSR[16]; /**< \brief (Matrix Offset: 0x0200) Security Slave 0 Register */
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65 __IO uint32_t MATRIX_SASSR[16]; /**< \brief (Matrix Offset: 0x0240) Security Areas Split Slave 0 Register */
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66 __IO uint32_t MATRIX_SRTSR[16]; /**< \brief (Matrix Offset: 0x0280) Security Region Top Slave 0 Register */
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67 __IO uint32_t MATRIX_SPSELR[3]; /**< \brief (Matrix Offset: 0x02C0) Security Peripheral Select 1 Register */
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69 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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70 /* -------- MATRIX_MCFG[16] : (MATRIX Offset: 0x0000) Master Configuration Register -------- */
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71 #define MATRIX_MCFG_ULBT_Pos 0
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72 #define MATRIX_MCFG_ULBT_Msk (0x7u << MATRIX_MCFG_ULBT_Pos) /**< \brief (MATRIX_MCFG[16]) Undefined Length Burst Type */
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73 #define MATRIX_MCFG_ULBT(value) ((MATRIX_MCFG_ULBT_Msk & ((value) << MATRIX_MCFG_ULBT_Pos)))
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74 /* -------- MATRIX_SCFG[16] : (MATRIX Offset: 0x0040) Slave Configuration Register -------- */
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75 #define MATRIX_SCFG_SLOT_CYCLE_Pos 0
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76 #define MATRIX_SCFG_SLOT_CYCLE_Msk (0x1ffu << MATRIX_SCFG_SLOT_CYCLE_Pos) /**< \brief (MATRIX_SCFG[16]) Maximum Bus Grant Duration for Masters */
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77 #define MATRIX_SCFG_SLOT_CYCLE(value) ((MATRIX_SCFG_SLOT_CYCLE_Msk & ((value) << MATRIX_SCFG_SLOT_CYCLE_Pos)))
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78 #define MATRIX_SCFG_DEFMSTR_TYPE_Pos 16
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79 #define MATRIX_SCFG_DEFMSTR_TYPE_Msk (0x3u << MATRIX_SCFG_DEFMSTR_TYPE_Pos) /**< \brief (MATRIX_SCFG[16]) Default Master Type */
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80 #define MATRIX_SCFG_DEFMSTR_TYPE(value) ((MATRIX_SCFG_DEFMSTR_TYPE_Msk & ((value) << MATRIX_SCFG_DEFMSTR_TYPE_Pos)))
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81 #define MATRIX_SCFG_FIXED_DEFMSTR_Pos 18
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82 #define MATRIX_SCFG_FIXED_DEFMSTR_Msk (0xfu << MATRIX_SCFG_FIXED_DEFMSTR_Pos) /**< \brief (MATRIX_SCFG[16]) Fixed Default Master */
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83 #define MATRIX_SCFG_FIXED_DEFMSTR(value) ((MATRIX_SCFG_FIXED_DEFMSTR_Msk & ((value) << MATRIX_SCFG_FIXED_DEFMSTR_Pos)))
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84 /* -------- MATRIX_PRAS : (MATRIX Offset: N/A) Priority Register A for Slave 0 -------- */
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85 #define MATRIX_PRAS_M0PR_Pos 0
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86 #define MATRIX_PRAS_M0PR_Msk (0x3u << MATRIX_PRAS_M0PR_Pos) /**< \brief (MATRIX_PRAS) Master 0 Priority */
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87 #define MATRIX_PRAS_M0PR(value) ((MATRIX_PRAS_M0PR_Msk & ((value) << MATRIX_PRAS_M0PR_Pos)))
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88 #define MATRIX_PRAS_M1PR_Pos 4
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89 #define MATRIX_PRAS_M1PR_Msk (0x3u << MATRIX_PRAS_M1PR_Pos) /**< \brief (MATRIX_PRAS) Master 1 Priority */
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90 #define MATRIX_PRAS_M1PR(value) ((MATRIX_PRAS_M1PR_Msk & ((value) << MATRIX_PRAS_M1PR_Pos)))
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91 #define MATRIX_PRAS_M2PR_Pos 8
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92 #define MATRIX_PRAS_M2PR_Msk (0x3u << MATRIX_PRAS_M2PR_Pos) /**< \brief (MATRIX_PRAS) Master 2 Priority */
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93 #define MATRIX_PRAS_M2PR(value) ((MATRIX_PRAS_M2PR_Msk & ((value) << MATRIX_PRAS_M2PR_Pos)))
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94 #define MATRIX_PRAS_M3PR_Pos 12
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95 #define MATRIX_PRAS_M3PR_Msk (0x3u << MATRIX_PRAS_M3PR_Pos) /**< \brief (MATRIX_PRAS) Master 3 Priority */
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96 #define MATRIX_PRAS_M3PR(value) ((MATRIX_PRAS_M3PR_Msk & ((value) << MATRIX_PRAS_M3PR_Pos)))
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97 #define MATRIX_PRAS_M4PR_Pos 16
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98 #define MATRIX_PRAS_M4PR_Msk (0x3u << MATRIX_PRAS_M4PR_Pos) /**< \brief (MATRIX_PRAS) Master 4 Priority */
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99 #define MATRIX_PRAS_M4PR(value) ((MATRIX_PRAS_M4PR_Msk & ((value) << MATRIX_PRAS_M4PR_Pos)))
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100 #define MATRIX_PRAS_M5PR_Pos 20
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101 #define MATRIX_PRAS_M5PR_Msk (0x3u << MATRIX_PRAS_M5PR_Pos) /**< \brief (MATRIX_PRAS) Master 5 Priority */
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102 #define MATRIX_PRAS_M5PR(value) ((MATRIX_PRAS_M5PR_Msk & ((value) << MATRIX_PRAS_M5PR_Pos)))
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103 #define MATRIX_PRAS_M6PR_Pos 24
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104 #define MATRIX_PRAS_M6PR_Msk (0x3u << MATRIX_PRAS_M6PR_Pos) /**< \brief (MATRIX_PRAS) Master 6 Priority */
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105 #define MATRIX_PRAS_M6PR(value) ((MATRIX_PRAS_M6PR_Msk & ((value) << MATRIX_PRAS_M6PR_Pos)))
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106 #define MATRIX_PRAS_M7PR_Pos 28
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107 #define MATRIX_PRAS_M7PR_Msk (0x3u << MATRIX_PRAS_M7PR_Pos) /**< \brief (MATRIX_PRAS) Master 7 Priority */
\r
108 #define MATRIX_PRAS_M7PR(value) ((MATRIX_PRAS_M7PR_Msk & ((value) << MATRIX_PRAS_M7PR_Pos)))
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109 /* -------- MATRIX_PRBS : (MATRIX Offset: N/A) Priority Register B for Slave 0 -------- */
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110 #define MATRIX_PRBS_M8PR_Pos 0
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111 #define MATRIX_PRBS_M8PR_Msk (0x3u << MATRIX_PRBS_M8PR_Pos) /**< \brief (MATRIX_PRBS) Master 8 Priority */
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112 #define MATRIX_PRBS_M8PR(value) ((MATRIX_PRBS_M8PR_Msk & ((value) << MATRIX_PRBS_M8PR_Pos)))
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113 #define MATRIX_PRBS_M9PR_Pos 4
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114 #define MATRIX_PRBS_M9PR_Msk (0x3u << MATRIX_PRBS_M9PR_Pos) /**< \brief (MATRIX_PRBS) Master 9 Priority */
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115 #define MATRIX_PRBS_M9PR(value) ((MATRIX_PRBS_M9PR_Msk & ((value) << MATRIX_PRBS_M9PR_Pos)))
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116 #define MATRIX_PRBS_M10PR_Pos 8
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117 #define MATRIX_PRBS_M10PR_Msk (0x3u << MATRIX_PRBS_M10PR_Pos) /**< \brief (MATRIX_PRBS) Master 10 Priority */
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118 #define MATRIX_PRBS_M10PR(value) ((MATRIX_PRBS_M10PR_Msk & ((value) << MATRIX_PRBS_M10PR_Pos)))
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119 #define MATRIX_PRBS_M11PR_Pos 12
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120 #define MATRIX_PRBS_M11PR_Msk (0x3u << MATRIX_PRBS_M11PR_Pos) /**< \brief (MATRIX_PRBS) Master 11 Priority */
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121 #define MATRIX_PRBS_M11PR(value) ((MATRIX_PRBS_M11PR_Msk & ((value) << MATRIX_PRBS_M11PR_Pos)))
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122 #define MATRIX_PRBS_M12PR_Pos 16
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123 #define MATRIX_PRBS_M12PR_Msk (0x3u << MATRIX_PRBS_M12PR_Pos) /**< \brief (MATRIX_PRBS) Master 12 Priority */
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124 #define MATRIX_PRBS_M12PR(value) ((MATRIX_PRBS_M12PR_Msk & ((value) << MATRIX_PRBS_M12PR_Pos)))
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125 #define MATRIX_PRBS_M13PR_Pos 20
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126 #define MATRIX_PRBS_M13PR_Msk (0x3u << MATRIX_PRBS_M13PR_Pos) /**< \brief (MATRIX_PRBS) Master 13 Priority */
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127 #define MATRIX_PRBS_M13PR(value) ((MATRIX_PRBS_M13PR_Msk & ((value) << MATRIX_PRBS_M13PR_Pos)))
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128 #define MATRIX_PRBS_M14PR_Pos 24
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129 #define MATRIX_PRBS_M14PR_Msk (0x3u << MATRIX_PRBS_M14PR_Pos) /**< \brief (MATRIX_PRBS) Master 14 Priority */
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130 #define MATRIX_PRBS_M14PR(value) ((MATRIX_PRBS_M14PR_Msk & ((value) << MATRIX_PRBS_M14PR_Pos)))
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131 #define MATRIX_PRBS_M15PR_Pos 28
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132 #define MATRIX_PRBS_M15PR_Msk (0x3u << MATRIX_PRBS_M15PR_Pos) /**< \brief (MATRIX_PRBS) Master 15 Priority */
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133 #define MATRIX_PRBS_M15PR(value) ((MATRIX_PRBS_M15PR_Msk & ((value) << MATRIX_PRBS_M15PR_Pos)))
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134 /* -------- MATRIX_MRCR : (MATRIX Offset: 0x0100) Master Remap Control Register -------- */
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135 #define MATRIX_MRCR_RCB0 (0x1u << 0) /**< \brief (MATRIX_MRCR) */
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136 #define MATRIX_MRCR_RCB1 (0x1u << 1) /**< \brief (MATRIX_MRCR) */
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137 #define MATRIX_MRCR_RCB2 (0x1u << 2) /**< \brief (MATRIX_MRCR) */
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138 #define MATRIX_MRCR_RCB3 (0x1u << 3) /**< \brief (MATRIX_MRCR) */
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139 #define MATRIX_MRCR_RCB4 (0x1u << 4) /**< \brief (MATRIX_MRCR) */
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140 #define MATRIX_MRCR_RCB5 (0x1u << 5) /**< \brief (MATRIX_MRCR) */
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141 #define MATRIX_MRCR_RCB6 (0x1u << 6) /**< \brief (MATRIX_MRCR) */
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142 #define MATRIX_MRCR_RCB7 (0x1u << 7) /**< \brief (MATRIX_MRCR) */
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143 #define MATRIX_MRCR_RCB8 (0x1u << 8) /**< \brief (MATRIX_MRCR) */
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144 #define MATRIX_MRCR_RCB9 (0x1u << 9) /**< \brief (MATRIX_MRCR) */
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145 #define MATRIX_MRCR_RCB10 (0x1u << 10) /**< \brief (MATRIX_MRCR) */
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146 #define MATRIX_MRCR_RCB11 (0x1u << 11) /**< \brief (MATRIX_MRCR) */
\r
147 #define MATRIX_MRCR_RCB12 (0x1u << 12) /**< \brief (MATRIX_MRCR) */
\r
148 #define MATRIX_MRCR_RCB13 (0x1u << 13) /**< \brief (MATRIX_MRCR) */
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149 #define MATRIX_MRCR_RCB14 (0x1u << 14) /**< \brief (MATRIX_MRCR) */
\r
150 #define MATRIX_MRCR_RCB15 (0x1u << 15) /**< \brief (MATRIX_MRCR) */
\r
151 /* -------- MATRIX_SFR[16] : (MATRIX Offset: 0x0110) Special Function Register -------- */
\r
152 #define MATRIX_SFR_SFR_Pos 0
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153 #define MATRIX_SFR_SFR_Msk (0xffffffffu << MATRIX_SFR_SFR_Pos) /**< \brief (MATRIX_SFR[16]) Special Function Register Fields */
\r
154 #define MATRIX_SFR_SFR(value) ((MATRIX_SFR_SFR_Msk & ((value) << MATRIX_SFR_SFR_Pos)))
\r
155 /* -------- MATRIX_MEIER : (MATRIX Offset: 0x0150) Master Error Interrupt Enable Register -------- */
\r
156 #define MATRIX_MEIER_MERR0 (0x1u << 0) /**< \brief (MATRIX_MEIER) Master 0 Access Error */
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157 #define MATRIX_MEIER_MERR1 (0x1u << 1) /**< \brief (MATRIX_MEIER) Master 1 Access Error */
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158 #define MATRIX_MEIER_MERR2 (0x1u << 2) /**< \brief (MATRIX_MEIER) Master 2 Access Error */
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159 #define MATRIX_MEIER_MERR3 (0x1u << 3) /**< \brief (MATRIX_MEIER) Master 3 Access Error */
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160 #define MATRIX_MEIER_MERR4 (0x1u << 4) /**< \brief (MATRIX_MEIER) Master 4 Access Error */
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161 #define MATRIX_MEIER_MERR5 (0x1u << 5) /**< \brief (MATRIX_MEIER) Master 5 Access Error */
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162 #define MATRIX_MEIER_MERR6 (0x1u << 6) /**< \brief (MATRIX_MEIER) Master 6 Access Error */
\r
163 #define MATRIX_MEIER_MERR7 (0x1u << 7) /**< \brief (MATRIX_MEIER) Master 7 Access Error */
\r
164 #define MATRIX_MEIER_MERR8 (0x1u << 8) /**< \brief (MATRIX_MEIER) Master 8 Access Error */
\r
165 #define MATRIX_MEIER_MERR9 (0x1u << 9) /**< \brief (MATRIX_MEIER) Master 9 Access Error */
\r
166 #define MATRIX_MEIER_MERR10 (0x1u << 10) /**< \brief (MATRIX_MEIER) Master 10 Access Error */
\r
167 #define MATRIX_MEIER_MERR11 (0x1u << 11) /**< \brief (MATRIX_MEIER) Master 11 Access Error */
\r
168 #define MATRIX_MEIER_MERR12 (0x1u << 12) /**< \brief (MATRIX_MEIER) Master 12 Access Error */
\r
169 #define MATRIX_MEIER_MERR13 (0x1u << 13) /**< \brief (MATRIX_MEIER) Master 13 Access Error */
\r
170 #define MATRIX_MEIER_MERR14 (0x1u << 14) /**< \brief (MATRIX_MEIER) Master 14 Access Error */
\r
171 #define MATRIX_MEIER_MERR15 (0x1u << 15) /**< \brief (MATRIX_MEIER) Master 15 Access Error */
\r
172 /* -------- MATRIX_MEIDR : (MATRIX Offset: 0x0154) Master Error Interrupt Disable Register -------- */
\r
173 #define MATRIX_MEIDR_MERR0 (0x1u << 0) /**< \brief (MATRIX_MEIDR) Master 0 Access Error */
\r
174 #define MATRIX_MEIDR_MERR1 (0x1u << 1) /**< \brief (MATRIX_MEIDR) Master 1 Access Error */
\r
175 #define MATRIX_MEIDR_MERR2 (0x1u << 2) /**< \brief (MATRIX_MEIDR) Master 2 Access Error */
\r
176 #define MATRIX_MEIDR_MERR3 (0x1u << 3) /**< \brief (MATRIX_MEIDR) Master 3 Access Error */
\r
177 #define MATRIX_MEIDR_MERR4 (0x1u << 4) /**< \brief (MATRIX_MEIDR) Master 4 Access Error */
\r
178 #define MATRIX_MEIDR_MERR5 (0x1u << 5) /**< \brief (MATRIX_MEIDR) Master 5 Access Error */
\r
179 #define MATRIX_MEIDR_MERR6 (0x1u << 6) /**< \brief (MATRIX_MEIDR) Master 6 Access Error */
\r
180 #define MATRIX_MEIDR_MERR7 (0x1u << 7) /**< \brief (MATRIX_MEIDR) Master 7 Access Error */
\r
181 #define MATRIX_MEIDR_MERR8 (0x1u << 8) /**< \brief (MATRIX_MEIDR) Master 8 Access Error */
\r
182 #define MATRIX_MEIDR_MERR9 (0x1u << 9) /**< \brief (MATRIX_MEIDR) Master 9 Access Error */
\r
183 #define MATRIX_MEIDR_MERR10 (0x1u << 10) /**< \brief (MATRIX_MEIDR) Master 10 Access Error */
\r
184 #define MATRIX_MEIDR_MERR11 (0x1u << 11) /**< \brief (MATRIX_MEIDR) Master 11 Access Error */
\r
185 #define MATRIX_MEIDR_MERR12 (0x1u << 12) /**< \brief (MATRIX_MEIDR) Master 12 Access Error */
\r
186 #define MATRIX_MEIDR_MERR13 (0x1u << 13) /**< \brief (MATRIX_MEIDR) Master 13 Access Error */
\r
187 #define MATRIX_MEIDR_MERR14 (0x1u << 14) /**< \brief (MATRIX_MEIDR) Master 14 Access Error */
\r
188 #define MATRIX_MEIDR_MERR15 (0x1u << 15) /**< \brief (MATRIX_MEIDR) Master 15 Access Error */
\r
189 /* -------- MATRIX_MEIMR : (MATRIX Offset: 0x0158) Master Error Interrupt Mask Register -------- */
\r
190 #define MATRIX_MEIMR_MERR0 (0x1u << 0) /**< \brief (MATRIX_MEIMR) Master 0 Access Error */
\r
191 #define MATRIX_MEIMR_MERR1 (0x1u << 1) /**< \brief (MATRIX_MEIMR) Master 1 Access Error */
\r
192 #define MATRIX_MEIMR_MERR2 (0x1u << 2) /**< \brief (MATRIX_MEIMR) Master 2 Access Error */
\r
193 #define MATRIX_MEIMR_MERR3 (0x1u << 3) /**< \brief (MATRIX_MEIMR) Master 3 Access Error */
\r
194 #define MATRIX_MEIMR_MERR4 (0x1u << 4) /**< \brief (MATRIX_MEIMR) Master 4 Access Error */
\r
195 #define MATRIX_MEIMR_MERR5 (0x1u << 5) /**< \brief (MATRIX_MEIMR) Master 5 Access Error */
\r
196 #define MATRIX_MEIMR_MERR6 (0x1u << 6) /**< \brief (MATRIX_MEIMR) Master 6 Access Error */
\r
197 #define MATRIX_MEIMR_MERR7 (0x1u << 7) /**< \brief (MATRIX_MEIMR) Master 7 Access Error */
\r
198 #define MATRIX_MEIMR_MERR8 (0x1u << 8) /**< \brief (MATRIX_MEIMR) Master 8 Access Error */
\r
199 #define MATRIX_MEIMR_MERR9 (0x1u << 9) /**< \brief (MATRIX_MEIMR) Master 9 Access Error */
\r
200 #define MATRIX_MEIMR_MERR10 (0x1u << 10) /**< \brief (MATRIX_MEIMR) Master 10 Access Error */
\r
201 #define MATRIX_MEIMR_MERR11 (0x1u << 11) /**< \brief (MATRIX_MEIMR) Master 11 Access Error */
\r
202 #define MATRIX_MEIMR_MERR12 (0x1u << 12) /**< \brief (MATRIX_MEIMR) Master 12 Access Error */
\r
203 #define MATRIX_MEIMR_MERR13 (0x1u << 13) /**< \brief (MATRIX_MEIMR) Master 13 Access Error */
\r
204 #define MATRIX_MEIMR_MERR14 (0x1u << 14) /**< \brief (MATRIX_MEIMR) Master 14 Access Error */
\r
205 #define MATRIX_MEIMR_MERR15 (0x1u << 15) /**< \brief (MATRIX_MEIMR) Master 15 Access Error */
\r
206 /* -------- MATRIX_MESR : (MATRIX Offset: 0x015C) Master Error Status Register -------- */
\r
207 #define MATRIX_MESR_MERR0 (0x1u << 0) /**< \brief (MATRIX_MESR) Master 0 Access Error */
\r
208 #define MATRIX_MESR_MERR1 (0x1u << 1) /**< \brief (MATRIX_MESR) Master 1 Access Error */
\r
209 #define MATRIX_MESR_MERR2 (0x1u << 2) /**< \brief (MATRIX_MESR) Master 2 Access Error */
\r
210 #define MATRIX_MESR_MERR3 (0x1u << 3) /**< \brief (MATRIX_MESR) Master 3 Access Error */
\r
211 #define MATRIX_MESR_MERR4 (0x1u << 4) /**< \brief (MATRIX_MESR) Master 4 Access Error */
\r
212 #define MATRIX_MESR_MERR5 (0x1u << 5) /**< \brief (MATRIX_MESR) Master 5 Access Error */
\r
213 #define MATRIX_MESR_MERR6 (0x1u << 6) /**< \brief (MATRIX_MESR) Master 6 Access Error */
\r
214 #define MATRIX_MESR_MERR7 (0x1u << 7) /**< \brief (MATRIX_MESR) Master 7 Access Error */
\r
215 #define MATRIX_MESR_MERR8 (0x1u << 8) /**< \brief (MATRIX_MESR) Master 8 Access Error */
\r
216 #define MATRIX_MESR_MERR9 (0x1u << 9) /**< \brief (MATRIX_MESR) Master 9 Access Error */
\r
217 #define MATRIX_MESR_MERR10 (0x1u << 10) /**< \brief (MATRIX_MESR) Master 10 Access Error */
\r
218 #define MATRIX_MESR_MERR11 (0x1u << 11) /**< \brief (MATRIX_MESR) Master 11 Access Error */
\r
219 #define MATRIX_MESR_MERR12 (0x1u << 12) /**< \brief (MATRIX_MESR) Master 12 Access Error */
\r
220 #define MATRIX_MESR_MERR13 (0x1u << 13) /**< \brief (MATRIX_MESR) Master 13 Access Error */
\r
221 #define MATRIX_MESR_MERR14 (0x1u << 14) /**< \brief (MATRIX_MESR) Master 14 Access Error */
\r
222 #define MATRIX_MESR_MERR15 (0x1u << 15) /**< \brief (MATRIX_MESR) Master 15 Access Error */
\r
223 /* -------- MATRIX_MEAR[16] : (MATRIX Offset: 0x0160) Master 0 Error Address Register -------- */
\r
224 #define MATRIX_MEAR_ERRADD_Pos 0
\r
225 #define MATRIX_MEAR_ERRADD_Msk (0xffffffffu << MATRIX_MEAR_ERRADD_Pos) /**< \brief (MATRIX_MEAR[16]) Master Error Address */
\r
226 /* -------- MATRIX_WPMR : (MATRIX Offset: 0x01E4) Write Protect Mode Register -------- */
\r
227 #define MATRIX_WPMR_WPEN (0x1u << 0) /**< \brief (MATRIX_WPMR) Write Protect Enable */
\r
228 #define MATRIX_WPMR_WPKEY_Pos 8
\r
229 #define MATRIX_WPMR_WPKEY_Msk (0xffffffu << MATRIX_WPMR_WPKEY_Pos) /**< \brief (MATRIX_WPMR) Write Protect KEY (Write-only) */
\r
230 #define MATRIX_WPMR_WPKEY(value) ((MATRIX_WPMR_WPKEY_Msk & ((value) << MATRIX_WPMR_WPKEY_Pos)))
\r
231 /* -------- MATRIX_WPSR : (MATRIX Offset: 0x01E8) Write Protect Status Register -------- */
\r
232 #define MATRIX_WPSR_WPVS (0x1u << 0) /**< \brief (MATRIX_WPSR) Write Protect Violation Status */
\r
233 #define MATRIX_WPSR_WPVSRC_Pos 8
\r
234 #define MATRIX_WPSR_WPVSRC_Msk (0xffffu << MATRIX_WPSR_WPVSRC_Pos) /**< \brief (MATRIX_WPSR) Write Protect Violation Source */
\r
235 /* -------- MATRIX_VERSION : (MATRIX Offset: 0x01FC) Version Register -------- */
\r
236 #define MATRIX_VERSION_VERSION_Pos 0
\r
237 #define MATRIX_VERSION_VERSION_Msk (0xfffu << MATRIX_VERSION_VERSION_Pos) /**< \brief (MATRIX_VERSION) */
\r
238 #define MATRIX_VERSION_MFN_Pos 16
\r
239 #define MATRIX_VERSION_MFN_Msk (0x7u << MATRIX_VERSION_MFN_Pos) /**< \brief (MATRIX_VERSION) */
\r
240 /* -------- MATRIX_SSR[16] : (MATRIX Offset: 0x0200) Security Slave 0 Register -------- */
\r
241 #define MATRIX_SSR_LANSECH0 (0x1u << 0) /**< \brief (MATRIX_SSR[16]) Low Area Not Secured in HSELx Security Region */
\r
242 #define MATRIX_SSR_LANSECH1 (0x1u << 1) /**< \brief (MATRIX_SSR[16]) Low Area Not Secured in HSELx Security Region */
\r
243 #define MATRIX_SSR_LANSECH2 (0x1u << 2) /**< \brief (MATRIX_SSR[16]) Low Area Not Secured in HSELx Security Region */
\r
244 #define MATRIX_SSR_LANSECH3 (0x1u << 3) /**< \brief (MATRIX_SSR[16]) Low Area Not Secured in HSELx Security Region */
\r
245 #define MATRIX_SSR_LANSECH4 (0x1u << 4) /**< \brief (MATRIX_SSR[16]) Low Area Not Secured in HSELx Security Region */
\r
246 #define MATRIX_SSR_LANSECH5 (0x1u << 5) /**< \brief (MATRIX_SSR[16]) Low Area Not Secured in HSELx Security Region */
\r
247 #define MATRIX_SSR_LANSECH6 (0x1u << 6) /**< \brief (MATRIX_SSR[16]) Low Area Not Secured in HSELx Security Region */
\r
248 #define MATRIX_SSR_LANSECH7 (0x1u << 7) /**< \brief (MATRIX_SSR[16]) Low Area Not Secured in HSELx Security Region */
\r
249 #define MATRIX_SSR_RDNSECH0 (0x1u << 8) /**< \brief (MATRIX_SSR[16]) Read Not Secured for HSELx Security Region */
\r
250 #define MATRIX_SSR_RDNSECH1 (0x1u << 9) /**< \brief (MATRIX_SSR[16]) Read Not Secured for HSELx Security Region */
\r
251 #define MATRIX_SSR_RDNSECH2 (0x1u << 10) /**< \brief (MATRIX_SSR[16]) Read Not Secured for HSELx Security Region */
\r
252 #define MATRIX_SSR_RDNSECH3 (0x1u << 11) /**< \brief (MATRIX_SSR[16]) Read Not Secured for HSELx Security Region */
\r
253 #define MATRIX_SSR_RDNSECH4 (0x1u << 12) /**< \brief (MATRIX_SSR[16]) Read Not Secured for HSELx Security Region */
\r
254 #define MATRIX_SSR_RDNSECH5 (0x1u << 13) /**< \brief (MATRIX_SSR[16]) Read Not Secured for HSELx Security Region */
\r
255 #define MATRIX_SSR_RDNSECH6 (0x1u << 14) /**< \brief (MATRIX_SSR[16]) Read Not Secured for HSELx Security Region */
\r
256 #define MATRIX_SSR_RDNSECH7 (0x1u << 15) /**< \brief (MATRIX_SSR[16]) Read Not Secured for HSELx Security Region */
\r
257 #define MATRIX_SSR_WRNSECH0 (0x1u << 16) /**< \brief (MATRIX_SSR[16]) Write Not Secured for HSELx Security Region */
\r
258 #define MATRIX_SSR_WRNSECH1 (0x1u << 17) /**< \brief (MATRIX_SSR[16]) Write Not Secured for HSELx Security Region */
\r
259 #define MATRIX_SSR_WRNSECH2 (0x1u << 18) /**< \brief (MATRIX_SSR[16]) Write Not Secured for HSELx Security Region */
\r
260 #define MATRIX_SSR_WRNSECH3 (0x1u << 19) /**< \brief (MATRIX_SSR[16]) Write Not Secured for HSELx Security Region */
\r
261 #define MATRIX_SSR_WRNSECH4 (0x1u << 20) /**< \brief (MATRIX_SSR[16]) Write Not Secured for HSELx Security Region */
\r
262 #define MATRIX_SSR_WRNSECH5 (0x1u << 21) /**< \brief (MATRIX_SSR[16]) Write Not Secured for HSELx Security Region */
\r
263 #define MATRIX_SSR_WRNSECH6 (0x1u << 22) /**< \brief (MATRIX_SSR[16]) Write Not Secured for HSELx Security Region */
\r
264 #define MATRIX_SSR_WRNSECH7 (0x1u << 23) /**< \brief (MATRIX_SSR[16]) Write Not Secured for HSELx Security Region */
\r
265 /* -------- MATRIX_SASSR[16] : (MATRIX Offset: 0x0240) Security Areas Split Slave 0 Register -------- */
\r
266 #define MATRIX_SASSR_SASPLIT0_Pos 0
\r
267 #define MATRIX_SASSR_SASPLIT0_Msk (0xfu << MATRIX_SASSR_SASPLIT0_Pos) /**< \brief (MATRIX_SASSR[16]) Security Areas Split for HSELx Security Region */
\r
268 #define MATRIX_SASSR_SASPLIT0(value) ((MATRIX_SASSR_SASPLIT0_Msk & ((value) << MATRIX_SASSR_SASPLIT0_Pos)))
\r
269 #define MATRIX_SASSR_SASPLIT1_Pos 4
\r
270 #define MATRIX_SASSR_SASPLIT1_Msk (0xfu << MATRIX_SASSR_SASPLIT1_Pos) /**< \brief (MATRIX_SASSR[16]) Security Areas Split for HSELx Security Region */
\r
271 #define MATRIX_SASSR_SASPLIT1(value) ((MATRIX_SASSR_SASPLIT1_Msk & ((value) << MATRIX_SASSR_SASPLIT1_Pos)))
\r
272 #define MATRIX_SASSR_SASPLIT2_Pos 8
\r
273 #define MATRIX_SASSR_SASPLIT2_Msk (0xfu << MATRIX_SASSR_SASPLIT2_Pos) /**< \brief (MATRIX_SASSR[16]) Security Areas Split for HSELx Security Region */
\r
274 #define MATRIX_SASSR_SASPLIT2(value) ((MATRIX_SASSR_SASPLIT2_Msk & ((value) << MATRIX_SASSR_SASPLIT2_Pos)))
\r
275 #define MATRIX_SASSR_SASPLIT3_Pos 12
\r
276 #define MATRIX_SASSR_SASPLIT3_Msk (0xfu << MATRIX_SASSR_SASPLIT3_Pos) /**< \brief (MATRIX_SASSR[16]) Security Areas Split for HSELx Security Region */
\r
277 #define MATRIX_SASSR_SASPLIT3(value) ((MATRIX_SASSR_SASPLIT3_Msk & ((value) << MATRIX_SASSR_SASPLIT3_Pos)))
\r
278 #define MATRIX_SASSR_SASPLIT4_Pos 16
\r
279 #define MATRIX_SASSR_SASPLIT4_Msk (0xfu << MATRIX_SASSR_SASPLIT4_Pos) /**< \brief (MATRIX_SASSR[16]) Security Areas Split for HSELx Security Region */
\r
280 #define MATRIX_SASSR_SASPLIT4(value) ((MATRIX_SASSR_SASPLIT4_Msk & ((value) << MATRIX_SASSR_SASPLIT4_Pos)))
\r
281 #define MATRIX_SASSR_SASPLIT5_Pos 20
\r
282 #define MATRIX_SASSR_SASPLIT5_Msk (0xfu << MATRIX_SASSR_SASPLIT5_Pos) /**< \brief (MATRIX_SASSR[16]) Security Areas Split for HSELx Security Region */
\r
283 #define MATRIX_SASSR_SASPLIT5(value) ((MATRIX_SASSR_SASPLIT5_Msk & ((value) << MATRIX_SASSR_SASPLIT5_Pos)))
\r
284 #define MATRIX_SASSR_SASPLIT6_Pos 24
\r
285 #define MATRIX_SASSR_SASPLIT6_Msk (0xfu << MATRIX_SASSR_SASPLIT6_Pos) /**< \brief (MATRIX_SASSR[16]) Security Areas Split for HSELx Security Region */
\r
286 #define MATRIX_SASSR_SASPLIT6(value) ((MATRIX_SASSR_SASPLIT6_Msk & ((value) << MATRIX_SASSR_SASPLIT6_Pos)))
\r
287 #define MATRIX_SASSR_SASPLIT7_Pos 28
\r
288 #define MATRIX_SASSR_SASPLIT7_Msk (0xfu << MATRIX_SASSR_SASPLIT7_Pos) /**< \brief (MATRIX_SASSR[16]) Security Areas Split for HSELx Security Region */
\r
289 #define MATRIX_SASSR_SASPLIT7(value) ((MATRIX_SASSR_SASPLIT7_Msk & ((value) << MATRIX_SASSR_SASPLIT7_Pos)))
\r
290 /* -------- MATRIX_SRTSR[16] : (MATRIX Offset: 0x0280) Security Region Top Slave 0 Register -------- */
\r
291 #define MATRIX_SRTSR_SRTOP0_Pos 0
\r
292 #define MATRIX_SRTSR_SRTOP0_Msk (0xfu << MATRIX_SRTSR_SRTOP0_Pos) /**< \brief (MATRIX_SRTSR[16]) HSELx Security Region Top */
\r
293 #define MATRIX_SRTSR_SRTOP0(value) ((MATRIX_SRTSR_SRTOP0_Msk & ((value) << MATRIX_SRTSR_SRTOP0_Pos)))
\r
294 #define MATRIX_SRTSR_SRTOP1_Pos 4
\r
295 #define MATRIX_SRTSR_SRTOP1_Msk (0xfu << MATRIX_SRTSR_SRTOP1_Pos) /**< \brief (MATRIX_SRTSR[16]) HSELx Security Region Top */
\r
296 #define MATRIX_SRTSR_SRTOP1(value) ((MATRIX_SRTSR_SRTOP1_Msk & ((value) << MATRIX_SRTSR_SRTOP1_Pos)))
\r
297 #define MATRIX_SRTSR_SRTOP2_Pos 8
\r
298 #define MATRIX_SRTSR_SRTOP2_Msk (0xfu << MATRIX_SRTSR_SRTOP2_Pos) /**< \brief (MATRIX_SRTSR[16]) HSELx Security Region Top */
\r
299 #define MATRIX_SRTSR_SRTOP2(value) ((MATRIX_SRTSR_SRTOP2_Msk & ((value) << MATRIX_SRTSR_SRTOP2_Pos)))
\r
300 #define MATRIX_SRTSR_SRTOP3_Pos 12
\r
301 #define MATRIX_SRTSR_SRTOP3_Msk (0xfu << MATRIX_SRTSR_SRTOP3_Pos) /**< \brief (MATRIX_SRTSR[16]) HSELx Security Region Top */
\r
302 #define MATRIX_SRTSR_SRTOP3(value) ((MATRIX_SRTSR_SRTOP3_Msk & ((value) << MATRIX_SRTSR_SRTOP3_Pos)))
\r
303 #define MATRIX_SRTSR_SRTOP4_Pos 16
\r
304 #define MATRIX_SRTSR_SRTOP4_Msk (0xfu << MATRIX_SRTSR_SRTOP4_Pos) /**< \brief (MATRIX_SRTSR[16]) HSELx Security Region Top */
\r
305 #define MATRIX_SRTSR_SRTOP4(value) ((MATRIX_SRTSR_SRTOP4_Msk & ((value) << MATRIX_SRTSR_SRTOP4_Pos)))
\r
306 #define MATRIX_SRTSR_SRTOP5_Pos 20
\r
307 #define MATRIX_SRTSR_SRTOP5_Msk (0xfu << MATRIX_SRTSR_SRTOP5_Pos) /**< \brief (MATRIX_SRTSR[16]) HSELx Security Region Top */
\r
308 #define MATRIX_SRTSR_SRTOP5(value) ((MATRIX_SRTSR_SRTOP5_Msk & ((value) << MATRIX_SRTSR_SRTOP5_Pos)))
\r
309 #define MATRIX_SRTSR_SRTOP6_Pos 24
\r
310 #define MATRIX_SRTSR_SRTOP6_Msk (0xfu << MATRIX_SRTSR_SRTOP6_Pos) /**< \brief (MATRIX_SRTSR[16]) HSELx Security Region Top */
\r
311 #define MATRIX_SRTSR_SRTOP6(value) ((MATRIX_SRTSR_SRTOP6_Msk & ((value) << MATRIX_SRTSR_SRTOP6_Pos)))
\r
312 #define MATRIX_SRTSR_SRTOP7_Pos 28
\r
313 #define MATRIX_SRTSR_SRTOP7_Msk (0xfu << MATRIX_SRTSR_SRTOP7_Pos) /**< \brief (MATRIX_SRTSR[16]) HSELx Security Region Top */
\r
314 #define MATRIX_SRTSR_SRTOP7(value) ((MATRIX_SRTSR_SRTOP7_Msk & ((value) << MATRIX_SRTSR_SRTOP7_Pos)))
\r
315 /* -------- MATRIX_SPSELR[3] : (MATRIX Offset: 0x02C0) Security Peripheral Select 1 Register -------- */
\r
316 #define MATRIX_SPSELR_NSECP0 (0x1u << 0) /**< \brief (MATRIX_SPSELR[3]) Not Secured PSELy Peripheral */
\r
317 #define MATRIX_SPSELR_NSECP1 (0x1u << 1) /**< \brief (MATRIX_SPSELR[3]) Not Secured PSELy Peripheral */
\r
318 #define MATRIX_SPSELR_NSECP2 (0x1u << 2) /**< \brief (MATRIX_SPSELR[3]) Not Secured PSELy Peripheral */
\r
319 #define MATRIX_SPSELR_NSECP3 (0x1u << 3) /**< \brief (MATRIX_SPSELR[3]) Not Secured PSELy Peripheral */
\r
320 #define MATRIX_SPSELR_NSECP4 (0x1u << 4) /**< \brief (MATRIX_SPSELR[3]) Not Secured PSELy Peripheral */
\r
321 #define MATRIX_SPSELR_NSECP5 (0x1u << 5) /**< \brief (MATRIX_SPSELR[3]) Not Secured PSELy Peripheral */
\r
322 #define MATRIX_SPSELR_NSECP6 (0x1u << 6) /**< \brief (MATRIX_SPSELR[3]) Not Secured PSELy Peripheral */
\r
323 #define MATRIX_SPSELR_NSECP7 (0x1u << 7) /**< \brief (MATRIX_SPSELR[3]) Not Secured PSELy Peripheral */
\r
324 #define MATRIX_SPSELR_NSECP8 (0x1u << 8) /**< \brief (MATRIX_SPSELR[3]) Not Secured PSELy Peripheral */
\r
325 #define MATRIX_SPSELR_NSECP9 (0x1u << 9) /**< \brief (MATRIX_SPSELR[3]) Not Secured PSELy Peripheral */
\r
326 #define MATRIX_SPSELR_NSECP10 (0x1u << 10) /**< \brief (MATRIX_SPSELR[3]) Not Secured PSELy Peripheral */
\r
327 #define MATRIX_SPSELR_NSECP11 (0x1u << 11) /**< \brief (MATRIX_SPSELR[3]) Not Secured PSELy Peripheral */
\r
328 #define MATRIX_SPSELR_NSECP12 (0x1u << 12) /**< \brief (MATRIX_SPSELR[3]) Not Secured PSELy Peripheral */
\r
329 #define MATRIX_SPSELR_NSECP13 (0x1u << 13) /**< \brief (MATRIX_SPSELR[3]) Not Secured PSELy Peripheral */
\r
330 #define MATRIX_SPSELR_NSECP14 (0x1u << 14) /**< \brief (MATRIX_SPSELR[3]) Not Secured PSELy Peripheral */
\r
331 #define MATRIX_SPSELR_NSECP15 (0x1u << 15) /**< \brief (MATRIX_SPSELR[3]) Not Secured PSELy Peripheral */
\r
332 #define MATRIX_SPSELR_NSECP16 (0x1u << 16) /**< \brief (MATRIX_SPSELR[3]) Not Secured PSELy Peripheral */
\r
333 #define MATRIX_SPSELR_NSECP17 (0x1u << 17) /**< \brief (MATRIX_SPSELR[3]) Not Secured PSELy Peripheral */
\r
334 #define MATRIX_SPSELR_NSECP18 (0x1u << 18) /**< \brief (MATRIX_SPSELR[3]) Not Secured PSELy Peripheral */
\r
335 #define MATRIX_SPSELR_NSECP19 (0x1u << 19) /**< \brief (MATRIX_SPSELR[3]) Not Secured PSELy Peripheral */
\r
336 #define MATRIX_SPSELR_NSECP20 (0x1u << 20) /**< \brief (MATRIX_SPSELR[3]) Not Secured PSELy Peripheral */
\r
337 #define MATRIX_SPSELR_NSECP21 (0x1u << 21) /**< \brief (MATRIX_SPSELR[3]) Not Secured PSELy Peripheral */
\r
338 #define MATRIX_SPSELR_NSECP22 (0x1u << 22) /**< \brief (MATRIX_SPSELR[3]) Not Secured PSELy Peripheral */
\r
339 #define MATRIX_SPSELR_NSECP23 (0x1u << 23) /**< \brief (MATRIX_SPSELR[3]) Not Secured PSELy Peripheral */
\r
340 #define MATRIX_SPSELR_NSECP24 (0x1u << 24) /**< \brief (MATRIX_SPSELR[3]) Not Secured PSELy Peripheral */
\r
341 #define MATRIX_SPSELR_NSECP25 (0x1u << 25) /**< \brief (MATRIX_SPSELR[3]) Not Secured PSELy Peripheral */
\r
342 #define MATRIX_SPSELR_NSECP26 (0x1u << 26) /**< \brief (MATRIX_SPSELR[3]) Not Secured PSELy Peripheral */
\r
343 #define MATRIX_SPSELR_NSECP27 (0x1u << 27) /**< \brief (MATRIX_SPSELR[3]) Not Secured PSELy Peripheral */
\r
344 #define MATRIX_SPSELR_NSECP28 (0x1u << 28) /**< \brief (MATRIX_SPSELR[3]) Not Secured PSELy Peripheral */
\r
345 #define MATRIX_SPSELR_NSECP29 (0x1u << 29) /**< \brief (MATRIX_SPSELR[3]) Not Secured PSELy Peripheral */
\r
346 #define MATRIX_SPSELR_NSECP30 (0x1u << 30) /**< \brief (MATRIX_SPSELR[3]) Not Secured PSELy Peripheral */
\r
347 #define MATRIX_SPSELR_NSECP31 (0x1u << 31) /**< \brief (MATRIX_SPSELR[3]) Not Secured PSELy Peripheral */
\r
352 #endif /* _SAM_MATRIX_COMPONENT_ */
\r
projects / freertos / blob