1 /* ---------------------------------------------------------------------------- */
\r
2 /* Atmel Microcontroller Software Support */
\r
3 /* SAM Software Package License */
\r
4 /* ---------------------------------------------------------------------------- */
\r
5 /* Copyright (c) 2014, Atmel Corporation */
\r
7 /* All rights reserved. */
\r
9 /* Redistribution and use in source and binary forms, with or without */
\r
10 /* modification, are permitted provided that the following condition is met: */
\r
12 /* - Redistributions of source code must retain the above copyright notice, */
\r
13 /* this list of conditions and the disclaimer below. */
\r
15 /* Atmel's name may not be used to endorse or promote products derived from */
\r
16 /* this software without specific prior written permission. */
\r
18 /* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
\r
19 /* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
\r
20 /* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
\r
21 /* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
\r
22 /* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
\r
23 /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
\r
24 /* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
\r
25 /* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
\r
26 /* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
\r
27 /* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
\r
28 /* ---------------------------------------------------------------------------- */
\r
30 #ifndef _SAM_PIO_COMPONENT_
\r
31 #define _SAM_PIO_COMPONENT_
\r
33 /* ============================================================================= */
\r
34 /** SOFTWARE API DEFINITION FOR Parallel Input/Output Controller */
\r
35 /* ============================================================================= */
\r
36 /** \addtogroup SAM_PIO Parallel Input/Output Controller */
\r
39 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
\r
40 /** \brief Pio hardware registers */
\r
42 __O uint32_t PIO_PER; /**< \brief (Pio Offset: 0x0000) PIO Enable Register */
\r
43 __O uint32_t PIO_PDR; /**< \brief (Pio Offset: 0x0004) PIO Disable Register */
\r
44 __I uint32_t PIO_PSR; /**< \brief (Pio Offset: 0x0008) PIO Status Register */
\r
45 __I uint32_t Reserved1[1];
\r
46 __O uint32_t PIO_OER; /**< \brief (Pio Offset: 0x0010) Output Enable Register */
\r
47 __O uint32_t PIO_ODR; /**< \brief (Pio Offset: 0x0014) Output Disable Register */
\r
48 __I uint32_t PIO_OSR; /**< \brief (Pio Offset: 0x0018) Output Status Register */
\r
49 __I uint32_t Reserved2[1];
\r
50 __O uint32_t PIO_IFER; /**< \brief (Pio Offset: 0x0020) Glitch Input Filter Enable Register */
\r
51 __O uint32_t PIO_IFDR; /**< \brief (Pio Offset: 0x0024) Glitch Input Filter Disable Register */
\r
52 __I uint32_t PIO_IFSR; /**< \brief (Pio Offset: 0x0028) Glitch Input Filter Status Register */
\r
53 __I uint32_t Reserved3[1];
\r
54 __O uint32_t PIO_SODR; /**< \brief (Pio Offset: 0x0030) Set Output Data Register */
\r
55 __O uint32_t PIO_CODR; /**< \brief (Pio Offset: 0x0034) Clear Output Data Register */
\r
56 __IO uint32_t PIO_ODSR; /**< \brief (Pio Offset: 0x0038) Output Data Status Register */
\r
57 __I uint32_t PIO_PDSR; /**< \brief (Pio Offset: 0x003C) Pin Data Status Register */
\r
58 __O uint32_t PIO_IER; /**< \brief (Pio Offset: 0x0040) Interrupt Enable Register */
\r
59 __O uint32_t PIO_IDR; /**< \brief (Pio Offset: 0x0044) Interrupt Disable Register */
\r
60 __I uint32_t PIO_IMR; /**< \brief (Pio Offset: 0x0048) Interrupt Mask Register */
\r
61 __I uint32_t PIO_ISR; /**< \brief (Pio Offset: 0x004C) Interrupt Status Register */
\r
62 __O uint32_t PIO_MDER; /**< \brief (Pio Offset: 0x0050) Multi-driver Enable Register */
\r
63 __O uint32_t PIO_MDDR; /**< \brief (Pio Offset: 0x0054) Multi-driver Disable Register */
\r
64 __I uint32_t PIO_MDSR; /**< \brief (Pio Offset: 0x0058) Multi-driver Status Register */
\r
65 __I uint32_t Reserved4[1];
\r
66 __O uint32_t PIO_PUDR; /**< \brief (Pio Offset: 0x0060) Pull-up Disable Register */
\r
67 __O uint32_t PIO_PUER; /**< \brief (Pio Offset: 0x0064) Pull-up Enable Register */
\r
68 __I uint32_t PIO_PUSR; /**< \brief (Pio Offset: 0x0068) Pad Pull-up Status Register */
\r
69 __I uint32_t Reserved5[1];
\r
70 __IO uint32_t PIO_ABCDSR[2]; /**< \brief (Pio Offset: 0x0070) Peripheral Select Register */
\r
71 __I uint32_t Reserved6[2];
\r
72 __O uint32_t PIO_IFSCDR; /**< \brief (Pio Offset: 0x0080) Input Filter Slow Clock Disable Register */
\r
73 __O uint32_t PIO_IFSCER; /**< \brief (Pio Offset: 0x0084) Input Filter Slow Clock Enable Register */
\r
74 __I uint32_t PIO_IFSCSR; /**< \brief (Pio Offset: 0x0088) Input Filter Slow Clock Status Register */
\r
75 __IO uint32_t PIO_SCDR; /**< \brief (Pio Offset: 0x008C) Slow Clock Divider Debouncing Register */
\r
76 __O uint32_t PIO_PPDDR; /**< \brief (Pio Offset: 0x0090) Pad Pull-down Disable Register */
\r
77 __O uint32_t PIO_PPDER; /**< \brief (Pio Offset: 0x0094) Pad Pull-down Enable Register */
\r
78 __I uint32_t PIO_PPDSR; /**< \brief (Pio Offset: 0x0098) Pad Pull-down Status Register */
\r
79 __I uint32_t Reserved7[1];
\r
80 __O uint32_t PIO_OWER; /**< \brief (Pio Offset: 0x00A0) Output Write Enable */
\r
81 __O uint32_t PIO_OWDR; /**< \brief (Pio Offset: 0x00A4) Output Write Disable */
\r
82 __I uint32_t PIO_OWSR; /**< \brief (Pio Offset: 0x00A8) Output Write Status Register */
\r
83 __I uint32_t Reserved8[1];
\r
84 __O uint32_t PIO_AIMER; /**< \brief (Pio Offset: 0x00B0) Additional Interrupt Modes Enable Register */
\r
85 __O uint32_t PIO_AIMDR; /**< \brief (Pio Offset: 0x00B4) Additional Interrupt Modes Disable Register */
\r
86 __I uint32_t PIO_AIMMR; /**< \brief (Pio Offset: 0x00B8) Additional Interrupt Modes Mask Register */
\r
87 __I uint32_t Reserved9[1];
\r
88 __O uint32_t PIO_ESR; /**< \brief (Pio Offset: 0x00C0) Edge Select Register */
\r
89 __O uint32_t PIO_LSR; /**< \brief (Pio Offset: 0x00C4) Level Select Register */
\r
90 __I uint32_t PIO_ELSR; /**< \brief (Pio Offset: 0x00C8) Edge/Level Status Register */
\r
91 __I uint32_t Reserved10[1];
\r
92 __O uint32_t PIO_FELLSR; /**< \brief (Pio Offset: 0x00D0) Falling Edge/Low-Level Select Register */
\r
93 __O uint32_t PIO_REHLSR; /**< \brief (Pio Offset: 0x00D4) Rising Edge/ High-Level Select Register */
\r
94 __I uint32_t PIO_FRLHSR; /**< \brief (Pio Offset: 0x00D8) Fall/Rise - Low/High Status Register */
\r
95 __I uint32_t Reserved11[1];
\r
96 __I uint32_t PIO_LOCKSR; /**< \brief (Pio Offset: 0x00E0) Lock Status */
\r
97 __IO uint32_t PIO_WPMR; /**< \brief (Pio Offset: 0x00E4) Write Protection Mode Register */
\r
98 __I uint32_t PIO_WPSR; /**< \brief (Pio Offset: 0x00E8) Write Protection Status Register */
\r
99 __I uint32_t Reserved12[4];
\r
100 __I uint32_t PIO_VERSION; /**< \brief (Pio Offset: 0x00FC) Version Register */
\r
101 __IO uint32_t PIO_SCHMITT; /**< \brief (Pio Offset: 0x0100) Schmitt Trigger Register */
\r
102 __I uint32_t Reserved13[7];
\r
103 __IO uint32_t PIO_KER; /**< \brief (Pio Offset: 0x0120) Keypad Controller Enable Register */
\r
104 __IO uint32_t PIO_KRCR; /**< \brief (Pio Offset: 0x0124) Keypad Controller Row Column Register */
\r
105 __IO uint32_t PIO_KDR; /**< \brief (Pio Offset: 0x0128) Keypad Controller Debouncing Register */
\r
106 __I uint32_t Reserved14[1];
\r
107 __O uint32_t PIO_KIER; /**< \brief (Pio Offset: 0x0130) Keypad Controller Interrupt Enable Register */
\r
108 __O uint32_t PIO_KIDR; /**< \brief (Pio Offset: 0x0134) Keypad Controller Interrupt Disable Register */
\r
109 __I uint32_t PIO_KIMR; /**< \brief (Pio Offset: 0x0138) Keypad Controller Interrupt Mask Register */
\r
110 __I uint32_t PIO_KSR; /**< \brief (Pio Offset: 0x013C) Keypad Controller Status Register */
\r
111 __I uint32_t PIO_KKPR; /**< \brief (Pio Offset: 0x0140) Keypad Controller Key Press Register */
\r
112 __I uint32_t PIO_KKRR; /**< \brief (Pio Offset: 0x0144) Keypad Controller Key Release Register */
\r
113 __I uint32_t Reserved15[2];
\r
114 __IO uint32_t PIO_PCMR; /**< \brief (Pio Offset: 0x150) Parallel Capture Mode Register */
\r
115 __O uint32_t PIO_PCIER; /**< \brief (Pio Offset: 0x154) Parallel Capture Interrupt Enable Register */
\r
116 __O uint32_t PIO_PCIDR; /**< \brief (Pio Offset: 0x158) Parallel Capture Interrupt Disable Register */
\r
117 __I uint32_t PIO_PCIMR; /**< \brief (Pio Offset: 0x15C) Parallel Capture Interrupt Mask Register */
\r
118 __I uint32_t PIO_PCISR; /**< \brief (Pio Offset: 0x160) Parallel Capture Interrupt Status Register */
\r
119 __I uint32_t PIO_PCRHR; /**< \brief (Pio Offset: 0x164) Parallel Capture Reception Holding Register */
\r
121 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
\r
122 /* -------- PIO_PER : (PIO Offset: 0x0000) PIO Enable Register -------- */
\r
123 #define PIO_PER_P0 (0x1u << 0) /**< \brief (PIO_PER) PIO Enable */
\r
124 #define PIO_PER_P1 (0x1u << 1) /**< \brief (PIO_PER) PIO Enable */
\r
125 #define PIO_PER_P2 (0x1u << 2) /**< \brief (PIO_PER) PIO Enable */
\r
126 #define PIO_PER_P3 (0x1u << 3) /**< \brief (PIO_PER) PIO Enable */
\r
127 #define PIO_PER_P4 (0x1u << 4) /**< \brief (PIO_PER) PIO Enable */
\r
128 #define PIO_PER_P5 (0x1u << 5) /**< \brief (PIO_PER) PIO Enable */
\r
129 #define PIO_PER_P6 (0x1u << 6) /**< \brief (PIO_PER) PIO Enable */
\r
130 #define PIO_PER_P7 (0x1u << 7) /**< \brief (PIO_PER) PIO Enable */
\r
131 #define PIO_PER_P8 (0x1u << 8) /**< \brief (PIO_PER) PIO Enable */
\r
132 #define PIO_PER_P9 (0x1u << 9) /**< \brief (PIO_PER) PIO Enable */
\r
133 #define PIO_PER_P10 (0x1u << 10) /**< \brief (PIO_PER) PIO Enable */
\r
134 #define PIO_PER_P11 (0x1u << 11) /**< \brief (PIO_PER) PIO Enable */
\r
135 #define PIO_PER_P12 (0x1u << 12) /**< \brief (PIO_PER) PIO Enable */
\r
136 #define PIO_PER_P13 (0x1u << 13) /**< \brief (PIO_PER) PIO Enable */
\r
137 #define PIO_PER_P14 (0x1u << 14) /**< \brief (PIO_PER) PIO Enable */
\r
138 #define PIO_PER_P15 (0x1u << 15) /**< \brief (PIO_PER) PIO Enable */
\r
139 #define PIO_PER_P16 (0x1u << 16) /**< \brief (PIO_PER) PIO Enable */
\r
140 #define PIO_PER_P17 (0x1u << 17) /**< \brief (PIO_PER) PIO Enable */
\r
141 #define PIO_PER_P18 (0x1u << 18) /**< \brief (PIO_PER) PIO Enable */
\r
142 #define PIO_PER_P19 (0x1u << 19) /**< \brief (PIO_PER) PIO Enable */
\r
143 #define PIO_PER_P20 (0x1u << 20) /**< \brief (PIO_PER) PIO Enable */
\r
144 #define PIO_PER_P21 (0x1u << 21) /**< \brief (PIO_PER) PIO Enable */
\r
145 #define PIO_PER_P22 (0x1u << 22) /**< \brief (PIO_PER) PIO Enable */
\r
146 #define PIO_PER_P23 (0x1u << 23) /**< \brief (PIO_PER) PIO Enable */
\r
147 #define PIO_PER_P24 (0x1u << 24) /**< \brief (PIO_PER) PIO Enable */
\r
148 #define PIO_PER_P25 (0x1u << 25) /**< \brief (PIO_PER) PIO Enable */
\r
149 #define PIO_PER_P26 (0x1u << 26) /**< \brief (PIO_PER) PIO Enable */
\r
150 #define PIO_PER_P27 (0x1u << 27) /**< \brief (PIO_PER) PIO Enable */
\r
151 #define PIO_PER_P28 (0x1u << 28) /**< \brief (PIO_PER) PIO Enable */
\r
152 #define PIO_PER_P29 (0x1u << 29) /**< \brief (PIO_PER) PIO Enable */
\r
153 #define PIO_PER_P30 (0x1u << 30) /**< \brief (PIO_PER) PIO Enable */
\r
154 #define PIO_PER_P31 (0x1u << 31) /**< \brief (PIO_PER) PIO Enable */
\r
155 /* -------- PIO_PDR : (PIO Offset: 0x0004) PIO Disable Register -------- */
\r
156 #define PIO_PDR_P0 (0x1u << 0) /**< \brief (PIO_PDR) PIO Disable */
\r
157 #define PIO_PDR_P1 (0x1u << 1) /**< \brief (PIO_PDR) PIO Disable */
\r
158 #define PIO_PDR_P2 (0x1u << 2) /**< \brief (PIO_PDR) PIO Disable */
\r
159 #define PIO_PDR_P3 (0x1u << 3) /**< \brief (PIO_PDR) PIO Disable */
\r
160 #define PIO_PDR_P4 (0x1u << 4) /**< \brief (PIO_PDR) PIO Disable */
\r
161 #define PIO_PDR_P5 (0x1u << 5) /**< \brief (PIO_PDR) PIO Disable */
\r
162 #define PIO_PDR_P6 (0x1u << 6) /**< \brief (PIO_PDR) PIO Disable */
\r
163 #define PIO_PDR_P7 (0x1u << 7) /**< \brief (PIO_PDR) PIO Disable */
\r
164 #define PIO_PDR_P8 (0x1u << 8) /**< \brief (PIO_PDR) PIO Disable */
\r
165 #define PIO_PDR_P9 (0x1u << 9) /**< \brief (PIO_PDR) PIO Disable */
\r
166 #define PIO_PDR_P10 (0x1u << 10) /**< \brief (PIO_PDR) PIO Disable */
\r
167 #define PIO_PDR_P11 (0x1u << 11) /**< \brief (PIO_PDR) PIO Disable */
\r
168 #define PIO_PDR_P12 (0x1u << 12) /**< \brief (PIO_PDR) PIO Disable */
\r
169 #define PIO_PDR_P13 (0x1u << 13) /**< \brief (PIO_PDR) PIO Disable */
\r
170 #define PIO_PDR_P14 (0x1u << 14) /**< \brief (PIO_PDR) PIO Disable */
\r
171 #define PIO_PDR_P15 (0x1u << 15) /**< \brief (PIO_PDR) PIO Disable */
\r
172 #define PIO_PDR_P16 (0x1u << 16) /**< \brief (PIO_PDR) PIO Disable */
\r
173 #define PIO_PDR_P17 (0x1u << 17) /**< \brief (PIO_PDR) PIO Disable */
\r
174 #define PIO_PDR_P18 (0x1u << 18) /**< \brief (PIO_PDR) PIO Disable */
\r
175 #define PIO_PDR_P19 (0x1u << 19) /**< \brief (PIO_PDR) PIO Disable */
\r
176 #define PIO_PDR_P20 (0x1u << 20) /**< \brief (PIO_PDR) PIO Disable */
\r
177 #define PIO_PDR_P21 (0x1u << 21) /**< \brief (PIO_PDR) PIO Disable */
\r
178 #define PIO_PDR_P22 (0x1u << 22) /**< \brief (PIO_PDR) PIO Disable */
\r
179 #define PIO_PDR_P23 (0x1u << 23) /**< \brief (PIO_PDR) PIO Disable */
\r
180 #define PIO_PDR_P24 (0x1u << 24) /**< \brief (PIO_PDR) PIO Disable */
\r
181 #define PIO_PDR_P25 (0x1u << 25) /**< \brief (PIO_PDR) PIO Disable */
\r
182 #define PIO_PDR_P26 (0x1u << 26) /**< \brief (PIO_PDR) PIO Disable */
\r
183 #define PIO_PDR_P27 (0x1u << 27) /**< \brief (PIO_PDR) PIO Disable */
\r
184 #define PIO_PDR_P28 (0x1u << 28) /**< \brief (PIO_PDR) PIO Disable */
\r
185 #define PIO_PDR_P29 (0x1u << 29) /**< \brief (PIO_PDR) PIO Disable */
\r
186 #define PIO_PDR_P30 (0x1u << 30) /**< \brief (PIO_PDR) PIO Disable */
\r
187 #define PIO_PDR_P31 (0x1u << 31) /**< \brief (PIO_PDR) PIO Disable */
\r
188 /* -------- PIO_PSR : (PIO Offset: 0x0008) PIO Status Register -------- */
\r
189 #define PIO_PSR_P0 (0x1u << 0) /**< \brief (PIO_PSR) PIO Status */
\r
190 #define PIO_PSR_P1 (0x1u << 1) /**< \brief (PIO_PSR) PIO Status */
\r
191 #define PIO_PSR_P2 (0x1u << 2) /**< \brief (PIO_PSR) PIO Status */
\r
192 #define PIO_PSR_P3 (0x1u << 3) /**< \brief (PIO_PSR) PIO Status */
\r
193 #define PIO_PSR_P4 (0x1u << 4) /**< \brief (PIO_PSR) PIO Status */
\r
194 #define PIO_PSR_P5 (0x1u << 5) /**< \brief (PIO_PSR) PIO Status */
\r
195 #define PIO_PSR_P6 (0x1u << 6) /**< \brief (PIO_PSR) PIO Status */
\r
196 #define PIO_PSR_P7 (0x1u << 7) /**< \brief (PIO_PSR) PIO Status */
\r
197 #define PIO_PSR_P8 (0x1u << 8) /**< \brief (PIO_PSR) PIO Status */
\r
198 #define PIO_PSR_P9 (0x1u << 9) /**< \brief (PIO_PSR) PIO Status */
\r
199 #define PIO_PSR_P10 (0x1u << 10) /**< \brief (PIO_PSR) PIO Status */
\r
200 #define PIO_PSR_P11 (0x1u << 11) /**< \brief (PIO_PSR) PIO Status */
\r
201 #define PIO_PSR_P12 (0x1u << 12) /**< \brief (PIO_PSR) PIO Status */
\r
202 #define PIO_PSR_P13 (0x1u << 13) /**< \brief (PIO_PSR) PIO Status */
\r
203 #define PIO_PSR_P14 (0x1u << 14) /**< \brief (PIO_PSR) PIO Status */
\r
204 #define PIO_PSR_P15 (0x1u << 15) /**< \brief (PIO_PSR) PIO Status */
\r
205 #define PIO_PSR_P16 (0x1u << 16) /**< \brief (PIO_PSR) PIO Status */
\r
206 #define PIO_PSR_P17 (0x1u << 17) /**< \brief (PIO_PSR) PIO Status */
\r
207 #define PIO_PSR_P18 (0x1u << 18) /**< \brief (PIO_PSR) PIO Status */
\r
208 #define PIO_PSR_P19 (0x1u << 19) /**< \brief (PIO_PSR) PIO Status */
\r
209 #define PIO_PSR_P20 (0x1u << 20) /**< \brief (PIO_PSR) PIO Status */
\r
210 #define PIO_PSR_P21 (0x1u << 21) /**< \brief (PIO_PSR) PIO Status */
\r
211 #define PIO_PSR_P22 (0x1u << 22) /**< \brief (PIO_PSR) PIO Status */
\r
212 #define PIO_PSR_P23 (0x1u << 23) /**< \brief (PIO_PSR) PIO Status */
\r
213 #define PIO_PSR_P24 (0x1u << 24) /**< \brief (PIO_PSR) PIO Status */
\r
214 #define PIO_PSR_P25 (0x1u << 25) /**< \brief (PIO_PSR) PIO Status */
\r
215 #define PIO_PSR_P26 (0x1u << 26) /**< \brief (PIO_PSR) PIO Status */
\r
216 #define PIO_PSR_P27 (0x1u << 27) /**< \brief (PIO_PSR) PIO Status */
\r
217 #define PIO_PSR_P28 (0x1u << 28) /**< \brief (PIO_PSR) PIO Status */
\r
218 #define PIO_PSR_P29 (0x1u << 29) /**< \brief (PIO_PSR) PIO Status */
\r
219 #define PIO_PSR_P30 (0x1u << 30) /**< \brief (PIO_PSR) PIO Status */
\r
220 #define PIO_PSR_P31 (0x1u << 31) /**< \brief (PIO_PSR) PIO Status */
\r
221 /* -------- PIO_OER : (PIO Offset: 0x0010) Output Enable Register -------- */
\r
222 #define PIO_OER_P0 (0x1u << 0) /**< \brief (PIO_OER) Output Enable */
\r
223 #define PIO_OER_P1 (0x1u << 1) /**< \brief (PIO_OER) Output Enable */
\r
224 #define PIO_OER_P2 (0x1u << 2) /**< \brief (PIO_OER) Output Enable */
\r
225 #define PIO_OER_P3 (0x1u << 3) /**< \brief (PIO_OER) Output Enable */
\r
226 #define PIO_OER_P4 (0x1u << 4) /**< \brief (PIO_OER) Output Enable */
\r
227 #define PIO_OER_P5 (0x1u << 5) /**< \brief (PIO_OER) Output Enable */
\r
228 #define PIO_OER_P6 (0x1u << 6) /**< \brief (PIO_OER) Output Enable */
\r
229 #define PIO_OER_P7 (0x1u << 7) /**< \brief (PIO_OER) Output Enable */
\r
230 #define PIO_OER_P8 (0x1u << 8) /**< \brief (PIO_OER) Output Enable */
\r
231 #define PIO_OER_P9 (0x1u << 9) /**< \brief (PIO_OER) Output Enable */
\r
232 #define PIO_OER_P10 (0x1u << 10) /**< \brief (PIO_OER) Output Enable */
\r
233 #define PIO_OER_P11 (0x1u << 11) /**< \brief (PIO_OER) Output Enable */
\r
234 #define PIO_OER_P12 (0x1u << 12) /**< \brief (PIO_OER) Output Enable */
\r
235 #define PIO_OER_P13 (0x1u << 13) /**< \brief (PIO_OER) Output Enable */
\r
236 #define PIO_OER_P14 (0x1u << 14) /**< \brief (PIO_OER) Output Enable */
\r
237 #define PIO_OER_P15 (0x1u << 15) /**< \brief (PIO_OER) Output Enable */
\r
238 #define PIO_OER_P16 (0x1u << 16) /**< \brief (PIO_OER) Output Enable */
\r
239 #define PIO_OER_P17 (0x1u << 17) /**< \brief (PIO_OER) Output Enable */
\r
240 #define PIO_OER_P18 (0x1u << 18) /**< \brief (PIO_OER) Output Enable */
\r
241 #define PIO_OER_P19 (0x1u << 19) /**< \brief (PIO_OER) Output Enable */
\r
242 #define PIO_OER_P20 (0x1u << 20) /**< \brief (PIO_OER) Output Enable */
\r
243 #define PIO_OER_P21 (0x1u << 21) /**< \brief (PIO_OER) Output Enable */
\r
244 #define PIO_OER_P22 (0x1u << 22) /**< \brief (PIO_OER) Output Enable */
\r
245 #define PIO_OER_P23 (0x1u << 23) /**< \brief (PIO_OER) Output Enable */
\r
246 #define PIO_OER_P24 (0x1u << 24) /**< \brief (PIO_OER) Output Enable */
\r
247 #define PIO_OER_P25 (0x1u << 25) /**< \brief (PIO_OER) Output Enable */
\r
248 #define PIO_OER_P26 (0x1u << 26) /**< \brief (PIO_OER) Output Enable */
\r
249 #define PIO_OER_P27 (0x1u << 27) /**< \brief (PIO_OER) Output Enable */
\r
250 #define PIO_OER_P28 (0x1u << 28) /**< \brief (PIO_OER) Output Enable */
\r
251 #define PIO_OER_P29 (0x1u << 29) /**< \brief (PIO_OER) Output Enable */
\r
252 #define PIO_OER_P30 (0x1u << 30) /**< \brief (PIO_OER) Output Enable */
\r
253 #define PIO_OER_P31 (0x1u << 31) /**< \brief (PIO_OER) Output Enable */
\r
254 /* -------- PIO_ODR : (PIO Offset: 0x0014) Output Disable Register -------- */
\r
255 #define PIO_ODR_P0 (0x1u << 0) /**< \brief (PIO_ODR) Output Disable */
\r
256 #define PIO_ODR_P1 (0x1u << 1) /**< \brief (PIO_ODR) Output Disable */
\r
257 #define PIO_ODR_P2 (0x1u << 2) /**< \brief (PIO_ODR) Output Disable */
\r
258 #define PIO_ODR_P3 (0x1u << 3) /**< \brief (PIO_ODR) Output Disable */
\r
259 #define PIO_ODR_P4 (0x1u << 4) /**< \brief (PIO_ODR) Output Disable */
\r
260 #define PIO_ODR_P5 (0x1u << 5) /**< \brief (PIO_ODR) Output Disable */
\r
261 #define PIO_ODR_P6 (0x1u << 6) /**< \brief (PIO_ODR) Output Disable */
\r
262 #define PIO_ODR_P7 (0x1u << 7) /**< \brief (PIO_ODR) Output Disable */
\r
263 #define PIO_ODR_P8 (0x1u << 8) /**< \brief (PIO_ODR) Output Disable */
\r
264 #define PIO_ODR_P9 (0x1u << 9) /**< \brief (PIO_ODR) Output Disable */
\r
265 #define PIO_ODR_P10 (0x1u << 10) /**< \brief (PIO_ODR) Output Disable */
\r
266 #define PIO_ODR_P11 (0x1u << 11) /**< \brief (PIO_ODR) Output Disable */
\r
267 #define PIO_ODR_P12 (0x1u << 12) /**< \brief (PIO_ODR) Output Disable */
\r
268 #define PIO_ODR_P13 (0x1u << 13) /**< \brief (PIO_ODR) Output Disable */
\r
269 #define PIO_ODR_P14 (0x1u << 14) /**< \brief (PIO_ODR) Output Disable */
\r
270 #define PIO_ODR_P15 (0x1u << 15) /**< \brief (PIO_ODR) Output Disable */
\r
271 #define PIO_ODR_P16 (0x1u << 16) /**< \brief (PIO_ODR) Output Disable */
\r
272 #define PIO_ODR_P17 (0x1u << 17) /**< \brief (PIO_ODR) Output Disable */
\r
273 #define PIO_ODR_P18 (0x1u << 18) /**< \brief (PIO_ODR) Output Disable */
\r
274 #define PIO_ODR_P19 (0x1u << 19) /**< \brief (PIO_ODR) Output Disable */
\r
275 #define PIO_ODR_P20 (0x1u << 20) /**< \brief (PIO_ODR) Output Disable */
\r
276 #define PIO_ODR_P21 (0x1u << 21) /**< \brief (PIO_ODR) Output Disable */
\r
277 #define PIO_ODR_P22 (0x1u << 22) /**< \brief (PIO_ODR) Output Disable */
\r
278 #define PIO_ODR_P23 (0x1u << 23) /**< \brief (PIO_ODR) Output Disable */
\r
279 #define PIO_ODR_P24 (0x1u << 24) /**< \brief (PIO_ODR) Output Disable */
\r
280 #define PIO_ODR_P25 (0x1u << 25) /**< \brief (PIO_ODR) Output Disable */
\r
281 #define PIO_ODR_P26 (0x1u << 26) /**< \brief (PIO_ODR) Output Disable */
\r
282 #define PIO_ODR_P27 (0x1u << 27) /**< \brief (PIO_ODR) Output Disable */
\r
283 #define PIO_ODR_P28 (0x1u << 28) /**< \brief (PIO_ODR) Output Disable */
\r
284 #define PIO_ODR_P29 (0x1u << 29) /**< \brief (PIO_ODR) Output Disable */
\r
285 #define PIO_ODR_P30 (0x1u << 30) /**< \brief (PIO_ODR) Output Disable */
\r
286 #define PIO_ODR_P31 (0x1u << 31) /**< \brief (PIO_ODR) Output Disable */
\r
287 /* -------- PIO_OSR : (PIO Offset: 0x0018) Output Status Register -------- */
\r
288 #define PIO_OSR_P0 (0x1u << 0) /**< \brief (PIO_OSR) Output Status */
\r
289 #define PIO_OSR_P1 (0x1u << 1) /**< \brief (PIO_OSR) Output Status */
\r
290 #define PIO_OSR_P2 (0x1u << 2) /**< \brief (PIO_OSR) Output Status */
\r
291 #define PIO_OSR_P3 (0x1u << 3) /**< \brief (PIO_OSR) Output Status */
\r
292 #define PIO_OSR_P4 (0x1u << 4) /**< \brief (PIO_OSR) Output Status */
\r
293 #define PIO_OSR_P5 (0x1u << 5) /**< \brief (PIO_OSR) Output Status */
\r
294 #define PIO_OSR_P6 (0x1u << 6) /**< \brief (PIO_OSR) Output Status */
\r
295 #define PIO_OSR_P7 (0x1u << 7) /**< \brief (PIO_OSR) Output Status */
\r
296 #define PIO_OSR_P8 (0x1u << 8) /**< \brief (PIO_OSR) Output Status */
\r
297 #define PIO_OSR_P9 (0x1u << 9) /**< \brief (PIO_OSR) Output Status */
\r
298 #define PIO_OSR_P10 (0x1u << 10) /**< \brief (PIO_OSR) Output Status */
\r
299 #define PIO_OSR_P11 (0x1u << 11) /**< \brief (PIO_OSR) Output Status */
\r
300 #define PIO_OSR_P12 (0x1u << 12) /**< \brief (PIO_OSR) Output Status */
\r
301 #define PIO_OSR_P13 (0x1u << 13) /**< \brief (PIO_OSR) Output Status */
\r
302 #define PIO_OSR_P14 (0x1u << 14) /**< \brief (PIO_OSR) Output Status */
\r
303 #define PIO_OSR_P15 (0x1u << 15) /**< \brief (PIO_OSR) Output Status */
\r
304 #define PIO_OSR_P16 (0x1u << 16) /**< \brief (PIO_OSR) Output Status */
\r
305 #define PIO_OSR_P17 (0x1u << 17) /**< \brief (PIO_OSR) Output Status */
\r
306 #define PIO_OSR_P18 (0x1u << 18) /**< \brief (PIO_OSR) Output Status */
\r
307 #define PIO_OSR_P19 (0x1u << 19) /**< \brief (PIO_OSR) Output Status */
\r
308 #define PIO_OSR_P20 (0x1u << 20) /**< \brief (PIO_OSR) Output Status */
\r
309 #define PIO_OSR_P21 (0x1u << 21) /**< \brief (PIO_OSR) Output Status */
\r
310 #define PIO_OSR_P22 (0x1u << 22) /**< \brief (PIO_OSR) Output Status */
\r
311 #define PIO_OSR_P23 (0x1u << 23) /**< \brief (PIO_OSR) Output Status */
\r
312 #define PIO_OSR_P24 (0x1u << 24) /**< \brief (PIO_OSR) Output Status */
\r
313 #define PIO_OSR_P25 (0x1u << 25) /**< \brief (PIO_OSR) Output Status */
\r
314 #define PIO_OSR_P26 (0x1u << 26) /**< \brief (PIO_OSR) Output Status */
\r
315 #define PIO_OSR_P27 (0x1u << 27) /**< \brief (PIO_OSR) Output Status */
\r
316 #define PIO_OSR_P28 (0x1u << 28) /**< \brief (PIO_OSR) Output Status */
\r
317 #define PIO_OSR_P29 (0x1u << 29) /**< \brief (PIO_OSR) Output Status */
\r
318 #define PIO_OSR_P30 (0x1u << 30) /**< \brief (PIO_OSR) Output Status */
\r
319 #define PIO_OSR_P31 (0x1u << 31) /**< \brief (PIO_OSR) Output Status */
\r
320 /* -------- PIO_IFER : (PIO Offset: 0x0020) Glitch Input Filter Enable Register -------- */
\r
321 #define PIO_IFER_P0 (0x1u << 0) /**< \brief (PIO_IFER) Input Filter Enable */
\r
322 #define PIO_IFER_P1 (0x1u << 1) /**< \brief (PIO_IFER) Input Filter Enable */
\r
323 #define PIO_IFER_P2 (0x1u << 2) /**< \brief (PIO_IFER) Input Filter Enable */
\r
324 #define PIO_IFER_P3 (0x1u << 3) /**< \brief (PIO_IFER) Input Filter Enable */
\r
325 #define PIO_IFER_P4 (0x1u << 4) /**< \brief (PIO_IFER) Input Filter Enable */
\r
326 #define PIO_IFER_P5 (0x1u << 5) /**< \brief (PIO_IFER) Input Filter Enable */
\r
327 #define PIO_IFER_P6 (0x1u << 6) /**< \brief (PIO_IFER) Input Filter Enable */
\r
328 #define PIO_IFER_P7 (0x1u << 7) /**< \brief (PIO_IFER) Input Filter Enable */
\r
329 #define PIO_IFER_P8 (0x1u << 8) /**< \brief (PIO_IFER) Input Filter Enable */
\r
330 #define PIO_IFER_P9 (0x1u << 9) /**< \brief (PIO_IFER) Input Filter Enable */
\r
331 #define PIO_IFER_P10 (0x1u << 10) /**< \brief (PIO_IFER) Input Filter Enable */
\r
332 #define PIO_IFER_P11 (0x1u << 11) /**< \brief (PIO_IFER) Input Filter Enable */
\r
333 #define PIO_IFER_P12 (0x1u << 12) /**< \brief (PIO_IFER) Input Filter Enable */
\r
334 #define PIO_IFER_P13 (0x1u << 13) /**< \brief (PIO_IFER) Input Filter Enable */
\r
335 #define PIO_IFER_P14 (0x1u << 14) /**< \brief (PIO_IFER) Input Filter Enable */
\r
336 #define PIO_IFER_P15 (0x1u << 15) /**< \brief (PIO_IFER) Input Filter Enable */
\r
337 #define PIO_IFER_P16 (0x1u << 16) /**< \brief (PIO_IFER) Input Filter Enable */
\r
338 #define PIO_IFER_P17 (0x1u << 17) /**< \brief (PIO_IFER) Input Filter Enable */
\r
339 #define PIO_IFER_P18 (0x1u << 18) /**< \brief (PIO_IFER) Input Filter Enable */
\r
340 #define PIO_IFER_P19 (0x1u << 19) /**< \brief (PIO_IFER) Input Filter Enable */
\r
341 #define PIO_IFER_P20 (0x1u << 20) /**< \brief (PIO_IFER) Input Filter Enable */
\r
342 #define PIO_IFER_P21 (0x1u << 21) /**< \brief (PIO_IFER) Input Filter Enable */
\r
343 #define PIO_IFER_P22 (0x1u << 22) /**< \brief (PIO_IFER) Input Filter Enable */
\r
344 #define PIO_IFER_P23 (0x1u << 23) /**< \brief (PIO_IFER) Input Filter Enable */
\r
345 #define PIO_IFER_P24 (0x1u << 24) /**< \brief (PIO_IFER) Input Filter Enable */
\r
346 #define PIO_IFER_P25 (0x1u << 25) /**< \brief (PIO_IFER) Input Filter Enable */
\r
347 #define PIO_IFER_P26 (0x1u << 26) /**< \brief (PIO_IFER) Input Filter Enable */
\r
348 #define PIO_IFER_P27 (0x1u << 27) /**< \brief (PIO_IFER) Input Filter Enable */
\r
349 #define PIO_IFER_P28 (0x1u << 28) /**< \brief (PIO_IFER) Input Filter Enable */
\r
350 #define PIO_IFER_P29 (0x1u << 29) /**< \brief (PIO_IFER) Input Filter Enable */
\r
351 #define PIO_IFER_P30 (0x1u << 30) /**< \brief (PIO_IFER) Input Filter Enable */
\r
352 #define PIO_IFER_P31 (0x1u << 31) /**< \brief (PIO_IFER) Input Filter Enable */
\r
353 /* -------- PIO_IFDR : (PIO Offset: 0x0024) Glitch Input Filter Disable Register -------- */
\r
354 #define PIO_IFDR_P0 (0x1u << 0) /**< \brief (PIO_IFDR) Input Filter Disable */
\r
355 #define PIO_IFDR_P1 (0x1u << 1) /**< \brief (PIO_IFDR) Input Filter Disable */
\r
356 #define PIO_IFDR_P2 (0x1u << 2) /**< \brief (PIO_IFDR) Input Filter Disable */
\r
357 #define PIO_IFDR_P3 (0x1u << 3) /**< \brief (PIO_IFDR) Input Filter Disable */
\r
358 #define PIO_IFDR_P4 (0x1u << 4) /**< \brief (PIO_IFDR) Input Filter Disable */
\r
359 #define PIO_IFDR_P5 (0x1u << 5) /**< \brief (PIO_IFDR) Input Filter Disable */
\r
360 #define PIO_IFDR_P6 (0x1u << 6) /**< \brief (PIO_IFDR) Input Filter Disable */
\r
361 #define PIO_IFDR_P7 (0x1u << 7) /**< \brief (PIO_IFDR) Input Filter Disable */
\r
362 #define PIO_IFDR_P8 (0x1u << 8) /**< \brief (PIO_IFDR) Input Filter Disable */
\r
363 #define PIO_IFDR_P9 (0x1u << 9) /**< \brief (PIO_IFDR) Input Filter Disable */
\r
364 #define PIO_IFDR_P10 (0x1u << 10) /**< \brief (PIO_IFDR) Input Filter Disable */
\r
365 #define PIO_IFDR_P11 (0x1u << 11) /**< \brief (PIO_IFDR) Input Filter Disable */
\r
366 #define PIO_IFDR_P12 (0x1u << 12) /**< \brief (PIO_IFDR) Input Filter Disable */
\r
367 #define PIO_IFDR_P13 (0x1u << 13) /**< \brief (PIO_IFDR) Input Filter Disable */
\r
368 #define PIO_IFDR_P14 (0x1u << 14) /**< \brief (PIO_IFDR) Input Filter Disable */
\r
369 #define PIO_IFDR_P15 (0x1u << 15) /**< \brief (PIO_IFDR) Input Filter Disable */
\r
370 #define PIO_IFDR_P16 (0x1u << 16) /**< \brief (PIO_IFDR) Input Filter Disable */
\r
371 #define PIO_IFDR_P17 (0x1u << 17) /**< \brief (PIO_IFDR) Input Filter Disable */
\r
372 #define PIO_IFDR_P18 (0x1u << 18) /**< \brief (PIO_IFDR) Input Filter Disable */
\r
373 #define PIO_IFDR_P19 (0x1u << 19) /**< \brief (PIO_IFDR) Input Filter Disable */
\r
374 #define PIO_IFDR_P20 (0x1u << 20) /**< \brief (PIO_IFDR) Input Filter Disable */
\r
375 #define PIO_IFDR_P21 (0x1u << 21) /**< \brief (PIO_IFDR) Input Filter Disable */
\r
376 #define PIO_IFDR_P22 (0x1u << 22) /**< \brief (PIO_IFDR) Input Filter Disable */
\r
377 #define PIO_IFDR_P23 (0x1u << 23) /**< \brief (PIO_IFDR) Input Filter Disable */
\r
378 #define PIO_IFDR_P24 (0x1u << 24) /**< \brief (PIO_IFDR) Input Filter Disable */
\r
379 #define PIO_IFDR_P25 (0x1u << 25) /**< \brief (PIO_IFDR) Input Filter Disable */
\r
380 #define PIO_IFDR_P26 (0x1u << 26) /**< \brief (PIO_IFDR) Input Filter Disable */
\r
381 #define PIO_IFDR_P27 (0x1u << 27) /**< \brief (PIO_IFDR) Input Filter Disable */
\r
382 #define PIO_IFDR_P28 (0x1u << 28) /**< \brief (PIO_IFDR) Input Filter Disable */
\r
383 #define PIO_IFDR_P29 (0x1u << 29) /**< \brief (PIO_IFDR) Input Filter Disable */
\r
384 #define PIO_IFDR_P30 (0x1u << 30) /**< \brief (PIO_IFDR) Input Filter Disable */
\r
385 #define PIO_IFDR_P31 (0x1u << 31) /**< \brief (PIO_IFDR) Input Filter Disable */
\r
386 /* -------- PIO_IFSR : (PIO Offset: 0x0028) Glitch Input Filter Status Register -------- */
\r
387 #define PIO_IFSR_P0 (0x1u << 0) /**< \brief (PIO_IFSR) Input Filer Status */
\r
388 #define PIO_IFSR_P1 (0x1u << 1) /**< \brief (PIO_IFSR) Input Filer Status */
\r
389 #define PIO_IFSR_P2 (0x1u << 2) /**< \brief (PIO_IFSR) Input Filer Status */
\r
390 #define PIO_IFSR_P3 (0x1u << 3) /**< \brief (PIO_IFSR) Input Filer Status */
\r
391 #define PIO_IFSR_P4 (0x1u << 4) /**< \brief (PIO_IFSR) Input Filer Status */
\r
392 #define PIO_IFSR_P5 (0x1u << 5) /**< \brief (PIO_IFSR) Input Filer Status */
\r
393 #define PIO_IFSR_P6 (0x1u << 6) /**< \brief (PIO_IFSR) Input Filer Status */
\r
394 #define PIO_IFSR_P7 (0x1u << 7) /**< \brief (PIO_IFSR) Input Filer Status */
\r
395 #define PIO_IFSR_P8 (0x1u << 8) /**< \brief (PIO_IFSR) Input Filer Status */
\r
396 #define PIO_IFSR_P9 (0x1u << 9) /**< \brief (PIO_IFSR) Input Filer Status */
\r
397 #define PIO_IFSR_P10 (0x1u << 10) /**< \brief (PIO_IFSR) Input Filer Status */
\r
398 #define PIO_IFSR_P11 (0x1u << 11) /**< \brief (PIO_IFSR) Input Filer Status */
\r
399 #define PIO_IFSR_P12 (0x1u << 12) /**< \brief (PIO_IFSR) Input Filer Status */
\r
400 #define PIO_IFSR_P13 (0x1u << 13) /**< \brief (PIO_IFSR) Input Filer Status */
\r
401 #define PIO_IFSR_P14 (0x1u << 14) /**< \brief (PIO_IFSR) Input Filer Status */
\r
402 #define PIO_IFSR_P15 (0x1u << 15) /**< \brief (PIO_IFSR) Input Filer Status */
\r
403 #define PIO_IFSR_P16 (0x1u << 16) /**< \brief (PIO_IFSR) Input Filer Status */
\r
404 #define PIO_IFSR_P17 (0x1u << 17) /**< \brief (PIO_IFSR) Input Filer Status */
\r
405 #define PIO_IFSR_P18 (0x1u << 18) /**< \brief (PIO_IFSR) Input Filer Status */
\r
406 #define PIO_IFSR_P19 (0x1u << 19) /**< \brief (PIO_IFSR) Input Filer Status */
\r
407 #define PIO_IFSR_P20 (0x1u << 20) /**< \brief (PIO_IFSR) Input Filer Status */
\r
408 #define PIO_IFSR_P21 (0x1u << 21) /**< \brief (PIO_IFSR) Input Filer Status */
\r
409 #define PIO_IFSR_P22 (0x1u << 22) /**< \brief (PIO_IFSR) Input Filer Status */
\r
410 #define PIO_IFSR_P23 (0x1u << 23) /**< \brief (PIO_IFSR) Input Filer Status */
\r
411 #define PIO_IFSR_P24 (0x1u << 24) /**< \brief (PIO_IFSR) Input Filer Status */
\r
412 #define PIO_IFSR_P25 (0x1u << 25) /**< \brief (PIO_IFSR) Input Filer Status */
\r
413 #define PIO_IFSR_P26 (0x1u << 26) /**< \brief (PIO_IFSR) Input Filer Status */
\r
414 #define PIO_IFSR_P27 (0x1u << 27) /**< \brief (PIO_IFSR) Input Filer Status */
\r
415 #define PIO_IFSR_P28 (0x1u << 28) /**< \brief (PIO_IFSR) Input Filer Status */
\r
416 #define PIO_IFSR_P29 (0x1u << 29) /**< \brief (PIO_IFSR) Input Filer Status */
\r
417 #define PIO_IFSR_P30 (0x1u << 30) /**< \brief (PIO_IFSR) Input Filer Status */
\r
418 #define PIO_IFSR_P31 (0x1u << 31) /**< \brief (PIO_IFSR) Input Filer Status */
\r
419 /* -------- PIO_SODR : (PIO Offset: 0x0030) Set Output Data Register -------- */
\r
420 #define PIO_SODR_P0 (0x1u << 0) /**< \brief (PIO_SODR) Set Output Data */
\r
421 #define PIO_SODR_P1 (0x1u << 1) /**< \brief (PIO_SODR) Set Output Data */
\r
422 #define PIO_SODR_P2 (0x1u << 2) /**< \brief (PIO_SODR) Set Output Data */
\r
423 #define PIO_SODR_P3 (0x1u << 3) /**< \brief (PIO_SODR) Set Output Data */
\r
424 #define PIO_SODR_P4 (0x1u << 4) /**< \brief (PIO_SODR) Set Output Data */
\r
425 #define PIO_SODR_P5 (0x1u << 5) /**< \brief (PIO_SODR) Set Output Data */
\r
426 #define PIO_SODR_P6 (0x1u << 6) /**< \brief (PIO_SODR) Set Output Data */
\r
427 #define PIO_SODR_P7 (0x1u << 7) /**< \brief (PIO_SODR) Set Output Data */
\r
428 #define PIO_SODR_P8 (0x1u << 8) /**< \brief (PIO_SODR) Set Output Data */
\r
429 #define PIO_SODR_P9 (0x1u << 9) /**< \brief (PIO_SODR) Set Output Data */
\r
430 #define PIO_SODR_P10 (0x1u << 10) /**< \brief (PIO_SODR) Set Output Data */
\r
431 #define PIO_SODR_P11 (0x1u << 11) /**< \brief (PIO_SODR) Set Output Data */
\r
432 #define PIO_SODR_P12 (0x1u << 12) /**< \brief (PIO_SODR) Set Output Data */
\r
433 #define PIO_SODR_P13 (0x1u << 13) /**< \brief (PIO_SODR) Set Output Data */
\r
434 #define PIO_SODR_P14 (0x1u << 14) /**< \brief (PIO_SODR) Set Output Data */
\r
435 #define PIO_SODR_P15 (0x1u << 15) /**< \brief (PIO_SODR) Set Output Data */
\r
436 #define PIO_SODR_P16 (0x1u << 16) /**< \brief (PIO_SODR) Set Output Data */
\r
437 #define PIO_SODR_P17 (0x1u << 17) /**< \brief (PIO_SODR) Set Output Data */
\r
438 #define PIO_SODR_P18 (0x1u << 18) /**< \brief (PIO_SODR) Set Output Data */
\r
439 #define PIO_SODR_P19 (0x1u << 19) /**< \brief (PIO_SODR) Set Output Data */
\r
440 #define PIO_SODR_P20 (0x1u << 20) /**< \brief (PIO_SODR) Set Output Data */
\r
441 #define PIO_SODR_P21 (0x1u << 21) /**< \brief (PIO_SODR) Set Output Data */
\r
442 #define PIO_SODR_P22 (0x1u << 22) /**< \brief (PIO_SODR) Set Output Data */
\r
443 #define PIO_SODR_P23 (0x1u << 23) /**< \brief (PIO_SODR) Set Output Data */
\r
444 #define PIO_SODR_P24 (0x1u << 24) /**< \brief (PIO_SODR) Set Output Data */
\r
445 #define PIO_SODR_P25 (0x1u << 25) /**< \brief (PIO_SODR) Set Output Data */
\r
446 #define PIO_SODR_P26 (0x1u << 26) /**< \brief (PIO_SODR) Set Output Data */
\r
447 #define PIO_SODR_P27 (0x1u << 27) /**< \brief (PIO_SODR) Set Output Data */
\r
448 #define PIO_SODR_P28 (0x1u << 28) /**< \brief (PIO_SODR) Set Output Data */
\r
449 #define PIO_SODR_P29 (0x1u << 29) /**< \brief (PIO_SODR) Set Output Data */
\r
450 #define PIO_SODR_P30 (0x1u << 30) /**< \brief (PIO_SODR) Set Output Data */
\r
451 #define PIO_SODR_P31 (0x1u << 31) /**< \brief (PIO_SODR) Set Output Data */
\r
452 /* -------- PIO_CODR : (PIO Offset: 0x0034) Clear Output Data Register -------- */
\r
453 #define PIO_CODR_P0 (0x1u << 0) /**< \brief (PIO_CODR) Clear Output Data */
\r
454 #define PIO_CODR_P1 (0x1u << 1) /**< \brief (PIO_CODR) Clear Output Data */
\r
455 #define PIO_CODR_P2 (0x1u << 2) /**< \brief (PIO_CODR) Clear Output Data */
\r
456 #define PIO_CODR_P3 (0x1u << 3) /**< \brief (PIO_CODR) Clear Output Data */
\r
457 #define PIO_CODR_P4 (0x1u << 4) /**< \brief (PIO_CODR) Clear Output Data */
\r
458 #define PIO_CODR_P5 (0x1u << 5) /**< \brief (PIO_CODR) Clear Output Data */
\r
459 #define PIO_CODR_P6 (0x1u << 6) /**< \brief (PIO_CODR) Clear Output Data */
\r
460 #define PIO_CODR_P7 (0x1u << 7) /**< \brief (PIO_CODR) Clear Output Data */
\r
461 #define PIO_CODR_P8 (0x1u << 8) /**< \brief (PIO_CODR) Clear Output Data */
\r
462 #define PIO_CODR_P9 (0x1u << 9) /**< \brief (PIO_CODR) Clear Output Data */
\r
463 #define PIO_CODR_P10 (0x1u << 10) /**< \brief (PIO_CODR) Clear Output Data */
\r
464 #define PIO_CODR_P11 (0x1u << 11) /**< \brief (PIO_CODR) Clear Output Data */
\r
465 #define PIO_CODR_P12 (0x1u << 12) /**< \brief (PIO_CODR) Clear Output Data */
\r
466 #define PIO_CODR_P13 (0x1u << 13) /**< \brief (PIO_CODR) Clear Output Data */
\r
467 #define PIO_CODR_P14 (0x1u << 14) /**< \brief (PIO_CODR) Clear Output Data */
\r
468 #define PIO_CODR_P15 (0x1u << 15) /**< \brief (PIO_CODR) Clear Output Data */
\r
469 #define PIO_CODR_P16 (0x1u << 16) /**< \brief (PIO_CODR) Clear Output Data */
\r
470 #define PIO_CODR_P17 (0x1u << 17) /**< \brief (PIO_CODR) Clear Output Data */
\r
471 #define PIO_CODR_P18 (0x1u << 18) /**< \brief (PIO_CODR) Clear Output Data */
\r
472 #define PIO_CODR_P19 (0x1u << 19) /**< \brief (PIO_CODR) Clear Output Data */
\r
473 #define PIO_CODR_P20 (0x1u << 20) /**< \brief (PIO_CODR) Clear Output Data */
\r
474 #define PIO_CODR_P21 (0x1u << 21) /**< \brief (PIO_CODR) Clear Output Data */
\r
475 #define PIO_CODR_P22 (0x1u << 22) /**< \brief (PIO_CODR) Clear Output Data */
\r
476 #define PIO_CODR_P23 (0x1u << 23) /**< \brief (PIO_CODR) Clear Output Data */
\r
477 #define PIO_CODR_P24 (0x1u << 24) /**< \brief (PIO_CODR) Clear Output Data */
\r
478 #define PIO_CODR_P25 (0x1u << 25) /**< \brief (PIO_CODR) Clear Output Data */
\r
479 #define PIO_CODR_P26 (0x1u << 26) /**< \brief (PIO_CODR) Clear Output Data */
\r
480 #define PIO_CODR_P27 (0x1u << 27) /**< \brief (PIO_CODR) Clear Output Data */
\r
481 #define PIO_CODR_P28 (0x1u << 28) /**< \brief (PIO_CODR) Clear Output Data */
\r
482 #define PIO_CODR_P29 (0x1u << 29) /**< \brief (PIO_CODR) Clear Output Data */
\r
483 #define PIO_CODR_P30 (0x1u << 30) /**< \brief (PIO_CODR) Clear Output Data */
\r
484 #define PIO_CODR_P31 (0x1u << 31) /**< \brief (PIO_CODR) Clear Output Data */
\r
485 /* -------- PIO_ODSR : (PIO Offset: 0x0038) Output Data Status Register -------- */
\r
486 #define PIO_ODSR_P0 (0x1u << 0) /**< \brief (PIO_ODSR) Output Data Status */
\r
487 #define PIO_ODSR_P1 (0x1u << 1) /**< \brief (PIO_ODSR) Output Data Status */
\r
488 #define PIO_ODSR_P2 (0x1u << 2) /**< \brief (PIO_ODSR) Output Data Status */
\r
489 #define PIO_ODSR_P3 (0x1u << 3) /**< \brief (PIO_ODSR) Output Data Status */
\r
490 #define PIO_ODSR_P4 (0x1u << 4) /**< \brief (PIO_ODSR) Output Data Status */
\r
491 #define PIO_ODSR_P5 (0x1u << 5) /**< \brief (PIO_ODSR) Output Data Status */
\r
492 #define PIO_ODSR_P6 (0x1u << 6) /**< \brief (PIO_ODSR) Output Data Status */
\r
493 #define PIO_ODSR_P7 (0x1u << 7) /**< \brief (PIO_ODSR) Output Data Status */
\r
494 #define PIO_ODSR_P8 (0x1u << 8) /**< \brief (PIO_ODSR) Output Data Status */
\r
495 #define PIO_ODSR_P9 (0x1u << 9) /**< \brief (PIO_ODSR) Output Data Status */
\r
496 #define PIO_ODSR_P10 (0x1u << 10) /**< \brief (PIO_ODSR) Output Data Status */
\r
497 #define PIO_ODSR_P11 (0x1u << 11) /**< \brief (PIO_ODSR) Output Data Status */
\r
498 #define PIO_ODSR_P12 (0x1u << 12) /**< \brief (PIO_ODSR) Output Data Status */
\r
499 #define PIO_ODSR_P13 (0x1u << 13) /**< \brief (PIO_ODSR) Output Data Status */
\r
500 #define PIO_ODSR_P14 (0x1u << 14) /**< \brief (PIO_ODSR) Output Data Status */
\r
501 #define PIO_ODSR_P15 (0x1u << 15) /**< \brief (PIO_ODSR) Output Data Status */
\r
502 #define PIO_ODSR_P16 (0x1u << 16) /**< \brief (PIO_ODSR) Output Data Status */
\r
503 #define PIO_ODSR_P17 (0x1u << 17) /**< \brief (PIO_ODSR) Output Data Status */
\r
504 #define PIO_ODSR_P18 (0x1u << 18) /**< \brief (PIO_ODSR) Output Data Status */
\r
505 #define PIO_ODSR_P19 (0x1u << 19) /**< \brief (PIO_ODSR) Output Data Status */
\r
506 #define PIO_ODSR_P20 (0x1u << 20) /**< \brief (PIO_ODSR) Output Data Status */
\r
507 #define PIO_ODSR_P21 (0x1u << 21) /**< \brief (PIO_ODSR) Output Data Status */
\r
508 #define PIO_ODSR_P22 (0x1u << 22) /**< \brief (PIO_ODSR) Output Data Status */
\r
509 #define PIO_ODSR_P23 (0x1u << 23) /**< \brief (PIO_ODSR) Output Data Status */
\r
510 #define PIO_ODSR_P24 (0x1u << 24) /**< \brief (PIO_ODSR) Output Data Status */
\r
511 #define PIO_ODSR_P25 (0x1u << 25) /**< \brief (PIO_ODSR) Output Data Status */
\r
512 #define PIO_ODSR_P26 (0x1u << 26) /**< \brief (PIO_ODSR) Output Data Status */
\r
513 #define PIO_ODSR_P27 (0x1u << 27) /**< \brief (PIO_ODSR) Output Data Status */
\r
514 #define PIO_ODSR_P28 (0x1u << 28) /**< \brief (PIO_ODSR) Output Data Status */
\r
515 #define PIO_ODSR_P29 (0x1u << 29) /**< \brief (PIO_ODSR) Output Data Status */
\r
516 #define PIO_ODSR_P30 (0x1u << 30) /**< \brief (PIO_ODSR) Output Data Status */
\r
517 #define PIO_ODSR_P31 (0x1u << 31) /**< \brief (PIO_ODSR) Output Data Status */
\r
518 /* -------- PIO_PDSR : (PIO Offset: 0x003C) Pin Data Status Register -------- */
\r
519 #define PIO_PDSR_P0 (0x1u << 0) /**< \brief (PIO_PDSR) Output Data Status */
\r
520 #define PIO_PDSR_P1 (0x1u << 1) /**< \brief (PIO_PDSR) Output Data Status */
\r
521 #define PIO_PDSR_P2 (0x1u << 2) /**< \brief (PIO_PDSR) Output Data Status */
\r
522 #define PIO_PDSR_P3 (0x1u << 3) /**< \brief (PIO_PDSR) Output Data Status */
\r
523 #define PIO_PDSR_P4 (0x1u << 4) /**< \brief (PIO_PDSR) Output Data Status */
\r
524 #define PIO_PDSR_P5 (0x1u << 5) /**< \brief (PIO_PDSR) Output Data Status */
\r
525 #define PIO_PDSR_P6 (0x1u << 6) /**< \brief (PIO_PDSR) Output Data Status */
\r
526 #define PIO_PDSR_P7 (0x1u << 7) /**< \brief (PIO_PDSR) Output Data Status */
\r
527 #define PIO_PDSR_P8 (0x1u << 8) /**< \brief (PIO_PDSR) Output Data Status */
\r
528 #define PIO_PDSR_P9 (0x1u << 9) /**< \brief (PIO_PDSR) Output Data Status */
\r
529 #define PIO_PDSR_P10 (0x1u << 10) /**< \brief (PIO_PDSR) Output Data Status */
\r
530 #define PIO_PDSR_P11 (0x1u << 11) /**< \brief (PIO_PDSR) Output Data Status */
\r
531 #define PIO_PDSR_P12 (0x1u << 12) /**< \brief (PIO_PDSR) Output Data Status */
\r
532 #define PIO_PDSR_P13 (0x1u << 13) /**< \brief (PIO_PDSR) Output Data Status */
\r
533 #define PIO_PDSR_P14 (0x1u << 14) /**< \brief (PIO_PDSR) Output Data Status */
\r
534 #define PIO_PDSR_P15 (0x1u << 15) /**< \brief (PIO_PDSR) Output Data Status */
\r
535 #define PIO_PDSR_P16 (0x1u << 16) /**< \brief (PIO_PDSR) Output Data Status */
\r
536 #define PIO_PDSR_P17 (0x1u << 17) /**< \brief (PIO_PDSR) Output Data Status */
\r
537 #define PIO_PDSR_P18 (0x1u << 18) /**< \brief (PIO_PDSR) Output Data Status */
\r
538 #define PIO_PDSR_P19 (0x1u << 19) /**< \brief (PIO_PDSR) Output Data Status */
\r
539 #define PIO_PDSR_P20 (0x1u << 20) /**< \brief (PIO_PDSR) Output Data Status */
\r
540 #define PIO_PDSR_P21 (0x1u << 21) /**< \brief (PIO_PDSR) Output Data Status */
\r
541 #define PIO_PDSR_P22 (0x1u << 22) /**< \brief (PIO_PDSR) Output Data Status */
\r
542 #define PIO_PDSR_P23 (0x1u << 23) /**< \brief (PIO_PDSR) Output Data Status */
\r
543 #define PIO_PDSR_P24 (0x1u << 24) /**< \brief (PIO_PDSR) Output Data Status */
\r
544 #define PIO_PDSR_P25 (0x1u << 25) /**< \brief (PIO_PDSR) Output Data Status */
\r
545 #define PIO_PDSR_P26 (0x1u << 26) /**< \brief (PIO_PDSR) Output Data Status */
\r
546 #define PIO_PDSR_P27 (0x1u << 27) /**< \brief (PIO_PDSR) Output Data Status */
\r
547 #define PIO_PDSR_P28 (0x1u << 28) /**< \brief (PIO_PDSR) Output Data Status */
\r
548 #define PIO_PDSR_P29 (0x1u << 29) /**< \brief (PIO_PDSR) Output Data Status */
\r
549 #define PIO_PDSR_P30 (0x1u << 30) /**< \brief (PIO_PDSR) Output Data Status */
\r
550 #define PIO_PDSR_P31 (0x1u << 31) /**< \brief (PIO_PDSR) Output Data Status */
\r
551 /* -------- PIO_IER : (PIO Offset: 0x0040) Interrupt Enable Register -------- */
\r
552 #define PIO_IER_P0 (0x1u << 0) /**< \brief (PIO_IER) Input Change Interrupt Enable */
\r
553 #define PIO_IER_P1 (0x1u << 1) /**< \brief (PIO_IER) Input Change Interrupt Enable */
\r
554 #define PIO_IER_P2 (0x1u << 2) /**< \brief (PIO_IER) Input Change Interrupt Enable */
\r
555 #define PIO_IER_P3 (0x1u << 3) /**< \brief (PIO_IER) Input Change Interrupt Enable */
\r
556 #define PIO_IER_P4 (0x1u << 4) /**< \brief (PIO_IER) Input Change Interrupt Enable */
\r
557 #define PIO_IER_P5 (0x1u << 5) /**< \brief (PIO_IER) Input Change Interrupt Enable */
\r
558 #define PIO_IER_P6 (0x1u << 6) /**< \brief (PIO_IER) Input Change Interrupt Enable */
\r
559 #define PIO_IER_P7 (0x1u << 7) /**< \brief (PIO_IER) Input Change Interrupt Enable */
\r
560 #define PIO_IER_P8 (0x1u << 8) /**< \brief (PIO_IER) Input Change Interrupt Enable */
\r
561 #define PIO_IER_P9 (0x1u << 9) /**< \brief (PIO_IER) Input Change Interrupt Enable */
\r
562 #define PIO_IER_P10 (0x1u << 10) /**< \brief (PIO_IER) Input Change Interrupt Enable */
\r
563 #define PIO_IER_P11 (0x1u << 11) /**< \brief (PIO_IER) Input Change Interrupt Enable */
\r
564 #define PIO_IER_P12 (0x1u << 12) /**< \brief (PIO_IER) Input Change Interrupt Enable */
\r
565 #define PIO_IER_P13 (0x1u << 13) /**< \brief (PIO_IER) Input Change Interrupt Enable */
\r
566 #define PIO_IER_P14 (0x1u << 14) /**< \brief (PIO_IER) Input Change Interrupt Enable */
\r
567 #define PIO_IER_P15 (0x1u << 15) /**< \brief (PIO_IER) Input Change Interrupt Enable */
\r
568 #define PIO_IER_P16 (0x1u << 16) /**< \brief (PIO_IER) Input Change Interrupt Enable */
\r
569 #define PIO_IER_P17 (0x1u << 17) /**< \brief (PIO_IER) Input Change Interrupt Enable */
\r
570 #define PIO_IER_P18 (0x1u << 18) /**< \brief (PIO_IER) Input Change Interrupt Enable */
\r
571 #define PIO_IER_P19 (0x1u << 19) /**< \brief (PIO_IER) Input Change Interrupt Enable */
\r
572 #define PIO_IER_P20 (0x1u << 20) /**< \brief (PIO_IER) Input Change Interrupt Enable */
\r
573 #define PIO_IER_P21 (0x1u << 21) /**< \brief (PIO_IER) Input Change Interrupt Enable */
\r
574 #define PIO_IER_P22 (0x1u << 22) /**< \brief (PIO_IER) Input Change Interrupt Enable */
\r
575 #define PIO_IER_P23 (0x1u << 23) /**< \brief (PIO_IER) Input Change Interrupt Enable */
\r
576 #define PIO_IER_P24 (0x1u << 24) /**< \brief (PIO_IER) Input Change Interrupt Enable */
\r
577 #define PIO_IER_P25 (0x1u << 25) /**< \brief (PIO_IER) Input Change Interrupt Enable */
\r
578 #define PIO_IER_P26 (0x1u << 26) /**< \brief (PIO_IER) Input Change Interrupt Enable */
\r
579 #define PIO_IER_P27 (0x1u << 27) /**< \brief (PIO_IER) Input Change Interrupt Enable */
\r
580 #define PIO_IER_P28 (0x1u << 28) /**< \brief (PIO_IER) Input Change Interrupt Enable */
\r
581 #define PIO_IER_P29 (0x1u << 29) /**< \brief (PIO_IER) Input Change Interrupt Enable */
\r
582 #define PIO_IER_P30 (0x1u << 30) /**< \brief (PIO_IER) Input Change Interrupt Enable */
\r
583 #define PIO_IER_P31 (0x1u << 31) /**< \brief (PIO_IER) Input Change Interrupt Enable */
\r
584 /* -------- PIO_IDR : (PIO Offset: 0x0044) Interrupt Disable Register -------- */
\r
585 #define PIO_IDR_P0 (0x1u << 0) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
\r
586 #define PIO_IDR_P1 (0x1u << 1) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
\r
587 #define PIO_IDR_P2 (0x1u << 2) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
\r
588 #define PIO_IDR_P3 (0x1u << 3) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
\r
589 #define PIO_IDR_P4 (0x1u << 4) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
\r
590 #define PIO_IDR_P5 (0x1u << 5) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
\r
591 #define PIO_IDR_P6 (0x1u << 6) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
\r
592 #define PIO_IDR_P7 (0x1u << 7) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
\r
593 #define PIO_IDR_P8 (0x1u << 8) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
\r
594 #define PIO_IDR_P9 (0x1u << 9) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
\r
595 #define PIO_IDR_P10 (0x1u << 10) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
\r
596 #define PIO_IDR_P11 (0x1u << 11) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
\r
597 #define PIO_IDR_P12 (0x1u << 12) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
\r
598 #define PIO_IDR_P13 (0x1u << 13) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
\r
599 #define PIO_IDR_P14 (0x1u << 14) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
\r
600 #define PIO_IDR_P15 (0x1u << 15) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
\r
601 #define PIO_IDR_P16 (0x1u << 16) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
\r
602 #define PIO_IDR_P17 (0x1u << 17) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
\r
603 #define PIO_IDR_P18 (0x1u << 18) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
\r
604 #define PIO_IDR_P19 (0x1u << 19) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
\r
605 #define PIO_IDR_P20 (0x1u << 20) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
\r
606 #define PIO_IDR_P21 (0x1u << 21) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
\r
607 #define PIO_IDR_P22 (0x1u << 22) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
\r
608 #define PIO_IDR_P23 (0x1u << 23) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
\r
609 #define PIO_IDR_P24 (0x1u << 24) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
\r
610 #define PIO_IDR_P25 (0x1u << 25) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
\r
611 #define PIO_IDR_P26 (0x1u << 26) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
\r
612 #define PIO_IDR_P27 (0x1u << 27) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
\r
613 #define PIO_IDR_P28 (0x1u << 28) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
\r
614 #define PIO_IDR_P29 (0x1u << 29) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
\r
615 #define PIO_IDR_P30 (0x1u << 30) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
\r
616 #define PIO_IDR_P31 (0x1u << 31) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
\r
617 /* -------- PIO_IMR : (PIO Offset: 0x0048) Interrupt Mask Register -------- */
\r
618 #define PIO_IMR_P0 (0x1u << 0) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
\r
619 #define PIO_IMR_P1 (0x1u << 1) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
\r
620 #define PIO_IMR_P2 (0x1u << 2) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
\r
621 #define PIO_IMR_P3 (0x1u << 3) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
\r
622 #define PIO_IMR_P4 (0x1u << 4) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
\r
623 #define PIO_IMR_P5 (0x1u << 5) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
\r
624 #define PIO_IMR_P6 (0x1u << 6) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
\r
625 #define PIO_IMR_P7 (0x1u << 7) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
\r
626 #define PIO_IMR_P8 (0x1u << 8) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
\r
627 #define PIO_IMR_P9 (0x1u << 9) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
\r
628 #define PIO_IMR_P10 (0x1u << 10) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
\r
629 #define PIO_IMR_P11 (0x1u << 11) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
\r
630 #define PIO_IMR_P12 (0x1u << 12) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
\r
631 #define PIO_IMR_P13 (0x1u << 13) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
\r
632 #define PIO_IMR_P14 (0x1u << 14) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
\r
633 #define PIO_IMR_P15 (0x1u << 15) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
\r
634 #define PIO_IMR_P16 (0x1u << 16) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
\r
635 #define PIO_IMR_P17 (0x1u << 17) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
\r
636 #define PIO_IMR_P18 (0x1u << 18) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
\r
637 #define PIO_IMR_P19 (0x1u << 19) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
\r
638 #define PIO_IMR_P20 (0x1u << 20) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
\r
639 #define PIO_IMR_P21 (0x1u << 21) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
\r
640 #define PIO_IMR_P22 (0x1u << 22) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
\r
641 #define PIO_IMR_P23 (0x1u << 23) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
\r
642 #define PIO_IMR_P24 (0x1u << 24) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
\r
643 #define PIO_IMR_P25 (0x1u << 25) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
\r
644 #define PIO_IMR_P26 (0x1u << 26) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
\r
645 #define PIO_IMR_P27 (0x1u << 27) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
\r
646 #define PIO_IMR_P28 (0x1u << 28) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
\r
647 #define PIO_IMR_P29 (0x1u << 29) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
\r
648 #define PIO_IMR_P30 (0x1u << 30) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
\r
649 #define PIO_IMR_P31 (0x1u << 31) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
\r
650 /* -------- PIO_ISR : (PIO Offset: 0x004C) Interrupt Status Register -------- */
\r
651 #define PIO_ISR_P0 (0x1u << 0) /**< \brief (PIO_ISR) Input Change Interrupt Status */
\r
652 #define PIO_ISR_P1 (0x1u << 1) /**< \brief (PIO_ISR) Input Change Interrupt Status */
\r
653 #define PIO_ISR_P2 (0x1u << 2) /**< \brief (PIO_ISR) Input Change Interrupt Status */
\r
654 #define PIO_ISR_P3 (0x1u << 3) /**< \brief (PIO_ISR) Input Change Interrupt Status */
\r
655 #define PIO_ISR_P4 (0x1u << 4) /**< \brief (PIO_ISR) Input Change Interrupt Status */
\r
656 #define PIO_ISR_P5 (0x1u << 5) /**< \brief (PIO_ISR) Input Change Interrupt Status */
\r
657 #define PIO_ISR_P6 (0x1u << 6) /**< \brief (PIO_ISR) Input Change Interrupt Status */
\r
658 #define PIO_ISR_P7 (0x1u << 7) /**< \brief (PIO_ISR) Input Change Interrupt Status */
\r
659 #define PIO_ISR_P8 (0x1u << 8) /**< \brief (PIO_ISR) Input Change Interrupt Status */
\r
660 #define PIO_ISR_P9 (0x1u << 9) /**< \brief (PIO_ISR) Input Change Interrupt Status */
\r
661 #define PIO_ISR_P10 (0x1u << 10) /**< \brief (PIO_ISR) Input Change Interrupt Status */
\r
662 #define PIO_ISR_P11 (0x1u << 11) /**< \brief (PIO_ISR) Input Change Interrupt Status */
\r
663 #define PIO_ISR_P12 (0x1u << 12) /**< \brief (PIO_ISR) Input Change Interrupt Status */
\r
664 #define PIO_ISR_P13 (0x1u << 13) /**< \brief (PIO_ISR) Input Change Interrupt Status */
\r
665 #define PIO_ISR_P14 (0x1u << 14) /**< \brief (PIO_ISR) Input Change Interrupt Status */
\r
666 #define PIO_ISR_P15 (0x1u << 15) /**< \brief (PIO_ISR) Input Change Interrupt Status */
\r
667 #define PIO_ISR_P16 (0x1u << 16) /**< \brief (PIO_ISR) Input Change Interrupt Status */
\r
668 #define PIO_ISR_P17 (0x1u << 17) /**< \brief (PIO_ISR) Input Change Interrupt Status */
\r
669 #define PIO_ISR_P18 (0x1u << 18) /**< \brief (PIO_ISR) Input Change Interrupt Status */
\r
670 #define PIO_ISR_P19 (0x1u << 19) /**< \brief (PIO_ISR) Input Change Interrupt Status */
\r
671 #define PIO_ISR_P20 (0x1u << 20) /**< \brief (PIO_ISR) Input Change Interrupt Status */
\r
672 #define PIO_ISR_P21 (0x1u << 21) /**< \brief (PIO_ISR) Input Change Interrupt Status */
\r
673 #define PIO_ISR_P22 (0x1u << 22) /**< \brief (PIO_ISR) Input Change Interrupt Status */
\r
674 #define PIO_ISR_P23 (0x1u << 23) /**< \brief (PIO_ISR) Input Change Interrupt Status */
\r
675 #define PIO_ISR_P24 (0x1u << 24) /**< \brief (PIO_ISR) Input Change Interrupt Status */
\r
676 #define PIO_ISR_P25 (0x1u << 25) /**< \brief (PIO_ISR) Input Change Interrupt Status */
\r
677 #define PIO_ISR_P26 (0x1u << 26) /**< \brief (PIO_ISR) Input Change Interrupt Status */
\r
678 #define PIO_ISR_P27 (0x1u << 27) /**< \brief (PIO_ISR) Input Change Interrupt Status */
\r
679 #define PIO_ISR_P28 (0x1u << 28) /**< \brief (PIO_ISR) Input Change Interrupt Status */
\r
680 #define PIO_ISR_P29 (0x1u << 29) /**< \brief (PIO_ISR) Input Change Interrupt Status */
\r
681 #define PIO_ISR_P30 (0x1u << 30) /**< \brief (PIO_ISR) Input Change Interrupt Status */
\r
682 #define PIO_ISR_P31 (0x1u << 31) /**< \brief (PIO_ISR) Input Change Interrupt Status */
\r
683 /* -------- PIO_MDER : (PIO Offset: 0x0050) Multi-driver Enable Register -------- */
\r
684 #define PIO_MDER_P0 (0x1u << 0) /**< \brief (PIO_MDER) Multi-Drive Enable */
\r
685 #define PIO_MDER_P1 (0x1u << 1) /**< \brief (PIO_MDER) Multi-Drive Enable */
\r
686 #define PIO_MDER_P2 (0x1u << 2) /**< \brief (PIO_MDER) Multi-Drive Enable */
\r
687 #define PIO_MDER_P3 (0x1u << 3) /**< \brief (PIO_MDER) Multi-Drive Enable */
\r
688 #define PIO_MDER_P4 (0x1u << 4) /**< \brief (PIO_MDER) Multi-Drive Enable */
\r
689 #define PIO_MDER_P5 (0x1u << 5) /**< \brief (PIO_MDER) Multi-Drive Enable */
\r
690 #define PIO_MDER_P6 (0x1u << 6) /**< \brief (PIO_MDER) Multi-Drive Enable */
\r
691 #define PIO_MDER_P7 (0x1u << 7) /**< \brief (PIO_MDER) Multi-Drive Enable */
\r
692 #define PIO_MDER_P8 (0x1u << 8) /**< \brief (PIO_MDER) Multi-Drive Enable */
\r
693 #define PIO_MDER_P9 (0x1u << 9) /**< \brief (PIO_MDER) Multi-Drive Enable */
\r
694 #define PIO_MDER_P10 (0x1u << 10) /**< \brief (PIO_MDER) Multi-Drive Enable */
\r
695 #define PIO_MDER_P11 (0x1u << 11) /**< \brief (PIO_MDER) Multi-Drive Enable */
\r
696 #define PIO_MDER_P12 (0x1u << 12) /**< \brief (PIO_MDER) Multi-Drive Enable */
\r
697 #define PIO_MDER_P13 (0x1u << 13) /**< \brief (PIO_MDER) Multi-Drive Enable */
\r
698 #define PIO_MDER_P14 (0x1u << 14) /**< \brief (PIO_MDER) Multi-Drive Enable */
\r
699 #define PIO_MDER_P15 (0x1u << 15) /**< \brief (PIO_MDER) Multi-Drive Enable */
\r
700 #define PIO_MDER_P16 (0x1u << 16) /**< \brief (PIO_MDER) Multi-Drive Enable */
\r
701 #define PIO_MDER_P17 (0x1u << 17) /**< \brief (PIO_MDER) Multi-Drive Enable */
\r
702 #define PIO_MDER_P18 (0x1u << 18) /**< \brief (PIO_MDER) Multi-Drive Enable */
\r
703 #define PIO_MDER_P19 (0x1u << 19) /**< \brief (PIO_MDER) Multi-Drive Enable */
\r
704 #define PIO_MDER_P20 (0x1u << 20) /**< \brief (PIO_MDER) Multi-Drive Enable */
\r
705 #define PIO_MDER_P21 (0x1u << 21) /**< \brief (PIO_MDER) Multi-Drive Enable */
\r
706 #define PIO_MDER_P22 (0x1u << 22) /**< \brief (PIO_MDER) Multi-Drive Enable */
\r
707 #define PIO_MDER_P23 (0x1u << 23) /**< \brief (PIO_MDER) Multi-Drive Enable */
\r
708 #define PIO_MDER_P24 (0x1u << 24) /**< \brief (PIO_MDER) Multi-Drive Enable */
\r
709 #define PIO_MDER_P25 (0x1u << 25) /**< \brief (PIO_MDER) Multi-Drive Enable */
\r
710 #define PIO_MDER_P26 (0x1u << 26) /**< \brief (PIO_MDER) Multi-Drive Enable */
\r
711 #define PIO_MDER_P27 (0x1u << 27) /**< \brief (PIO_MDER) Multi-Drive Enable */
\r
712 #define PIO_MDER_P28 (0x1u << 28) /**< \brief (PIO_MDER) Multi-Drive Enable */
\r
713 #define PIO_MDER_P29 (0x1u << 29) /**< \brief (PIO_MDER) Multi-Drive Enable */
\r
714 #define PIO_MDER_P30 (0x1u << 30) /**< \brief (PIO_MDER) Multi-Drive Enable */
\r
715 #define PIO_MDER_P31 (0x1u << 31) /**< \brief (PIO_MDER) Multi-Drive Enable */
\r
716 /* -------- PIO_MDDR : (PIO Offset: 0x0054) Multi-driver Disable Register -------- */
\r
717 #define PIO_MDDR_P0 (0x1u << 0) /**< \brief (PIO_MDDR) Multi-Drive Disable */
\r
718 #define PIO_MDDR_P1 (0x1u << 1) /**< \brief (PIO_MDDR) Multi-Drive Disable */
\r
719 #define PIO_MDDR_P2 (0x1u << 2) /**< \brief (PIO_MDDR) Multi-Drive Disable */
\r
720 #define PIO_MDDR_P3 (0x1u << 3) /**< \brief (PIO_MDDR) Multi-Drive Disable */
\r
721 #define PIO_MDDR_P4 (0x1u << 4) /**< \brief (PIO_MDDR) Multi-Drive Disable */
\r
722 #define PIO_MDDR_P5 (0x1u << 5) /**< \brief (PIO_MDDR) Multi-Drive Disable */
\r
723 #define PIO_MDDR_P6 (0x1u << 6) /**< \brief (PIO_MDDR) Multi-Drive Disable */
\r
724 #define PIO_MDDR_P7 (0x1u << 7) /**< \brief (PIO_MDDR) Multi-Drive Disable */
\r
725 #define PIO_MDDR_P8 (0x1u << 8) /**< \brief (PIO_MDDR) Multi-Drive Disable */
\r
726 #define PIO_MDDR_P9 (0x1u << 9) /**< \brief (PIO_MDDR) Multi-Drive Disable */
\r
727 #define PIO_MDDR_P10 (0x1u << 10) /**< \brief (PIO_MDDR) Multi-Drive Disable */
\r
728 #define PIO_MDDR_P11 (0x1u << 11) /**< \brief (PIO_MDDR) Multi-Drive Disable */
\r
729 #define PIO_MDDR_P12 (0x1u << 12) /**< \brief (PIO_MDDR) Multi-Drive Disable */
\r
730 #define PIO_MDDR_P13 (0x1u << 13) /**< \brief (PIO_MDDR) Multi-Drive Disable */
\r
731 #define PIO_MDDR_P14 (0x1u << 14) /**< \brief (PIO_MDDR) Multi-Drive Disable */
\r
732 #define PIO_MDDR_P15 (0x1u << 15) /**< \brief (PIO_MDDR) Multi-Drive Disable */
\r
733 #define PIO_MDDR_P16 (0x1u << 16) /**< \brief (PIO_MDDR) Multi-Drive Disable */
\r
734 #define PIO_MDDR_P17 (0x1u << 17) /**< \brief (PIO_MDDR) Multi-Drive Disable */
\r
735 #define PIO_MDDR_P18 (0x1u << 18) /**< \brief (PIO_MDDR) Multi-Drive Disable */
\r
736 #define PIO_MDDR_P19 (0x1u << 19) /**< \brief (PIO_MDDR) Multi-Drive Disable */
\r
737 #define PIO_MDDR_P20 (0x1u << 20) /**< \brief (PIO_MDDR) Multi-Drive Disable */
\r
738 #define PIO_MDDR_P21 (0x1u << 21) /**< \brief (PIO_MDDR) Multi-Drive Disable */
\r
739 #define PIO_MDDR_P22 (0x1u << 22) /**< \brief (PIO_MDDR) Multi-Drive Disable */
\r
740 #define PIO_MDDR_P23 (0x1u << 23) /**< \brief (PIO_MDDR) Multi-Drive Disable */
\r
741 #define PIO_MDDR_P24 (0x1u << 24) /**< \brief (PIO_MDDR) Multi-Drive Disable */
\r
742 #define PIO_MDDR_P25 (0x1u << 25) /**< \brief (PIO_MDDR) Multi-Drive Disable */
\r
743 #define PIO_MDDR_P26 (0x1u << 26) /**< \brief (PIO_MDDR) Multi-Drive Disable */
\r
744 #define PIO_MDDR_P27 (0x1u << 27) /**< \brief (PIO_MDDR) Multi-Drive Disable */
\r
745 #define PIO_MDDR_P28 (0x1u << 28) /**< \brief (PIO_MDDR) Multi-Drive Disable */
\r
746 #define PIO_MDDR_P29 (0x1u << 29) /**< \brief (PIO_MDDR) Multi-Drive Disable */
\r
747 #define PIO_MDDR_P30 (0x1u << 30) /**< \brief (PIO_MDDR) Multi-Drive Disable */
\r
748 #define PIO_MDDR_P31 (0x1u << 31) /**< \brief (PIO_MDDR) Multi-Drive Disable */
\r
749 /* -------- PIO_MDSR : (PIO Offset: 0x0058) Multi-driver Status Register -------- */
\r
750 #define PIO_MDSR_P0 (0x1u << 0) /**< \brief (PIO_MDSR) Multi-Drive Status */
\r
751 #define PIO_MDSR_P1 (0x1u << 1) /**< \brief (PIO_MDSR) Multi-Drive Status */
\r
752 #define PIO_MDSR_P2 (0x1u << 2) /**< \brief (PIO_MDSR) Multi-Drive Status */
\r
753 #define PIO_MDSR_P3 (0x1u << 3) /**< \brief (PIO_MDSR) Multi-Drive Status */
\r
754 #define PIO_MDSR_P4 (0x1u << 4) /**< \brief (PIO_MDSR) Multi-Drive Status */
\r
755 #define PIO_MDSR_P5 (0x1u << 5) /**< \brief (PIO_MDSR) Multi-Drive Status */
\r
756 #define PIO_MDSR_P6 (0x1u << 6) /**< \brief (PIO_MDSR) Multi-Drive Status */
\r
757 #define PIO_MDSR_P7 (0x1u << 7) /**< \brief (PIO_MDSR) Multi-Drive Status */
\r
758 #define PIO_MDSR_P8 (0x1u << 8) /**< \brief (PIO_MDSR) Multi-Drive Status */
\r
759 #define PIO_MDSR_P9 (0x1u << 9) /**< \brief (PIO_MDSR) Multi-Drive Status */
\r
760 #define PIO_MDSR_P10 (0x1u << 10) /**< \brief (PIO_MDSR) Multi-Drive Status */
\r
761 #define PIO_MDSR_P11 (0x1u << 11) /**< \brief (PIO_MDSR) Multi-Drive Status */
\r
762 #define PIO_MDSR_P12 (0x1u << 12) /**< \brief (PIO_MDSR) Multi-Drive Status */
\r
763 #define PIO_MDSR_P13 (0x1u << 13) /**< \brief (PIO_MDSR) Multi-Drive Status */
\r
764 #define PIO_MDSR_P14 (0x1u << 14) /**< \brief (PIO_MDSR) Multi-Drive Status */
\r
765 #define PIO_MDSR_P15 (0x1u << 15) /**< \brief (PIO_MDSR) Multi-Drive Status */
\r
766 #define PIO_MDSR_P16 (0x1u << 16) /**< \brief (PIO_MDSR) Multi-Drive Status */
\r
767 #define PIO_MDSR_P17 (0x1u << 17) /**< \brief (PIO_MDSR) Multi-Drive Status */
\r
768 #define PIO_MDSR_P18 (0x1u << 18) /**< \brief (PIO_MDSR) Multi-Drive Status */
\r
769 #define PIO_MDSR_P19 (0x1u << 19) /**< \brief (PIO_MDSR) Multi-Drive Status */
\r
770 #define PIO_MDSR_P20 (0x1u << 20) /**< \brief (PIO_MDSR) Multi-Drive Status */
\r
771 #define PIO_MDSR_P21 (0x1u << 21) /**< \brief (PIO_MDSR) Multi-Drive Status */
\r
772 #define PIO_MDSR_P22 (0x1u << 22) /**< \brief (PIO_MDSR) Multi-Drive Status */
\r
773 #define PIO_MDSR_P23 (0x1u << 23) /**< \brief (PIO_MDSR) Multi-Drive Status */
\r
774 #define PIO_MDSR_P24 (0x1u << 24) /**< \brief (PIO_MDSR) Multi-Drive Status */
\r
775 #define PIO_MDSR_P25 (0x1u << 25) /**< \brief (PIO_MDSR) Multi-Drive Status */
\r
776 #define PIO_MDSR_P26 (0x1u << 26) /**< \brief (PIO_MDSR) Multi-Drive Status */
\r
777 #define PIO_MDSR_P27 (0x1u << 27) /**< \brief (PIO_MDSR) Multi-Drive Status */
\r
778 #define PIO_MDSR_P28 (0x1u << 28) /**< \brief (PIO_MDSR) Multi-Drive Status */
\r
779 #define PIO_MDSR_P29 (0x1u << 29) /**< \brief (PIO_MDSR) Multi-Drive Status */
\r
780 #define PIO_MDSR_P30 (0x1u << 30) /**< \brief (PIO_MDSR) Multi-Drive Status */
\r
781 #define PIO_MDSR_P31 (0x1u << 31) /**< \brief (PIO_MDSR) Multi-Drive Status */
\r
782 /* -------- PIO_PUDR : (PIO Offset: 0x0060) Pull-up Disable Register -------- */
\r
783 #define PIO_PUDR_P0 (0x1u << 0) /**< \brief (PIO_PUDR) Pull-Up Disable */
\r
784 #define PIO_PUDR_P1 (0x1u << 1) /**< \brief (PIO_PUDR) Pull-Up Disable */
\r
785 #define PIO_PUDR_P2 (0x1u << 2) /**< \brief (PIO_PUDR) Pull-Up Disable */
\r
786 #define PIO_PUDR_P3 (0x1u << 3) /**< \brief (PIO_PUDR) Pull-Up Disable */
\r
787 #define PIO_PUDR_P4 (0x1u << 4) /**< \brief (PIO_PUDR) Pull-Up Disable */
\r
788 #define PIO_PUDR_P5 (0x1u << 5) /**< \brief (PIO_PUDR) Pull-Up Disable */
\r
789 #define PIO_PUDR_P6 (0x1u << 6) /**< \brief (PIO_PUDR) Pull-Up Disable */
\r
790 #define PIO_PUDR_P7 (0x1u << 7) /**< \brief (PIO_PUDR) Pull-Up Disable */
\r
791 #define PIO_PUDR_P8 (0x1u << 8) /**< \brief (PIO_PUDR) Pull-Up Disable */
\r
792 #define PIO_PUDR_P9 (0x1u << 9) /**< \brief (PIO_PUDR) Pull-Up Disable */
\r
793 #define PIO_PUDR_P10 (0x1u << 10) /**< \brief (PIO_PUDR) Pull-Up Disable */
\r
794 #define PIO_PUDR_P11 (0x1u << 11) /**< \brief (PIO_PUDR) Pull-Up Disable */
\r
795 #define PIO_PUDR_P12 (0x1u << 12) /**< \brief (PIO_PUDR) Pull-Up Disable */
\r
796 #define PIO_PUDR_P13 (0x1u << 13) /**< \brief (PIO_PUDR) Pull-Up Disable */
\r
797 #define PIO_PUDR_P14 (0x1u << 14) /**< \brief (PIO_PUDR) Pull-Up Disable */
\r
798 #define PIO_PUDR_P15 (0x1u << 15) /**< \brief (PIO_PUDR) Pull-Up Disable */
\r
799 #define PIO_PUDR_P16 (0x1u << 16) /**< \brief (PIO_PUDR) Pull-Up Disable */
\r
800 #define PIO_PUDR_P17 (0x1u << 17) /**< \brief (PIO_PUDR) Pull-Up Disable */
\r
801 #define PIO_PUDR_P18 (0x1u << 18) /**< \brief (PIO_PUDR) Pull-Up Disable */
\r
802 #define PIO_PUDR_P19 (0x1u << 19) /**< \brief (PIO_PUDR) Pull-Up Disable */
\r
803 #define PIO_PUDR_P20 (0x1u << 20) /**< \brief (PIO_PUDR) Pull-Up Disable */
\r
804 #define PIO_PUDR_P21 (0x1u << 21) /**< \brief (PIO_PUDR) Pull-Up Disable */
\r
805 #define PIO_PUDR_P22 (0x1u << 22) /**< \brief (PIO_PUDR) Pull-Up Disable */
\r
806 #define PIO_PUDR_P23 (0x1u << 23) /**< \brief (PIO_PUDR) Pull-Up Disable */
\r
807 #define PIO_PUDR_P24 (0x1u << 24) /**< \brief (PIO_PUDR) Pull-Up Disable */
\r
808 #define PIO_PUDR_P25 (0x1u << 25) /**< \brief (PIO_PUDR) Pull-Up Disable */
\r
809 #define PIO_PUDR_P26 (0x1u << 26) /**< \brief (PIO_PUDR) Pull-Up Disable */
\r
810 #define PIO_PUDR_P27 (0x1u << 27) /**< \brief (PIO_PUDR) Pull-Up Disable */
\r
811 #define PIO_PUDR_P28 (0x1u << 28) /**< \brief (PIO_PUDR) Pull-Up Disable */
\r
812 #define PIO_PUDR_P29 (0x1u << 29) /**< \brief (PIO_PUDR) Pull-Up Disable */
\r
813 #define PIO_PUDR_P30 (0x1u << 30) /**< \brief (PIO_PUDR) Pull-Up Disable */
\r
814 #define PIO_PUDR_P31 (0x1u << 31) /**< \brief (PIO_PUDR) Pull-Up Disable */
\r
815 /* -------- PIO_PUER : (PIO Offset: 0x0064) Pull-up Enable Register -------- */
\r
816 #define PIO_PUER_P0 (0x1u << 0) /**< \brief (PIO_PUER) Pull-Up Enable */
\r
817 #define PIO_PUER_P1 (0x1u << 1) /**< \brief (PIO_PUER) Pull-Up Enable */
\r
818 #define PIO_PUER_P2 (0x1u << 2) /**< \brief (PIO_PUER) Pull-Up Enable */
\r
819 #define PIO_PUER_P3 (0x1u << 3) /**< \brief (PIO_PUER) Pull-Up Enable */
\r
820 #define PIO_PUER_P4 (0x1u << 4) /**< \brief (PIO_PUER) Pull-Up Enable */
\r
821 #define PIO_PUER_P5 (0x1u << 5) /**< \brief (PIO_PUER) Pull-Up Enable */
\r
822 #define PIO_PUER_P6 (0x1u << 6) /**< \brief (PIO_PUER) Pull-Up Enable */
\r
823 #define PIO_PUER_P7 (0x1u << 7) /**< \brief (PIO_PUER) Pull-Up Enable */
\r
824 #define PIO_PUER_P8 (0x1u << 8) /**< \brief (PIO_PUER) Pull-Up Enable */
\r
825 #define PIO_PUER_P9 (0x1u << 9) /**< \brief (PIO_PUER) Pull-Up Enable */
\r
826 #define PIO_PUER_P10 (0x1u << 10) /**< \brief (PIO_PUER) Pull-Up Enable */
\r
827 #define PIO_PUER_P11 (0x1u << 11) /**< \brief (PIO_PUER) Pull-Up Enable */
\r
828 #define PIO_PUER_P12 (0x1u << 12) /**< \brief (PIO_PUER) Pull-Up Enable */
\r
829 #define PIO_PUER_P13 (0x1u << 13) /**< \brief (PIO_PUER) Pull-Up Enable */
\r
830 #define PIO_PUER_P14 (0x1u << 14) /**< \brief (PIO_PUER) Pull-Up Enable */
\r
831 #define PIO_PUER_P15 (0x1u << 15) /**< \brief (PIO_PUER) Pull-Up Enable */
\r
832 #define PIO_PUER_P16 (0x1u << 16) /**< \brief (PIO_PUER) Pull-Up Enable */
\r
833 #define PIO_PUER_P17 (0x1u << 17) /**< \brief (PIO_PUER) Pull-Up Enable */
\r
834 #define PIO_PUER_P18 (0x1u << 18) /**< \brief (PIO_PUER) Pull-Up Enable */
\r
835 #define PIO_PUER_P19 (0x1u << 19) /**< \brief (PIO_PUER) Pull-Up Enable */
\r
836 #define PIO_PUER_P20 (0x1u << 20) /**< \brief (PIO_PUER) Pull-Up Enable */
\r
837 #define PIO_PUER_P21 (0x1u << 21) /**< \brief (PIO_PUER) Pull-Up Enable */
\r
838 #define PIO_PUER_P22 (0x1u << 22) /**< \brief (PIO_PUER) Pull-Up Enable */
\r
839 #define PIO_PUER_P23 (0x1u << 23) /**< \brief (PIO_PUER) Pull-Up Enable */
\r
840 #define PIO_PUER_P24 (0x1u << 24) /**< \brief (PIO_PUER) Pull-Up Enable */
\r
841 #define PIO_PUER_P25 (0x1u << 25) /**< \brief (PIO_PUER) Pull-Up Enable */
\r
842 #define PIO_PUER_P26 (0x1u << 26) /**< \brief (PIO_PUER) Pull-Up Enable */
\r
843 #define PIO_PUER_P27 (0x1u << 27) /**< \brief (PIO_PUER) Pull-Up Enable */
\r
844 #define PIO_PUER_P28 (0x1u << 28) /**< \brief (PIO_PUER) Pull-Up Enable */
\r
845 #define PIO_PUER_P29 (0x1u << 29) /**< \brief (PIO_PUER) Pull-Up Enable */
\r
846 #define PIO_PUER_P30 (0x1u << 30) /**< \brief (PIO_PUER) Pull-Up Enable */
\r
847 #define PIO_PUER_P31 (0x1u << 31) /**< \brief (PIO_PUER) Pull-Up Enable */
\r
848 /* -------- PIO_PUSR : (PIO Offset: 0x0068) Pad Pull-up Status Register -------- */
\r
849 #define PIO_PUSR_P0 (0x1u << 0) /**< \brief (PIO_PUSR) Pull-Up Status */
\r
850 #define PIO_PUSR_P1 (0x1u << 1) /**< \brief (PIO_PUSR) Pull-Up Status */
\r
851 #define PIO_PUSR_P2 (0x1u << 2) /**< \brief (PIO_PUSR) Pull-Up Status */
\r
852 #define PIO_PUSR_P3 (0x1u << 3) /**< \brief (PIO_PUSR) Pull-Up Status */
\r
853 #define PIO_PUSR_P4 (0x1u << 4) /**< \brief (PIO_PUSR) Pull-Up Status */
\r
854 #define PIO_PUSR_P5 (0x1u << 5) /**< \brief (PIO_PUSR) Pull-Up Status */
\r
855 #define PIO_PUSR_P6 (0x1u << 6) /**< \brief (PIO_PUSR) Pull-Up Status */
\r
856 #define PIO_PUSR_P7 (0x1u << 7) /**< \brief (PIO_PUSR) Pull-Up Status */
\r
857 #define PIO_PUSR_P8 (0x1u << 8) /**< \brief (PIO_PUSR) Pull-Up Status */
\r
858 #define PIO_PUSR_P9 (0x1u << 9) /**< \brief (PIO_PUSR) Pull-Up Status */
\r
859 #define PIO_PUSR_P10 (0x1u << 10) /**< \brief (PIO_PUSR) Pull-Up Status */
\r
860 #define PIO_PUSR_P11 (0x1u << 11) /**< \brief (PIO_PUSR) Pull-Up Status */
\r
861 #define PIO_PUSR_P12 (0x1u << 12) /**< \brief (PIO_PUSR) Pull-Up Status */
\r
862 #define PIO_PUSR_P13 (0x1u << 13) /**< \brief (PIO_PUSR) Pull-Up Status */
\r
863 #define PIO_PUSR_P14 (0x1u << 14) /**< \brief (PIO_PUSR) Pull-Up Status */
\r
864 #define PIO_PUSR_P15 (0x1u << 15) /**< \brief (PIO_PUSR) Pull-Up Status */
\r
865 #define PIO_PUSR_P16 (0x1u << 16) /**< \brief (PIO_PUSR) Pull-Up Status */
\r
866 #define PIO_PUSR_P17 (0x1u << 17) /**< \brief (PIO_PUSR) Pull-Up Status */
\r
867 #define PIO_PUSR_P18 (0x1u << 18) /**< \brief (PIO_PUSR) Pull-Up Status */
\r
868 #define PIO_PUSR_P19 (0x1u << 19) /**< \brief (PIO_PUSR) Pull-Up Status */
\r
869 #define PIO_PUSR_P20 (0x1u << 20) /**< \brief (PIO_PUSR) Pull-Up Status */
\r
870 #define PIO_PUSR_P21 (0x1u << 21) /**< \brief (PIO_PUSR) Pull-Up Status */
\r
871 #define PIO_PUSR_P22 (0x1u << 22) /**< \brief (PIO_PUSR) Pull-Up Status */
\r
872 #define PIO_PUSR_P23 (0x1u << 23) /**< \brief (PIO_PUSR) Pull-Up Status */
\r
873 #define PIO_PUSR_P24 (0x1u << 24) /**< \brief (PIO_PUSR) Pull-Up Status */
\r
874 #define PIO_PUSR_P25 (0x1u << 25) /**< \brief (PIO_PUSR) Pull-Up Status */
\r
875 #define PIO_PUSR_P26 (0x1u << 26) /**< \brief (PIO_PUSR) Pull-Up Status */
\r
876 #define PIO_PUSR_P27 (0x1u << 27) /**< \brief (PIO_PUSR) Pull-Up Status */
\r
877 #define PIO_PUSR_P28 (0x1u << 28) /**< \brief (PIO_PUSR) Pull-Up Status */
\r
878 #define PIO_PUSR_P29 (0x1u << 29) /**< \brief (PIO_PUSR) Pull-Up Status */
\r
879 #define PIO_PUSR_P30 (0x1u << 30) /**< \brief (PIO_PUSR) Pull-Up Status */
\r
880 #define PIO_PUSR_P31 (0x1u << 31) /**< \brief (PIO_PUSR) Pull-Up Status */
\r
881 /* -------- PIO_ABCDSR[2] : (PIO Offset: 0x0070) Peripheral Select Register -------- */
\r
882 #define PIO_ABCDSR_P0 (0x1u << 0) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */
\r
883 #define PIO_ABCDSR_P1 (0x1u << 1) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */
\r
884 #define PIO_ABCDSR_P2 (0x1u << 2) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */
\r
885 #define PIO_ABCDSR_P3 (0x1u << 3) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */
\r
886 #define PIO_ABCDSR_P4 (0x1u << 4) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */
\r
887 #define PIO_ABCDSR_P5 (0x1u << 5) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */
\r
888 #define PIO_ABCDSR_P6 (0x1u << 6) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */
\r
889 #define PIO_ABCDSR_P7 (0x1u << 7) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */
\r
890 #define PIO_ABCDSR_P8 (0x1u << 8) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */
\r
891 #define PIO_ABCDSR_P9 (0x1u << 9) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */
\r
892 #define PIO_ABCDSR_P10 (0x1u << 10) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */
\r
893 #define PIO_ABCDSR_P11 (0x1u << 11) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */
\r
894 #define PIO_ABCDSR_P12 (0x1u << 12) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */
\r
895 #define PIO_ABCDSR_P13 (0x1u << 13) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */
\r
896 #define PIO_ABCDSR_P14 (0x1u << 14) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */
\r
897 #define PIO_ABCDSR_P15 (0x1u << 15) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */
\r
898 #define PIO_ABCDSR_P16 (0x1u << 16) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */
\r
899 #define PIO_ABCDSR_P17 (0x1u << 17) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */
\r
900 #define PIO_ABCDSR_P18 (0x1u << 18) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */
\r
901 #define PIO_ABCDSR_P19 (0x1u << 19) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */
\r
902 #define PIO_ABCDSR_P20 (0x1u << 20) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */
\r
903 #define PIO_ABCDSR_P21 (0x1u << 21) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */
\r
904 #define PIO_ABCDSR_P22 (0x1u << 22) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */
\r
905 #define PIO_ABCDSR_P23 (0x1u << 23) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */
\r
906 #define PIO_ABCDSR_P24 (0x1u << 24) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */
\r
907 #define PIO_ABCDSR_P25 (0x1u << 25) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */
\r
908 #define PIO_ABCDSR_P26 (0x1u << 26) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */
\r
909 #define PIO_ABCDSR_P27 (0x1u << 27) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */
\r
910 #define PIO_ABCDSR_P28 (0x1u << 28) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */
\r
911 #define PIO_ABCDSR_P29 (0x1u << 29) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */
\r
912 #define PIO_ABCDSR_P30 (0x1u << 30) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */
\r
913 #define PIO_ABCDSR_P31 (0x1u << 31) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */
\r
914 /* -------- PIO_IFSCDR : (PIO Offset: 0x0080) Input Filter Slow Clock Disable Register -------- */
\r
915 #define PIO_IFSCDR_P0 (0x1u << 0) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select */
\r
916 #define PIO_IFSCDR_P1 (0x1u << 1) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select */
\r
917 #define PIO_IFSCDR_P2 (0x1u << 2) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select */
\r
918 #define PIO_IFSCDR_P3 (0x1u << 3) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select */
\r
919 #define PIO_IFSCDR_P4 (0x1u << 4) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select */
\r
920 #define PIO_IFSCDR_P5 (0x1u << 5) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select */
\r
921 #define PIO_IFSCDR_P6 (0x1u << 6) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select */
\r
922 #define PIO_IFSCDR_P7 (0x1u << 7) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select */
\r
923 #define PIO_IFSCDR_P8 (0x1u << 8) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select */
\r
924 #define PIO_IFSCDR_P9 (0x1u << 9) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select */
\r
925 #define PIO_IFSCDR_P10 (0x1u << 10) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select */
\r
926 #define PIO_IFSCDR_P11 (0x1u << 11) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select */
\r
927 #define PIO_IFSCDR_P12 (0x1u << 12) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select */
\r
928 #define PIO_IFSCDR_P13 (0x1u << 13) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select */
\r
929 #define PIO_IFSCDR_P14 (0x1u << 14) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select */
\r
930 #define PIO_IFSCDR_P15 (0x1u << 15) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select */
\r
931 #define PIO_IFSCDR_P16 (0x1u << 16) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select */
\r
932 #define PIO_IFSCDR_P17 (0x1u << 17) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select */
\r
933 #define PIO_IFSCDR_P18 (0x1u << 18) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select */
\r
934 #define PIO_IFSCDR_P19 (0x1u << 19) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select */
\r
935 #define PIO_IFSCDR_P20 (0x1u << 20) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select */
\r
936 #define PIO_IFSCDR_P21 (0x1u << 21) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select */
\r
937 #define PIO_IFSCDR_P22 (0x1u << 22) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select */
\r
938 #define PIO_IFSCDR_P23 (0x1u << 23) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select */
\r
939 #define PIO_IFSCDR_P24 (0x1u << 24) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select */
\r
940 #define PIO_IFSCDR_P25 (0x1u << 25) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select */
\r
941 #define PIO_IFSCDR_P26 (0x1u << 26) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select */
\r
942 #define PIO_IFSCDR_P27 (0x1u << 27) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select */
\r
943 #define PIO_IFSCDR_P28 (0x1u << 28) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select */
\r
944 #define PIO_IFSCDR_P29 (0x1u << 29) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select */
\r
945 #define PIO_IFSCDR_P30 (0x1u << 30) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select */
\r
946 #define PIO_IFSCDR_P31 (0x1u << 31) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select */
\r
947 /* -------- PIO_IFSCER : (PIO Offset: 0x0084) Input Filter Slow Clock Enable Register -------- */
\r
948 #define PIO_IFSCER_P0 (0x1u << 0) /**< \brief (PIO_IFSCER) Debouncing Filtering Select */
\r
949 #define PIO_IFSCER_P1 (0x1u << 1) /**< \brief (PIO_IFSCER) Debouncing Filtering Select */
\r
950 #define PIO_IFSCER_P2 (0x1u << 2) /**< \brief (PIO_IFSCER) Debouncing Filtering Select */
\r
951 #define PIO_IFSCER_P3 (0x1u << 3) /**< \brief (PIO_IFSCER) Debouncing Filtering Select */
\r
952 #define PIO_IFSCER_P4 (0x1u << 4) /**< \brief (PIO_IFSCER) Debouncing Filtering Select */
\r
953 #define PIO_IFSCER_P5 (0x1u << 5) /**< \brief (PIO_IFSCER) Debouncing Filtering Select */
\r
954 #define PIO_IFSCER_P6 (0x1u << 6) /**< \brief (PIO_IFSCER) Debouncing Filtering Select */
\r
955 #define PIO_IFSCER_P7 (0x1u << 7) /**< \brief (PIO_IFSCER) Debouncing Filtering Select */
\r
956 #define PIO_IFSCER_P8 (0x1u << 8) /**< \brief (PIO_IFSCER) Debouncing Filtering Select */
\r
957 #define PIO_IFSCER_P9 (0x1u << 9) /**< \brief (PIO_IFSCER) Debouncing Filtering Select */
\r
958 #define PIO_IFSCER_P10 (0x1u << 10) /**< \brief (PIO_IFSCER) Debouncing Filtering Select */
\r
959 #define PIO_IFSCER_P11 (0x1u << 11) /**< \brief (PIO_IFSCER) Debouncing Filtering Select */
\r
960 #define PIO_IFSCER_P12 (0x1u << 12) /**< \brief (PIO_IFSCER) Debouncing Filtering Select */
\r
961 #define PIO_IFSCER_P13 (0x1u << 13) /**< \brief (PIO_IFSCER) Debouncing Filtering Select */
\r
962 #define PIO_IFSCER_P14 (0x1u << 14) /**< \brief (PIO_IFSCER) Debouncing Filtering Select */
\r
963 #define PIO_IFSCER_P15 (0x1u << 15) /**< \brief (PIO_IFSCER) Debouncing Filtering Select */
\r
964 #define PIO_IFSCER_P16 (0x1u << 16) /**< \brief (PIO_IFSCER) Debouncing Filtering Select */
\r
965 #define PIO_IFSCER_P17 (0x1u << 17) /**< \brief (PIO_IFSCER) Debouncing Filtering Select */
\r
966 #define PIO_IFSCER_P18 (0x1u << 18) /**< \brief (PIO_IFSCER) Debouncing Filtering Select */
\r
967 #define PIO_IFSCER_P19 (0x1u << 19) /**< \brief (PIO_IFSCER) Debouncing Filtering Select */
\r
968 #define PIO_IFSCER_P20 (0x1u << 20) /**< \brief (PIO_IFSCER) Debouncing Filtering Select */
\r
969 #define PIO_IFSCER_P21 (0x1u << 21) /**< \brief (PIO_IFSCER) Debouncing Filtering Select */
\r
970 #define PIO_IFSCER_P22 (0x1u << 22) /**< \brief (PIO_IFSCER) Debouncing Filtering Select */
\r
971 #define PIO_IFSCER_P23 (0x1u << 23) /**< \brief (PIO_IFSCER) Debouncing Filtering Select */
\r
972 #define PIO_IFSCER_P24 (0x1u << 24) /**< \brief (PIO_IFSCER) Debouncing Filtering Select */
\r
973 #define PIO_IFSCER_P25 (0x1u << 25) /**< \brief (PIO_IFSCER) Debouncing Filtering Select */
\r
974 #define PIO_IFSCER_P26 (0x1u << 26) /**< \brief (PIO_IFSCER) Debouncing Filtering Select */
\r
975 #define PIO_IFSCER_P27 (0x1u << 27) /**< \brief (PIO_IFSCER) Debouncing Filtering Select */
\r
976 #define PIO_IFSCER_P28 (0x1u << 28) /**< \brief (PIO_IFSCER) Debouncing Filtering Select */
\r
977 #define PIO_IFSCER_P29 (0x1u << 29) /**< \brief (PIO_IFSCER) Debouncing Filtering Select */
\r
978 #define PIO_IFSCER_P30 (0x1u << 30) /**< \brief (PIO_IFSCER) Debouncing Filtering Select */
\r
979 #define PIO_IFSCER_P31 (0x1u << 31) /**< \brief (PIO_IFSCER) Debouncing Filtering Select */
\r
980 /* -------- PIO_IFSCSR : (PIO Offset: 0x0088) Input Filter Slow Clock Status Register -------- */
\r
981 #define PIO_IFSCSR_P0 (0x1u << 0) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
\r
982 #define PIO_IFSCSR_P1 (0x1u << 1) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
\r
983 #define PIO_IFSCSR_P2 (0x1u << 2) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
\r
984 #define PIO_IFSCSR_P3 (0x1u << 3) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
\r
985 #define PIO_IFSCSR_P4 (0x1u << 4) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
\r
986 #define PIO_IFSCSR_P5 (0x1u << 5) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
\r
987 #define PIO_IFSCSR_P6 (0x1u << 6) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
\r
988 #define PIO_IFSCSR_P7 (0x1u << 7) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
\r
989 #define PIO_IFSCSR_P8 (0x1u << 8) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
\r
990 #define PIO_IFSCSR_P9 (0x1u << 9) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
\r
991 #define PIO_IFSCSR_P10 (0x1u << 10) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
\r
992 #define PIO_IFSCSR_P11 (0x1u << 11) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
\r
993 #define PIO_IFSCSR_P12 (0x1u << 12) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
\r
994 #define PIO_IFSCSR_P13 (0x1u << 13) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
\r
995 #define PIO_IFSCSR_P14 (0x1u << 14) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
\r
996 #define PIO_IFSCSR_P15 (0x1u << 15) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
\r
997 #define PIO_IFSCSR_P16 (0x1u << 16) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
\r
998 #define PIO_IFSCSR_P17 (0x1u << 17) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
\r
999 #define PIO_IFSCSR_P18 (0x1u << 18) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
\r
1000 #define PIO_IFSCSR_P19 (0x1u << 19) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
\r
1001 #define PIO_IFSCSR_P20 (0x1u << 20) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
\r
1002 #define PIO_IFSCSR_P21 (0x1u << 21) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
\r
1003 #define PIO_IFSCSR_P22 (0x1u << 22) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
\r
1004 #define PIO_IFSCSR_P23 (0x1u << 23) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
\r
1005 #define PIO_IFSCSR_P24 (0x1u << 24) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
\r
1006 #define PIO_IFSCSR_P25 (0x1u << 25) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
\r
1007 #define PIO_IFSCSR_P26 (0x1u << 26) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
\r
1008 #define PIO_IFSCSR_P27 (0x1u << 27) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
\r
1009 #define PIO_IFSCSR_P28 (0x1u << 28) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
\r
1010 #define PIO_IFSCSR_P29 (0x1u << 29) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
\r
1011 #define PIO_IFSCSR_P30 (0x1u << 30) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
\r
1012 #define PIO_IFSCSR_P31 (0x1u << 31) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
\r
1013 /* -------- PIO_SCDR : (PIO Offset: 0x008C) Slow Clock Divider Debouncing Register -------- */
\r
1014 #define PIO_SCDR_DIV_Pos 0
\r
1015 #define PIO_SCDR_DIV_Msk (0x3fffu << PIO_SCDR_DIV_Pos) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */
\r
1016 #define PIO_SCDR_DIV(value) ((PIO_SCDR_DIV_Msk & ((value) << PIO_SCDR_DIV_Pos)))
\r
1017 /* -------- PIO_PPDDR : (PIO Offset: 0x0090) Pad Pull-down Disable Register -------- */
\r
1018 #define PIO_PPDDR_P0 (0x1u << 0) /**< \brief (PIO_PPDDR) Pull-Down Disable */
\r
1019 #define PIO_PPDDR_P1 (0x1u << 1) /**< \brief (PIO_PPDDR) Pull-Down Disable */
\r
1020 #define PIO_PPDDR_P2 (0x1u << 2) /**< \brief (PIO_PPDDR) Pull-Down Disable */
\r
1021 #define PIO_PPDDR_P3 (0x1u << 3) /**< \brief (PIO_PPDDR) Pull-Down Disable */
\r
1022 #define PIO_PPDDR_P4 (0x1u << 4) /**< \brief (PIO_PPDDR) Pull-Down Disable */
\r
1023 #define PIO_PPDDR_P5 (0x1u << 5) /**< \brief (PIO_PPDDR) Pull-Down Disable */
\r
1024 #define PIO_PPDDR_P6 (0x1u << 6) /**< \brief (PIO_PPDDR) Pull-Down Disable */
\r
1025 #define PIO_PPDDR_P7 (0x1u << 7) /**< \brief (PIO_PPDDR) Pull-Down Disable */
\r
1026 #define PIO_PPDDR_P8 (0x1u << 8) /**< \brief (PIO_PPDDR) Pull-Down Disable */
\r
1027 #define PIO_PPDDR_P9 (0x1u << 9) /**< \brief (PIO_PPDDR) Pull-Down Disable */
\r
1028 #define PIO_PPDDR_P10 (0x1u << 10) /**< \brief (PIO_PPDDR) Pull-Down Disable */
\r
1029 #define PIO_PPDDR_P11 (0x1u << 11) /**< \brief (PIO_PPDDR) Pull-Down Disable */
\r
1030 #define PIO_PPDDR_P12 (0x1u << 12) /**< \brief (PIO_PPDDR) Pull-Down Disable */
\r
1031 #define PIO_PPDDR_P13 (0x1u << 13) /**< \brief (PIO_PPDDR) Pull-Down Disable */
\r
1032 #define PIO_PPDDR_P14 (0x1u << 14) /**< \brief (PIO_PPDDR) Pull-Down Disable */
\r
1033 #define PIO_PPDDR_P15 (0x1u << 15) /**< \brief (PIO_PPDDR) Pull-Down Disable */
\r
1034 #define PIO_PPDDR_P16 (0x1u << 16) /**< \brief (PIO_PPDDR) Pull-Down Disable */
\r
1035 #define PIO_PPDDR_P17 (0x1u << 17) /**< \brief (PIO_PPDDR) Pull-Down Disable */
\r
1036 #define PIO_PPDDR_P18 (0x1u << 18) /**< \brief (PIO_PPDDR) Pull-Down Disable */
\r
1037 #define PIO_PPDDR_P19 (0x1u << 19) /**< \brief (PIO_PPDDR) Pull-Down Disable */
\r
1038 #define PIO_PPDDR_P20 (0x1u << 20) /**< \brief (PIO_PPDDR) Pull-Down Disable */
\r
1039 #define PIO_PPDDR_P21 (0x1u << 21) /**< \brief (PIO_PPDDR) Pull-Down Disable */
\r
1040 #define PIO_PPDDR_P22 (0x1u << 22) /**< \brief (PIO_PPDDR) Pull-Down Disable */
\r
1041 #define PIO_PPDDR_P23 (0x1u << 23) /**< \brief (PIO_PPDDR) Pull-Down Disable */
\r
1042 #define PIO_PPDDR_P24 (0x1u << 24) /**< \brief (PIO_PPDDR) Pull-Down Disable */
\r
1043 #define PIO_PPDDR_P25 (0x1u << 25) /**< \brief (PIO_PPDDR) Pull-Down Disable */
\r
1044 #define PIO_PPDDR_P26 (0x1u << 26) /**< \brief (PIO_PPDDR) Pull-Down Disable */
\r
1045 #define PIO_PPDDR_P27 (0x1u << 27) /**< \brief (PIO_PPDDR) Pull-Down Disable */
\r
1046 #define PIO_PPDDR_P28 (0x1u << 28) /**< \brief (PIO_PPDDR) Pull-Down Disable */
\r
1047 #define PIO_PPDDR_P29 (0x1u << 29) /**< \brief (PIO_PPDDR) Pull-Down Disable */
\r
1048 #define PIO_PPDDR_P30 (0x1u << 30) /**< \brief (PIO_PPDDR) Pull-Down Disable */
\r
1049 #define PIO_PPDDR_P31 (0x1u << 31) /**< \brief (PIO_PPDDR) Pull-Down Disable */
\r
1050 /* -------- PIO_PPDER : (PIO Offset: 0x0094) Pad Pull-down Enable Register -------- */
\r
1051 #define PIO_PPDER_P0 (0x1u << 0) /**< \brief (PIO_PPDER) Pull-Down Enable */
\r
1052 #define PIO_PPDER_P1 (0x1u << 1) /**< \brief (PIO_PPDER) Pull-Down Enable */
\r
1053 #define PIO_PPDER_P2 (0x1u << 2) /**< \brief (PIO_PPDER) Pull-Down Enable */
\r
1054 #define PIO_PPDER_P3 (0x1u << 3) /**< \brief (PIO_PPDER) Pull-Down Enable */
\r
1055 #define PIO_PPDER_P4 (0x1u << 4) /**< \brief (PIO_PPDER) Pull-Down Enable */
\r
1056 #define PIO_PPDER_P5 (0x1u << 5) /**< \brief (PIO_PPDER) Pull-Down Enable */
\r
1057 #define PIO_PPDER_P6 (0x1u << 6) /**< \brief (PIO_PPDER) Pull-Down Enable */
\r
1058 #define PIO_PPDER_P7 (0x1u << 7) /**< \brief (PIO_PPDER) Pull-Down Enable */
\r
1059 #define PIO_PPDER_P8 (0x1u << 8) /**< \brief (PIO_PPDER) Pull-Down Enable */
\r
1060 #define PIO_PPDER_P9 (0x1u << 9) /**< \brief (PIO_PPDER) Pull-Down Enable */
\r
1061 #define PIO_PPDER_P10 (0x1u << 10) /**< \brief (PIO_PPDER) Pull-Down Enable */
\r
1062 #define PIO_PPDER_P11 (0x1u << 11) /**< \brief (PIO_PPDER) Pull-Down Enable */
\r
1063 #define PIO_PPDER_P12 (0x1u << 12) /**< \brief (PIO_PPDER) Pull-Down Enable */
\r
1064 #define PIO_PPDER_P13 (0x1u << 13) /**< \brief (PIO_PPDER) Pull-Down Enable */
\r
1065 #define PIO_PPDER_P14 (0x1u << 14) /**< \brief (PIO_PPDER) Pull-Down Enable */
\r
1066 #define PIO_PPDER_P15 (0x1u << 15) /**< \brief (PIO_PPDER) Pull-Down Enable */
\r
1067 #define PIO_PPDER_P16 (0x1u << 16) /**< \brief (PIO_PPDER) Pull-Down Enable */
\r
1068 #define PIO_PPDER_P17 (0x1u << 17) /**< \brief (PIO_PPDER) Pull-Down Enable */
\r
1069 #define PIO_PPDER_P18 (0x1u << 18) /**< \brief (PIO_PPDER) Pull-Down Enable */
\r
1070 #define PIO_PPDER_P19 (0x1u << 19) /**< \brief (PIO_PPDER) Pull-Down Enable */
\r
1071 #define PIO_PPDER_P20 (0x1u << 20) /**< \brief (PIO_PPDER) Pull-Down Enable */
\r
1072 #define PIO_PPDER_P21 (0x1u << 21) /**< \brief (PIO_PPDER) Pull-Down Enable */
\r
1073 #define PIO_PPDER_P22 (0x1u << 22) /**< \brief (PIO_PPDER) Pull-Down Enable */
\r
1074 #define PIO_PPDER_P23 (0x1u << 23) /**< \brief (PIO_PPDER) Pull-Down Enable */
\r
1075 #define PIO_PPDER_P24 (0x1u << 24) /**< \brief (PIO_PPDER) Pull-Down Enable */
\r
1076 #define PIO_PPDER_P25 (0x1u << 25) /**< \brief (PIO_PPDER) Pull-Down Enable */
\r
1077 #define PIO_PPDER_P26 (0x1u << 26) /**< \brief (PIO_PPDER) Pull-Down Enable */
\r
1078 #define PIO_PPDER_P27 (0x1u << 27) /**< \brief (PIO_PPDER) Pull-Down Enable */
\r
1079 #define PIO_PPDER_P28 (0x1u << 28) /**< \brief (PIO_PPDER) Pull-Down Enable */
\r
1080 #define PIO_PPDER_P29 (0x1u << 29) /**< \brief (PIO_PPDER) Pull-Down Enable */
\r
1081 #define PIO_PPDER_P30 (0x1u << 30) /**< \brief (PIO_PPDER) Pull-Down Enable */
\r
1082 #define PIO_PPDER_P31 (0x1u << 31) /**< \brief (PIO_PPDER) Pull-Down Enable */
\r
1083 /* -------- PIO_PPDSR : (PIO Offset: 0x0098) Pad Pull-down Status Register -------- */
\r
1084 #define PIO_PPDSR_P0 (0x1u << 0) /**< \brief (PIO_PPDSR) Pull-Down Status */
\r
1085 #define PIO_PPDSR_P1 (0x1u << 1) /**< \brief (PIO_PPDSR) Pull-Down Status */
\r
1086 #define PIO_PPDSR_P2 (0x1u << 2) /**< \brief (PIO_PPDSR) Pull-Down Status */
\r
1087 #define PIO_PPDSR_P3 (0x1u << 3) /**< \brief (PIO_PPDSR) Pull-Down Status */
\r
1088 #define PIO_PPDSR_P4 (0x1u << 4) /**< \brief (PIO_PPDSR) Pull-Down Status */
\r
1089 #define PIO_PPDSR_P5 (0x1u << 5) /**< \brief (PIO_PPDSR) Pull-Down Status */
\r
1090 #define PIO_PPDSR_P6 (0x1u << 6) /**< \brief (PIO_PPDSR) Pull-Down Status */
\r
1091 #define PIO_PPDSR_P7 (0x1u << 7) /**< \brief (PIO_PPDSR) Pull-Down Status */
\r
1092 #define PIO_PPDSR_P8 (0x1u << 8) /**< \brief (PIO_PPDSR) Pull-Down Status */
\r
1093 #define PIO_PPDSR_P9 (0x1u << 9) /**< \brief (PIO_PPDSR) Pull-Down Status */
\r
1094 #define PIO_PPDSR_P10 (0x1u << 10) /**< \brief (PIO_PPDSR) Pull-Down Status */
\r
1095 #define PIO_PPDSR_P11 (0x1u << 11) /**< \brief (PIO_PPDSR) Pull-Down Status */
\r
1096 #define PIO_PPDSR_P12 (0x1u << 12) /**< \brief (PIO_PPDSR) Pull-Down Status */
\r
1097 #define PIO_PPDSR_P13 (0x1u << 13) /**< \brief (PIO_PPDSR) Pull-Down Status */
\r
1098 #define PIO_PPDSR_P14 (0x1u << 14) /**< \brief (PIO_PPDSR) Pull-Down Status */
\r
1099 #define PIO_PPDSR_P15 (0x1u << 15) /**< \brief (PIO_PPDSR) Pull-Down Status */
\r
1100 #define PIO_PPDSR_P16 (0x1u << 16) /**< \brief (PIO_PPDSR) Pull-Down Status */
\r
1101 #define PIO_PPDSR_P17 (0x1u << 17) /**< \brief (PIO_PPDSR) Pull-Down Status */
\r
1102 #define PIO_PPDSR_P18 (0x1u << 18) /**< \brief (PIO_PPDSR) Pull-Down Status */
\r
1103 #define PIO_PPDSR_P19 (0x1u << 19) /**< \brief (PIO_PPDSR) Pull-Down Status */
\r
1104 #define PIO_PPDSR_P20 (0x1u << 20) /**< \brief (PIO_PPDSR) Pull-Down Status */
\r
1105 #define PIO_PPDSR_P21 (0x1u << 21) /**< \brief (PIO_PPDSR) Pull-Down Status */
\r
1106 #define PIO_PPDSR_P22 (0x1u << 22) /**< \brief (PIO_PPDSR) Pull-Down Status */
\r
1107 #define PIO_PPDSR_P23 (0x1u << 23) /**< \brief (PIO_PPDSR) Pull-Down Status */
\r
1108 #define PIO_PPDSR_P24 (0x1u << 24) /**< \brief (PIO_PPDSR) Pull-Down Status */
\r
1109 #define PIO_PPDSR_P25 (0x1u << 25) /**< \brief (PIO_PPDSR) Pull-Down Status */
\r
1110 #define PIO_PPDSR_P26 (0x1u << 26) /**< \brief (PIO_PPDSR) Pull-Down Status */
\r
1111 #define PIO_PPDSR_P27 (0x1u << 27) /**< \brief (PIO_PPDSR) Pull-Down Status */
\r
1112 #define PIO_PPDSR_P28 (0x1u << 28) /**< \brief (PIO_PPDSR) Pull-Down Status */
\r
1113 #define PIO_PPDSR_P29 (0x1u << 29) /**< \brief (PIO_PPDSR) Pull-Down Status */
\r
1114 #define PIO_PPDSR_P30 (0x1u << 30) /**< \brief (PIO_PPDSR) Pull-Down Status */
\r
1115 #define PIO_PPDSR_P31 (0x1u << 31) /**< \brief (PIO_PPDSR) Pull-Down Status */
\r
1116 /* -------- PIO_OWER : (PIO Offset: 0x00A0) Output Write Enable -------- */
\r
1117 #define PIO_OWER_P0 (0x1u << 0) /**< \brief (PIO_OWER) Output Write Enable */
\r
1118 #define PIO_OWER_P1 (0x1u << 1) /**< \brief (PIO_OWER) Output Write Enable */
\r
1119 #define PIO_OWER_P2 (0x1u << 2) /**< \brief (PIO_OWER) Output Write Enable */
\r
1120 #define PIO_OWER_P3 (0x1u << 3) /**< \brief (PIO_OWER) Output Write Enable */
\r
1121 #define PIO_OWER_P4 (0x1u << 4) /**< \brief (PIO_OWER) Output Write Enable */
\r
1122 #define PIO_OWER_P5 (0x1u << 5) /**< \brief (PIO_OWER) Output Write Enable */
\r
1123 #define PIO_OWER_P6 (0x1u << 6) /**< \brief (PIO_OWER) Output Write Enable */
\r
1124 #define PIO_OWER_P7 (0x1u << 7) /**< \brief (PIO_OWER) Output Write Enable */
\r
1125 #define PIO_OWER_P8 (0x1u << 8) /**< \brief (PIO_OWER) Output Write Enable */
\r
1126 #define PIO_OWER_P9 (0x1u << 9) /**< \brief (PIO_OWER) Output Write Enable */
\r
1127 #define PIO_OWER_P10 (0x1u << 10) /**< \brief (PIO_OWER) Output Write Enable */
\r
1128 #define PIO_OWER_P11 (0x1u << 11) /**< \brief (PIO_OWER) Output Write Enable */
\r
1129 #define PIO_OWER_P12 (0x1u << 12) /**< \brief (PIO_OWER) Output Write Enable */
\r
1130 #define PIO_OWER_P13 (0x1u << 13) /**< \brief (PIO_OWER) Output Write Enable */
\r
1131 #define PIO_OWER_P14 (0x1u << 14) /**< \brief (PIO_OWER) Output Write Enable */
\r
1132 #define PIO_OWER_P15 (0x1u << 15) /**< \brief (PIO_OWER) Output Write Enable */
\r
1133 #define PIO_OWER_P16 (0x1u << 16) /**< \brief (PIO_OWER) Output Write Enable */
\r
1134 #define PIO_OWER_P17 (0x1u << 17) /**< \brief (PIO_OWER) Output Write Enable */
\r
1135 #define PIO_OWER_P18 (0x1u << 18) /**< \brief (PIO_OWER) Output Write Enable */
\r
1136 #define PIO_OWER_P19 (0x1u << 19) /**< \brief (PIO_OWER) Output Write Enable */
\r
1137 #define PIO_OWER_P20 (0x1u << 20) /**< \brief (PIO_OWER) Output Write Enable */
\r
1138 #define PIO_OWER_P21 (0x1u << 21) /**< \brief (PIO_OWER) Output Write Enable */
\r
1139 #define PIO_OWER_P22 (0x1u << 22) /**< \brief (PIO_OWER) Output Write Enable */
\r
1140 #define PIO_OWER_P23 (0x1u << 23) /**< \brief (PIO_OWER) Output Write Enable */
\r
1141 #define PIO_OWER_P24 (0x1u << 24) /**< \brief (PIO_OWER) Output Write Enable */
\r
1142 #define PIO_OWER_P25 (0x1u << 25) /**< \brief (PIO_OWER) Output Write Enable */
\r
1143 #define PIO_OWER_P26 (0x1u << 26) /**< \brief (PIO_OWER) Output Write Enable */
\r
1144 #define PIO_OWER_P27 (0x1u << 27) /**< \brief (PIO_OWER) Output Write Enable */
\r
1145 #define PIO_OWER_P28 (0x1u << 28) /**< \brief (PIO_OWER) Output Write Enable */
\r
1146 #define PIO_OWER_P29 (0x1u << 29) /**< \brief (PIO_OWER) Output Write Enable */
\r
1147 #define PIO_OWER_P30 (0x1u << 30) /**< \brief (PIO_OWER) Output Write Enable */
\r
1148 #define PIO_OWER_P31 (0x1u << 31) /**< \brief (PIO_OWER) Output Write Enable */
\r
1149 /* -------- PIO_OWDR : (PIO Offset: 0x00A4) Output Write Disable -------- */
\r
1150 #define PIO_OWDR_P0 (0x1u << 0) /**< \brief (PIO_OWDR) Output Write Disable */
\r
1151 #define PIO_OWDR_P1 (0x1u << 1) /**< \brief (PIO_OWDR) Output Write Disable */
\r
1152 #define PIO_OWDR_P2 (0x1u << 2) /**< \brief (PIO_OWDR) Output Write Disable */
\r
1153 #define PIO_OWDR_P3 (0x1u << 3) /**< \brief (PIO_OWDR) Output Write Disable */
\r
1154 #define PIO_OWDR_P4 (0x1u << 4) /**< \brief (PIO_OWDR) Output Write Disable */
\r
1155 #define PIO_OWDR_P5 (0x1u << 5) /**< \brief (PIO_OWDR) Output Write Disable */
\r
1156 #define PIO_OWDR_P6 (0x1u << 6) /**< \brief (PIO_OWDR) Output Write Disable */
\r
1157 #define PIO_OWDR_P7 (0x1u << 7) /**< \brief (PIO_OWDR) Output Write Disable */
\r
1158 #define PIO_OWDR_P8 (0x1u << 8) /**< \brief (PIO_OWDR) Output Write Disable */
\r
1159 #define PIO_OWDR_P9 (0x1u << 9) /**< \brief (PIO_OWDR) Output Write Disable */
\r
1160 #define PIO_OWDR_P10 (0x1u << 10) /**< \brief (PIO_OWDR) Output Write Disable */
\r
1161 #define PIO_OWDR_P11 (0x1u << 11) /**< \brief (PIO_OWDR) Output Write Disable */
\r
1162 #define PIO_OWDR_P12 (0x1u << 12) /**< \brief (PIO_OWDR) Output Write Disable */
\r
1163 #define PIO_OWDR_P13 (0x1u << 13) /**< \brief (PIO_OWDR) Output Write Disable */
\r
1164 #define PIO_OWDR_P14 (0x1u << 14) /**< \brief (PIO_OWDR) Output Write Disable */
\r
1165 #define PIO_OWDR_P15 (0x1u << 15) /**< \brief (PIO_OWDR) Output Write Disable */
\r
1166 #define PIO_OWDR_P16 (0x1u << 16) /**< \brief (PIO_OWDR) Output Write Disable */
\r
1167 #define PIO_OWDR_P17 (0x1u << 17) /**< \brief (PIO_OWDR) Output Write Disable */
\r
1168 #define PIO_OWDR_P18 (0x1u << 18) /**< \brief (PIO_OWDR) Output Write Disable */
\r
1169 #define PIO_OWDR_P19 (0x1u << 19) /**< \brief (PIO_OWDR) Output Write Disable */
\r
1170 #define PIO_OWDR_P20 (0x1u << 20) /**< \brief (PIO_OWDR) Output Write Disable */
\r
1171 #define PIO_OWDR_P21 (0x1u << 21) /**< \brief (PIO_OWDR) Output Write Disable */
\r
1172 #define PIO_OWDR_P22 (0x1u << 22) /**< \brief (PIO_OWDR) Output Write Disable */
\r
1173 #define PIO_OWDR_P23 (0x1u << 23) /**< \brief (PIO_OWDR) Output Write Disable */
\r
1174 #define PIO_OWDR_P24 (0x1u << 24) /**< \brief (PIO_OWDR) Output Write Disable */
\r
1175 #define PIO_OWDR_P25 (0x1u << 25) /**< \brief (PIO_OWDR) Output Write Disable */
\r
1176 #define PIO_OWDR_P26 (0x1u << 26) /**< \brief (PIO_OWDR) Output Write Disable */
\r
1177 #define PIO_OWDR_P27 (0x1u << 27) /**< \brief (PIO_OWDR) Output Write Disable */
\r
1178 #define PIO_OWDR_P28 (0x1u << 28) /**< \brief (PIO_OWDR) Output Write Disable */
\r
1179 #define PIO_OWDR_P29 (0x1u << 29) /**< \brief (PIO_OWDR) Output Write Disable */
\r
1180 #define PIO_OWDR_P30 (0x1u << 30) /**< \brief (PIO_OWDR) Output Write Disable */
\r
1181 #define PIO_OWDR_P31 (0x1u << 31) /**< \brief (PIO_OWDR) Output Write Disable */
\r
1182 /* -------- PIO_OWSR : (PIO Offset: 0x00A8) Output Write Status Register -------- */
\r
1183 #define PIO_OWSR_P0 (0x1u << 0) /**< \brief (PIO_OWSR) Output Write Status */
\r
1184 #define PIO_OWSR_P1 (0x1u << 1) /**< \brief (PIO_OWSR) Output Write Status */
\r
1185 #define PIO_OWSR_P2 (0x1u << 2) /**< \brief (PIO_OWSR) Output Write Status */
\r
1186 #define PIO_OWSR_P3 (0x1u << 3) /**< \brief (PIO_OWSR) Output Write Status */
\r
1187 #define PIO_OWSR_P4 (0x1u << 4) /**< \brief (PIO_OWSR) Output Write Status */
\r
1188 #define PIO_OWSR_P5 (0x1u << 5) /**< \brief (PIO_OWSR) Output Write Status */
\r
1189 #define PIO_OWSR_P6 (0x1u << 6) /**< \brief (PIO_OWSR) Output Write Status */
\r
1190 #define PIO_OWSR_P7 (0x1u << 7) /**< \brief (PIO_OWSR) Output Write Status */
\r
1191 #define PIO_OWSR_P8 (0x1u << 8) /**< \brief (PIO_OWSR) Output Write Status */
\r
1192 #define PIO_OWSR_P9 (0x1u << 9) /**< \brief (PIO_OWSR) Output Write Status */
\r
1193 #define PIO_OWSR_P10 (0x1u << 10) /**< \brief (PIO_OWSR) Output Write Status */
\r
1194 #define PIO_OWSR_P11 (0x1u << 11) /**< \brief (PIO_OWSR) Output Write Status */
\r
1195 #define PIO_OWSR_P12 (0x1u << 12) /**< \brief (PIO_OWSR) Output Write Status */
\r
1196 #define PIO_OWSR_P13 (0x1u << 13) /**< \brief (PIO_OWSR) Output Write Status */
\r
1197 #define PIO_OWSR_P14 (0x1u << 14) /**< \brief (PIO_OWSR) Output Write Status */
\r
1198 #define PIO_OWSR_P15 (0x1u << 15) /**< \brief (PIO_OWSR) Output Write Status */
\r
1199 #define PIO_OWSR_P16 (0x1u << 16) /**< \brief (PIO_OWSR) Output Write Status */
\r
1200 #define PIO_OWSR_P17 (0x1u << 17) /**< \brief (PIO_OWSR) Output Write Status */
\r
1201 #define PIO_OWSR_P18 (0x1u << 18) /**< \brief (PIO_OWSR) Output Write Status */
\r
1202 #define PIO_OWSR_P19 (0x1u << 19) /**< \brief (PIO_OWSR) Output Write Status */
\r
1203 #define PIO_OWSR_P20 (0x1u << 20) /**< \brief (PIO_OWSR) Output Write Status */
\r
1204 #define PIO_OWSR_P21 (0x1u << 21) /**< \brief (PIO_OWSR) Output Write Status */
\r
1205 #define PIO_OWSR_P22 (0x1u << 22) /**< \brief (PIO_OWSR) Output Write Status */
\r
1206 #define PIO_OWSR_P23 (0x1u << 23) /**< \brief (PIO_OWSR) Output Write Status */
\r
1207 #define PIO_OWSR_P24 (0x1u << 24) /**< \brief (PIO_OWSR) Output Write Status */
\r
1208 #define PIO_OWSR_P25 (0x1u << 25) /**< \brief (PIO_OWSR) Output Write Status */
\r
1209 #define PIO_OWSR_P26 (0x1u << 26) /**< \brief (PIO_OWSR) Output Write Status */
\r
1210 #define PIO_OWSR_P27 (0x1u << 27) /**< \brief (PIO_OWSR) Output Write Status */
\r
1211 #define PIO_OWSR_P28 (0x1u << 28) /**< \brief (PIO_OWSR) Output Write Status */
\r
1212 #define PIO_OWSR_P29 (0x1u << 29) /**< \brief (PIO_OWSR) Output Write Status */
\r
1213 #define PIO_OWSR_P30 (0x1u << 30) /**< \brief (PIO_OWSR) Output Write Status */
\r
1214 #define PIO_OWSR_P31 (0x1u << 31) /**< \brief (PIO_OWSR) Output Write Status */
\r
1215 /* -------- PIO_AIMER : (PIO Offset: 0x00B0) Additional Interrupt Modes Enable Register -------- */
\r
1216 #define PIO_AIMER_P0 (0x1u << 0) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */
\r
1217 #define PIO_AIMER_P1 (0x1u << 1) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */
\r
1218 #define PIO_AIMER_P2 (0x1u << 2) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */
\r
1219 #define PIO_AIMER_P3 (0x1u << 3) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */
\r
1220 #define PIO_AIMER_P4 (0x1u << 4) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */
\r
1221 #define PIO_AIMER_P5 (0x1u << 5) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */
\r
1222 #define PIO_AIMER_P6 (0x1u << 6) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */
\r
1223 #define PIO_AIMER_P7 (0x1u << 7) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */
\r
1224 #define PIO_AIMER_P8 (0x1u << 8) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */
\r
1225 #define PIO_AIMER_P9 (0x1u << 9) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */
\r
1226 #define PIO_AIMER_P10 (0x1u << 10) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */
\r
1227 #define PIO_AIMER_P11 (0x1u << 11) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */
\r
1228 #define PIO_AIMER_P12 (0x1u << 12) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */
\r
1229 #define PIO_AIMER_P13 (0x1u << 13) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */
\r
1230 #define PIO_AIMER_P14 (0x1u << 14) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */
\r
1231 #define PIO_AIMER_P15 (0x1u << 15) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */
\r
1232 #define PIO_AIMER_P16 (0x1u << 16) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */
\r
1233 #define PIO_AIMER_P17 (0x1u << 17) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */
\r
1234 #define PIO_AIMER_P18 (0x1u << 18) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */
\r
1235 #define PIO_AIMER_P19 (0x1u << 19) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */
\r
1236 #define PIO_AIMER_P20 (0x1u << 20) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */
\r
1237 #define PIO_AIMER_P21 (0x1u << 21) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */
\r
1238 #define PIO_AIMER_P22 (0x1u << 22) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */
\r
1239 #define PIO_AIMER_P23 (0x1u << 23) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */
\r
1240 #define PIO_AIMER_P24 (0x1u << 24) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */
\r
1241 #define PIO_AIMER_P25 (0x1u << 25) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */
\r
1242 #define PIO_AIMER_P26 (0x1u << 26) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */
\r
1243 #define PIO_AIMER_P27 (0x1u << 27) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */
\r
1244 #define PIO_AIMER_P28 (0x1u << 28) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */
\r
1245 #define PIO_AIMER_P29 (0x1u << 29) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */
\r
1246 #define PIO_AIMER_P30 (0x1u << 30) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */
\r
1247 #define PIO_AIMER_P31 (0x1u << 31) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */
\r
1248 /* -------- PIO_AIMDR : (PIO Offset: 0x00B4) Additional Interrupt Modes Disable Register -------- */
\r
1249 #define PIO_AIMDR_P0 (0x1u << 0) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */
\r
1250 #define PIO_AIMDR_P1 (0x1u << 1) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */
\r
1251 #define PIO_AIMDR_P2 (0x1u << 2) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */
\r
1252 #define PIO_AIMDR_P3 (0x1u << 3) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */
\r
1253 #define PIO_AIMDR_P4 (0x1u << 4) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */
\r
1254 #define PIO_AIMDR_P5 (0x1u << 5) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */
\r
1255 #define PIO_AIMDR_P6 (0x1u << 6) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */
\r
1256 #define PIO_AIMDR_P7 (0x1u << 7) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */
\r
1257 #define PIO_AIMDR_P8 (0x1u << 8) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */
\r
1258 #define PIO_AIMDR_P9 (0x1u << 9) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */
\r
1259 #define PIO_AIMDR_P10 (0x1u << 10) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */
\r
1260 #define PIO_AIMDR_P11 (0x1u << 11) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */
\r
1261 #define PIO_AIMDR_P12 (0x1u << 12) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */
\r
1262 #define PIO_AIMDR_P13 (0x1u << 13) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */
\r
1263 #define PIO_AIMDR_P14 (0x1u << 14) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */
\r
1264 #define PIO_AIMDR_P15 (0x1u << 15) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */
\r
1265 #define PIO_AIMDR_P16 (0x1u << 16) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */
\r
1266 #define PIO_AIMDR_P17 (0x1u << 17) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */
\r
1267 #define PIO_AIMDR_P18 (0x1u << 18) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */
\r
1268 #define PIO_AIMDR_P19 (0x1u << 19) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */
\r
1269 #define PIO_AIMDR_P20 (0x1u << 20) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */
\r
1270 #define PIO_AIMDR_P21 (0x1u << 21) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */
\r
1271 #define PIO_AIMDR_P22 (0x1u << 22) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */
\r
1272 #define PIO_AIMDR_P23 (0x1u << 23) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */
\r
1273 #define PIO_AIMDR_P24 (0x1u << 24) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */
\r
1274 #define PIO_AIMDR_P25 (0x1u << 25) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */
\r
1275 #define PIO_AIMDR_P26 (0x1u << 26) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */
\r
1276 #define PIO_AIMDR_P27 (0x1u << 27) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */
\r
1277 #define PIO_AIMDR_P28 (0x1u << 28) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */
\r
1278 #define PIO_AIMDR_P29 (0x1u << 29) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */
\r
1279 #define PIO_AIMDR_P30 (0x1u << 30) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */
\r
1280 #define PIO_AIMDR_P31 (0x1u << 31) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */
\r
1281 /* -------- PIO_AIMMR : (PIO Offset: 0x00B8) Additional Interrupt Modes Mask Register -------- */
\r
1282 #define PIO_AIMMR_P0 (0x1u << 0) /**< \brief (PIO_AIMMR) Peripheral CD Status */
\r
1283 #define PIO_AIMMR_P1 (0x1u << 1) /**< \brief (PIO_AIMMR) Peripheral CD Status */
\r
1284 #define PIO_AIMMR_P2 (0x1u << 2) /**< \brief (PIO_AIMMR) Peripheral CD Status */
\r
1285 #define PIO_AIMMR_P3 (0x1u << 3) /**< \brief (PIO_AIMMR) Peripheral CD Status */
\r
1286 #define PIO_AIMMR_P4 (0x1u << 4) /**< \brief (PIO_AIMMR) Peripheral CD Status */
\r
1287 #define PIO_AIMMR_P5 (0x1u << 5) /**< \brief (PIO_AIMMR) Peripheral CD Status */
\r
1288 #define PIO_AIMMR_P6 (0x1u << 6) /**< \brief (PIO_AIMMR) Peripheral CD Status */
\r
1289 #define PIO_AIMMR_P7 (0x1u << 7) /**< \brief (PIO_AIMMR) Peripheral CD Status */
\r
1290 #define PIO_AIMMR_P8 (0x1u << 8) /**< \brief (PIO_AIMMR) Peripheral CD Status */
\r
1291 #define PIO_AIMMR_P9 (0x1u << 9) /**< \brief (PIO_AIMMR) Peripheral CD Status */
\r
1292 #define PIO_AIMMR_P10 (0x1u << 10) /**< \brief (PIO_AIMMR) Peripheral CD Status */
\r
1293 #define PIO_AIMMR_P11 (0x1u << 11) /**< \brief (PIO_AIMMR) Peripheral CD Status */
\r
1294 #define PIO_AIMMR_P12 (0x1u << 12) /**< \brief (PIO_AIMMR) Peripheral CD Status */
\r
1295 #define PIO_AIMMR_P13 (0x1u << 13) /**< \brief (PIO_AIMMR) Peripheral CD Status */
\r
1296 #define PIO_AIMMR_P14 (0x1u << 14) /**< \brief (PIO_AIMMR) Peripheral CD Status */
\r
1297 #define PIO_AIMMR_P15 (0x1u << 15) /**< \brief (PIO_AIMMR) Peripheral CD Status */
\r
1298 #define PIO_AIMMR_P16 (0x1u << 16) /**< \brief (PIO_AIMMR) Peripheral CD Status */
\r
1299 #define PIO_AIMMR_P17 (0x1u << 17) /**< \brief (PIO_AIMMR) Peripheral CD Status */
\r
1300 #define PIO_AIMMR_P18 (0x1u << 18) /**< \brief (PIO_AIMMR) Peripheral CD Status */
\r
1301 #define PIO_AIMMR_P19 (0x1u << 19) /**< \brief (PIO_AIMMR) Peripheral CD Status */
\r
1302 #define PIO_AIMMR_P20 (0x1u << 20) /**< \brief (PIO_AIMMR) Peripheral CD Status */
\r
1303 #define PIO_AIMMR_P21 (0x1u << 21) /**< \brief (PIO_AIMMR) Peripheral CD Status */
\r
1304 #define PIO_AIMMR_P22 (0x1u << 22) /**< \brief (PIO_AIMMR) Peripheral CD Status */
\r
1305 #define PIO_AIMMR_P23 (0x1u << 23) /**< \brief (PIO_AIMMR) Peripheral CD Status */
\r
1306 #define PIO_AIMMR_P24 (0x1u << 24) /**< \brief (PIO_AIMMR) Peripheral CD Status */
\r
1307 #define PIO_AIMMR_P25 (0x1u << 25) /**< \brief (PIO_AIMMR) Peripheral CD Status */
\r
1308 #define PIO_AIMMR_P26 (0x1u << 26) /**< \brief (PIO_AIMMR) Peripheral CD Status */
\r
1309 #define PIO_AIMMR_P27 (0x1u << 27) /**< \brief (PIO_AIMMR) Peripheral CD Status */
\r
1310 #define PIO_AIMMR_P28 (0x1u << 28) /**< \brief (PIO_AIMMR) Peripheral CD Status */
\r
1311 #define PIO_AIMMR_P29 (0x1u << 29) /**< \brief (PIO_AIMMR) Peripheral CD Status */
\r
1312 #define PIO_AIMMR_P30 (0x1u << 30) /**< \brief (PIO_AIMMR) Peripheral CD Status */
\r
1313 #define PIO_AIMMR_P31 (0x1u << 31) /**< \brief (PIO_AIMMR) Peripheral CD Status */
\r
1314 /* -------- PIO_ESR : (PIO Offset: 0x00C0) Edge Select Register -------- */
\r
1315 #define PIO_ESR_P0 (0x1u << 0) /**< \brief (PIO_ESR) Edge Interrupt Selection */
\r
1316 #define PIO_ESR_P1 (0x1u << 1) /**< \brief (PIO_ESR) Edge Interrupt Selection */
\r
1317 #define PIO_ESR_P2 (0x1u << 2) /**< \brief (PIO_ESR) Edge Interrupt Selection */
\r
1318 #define PIO_ESR_P3 (0x1u << 3) /**< \brief (PIO_ESR) Edge Interrupt Selection */
\r
1319 #define PIO_ESR_P4 (0x1u << 4) /**< \brief (PIO_ESR) Edge Interrupt Selection */
\r
1320 #define PIO_ESR_P5 (0x1u << 5) /**< \brief (PIO_ESR) Edge Interrupt Selection */
\r
1321 #define PIO_ESR_P6 (0x1u << 6) /**< \brief (PIO_ESR) Edge Interrupt Selection */
\r
1322 #define PIO_ESR_P7 (0x1u << 7) /**< \brief (PIO_ESR) Edge Interrupt Selection */
\r
1323 #define PIO_ESR_P8 (0x1u << 8) /**< \brief (PIO_ESR) Edge Interrupt Selection */
\r
1324 #define PIO_ESR_P9 (0x1u << 9) /**< \brief (PIO_ESR) Edge Interrupt Selection */
\r
1325 #define PIO_ESR_P10 (0x1u << 10) /**< \brief (PIO_ESR) Edge Interrupt Selection */
\r
1326 #define PIO_ESR_P11 (0x1u << 11) /**< \brief (PIO_ESR) Edge Interrupt Selection */
\r
1327 #define PIO_ESR_P12 (0x1u << 12) /**< \brief (PIO_ESR) Edge Interrupt Selection */
\r
1328 #define PIO_ESR_P13 (0x1u << 13) /**< \brief (PIO_ESR) Edge Interrupt Selection */
\r
1329 #define PIO_ESR_P14 (0x1u << 14) /**< \brief (PIO_ESR) Edge Interrupt Selection */
\r
1330 #define PIO_ESR_P15 (0x1u << 15) /**< \brief (PIO_ESR) Edge Interrupt Selection */
\r
1331 #define PIO_ESR_P16 (0x1u << 16) /**< \brief (PIO_ESR) Edge Interrupt Selection */
\r
1332 #define PIO_ESR_P17 (0x1u << 17) /**< \brief (PIO_ESR) Edge Interrupt Selection */
\r
1333 #define PIO_ESR_P18 (0x1u << 18) /**< \brief (PIO_ESR) Edge Interrupt Selection */
\r
1334 #define PIO_ESR_P19 (0x1u << 19) /**< \brief (PIO_ESR) Edge Interrupt Selection */
\r
1335 #define PIO_ESR_P20 (0x1u << 20) /**< \brief (PIO_ESR) Edge Interrupt Selection */
\r
1336 #define PIO_ESR_P21 (0x1u << 21) /**< \brief (PIO_ESR) Edge Interrupt Selection */
\r
1337 #define PIO_ESR_P22 (0x1u << 22) /**< \brief (PIO_ESR) Edge Interrupt Selection */
\r
1338 #define PIO_ESR_P23 (0x1u << 23) /**< \brief (PIO_ESR) Edge Interrupt Selection */
\r
1339 #define PIO_ESR_P24 (0x1u << 24) /**< \brief (PIO_ESR) Edge Interrupt Selection */
\r
1340 #define PIO_ESR_P25 (0x1u << 25) /**< \brief (PIO_ESR) Edge Interrupt Selection */
\r
1341 #define PIO_ESR_P26 (0x1u << 26) /**< \brief (PIO_ESR) Edge Interrupt Selection */
\r
1342 #define PIO_ESR_P27 (0x1u << 27) /**< \brief (PIO_ESR) Edge Interrupt Selection */
\r
1343 #define PIO_ESR_P28 (0x1u << 28) /**< \brief (PIO_ESR) Edge Interrupt Selection */
\r
1344 #define PIO_ESR_P29 (0x1u << 29) /**< \brief (PIO_ESR) Edge Interrupt Selection */
\r
1345 #define PIO_ESR_P30 (0x1u << 30) /**< \brief (PIO_ESR) Edge Interrupt Selection */
\r
1346 #define PIO_ESR_P31 (0x1u << 31) /**< \brief (PIO_ESR) Edge Interrupt Selection */
\r
1347 /* -------- PIO_LSR : (PIO Offset: 0x00C4) Level Select Register -------- */
\r
1348 #define PIO_LSR_P0 (0x1u << 0) /**< \brief (PIO_LSR) Level Interrupt Selection */
\r
1349 #define PIO_LSR_P1 (0x1u << 1) /**< \brief (PIO_LSR) Level Interrupt Selection */
\r
1350 #define PIO_LSR_P2 (0x1u << 2) /**< \brief (PIO_LSR) Level Interrupt Selection */
\r
1351 #define PIO_LSR_P3 (0x1u << 3) /**< \brief (PIO_LSR) Level Interrupt Selection */
\r
1352 #define PIO_LSR_P4 (0x1u << 4) /**< \brief (PIO_LSR) Level Interrupt Selection */
\r
1353 #define PIO_LSR_P5 (0x1u << 5) /**< \brief (PIO_LSR) Level Interrupt Selection */
\r
1354 #define PIO_LSR_P6 (0x1u << 6) /**< \brief (PIO_LSR) Level Interrupt Selection */
\r
1355 #define PIO_LSR_P7 (0x1u << 7) /**< \brief (PIO_LSR) Level Interrupt Selection */
\r
1356 #define PIO_LSR_P8 (0x1u << 8) /**< \brief (PIO_LSR) Level Interrupt Selection */
\r
1357 #define PIO_LSR_P9 (0x1u << 9) /**< \brief (PIO_LSR) Level Interrupt Selection */
\r
1358 #define PIO_LSR_P10 (0x1u << 10) /**< \brief (PIO_LSR) Level Interrupt Selection */
\r
1359 #define PIO_LSR_P11 (0x1u << 11) /**< \brief (PIO_LSR) Level Interrupt Selection */
\r
1360 #define PIO_LSR_P12 (0x1u << 12) /**< \brief (PIO_LSR) Level Interrupt Selection */
\r
1361 #define PIO_LSR_P13 (0x1u << 13) /**< \brief (PIO_LSR) Level Interrupt Selection */
\r
1362 #define PIO_LSR_P14 (0x1u << 14) /**< \brief (PIO_LSR) Level Interrupt Selection */
\r
1363 #define PIO_LSR_P15 (0x1u << 15) /**< \brief (PIO_LSR) Level Interrupt Selection */
\r
1364 #define PIO_LSR_P16 (0x1u << 16) /**< \brief (PIO_LSR) Level Interrupt Selection */
\r
1365 #define PIO_LSR_P17 (0x1u << 17) /**< \brief (PIO_LSR) Level Interrupt Selection */
\r
1366 #define PIO_LSR_P18 (0x1u << 18) /**< \brief (PIO_LSR) Level Interrupt Selection */
\r
1367 #define PIO_LSR_P19 (0x1u << 19) /**< \brief (PIO_LSR) Level Interrupt Selection */
\r
1368 #define PIO_LSR_P20 (0x1u << 20) /**< \brief (PIO_LSR) Level Interrupt Selection */
\r
1369 #define PIO_LSR_P21 (0x1u << 21) /**< \brief (PIO_LSR) Level Interrupt Selection */
\r
1370 #define PIO_LSR_P22 (0x1u << 22) /**< \brief (PIO_LSR) Level Interrupt Selection */
\r
1371 #define PIO_LSR_P23 (0x1u << 23) /**< \brief (PIO_LSR) Level Interrupt Selection */
\r
1372 #define PIO_LSR_P24 (0x1u << 24) /**< \brief (PIO_LSR) Level Interrupt Selection */
\r
1373 #define PIO_LSR_P25 (0x1u << 25) /**< \brief (PIO_LSR) Level Interrupt Selection */
\r
1374 #define PIO_LSR_P26 (0x1u << 26) /**< \brief (PIO_LSR) Level Interrupt Selection */
\r
1375 #define PIO_LSR_P27 (0x1u << 27) /**< \brief (PIO_LSR) Level Interrupt Selection */
\r
1376 #define PIO_LSR_P28 (0x1u << 28) /**< \brief (PIO_LSR) Level Interrupt Selection */
\r
1377 #define PIO_LSR_P29 (0x1u << 29) /**< \brief (PIO_LSR) Level Interrupt Selection */
\r
1378 #define PIO_LSR_P30 (0x1u << 30) /**< \brief (PIO_LSR) Level Interrupt Selection */
\r
1379 #define PIO_LSR_P31 (0x1u << 31) /**< \brief (PIO_LSR) Level Interrupt Selection */
\r
1380 /* -------- PIO_ELSR : (PIO Offset: 0x00C8) Edge/Level Status Register -------- */
\r
1381 #define PIO_ELSR_P0 (0x1u << 0) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */
\r
1382 #define PIO_ELSR_P1 (0x1u << 1) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */
\r
1383 #define PIO_ELSR_P2 (0x1u << 2) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */
\r
1384 #define PIO_ELSR_P3 (0x1u << 3) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */
\r
1385 #define PIO_ELSR_P4 (0x1u << 4) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */
\r
1386 #define PIO_ELSR_P5 (0x1u << 5) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */
\r
1387 #define PIO_ELSR_P6 (0x1u << 6) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */
\r
1388 #define PIO_ELSR_P7 (0x1u << 7) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */
\r
1389 #define PIO_ELSR_P8 (0x1u << 8) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */
\r
1390 #define PIO_ELSR_P9 (0x1u << 9) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */
\r
1391 #define PIO_ELSR_P10 (0x1u << 10) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */
\r
1392 #define PIO_ELSR_P11 (0x1u << 11) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */
\r
1393 #define PIO_ELSR_P12 (0x1u << 12) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */
\r
1394 #define PIO_ELSR_P13 (0x1u << 13) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */
\r
1395 #define PIO_ELSR_P14 (0x1u << 14) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */
\r
1396 #define PIO_ELSR_P15 (0x1u << 15) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */
\r
1397 #define PIO_ELSR_P16 (0x1u << 16) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */
\r
1398 #define PIO_ELSR_P17 (0x1u << 17) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */
\r
1399 #define PIO_ELSR_P18 (0x1u << 18) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */
\r
1400 #define PIO_ELSR_P19 (0x1u << 19) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */
\r
1401 #define PIO_ELSR_P20 (0x1u << 20) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */
\r
1402 #define PIO_ELSR_P21 (0x1u << 21) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */
\r
1403 #define PIO_ELSR_P22 (0x1u << 22) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */
\r
1404 #define PIO_ELSR_P23 (0x1u << 23) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */
\r
1405 #define PIO_ELSR_P24 (0x1u << 24) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */
\r
1406 #define PIO_ELSR_P25 (0x1u << 25) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */
\r
1407 #define PIO_ELSR_P26 (0x1u << 26) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */
\r
1408 #define PIO_ELSR_P27 (0x1u << 27) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */
\r
1409 #define PIO_ELSR_P28 (0x1u << 28) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */
\r
1410 #define PIO_ELSR_P29 (0x1u << 29) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */
\r
1411 #define PIO_ELSR_P30 (0x1u << 30) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */
\r
1412 #define PIO_ELSR_P31 (0x1u << 31) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */
\r
1413 /* -------- PIO_FELLSR : (PIO Offset: 0x00D0) Falling Edge/Low-Level Select Register -------- */
\r
1414 #define PIO_FELLSR_P0 (0x1u << 0) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */
\r
1415 #define PIO_FELLSR_P1 (0x1u << 1) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */
\r
1416 #define PIO_FELLSR_P2 (0x1u << 2) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */
\r
1417 #define PIO_FELLSR_P3 (0x1u << 3) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */
\r
1418 #define PIO_FELLSR_P4 (0x1u << 4) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */
\r
1419 #define PIO_FELLSR_P5 (0x1u << 5) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */
\r
1420 #define PIO_FELLSR_P6 (0x1u << 6) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */
\r
1421 #define PIO_FELLSR_P7 (0x1u << 7) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */
\r
1422 #define PIO_FELLSR_P8 (0x1u << 8) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */
\r
1423 #define PIO_FELLSR_P9 (0x1u << 9) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */
\r
1424 #define PIO_FELLSR_P10 (0x1u << 10) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */
\r
1425 #define PIO_FELLSR_P11 (0x1u << 11) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */
\r
1426 #define PIO_FELLSR_P12 (0x1u << 12) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */
\r
1427 #define PIO_FELLSR_P13 (0x1u << 13) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */
\r
1428 #define PIO_FELLSR_P14 (0x1u << 14) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */
\r
1429 #define PIO_FELLSR_P15 (0x1u << 15) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */
\r
1430 #define PIO_FELLSR_P16 (0x1u << 16) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */
\r
1431 #define PIO_FELLSR_P17 (0x1u << 17) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */
\r
1432 #define PIO_FELLSR_P18 (0x1u << 18) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */
\r
1433 #define PIO_FELLSR_P19 (0x1u << 19) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */
\r
1434 #define PIO_FELLSR_P20 (0x1u << 20) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */
\r
1435 #define PIO_FELLSR_P21 (0x1u << 21) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */
\r
1436 #define PIO_FELLSR_P22 (0x1u << 22) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */
\r
1437 #define PIO_FELLSR_P23 (0x1u << 23) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */
\r
1438 #define PIO_FELLSR_P24 (0x1u << 24) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */
\r
1439 #define PIO_FELLSR_P25 (0x1u << 25) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */
\r
1440 #define PIO_FELLSR_P26 (0x1u << 26) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */
\r
1441 #define PIO_FELLSR_P27 (0x1u << 27) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */
\r
1442 #define PIO_FELLSR_P28 (0x1u << 28) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */
\r
1443 #define PIO_FELLSR_P29 (0x1u << 29) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */
\r
1444 #define PIO_FELLSR_P30 (0x1u << 30) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */
\r
1445 #define PIO_FELLSR_P31 (0x1u << 31) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */
\r
1446 /* -------- PIO_REHLSR : (PIO Offset: 0x00D4) Rising Edge/ High-Level Select Register -------- */
\r
1447 #define PIO_REHLSR_P0 (0x1u << 0) /**< \brief (PIO_REHLSR) Rising Edge /High-Level Interrupt Selection */
\r
1448 #define PIO_REHLSR_P1 (0x1u << 1) /**< \brief (PIO_REHLSR) Rising Edge /High-Level Interrupt Selection */
\r
1449 #define PIO_REHLSR_P2 (0x1u << 2) /**< \brief (PIO_REHLSR) Rising Edge /High-Level Interrupt Selection */
\r
1450 #define PIO_REHLSR_P3 (0x1u << 3) /**< \brief (PIO_REHLSR) Rising Edge /High-Level Interrupt Selection */
\r
1451 #define PIO_REHLSR_P4 (0x1u << 4) /**< \brief (PIO_REHLSR) Rising Edge /High-Level Interrupt Selection */
\r
1452 #define PIO_REHLSR_P5 (0x1u << 5) /**< \brief (PIO_REHLSR) Rising Edge /High-Level Interrupt Selection */
\r
1453 #define PIO_REHLSR_P6 (0x1u << 6) /**< \brief (PIO_REHLSR) Rising Edge /High-Level Interrupt Selection */
\r
1454 #define PIO_REHLSR_P7 (0x1u << 7) /**< \brief (PIO_REHLSR) Rising Edge /High-Level Interrupt Selection */
\r
1455 #define PIO_REHLSR_P8 (0x1u << 8) /**< \brief (PIO_REHLSR) Rising Edge /High-Level Interrupt Selection */
\r
1456 #define PIO_REHLSR_P9 (0x1u << 9) /**< \brief (PIO_REHLSR) Rising Edge /High-Level Interrupt Selection */
\r
1457 #define PIO_REHLSR_P10 (0x1u << 10) /**< \brief (PIO_REHLSR) Rising Edge /High-Level Interrupt Selection */
\r
1458 #define PIO_REHLSR_P11 (0x1u << 11) /**< \brief (PIO_REHLSR) Rising Edge /High-Level Interrupt Selection */
\r
1459 #define PIO_REHLSR_P12 (0x1u << 12) /**< \brief (PIO_REHLSR) Rising Edge /High-Level Interrupt Selection */
\r
1460 #define PIO_REHLSR_P13 (0x1u << 13) /**< \brief (PIO_REHLSR) Rising Edge /High-Level Interrupt Selection */
\r
1461 #define PIO_REHLSR_P14 (0x1u << 14) /**< \brief (PIO_REHLSR) Rising Edge /High-Level Interrupt Selection */
\r
1462 #define PIO_REHLSR_P15 (0x1u << 15) /**< \brief (PIO_REHLSR) Rising Edge /High-Level Interrupt Selection */
\r
1463 #define PIO_REHLSR_P16 (0x1u << 16) /**< \brief (PIO_REHLSR) Rising Edge /High-Level Interrupt Selection */
\r
1464 #define PIO_REHLSR_P17 (0x1u << 17) /**< \brief (PIO_REHLSR) Rising Edge /High-Level Interrupt Selection */
\r
1465 #define PIO_REHLSR_P18 (0x1u << 18) /**< \brief (PIO_REHLSR) Rising Edge /High-Level Interrupt Selection */
\r
1466 #define PIO_REHLSR_P19 (0x1u << 19) /**< \brief (PIO_REHLSR) Rising Edge /High-Level Interrupt Selection */
\r
1467 #define PIO_REHLSR_P20 (0x1u << 20) /**< \brief (PIO_REHLSR) Rising Edge /High-Level Interrupt Selection */
\r
1468 #define PIO_REHLSR_P21 (0x1u << 21) /**< \brief (PIO_REHLSR) Rising Edge /High-Level Interrupt Selection */
\r
1469 #define PIO_REHLSR_P22 (0x1u << 22) /**< \brief (PIO_REHLSR) Rising Edge /High-Level Interrupt Selection */
\r
1470 #define PIO_REHLSR_P23 (0x1u << 23) /**< \brief (PIO_REHLSR) Rising Edge /High-Level Interrupt Selection */
\r
1471 #define PIO_REHLSR_P24 (0x1u << 24) /**< \brief (PIO_REHLSR) Rising Edge /High-Level Interrupt Selection */
\r
1472 #define PIO_REHLSR_P25 (0x1u << 25) /**< \brief (PIO_REHLSR) Rising Edge /High-Level Interrupt Selection */
\r
1473 #define PIO_REHLSR_P26 (0x1u << 26) /**< \brief (PIO_REHLSR) Rising Edge /High-Level Interrupt Selection */
\r
1474 #define PIO_REHLSR_P27 (0x1u << 27) /**< \brief (PIO_REHLSR) Rising Edge /High-Level Interrupt Selection */
\r
1475 #define PIO_REHLSR_P28 (0x1u << 28) /**< \brief (PIO_REHLSR) Rising Edge /High-Level Interrupt Selection */
\r
1476 #define PIO_REHLSR_P29 (0x1u << 29) /**< \brief (PIO_REHLSR) Rising Edge /High-Level Interrupt Selection */
\r
1477 #define PIO_REHLSR_P30 (0x1u << 30) /**< \brief (PIO_REHLSR) Rising Edge /High-Level Interrupt Selection */
\r
1478 #define PIO_REHLSR_P31 (0x1u << 31) /**< \brief (PIO_REHLSR) Rising Edge /High-Level Interrupt Selection */
\r
1479 /* -------- PIO_FRLHSR : (PIO Offset: 0x00D8) Fall/Rise - Low/High Status Register -------- */
\r
1480 #define PIO_FRLHSR_P0 (0x1u << 0) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection */
\r
1481 #define PIO_FRLHSR_P1 (0x1u << 1) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection */
\r
1482 #define PIO_FRLHSR_P2 (0x1u << 2) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection */
\r
1483 #define PIO_FRLHSR_P3 (0x1u << 3) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection */
\r
1484 #define PIO_FRLHSR_P4 (0x1u << 4) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection */
\r
1485 #define PIO_FRLHSR_P5 (0x1u << 5) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection */
\r
1486 #define PIO_FRLHSR_P6 (0x1u << 6) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection */
\r
1487 #define PIO_FRLHSR_P7 (0x1u << 7) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection */
\r
1488 #define PIO_FRLHSR_P8 (0x1u << 8) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection */
\r
1489 #define PIO_FRLHSR_P9 (0x1u << 9) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection */
\r
1490 #define PIO_FRLHSR_P10 (0x1u << 10) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection */
\r
1491 #define PIO_FRLHSR_P11 (0x1u << 11) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection */
\r
1492 #define PIO_FRLHSR_P12 (0x1u << 12) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection */
\r
1493 #define PIO_FRLHSR_P13 (0x1u << 13) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection */
\r
1494 #define PIO_FRLHSR_P14 (0x1u << 14) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection */
\r
1495 #define PIO_FRLHSR_P15 (0x1u << 15) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection */
\r
1496 #define PIO_FRLHSR_P16 (0x1u << 16) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection */
\r
1497 #define PIO_FRLHSR_P17 (0x1u << 17) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection */
\r
1498 #define PIO_FRLHSR_P18 (0x1u << 18) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection */
\r
1499 #define PIO_FRLHSR_P19 (0x1u << 19) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection */
\r
1500 #define PIO_FRLHSR_P20 (0x1u << 20) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection */
\r
1501 #define PIO_FRLHSR_P21 (0x1u << 21) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection */
\r
1502 #define PIO_FRLHSR_P22 (0x1u << 22) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection */
\r
1503 #define PIO_FRLHSR_P23 (0x1u << 23) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection */
\r
1504 #define PIO_FRLHSR_P24 (0x1u << 24) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection */
\r
1505 #define PIO_FRLHSR_P25 (0x1u << 25) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection */
\r
1506 #define PIO_FRLHSR_P26 (0x1u << 26) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection */
\r
1507 #define PIO_FRLHSR_P27 (0x1u << 27) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection */
\r
1508 #define PIO_FRLHSR_P28 (0x1u << 28) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection */
\r
1509 #define PIO_FRLHSR_P29 (0x1u << 29) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection */
\r
1510 #define PIO_FRLHSR_P30 (0x1u << 30) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection */
\r
1511 #define PIO_FRLHSR_P31 (0x1u << 31) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection */
\r
1512 /* -------- PIO_LOCKSR : (PIO Offset: 0x00E0) Lock Status -------- */
\r
1513 #define PIO_LOCKSR_P0 (0x1u << 0) /**< \brief (PIO_LOCKSR) Lock Status */
\r
1514 #define PIO_LOCKSR_P1 (0x1u << 1) /**< \brief (PIO_LOCKSR) Lock Status */
\r
1515 #define PIO_LOCKSR_P2 (0x1u << 2) /**< \brief (PIO_LOCKSR) Lock Status */
\r
1516 #define PIO_LOCKSR_P3 (0x1u << 3) /**< \brief (PIO_LOCKSR) Lock Status */
\r
1517 #define PIO_LOCKSR_P4 (0x1u << 4) /**< \brief (PIO_LOCKSR) Lock Status */
\r
1518 #define PIO_LOCKSR_P5 (0x1u << 5) /**< \brief (PIO_LOCKSR) Lock Status */
\r
1519 #define PIO_LOCKSR_P6 (0x1u << 6) /**< \brief (PIO_LOCKSR) Lock Status */
\r
1520 #define PIO_LOCKSR_P7 (0x1u << 7) /**< \brief (PIO_LOCKSR) Lock Status */
\r
1521 #define PIO_LOCKSR_P8 (0x1u << 8) /**< \brief (PIO_LOCKSR) Lock Status */
\r
1522 #define PIO_LOCKSR_P9 (0x1u << 9) /**< \brief (PIO_LOCKSR) Lock Status */
\r
1523 #define PIO_LOCKSR_P10 (0x1u << 10) /**< \brief (PIO_LOCKSR) Lock Status */
\r
1524 #define PIO_LOCKSR_P11 (0x1u << 11) /**< \brief (PIO_LOCKSR) Lock Status */
\r
1525 #define PIO_LOCKSR_P12 (0x1u << 12) /**< \brief (PIO_LOCKSR) Lock Status */
\r
1526 #define PIO_LOCKSR_P13 (0x1u << 13) /**< \brief (PIO_LOCKSR) Lock Status */
\r
1527 #define PIO_LOCKSR_P14 (0x1u << 14) /**< \brief (PIO_LOCKSR) Lock Status */
\r
1528 #define PIO_LOCKSR_P15 (0x1u << 15) /**< \brief (PIO_LOCKSR) Lock Status */
\r
1529 #define PIO_LOCKSR_P16 (0x1u << 16) /**< \brief (PIO_LOCKSR) Lock Status */
\r
1530 #define PIO_LOCKSR_P17 (0x1u << 17) /**< \brief (PIO_LOCKSR) Lock Status */
\r
1531 #define PIO_LOCKSR_P18 (0x1u << 18) /**< \brief (PIO_LOCKSR) Lock Status */
\r
1532 #define PIO_LOCKSR_P19 (0x1u << 19) /**< \brief (PIO_LOCKSR) Lock Status */
\r
1533 #define PIO_LOCKSR_P20 (0x1u << 20) /**< \brief (PIO_LOCKSR) Lock Status */
\r
1534 #define PIO_LOCKSR_P21 (0x1u << 21) /**< \brief (PIO_LOCKSR) Lock Status */
\r
1535 #define PIO_LOCKSR_P22 (0x1u << 22) /**< \brief (PIO_LOCKSR) Lock Status */
\r
1536 #define PIO_LOCKSR_P23 (0x1u << 23) /**< \brief (PIO_LOCKSR) Lock Status */
\r
1537 #define PIO_LOCKSR_P24 (0x1u << 24) /**< \brief (PIO_LOCKSR) Lock Status */
\r
1538 #define PIO_LOCKSR_P25 (0x1u << 25) /**< \brief (PIO_LOCKSR) Lock Status */
\r
1539 #define PIO_LOCKSR_P26 (0x1u << 26) /**< \brief (PIO_LOCKSR) Lock Status */
\r
1540 #define PIO_LOCKSR_P27 (0x1u << 27) /**< \brief (PIO_LOCKSR) Lock Status */
\r
1541 #define PIO_LOCKSR_P28 (0x1u << 28) /**< \brief (PIO_LOCKSR) Lock Status */
\r
1542 #define PIO_LOCKSR_P29 (0x1u << 29) /**< \brief (PIO_LOCKSR) Lock Status */
\r
1543 #define PIO_LOCKSR_P30 (0x1u << 30) /**< \brief (PIO_LOCKSR) Lock Status */
\r
1544 #define PIO_LOCKSR_P31 (0x1u << 31) /**< \brief (PIO_LOCKSR) Lock Status */
\r
1545 /* -------- PIO_WPMR : (PIO Offset: 0x00E4) Write Protection Mode Register -------- */
\r
1546 #define PIO_WPMR_WPEN (0x1u << 0) /**< \brief (PIO_WPMR) Write Protection Enable */
\r
1547 #define PIO_WPMR_WPKEY_Pos 8
\r
1548 #define PIO_WPMR_WPKEY_Msk (0xffffffu << PIO_WPMR_WPKEY_Pos) /**< \brief (PIO_WPMR) Write Protection Key. */
\r
1549 #define PIO_WPMR_WPKEY_PASSWD (0x50494Fu << 8) /**< \brief (PIO_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. */
\r
1550 /* -------- PIO_WPSR : (PIO Offset: 0x00E8) Write Protection Status Register -------- */
\r
1551 #define PIO_WPSR_WPVS (0x1u << 0) /**< \brief (PIO_WPSR) Write Protection Violation Status */
\r
1552 #define PIO_WPSR_WPVSRC_Pos 8
\r
1553 #define PIO_WPSR_WPVSRC_Msk (0xffffu << PIO_WPSR_WPVSRC_Pos) /**< \brief (PIO_WPSR) Write Protection Violation Source */
\r
1554 /* -------- PIO_VERSION : (PIO Offset: 0x00FC) Version Register -------- */
\r
1555 #define PIO_VERSION_VERSION_Pos 0
\r
1556 #define PIO_VERSION_VERSION_Msk (0xfffu << PIO_VERSION_VERSION_Pos) /**< \brief (PIO_VERSION) Hardware Module Version */
\r
1557 #define PIO_VERSION_MFN_Pos 16
\r
1558 #define PIO_VERSION_MFN_Msk (0x7u << PIO_VERSION_MFN_Pos) /**< \brief (PIO_VERSION) Metal Fix Number */
\r
1559 /* -------- PIO_SCHMITT : (PIO Offset: 0x0100) Schmitt Trigger Register -------- */
\r
1560 #define PIO_SCHMITT_SCHMITT0 (0x1u << 0) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */
\r
1561 #define PIO_SCHMITT_SCHMITT1 (0x1u << 1) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */
\r
1562 #define PIO_SCHMITT_SCHMITT2 (0x1u << 2) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */
\r
1563 #define PIO_SCHMITT_SCHMITT3 (0x1u << 3) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */
\r
1564 #define PIO_SCHMITT_SCHMITT4 (0x1u << 4) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */
\r
1565 #define PIO_SCHMITT_SCHMITT5 (0x1u << 5) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */
\r
1566 #define PIO_SCHMITT_SCHMITT6 (0x1u << 6) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */
\r
1567 #define PIO_SCHMITT_SCHMITT7 (0x1u << 7) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */
\r
1568 #define PIO_SCHMITT_SCHMITT8 (0x1u << 8) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */
\r
1569 #define PIO_SCHMITT_SCHMITT9 (0x1u << 9) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */
\r
1570 #define PIO_SCHMITT_SCHMITT10 (0x1u << 10) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */
\r
1571 #define PIO_SCHMITT_SCHMITT11 (0x1u << 11) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */
\r
1572 #define PIO_SCHMITT_SCHMITT12 (0x1u << 12) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */
\r
1573 #define PIO_SCHMITT_SCHMITT13 (0x1u << 13) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */
\r
1574 #define PIO_SCHMITT_SCHMITT14 (0x1u << 14) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */
\r
1575 #define PIO_SCHMITT_SCHMITT15 (0x1u << 15) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */
\r
1576 #define PIO_SCHMITT_SCHMITT16 (0x1u << 16) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */
\r
1577 #define PIO_SCHMITT_SCHMITT17 (0x1u << 17) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */
\r
1578 #define PIO_SCHMITT_SCHMITT18 (0x1u << 18) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */
\r
1579 #define PIO_SCHMITT_SCHMITT19 (0x1u << 19) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */
\r
1580 #define PIO_SCHMITT_SCHMITT20 (0x1u << 20) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */
\r
1581 #define PIO_SCHMITT_SCHMITT21 (0x1u << 21) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */
\r
1582 #define PIO_SCHMITT_SCHMITT22 (0x1u << 22) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */
\r
1583 #define PIO_SCHMITT_SCHMITT23 (0x1u << 23) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */
\r
1584 #define PIO_SCHMITT_SCHMITT24 (0x1u << 24) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */
\r
1585 #define PIO_SCHMITT_SCHMITT25 (0x1u << 25) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */
\r
1586 #define PIO_SCHMITT_SCHMITT26 (0x1u << 26) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */
\r
1587 #define PIO_SCHMITT_SCHMITT27 (0x1u << 27) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */
\r
1588 #define PIO_SCHMITT_SCHMITT28 (0x1u << 28) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */
\r
1589 #define PIO_SCHMITT_SCHMITT29 (0x1u << 29) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */
\r
1590 #define PIO_SCHMITT_SCHMITT30 (0x1u << 30) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */
\r
1591 #define PIO_SCHMITT_SCHMITT31 (0x1u << 31) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */
\r
1592 /* -------- PIO_KER : (PIO Offset: 0x0120) Keypad Controller Enable Register -------- */
\r
1593 #define PIO_KER_KCE (0x1u << 0) /**< \brief (PIO_KER) Keypad Controller Enable */
\r
1594 /* -------- PIO_KRCR : (PIO Offset: 0x0124) Keypad Controller Row Column Register -------- */
\r
1595 #define PIO_KRCR_NBR_Pos 0
\r
1596 #define PIO_KRCR_NBR_Msk (0x7u << PIO_KRCR_NBR_Pos) /**< \brief (PIO_KRCR) Number of Columns of the Keypad Matrix */
\r
1597 #define PIO_KRCR_NBR(value) ((PIO_KRCR_NBR_Msk & ((value) << PIO_KRCR_NBR_Pos)))
\r
1598 #define PIO_KRCR_NBC_Pos 8
\r
1599 #define PIO_KRCR_NBC_Msk (0x7u << PIO_KRCR_NBC_Pos) /**< \brief (PIO_KRCR) Number of Rows of the Keypad Matrix */
\r
1600 #define PIO_KRCR_NBC(value) ((PIO_KRCR_NBC_Msk & ((value) << PIO_KRCR_NBC_Pos)))
\r
1601 /* -------- PIO_KDR : (PIO Offset: 0x0128) Keypad Controller Debouncing Register -------- */
\r
1602 #define PIO_KDR_DBC_Pos 0
\r
1603 #define PIO_KDR_DBC_Msk (0x3ffu << PIO_KDR_DBC_Pos) /**< \brief (PIO_KDR) Debouncing Value */
\r
1604 #define PIO_KDR_DBC(value) ((PIO_KDR_DBC_Msk & ((value) << PIO_KDR_DBC_Pos)))
\r
1605 /* -------- PIO_KIER : (PIO Offset: 0x0130) Keypad Controller Interrupt Enable Register -------- */
\r
1606 #define PIO_KIER_KPR (0x1u << 0) /**< \brief (PIO_KIER) Key Press Interrupt Enable */
\r
1607 #define PIO_KIER_KRL (0x1u << 1) /**< \brief (PIO_KIER) Key Release Interrupt Enable */
\r
1608 /* -------- PIO_KIDR : (PIO Offset: 0x0134) Keypad Controller Interrupt Disable Register -------- */
\r
1609 #define PIO_KIDR_KPR (0x1u << 0) /**< \brief (PIO_KIDR) Key Press Interrupt Disable */
\r
1610 #define PIO_KIDR_KRL (0x1u << 1) /**< \brief (PIO_KIDR) Key Release Interrupt Disable */
\r
1611 /* -------- PIO_KIMR : (PIO Offset: 0x0138) Keypad Controller Interrupt Mask Register -------- */
\r
1612 #define PIO_KIMR_KPR (0x1u << 0) /**< \brief (PIO_KIMR) Key Press Interrupt Mask */
\r
1613 #define PIO_KIMR_KRL (0x1u << 1) /**< \brief (PIO_KIMR) Key Release Interrupt Mask */
\r
1614 /* -------- PIO_KSR : (PIO Offset: 0x013C) Keypad Controller Status Register -------- */
\r
1615 #define PIO_KSR_KPR (0x1u << 0) /**< \brief (PIO_KSR) Key Press Status */
\r
1616 #define PIO_KSR_KRL (0x1u << 1) /**< \brief (PIO_KSR) Key Release Status */
\r
1617 #define PIO_KSR_NBKPR_Pos 8
\r
1618 #define PIO_KSR_NBKPR_Msk (0x3u << PIO_KSR_NBKPR_Pos) /**< \brief (PIO_KSR) Number of Simultaneous Key Presses */
\r
1619 #define PIO_KSR_NBKRL_Pos 16
\r
1620 #define PIO_KSR_NBKRL_Msk (0x3u << PIO_KSR_NBKRL_Pos) /**< \brief (PIO_KSR) Number of Simultaneous Key Releases */
\r
1621 /* -------- PIO_KKPR : (PIO Offset: 0x0140) Keypad Controller Key Press Register -------- */
\r
1622 #define PIO_KKPR_KEY0ROW_Pos 0
\r
1623 #define PIO_KKPR_KEY0ROW_Msk (0x7u << PIO_KKPR_KEY0ROW_Pos) /**< \brief (PIO_KKPR) Row Index of the First Detected Key Press */
\r
1624 #define PIO_KKPR_KEY0COL_Pos 4
\r
1625 #define PIO_KKPR_KEY0COL_Msk (0x7u << PIO_KKPR_KEY0COL_Pos) /**< \brief (PIO_KKPR) Column Index of the First Detected Key Press */
\r
1626 #define PIO_KKPR_KEY1ROW_Pos 8
\r
1627 #define PIO_KKPR_KEY1ROW_Msk (0x7u << PIO_KKPR_KEY1ROW_Pos) /**< \brief (PIO_KKPR) Row Index of the Second Detected Key Press */
\r
1628 #define PIO_KKPR_KEY1COL_Pos 12
\r
1629 #define PIO_KKPR_KEY1COL_Msk (0x7u << PIO_KKPR_KEY1COL_Pos) /**< \brief (PIO_KKPR) Column Index of the Second Detected Key Press */
\r
1630 #define PIO_KKPR_KEY2ROW_Pos 16
\r
1631 #define PIO_KKPR_KEY2ROW_Msk (0x7u << PIO_KKPR_KEY2ROW_Pos) /**< \brief (PIO_KKPR) Row Index of the Third Detected Key Press */
\r
1632 #define PIO_KKPR_KEY2COL_Pos 20
\r
1633 #define PIO_KKPR_KEY2COL_Msk (0x7u << PIO_KKPR_KEY2COL_Pos) /**< \brief (PIO_KKPR) Column Index of the Third Detected Key Press */
\r
1634 #define PIO_KKPR_KEY3ROW_Pos 24
\r
1635 #define PIO_KKPR_KEY3ROW_Msk (0x7u << PIO_KKPR_KEY3ROW_Pos) /**< \brief (PIO_KKPR) Row Index of the Fourth Detected Key Press */
\r
1636 #define PIO_KKPR_KEY3COL_Pos 28
\r
1637 #define PIO_KKPR_KEY3COL_Msk (0x7u << PIO_KKPR_KEY3COL_Pos) /**< \brief (PIO_KKPR) Column Index of the Fourth Detected Key Press */
\r
1638 /* -------- PIO_KKRR : (PIO Offset: 0x0144) Keypad Controller Key Release Register -------- */
\r
1639 #define PIO_KKRR_KEY0ROW_Pos 0
\r
1640 #define PIO_KKRR_KEY0ROW_Msk (0x7u << PIO_KKRR_KEY0ROW_Pos) /**< \brief (PIO_KKRR) Row Index of the First Detected Key Release */
\r
1641 #define PIO_KKRR_KEY0COL_Pos 4
\r
1642 #define PIO_KKRR_KEY0COL_Msk (0x7u << PIO_KKRR_KEY0COL_Pos) /**< \brief (PIO_KKRR) Column Index of the First Detected Key Release */
\r
1643 #define PIO_KKRR_KEY1ROW_Pos 8
\r
1644 #define PIO_KKRR_KEY1ROW_Msk (0x7u << PIO_KKRR_KEY1ROW_Pos) /**< \brief (PIO_KKRR) Row Index of the Second Detected Key Release */
\r
1645 #define PIO_KKRR_KEY1COL_Pos 12
\r
1646 #define PIO_KKRR_KEY1COL_Msk (0x7u << PIO_KKRR_KEY1COL_Pos) /**< \brief (PIO_KKRR) Column Index of the Second Detected Key Release */
\r
1647 #define PIO_KKRR_KEY2ROW_Pos 16
\r
1648 #define PIO_KKRR_KEY2ROW_Msk (0x7u << PIO_KKRR_KEY2ROW_Pos) /**< \brief (PIO_KKRR) Row Index of the Third Detected Key Release */
\r
1649 #define PIO_KKRR_KEY2COL_Pos 20
\r
1650 #define PIO_KKRR_KEY2COL_Msk (0x7u << PIO_KKRR_KEY2COL_Pos) /**< \brief (PIO_KKRR) Column Index of the Third Detected Key Release */
\r
1651 #define PIO_KKRR_KEY3ROW_Pos 24
\r
1652 #define PIO_KKRR_KEY3ROW_Msk (0x7u << PIO_KKRR_KEY3ROW_Pos) /**< \brief (PIO_KKRR) Row Index of the Fourth Detected Key Release */
\r
1653 #define PIO_KKRR_KEY3COL_Pos 28
\r
1654 #define PIO_KKRR_KEY3COL_Msk (0x7u << PIO_KKRR_KEY3COL_Pos) /**< \brief (PIO_KKRR) Column Index of the Fourth Detected Key Release */
\r
1655 /* -------- PIO_PCMR : (PIO Offset: 0x150) Parallel Capture Mode Register -------- */
\r
1656 #define PIO_PCMR_PCEN (0x1u << 0) /**< \brief (PIO_PCMR) Parallel Capture Mode Enable */
\r
1657 #define PIO_PCMR_DSIZE_Pos 4
\r
1658 #define PIO_PCMR_DSIZE_Msk (0x3u << PIO_PCMR_DSIZE_Pos) /**< \brief (PIO_PCMR) Parallel Capture Mode Data Size */
\r
1659 #define PIO_PCMR_DSIZE_BYTE (0x0u << 4) /**< \brief (PIO_PCMR) The reception data in the PIO_PCRHR is a byte (8-bit) */
\r
1660 #define PIO_PCMR_DSIZE_HALFWORD (0x1u << 4) /**< \brief (PIO_PCMR) The reception data in the PIO_PCRHR is a half-word (16-bit) */
\r
1661 #define PIO_PCMR_DSIZE_WORD (0x2u << 4) /**< \brief (PIO_PCMR) The reception data in the PIO_PCRHR is a word (32-bit) */
\r
1662 #define PIO_PCMR_ALWYS (0x1u << 9) /**< \brief (PIO_PCMR) Parallel Capture Mode Always Sampling */
\r
1663 #define PIO_PCMR_HALFS (0x1u << 10) /**< \brief (PIO_PCMR) Parallel Capture Mode Half Sampling */
\r
1664 #define PIO_PCMR_FRSTS (0x1u << 11) /**< \brief (PIO_PCMR) Parallel Capture Mode First Sample */
\r
1665 /* -------- PIO_PCIER : (PIO Offset: 0x154) Parallel Capture Interrupt Enable Register -------- */
\r
1666 #define PIO_PCIER_DRDY (0x1u << 0) /**< \brief (PIO_PCIER) Parallel Capture Mode Data Ready Interrupt Enable */
\r
1667 #define PIO_PCIER_OVRE (0x1u << 1) /**< \brief (PIO_PCIER) Parallel Capture Mode Overrun Error Interrupt Enable */
\r
1668 #define PIO_PCIER_ENDRX (0x1u << 2) /**< \brief (PIO_PCIER) End of Reception Transfer Interrupt Enable */
\r
1669 #define PIO_PCIER_RXBUFF (0x1u << 3) /**< \brief (PIO_PCIER) Reception Buffer Full Interrupt Enable */
\r
1670 /* -------- PIO_PCIDR : (PIO Offset: 0x158) Parallel Capture Interrupt Disable Register -------- */
\r
1671 #define PIO_PCIDR_DRDY (0x1u << 0) /**< \brief (PIO_PCIDR) Parallel Capture Mode Data Ready Interrupt Disable */
\r
1672 #define PIO_PCIDR_OVRE (0x1u << 1) /**< \brief (PIO_PCIDR) Parallel Capture Mode Overrun Error Interrupt Disable */
\r
1673 #define PIO_PCIDR_ENDRX (0x1u << 2) /**< \brief (PIO_PCIDR) End of Reception Transfer Interrupt Disable */
\r
1674 #define PIO_PCIDR_RXBUFF (0x1u << 3) /**< \brief (PIO_PCIDR) Reception Buffer Full Interrupt Disable */
\r
1675 /* -------- PIO_PCIMR : (PIO Offset: 0x15C) Parallel Capture Interrupt Mask Register -------- */
\r
1676 #define PIO_PCIMR_DRDY (0x1u << 0) /**< \brief (PIO_PCIMR) Parallel Capture Mode Data Ready Interrupt Mask */
\r
1677 #define PIO_PCIMR_OVRE (0x1u << 1) /**< \brief (PIO_PCIMR) Parallel Capture Mode Overrun Error Interrupt Mask */
\r
1678 #define PIO_PCIMR_ENDRX (0x1u << 2) /**< \brief (PIO_PCIMR) End of Reception Transfer Interrupt Mask */
\r
1679 #define PIO_PCIMR_RXBUFF (0x1u << 3) /**< \brief (PIO_PCIMR) Reception Buffer Full Interrupt Mask */
\r
1680 /* -------- PIO_PCISR : (PIO Offset: 0x160) Parallel Capture Interrupt Status Register -------- */
\r
1681 #define PIO_PCISR_DRDY (0x1u << 0) /**< \brief (PIO_PCISR) Parallel Capture Mode Data Ready */
\r
1682 #define PIO_PCISR_OVRE (0x1u << 1) /**< \brief (PIO_PCISR) Parallel Capture Mode Overrun Error. */
\r
1683 #define PIO_PCISR_ENDRX (0x1u << 2) /**< \brief (PIO_PCISR) End of Reception Transfer. */
\r
1684 #define PIO_PCISR_RXBUFF (0x1u << 3) /**< \brief (PIO_PCISR) Reception Buffer Full */
\r
1685 /* -------- PIO_PCRHR : (PIO Offset: 0x164) Parallel Capture Reception Holding Register -------- */
\r
1686 #define PIO_PCRHR_RDATA_Pos 0
\r
1687 #define PIO_PCRHR_RDATA_Msk (0xffffffffu << PIO_PCRHR_RDATA_Pos) /**< \brief (PIO_PCRHR) Parallel Capture Mode Reception Data. */
\r
1692 #endif /* _SAM_PIO_COMPONENT_ */
\r
projects / freertos / blob